5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
7 * Copyright (C) 2008-2009 MontaVista Software Inc.
8 * Copyright (C) 2008-2009 Texas Instruments Inc
10 * Based on the LCD driver for TI Avalanche processors written by
11 * Ajay Singh and Shalom Hai.
13 * SPDX-License-Identifier: GPL-2.0+
19 #include <linux/list.h>
23 #include <asm/errno.h>
25 #include <asm/hardware.h>
26 #include <asm/arch/cpu.h>
27 #include <asm/arch/da8xx-fb.h>
29 #include "videomodes.h"
31 #if !defined(DA8XX_LCD_CNTL_BASE)
32 #define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE
35 #define DRIVER_NAME "da8xx_lcdc"
37 #define LCD_VERSION_1 1
38 #define LCD_VERSION_2 2
40 #define BIT(x) (1 << (x))
42 /* LCD Status Register */
43 #define LCD_END_OF_FRAME1 BIT(9)
44 #define LCD_END_OF_FRAME0 BIT(8)
45 #define LCD_PL_LOAD_DONE BIT(6)
46 #define LCD_FIFO_UNDERFLOW BIT(5)
47 #define LCD_SYNC_LOST BIT(2)
49 /* LCD DMA Control Register */
50 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
51 #define LCD_DMA_BURST_SIZE_MASK (0x7 << 4)
52 #define LCD_DMA_BURST_1 0x0
53 #define LCD_DMA_BURST_2 0x1
54 #define LCD_DMA_BURST_4 0x2
55 #define LCD_DMA_BURST_8 0x3
56 #define LCD_DMA_BURST_16 0x4
57 #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
58 #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)
59 #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)
60 #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
62 /* LCD Control Register */
63 #define LCD_CLK_DIVISOR(x) ((x) << 8)
64 #define LCD_RASTER_MODE 0x01
66 /* LCD Raster Control Register */
67 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
68 #define PALETTE_AND_DATA 0x00
69 #define PALETTE_ONLY 0x01
70 #define DATA_ONLY 0x02
72 #define LCD_MONO_8BIT_MODE BIT(9)
73 #define LCD_RASTER_ORDER BIT(8)
74 #define LCD_TFT_MODE BIT(7)
75 #define LCD_V1_UNDERFLOW_INT_ENA BIT(6)
76 #define LCD_V2_UNDERFLOW_INT_ENA BIT(5)
77 #define LCD_V1_PL_INT_ENA BIT(4)
78 #define LCD_V2_PL_INT_ENA BIT(6)
79 #define LCD_MONOCHROME_MODE BIT(1)
80 #define LCD_RASTER_ENABLE BIT(0)
81 #define LCD_TFT_ALT_ENABLE BIT(23)
82 #define LCD_STN_565_ENABLE BIT(24)
83 #define LCD_TFT24 BIT(25)
84 #define LCD_TFT24_UNPACKED BIT(26)
85 #define LCD_V2_DMA_CLK_EN BIT(2)
86 #define LCD_V2_LIDD_CLK_EN BIT(1)
87 #define LCD_V2_CORE_CLK_EN BIT(0)
88 #define LCD_V2_LPP_B10 26
89 #define LCD_V2_TFT_24BPP_MODE (1 << 25)
90 #define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
92 /* LCD Raster Timing 2 Register */
93 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
94 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
95 #define LCD_SYNC_CTRL BIT(25)
96 #define LCD_SYNC_EDGE BIT(24)
97 #define LCD_INVERT_PIXEL_CLOCK BIT(22)
98 #define LCD_INVERT_LINE_CLOCK BIT(21)
99 #define LCD_INVERT_FRAME_CLOCK BIT(20)
101 /* Clock reset register */
102 #define LCD_CLK_MAIN_RESET BIT(3)
104 /* Clock registers available only on Version 2 */
106 struct da8xx_lcd_regs {
107 u32 revid; /* 0x00 */
110 u32 lidd_ctrl; /* 0x0c */
111 u32 lidd_cs0_conf; /* 0x10 */
112 u32 lidd_cs0_addr; /* 0x14 */
113 u32 lidd_cs0_data; /* 0x18 */
114 u32 lidd_cs1_conf; /* 0x1c */
115 u32 lidd_cs1_addr; /* 0x20 */
116 u32 lidd_cs1_data; /* 0x24 */
117 u32 raster_ctrl; /* 0x28 */
118 u32 raster_timing_0; /* 0x2c */
119 u32 raster_timing_1; /* 0x30 */
120 u32 raster_timing_2; /* 0x34 */
121 u32 raster_subpanel; /* 0x38 */
122 u32 reserved; /* 0x3c */
123 u32 dma_ctrl; /* 0x40 */
124 u32 dma_frm_buf_base_addr_0; /* 0x44 */
125 u32 dma_frm_buf_ceiling_addr_0; /* 0x48 */
126 u32 dma_frm_buf_base_addr_1; /* 0x4c */
127 u32 dma_frm_buf_ceiling_addr_1; /* 0x50 */
128 u32 rsrvd1; /* 0x54 */
129 u32 raw_stat; /* 0x58 */
130 u32 masked_stat; /* 0x5c */
131 u32 int_ena_set; /* 0x60 */
132 u32 int_ena_clr; /* 0x64 */
133 u32 end_of_int_ind; /* 0x68 */
134 u32 clk_ena; /* 0x6c */
135 u32 clk_reset; /* 0x70 */
136 /* Clock registers available only on Version 2 */
139 #define LCD_NUM_BUFFERS 1
141 #define WSI_TIMEOUT 50
142 #define PALETTE_SIZE 256
143 #define LEFT_MARGIN 64
144 #define RIGHT_MARGIN 64
145 #define UPPER_MARGIN 32
146 #define LOWER_MARGIN 32
147 #define WAIT_FOR_FRAME_DONE true
148 #define NO_WAIT_FOR_FRAME_DONE false
151 static struct da8xx_lcd_regs *da8xx_fb_reg_base;
153 DECLARE_GLOBAL_DATA_PTR;
156 static GraphicDevice gpanel;
157 static const struct da8xx_panel *lcd_panel;
158 static struct fb_info *da8xx_fb_info;
159 static int bits_x_pixel;
160 static unsigned int lcd_revision;
161 static u32 (*lcdc_irq_handler)(void);
162 const struct lcd_ctrl_config *da8xx_lcd_cfg;
164 static inline unsigned int lcdc_read(u32 *addr)
169 static inline void lcdc_write(unsigned int val, u32 *addr)
174 struct da8xx_fb_par {
175 unsigned long p_palette_base;
176 void *v_palette_base;
177 dma_addr_t vram_phys;
178 unsigned long vram_size;
180 unsigned int dma_start;
181 unsigned int dma_end;
182 struct clk *lcdc_clk;
184 unsigned short pseudo_palette[16];
185 unsigned int palette_sz;
186 unsigned int pxl_clk;
192 /* Variable Screen Information */
193 static struct fb_var_screeninfo da8xx_fb_var = {
201 .pixclock = 46666, /* 46us - AUO display */
203 .left_margin = LEFT_MARGIN,
204 .right_margin = RIGHT_MARGIN,
205 .upper_margin = UPPER_MARGIN,
206 .lower_margin = LOWER_MARGIN,
208 .vmode = FB_VMODE_NONINTERLACED
211 static struct fb_fix_screeninfo da8xx_fb_fix = {
212 .id = "DA8xx FB Drv",
213 .type = FB_TYPE_PACKED_PIXELS,
215 .visual = FB_VISUAL_PSEUDOCOLOR,
219 .accel = FB_ACCEL_NONE
222 /* Enable the Raster Engine of the LCD Controller */
223 static inline void lcd_enable_raster(void)
227 /* Put LCDC in reset for several cycles */
228 if (lcd_revision == LCD_VERSION_2)
229 lcdc_write(LCD_CLK_MAIN_RESET,
230 &da8xx_fb_reg_base->clk_reset);
233 /* Bring LCDC out of reset */
234 if (lcd_revision == LCD_VERSION_2)
235 lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
238 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
239 if (!(reg & LCD_RASTER_ENABLE))
240 lcdc_write(reg | LCD_RASTER_ENABLE,
241 &da8xx_fb_reg_base->raster_ctrl);
244 /* Disable the Raster Engine of the LCD Controller */
245 static inline void lcd_disable_raster(bool wait_for_frame_done)
252 if (wait_for_frame_done)
255 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
256 if (reg & LCD_RASTER_ENABLE)
257 lcdc_write(reg & ~LCD_RASTER_ENABLE,
258 &da8xx_fb_reg_base->raster_ctrl);
260 /* Wait for the current frame to complete */
262 if (lcd_revision == LCD_VERSION_1)
263 stat = lcdc_read(&da8xx_fb_reg_base->stat);
265 stat = lcdc_read(&da8xx_fb_reg_base->raw_stat);
268 } while (!(stat & 0x01) && (i++ < loop_cnt));
270 if (lcd_revision == LCD_VERSION_1)
271 lcdc_write(stat, &da8xx_fb_reg_base->stat);
273 lcdc_write(stat, &da8xx_fb_reg_base->raw_stat);
275 if ((loop_cnt != 0) && (i >= loop_cnt)) {
276 printf("LCD Controller timed out\n");
281 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
288 /* init reg to clear PLM (loading mode) fields */
289 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
290 reg_ras &= ~(3 << 20);
292 reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
294 if (load_mode == LOAD_DATA) {
295 start = par->dma_start;
298 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
299 if (lcd_revision == LCD_VERSION_1) {
300 reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
302 lcdc_write(LCD_V2_END_OF_FRAME0_INT_ENA |
303 LCD_V2_END_OF_FRAME1_INT_ENA |
304 LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST,
305 &da8xx_fb_reg_base->int_ena_set);
308 #if (LCD_NUM_BUFFERS == 2)
309 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
310 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
311 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
312 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
313 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
315 reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
316 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
317 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
318 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
319 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
321 } else if (load_mode == LOAD_PALETTE) {
322 start = par->p_palette_base;
323 end = start + par->palette_sz - 1;
325 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
327 if (lcd_revision == LCD_VERSION_1) {
328 reg_ras |= LCD_V1_PL_INT_ENA;
330 lcdc_write(LCD_V2_PL_INT_ENA,
331 &da8xx_fb_reg_base->int_ena_set);
334 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
335 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
338 lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
339 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
342 * The Raster enable bit must be set after all other control fields are
348 /* Configure the Burst Size of DMA */
349 static int lcd_cfg_dma(int burst_size)
353 reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
354 reg &= ~LCD_DMA_BURST_SIZE_MASK;
355 switch (burst_size) {
357 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
360 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
363 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
366 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
369 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
374 lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
379 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
383 /* Set the AC Bias Period and Number of Transisitons per Interrupt */
384 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
385 reg |= LCD_AC_BIAS_FREQUENCY(period) |
386 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
387 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
390 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
395 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
396 reg |= ((back_porch & 0xff) << 24)
397 | ((front_porch & 0xff) << 16)
398 | ((pulse_width & 0x3f) << 10);
399 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
402 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
407 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
408 reg |= ((back_porch & 0xff) << 24)
409 | ((front_porch & 0xff) << 16)
410 | ((pulse_width & 0x3f) << 10);
411 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
414 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
418 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
420 LCD_MONOCHROME_MODE |
424 switch (cfg->p_disp_panel->panel_shade) {
426 reg |= LCD_MONOCHROME_MODE;
427 if (cfg->mono_8bit_mode)
428 reg |= LCD_MONO_8BIT_MODE;
432 if (cfg->tft_alt_mode)
433 reg |= LCD_TFT_ALT_ENABLE;
437 if (cfg->stn_565_mode)
438 reg |= LCD_STN_565_ENABLE;
445 /* enable additional interrupts here */
446 if (lcd_revision == LCD_VERSION_1) {
447 reg |= LCD_V1_UNDERFLOW_INT_ENA;
449 if (bits_x_pixel >= 24)
452 reg |= LCD_TFT24_UNPACKED;
454 lcdc_write(LCD_V2_UNDERFLOW_INT_ENA,
455 &da8xx_fb_reg_base->int_ena_set);
458 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
460 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
463 reg |= LCD_SYNC_CTRL;
465 reg &= ~LCD_SYNC_CTRL;
468 reg |= LCD_SYNC_EDGE;
470 reg &= ~LCD_SYNC_EDGE;
472 if (cfg->invert_line_clock)
473 reg |= LCD_INVERT_LINE_CLOCK;
475 reg &= ~LCD_INVERT_LINE_CLOCK;
477 if (cfg->invert_frm_clock)
478 reg |= LCD_INVERT_FRAME_CLOCK;
480 reg &= ~LCD_INVERT_FRAME_CLOCK;
482 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
487 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
488 u32 bpp, u32 raster_order)
492 /* Set the Panel Width */
493 /* Pixels per line = (PPL + 1)*16 */
494 if (lcd_revision == LCD_VERSION_1) {
496 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
502 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
508 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
510 if (lcd_revision == LCD_VERSION_1) {
511 reg |= ((width >> 4) - 1) << 4;
513 width = (width >> 4) - 1;
514 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
516 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
518 /* Set the Panel Height */
519 /* Set bits 9:0 of Lines Per Pixel */
520 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
521 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
522 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
524 /* Set bit 10 of Lines Per Pixel */
525 if (lcd_revision == LCD_VERSION_2) {
526 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
527 reg |= ((height - 1) & 0x400) << 16;
528 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
531 /* Set the Raster Order of the Frame Buffer */
532 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
534 reg |= LCD_RASTER_ORDER;
537 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
539 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
540 | LCD_V2_TFT_24BPP_UNPACK);
542 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
551 par->palette_sz = 16 * 2;
555 par->palette_sz = 256 * 2;
565 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
566 unsigned blue, unsigned transp,
567 struct fb_info *info)
569 struct da8xx_fb_par *par = info->par;
570 unsigned short *palette = par->v_palette_base;
577 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
580 if (info->var.bits_per_pixel == 8) {
585 pal = (red & 0x0f00);
586 pal |= (green & 0x00f0);
587 pal |= (blue & 0x000f);
589 if (palette[regno] != pal) {
591 palette[regno] = pal;
593 } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
594 red >>= (16 - info->var.red.length);
595 red <<= info->var.red.offset;
597 green >>= (16 - info->var.green.length);
598 green <<= info->var.green.offset;
600 blue >>= (16 - info->var.blue.length);
601 blue <<= info->var.blue.offset;
603 par->pseudo_palette[regno] = red | green | blue;
605 if (palette[0] != 0x4000) {
609 } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
610 ((info->var.bits_per_pixel == 24) && regno < 24)) {
611 red >>= (24 - info->var.red.length);
612 red <<= info->var.red.offset;
614 green >>= (24 - info->var.green.length);
615 green <<= info->var.green.offset;
617 blue >>= (24 - info->var.blue.length);
618 blue <<= info->var.blue.offset;
620 par->pseudo_palette[regno] = red | green | blue;
622 if (palette[0] != 0x4000) {
628 /* Update the palette in the h/w as needed. */
630 lcd_blit(LOAD_PALETTE, par);
635 static void lcd_reset(struct da8xx_fb_par *par)
637 /* Disable the Raster if previously Enabled */
638 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
640 /* DMA has to be disabled */
641 lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
642 lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
644 if (lcd_revision == LCD_VERSION_2) {
645 /* Write 1 to reset */
646 lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
647 lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
651 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
653 unsigned int lcd_clk, div;
655 #ifndef CONFIG_AM33XX
656 /* Get clock from sysclk2 */
657 lcd_clk = clk_get(2);
659 lcd_clk = lcdc_clk_rate();
661 /* calculate divisor so that the resulting clock is rounded down */
662 div = (lcd_clk + par->pxl_clk - 1)/ par->pxl_clk;
668 debug("LCD Clock: %u.%03uMHz Divider: 0x%08x PixClk requested: %u.%03uMHz actual: %u.%03uMHz\n",
669 lcd_clk / 1000000, lcd_clk / 1000 % 1000, div,
670 par->pxl_clk / 1000000, par->pxl_clk / 1000 % 1000,
671 lcd_clk / div / 1000000, lcd_clk / div / 1000 % 1000);
673 /* Configure the LCD clock divisor. */
674 lcdc_write(LCD_CLK_DIVISOR(div) | LCD_RASTER_MODE,
675 &da8xx_fb_reg_base->ctrl);
677 if (lcd_revision == LCD_VERSION_2)
678 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
680 &da8xx_fb_reg_base->clk_ena);
683 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
684 const struct da8xx_panel *panel)
691 /* Calculate the divider */
692 lcd_calc_clk_divider(par);
694 if (panel->invert_pxl_clk)
695 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
696 LCD_INVERT_PIXEL_CLOCK),
697 &da8xx_fb_reg_base->raster_timing_2);
699 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
700 ~LCD_INVERT_PIXEL_CLOCK),
701 &da8xx_fb_reg_base->raster_timing_2);
703 /* Configure the DMA burst size. */
704 ret = lcd_cfg_dma(cfg->dma_burst_sz);
708 /* Configure the AC bias properties. */
709 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
711 /* Configure the vertical and horizontal sync properties. */
712 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
713 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
715 /* Configure for display */
716 ret = lcd_cfg_display(cfg);
720 if ((QVGA != cfg->p_disp_panel->panel_type) &&
721 (WVGA != cfg->p_disp_panel->panel_type))
724 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
725 cfg->bpp >= cfg->p_disp_panel->min_bpp)
728 bpp = cfg->p_disp_panel->max_bpp;
731 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
732 (unsigned int)panel->height, bpp,
738 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
739 (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
744 static void lcdc_dma_start(void)
746 struct da8xx_fb_par *par = da8xx_fb_info->par;
747 lcdc_write(par->dma_start,
748 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
749 lcdc_write(par->dma_end,
750 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
752 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
754 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
757 /* IRQ handler for version 2 of LCDC */
758 static u32 lcdc_irq_handler_rev02(void)
761 struct da8xx_fb_par *par = da8xx_fb_info->par;
762 u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
764 debug("%s: stat=%08x\n", __func__, stat);
766 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
767 debug("LCD_SYNC_LOST\n");
768 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
769 lcdc_write(stat, &da8xx_fb_reg_base->stat);
772 } else if (stat & LCD_PL_LOAD_DONE) {
773 debug("LCD_PL_LOAD_DONE\n");
775 * Must disable raster before changing state of any control bit.
776 * And also must be disabled before clearing the PL loading
777 * interrupt via the following write to the status register. If
778 * this is done after then one gets multiple PL done interrupts.
780 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
782 lcdc_write(stat, &da8xx_fb_reg_base->stat);
784 /* Disable PL completion inerrupt */
785 lcdc_write(LCD_V2_PL_INT_ENA,
786 &da8xx_fb_reg_base->int_ena_clr);
788 /* Setup and start data loading mode */
789 lcd_blit(LOAD_DATA, par);
790 ret = LCD_PL_LOAD_DONE;
791 } else if (stat & (LCD_END_OF_FRAME0 | LCD_END_OF_FRAME1)) {
793 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
795 if (stat & LCD_END_OF_FRAME0) {
796 debug("LCD_END_OF_FRAME0\n");
798 lcdc_write(par->dma_start,
799 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
800 lcdc_write(par->dma_end,
801 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
803 if (stat & LCD_END_OF_FRAME1) {
804 debug("LCD_END_OF_FRAME1\n");
805 lcdc_write(par->dma_start,
806 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
807 lcdc_write(par->dma_end,
808 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
811 ret = (stat & LCD_END_OF_FRAME0) ?
812 LCD_END_OF_FRAME0 : LCD_END_OF_FRAME1;
814 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
818 static u32 lcdc_irq_handler_rev01(void)
820 struct da8xx_fb_par *par = da8xx_fb_info->par;
821 u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
824 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
825 debug("LCD_SYNC_LOST\n");
826 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
827 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
829 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
830 return LCD_SYNC_LOST;
831 } else if (stat & LCD_PL_LOAD_DONE) {
832 debug("LCD_PL_LOAD_DONE\n");
834 * Must disable raster before changing state of any control bit.
835 * And also must be disabled before clearing the PL loading
836 * interrupt via the following write to the status register. If
837 * this is done after then one gets multiple PL done interrupts.
839 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
841 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
843 /* Disable PL completion inerrupt */
844 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
845 reg_ras &= ~LCD_V1_PL_INT_ENA;
846 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
848 /* Setup and start data loading mode */
849 lcd_blit(LOAD_DATA, par);
850 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
851 return LCD_PL_LOAD_DONE;
852 } else if (stat & (LCD_END_OF_FRAME0 | LCD_END_OF_FRAME1)) {
854 lcdc_write(stat, &da8xx_fb_reg_base->stat);
856 if (stat & LCD_END_OF_FRAME0) {
857 debug("LCD_END_OF_FRAME0\n");
859 lcdc_write(par->dma_start,
860 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
861 lcdc_write(par->dma_end,
862 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
865 if (stat & LCD_END_OF_FRAME1) {
866 debug("LCD_END_OF_FRAME1\n");
867 lcdc_write(par->dma_start,
868 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
869 lcdc_write(par->dma_end,
870 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
873 return (stat & LCD_END_OF_FRAME0) ?
874 LCD_END_OF_FRAME0 : LCD_END_OF_FRAME1;
876 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
880 static u32 wait_for_event(u32 event)
886 ret = lcdc_irq_handler();
890 } while (--timeout > 0);
893 printf("%s: event %d not hit\n", __func__, event);
901 void *video_hw_init(void)
903 struct da8xx_fb_par *par;
908 printf("Display not initialized\n");
912 gpanel.winSizeX = lcd_panel->width;
913 gpanel.winSizeY = lcd_panel->height;
914 gpanel.plnSizeX = lcd_panel->width;
915 gpanel.plnSizeY = lcd_panel->height;
917 switch (bits_x_pixel) {
919 gpanel.gdfBytesPP = 4;
920 gpanel.gdfIndex = GDF_32BIT_X888RGB;
923 gpanel.gdfBytesPP = 4;
924 gpanel.gdfIndex = GDF_32BIT_X888RGB;
927 gpanel.gdfBytesPP = 2;
928 gpanel.gdfIndex = GDF_16BIT_565RGB;
931 gpanel.gdfBytesPP = 1;
932 gpanel.gdfIndex = GDF__8BIT_INDEX;
935 da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE;
937 /* Determine LCD IP Version */
939 lcd_revision = lcdc_read(&da8xx_fb_reg_base->revid);
940 switch (lcd_revision & 0xfff00000) {
942 lcd_revision = LCD_VERSION_1;
946 lcd_revision = LCD_VERSION_2;
950 printf("Unknown PID Reg value 0x%08x, defaulting to LCD revision 1\n",
952 lcd_revision = LCD_VERSION_1;
955 debug("Resolution: %dx%d %d\n",
960 size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
961 da8xx_fb_info = malloc(size);
962 debug("da8xx_fb_info at %p\n", da8xx_fb_info);
964 if (!da8xx_fb_info) {
965 printf("Memory allocation failed for fb_info\n");
968 memset(da8xx_fb_info, 0, size);
969 p = (char *)da8xx_fb_info;
970 da8xx_fb_info->par = p + sizeof(struct fb_info);
971 debug("da8xx_par at %p\n", da8xx_fb_info->par);
973 par = da8xx_fb_info->par;
974 par->pxl_clk = lcd_panel->pxl_clk;
976 if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) {
977 printf("lcd_init failed\n");
981 /* allocate frame buffer */
982 par->vram_size = lcd_panel->width * lcd_panel->height *
984 par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
987 par->vram_virt = (void *)gd->fb_base;
989 par->vram_virt = malloc(par->vram_size);
991 par->vram_phys = (dma_addr_t) par->vram_virt;
992 debug("Requesting 0x%lx bytes for framebuffer at 0x%p\n",
993 par->vram_size, par->vram_virt);
994 if (!par->vram_virt) {
995 printf("GLCD: malloc for frame buffer failed\n");
999 gpanel.frameAdrs = (unsigned int)par->vram_virt;
1000 da8xx_fb_info->screen_base = par->vram_virt;
1001 da8xx_fb_fix.smem_start = gpanel.frameAdrs;
1002 da8xx_fb_fix.smem_len = par->vram_size;
1003 da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8;
1004 debug("%s: vram_virt: %p size %ux%u=%lu bpp %u\n", __func__,
1005 par->vram_virt, lcd_panel->width, lcd_panel->height,
1006 par->vram_size, da8xx_lcd_cfg->bpp);
1007 par->dma_start = par->vram_phys;
1008 par->dma_end = par->dma_start + lcd_panel->height *
1009 da8xx_fb_fix.line_length - 1;
1011 /* allocate palette buffer */
1012 par->v_palette_base = malloc(PALETTE_SIZE);
1013 if (!par->v_palette_base) {
1014 printf("GLCD: malloc for palette buffer failed\n");
1015 goto err_release_fb_mem;
1017 memset(par->v_palette_base, 0, PALETTE_SIZE);
1018 par->p_palette_base = (unsigned long)par->v_palette_base;
1019 /* Initialize par */
1020 da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp;
1022 /* Initialize var */
1023 da8xx_fb_var.xres = lcd_panel->width;
1024 da8xx_fb_var.xres_virtual = lcd_panel->width;
1026 da8xx_fb_var.yres = lcd_panel->height;
1027 da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
1029 da8xx_fb_var.grayscale =
1030 da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
1031 da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp;
1033 da8xx_fb_var.hsync_len = lcd_panel->hsw;
1034 da8xx_fb_var.vsync_len = lcd_panel->vsw;
1036 /* Initialize fbinfo */
1037 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1038 da8xx_fb_info->fix = da8xx_fb_fix;
1039 da8xx_fb_info->var = da8xx_fb_var;
1040 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1041 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1042 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1044 /* Clear interrupt */
1045 memset(par->vram_virt, 0, par->vram_size);
1046 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
1047 if (lcd_revision == LCD_VERSION_1)
1048 lcdc_irq_handler = lcdc_irq_handler_rev01;
1050 lcdc_irq_handler = lcdc_irq_handler_rev02;
1052 /* Clear interrupt */
1053 memset(par->vram_virt, 0, par->vram_size);
1054 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
1055 lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
1056 debug("Palette at 0x%08lx size %u\n", par->p_palette_base,
1060 /* Load a default palette */
1061 fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
1063 /* Check that the palette is loaded */
1064 wait_for_event(LCD_PL_LOAD_DONE);
1066 /* Wait until DMA is working */
1067 wait_for_event(LCD_END_OF_FRAME0);
1073 free(par->vram_virt);
1077 free(da8xx_fb_info);
1082 void da8xx_fb_disable(void)
1084 lcd_reset(da8xx_fb_info->par);
1087 void video_set_lut(unsigned int index, /* color number */
1088 unsigned char r, /* red */
1089 unsigned char g, /* green */
1090 unsigned char b /* blue */
1095 void da8xx_video_init(const struct da8xx_panel *panel,
1096 const struct lcd_ctrl_config *lcd_cfg, int bits_pixel)
1099 da8xx_lcd_cfg = lcd_cfg;
1100 bits_x_pixel = bits_pixel;