drivers/video/ipu_disp.c

   1 /*
   2  * Porting to u-boot:
   3  *
   4  * (C) Copyright 2010
   5  * Stefano Babic, DENX Software Engineering, sbabic@denx.de
   6  *
   7  * Linux IPU driver
   8  *
   9  * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /* #define DEBUG */
  31
  32 #include <common.h>
  33 #include <ipu.h>
  34 #include <linux/types.h>
  35 #include <asm/errno.h>
  36 #include <asm/io.h>
  37 #include <asm/arch/imx-regs.h>
  38
  39 #include "ipu_regs.h"
  40
  41 enum csc_type_t {
  42         RGB2YUV = 0,
  43         YUV2RGB,
  44         RGB2RGB,
  45         YUV2YUV,
  46         CSC_NONE,
  47         CSC_NUM
  48 };
  49
  50 struct dp_csc_param_t {
  51         int mode;
  52         void *coeff;
  53 };
  54
  55 #define SYNC_WAVE 0
  56
  57 /* DC display ID assignments */
  58 #define DC_DISP_ID_SYNC(di)     (di)
  59 #define DC_DISP_ID_SERIAL       2
  60 #define DC_DISP_ID_ASYNC        3
  61
  62 static int dmfc_type_setup;
  63 static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;
  64 static int g_di1_tvout;
  65
  66 #if 0
  67 extern struct clk *g_ipu_clk;
  68 extern struct clk *g_di_clk[2];
  69 extern struct clk *g_pixel_clk[2];
  70
  71 extern unsigned char g_ipu_clk_enabled;
  72 extern unsigned char g_dc_di_assignment[];
  73 #endif
  74
  75 void ipu_dmfc_init(int dmfc_type, int first)
  76 {
  77         u32 dmfc_wr_chan, dmfc_dp_chan;
  78
  79         if (first) {
  80                 if (dmfc_type_setup > dmfc_type)
  81                         dmfc_type = dmfc_type_setup;
  82                 else
  83                         dmfc_type_setup = dmfc_type;
  84
  85                 /* disable DMFC-IC channel*/
  86                 __raw_writel(0x2, DMFC_IC_CTRL);
  87         } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
  88                 printf("DMFC high resolution has set, will not change\n");
  89                 return;
  90         } else
  91                 dmfc_type_setup = dmfc_type;
  92
  93         if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
  94                 /* 1 - segment 0~3;
  95                  * 5B - segement 4, 5;
  96                  * 5F - segement 6, 7;
  97                  * 1C, 2C and 6B, 6F unused;
  98                  */
  99                 debug("IPU DMFC DC HIGH RES: 1(0~3), 5B(4,5), 5F(6,7)\n");
 100                 dmfc_wr_chan = 0x00000088;
 101                 dmfc_dp_chan = 0x00009694;
 102                 dmfc_size_28 = 256 * 4;
 103                 dmfc_size_29 = 0;
 104                 dmfc_size_24 = 0;
 105                 dmfc_size_27 = 128 * 4;
 106                 dmfc_size_23 = 128 * 4;
 107         } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
 108                 /* 1 - segment 0, 1;
 109                  * 5B - segement 2~5;
 110                  * 5F - segement 6,7;
 111                  * 1C, 2C and 6B, 6F unused;
 112                  */
 113                 debug("IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)\n");
 114                 dmfc_wr_chan = 0x00000090;
 115                 dmfc_dp_chan = 0x0000968a;
 116                 dmfc_size_28 = 128 * 4;
 117                 dmfc_size_29 = 0;
 118                 dmfc_size_24 = 0;
 119                 dmfc_size_27 = 128 * 4;
 120                 dmfc_size_23 = 256 * 4;
 121         } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
 122                 /* 5B - segement 0~3;
 123                  * 5F - segement 4~7;
 124                  * 1, 1C, 2C and 6B, 6F unused;
 125                  */
 126                 debug("IPU DMFC ONLY-DP HIGH RES: 5B(0~3), 5F(4~7)\n");
 127                 dmfc_wr_chan = 0x00000000;
 128                 dmfc_dp_chan = 0x00008c88;
 129                 dmfc_size_28 = 0;
 130                 dmfc_size_29 = 0;
 131                 dmfc_size_24 = 0;
 132                 dmfc_size_27 = 256 * 4;
 133                 dmfc_size_23 = 256 * 4;
 134         } else {
 135                 /* 1 - segment 0, 1;
 136                  * 5B - segement 4, 5;
 137                  * 5F - segement 6, 7;
 138                  * 1C, 2C and 6B, 6F unused;
 139                  */
 140                 debug("IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
 141                 dmfc_wr_chan = 0x00000090;
 142                 dmfc_dp_chan = 0x00009694;
 143                 dmfc_size_28 = 128 * 4;
 144                 dmfc_size_29 = 0;
 145                 dmfc_size_24 = 0;
 146                 dmfc_size_27 = 128 * 4;
 147                 dmfc_size_23 = 128 * 4;
 148         }
 149         __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN);
 150         __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF);
 151         __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN);
 152         /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
 153         __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF);
 154 }
 155
 156 void ipu_dmfc_set_wait4eot(int dma_chan, int width)
 157 {
 158         u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1);
 159
 160         if (width >= HIGH_RESOLUTION_WIDTH) {
 161                 if (dma_chan == 23)
 162                         ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0);
 163                 else if (dma_chan == 28)
 164                         ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0);
 165         }
 166
 167         if (dma_chan == 23) { /*5B*/
 168                 if (dmfc_size_23 / width > 3)
 169                         dmfc_gen1 |= 1UL << 20;
 170                 else
 171                         dmfc_gen1 &= ~(1UL << 20);
 172         } else if (dma_chan == 24) { /*6B*/
 173                 if (dmfc_size_24 / width > 1)
 174                         dmfc_gen1 |= 1UL << 22;
 175                 else
 176                         dmfc_gen1 &= ~(1UL << 22);
 177         } else if (dma_chan == 27) { /*5F*/
 178                 if (dmfc_size_27 / width > 2)
 179                         dmfc_gen1 |= 1UL << 21;
 180                 else
 181                         dmfc_gen1 &= ~(1UL << 21);
 182         } else if (dma_chan == 28) { /*1*/
 183                 if (dmfc_size_28 / width > 2)
 184                         dmfc_gen1 |= 1UL << 16;
 185                 else
 186                         dmfc_gen1 &= ~(1UL << 16);
 187         } else if (dma_chan == 29) { /*6F*/
 188                 if (dmfc_size_29 / width > 1)
 189                         dmfc_gen1 |= 1UL << 23;
 190                 else
 191                         dmfc_gen1 &= ~(1UL << 23);
 192         }
 193
 194         __raw_writel(dmfc_gen1, DMFC_GENERAL1);
 195 }
 196
 197 static void ipu_di_data_wave_config(int di,
 198                                      int wave_gen,
 199                                      int access_size, int component_size)
 200 {
 201         u32 reg;
 202         reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
 203             (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
 204         __raw_writel(reg, DI_DW_GEN(di, wave_gen));
 205 }
 206
 207 static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set,
 208                                     int up, int down)
 209 {
 210         u32 reg;
 211
 212         reg = __raw_readl(DI_DW_GEN(di, wave_gen));
 213         reg &= ~(0x3 << (di_pin * 2));
 214         reg |= set << (di_pin * 2);
 215         __raw_writel(reg, DI_DW_GEN(di, wave_gen));
 216
 217         __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set));
 218 }
 219
 220 static void ipu_di_sync_config(int di, int wave_gen,
 221                                 int run_count, int run_src,
 222                                 int offset_count, int offset_src,
 223                                 int repeat_count, int cnt_clr_src,
 224                                 int cnt_polarity_gen_en,
 225                                 int cnt_polarity_clr_src,
 226                                 int cnt_polarity_trigger_src,
 227                                 int cnt_up, int cnt_down)
 228 {
 229         u32 reg;
 230
 231         if ((run_count >= 0x1000) || (offset_count >= 0x1000) ||
 232                 (repeat_count >= 0x1000) ||
 233                 (cnt_up >= 0x400) || (cnt_down >= 0x400)) {
 234                 printf("DI%d counters out of range.\n", di);
 235                 return;
 236         }
 237
 238         reg = (run_count << 19) | (++run_src << 16) |
 239             (offset_count << 3) | ++offset_src;
 240         __raw_writel(reg, DI_SW_GEN0(di, wave_gen));
 241         reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
 242             (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
 243         reg |= (cnt_down << 16) | cnt_up;
 244         if (repeat_count == 0) {
 245                 /* Enable auto reload */
 246                 reg |= 0x10000000;
 247         }
 248         __raw_writel(reg, DI_SW_GEN1(di, wave_gen));
 249         reg = __raw_readl(DI_STP_REP(di, wave_gen));
 250         reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
 251         reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
 252         __raw_writel(reg, DI_STP_REP(di, wave_gen));
 253 }
 254
 255 static void ipu_dc_map_config(int map, int byte_num, int offset, int mask)
 256 {
 257         int ptr = map * 3 + byte_num;
 258         u32 reg;
 259
 260         reg = __raw_readl(DC_MAP_CONF_VAL(ptr));
 261         reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
 262         reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
 263         __raw_writel(reg, DC_MAP_CONF_VAL(ptr));
 264
 265         reg = __raw_readl(DC_MAP_CONF_PTR(map));
 266         reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
 267         reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
 268         __raw_writel(reg, DC_MAP_CONF_PTR(map));
 269 }
 270
 271 static void ipu_dc_map_clear(int map)
 272 {
 273         u32 reg = __raw_readl(DC_MAP_CONF_PTR(map));
 274         __raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))),
 275                      DC_MAP_CONF_PTR(map));
 276 }
 277
 278 static void ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map,
 279                                int wave, int glue, int sync)
 280 {
 281         u32 reg;
 282         int stop = 1;
 283
 284         reg = sync;
 285         reg |= (glue << 4);
 286         reg |= (++wave << 11);
 287         reg |= (++map << 15);
 288         reg |= (operand << 20) & 0xFFF00000;
 289         __raw_writel(reg, ipu_dc_tmpl_reg + word * 2);
 290
 291         reg = (operand >> 12);
 292         reg |= opcode << 4;
 293         reg |= (stop << 9);
 294         __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1);
 295 }
 296
 297 static void ipu_dc_link_event(int chan, int event, int addr, int priority)
 298 {
 299         u32 reg;
 300
 301         reg = __raw_readl(DC_RL_CH(chan, event));
 302         reg &= ~(0xFFFF << (16 * (event & 0x1)));
 303         reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
 304         __raw_writel(reg, DC_RL_CH(chan, event));
 305 }
 306
 307 /* Y = R *  1.200 + G *  2.343 + B *  .453 + 0.250;
 308  * U = R * -.672 + G * -1.328 + B *  2.000 + 512.250.;
 309  * V = R *  2.000 + G * -1.672 + B * -.328 + 512.250.;
 310  */
 311 static const int rgb2ycbcr_coeff[5][3] = {
 312         {0x4D, 0x96, 0x1D},
 313         {0x3D5, 0x3AB, 0x80},
 314         {0x80, 0x395, 0x3EB},
 315         {0x0000, 0x0200, 0x0200},       /* B0, B1, B2 */
 316         {0x2, 0x2, 0x2},        /* S0, S1, S2 */
 317 };
 318
 319 /* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
 320  * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
 321  * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);
 322  */
 323 static const int ycbcr2rgb_coeff[5][3] = {
 324         {0x095, 0x000, 0x0CC},
 325         {0x095, 0x3CE, 0x398},
 326         {0x095, 0x0FF, 0x000},
 327         {0x3E42, 0x010A, 0x3DD6},       /*B0,B1,B2 */
 328         {0x1, 0x1, 0x1},        /*S0,S1,S2 */
 329 };
 330
 331 #define mask_a(a) ((u32)(a) & 0x3FF)
 332 #define mask_b(b) ((u32)(b) & 0x3FFF)
 333
 334 /* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
 335 static int rgb_to_yuv(int n, int red, int green, int blue)
 336 {
 337         int c;
 338         c = red * rgb2ycbcr_coeff[n][0];
 339         c += green * rgb2ycbcr_coeff[n][1];
 340         c += blue * rgb2ycbcr_coeff[n][2];
 341         c /= 16;
 342         c += rgb2ycbcr_coeff[3][n] * 4;
 343         c += 8;
 344         c /= 16;
 345         if (c < 0)
 346                 c = 0;
 347         if (c > 255)
 348                 c = 255;
 349         return c;
 350 }
 351
 352 /*
 353  * Row is for BG:       RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
 354  * Column is for FG:    RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
 355  */
 356 static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
 357         {
 358                 {DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff},
 359                 {0, 0},
 360                 {0, 0},
 361                 {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff},
 362                 {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}
 363         },
 364         {
 365                 {0, 0},
 366                 {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff},
 367                 {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff},
 368                 {0, 0},
 369                 {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}
 370         },
 371         {
 372                 {0, 0},
 373                 {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
 374                 {0, 0},
 375                 {0, 0},
 376                 {0, 0}
 377         },
 378         {
 379                 {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
 380                 {0, 0},
 381                 {0, 0},
 382                 {0, 0},
 383                 {0, 0}
 384         },
 385         {
 386                 {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
 387                 {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
 388                 {0, 0},
 389                 {0, 0},
 390                 {0, 0}
 391         }
 392 };
 393
 394 static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE;
 395 static int color_key_4rgb = 1;
 396
 397 void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
 398                         unsigned char srm_mode_update)
 399 {
 400         u32 reg;
 401         const int (*coeff)[5][3];
 402
 403         if (dp_csc_param.mode >= 0) {
 404                 reg = __raw_readl(DP_COM_CONF());
 405                 reg &= ~DP_COM_CONF_CSC_DEF_MASK;
 406                 reg |= dp_csc_param.mode;
 407                 __raw_writel(reg, DP_COM_CONF());
 408         }
 409
 410         coeff = dp_csc_param.coeff;
 411
 412         if (coeff) {
 413                 __raw_writel(mask_a((*coeff)[0][0]) |
 414                                 (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0());
 415                 __raw_writel(mask_a((*coeff)[0][2]) |
 416                                 (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1());
 417                 __raw_writel(mask_a((*coeff)[1][1]) |
 418                                 (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2());
 419                 __raw_writel(mask_a((*coeff)[2][0]) |
 420                                 (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3());
 421                 __raw_writel(mask_a((*coeff)[2][2]) |
 422                                 (mask_b((*coeff)[3][0]) << 16) |
 423                                 ((*coeff)[4][0] << 30), DP_CSC_0());
 424                 __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
 425                                 (mask_b((*coeff)[3][2]) << 16) |
 426                                 ((*coeff)[4][2] << 30), DP_CSC_1());
 427         }
 428
 429         if (srm_mode_update) {
 430                 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
 431                 __raw_writel(reg, IPU_SRM_PRI2);
 432         }
 433 }
 434
 435 int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
 436                  uint32_t out_pixel_fmt)
 437 {
 438         int in_fmt, out_fmt;
 439         int dp;
 440         int partial = 0;
 441         uint32_t reg;
 442
 443         if (channel == MEM_FG_SYNC) {
 444                 dp = DP_SYNC;
 445                 partial = 1;
 446         } else if (channel == MEM_BG_SYNC) {
 447                 dp = DP_SYNC;
 448                 partial = 0;
 449         } else if (channel == MEM_BG_ASYNC0) {
 450                 dp = DP_ASYNC0;
 451                 partial = 0;
 452         } else {
 453                 return -EINVAL;
 454         }
 455
 456         in_fmt = format_to_colorspace(in_pixel_fmt);
 457         out_fmt = format_to_colorspace(out_pixel_fmt);
 458
 459         if (partial) {
 460                 if (in_fmt == RGB) {
 461                         if (out_fmt == RGB)
 462                                 fg_csc_type = RGB2RGB;
 463                         else
 464                                 fg_csc_type = RGB2YUV;
 465                 } else {
 466                         if (out_fmt == RGB)
 467                                 fg_csc_type = YUV2RGB;
 468                         else
 469                                 fg_csc_type = YUV2YUV;
 470                 }
 471         } else {
 472                 if (in_fmt == RGB) {
 473                         if (out_fmt == RGB)
 474                                 bg_csc_type = RGB2RGB;
 475                         else
 476                                 bg_csc_type = RGB2YUV;
 477                 } else {
 478                         if (out_fmt == RGB)
 479                                 bg_csc_type = YUV2RGB;
 480                         else
 481                                 bg_csc_type = YUV2YUV;
 482                 }
 483         }
 484
 485         /* Transform color key from rgb to yuv if CSC is enabled */
 486         reg = __raw_readl(DP_COM_CONF());
 487         if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
 488                 (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
 489                 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
 490                 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
 491                 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {
 492                 int red, green, blue;
 493                 int y, u, v;
 494                 uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) &
 495                         0xFFFFFFL;
 496
 497                 debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n",
 498                         color_key);
 499
 500                 red = (color_key >> 16) & 0xFF;
 501                 green = (color_key >> 8) & 0xFF;
 502                 blue = color_key & 0xFF;
 503
 504                 y = rgb_to_yuv(0, red, green, blue);
 505                 u = rgb_to_yuv(1, red, green, blue);
 506                 v = rgb_to_yuv(2, red, green, blue);
 507                 color_key = (y << 16) | (u << 8) | v;
 508
 509                 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
 510                 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
 511                 color_key_4rgb = 0;
 512
 513                 debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n",
 514                         color_key);
 515         }
 516
 517         ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 1);
 518
 519         return 0;
 520 }
 521
 522 void ipu_dp_uninit(ipu_channel_t channel)
 523 {
 524         int dp;
 525         int partial = 0;
 526
 527         if (channel == MEM_FG_SYNC) {
 528                 dp = DP_SYNC;
 529                 partial = 1;
 530         } else if (channel == MEM_BG_SYNC) {
 531                 dp = DP_SYNC;
 532                 partial = 0;
 533         } else if (channel == MEM_BG_ASYNC0) {
 534                 dp = DP_ASYNC0;
 535                 partial = 0;
 536         } else {
 537                 return;
 538         }
 539
 540         if (partial)
 541                 fg_csc_type = CSC_NONE;
 542         else
 543                 bg_csc_type = CSC_NONE;
 544
 545         ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 0);
 546 }
 547
 548 void ipu_dc_init(int dc_chan, int di, unsigned char interlaced)
 549 {
 550         u32 reg = 0;
 551
 552         if ((dc_chan == 1) || (dc_chan == 5)) {
 553                 if (interlaced) {
 554                         ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3);
 555                         ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2);
 556                         ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1);
 557                 } else {
 558                         if (di) {
 559                                 ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3);
 560                                 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2);
 561                                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
 562                                         4, 1);
 563                         } else {
 564                                 ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3);
 565                                 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2);
 566                                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
 567                                         7, 1);
 568                         }
 569                 }
 570                 ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
 571                 ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
 572                 ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
 573                 ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
 574                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
 575                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
 576
 577                 reg = 0x2;
 578                 reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
 579                 reg |= di << 2;
 580                 if (interlaced)
 581                         reg |= DC_WR_CH_CONF_FIELD_MODE;
 582         } else if ((dc_chan == 8) || (dc_chan == 9)) {
 583                 /* async channels */
 584                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
 585                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
 586
 587                 reg = 0x3;
 588                 reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
 589         }
 590         __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
 591
 592         __raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan));
 593
 594         __raw_writel(0x00000084, DC_GEN);
 595 }
 596
 597 void ipu_dc_uninit(int dc_chan)
 598 {
 599         if ((dc_chan == 1) || (dc_chan == 5)) {
 600                 ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0);
 601                 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0);
 602                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0);
 603                 ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
 604                 ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
 605                 ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
 606                 ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
 607                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
 608                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
 609         } else if ((dc_chan == 8) || (dc_chan == 9)) {
 610                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
 611                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
 612                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
 613                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
 614                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
 615                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
 616                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
 617                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
 618                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
 619                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
 620                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
 621                 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
 622         }
 623 }
 624
 625 int ipu_chan_is_interlaced(ipu_channel_t channel)
 626 {
 627         if (channel == MEM_DC_SYNC)
 628                 return !!(__raw_readl(DC_WR_CH_CONF_1) &
 629                           DC_WR_CH_CONF_FIELD_MODE);
 630         else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
 631                 return !!(__raw_readl(DC_WR_CH_CONF_5) &
 632                           DC_WR_CH_CONF_FIELD_MODE);
 633         return 0;
 634 }
 635
 636 void ipu_dp_dc_enable(ipu_channel_t channel)
 637 {
 638         int di;
 639         uint32_t reg;
 640         uint32_t dc_chan;
 641
 642         if (channel == MEM_FG_SYNC)
 643                 dc_chan = 5;
 644         if (channel == MEM_DC_SYNC)
 645                 dc_chan = 1;
 646         else if (channel == MEM_BG_SYNC)
 647                 dc_chan = 5;
 648         else
 649                 return;
 650
 651         if (channel == MEM_FG_SYNC) {
 652                 /* Enable FG channel */
 653                 reg = __raw_readl(DP_COM_CONF());
 654                 __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF());
 655
 656                 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
 657                 __raw_writel(reg, IPU_SRM_PRI2);
 658                 return;
 659         }
 660
 661         di = g_dc_di_assignment[dc_chan];
 662
 663         /* Make sure other DC sync channel is not assigned same DI */
 664         reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan));
 665         if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
 666                 reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
 667                 reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
 668                 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
 669         }
 670
 671         reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
 672         reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
 673         __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
 674
 675         clk_enable(g_pixel_clk[di]);
 676 }
 677
 678 static unsigned char dc_swap;
 679
 680 void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)
 681 {
 682         uint32_t reg;
 683         uint32_t csc;
 684         uint32_t dc_chan = 0;
 685         int timeout = 50;
 686
 687         dc_swap = swap;
 688
 689         if (channel == MEM_DC_SYNC) {
 690                 dc_chan = 1;
 691         } else if (channel == MEM_BG_SYNC) {
 692                 dc_chan = 5;
 693         } else if (channel == MEM_FG_SYNC) {
 694                 /* Disable FG channel */
 695                 dc_chan = 5;
 696
 697                 reg = __raw_readl(DP_COM_CONF());
 698                 csc = reg & DP_COM_CONF_CSC_DEF_MASK;
 699                 if (csc == DP_COM_CONF_CSC_DEF_FG)
 700                         reg &= ~DP_COM_CONF_CSC_DEF_MASK;
 701
 702                 reg &= ~DP_COM_CONF_FG_EN;
 703                 __raw_writel(reg, DP_COM_CONF());
 704
 705                 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
 706                 __raw_writel(reg, IPU_SRM_PRI2);
 707
 708                 timeout = 50;
 709
 710                 /*
 711                  * Wait for DC triple buffer to empty,
 712                  * this check is useful for tv overlay.
 713                  */
 714                 if (g_dc_di_assignment[dc_chan] == 0)
 715                         while ((__raw_readl(DC_STAT) & 0x00000002)
 716                                != 0x00000002) {
 717                                 udelay(2000);
 718                                 timeout -= 2;
 719                                 if (timeout <= 0)
 720                                         break;
 721                         }
 722                 else if (g_dc_di_assignment[dc_chan] == 1)
 723                         while ((__raw_readl(DC_STAT) & 0x00000020)
 724                                != 0x00000020) {
 725                                 udelay(2000);
 726                                 timeout -= 2;
 727                                 if (timeout <= 0)
 728                                         break;
 729                         }
 730                 return;
 731         } else {
 732                 return;
 733         }
 734
 735         if (dc_swap) {
 736                 /* Swap DC channel 1 and 5 settings, and disable old dc chan */
 737                 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
 738                 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
 739                 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 740                 reg ^= DC_WR_CH_CONF_PROG_DI_ID;
 741                 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
 742         } else {
 743                 timeout = 50;
 744
 745                 /* Wait for DC triple buffer to empty */
 746                 if (g_dc_di_assignment[dc_chan] == 0)
 747                         while ((__raw_readl(DC_STAT) & 0x00000002)
 748                                 != 0x00000002) {
 749                                 udelay(2000);
 750                                 timeout -= 2;
 751                                 if (timeout <= 0)
 752                                         break;
 753                         }
 754                 else if (g_dc_di_assignment[dc_chan] == 1)
 755                         while ((__raw_readl(DC_STAT) & 0x00000020)
 756                                 != 0x00000020) {
 757                                 udelay(2000);
 758                                 timeout -= 2;
 759                                 if (timeout <= 0)
 760                                         break;
 761                         }
 762
 763                 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
 764                 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 765                 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
 766
 767                 reg = __raw_readl(IPU_DISP_GEN);
 768                 if (g_dc_di_assignment[dc_chan])
 769                         reg &= ~DI1_COUNTER_RELEASE;
 770                 else
 771                         reg &= ~DI0_COUNTER_RELEASE;
 772                 __raw_writel(reg, IPU_DISP_GEN);
 773
 774                 /* Clock is already off because it must be done quickly, but
 775                    we need to fix the ref count */
 776                 clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]);
 777         }
 778 }
 779
 780 void ipu_init_dc_mappings(void)
 781 {
 782         /* IPU_PIX_FMT_RGB24 */
 783         ipu_dc_map_clear(0);
 784         ipu_dc_map_config(0, 0, 7, 0xFF);
 785         ipu_dc_map_config(0, 1, 15, 0xFF);
 786         ipu_dc_map_config(0, 2, 23, 0xFF);
 787
 788         /* IPU_PIX_FMT_RGB666 */
 789         ipu_dc_map_clear(1);
 790         ipu_dc_map_config(1, 0, 5, 0xFC);
 791         ipu_dc_map_config(1, 1, 11, 0xFC);
 792         ipu_dc_map_config(1, 2, 17, 0xFC);
 793
 794         /* IPU_PIX_FMT_YUV444 */
 795         ipu_dc_map_clear(2);
 796         ipu_dc_map_config(2, 0, 15, 0xFF);
 797         ipu_dc_map_config(2, 1, 23, 0xFF);
 798         ipu_dc_map_config(2, 2, 7, 0xFF);
 799
 800         /* IPU_PIX_FMT_RGB565 */
 801         ipu_dc_map_clear(3);
 802         ipu_dc_map_config(3, 0, 4, 0xF8);
 803         ipu_dc_map_config(3, 1, 10, 0xFC);
 804         ipu_dc_map_config(3, 2, 15, 0xF8);
 805
 806         /* IPU_PIX_FMT_LVDS666 */
 807         ipu_dc_map_clear(4);
 808         ipu_dc_map_config(4, 0, 5, 0xFC);
 809         ipu_dc_map_config(4, 1, 11, 0xFC);
 810         ipu_dc_map_config(4, 2, 17, 0xFC);
 811 }
 812
 813 int ipu_pixfmt_to_map(uint32_t fmt)
 814 {
 815         switch (fmt) {
 816         case IPU_PIX_FMT_GENERIC:
 817         case IPU_PIX_FMT_RGB24:
 818         case IPU_PIX_FMT_LVDS888:
 819                 return 0;
 820         case IPU_PIX_FMT_RGB666:
 821                 return 1;
 822         case IPU_PIX_FMT_YUV444:
 823                 return 2;
 824         case IPU_PIX_FMT_RGB565:
 825                 return 3;
 826         case IPU_PIX_FMT_LVDS666:
 827                 return 4;
 828         }
 829
 830         return -1;
 831 }
 832
 833 /*
 834  * This function is called to adapt synchronous LCD panel to IPU restriction.
 835  */
 836 void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk,
 837                                       uint16_t width, uint16_t height,
 838                                       uint16_t h_start_width,
 839                                       uint16_t h_end_width,
 840                                       uint16_t v_start_width,
 841                                       uint16_t *v_end_width)
 842 {
 843         if (*v_end_width < 2) {
 844                 uint16_t total_width = width + h_start_width + h_end_width;
 845                 uint16_t total_height_old = height + v_start_width +
 846                         (*v_end_width);
 847                 uint16_t total_height_new = height + v_start_width + 2;
 848                 *v_end_width = 2;
 849                 *pixel_clk = (*pixel_clk) * total_width * total_height_new /
 850                         (total_width * total_height_old);
 851                 printf("WARNING: adapt panel end blank lines\n");
 852         }
 853 }
 854
 855 /*
 856  * This function is called to initialize a synchronous LCD panel.
 857  *
 858  * @param       disp            The DI the panel is attached to.
 859  *
 860  * @param       pixel_clk       Desired pixel clock frequency in Hz.
 861  *
 862  * @param       pixel_fmt       Input parameter for pixel format of buffer.
 863  *                              Pixel format is a FOURCC ASCII code.
 864  *
 865  * @param       width           The width of panel in pixels.
 866  *
 867  * @param       height          The height of panel in pixels.
 868  *
 869  * @param       hStartWidth     The number of pixel clocks between the HSYNC
 870  *                              signal pulse and the start of valid data.
 871  *
 872  * @param       hSyncWidth      The width of the HSYNC signal in units of pixel
 873  *                              clocks.
 874  *
 875  * @param       hEndWidth       The number of pixel clocks between the end of
 876  *                              valid data and the HSYNC signal for next line.
 877  *
 878  * @param       vStartWidth     The number of lines between the VSYNC
 879  *                              signal pulse and the start of valid data.
 880  *
 881  * @param       vSyncWidth      The width of the VSYNC signal in units of lines
 882  *
 883  * @param       vEndWidth       The number of lines between the end of valid
 884  *                              data and the VSYNC signal for next frame.
 885  *
 886  * @param       sig             Bitfield of signal polarities for LCD interface.
 887  *
 888  * @return      This function returns 0 on success or negative error code on
 889  *              fail.
 890  */
 891
 892 int ipu_init_sync_panel(int disp, uint32_t pixel_clk,
 893                         uint16_t width, uint16_t height,
 894                         uint32_t pixel_fmt,
 895                         uint16_t h_start_width, uint16_t h_sync_width,
 896                         uint16_t h_end_width, uint16_t v_start_width,
 897                         uint16_t v_sync_width, uint16_t v_end_width,
 898                         uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
 899 {
 900         uint32_t reg;
 901         uint32_t di_gen, vsync_cnt;
 902         uint32_t div, rounded_pixel_clk;
 903         uint32_t h_total, v_total;
 904         int map;
 905         struct clk *di_parent;
 906
 907         debug("panel size = %d x %d\n", width, height);
 908
 909         if ((v_sync_width == 0) || (h_sync_width == 0))
 910                 return EINVAL;
 911
 912         adapt_panel_to_ipu_restricitions(&pixel_clk, width, height,
 913                                          h_start_width, h_end_width,
 914                                          v_start_width, &v_end_width);
 915         h_total = width + h_sync_width + h_start_width + h_end_width;
 916         v_total = height + v_sync_width + v_start_width + v_end_width;
 917
 918         /* Init clocking */
 919         debug("pixel clk = %d\n", pixel_clk);
 920
 921         if (sig.ext_clk) {
 922                 if (!(g_di1_tvout && (disp == 1))) { /* don't round div for tvout */
 923                         /*
 924                          * Set the  PLL to be an even multiple
 925                          * of the pixel clock.
 926                          */
 927                         if ((clk_get_usecount(g_pixel_clk[0]) == 0) &&
 928                                 (clk_get_usecount(g_pixel_clk[1]) == 0)) {
 929                                 di_parent = clk_get_parent(g_di_clk[disp]);
 930                                 rounded_pixel_clk =
 931                                         clk_round_rate(g_pixel_clk[disp],
 932                                                 pixel_clk);
 933                                 if (di_parent != NULL) {
 934                                         div  = clk_get_rate(di_parent) /
 935                                                 rounded_pixel_clk;
 936                                         if (div % 2)
 937                                                 div++;
 938                                         if (clk_get_rate(di_parent) != div *
 939                                                 rounded_pixel_clk)
 940                                                 clk_set_rate(di_parent,
 941                                                         div * rounded_pixel_clk);
 942                                         udelay(10000);
 943                                         clk_set_rate(g_di_clk[disp],
 944                                                 2 * rounded_pixel_clk);
 945                                         udelay(10000);
 946                                 }
 947                         }
 948                 }
 949                 clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]);
 950         } else {
 951                 if (clk_get_usecount(g_pixel_clk[disp]) != 0)
 952                         clk_set_parent(g_pixel_clk[disp], g_ipu_clk);
 953         }
 954         rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk);
 955         clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
 956         udelay(5000);
 957         /* Get integer portion of divider */
 958         div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
 959                 rounded_pixel_clk;
 960
 961         /* Enable for a divide by 2 clock change. */
 962         reg = __raw_readl(IPU_PM);
 963         reg &= ~(0x7f << 7);
 964         reg |= 0x20 << 7;
 965         reg &= ~(0x7f << 23);
 966         reg |= 0x20 << 23;
 967         __raw_writel(reg, IPU_PM);
 968
 969         di_gen = 0;
 970
 971         if (pixel_fmt != IPU_PIX_FMT_LVDS666 &&
 972                         pixel_fmt != IPU_PIX_FMT_LVDS888) {
 973                 clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
 974                 udelay(5000);
 975                 /* Get integer portion of divider */
 976                 div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
 977                         rounded_pixel_clk;
 978                 ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1);
 979         } else {
 980                 clk_set_rate(g_pixel_clk[disp], clk_get_rate(g_ipu_clk));
 981                 div = 1;
 982                 ipu_di_data_wave_config(disp, SYNC_WAVE, 0, 0);
 983                 di_gen |= (6 << 24);
 984                 di_gen |= DI_GEN_DI_CLK_EXT;
 985         }
 986         ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
 987
 988         map = ipu_pixfmt_to_map(pixel_fmt);
 989         if (map < 0) {
 990                 debug("IPU_DISP: No MAP\n");
 991                 return -EINVAL;
 992         }
 993
 994         if (sig.interlaced) {
 995                 /* Setup internal HSYNC waveform */
 996                 ipu_di_sync_config(
 997                                 disp,           /* display */
 998                                 1,              /* counter */
 999                                 h_total / 2 - 1,/* run count */
1000                                 DI_SYNC_CLK,    /* run_resolution */
1001                                 0,              /* offset */
1002                                 DI_SYNC_NONE,   /* offset resolution */
1003                                 0,              /* repeat count */
1004                                 DI_SYNC_NONE,   /* CNT_CLR_SEL */
1005                                 0,              /* CNT_POLARITY_GEN_EN */
1006                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1007                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1008                                 0,              /* COUNT UP */
1009                                 0               /* COUNT DOWN */
1010                                 );
1011
1012                 /* Field 1 VSYNC waveform */
1013                 ipu_di_sync_config(
1014                                 disp,           /* display */
1015                                 2,              /* counter */
1016                                 h_total - 1,    /* run count */
1017                                 DI_SYNC_CLK,    /* run_resolution */
1018                                 0,              /* offset */
1019                                 DI_SYNC_NONE,   /* offset resolution */
1020                                 0,              /* repeat count */
1021                                 DI_SYNC_NONE,   /* CNT_CLR_SEL */
1022                                 0,              /* CNT_POLARITY_GEN_EN */
1023                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1024                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1025                                 0,              /* COUNT UP */
1026                                 4               /* COUNT DOWN */
1027                                 );
1028
1029                 /* Setup internal HSYNC waveform */
1030                 ipu_di_sync_config(
1031                                 disp,           /* display */
1032                                 3,              /* counter */
1033                                 v_total * 2 - 1,/* run count */
1034                                 DI_SYNC_INT_HSYNC,      /* run_resolution */
1035                                 1,              /* offset */
1036                                 DI_SYNC_INT_HSYNC,      /* offset resolution */
1037                                 0,              /* repeat count */
1038                                 DI_SYNC_NONE,   /* CNT_CLR_SEL */
1039                                 0,              /* CNT_POLARITY_GEN_EN */
1040                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1041                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1042                                 0,              /* COUNT UP */
1043                                 4               /* COUNT DOWN */
1044                                 );
1045
1046                 /* Active Field ? */
1047                 ipu_di_sync_config(
1048                                 disp,           /* display */
1049                                 4,              /* counter */
1050                                 v_total / 2 - 1,/* run count */
1051                                 DI_SYNC_HSYNC,  /* run_resolution */
1052                                 v_start_width,  /*  offset */
1053                                 DI_SYNC_HSYNC,  /* offset resolution */
1054                                 2,              /* repeat count */
1055                                 DI_SYNC_VSYNC,  /* CNT_CLR_SEL */
1056                                 0,              /* CNT_POLARITY_GEN_EN */
1057                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1058                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1059                                 0,              /* COUNT UP */
1060                                 0               /* COUNT DOWN */
1061                                 );
1062
1063                 /* Active Line */
1064                 ipu_di_sync_config(
1065                                 disp,           /* display */
1066                                 5,              /* counter */
1067                                 0,              /* run count */
1068                                 DI_SYNC_HSYNC,  /* run_resolution */
1069                                 0,              /*  offset */
1070                                 DI_SYNC_NONE,   /* offset resolution */
1071                                 height / 2,     /* repeat count */
1072                                 4,              /* CNT_CLR_SEL */
1073                                 0,              /* CNT_POLARITY_GEN_EN */
1074                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1075                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1076                                 0,              /* COUNT UP */
1077                                 0               /* COUNT DOWN */
1078                                 );
1079
1080                 /* Field 0 VSYNC waveform */
1081                 ipu_di_sync_config(
1082                                 disp,           /* display */
1083                                 6,              /* counter */
1084                                 v_total - 1,    /* run count */
1085                                 DI_SYNC_HSYNC,  /* run_resolution */
1086                                 0,              /* offset */
1087                                 DI_SYNC_NONE,   /* offset resolution */
1088                                 0,              /* repeat count */
1089                                 DI_SYNC_NONE,   /* CNT_CLR_SEL  */
1090                                 0,              /* CNT_POLARITY_GEN_EN */
1091                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1092                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1093                                 0,              /* COUNT UP */
1094                                 0               /* COUNT DOWN */
1095                                 );
1096
1097                 /* DC VSYNC waveform */
1098                 vsync_cnt = 7;
1099                 ipu_di_sync_config(
1100                                 disp,           /* display */
1101                                 7,              /* counter */
1102                                 v_total / 2 - 1,/* run count */
1103                                 DI_SYNC_HSYNC,  /* run_resolution  */
1104                                 9,              /* offset  */
1105                                 DI_SYNC_HSYNC,  /* offset resolution */
1106                                 2,              /* repeat count */
1107                                 DI_SYNC_VSYNC,  /* CNT_CLR_SEL */
1108                                 0,              /* CNT_POLARITY_GEN_EN */
1109                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1110                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1111                                 0,              /* COUNT UP */
1112                                 0               /* COUNT DOWN */
1113                                 );
1114
1115                 /* active pixel waveform */
1116                 ipu_di_sync_config(
1117                                 disp,           /* display */
1118                                 8,              /* counter */
1119                                 0,              /* run count  */
1120                                 DI_SYNC_CLK,    /* run_resolution */
1121                                 h_start_width,  /* offset  */
1122                                 DI_SYNC_CLK,    /* offset resolution */
1123                                 width,          /* repeat count  */
1124                                 5,              /* CNT_CLR_SEL  */
1125                                 0,              /* CNT_POLARITY_GEN_EN  */
1126                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1127                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL  */
1128                                 0,              /* COUNT UP  */
1129                                 0               /* COUNT DOWN */
1130                                 );
1131
1132                 ipu_di_sync_config(
1133                                 disp,           /* display */
1134                                 9,              /* counter */
1135                                 v_total - 1,    /* run count */
1136                                 DI_SYNC_INT_HSYNC,/* run_resolution */
1137                                 v_total / 2,    /* offset  */
1138                                 DI_SYNC_INT_HSYNC,/* offset resolution  */
1139                                 0,              /* repeat count */
1140                                 DI_SYNC_HSYNC,  /* CNT_CLR_SEL */
1141                                 0,              /* CNT_POLARITY_GEN_EN  */
1142                                 DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL  */
1143                                 DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1144                                 0,              /* COUNT UP */
1145                                 4               /* COUNT DOWN */
1146                                 );
1147
1148                 /* set gentime select and tag sel */
1149                 reg = __raw_readl(DI_SW_GEN1(disp, 9));
1150                 reg &= 0x1FFFFFFF;
1151                 reg |= ((3 - 1) << 29) | 0x00008000;
1152                 __raw_writel(reg, DI_SW_GEN1(disp, 9));
1153
1154                 __raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp));
1155
1156                 /* set y_sel = 1 */
1157                 di_gen |= 0x10000000;
1158                 di_gen |= DI_GEN_POLARITY_5;
1159                 di_gen |= DI_GEN_POLARITY_8;
1160         } else {
1161                 /* Setup internal HSYNC waveform */
1162                 ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK,
1163                                 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
1164                                 0, DI_SYNC_NONE,
1165                                 DI_SYNC_NONE, 0, 0);
1166
1167                 /* Setup external (delayed) HSYNC waveform */
1168                 ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1,
1169                                 DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
1170                                 0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
1171                                 DI_SYNC_CLK, 0, h_sync_width * 2);
1172                 /* Setup VSYNC waveform */
1173                 vsync_cnt = DI_SYNC_VSYNC;
1174                 ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1,
1175                                 DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
1176                                 DI_SYNC_NONE, 1, DI_SYNC_NONE,
1177                                 DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
1178                 __raw_writel(v_total - 1, DI_SCR_CONF(disp));
1179
1180                 /* Setup active data waveform to sync with DC */
1181                 ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC,
1182                                 v_sync_width + v_start_width, DI_SYNC_HSYNC,
1183                                 height,
1184                                 DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
1185                                 DI_SYNC_NONE, 0, 0);
1186                 ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK,
1187                                 h_sync_width + h_start_width, DI_SYNC_CLK,
1188                                 width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
1189                                 0);
1190
1191                 /* reset all unused counters */
1192                 __raw_writel(0, DI_SW_GEN0(disp, 6));
1193                 __raw_writel(0, DI_SW_GEN1(disp, 6));
1194                 __raw_writel(0, DI_SW_GEN0(disp, 7));
1195                 __raw_writel(0, DI_SW_GEN1(disp, 7));
1196                 __raw_writel(0, DI_SW_GEN0(disp, 8));
1197                 __raw_writel(0, DI_SW_GEN1(disp, 8));
1198                 __raw_writel(0, DI_SW_GEN0(disp, 9));
1199                 __raw_writel(0, DI_SW_GEN1(disp, 9));
1200
1201                 reg = __raw_readl(DI_STP_REP(disp, 6));
1202                 reg &= 0x0000FFFF;
1203                 __raw_writel(reg, DI_STP_REP(disp, 6));
1204                 __raw_writel(0, DI_STP_REP(disp, 7));
1205                 __raw_writel(0, DI_STP_REP(disp, 9));
1206
1207                 h_total = ((width + h_start_width + h_sync_width) / 2) - 2;
1208                 ipu_di_sync_config(disp, 6, 1, 0, 2, DI_SYNC_CLK, h_total,
1209                                 DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE,
1210                                 DI_SYNC_NONE, 0, 0);
1211
1212                 /* Init template microcode */
1213                 if (disp) {
1214                         ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
1215                         ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
1216                         ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
1217                 } else {
1218                         ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
1219                         ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
1220                         ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
1221                 }
1222
1223                 if (sig.Hsync_pol)
1224                         di_gen |= DI_GEN_POLARITY_2;
1225                 if (sig.Vsync_pol)
1226                         di_gen |= DI_GEN_POLARITY_3;
1227
1228                 if (sig.clk_pol)
1229                         di_gen |= DI_GEN_POL_CLK;
1230
1231                 /* Set the clock to stop at counter 6. */
1232                 di_gen |= 0x6000000;
1233         }
1234
1235         __raw_writel(di_gen, DI_GENERAL(disp));
1236
1237         if (sig.interlaced)
1238                 __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
1239                                 0x00000002, DI_SYNC_AS_GEN(disp));
1240         else
1241                 __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET),
1242                                 DI_SYNC_AS_GEN(disp));
1243
1244         reg = __raw_readl(DI_POL(disp));
1245         reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
1246         if (sig.enable_pol)
1247                 reg |= DI_POL_DRDY_POLARITY_15;
1248         if (sig.data_pol)
1249                 reg |= DI_POL_DRDY_DATA_POLARITY;
1250         __raw_writel(reg, DI_POL(disp));
1251
1252         __raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
1253
1254         return 0;
1255 }
1256
1257 /*
1258  * This function sets the foreground and background plane global alpha blending
1259  * modes. This function also sets the DP graphic plane according to the
1260  * parameter of IPUv3 DP channel.
1261  *
1262  * @param       channel         IPUv3 DP channel
1263  *
1264  * @param       enable          Boolean to enable or disable global alpha
1265  *                              blending. If disabled, local blending is used.
1266  *
1267  * @param       alpha           Global alpha value.
1268  *
1269  * @return      Returns 0 on success or negative error code on fail
1270  */
1271 int ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
1272                                   uint8_t alpha)
1273 {
1274         int ret;
1275         uint32_t reg;
1276
1277         unsigned char bg_chan;
1278
1279         if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
1280                 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
1281                 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
1282                 return -EINVAL;
1283
1284         if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
1285             channel == MEM_BG_ASYNC1)
1286                 bg_chan = 1;
1287         else
1288                 bg_chan = 0;
1289
1290         ret = clk_enable(g_ipu_clk);
1291         if (ret)
1292                 return ret;
1293
1294         if (bg_chan) {
1295                 reg = __raw_readl(DP_COM_CONF());
1296                 __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF());
1297         } else {
1298                 reg = __raw_readl(DP_COM_CONF());
1299                 __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF());
1300         }
1301
1302         if (enable) {
1303                 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL;
1304                 __raw_writel(reg | ((uint32_t) alpha << 24),
1305                              DP_GRAPH_WIND_CTRL());
1306
1307                 reg = __raw_readl(DP_COM_CONF());
1308                 __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF());
1309         } else {
1310                 reg = __raw_readl(DP_COM_CONF());
1311                 __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF());
1312         }
1313
1314         reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
1315         __raw_writel(reg, IPU_SRM_PRI2);
1316
1317         clk_disable(g_ipu_clk);
1318
1319         return 0;
1320 }
1321
1322 /*
1323  * This function sets the transparent color key for SDC graphic plane.
1324  *
1325  * @param       channel         Input parameter for the logical channel ID.
1326  *
1327  * @param       enable          Boolean to enable or disable color key
1328  *
1329  * @param       colorKey        24-bit RGB color for transparent color key.
1330  *
1331  * @return      Returns 0 on success or negative error code on fail
1332  */
1333 int ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
1334                                uint32_t color_key)
1335 {
1336         int ret;
1337         uint32_t reg;
1338         int y, u, v;
1339         int red, green, blue;
1340
1341         if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
1342                 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
1343                 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
1344                 return -EINVAL;
1345
1346         ret = clk_enable(g_ipu_clk);
1347         if (ret)
1348                 return ret;
1349
1350         color_key_4rgb = 1;
1351         /* Transform color key from rgb to yuv if CSC is enabled */
1352         if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
1353                 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
1354                 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
1355                 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) {
1356
1357                 debug("color key 0x%x need change to yuv fmt\n", color_key);
1358
1359                 red = (color_key >> 16) & 0xFF;
1360                 green = (color_key >> 8) & 0xFF;
1361                 blue = color_key & 0xFF;
1362
1363                 y = rgb_to_yuv(0, red, green, blue);
1364                 u = rgb_to_yuv(1, red, green, blue);
1365                 v = rgb_to_yuv(2, red, green, blue);
1366                 color_key = (y << 16) | (u << 8) | v;
1367
1368                 color_key_4rgb = 0;
1369
1370                 debug("color key change to yuv fmt 0x%x\n", color_key);
1371         }
1372
1373         if (enable) {
1374                 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
1375                 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
1376
1377                 reg = __raw_readl(DP_COM_CONF());
1378                 __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF());
1379         } else {
1380                 reg = __raw_readl(DP_COM_CONF());
1381                 __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF());
1382         }
1383
1384         reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
1385         __raw_writel(reg, IPU_SRM_PRI2);
1386
1387         clk_disable(g_ipu_clk);
1388
1389         return 0;
1390 }