drivers/video/mxc_epdc_fb.h

   1 /*
   2  * Copyright (C) 2010 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  17  *
  18  */
  19 #ifndef __EPDC_REGS_INCLUDED__
  20 #define __EPDC_REGS_INCLUDED__
  21
  22 #include <linux/types.h>
  23 #include <linux/list.h>
  24
  25 /*************************************
  26  * Register addresses
  27  *************************************/
  28 #define EPDC_BASE                       (EPDC_BASE_ADDR)
  29
  30 #define EPDC_CTRL                       (0x000)
  31 #define EPDC_CTRL_SET                   (0x004)
  32 #define EPDC_CTRL_CLR                   (0x008)
  33 #define EPDC_CTRL_TOG                   (0x00c)
  34 #define EPDC_WVADDR                     (0x020)
  35 #define EPDC_WB_ADDR                    (0x030)
  36 #define EPDC_RES                        (0x040)
  37 #define EPDC_FORMAT                     (0x050)
  38 #define EPDC_FORMAT_SET                 (0x054)
  39 #define EPDC_FORMAT_CLR                 (0x058)
  40 #define EPDC_FORMAT_TOG                 (0x05c)
  41 #define EPDC_FIFOCTRL                   (0x0a0)
  42 #define EPDC_FIFOCTRL_SET               (0x0a4)
  43 #define EPDC_FIFOCTRL_CLR               (0x0a8)
  44 #define EPDC_FIFOCTRL_TOG               (0x0ac)
  45 #define EPDC_UPD_ADDR                   (0x100)
  46 #define EPDC_UPD_CORD                   (0x120)
  47 #define EPDC_UPD_SIZE                   (0x140)
  48 #define EPDC_UPD_CTRL                   (0x160)
  49 #define EPDC_UPD_FIXED                  (0x180)
  50 #define EPDC_TEMP                       (0x1a0)
  51 #define EPDC_TCE_CTRL                   (0x200)
  52 #define EPDC_TCE_SDCFG                  (0x220)
  53 #define EPDC_TCE_GDCFG                  (0x240)
  54 #define EPDC_TCE_HSCAN1                 (0x260)
  55 #define EPDC_TCE_HSCAN2                 (0x280)
  56 #define EPDC_TCE_VSCAN                  (0x2a0)
  57 #define EPDC_TCE_OE                     (0x2c0)
  58 #define EPDC_TCE_POLARITY               (0x2e0)
  59 #define EPDC_TCE_TIMING1                (0x300)
  60 #define EPDC_TCE_TIMING2                (0x310)
  61 #define EPDC_TCE_TIMING3                (0x320)
  62 #define EPDC_IRQ_MASK                   (0x400)
  63 #define EPDC_IRQ_MASK_SET               (0x404)
  64 #define EPDC_IRQ_MASK_CLR               (0x408)
  65 #define EPDC_IRQ_MASK_TOG               (0x40c)
  66 #define EPDC_IRQ                        (0x420)
  67 #define EPDC_IRQ_SET                    (0x424)
  68 #define EPDC_IRQ_CLR                    (0x428)
  69 #define EPDC_IRQ_TOG                    (0x42c)
  70 #define EPDC_STATUS_LUTS                (0x440)
  71 #define EPDC_STATUS_LUTS_SET            (0x444)
  72 #define EPDC_STATUS_LUTS_CLR            (0x448)
  73 #define EPDC_STATUS_LUTS_TOG            (0x44c)
  74 #define EPDC_STATUS_NEXTLUT             (0x460)
  75 #define EPDC_STATUS_COL                 (0x480)
  76 #define EPDC_STATUS                     (0x4a0)
  77 #define EPDC_STATUS_SET                 (0x4a4)
  78 #define EPDC_STATUS_CLR                 (0x4a8)
  79 #define EPDC_STATUS_TOG                 (0x4ac)
  80 #define EPDC_DEBUG                      (0x500)
  81 #define EPDC_DEBUG_LUT0                 (0x540)
  82 #define EPDC_DEBUG_LUT1                 (0x550)
  83 #define EPDC_DEBUG_LUT2                 (0x560)
  84 #define EPDC_DEBUG_LUT3                 (0x570)
  85 #define EPDC_DEBUG_LUT4                 (0x580)
  86 #define EPDC_DEBUG_LUT5                 (0x590)
  87 #define EPDC_DEBUG_LUT6                 (0x5a0)
  88 #define EPDC_DEBUG_LUT7                 (0x5b0)
  89 #define EPDC_DEBUG_LUT8                 (0x5c0)
  90 #define EPDC_DEBUG_LUT9                 (0x5d0)
  91 #define EPDC_DEBUG_LUT10                (0x5e0)
  92 #define EPDC_DEBUG_LUT11                (0x5f0)
  93 #define EPDC_DEBUG_LUT12                (0x600)
  94 #define EPDC_DEBUG_LUT13                (0x610)
  95 #define EPDC_DEBUG_LUT14                (0x620)
  96 #define EPDC_DEBUG_LUT15                (0x630)
  97 #define EPDC_GPIO                       (0x700)
  98 #define EPDC_VERSION                    (0x7f0)
  99
 100 enum {
 101         /* EPDC_CTRL field values */
 102         EPDC_CTRL_SFTRST = 0x80000000,
 103         EPDC_CTRL_CLKGATE = 0x40000000,
 104         EPDC_CTRL_SRAM_POWERDOWN = 0x100,
 105         EPDC_CTRL_UPD_DATA_SWIZZLE_MASK = 0xc0,
 106         EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP = 0,
 107         EPDC_CTRL_UPD_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x40,
 108         EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_SWAP = 0x80,
 109         EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_BYTE_SWAP = 0xc0,
 110         EPDC_CTRL_LUT_DATA_SWIZZLE_MASK = 0x30,
 111         EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP = 0,
 112         EPDC_CTRL_LUT_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x10,
 113         EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_SWAP = 0x20,
 114         EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_BYTE_SWAP = 0x30,
 115         EPDC_CTRL_BURST_LEN_8_8 = 0x1,
 116         EPDC_CTRL_BURST_LEN_8_16 = 0,
 117
 118         /* EPDC_RES field values */
 119         EPDC_RES_VERTICAL_MASK = 0x1fff0000,
 120         EPDC_RES_VERTICAL_OFFSET = 16,
 121         EPDC_RES_HORIZONTAL_MASK = 0x1fff,
 122         EPDC_RES_HORIZONTAL_OFFSET = 0,
 123
 124         /* EPDC_FORMAT field values */
 125         EPDC_FORMAT_BUF_PIXEL_SCALE_ROUND = 0x1000000,
 126         EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK = 0xff0000,
 127         EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET = 16,
 128         EPDC_FORMAT_BUF_PIXEL_FORMAT_P2N = 0x200,
 129         EPDC_FORMAT_BUF_PIXEL_FORMAT_P3N = 0x300,
 130         EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N = 0x400,
 131         EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N = 0x500,
 132         EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT = 0x0,
 133         EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT_VCOM = 0x1,
 134         EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT = 0x2,
 135         EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT_VCOM = 0x3,
 136
 137         /* EPDC_FIFOCTRL field values */
 138         EPDC_FIFOCTRL_ENABLE_PRIORITY = 0x80000000,
 139         EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK = 0xff0000,
 140         EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET = 16,
 141         EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK = 0xff00,
 142         EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET = 8,
 143         EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK = 0xff,
 144         EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET = 0,
 145
 146         /* EPDC_UPD_CORD field values */
 147         EPDC_UPD_CORD_YCORD_MASK = 0x1fff0000,
 148         EPDC_UPD_CORD_YCORD_OFFSET = 16,
 149         EPDC_UPD_CORD_XCORD_MASK = 0x1fff,
 150         EPDC_UPD_CORD_XCORD_OFFSET = 0,
 151
 152         /* EPDC_UPD_SIZE field values */
 153         EPDC_UPD_SIZE_HEIGHT_MASK = 0x1fff0000,
 154         EPDC_UPD_SIZE_HEIGHT_OFFSET = 16,
 155         EPDC_UPD_SIZE_WIDTH_MASK = 0x1fff,
 156         EPDC_UPD_SIZE_WIDTH_OFFSET = 0,
 157
 158         /* EPDC_UPD_CTRL field values */
 159         EPDC_UPD_CTRL_USE_FIXED = 0x80000000,
 160         EPDC_UPD_CTRL_LUT_SEL_MASK = 0xf0000,
 161         EPDC_UPD_CTRL_LUT_SEL_OFFSET = 16,
 162         EPDC_UPD_CTRL_WAVEFORM_MODE_MASK = 0xff00,
 163         EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET = 8,
 164         EPDC_UPD_CTRL_UPDATE_MODE_FULL = 0x1,
 165
 166         /* EPDC_UPD_FIXED field values */
 167         EPDC_UPD_FIXED_FIXNP_EN = 0x80000000,
 168         EPDC_UPD_FIXED_FIXCP_EN = 0x40000000,
 169         EPDC_UPD_FIXED_FIXNP_MASK = 0xff00,
 170         EPDC_UPD_FIXED_FIXNP_OFFSET = 8,
 171         EPDC_UPD_FIXED_FIXCP_MASK = 0xff,
 172         EPDC_UPD_FIXED_FIXCP_OFFSET = 0,
 173
 174         /* EPDC_TCE_CTRL field values */
 175         EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK = 0x1ff0000,
 176         EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET = 16,
 177         EPDC_TCE_CTRL_VCOM_VAL_MASK = 0xc00,
 178         EPDC_TCE_CTRL_VCOM_VAL_OFFSET = 10,
 179         EPDC_TCE_CTRL_VCOM_MODE_AUTO = 0x200,
 180         EPDC_TCE_CTRL_VCOM_MODE_MANUAL = 0x000,
 181         EPDC_TCE_CTRL_DDR_MODE_ENABLE = 0x100,
 182         EPDC_TCE_CTRL_LVDS_MODE_CE_ENABLE = 0x80,
 183         EPDC_TCE_CTRL_LVDS_MODE_ENABLE = 0x40,
 184         EPDC_TCE_CTRL_SCAN_DIR_1_UP = 0x20,
 185         EPDC_TCE_CTRL_SCAN_DIR_0_UP = 0x10,
 186         EPDC_TCE_CTRL_DUAL_SCAN_ENABLE = 0x8,
 187         EPDC_TCE_CTRL_SDDO_WIDTH_16BIT = 0x4,
 188         EPDC_TCE_CTRL_PIXELS_PER_SDCLK_2 = 1,
 189         EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4 = 2,
 190         EPDC_TCE_CTRL_PIXELS_PER_SDCLK_8 = 3,
 191
 192         /* EPDC_TCE_SDCFG field values */
 193         EPDC_TCE_SDCFG_SDCLK_HOLD = 0x200000,
 194         EPDC_TCE_SDCFG_SDSHR = 0x100000,
 195         EPDC_TCE_SDCFG_NUM_CE_MASK = 0xf0000,
 196         EPDC_TCE_SDCFG_NUM_CE_OFFSET = 16,
 197         EPDC_TCE_SDCFG_SDDO_REFORMAT_STANDARD = 0,
 198         EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS = 0x4000,
 199         EPDC_TCE_SDCFG_SDDO_INVERT_ENABLE = 0x2000,
 200         EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK = 0x1fff,
 201         EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET = 0,
 202
 203         /* EPDC_TCE_GDCFG field values */
 204         EPDC_TCE_SDCFG_GDRL = 0x10,
 205         EPDC_TCE_SDCFG_GDOE_MODE_DELAYED_GDCLK = 0x2,
 206         EPDC_TCE_SDCFG_GDSP_MODE_FRAME_SYNC = 0x1,
 207         EPDC_TCE_SDCFG_GDSP_MODE_ONE_LINE = 0x0,
 208
 209         /* EPDC_TCE_HSCAN1 field values */
 210         EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK = 0xfff0000,
 211         EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET = 16,
 212         EPDC_TCE_HSCAN1_LINE_SYNC_MASK = 0xfff,
 213         EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET = 0,
 214
 215         /* EPDC_TCE_HSCAN2 field values */
 216         EPDC_TCE_HSCAN2_LINE_END_MASK = 0xfff0000,
 217         EPDC_TCE_HSCAN2_LINE_END_OFFSET = 16,
 218         EPDC_TCE_HSCAN2_LINE_BEGIN_MASK = 0xfff,
 219         EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET = 0,
 220
 221         /* EPDC_TCE_VSCAN field values */
 222         EPDC_TCE_VSCAN_FRAME_END_MASK = 0xff0000,
 223         EPDC_TCE_VSCAN_FRAME_END_OFFSET = 16,
 224         EPDC_TCE_VSCAN_FRAME_BEGIN_MASK = 0xff00,
 225         EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET = 8,
 226         EPDC_TCE_VSCAN_FRAME_SYNC_MASK = 0xff,
 227         EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET = 0,
 228
 229         /* EPDC_TCE_OE field values */
 230         EPDC_TCE_OE_SDOED_WIDTH_MASK = 0xff000000,
 231         EPDC_TCE_OE_SDOED_WIDTH_OFFSET = 24,
 232         EPDC_TCE_OE_SDOED_DLY_MASK = 0xff0000,
 233         EPDC_TCE_OE_SDOED_DLY_OFFSET = 16,
 234         EPDC_TCE_OE_SDOEZ_WIDTH_MASK = 0xff00,
 235         EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET = 8,
 236         EPDC_TCE_OE_SDOEZ_DLY_MASK = 0xff,
 237         EPDC_TCE_OE_SDOEZ_DLY_OFFSET = 0,
 238
 239         /* EPDC_TCE_POLARITY field values */
 240         EPDC_TCE_POLARITY_GDSP_POL_ACTIVE_HIGH = 0x10,
 241         EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH = 0x8,
 242         EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH = 0x4,
 243         EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH = 0x2,
 244         EPDC_TCE_POLARITY_SDCE_POL_ACTIVE_HIGH = 0x1,
 245
 246         /* EPDC_TCE_TIMING1 field values */
 247         EPDC_TCE_TIMING1_SDLE_SHIFT_NONE = 0x00,
 248         EPDC_TCE_TIMING1_SDLE_SHIFT_1 = 0x10,
 249         EPDC_TCE_TIMING1_SDLE_SHIFT_2 = 0x20,
 250         EPDC_TCE_TIMING1_SDLE_SHIFT_3 = 0x30,
 251         EPDC_TCE_TIMING1_SDCLK_INVERT = 0x8,
 252         EPDC_TCE_TIMING1_SDCLK_SHIFT_NONE = 0,
 253         EPDC_TCE_TIMING1_SDCLK_SHIFT_1CYCLE = 1,
 254         EPDC_TCE_TIMING1_SDCLK_SHIFT_2CYCLES = 2,
 255         EPDC_TCE_TIMING1_SDCLK_SHIFT_3CYCLES = 3,
 256
 257         /* EPDC_TCE_TIMING2 field values */
 258         EPDC_TCE_TIMING2_GDCLK_HP_MASK = 0xffff0000,
 259         EPDC_TCE_TIMING2_GDCLK_HP_OFFSET = 16,
 260         EPDC_TCE_TIMING2_GDSP_OFFSET_MASK = 0xffff,
 261         EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET = 0,
 262
 263         /* EPDC_TCE_TIMING3 field values */
 264         EPDC_TCE_TIMING3_GDOE_OFFSET_MASK = 0xffff0000,
 265         EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET = 16,
 266         EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK = 0xffff,
 267         EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET = 0,
 268
 269         /* EPDC_IRQ_MASK/EPDC_IRQ field values */
 270         EPDC_IRQ_WB_CMPLT_IRQ = 0x10000,
 271         EPDC_IRQ_LUT_COL_IRQ = 0x20000,
 272         EPDC_IRQ_TCE_UNDERRUN_IRQ = 0x40000,
 273         EPDC_IRQ_FRAME_END_IRQ = 0x80000,
 274         EPDC_IRQ_BUS_ERROR_IRQ = 0x100000,
 275         EPDC_IRQ_TCE_IDLE_IRQ = 0x200000,
 276
 277         /* EPDC_STATUS_NEXTLUT field values */
 278         EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID = 0x100,
 279         EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0xf,
 280         EPDC_STATUS_NEXTLUT_NEXT_LUT_OFFSET = 0,
 281
 282         /* EPDC_STATUS field values */
 283         EPDC_STATUS_LUTS_UNDERRUN = 0x4,
 284         EPDC_STATUS_LUTS_BUSY = 0x2,
 285         EPDC_STATUS_WB_BUSY = 0x1,
 286
 287         /* EPDC_DEBUG field values */
 288         EPDC_DEBUG_UNDERRUN_RECOVER = 0x2,
 289         EPDC_DEBUG_COLLISION_OFF = 0x1,
 290
 291         /* EPDC_GPIO field values */
 292         EPDC_GPIO_PWRCOM = 0x40,
 293         EPDC_GPIO_PWRCTRL_MASK = 0x3c,
 294         EPDC_GPIO_PWRCTRL_OFFSET = 2,
 295         EPDC_GPIO_BDR_MASK = 0x3,
 296         EPDC_GPIO_BDR_OFFSET = 0,
 297 };
 298
 299 #endif