drivers/video/pxa_lcd.c

   1 /*
   2  * PXA LCD Controller
   3  *
   4  * (C) Copyright 2001-2002
   5  * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /************************************************************************/
  27 /* ** HEADER FILES                                                      */
  28 /************************************************************************/
  29
  30 #include <config.h>
  31 #include <common.h>
  32 #include <version.h>
  33 #include <stdarg.h>
  34 #include <linux/types.h>
  35 #include <stdio_dev.h>
  36 #include <lcd.h>
  37 #include <asm/arch/pxa-regs.h>
  38 #include <asm/io.h>
  39
  40 /* #define DEBUG */
  41
  42 #ifdef CONFIG_LCD
  43
  44 /*----------------------------------------------------------------------*/
  45 /*
  46  * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
  47  * your display.
  48  */
  49
  50 #ifdef CONFIG_PXA_VGA
  51 /* LCD outputs connected to a video DAC  */
  52 # define LCD_BPP        LCD_COLOR8
  53
  54 /* you have to set lccr0 and lccr3 (including pcd) */
  55 # define REG_LCCR0      0x003008f8
  56 # define REG_LCCR3      0x0300FF01
  57
  58 /* 640x480x16 @ 61 Hz */
  59 vidinfo_t panel_info = {
  60         .vl_col         = 640,
  61         .vl_row         = 480,
  62         .vl_width       = 640,
  63         .vl_height      = 480,
  64         .vl_clkp        = CONFIG_SYS_HIGH,
  65         .vl_oep         = CONFIG_SYS_HIGH,
  66         .vl_hsp         = CONFIG_SYS_HIGH,
  67         .vl_vsp         = CONFIG_SYS_HIGH,
  68         .vl_dp          = CONFIG_SYS_HIGH,
  69         .vl_bpix        = LCD_BPP,
  70         .vl_lbw         = 0,
  71         .vl_splt        = 0,
  72         .vl_clor        = 0,
  73         .vl_tft         = 1,
  74         .vl_hpw         = 40,
  75         .vl_blw         = 56,
  76         .vl_elw         = 56,
  77         .vl_vpw         = 20,
  78         .vl_bfw         = 8,
  79         .vl_efw         = 8,
  80 };
  81 #endif /* CONFIG_PXA_VIDEO */
  82
  83 /*----------------------------------------------------------------------*/
  84 #ifdef CONFIG_SHARP_LM8V31
  85
  86 # define LCD_BPP        LCD_COLOR8
  87 # define LCD_INVERT_COLORS      /* Needed for colors to be correct, but why?    */
  88
  89 /* you have to set lccr0 and lccr3 (including pcd) */
  90 # define REG_LCCR0      0x0030087C
  91 # define REG_LCCR3      0x0340FF08
  92
  93 vidinfo_t panel_info = {
  94         .vl_col         = 640,
  95         .vl_row         = 480,
  96         .vl_width       = 157,
  97         .vl_height      = 118,
  98         .vl_clkp        = CONFIG_SYS_HIGH,
  99         .vl_oep         = CONFIG_SYS_HIGH,
 100         .vl_hsp         = CONFIG_SYS_HIGH,
 101         .vl_vsp         = CONFIG_SYS_HIGH,
 102         .vl_dp          = CONFIG_SYS_HIGH,
 103         .vl_bpix        = LCD_BPP,
 104         .vl_lbw         = 0,
 105         .vl_splt        = 1,
 106         .vl_clor        = 1,
 107         .vl_tft         = 0,
 108         .vl_hpw         = 1,
 109         .vl_blw         = 3,
 110         .vl_elw         = 3,
 111         .vl_vpw         = 1,
 112         .vl_bfw         = 0,
 113         .vl_efw         = 0,
 114 };
 115 #endif /* CONFIG_SHARP_LM8V31 */
 116 /*----------------------------------------------------------------------*/
 117 #ifdef CONFIG_VOIPAC_LCD
 118
 119 # define LCD_BPP        LCD_COLOR8
 120 # define LCD_INVERT_COLORS
 121
 122 /* you have to set lccr0 and lccr3 (including pcd) */
 123 # define REG_LCCR0      0x043008f8
 124 # define REG_LCCR3      0x0340FF08
 125
 126 vidinfo_t panel_info = {
 127         .vl_col         = 640,
 128         .vl_row         = 480,
 129         .vl_width       = 157,
 130         .vl_height      = 118,
 131         .vl_clkp        = CONFIG_SYS_HIGH,
 132         .vl_oep         = CONFIG_SYS_HIGH,
 133         .vl_hsp         = CONFIG_SYS_HIGH,
 134         .vl_vsp         = CONFIG_SYS_HIGH,
 135         .vl_dp          = CONFIG_SYS_HIGH,
 136         .vl_bpix        = LCD_BPP,
 137         .vl_lbw         = 0,
 138         .vl_splt        = 1,
 139         .vl_clor        = 1,
 140         .vl_tft         = 1,
 141         .vl_hpw         = 32,
 142         .vl_blw         = 144,
 143         .vl_elw         = 32,
 144         .vl_vpw         = 2,
 145         .vl_bfw         = 13,
 146         .vl_efw         = 30,
 147 };
 148 #endif /* CONFIG_VOIPAC_LCD */
 149
 150 /*----------------------------------------------------------------------*/
 151 #ifdef CONFIG_HITACHI_SX14
 152 /* Hitachi SX14Q004-ZZA color STN LCD */
 153 #define LCD_BPP         LCD_COLOR8
 154
 155 /* you have to set lccr0 and lccr3 (including pcd) */
 156 #define REG_LCCR0       0x00301079
 157 #define REG_LCCR3       0x0340FF20
 158
 159 vidinfo_t panel_info = {
 160         .vl_col         = 320,
 161         .vl_row         = 240,
 162         .vl_width       = 167,
 163         .vl_height      = 109,
 164         .vl_clkp        = CONFIG_SYS_HIGH,
 165         .vl_oep         = CONFIG_SYS_HIGH,
 166         .vl_hsp         = CONFIG_SYS_HIGH,
 167         .vl_vsp         = CONFIG_SYS_HIGH,
 168         .vl_dp          = CONFIG_SYS_HIGH,
 169         .vl_bpix        = LCD_BPP,
 170         .vl_lbw         = 1,
 171         .vl_splt        = 0,
 172         .vl_clor        = 1,
 173         .vl_tft         = 0,
 174         .vl_hpw         = 1,
 175         .vl_blw         = 1,
 176         .vl_elw         = 1,
 177         .vl_vpw         = 7,
 178         .vl_bfw         = 0,
 179         .vl_efw         = 0,
 180 };
 181 #endif /* CONFIG_HITACHI_SX14 */
 182
 183 /*----------------------------------------------------------------------*/
 184 #ifdef CONFIG_LMS283GF05
 185
 186 # define LCD_BPP        LCD_COLOR8
 187 /*# define LCD_INVERT_COLORS*/
 188
 189 /* you have to set lccr0 and lccr3 (including pcd) */
 190 # define REG_LCCR0      0x043008f8
 191 # define REG_LCCR3      0x03b00009
 192
 193 vidinfo_t panel_info = {
 194         .vl_col         = 240,
 195         .vl_row         = 320,
 196         .vl_width       = 240,
 197         .vl_height      = 320,
 198         .vl_clkp        = CONFIG_SYS_HIGH,
 199         .vl_oep         = CONFIG_SYS_LOW,
 200         .vl_hsp         = CONFIG_SYS_LOW,
 201         .vl_vsp         = CONFIG_SYS_LOW,
 202         .vl_dp          = CONFIG_SYS_HIGH,
 203         .vl_bpix        = LCD_BPP,
 204         .vl_lbw         = 0,
 205         .vl_splt        = 1,
 206         .vl_clor        = 1,
 207         .vl_tft         = 1,
 208         .vl_hpw         = 4,
 209         .vl_blw         = 4,
 210         .vl_elw         = 8,
 211         .vl_vpw         = 4,
 212         .vl_bfw         = 4,
 213         .vl_efw         = 8,
 214 };
 215 #endif /* CONFIG_LMS283GF05 */
 216
 217 /*----------------------------------------------------------------------*/
 218
 219 #ifdef CONFIG_ACX517AKN
 220
 221 # define LCD_BPP        LCD_COLOR8
 222
 223 /* you have to set lccr0 and lccr3 (including pcd) */
 224 # define REG_LCCR0      0x003008f9
 225 # define REG_LCCR3      0x03700006
 226
 227 vidinfo_t panel_info = {
 228         .vl_col         = 320,
 229         .vl_row         = 320,
 230         .vl_width       = 320,
 231         .vl_height      = 320,
 232         .vl_clkp        = CONFIG_SYS_HIGH,
 233         .vl_oep         = CONFIG_SYS_LOW,
 234         .vl_hsp         = CONFIG_SYS_LOW,
 235         .vl_vsp         = CONFIG_SYS_LOW,
 236         .vl_dp          = CONFIG_SYS_HIGH,
 237         .vl_bpix        = LCD_BPP,
 238         .vl_lbw         = 0,
 239         .vl_splt        = 1,
 240         .vl_clor        = 1,
 241         .vl_tft         = 1,
 242         .vl_hpw         = 0x04,
 243         .vl_blw         = 0x1c,
 244         .vl_elw         = 0x08,
 245         .vl_vpw         = 0x01,
 246         .vl_bfw         = 0x07,
 247         .vl_efw         = 0x08,
 248 };
 249 #endif /* CONFIG_ACX517AKN */
 250
 251 #ifdef CONFIG_ACX544AKN
 252
 253 # define LCD_BPP        LCD_COLOR16
 254
 255 /* you have to set lccr0 and lccr3 (including pcd) */
 256 # define REG_LCCR0      0x003008f9
 257 # define REG_LCCR3      0x04700007 /* 16bpp */
 258
 259 vidinfo_t panel_info = {
 260         .vl_col         = 320,
 261         .vl_row         = 320,
 262         .vl_width       = 320,
 263         .vl_height      = 320,
 264         .vl_clkp        = CONFIG_SYS_LOW,
 265         .vl_oep         = CONFIG_SYS_LOW,
 266         .vl_hsp         = CONFIG_SYS_LOW,
 267         .vl_vsp         = CONFIG_SYS_LOW,
 268         .vl_dp          = CONFIG_SYS_LOW,
 269         .vl_bpix        = LCD_BPP,
 270         .vl_lbw         = 0,
 271         .vl_splt        = 0,
 272         .vl_clor        = 1,
 273         .vl_tft         = 1,
 274         .vl_hpw         = 0x05,
 275         .vl_blw         = 0x13,
 276         .vl_elw         = 0x08,
 277         .vl_vpw         = 0x02,
 278         .vl_bfw         = 0x07,
 279         .vl_efw         = 0x05,
 280 };
 281 #endif /* CONFIG_ACX544AKN */
 282
 283 /*----------------------------------------------------------------------*/
 284
 285 #ifdef CONFIG_LQ038J7DH53
 286
 287 # define LCD_BPP        LCD_COLOR8
 288
 289 /* you have to set lccr0 and lccr3 (including pcd) */
 290 # define REG_LCCR0      0x003008f9
 291 # define REG_LCCR3      0x03700004
 292
 293 vidinfo_t panel_info = {
 294         .vl_col         = 320,
 295         .vl_row         = 480,
 296         .vl_width       = 320,
 297         .vl_height      = 480,
 298         .vl_clkp        = CONFIG_SYS_HIGH,
 299         .vl_oep         = CONFIG_SYS_LOW,
 300         .vl_hsp         = CONFIG_SYS_LOW,
 301         .vl_vsp         = CONFIG_SYS_LOW,
 302         .vl_dp          = CONFIG_SYS_HIGH,
 303         .vl_bpix        = LCD_BPP,
 304         .vl_lbw         = 0,
 305         .vl_splt        = 1,
 306         .vl_clor        = 1,
 307         .vl_tft         = 1,
 308         .vl_hpw         = 0x04,
 309         .vl_blw         = 0x20,
 310         .vl_elw         = 0x01,
 311         .vl_vpw         = 0x01,
 312         .vl_bfw         = 0x04,
 313         .vl_efw         = 0x01,
 314 };
 315 #endif /* CONFIG_ACX517AKN */
 316
 317 /*----------------------------------------------------------------------*/
 318
 319 #ifdef CONFIG_LITTLETON_LCD
 320 # define LCD_BPP        LCD_COLOR8
 321
 322 /* you have to set lccr0 and lccr3 (including pcd) */
 323 # define REG_LCCR0      0x003008f8
 324 # define REG_LCCR3      0x0300FF04
 325
 326 vidinfo_t panel_info = {
 327         .vl_col         = 480,
 328         .vl_row         = 640,
 329         .vl_width       = 480,
 330         .vl_height      = 640,
 331         .vl_clkp        = CONFIG_SYS_HIGH,
 332         .vl_oep         = CONFIG_SYS_HIGH,
 333         .vl_hsp         = CONFIG_SYS_HIGH,
 334         .vl_vsp         = CONFIG_SYS_HIGH,
 335         .vl_dp          = CONFIG_SYS_HIGH,
 336         .vl_bpix        = LCD_BPP,
 337         .vl_lbw         = 0,
 338         .vl_splt        = 0,
 339         .vl_clor        = 0,
 340         .vl_tft         = 1,
 341         .vl_hpw         = 9,
 342         .vl_blw         = 8,
 343         .vl_elw         = 24,
 344         .vl_vpw         = 2,
 345         .vl_bfw         = 2,
 346         .vl_efw         = 4,
 347 };
 348 #endif /* CONFIG_LITTLETON_LCD */
 349
 350 /*----------------------------------------------------------------------*/
 351
 352 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
 353 static void pxafb_setup_gpio (vidinfo_t *vid);
 354 static void pxafb_enable_controller (vidinfo_t *vid);
 355 static int pxafb_init (vidinfo_t *vid);
 356
 357 /************************************************************************/
 358 /* ---------------  PXA chipset specific functions  ------------------- */
 359 /************************************************************************/
 360
 361 void lcd_ctrl_init (void *lcdbase)
 362 {
 363         pxafb_init_mem(lcdbase, &panel_info);
 364         pxafb_init(&panel_info);
 365         pxafb_setup_gpio(&panel_info);
 366         pxafb_enable_controller(&panel_info);
 367 }
 368
 369 /*----------------------------------------------------------------------*/
 370 #if LCD_BPP == LCD_COLOR8
 371 void
 372 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
 373 {
 374         struct pxafb_info *fbi = &panel_info.pxa;
 375         unsigned short *palette = (unsigned short *)fbi->palette;
 376         u_int val;
 377
 378         if (regno < fbi->palette_size) {
 379                 val = ((red << 8) & 0xf800);
 380                 val |= ((green << 4) & 0x07e0);
 381                 val |= (blue & 0x001f);
 382
 383 #ifdef LCD_INVERT_COLORS
 384                 palette[regno] = ~val;
 385 #else
 386                 palette[regno] = val;
 387 #endif
 388         }
 389
 390         debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
 391                 regno, &palette[regno],
 392                 red, green, blue,
 393                 palette[regno]);
 394 }
 395 #endif /* LCD_COLOR8 */
 396
 397 /*----------------------------------------------------------------------*/
 398 #if LCD_BPP == LCD_MONOCHROME
 399 void lcd_initcolregs (void)
 400 {
 401         struct pxafb_info *fbi = &panel_info.pxa;
 402         cmap = (ushort *)fbi->palette;
 403         ushort regno;
 404
 405         for (regno = 0; regno < 16; regno++) {
 406                 cmap[regno * 2] = 0;
 407                 cmap[(regno * 2) + 1] = regno & 0x0f;
 408         }
 409 }
 410 #endif /* LCD_MONOCHROME */
 411
 412 /*----------------------------------------------------------------------*/
 413 __weak void lcd_enable(void)
 414 {
 415 }
 416
 417 /************************************************************************/
 418 /* ** PXA255 specific routines                                          */
 419 /************************************************************************/
 420
 421 /*
 422  * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
 423  * descriptors and palette areas.
 424  */
 425 ulong calc_fbsize (void)
 426 {
 427         ulong size;
 428         int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
 429
 430         size = line_length * panel_info.vl_row;
 431         size += PAGE_SIZE;
 432
 433         return size;
 434 }
 435
 436 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
 437 {
 438         u_long palette_mem_size;
 439         struct pxafb_info *fbi = &vid->pxa;
 440         int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
 441
 442         fbi->screen = (u_long)lcdbase;
 443
 444         fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
 445         palette_mem_size = fbi->palette_size * sizeof(u16);
 446
 447         debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
 448         /* locate palette and descs at end of page following fb */
 449         fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
 450
 451         return 0;
 452 }
 453 #ifdef  CONFIG_CPU_MONAHANS
 454 static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
 455 #else
 456 static void pxafb_setup_gpio (vidinfo_t *vid)
 457 {
 458         u_long lccr0;
 459
 460         /*
 461          * setup is based on type of panel supported
 462          */
 463
 464         lccr0 = vid->pxa.reg_lccr0;
 465
 466         /* 4 bit interface */
 467         if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
 468         {
 469                 debug("Setting GPIO for 4 bit data\n");
 470                 /* bits 58-61 */
 471                 writel(readl(GPDR1) | (0xf << 26), GPDR1);
 472                 writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
 473                         GAFR1_U);
 474
 475                 /* bits 74-77 */
 476                 writel(readl(GPDR2) | (0xf << 10), GPDR2);
 477                 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
 478                         GAFR2_L);
 479         }
 480
 481         /* 8 bit interface */
 482         else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
 483                 (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
 484         {
 485                 debug("Setting GPIO for 8 bit data\n");
 486                 /* bits 58-65 */
 487                 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
 488                 writel(readl(GPDR2) | (0x3), GPDR2);
 489
 490                 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
 491                         GAFR1_U);
 492                 writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
 493
 494                 /* bits 74-77 */
 495                 writel(readl(GPDR2) | (0xf << 10), GPDR2);
 496                 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
 497                         GAFR2_L);
 498         }
 499
 500         /* 16 bit interface */
 501         else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
 502         {
 503                 debug("Setting GPIO for 16 bit data\n");
 504                 /* bits 58-77 */
 505                 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
 506                 writel(readl(GPDR2) | 0x00003fff, GPDR2);
 507
 508                 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
 509                         GAFR1_U);
 510                 writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
 511         }
 512         else
 513         {
 514                 printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
 515         }
 516 }
 517 #endif
 518
 519 static void pxafb_enable_controller (vidinfo_t *vid)
 520 {
 521         debug("Enabling LCD controller\n");
 522
 523         /* Sequence from 11.7.10 */
 524         writel(vid->pxa.reg_lccr3, LCCR3);
 525         writel(vid->pxa.reg_lccr2, LCCR2);
 526         writel(vid->pxa.reg_lccr1, LCCR1);
 527         writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
 528         writel(vid->pxa.fdadr0, FDADR0);
 529         writel(vid->pxa.fdadr1, FDADR1);
 530         writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
 531
 532 #ifdef  CONFIG_CPU_MONAHANS
 533         writel(readl(CKENA) | CKENA_1_LCD, CKENA);
 534 #else
 535         writel(readl(CKEN) | CKEN16_LCD, CKEN);
 536 #endif
 537
 538         debug("FDADR0 = 0x%08x\n", readl(FDADR0));
 539         debug("FDADR1 = 0x%08x\n", readl(FDADR1));
 540         debug("LCCR0 = 0x%08x\n", readl(LCCR0));
 541         debug("LCCR1 = 0x%08x\n", readl(LCCR1));
 542         debug("LCCR2 = 0x%08x\n", readl(LCCR2));
 543         debug("LCCR3 = 0x%08x\n", readl(LCCR3));
 544 }
 545
 546 static int pxafb_init (vidinfo_t *vid)
 547 {
 548         struct pxafb_info *fbi = &vid->pxa;
 549
 550         debug("Configuring PXA LCD\n");
 551
 552         fbi->reg_lccr0 = REG_LCCR0;
 553         fbi->reg_lccr3 = REG_LCCR3;
 554
 555         debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
 556                 vid->vl_col, vid->vl_hpw,
 557                 vid->vl_blw, vid->vl_elw);
 558         debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
 559                 vid->vl_row, vid->vl_vpw,
 560                 vid->vl_bfw, vid->vl_efw);
 561
 562         fbi->reg_lccr1 =
 563                 LCCR1_DisWdth(vid->vl_col) +
 564                 LCCR1_HorSnchWdth(vid->vl_hpw) +
 565                 LCCR1_BegLnDel(vid->vl_blw) +
 566                 LCCR1_EndLnDel(vid->vl_elw);
 567
 568         fbi->reg_lccr2 =
 569                 LCCR2_DisHght(vid->vl_row) +
 570                 LCCR2_VrtSnchWdth(vid->vl_vpw) +
 571                 LCCR2_BegFrmDel(vid->vl_bfw) +
 572                 LCCR2_EndFrmDel(vid->vl_efw);
 573
 574         fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
 575         fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
 576                         | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
 577
 578
 579         /* setup dma descriptors */
 580         fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
 581         fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
 582         fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
 583
 584         #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
 585                 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
 586                 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
 587
 588         /* populate descriptors */
 589         fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
 590         fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
 591         fbi->dmadesc_fblow->fidr  = 0;
 592         fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
 593
 594         fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
 595
 596         fbi->dmadesc_fbhigh->fsadr = fbi->screen;
 597         fbi->dmadesc_fbhigh->fidr = 0;
 598         fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
 599
 600         fbi->dmadesc_palette->fsadr = fbi->palette;
 601         fbi->dmadesc_palette->fidr  = 0;
 602         fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
 603
 604         if( NBITS(vid->vl_bpix) < 12)
 605         {
 606                 /* assume any mode with <12 bpp is palette driven */
 607                 fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
 608                 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
 609                 /* flips back and forth between pal and fbhigh */
 610                 fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
 611         }
 612         else
 613         {
 614                 /* palette shouldn't be loaded in true-color mode */
 615                 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
 616                 fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
 617         }
 618
 619         debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
 620         debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
 621         debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
 622
 623         debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
 624         debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
 625         debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
 626
 627         debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
 628         debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
 629         debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
 630
 631         debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
 632         debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
 633         debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
 634
 635         return 0;
 636 }
 637
 638 /************************************************************************/
 639 /************************************************************************/
 640
 641 #endif /* CONFIG_LCD */