include/asm-arm/arch-mx35/mmu.h

   1 /*
   2  * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #ifndef __ARM_ARCH_MMU_H
  15 #define __ARM_ARCH_MMU_H
  16
  17 /*
  18  * Translation Table Base Bit Masks
  19  */
  20 #define ARM_TRANSLATION_TABLE_MASK               0xFFFFC000
  21
  22 /*
  23  * Domain Access Control Bit Masks
  24  */
  25 #define ARM_ACCESS_TYPE_NO_ACCESS(domain_num)    (0x0 << (domain_num)*2)
  26 #define ARM_ACCESS_TYPE_CLIENT(domain_num)       (0x1 << (domain_num)*2)
  27 #define ARM_ACCESS_TYPE_MANAGER(domain_num)      (0x3 << (domain_num)*2)
  28
  29 struct ARM_MMU_FIRST_LEVEL_FAULT {
  30         unsigned int id:2;
  31         unsigned int sbz:30;
  32 };
  33
  34 #define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
  35
  36 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
  37         unsigned int id:2;
  38         unsigned int imp:2;
  39         unsigned int domain:4;
  40         unsigned int sbz:1;
  41         unsigned int base_address:23;
  42 };
  43
  44 #define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
  45
  46 struct ARM_MMU_FIRST_LEVEL_SECTION {
  47         unsigned int id:2;
  48         unsigned int b:1;
  49         unsigned int c:1;
  50         unsigned int imp:1;
  51         unsigned int domain:4;
  52         unsigned int sbz0:1;
  53         unsigned int ap:2;
  54         unsigned int sbz1:8;
  55         unsigned int base_address:12;
  56 };
  57
  58 #define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
  59
  60 struct ARM_MMU_FIRST_LEVEL_RESERVED {
  61         unsigned int id:2;
  62         unsigned int sbz:30;
  63 };
  64
  65 #define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
  66
  67 #define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
  68         (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
  69
  70 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
  71
  72 #define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,            \
  73                         cacheable, bufferable, perm)                    \
  74         {                                                               \
  75         register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;             \
  76         desc.word = 0;                                                  \
  77         desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;               \
  78         desc.section.domain = 0;                                        \
  79         desc.section.c = (cacheable);                                   \
  80         desc.section.b = (bufferable);                                  \
  81         desc.section.ap = (perm);                                       \
  82         desc.section.base_address = (actual_base);                      \
  83         *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
  84                                 = desc.word;                            \
  85         }
  86
  87 #define X_ARM_MMU_SECTION(abase, vbase, size, cache, buff, access)      \
  88         {                                                               \
  89                 int i; int j = abase; int k = vbase;                    \
  90                 for (i = size; i > 0 ; i--, j++, k++)                   \
  91                         ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
  92         }
  93
  94 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
  95         unsigned long word;
  96         struct ARM_MMU_FIRST_LEVEL_FAULT fault;
  97         struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
  98         struct ARM_MMU_FIRST_LEVEL_SECTION section;
  99         struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
 100 };
 101
 102 #define ARM_UNCACHEABLE         0
 103 #define ARM_CACHEABLE           1
 104 #define ARM_UNBUFFERABLE        0
 105 #define ARM_BUFFERABLE          1
 106
 107 #define ARM_ACCESS_PERM_NONE_NONE       0
 108 #define ARM_ACCESS_PERM_RO_NONE         0
 109 #define ARM_ACCESS_PERM_RO_RO           0
 110 #define ARM_ACCESS_PERM_RW_NONE         1
 111 #define ARM_ACCESS_PERM_RW_RO           2
 112 #define ARM_ACCESS_PERM_RW_RW           3
 113
 114 /*
 115  * Initialization for the Domain Access Control Register
 116  */
 117 #define ARM_ACCESS_DACR_DEFAULT      (  \
 118         ARM_ACCESS_TYPE_MANAGER(0)    | \
 119         ARM_ACCESS_TYPE_NO_ACCESS(1)  | \
 120         ARM_ACCESS_TYPE_NO_ACCESS(2)  | \
 121         ARM_ACCESS_TYPE_NO_ACCESS(3)  | \
 122         ARM_ACCESS_TYPE_NO_ACCESS(4)  | \
 123         ARM_ACCESS_TYPE_NO_ACCESS(5)  | \
 124         ARM_ACCESS_TYPE_NO_ACCESS(6)  | \
 125         ARM_ACCESS_TYPE_NO_ACCESS(7)  | \
 126         ARM_ACCESS_TYPE_NO_ACCESS(8)  | \
 127         ARM_ACCESS_TYPE_NO_ACCESS(9)  | \
 128         ARM_ACCESS_TYPE_NO_ACCESS(10) | \
 129         ARM_ACCESS_TYPE_NO_ACCESS(11) | \
 130         ARM_ACCESS_TYPE_NO_ACCESS(12) | \
 131         ARM_ACCESS_TYPE_NO_ACCESS(13) | \
 132         ARM_ACCESS_TYPE_NO_ACCESS(14) | \
 133         ARM_ACCESS_TYPE_NO_ACCESS(15))
 134
 135 /*
 136  * Translate the virtual address of ram space to physical address
 137  * It is dependent on the implementation of mmu_init
 138  */
 139 inline unsigned long iomem_to_phys(unsigned long virt)
 140 {
 141         if (virt < 0x08000000)
 142                 return (unsigned long)(virt | PHYS_SDRAM_1);
 143
 144         if ((virt & 0xF0000000) == PHYS_SDRAM_1)
 145                 return (unsigned long)(virt & (~0x08000000));
 146
 147         return (unsigned long)virt;
 148 }
 149
 150 /*
 151  * Remap the physical address of ram space to uncacheable virtual address space
 152  * It is dependent on the implementation of hal_mmu_init
 153  */
 154 void __iounmap(void *addr)
 155 {
 156         return;
 157 }
 158
 159 void *__ioremap(unsigned long offset, size_t size, unsigned long flags)
 160 {
 161         if (1 == flags) {
 162                 /* 0x88000000~0x87FFFFFF is uncacheable meory
 163                 space which is mapped to SDRAM */
 164                 if ((offset & 0xF0000000) == PHYS_SDRAM_1)
 165                         return (void *)(offset | 0x08000000);
 166                 else
 167                         return NULL;
 168         } else
 169                 return (void *)offset;
 170 }
 171
 172 #endif