2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * Copyright (C) 2004, Intel Corporation.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
21 /* FIXME hack so that SA-1111.h will work [cb] */
24 typedef unsigned short Word16 ;
25 typedef unsigned int Word32 ;
27 typedef Word Quad [4] ;
28 typedef void *Address ;
29 typedef void (*ExcpHndlr) (void) ;
35 #ifdef CONFIG_CPU_MONAHANS
36 #define PXA_CS0_PHYS 0x00000000 /* for both small and large same start */
37 #define PXA_CS1_PHYS 0x04000000 /* Small partition start address (64MB) */
38 #define PXA_CS1_LPHYS 0x30000000 /* Large partition start address (256MB) */
39 #define PXA_CS2_PHYS 0x10000000 /* (64MB) */
40 #define PXA_CS3_PHYS 0x14000000 /* (64MB) */
41 #define PXA_PCMCIA_PHYS 0x20000000 /* (256MB) */
43 #define PXA_CS0_PHYS 0x00000000
44 #define PXA_CS1_PHYS 0x04000000
45 #define PXA_CS2_PHYS 0x08000000
46 #define PXA_CS3_PHYS 0x0C000000
47 #define PXA_CS4_PHYS 0x10000000
48 #define PXA_CS5_PHYS 0x14000000
49 #endif /* CONFIG_CPU_MONAHANS */
52 * Personal Computer Memory Card International Association (PCMCIA) sockets
55 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
56 #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
57 #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
58 #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
59 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
61 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
62 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
63 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
64 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
66 #ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */
67 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
68 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
69 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
70 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
73 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
74 (0x20000000 + (Nb)*PCMCIASp)
75 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
76 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
77 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
78 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
79 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
81 #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
82 #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
83 #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
84 #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
86 #ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */
87 #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
88 #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
89 #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
90 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
98 #define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
99 #define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
100 #define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
101 #define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
102 #define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
103 #define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
104 #define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
105 #define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
106 #define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
107 #define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
108 #define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
109 #define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
110 #define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
111 #define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
112 #define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
113 #define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
114 #define DCSR16 __REG(0x40000040) /* DMA Control / Status Register for Channel 16 */
115 #define DCSR17 __REG(0x40000044) /* DMA Control / Status Register for Channel 17 */
116 #define DCSR18 __REG(0x40000048) /* DMA Control / Status Register for Channel 18 */
117 #define DCSR19 __REG(0x4000004c) /* DMA Control / Status Register for Channel 19 */
118 #define DCSR20 __REG(0x40000050) /* DMA Control / Status Register for Channel 20 */
119 #define DCSR21 __REG(0x40000054) /* DMA Control / Status Register for Channel 21 */
120 #define DCSR22 __REG(0x40000058) /* DMA Control / Status Register for Channel 22 */
121 #define DCSR23 __REG(0x4000005c) /* DMA Control / Status Register for Channel 23 */
122 #define DCSR24 __REG(0x40000060) /* DMA Control / Status Register for Channel 24 */
123 #define DCSR25 __REG(0x40000064) /* DMA Control / Status Register for Channel 25 */
124 #define DCSR26 __REG(0x40000068) /* DMA Control / Status Register for Channel 26 */
125 #define DCSR27 __REG(0x4000006c) /* DMA Control / Status Register for Channel 27 */
126 #define DCSR28 __REG(0x40000070) /* DMA Control / Status Register for Channel 28 */
127 #define DCSR29 __REG(0x40000074) /* DMA Control / Status Register for Channel 29 */
128 #define DCSR30 __REG(0x40000078) /* DMA Control / Status Register for Channel 30 */
129 #define DCSR31 __REG(0x4000007c) /* DMA Control / Status Register for Channel 31 */
131 #define DCSR(x) __REG2(0x40000000, (x) << 2)
133 #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
134 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
135 #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
137 #if defined (CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS)
138 #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
139 #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
140 #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
141 #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
142 #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
143 #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
144 #define DCSR_EORINTR (1 << 9) /* The end of Receive */
147 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
148 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
149 #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
150 #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
151 #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
153 #ifdef CONFIG_CPU_MONAHANS
154 #define DPCSR __REG(0x400000a4) /* DMA Programmed IO control status register */
155 #define DRQSR0 __REG(0x400000e0) /* DMA DREQ<0> Status Register */
156 #define DRQSR1 __REG(0x400000e4) /* DMA DREQ<1> Status Register */
157 #define DRQSR2 __REG(0x400000e8) /* DMA DREQ<2> Status Register */
159 #define DALGN __REG(0x400000a0) /* DMA Alignment Register */
160 #endif /* CONFIG_CPU_MONAHANS */
162 #define DINT __REG(0x400000f0) /* DMA Interrupt Register */
164 #define DRCMR(n) __REG2(0x40000100, (n)<<2)
165 #define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
166 #define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
167 #define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
168 #define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
169 #define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
170 #define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
171 #define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
172 #define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
173 #define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
174 #define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
175 #define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
176 #define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
177 #define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
178 #define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
179 #define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
180 #define DRCMR15 __REG(0x4000013c) /* Reserved */
181 #define DRCMR16 __REG(0x40000140) /* Reserved */
182 #define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
183 #define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
184 #define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
185 #define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
186 #define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC/SDIO 1 receive Request */
187 #define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC/SDIO 2 transmit Request */
188 #define DRCMR23 __REG(0x4000015c) /* Reserved */
189 #define DRCMR24 __REG(0x40000160) /* Request to Channel Map Register for USB endpoint 0 request */
190 #define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
191 #define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
192 #define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
193 #define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
194 #define DRCMR29 __REG(0x40000174) /* Request to Channel Map Register for USB endpoint 5 Request */
195 #define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
196 #define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
197 #define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
198 #define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
199 #define DRCMR34 __REG(0x40000188) /* Request to Channel Map Register for USB endpoint 10 Request */
200 #define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
201 #define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
202 #define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
203 #define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
204 #define DRCMR39 __REG(0x4000019C) /* Request to Channel Map Register for USB endpoint 15 Request */
205 #define DRCMR40 __REG(0x400001A0) /* Request to Channel Map Register for USB endpoint 15 Request */
206 #define DRCMR41 __REG(0x400001A4) /* Request to Channel Map Register for USB endpoint 15 Request */
207 #define DRCMR42 __REG(0x400001A8) /* Request to Channel Map Register for USB endpoint 15 Request */
208 #define DRCMR43 __REG(0x400001AC) /* Request to Channel Map Register for USB endpoint 15 Request */
209 #define DRCMR44 __REG(0x400001B0) /* Request to Channel Map Register for USB endpoint 15 Request */
210 #define DRCMR45 __REG(0x400001B4) /* Request to Channel Map Register for USB endpoint 15 Request */
211 #define DRCMR46 __REG(0x400001B8) /* Request to Channel Map Register for USB endpoint 15 Request */
212 #define DRCMR47 __REG(0x400001BC) /* Request to Channel Map Register for USB endpoint 15 Request */
213 #define DRCMR48 __REG(0x400001C0) /* Request to Channel Map Register for MSL Receive Request 1 */
214 #define DRCMR49 __REG(0x400001C4) /* Request to Channel Map Register for MSL Transmit Request 1 */
215 #define DRCMR50 __REG(0x400001C8) /* Request to Channel Map Register for MSL Receive Request 2 */
216 #define DRCMR51 __REG(0x400001CC) /* Request to Channel Map Register for MSL Transmit Request 2 */
217 #define DRCMR52 __REG(0x400001D0) /* Request to Channel Map Register for MSL Receive Request 3 */
218 #define DRCMR53 __REG(0x400001D4) /* Request to Channel Map Register for MSL Transmit Request 3 */
219 #define DRCMR54 __REG(0x400001D8) /* Request to Channel Map Register for MSL Receive Request 4 */
220 #define DRCMR55 __REG(0x400001DC) /* Request to Channel Map Register for MSL Transmit Request 4 */
221 #define DRCMR56 __REG(0x400001E0) /* Request to Channel Map Register for MSL Receive Request 5 */
222 #define DRCMR57 __REG(0x400001E4) /* Request to Channel Map Register for MSL Transmit Request 5 */
223 #define DRCMR58 __REG(0x400001E8) /* Request to Channel Map Register for MSL Receive Request 6 */
224 #define DRCMR59 __REG(0x400001EC) /* Request to Channel Map Register for MSL Transmit Request 6 */
225 #define DRCMR60 __REG(0x400001F0) /* Request to Channel Map Register for MSL Receive Request 7 */
226 #define DRCMR61 __REG(0x400001F4) /* Request to Channel Map Register for MSL Transmit Request 7 */
227 #define DRCMR62 __REG(0x400001F8) /* Request to Channel Map Register for USIM 1 Receive Request */
228 #define DRCMR63 __REG(0x400001FC) /* Request to Channel Map Register for USIM 1 Transimit Request */
230 #define DRCMR64 __REG(0x40001100) /* Reserved */
231 #define DRCMR65 __REG(0x40001104) /* Reserved */
232 #define DRCMR66 __REG(0x40001108) /* Request to channel Map Register for SSP3 Receive Request */
233 #define DRCMR67 __REG(0x4000110C) /* Request to channel Map Register for SSP3 Receive Request */
235 #define DRCMR68 __REG(0x40001110) /* Reserved */
236 #define DRCMR69 __REG(0x40001114) /* Reserved */
237 #define DRCMR70 __REG(0x40001118) /* Reserved */
239 #define DRCMR71 __REG(0x4000111C) /* Request to Channel Map Register for TPM Receive Request */
240 #define DRCMR72 __REG(0x40001120) /* Request to Channel Map Register for TPM Transmit Request 1 */
241 #define DRCMR73 __REG(0x40001124) /* Request to Channel Map Register for TPM Transmit Request 2 */
242 #define DRCMR74 __REG(0x40001128) /* Request to Channel Map Register for DREQ<2> */
244 #define DRCMR91 __REG(0x4000116C) /* Request to Channel Map Register for USIM 2 Receive Request */
245 #define DRCMR92 __REG(0x40001170) /* Request to Channel Map Register for USIM 2 Transmit Request */
247 #define DRCMR93 __REG(0x40001174) /* Request to Channel Map Register for MMC Controller 1 Request */
248 #define DRCMR94 __REG(0x40001178) /* Request to Channel Map Register for MMC Controller 2 Request */
249 #define DRCMR95 __REG(0x4000117C) /* Request to Channel Map Register for AC97 Surround Transmit Request */
250 #define DRCMR96 __REG(0x40001180) /* Request to Channel Map Register for AC97 centre/LFE Transmit Request */
251 #define DRCMR97 __REG(0x40001184) /* Request to Channel Map Register for NAND interface data transmit & receive Request */
252 #define DRCMR98 __REG(0x40001188) /* Reserved */
253 #define DRCMR99 __REG(0x4000118C) /* Request to Channel Map Register for NAND interface command transmit Request */
256 #define DRCMRRXSADR DRCMR2
257 #define DRCMRTXSADR DRCMR3
258 #define DRCMRRXBTRBR DRCMR4
259 #define DRCMRTXBTTHR DRCMR5
260 #define DRCMRRXFFRBR DRCMR6
261 #define DRCMRTXFFTHR DRCMR7
262 #define DRCMRRXMCDR DRCMR8
263 #define DRCMRRXMODR DRCMR9
264 #define DRCMRTXMODR DRCMR10
265 #define DRCMRRXPCDR DRCMR11
266 #define DRCMRTXPCDR DRCMR12
267 #define DRCMRRXSSDR DRCMR13
268 #define DRCMRTXSSDR DRCMR14
269 #define DRCMRRXICDR DRCMR17
270 #define DRCMRTXICDR DRCMR18
271 #define DRCMRRXSTRBR DRCMR19
272 #define DRCMRTXSTTHR DRCMR20
273 #define DRCMRRXMMC DRCMR21
274 #define DRCMRTXMMC DRCMR22
275 #define DRCMRRXMMC2 DRCMR93
276 #define DRCMRTXMMC2 DRCMR94
277 #define DRCMRUDC(x) DRCMR((x) + 24)
279 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
280 #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
282 #define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
283 #define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
284 #define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
285 #define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
286 #define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
287 #define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
288 #define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
289 #define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
290 #define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
291 #define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
292 #define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
293 #define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
294 #define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
295 #define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
296 #define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
297 #define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
298 #define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
299 #define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
300 #define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
301 #define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
302 #define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
303 #define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
304 #define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
305 #define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
306 #define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
307 #define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
308 #define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
309 #define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
310 #define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
311 #define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
312 #define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
313 #define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
314 #define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
315 #define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
316 #define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
317 #define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
318 #define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
319 #define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
320 #define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
321 #define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
322 #define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
323 #define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
324 #define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
325 #define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
326 #define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
327 #define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
328 #define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
329 #define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
330 #define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
331 #define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
332 #define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
333 #define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
334 #define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
335 #define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
336 #define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
337 #define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
338 #define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
339 #define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
340 #define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
341 #define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
342 #define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
343 #define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
344 #define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
345 #define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
347 #define DDADR(x) __REG2(0x40000200, (x) << 4)
348 #define DSADR(x) __REG2(0x40000204, (x) << 4)
349 #define DTADR(x) __REG2(0x40000208, (x) << 4)
350 #define DCMD(x) __REG2(0x4000020c, (x) << 4)
352 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
353 #define DDADR_STOP (1 << 0) /* Stop (read / write) */
355 #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
356 #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
357 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
358 #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
359 #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
360 #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
361 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
362 #define DCMD_BURST8 (1 << 16) /* 8 byte burst */
363 #define DCMD_BURST16 (2 << 16) /* 16 byte burst */
364 #define DCMD_BURST32 (3 << 16) /* 32 byte burst */
365 #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
366 #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
367 #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
368 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
370 /* default combinations */
371 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
372 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
373 #define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
380 /* Full Function UART (FFUART) */
382 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
383 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
384 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
385 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
386 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
387 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
388 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
389 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
390 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
391 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
392 #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
393 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
394 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
396 /* Bluetooth UART (BTUART) */
398 #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
399 #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
400 #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
401 #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
402 #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
403 #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
404 #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
405 #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
406 #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
407 #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
408 #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
409 #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
410 #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
412 /* Standard UART (STUART) */
414 #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
415 #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
416 #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
417 #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
418 #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
419 #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
420 #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
421 #define STLSR __REG(0x40700014) /* Line Status Register (read only) */
422 #define STMSR __REG(0x40700018) /* Reserved */
423 #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
424 #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
425 #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
426 #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
428 #define IER_DMAE (1 << 7) /* DMA Requests Enable */
429 #define IER_UUE (1 << 6) /* UART Unit Enable */
430 #define IER_NRZE (1 << 5) /* NRZ coding Enable */
431 #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
432 #define IER_MIE (1 << 3) /* Modem Interrupt Enable */
433 #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
434 #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
435 #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
437 #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
438 #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
439 #define IIR_TOD (1 << 3) /* Time Out Detected */
440 #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
441 #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
442 #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
444 #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
445 #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
446 #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
447 #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
448 #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
449 #define FCR_ITL_1 (0)
450 #define FCR_ITL_8 (FCR_ITL1)
451 #define FCR_ITL_16 (FCR_ITL2)
452 #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
454 #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
455 #define LCR_SB (1 << 6) /* Set Break */
456 #define LCR_STKYP (1 << 5) /* Sticky Parity */
457 #define LCR_EPS (1 << 4) /* Even Parity Select */
458 #define LCR_PEN (1 << 3) /* Parity Enable */
459 #define LCR_STB (1 << 2) /* Stop Bit */
460 #define LCR_WLS1 (1 << 1) /* Word Length Select */
461 #define LCR_WLS0 (1 << 0) /* Word Length Select */
463 #define LSR_FIFOE (1 << 7) /* FIFO Error Status */
464 #define LSR_TEMT (1 << 6) /* Transmitter Empty */
465 #define LSR_TDRQ (1 << 5) /* Transmit Data Request */
466 #define LSR_BI (1 << 4) /* Break Interrupt */
467 #define LSR_FE (1 << 3) /* Framing Error */
468 #define LSR_PE (1 << 2) /* Parity Error */
469 #define LSR_OE (1 << 1) /* Overrun Error */
470 #define LSR_DR (1 << 0) /* Data Ready */
472 #define MCR_LOOP (1 << 4)
473 #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
474 #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
475 #define MCR_RTS (1 << 1) /* Request to Send */
476 #define MCR_DTR (1 << 0) /* Data Terminal Ready */
478 #define MSR_DCD (1 << 7) /* Data Carrier Detect */
479 #define MSR_RI (1 << 6) /* Ring Indicator */
480 #define MSR_DSR (1 << 5) /* Data Set Ready */
481 #define MSR_CTS (1 << 4) /* Clear To Send */
482 #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
483 #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
484 #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
485 #define MSR_DCTS (1 << 0) /* Delta Clear To Send */
488 * IrSR (Infrared Selection Register)
490 #ifdef CONFIG_CPU_MONAHANS
491 #define STISR_RXPL (1 << 4) /* Receive Data Polarity */
492 #define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
493 #define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
494 #define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
495 #define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
497 #define IrSR_OFFSET 0x20
499 #define IrSR_RXPL_NEG_IS_ZERO (1<<4)
500 #define IrSR_RXPL_POS_IS_ZERO 0x0
501 #define IrSR_TXPL_NEG_IS_ZERO (1<<3)
502 #define IrSR_TXPL_POS_IS_ZERO 0x0
503 #define IrSR_XMODE_PULSE_1_6 (1<<2)
504 #define IrSR_XMODE_PULSE_3_16 0x0
505 #define IrSR_RCVEIR_IR_MODE (1<<1)
506 #define IrSR_RCVEIR_UART_MODE 0x0
507 #define IrSR_XMITIR_IR_MODE (1<<0)
508 #define IrSR_XMITIR_UART_MODE 0x0
510 #define IrSR_IR_RECEIVE_ON (\
511 IrSR_RXPL_NEG_IS_ZERO | \
512 IrSR_TXPL_POS_IS_ZERO | \
513 IrSR_XMODE_PULSE_3_16 | \
514 IrSR_RCVEIR_IR_MODE | \
515 IrSR_XMITIR_UART_MODE)
517 #define IrSR_IR_TRANSMIT_ON (\
518 IrSR_RXPL_NEG_IS_ZERO | \
519 IrSR_TXPL_POS_IS_ZERO | \
520 IrSR_XMODE_PULSE_3_16 | \
521 IrSR_RCVEIR_UART_MODE | \
523 #endif /* not CONFIG_CPU_MONAHANS */
529 #define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
530 #define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
531 #define ICR __REG(0x40301690) /* I2C Control Register - ICR */
532 #define ISR __REG(0x40301698) /* I2C Status Register - ISR */
533 #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
535 #define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
536 #define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
537 #define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
538 #define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
539 #define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */
541 #define ICR_START (1 << 0) /* start bit */
542 #define ICR_STOP (1 << 1) /* stop bit */
543 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
544 #define ICR_TB (1 << 3) /* transfer byte bit */
545 #define ICR_MA (1 << 4) /* master abort */
546 #define ICR_SCLE (1 << 5) /* master clock enable */
547 #define ICR_IUE (1 << 6) /* unit enable */
548 #define ICR_GCD (1 << 7) /* general call disable */
549 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */
550 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */
551 #define ICR_BEIE (1 << 10) /* enable bus error ints */
552 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
553 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
554 #define ICR_SADIE (1 << 13) /* slave address detected int enable */
555 #define ICR_UR (1 << 14) /* unit reset */
557 #define ISR_RWM (1 << 0) /* read/write mode */
558 #define ISR_ACKNAK (1 << 1) /* ack/nak status */
559 #define ISR_UB (1 << 2) /* unit busy */
560 #define ISR_IBB (1 << 3) /* bus busy */
561 #define ISR_SSD (1 << 4) /* slave stop detected */
562 #define ISR_ALD (1 << 5) /* arbitration loss detected */
563 #define ISR_ITE (1 << 6) /* tx buffer empty */
564 #define ISR_IRF (1 << 7) /* rx buffer full */
565 #define ISR_GCAD (1 << 8) /* general call address detected */
566 #define ISR_SAD (1 << 9) /* slave address detected */
567 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */
571 * Serial Audio Controller
574 /* FIXME: This clash with SA1111 defines */
575 #ifndef CONFIG_SA1111
576 #define SACR0 __REG(0x40400000) /* Global Control Register */
577 #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
578 #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
579 #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
580 #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
581 #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
582 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
587 * AC97 Controller registers
590 #define POCR __REG(0x40500000) /* PCM Out Control Register */
591 #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
593 #define PICR __REG(0x40500004) /* PCM In Control Register */
594 #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
596 #define MCCR __REG(0x40500008) /* Mic In Control Register */
597 #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
599 #define GCR __REG(0x4050000C) /* Global Control Register */
600 #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
601 #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
602 #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
603 #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
604 #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
605 #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
606 #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
607 #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
608 #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
609 #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
611 #define POSR __REG(0x40500010) /* PCM Out Status Register */
612 #define POSR_FIFOE (1 << 4) /* FIFO error */
614 #define PISR __REG(0x40500014) /* PCM In Status Register */
615 #define PISR_FIFOE (1 << 4) /* FIFO error */
617 #define MCSR __REG(0x40500018) /* Mic In Status Register */
618 #define MCSR_FIFOE (1 << 4) /* FIFO error */
620 #define GSR __REG(0x4050001C) /* Global Status Register */
621 #define GSR_CDONE (1 << 19) /* Command Done */
622 #define GSR_SDONE (1 << 18) /* Status Done */
623 #define GSR_RDCS (1 << 15) /* Read Completion Status */
624 #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
625 #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
626 #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
627 #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
628 #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
629 #define GSR_SCR (1 << 9) /* Secondary Codec Ready */
630 #define GSR_PCR (1 << 8) /* Primary Codec Ready */
631 #define GSR_MINT (1 << 7) /* Mic In Interrupt */
632 #define GSR_POINT (1 << 6) /* PCM Out Interrupt */
633 #define GSR_PIINT (1 << 5) /* PCM In Interrupt */
634 #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
635 #define GSR_MIINT (1 << 1) /* Modem In Interrupt */
636 #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
638 #define CAR __REG(0x40500020) /* CODEC Access Register */
639 #define CAR_CAIP (1 << 0) /* Codec Access In Progress */
641 #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
642 #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
644 #define MOCR __REG(0x40500100) /* Modem Out Control Register */
645 #define MOCR_FEIE (1 << 3) /* FIFO Error */
647 #define MICR __REG(0x40500108) /* Modem In Control Register */
648 #define MICR_FEIE (1 << 3) /* FIFO Error */
650 #define MOSR __REG(0x40500110) /* Modem Out Status Register */
651 #define MOSR_FIFOE (1 << 4) /* FIFO error */
653 #define MISR __REG(0x40500118) /* Modem In Status Register */
654 #define MISR_FIFOE (1 << 4) /* FIFO error */
656 #define MODR __REG(0x40500140) /* Modem FIFO Data Register */
658 #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
659 #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
660 #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
661 #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
665 * USB Device Controller
666 * PXA25x and PXA27x USB device controller registers are different.
668 #if defined(CONFIG_PXA25x)
670 #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
671 #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
672 #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
674 #define UDCCR __REG(0x40600000) /* UDC Control Register */
675 #define UDCCR_UDE (1 << 0) /* UDC enable */
676 #define UDCCR_UDA (1 << 1) /* UDC active */
677 #define UDCCR_RSM (1 << 2) /* Device resume */
678 #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
679 #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
680 #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
681 #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
682 #define UDCCR_REM (1 << 7) /* Reset interrupt mask */
684 #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
685 #define UDCCS0_OPR (1 << 0) /* OUT packet ready */
686 #define UDCCS0_IPR (1 << 1) /* IN packet ready */
687 #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
688 #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
689 #define UDCCS0_SST (1 << 4) /* Sent stall */
690 #define UDCCS0_FST (1 << 5) /* Force stall */
691 #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
692 #define UDCCS0_SA (1 << 7) /* Setup active */
694 /* Bulk IN - Endpoint 1,6,11 */
695 #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
696 #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
697 #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
699 #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
700 #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
701 #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
702 #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
703 #define UDCCS_BI_SST (1 << 4) /* Sent stall */
704 #define UDCCS_BI_FST (1 << 5) /* Force stall */
705 #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
707 /* Bulk OUT - Endpoint 2,7,12 */
708 #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
709 #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
710 #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
712 #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
713 #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
714 #define UDCCS_BO_DME (1 << 3) /* DMA enable */
715 #define UDCCS_BO_SST (1 << 4) /* Sent stall */
716 #define UDCCS_BO_FST (1 << 5) /* Force stall */
717 #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
718 #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
720 /* Isochronous IN - Endpoint 3,8,13 */
721 #define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
722 #define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
723 #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
725 #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
726 #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
727 #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
728 #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
729 #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
731 /* Isochronous OUT - Endpoint 4,9,14 */
732 #define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
733 #define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
734 #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
736 #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
737 #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
738 #define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
739 #define UDCCS_IO_DME (1 << 3) /* DMA enable */
740 #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
741 #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
743 /* Interrupt IN - Endpoint 5,10,15 */
744 #define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
745 #define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
746 #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
748 #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
749 #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
750 #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
751 #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
752 #define UDCCS_INT_SST (1 << 4) /* Sent stall */
753 #define UDCCS_INT_FST (1 << 5) /* Force stall */
754 #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
756 #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
757 #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
758 #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
759 #define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
760 #define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
761 #define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
762 #define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
763 #define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
764 #define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
765 #define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
766 #define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
767 #define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
768 #define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
769 #define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
770 #define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
771 #define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
772 #define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
773 #define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
774 #define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
775 #define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
776 #define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
777 #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
778 #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
779 #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
781 #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
783 #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
784 #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
785 #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
786 #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
787 #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
788 #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
789 #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
790 #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
792 #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
794 #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
795 #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
796 #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
797 #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
798 #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
799 #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
800 #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
801 #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
803 #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
805 #define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
806 #define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */
807 #define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */
808 #define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
809 #define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
810 #define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
811 #define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
812 #define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
814 #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
816 #define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
817 #define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
818 #define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
819 #define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
820 #define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
821 #define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
822 #define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
823 #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
825 #elif defined(CONFIG_PXA27X)||( CONFIG_CPU_MONAHANS)
827 #define UDCCR __REG(0x40600000) /* UDC Control Register */
828 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
829 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
830 Protocol Port Support */
831 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
833 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
835 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
836 #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
837 #define UDCCR_ACN_S 11
838 #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
839 #define UDCCR_AIN_S 8
840 #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
842 #define UDCCR_AAISN_S 5
843 #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
845 #define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
847 #define UDCCR_UDR (1 << 2) /* UDC Resume */
848 #define UDCCR_UDA (1 << 1) /* UDC Active */
849 #define UDCCR_UDE (1 << 0) /* UDC Enable */
851 #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
852 #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
853 #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
854 #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
856 #define UDC_INT_FIFOERROR (0x2)
857 #define UDC_INT_PACKETCMP (0x1)
859 #define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
860 #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
861 #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
862 #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
863 #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
864 #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
866 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
867 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
868 #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
869 #define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */
870 #define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */
871 #define UDCISR1_IRRU (1 << 29) /* IntEn - Resume */
872 #define UDCISR1_IRSU (1 << 28) /* IntEn - Suspend */
873 #define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */
875 #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
876 #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
877 #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
878 #define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
879 Rising Edge Interrupt Enable */
880 #define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
881 Falling Edge Interrupt Enable */
882 #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
884 #define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
886 #define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
888 #define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
890 #define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
892 #define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
894 #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
895 Edge Interrupt Enable */
896 #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
897 Edge Interrupt Enable */
898 #define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
900 #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
902 #define UDCOTGISR __REG(0x4060001C) /* UDC OTG Interrupt Status Register*/
903 #define UP2OCR __REG(0x40600020) /* Port 2 control register */
904 #define UP3OCR __REG(0x40600024) /* Port 3 control register */
906 #define UDCCSN(x) __REG2(0x40600100, (x) << 2)
907 #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
908 #define UDCCSR0_ACM (1 << 9) /* ACK control mode */
909 #define UDCCSR0_AREN (1 << 8) /* ACK response enable */
910 #define UDCCSR0_SA (1 << 7) /* Setup Active */
911 #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
912 #define UDCCSR0_FST (1 << 5) /* Force Stall */
913 #define UDCCSR0_SST (1 << 4) /* Sent Stall */
914 #define UDCCSR0_DME (1 << 3) /* DMA Enable */
915 #define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
916 #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
917 #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
919 #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
920 #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
921 #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
922 #define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
923 #define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
924 #define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
925 #define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
926 #define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
927 #define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
928 #define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
929 #define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
930 #define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
931 #define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
932 #define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
933 #define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
934 #define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
935 #define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
936 #define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
937 #define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
938 #define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
939 #define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
940 #define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
941 #define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
943 #define UDCCSR_DPE (1 << 9) /* Data Packet Error */
944 #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
945 #define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
946 #define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
947 #define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
948 #define UDCCSR_FST (1 << 5) /* Force STALL */
949 #define UDCCSR_SST (1 << 4) /* Sent STALL */
950 #define UDCCSR_DME (1 << 3) /* DMA Enable */
951 #define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
952 #define UDCCSR_PC (1 << 1) /* Packet Complete */
953 #define UDCCSR_FS (1 << 0) /* FIFO needs service */
955 #define UDCBCN(x) __REG2(0x40600200, (x)<<2)
956 #define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
957 #define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
958 #define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
959 #define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
960 #define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
961 #define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
962 #define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
963 #define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
964 #define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
965 #define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
966 #define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
967 #define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
968 #define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
969 #define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
970 #define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
971 #define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
972 #define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
973 #define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
974 #define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
975 #define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
976 #define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
977 #define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
978 #define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
979 #define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
981 #define UDCDN(x) __REG2(0x40600300, (x)<<2)
982 #define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
983 #define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
984 #define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
985 #define UDCDRA __REG(0x40600304) /* Data Register - EPA */
986 #define UDCDRB __REG(0x40600308) /* Data Register - EPB */
987 #define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
988 #define UDCDRD __REG(0x40600310) /* Data Register - EPD */
989 #define UDCDRE __REG(0x40600314) /* Data Register - EPE */
990 #define UDCDRF __REG(0x40600318) /* Data Register - EPF */
991 #define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
992 #define UDCDRH __REG(0x40600320) /* Data Register - EPH */
993 #define UDCDRI __REG(0x40600324) /* Data Register - EPI */
994 #define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
995 #define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
996 #define UDCDRL __REG(0x40600330) /* Data Register - EPL */
997 #define UDCDRM __REG(0x40600334) /* Data Register - EPM */
998 #define UDCDRN __REG(0x40600338) /* Data Register - EPN */
999 #define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
1000 #define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
1001 #define UDCDRR __REG(0x40600344) /* Data Register - EPR */
1002 #define UDCDRS __REG(0x40600348) /* Data Register - EPS */
1003 #define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
1004 #define UDCDRU __REG(0x40600350) /* Data Register - EPU */
1005 #define UDCDRV __REG(0x40600354) /* Data Register - EPV */
1006 #define UDCDRW __REG(0x40600358) /* Data Register - EPW */
1007 #define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
1009 #define UDCCN(x) __REG2(0x40600400, (x)<<2)
1010 #define UDCCRA __REG(0x40600404) /* Configuration register EPA */
1011 #define UDCCRB __REG(0x40600408) /* Configuration register EPB */
1012 #define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
1013 #define UDCCRD __REG(0x40600410) /* Configuration register EPD */
1014 #define UDCCRE __REG(0x40600414) /* Configuration register EPE */
1015 #define UDCCRF __REG(0x40600418) /* Configuration register EPF */
1016 #define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
1017 #define UDCCRH __REG(0x40600420) /* Configuration register EPH */
1018 #define UDCCRI __REG(0x40600424) /* Configuration register EPI */
1019 #define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
1020 #define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
1021 #define UDCCRL __REG(0x40600430) /* Configuration register EPL */
1022 #define UDCCRM __REG(0x40600434) /* Configuration register EPM */
1023 #define UDCCRN __REG(0x40600438) /* Configuration register EPN */
1024 #define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
1025 #define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
1026 #define UDCCRR __REG(0x40600444) /* Configuration register EPR */
1027 #define UDCCRS __REG(0x40600448) /* Configuration register EPS */
1028 #define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
1029 #define UDCCRU __REG(0x40600450) /* Configuration register EPU */
1030 #define UDCCRV __REG(0x40600454) /* Configuration register EPV */
1031 #define UDCCRW __REG(0x40600458) /* Configuration register EPW */
1032 #define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
1034 #define UDCCONR_CN (0x03 << 25) /* Configuration Number */
1035 #define UDCCONR_CN_S (25)
1036 #define UDCCONR_IN (0x07 << 22) /* Interface Number */
1037 #define UDCCONR_IN_S (22)
1038 #define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
1039 #define UDCCONR_AISN_S (19)
1040 #define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
1041 #define UDCCONR_EN_S (15)
1042 #define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
1043 #define UDCCONR_ET_S (13)
1044 #define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
1045 #define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
1046 #define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
1047 #define UDCCONR_ET_NU (0x00 << 13) /* Not used */
1048 #define UDCCONR_ED (1 << 12) /* Endpoint Direction */
1049 #define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
1050 #define UDCCONR_MPS_S (2)
1051 #define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
1052 #define UDCCONR_EE (1 << 0) /* Endpoint Enable */
1055 #define UDC_INT_FIFOERROR (0x2)
1056 #define UDC_INT_PACKETCMP (0x1)
1058 #define UDC_FNR_MASK (0x7ff)
1060 #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
1061 #define UDC_BCR_MASK (0x3ff)
1065 * Fast Infrared Communication Port
1068 #define FICP __REG(0x40800000) /* Start of FICP area */
1069 #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
1070 #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
1071 #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
1072 #define ICDR __REG(0x4080000c) /* ICP Data Register */
1073 #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
1074 #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
1076 #define ICCR0_AME (1 << 7) /* Adress match enable */
1077 #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
1078 #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
1079 #define ICCR0_RXE (1 << 4) /* Receive enable */
1080 #define ICCR0_TXE (1 << 3) /* Transmit enable */
1081 #define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
1082 #define ICCR0_LBM (1 << 1) /* Loopback mode */
1083 #define ICCR0_ITR (1 << 0) /* IrDA transmission */
1085 #ifdef CONFIG_PXA27X
1086 #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
1087 #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
1088 #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
1089 #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
1090 #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
1091 #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
1094 #ifdef CONFIG_PXA27X
1095 #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
1097 #define ICSR0_FRE (1 << 5) /* Framing error */
1098 #define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
1099 #define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
1100 #define ICSR0_RAB (1 << 2) /* Receiver abort */
1101 #define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
1102 #define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
1104 #define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
1105 #define ICSR1_CRE (1 << 5) /* CRC error */
1106 #define ICSR1_EOF (1 << 4) /* End of frame */
1107 #define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
1108 #define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
1109 #define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
1110 #define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
1117 #define RCNR __REG(0x40900000) /* RTC Count Register */
1118 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
1119 #define RTSR __REG(0x40900008) /* RTC Status Register */
1120 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
1121 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
1123 #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
1124 #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
1125 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
1126 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
1127 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
1128 #define RTSR_AL (1 << 0) /* RTC alarm detected */
1132 * OS Timer & Match Registers
1135 #define OSMR0 __REG(0x40A00000) /* */
1136 #define OSMR1 __REG(0x40A00004) /* */
1137 #define OSMR2 __REG(0x40A00008) /* */
1138 #define OSMR3 __REG(0x40A0000C) /* */
1139 #define OSMR4 __REG(0x40A00080) /* */
1140 #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
1141 #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
1142 #define OMCR4 __REG(0x40A000C0) /* */
1143 #define OSSR __REG(0x40A00014) /* OS Timer Status Register */
1144 #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
1145 #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
1147 #define OSSR_M4 (1 << 4) /* Match status channel 4 */
1148 #define OSSR_M3 (1 << 3) /* Match status channel 3 */
1149 #define OSSR_M2 (1 << 2) /* Match status channel 2 */
1150 #define OSSR_M1 (1 << 1) /* Match status channel 1 */
1151 #define OSSR_M0 (1 << 0) /* Match status channel 0 */
1153 #define OWER_WME (1 << 0) /* Watchdog Match Enable */
1155 #define OIER_E4 (1 << 4) /* Interrupt enable channel 4 */
1156 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
1157 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
1158 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
1159 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
1163 * Pulse Width Modulator
1166 #define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
1167 #define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
1168 #define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
1170 #define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
1171 #define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
1172 #define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
1176 * Interrupt Controller
1178 /* ICIP to ICPR can only be accessed by coprocessor */
1179 /* #ifndef CONFIG_CPU_MONAHANS*/
1180 #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
1181 #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
1182 #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
1183 #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
1184 #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
1185 /* #endif // CONFIG_CPU_MONAHANS */
1186 #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
1190 * General Purpose I/O
1193 #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
1194 #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
1195 #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
1197 #define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
1198 #define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
1199 #define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
1201 #define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
1202 #define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
1203 #define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
1205 #define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
1206 #define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
1207 #define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
1209 #define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
1210 #define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
1211 #define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
1213 #define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
1214 #define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
1215 #define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
1217 #define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
1218 #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
1219 #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
1221 #ifndef CONFIG_CPU_MONAHANS
1222 #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
1223 #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
1224 #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
1225 #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
1226 #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
1227 #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */
1228 #define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
1229 #define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
1232 #define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
1233 #define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
1234 #define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
1235 #define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
1236 #define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
1237 #define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
1238 #define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
1240 /* More handy macros. The argument is a literal GPIO number. */
1242 #define GPIO_bit(x) (1 << ((x) & 0x1f))
1244 #if defined (CONFIG_PXA27X) || (CONFIG_CPU_MONAHANS)
1246 /* Interrupt Controller */
1247 /* #ifndef CONFIG_CPU_MONAHANS */
1248 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
1249 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
1250 #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
1251 #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
1252 #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
1253 /* #endif //CONFIG_CPU_MONAHANS */
1255 #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
1256 #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
1257 #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
1258 #define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
1259 #define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
1260 #define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
1261 #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
1262 #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
1264 #define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
1265 #define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
1266 #define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
1267 #define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
1268 #define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
1269 #define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
1270 #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
1271 #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
1272 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
1274 #ifdef CONFIG_CPU_MONAHANS
1275 #define GSDR0 __REG(0x40E00400) /* Bit-wise Set of GPDR[31:0] */
1276 #define GSDR1 __REG(0x40E00404) /* Bit-wise Set of GPDR[63:32] */
1277 #define GSDR2 __REG(0x40E00408) /* Bit-wise Set of GPDR[95:64] */
1278 #define GSDR3 __REG(0x40E0040C) /* Bit-wise Set of GPDR[127:96] */
1280 #define GCDR0 __REG(0x40E00420) /* Bit-wise Clear of GPDR[31:0] */
1281 #define GCDR1 __REG(0x40E00424) /* Bit-wise Clear of GPDR[63:32] */
1282 #define GCDR2 __REG(0x40E00428) /* Bit-wise Clear of GPDR[95:64] */
1283 #define GCDR3 __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */
1285 #define GSRER0 __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */
1286 #define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
1287 #define GSRER2 __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */
1288 #define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
1290 #define GCRER0 __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */
1291 #define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
1292 #define GCRER2 __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */
1293 #define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
1295 #define GSFER0 __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */
1296 #define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
1297 #define GSFER2 __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */
1298 #define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
1300 #define GCFER0 __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */
1301 #define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
1302 #define GCFER2 __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */
1303 #define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
1305 #define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3)
1306 #define GCDR(x) __REG2(0x40300420, ((x) & 0x60) >> 3)
1311 #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
1312 #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
1313 #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
1314 #define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
1315 #define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
1316 #define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
1317 #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
1318 #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
1323 /* GPIO alternate function assignments */
1324 #ifndef CONFIG_CPU_MONAHANS /* Monahans has its different definition */
1326 #define GPIO1_RST 1 /* reset */
1327 #define GPIO6_MMCCLK 6 /* MMC Clock */
1328 #define GPIO7_48MHz 7 /* 48 MHz clock output */
1329 #define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */
1330 #define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */
1331 #define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */
1332 #define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */
1333 #define GPIO12_32KHz 12 /* 32 kHz out */
1334 #define GPIO13_MBGNT 13 /* memory controller grant */
1335 #define GPIO14_MBREQ 14 /* alternate bus master request */
1336 #define GPIO15_nCS_1 15 /* chip select 1 */
1337 #define GPIO16_PWM0 16 /* PWM0 output */
1338 #define GPIO17_PWM1 17 /* PWM1 output */
1339 #define GPIO18_RDY 18 /* Ext. Bus Ready */
1340 #define GPIO19_DREQ1 19 /* External DMA Request */
1341 #define GPIO20_DREQ0 20 /* External DMA Request */
1342 #define GPIO23_SCLK 23 /* SSP clock */
1343 #define GPIO24_SFRM 24 /* SSP Frame */
1344 #define GPIO25_STXD 25 /* SSP transmit */
1345 #define GPIO26_SRXD 26 /* SSP receive */
1346 #define GPIO27_SEXTCLK 27 /* SSP ext_clk */
1347 #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
1348 #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
1349 #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
1350 #define GPIO31_SYNC 31 /* AC97/I2S sync */
1351 #define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */
1352 #define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */
1353 #define GPIO33_nCS_5 33 /* chip select 5 */
1354 #define GPIO34_FFRXD 34 /* FFUART receive */
1355 #define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
1356 #define GPIO35_FFCTS 35 /* FFUART Clear to send */
1357 #define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
1358 #define GPIO37_FFDSR 37 /* FFUART data set ready */
1359 #define GPIO38_FFRI 38 /* FFUART Ring Indicator */
1360 #define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */
1361 #define GPIO39_FFTXD 39 /* FFUART transmit data */
1362 #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
1363 #define GPIO41_FFRTS 41 /* FFUART request to send */
1364 #define GPIO42_BTRXD 42 /* BTUART receive data */
1365 #define GPIO43_BTTXD 43 /* BTUART transmit data */
1366 #define GPIO44_BTCTS 44 /* BTUART clear to send */
1367 #define GPIO45_BTRTS 45 /* BTUART request to send */
1368 #define GPIO46_ICPRXD 46 /* ICP receive data */
1369 #define GPIO46_STRXD 46 /* STD_UART receive data */
1370 #define GPIO47_ICPTXD 47 /* ICP transmit data */
1371 #define GPIO47_STTXD 47 /* STD_UART transmit data */
1372 #define GPIO48_nPOE 48 /* Output Enable for Card Space */
1373 #define GPIO49_nPWE 49 /* Write Enable for Card Space */
1374 #define GPIO50_nPIOR 50 /* I/O Read for Card Space */
1375 #define GPIO51_nPIOW 51 /* I/O Write for Card Space */
1376 #define GPIO52_nPCE_1 52 /* Card Enable for Card Space */
1377 #define GPIO53_nPCE_2 53 /* Card Enable for Card Space */
1378 #define GPIO53_MMCCLK 53 /* MMC Clock */
1379 #define GPIO54_MMCCLK 54 /* MMC Clock */
1380 #define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */
1381 #define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27X) */
1382 #define GPIO55_nPREG 55 /* Card Address bit 26 */
1383 #define GPIO56_nPWAIT 56 /* Wait signal for Card Space */
1384 #define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */
1385 #define GPIO58_LDD_0 58 /* LCD data pin 0 */
1386 #define GPIO59_LDD_1 59 /* LCD data pin 1 */
1387 #define GPIO60_LDD_2 60 /* LCD data pin 2 */
1388 #define GPIO61_LDD_3 61 /* LCD data pin 3 */
1389 #define GPIO62_LDD_4 62 /* LCD data pin 4 */
1390 #define GPIO63_LDD_5 63 /* LCD data pin 5 */
1391 #define GPIO64_LDD_6 64 /* LCD data pin 6 */
1392 #define GPIO65_LDD_7 65 /* LCD data pin 7 */
1393 #define GPIO66_LDD_8 66 /* LCD data pin 8 */
1394 #define GPIO66_MBREQ 66 /* alternate bus master req */
1395 #define GPIO67_LDD_9 67 /* LCD data pin 9 */
1396 #define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */
1397 #define GPIO68_LDD_10 68 /* LCD data pin 10 */
1398 #define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */
1399 #define GPIO69_LDD_11 69 /* LCD data pin 11 */
1400 #define GPIO69_MMCCLK 69 /* MMC_CLK */
1401 #define GPIO70_LDD_12 70 /* LCD data pin 12 */
1402 #define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */
1403 #define GPIO71_LDD_13 71 /* LCD data pin 13 */
1404 #define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */
1405 #define GPIO72_LDD_14 72 /* LCD data pin 14 */
1406 #define GPIO72_32kHz 72 /* 32 kHz clock */
1407 #define GPIO73_LDD_15 73 /* LCD data pin 15 */
1408 #define GPIO73_MBGNT 73 /* Memory controller grant */
1409 #define GPIO74_LCD_FCLK 74 /* LCD Frame clock */
1410 #define GPIO75_LCD_LCLK 75 /* LCD line clock */
1411 #define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */
1412 #define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */
1413 #define GPIO78_nCS_2 78 /* chip select 2 */
1414 #define GPIO79_nCS_3 79 /* chip select 3 */
1415 #define GPIO80_nCS_4 80 /* chip select 4 */
1416 #define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */
1417 #define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */
1418 #define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */
1419 #define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */
1420 #define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */
1421 #define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */
1422 #define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */
1423 #define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */
1424 #define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */
1426 /* GPIO alternate function mode & direction */
1428 #define GPIO_IN 0x000
1429 #define GPIO_OUT 0x080
1430 #define GPIO_ALT_FN_1_IN 0x100
1431 #define GPIO_ALT_FN_1_OUT 0x180
1432 #define GPIO_ALT_FN_2_IN 0x200
1433 #define GPIO_ALT_FN_2_OUT 0x280
1434 #define GPIO_ALT_FN_3_IN 0x300
1435 #define GPIO_ALT_FN_3_OUT 0x380
1436 #define GPIO_MD_MASK_NR 0x07f
1437 #define GPIO_MD_MASK_DIR 0x080
1438 #define GPIO_MD_MASK_FN 0x300
1440 #define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)
1441 #define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)
1442 #define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT)
1443 #define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)
1444 #define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)
1445 #define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)
1446 #define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)
1447 #define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)
1448 #define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)
1449 #define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)
1450 #define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT)
1451 #define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)
1452 #define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)
1453 #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
1454 #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
1455 #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
1456 #define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT)
1457 #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
1458 #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
1459 #define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
1460 #define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
1461 #define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
1462 #define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN)
1463 #define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
1464 #define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
1465 #define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
1466 #define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
1467 #define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
1468 #define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
1469 #define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
1470 #define GPIO32_MMCCLK_MD ( 32 | GPIO_ALT_FN_2_OUT)
1471 #define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT)
1472 #define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
1473 #define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
1474 #define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
1475 #define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
1476 #define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
1477 #define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
1478 #define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
1479 #define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
1480 #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
1481 #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
1482 #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
1483 #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
1484 #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
1485 #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
1486 #define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
1487 #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
1488 #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
1489 #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
1490 #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
1491 #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
1492 #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
1493 #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
1494 #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
1495 #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
1496 #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
1497 #define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
1498 #define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
1499 #define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT)
1500 #define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
1501 #define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
1502 #define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
1503 #define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
1504 #define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
1505 #define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
1506 #define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)
1507 #define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)
1508 #define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)
1509 #define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)
1510 #define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)
1511 #define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)
1512 #define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)
1513 #define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)
1514 #define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)
1515 #define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)
1516 #define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)
1517 #define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)
1518 #define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)
1519 #define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)
1520 #define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)
1521 #define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)
1522 #define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)
1523 #define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)
1524 #define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)
1525 #define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)
1526 #define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)
1527 #define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)
1528 #define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)
1529 #define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)
1530 #define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)
1531 #define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)
1532 #define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT)
1533 #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
1534 #define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT)
1535 #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
1536 #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
1537 #define GPIO88_USBH1_PWR_MD (88 | GPIO_ALT_FN_1_IN)
1538 #define GPIO89_USBH1_PEN_MD (89 | GPIO_ALT_FN_2_OUT)
1539 #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
1540 #define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)
1541 #define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)
1542 #define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT)
1543 #define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT)
1544 #define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT)
1545 #define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT)
1546 #define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
1547 #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_OUT)
1548 #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)
1554 #ifdef CONFIG_CPU_MONAHANS
1556 #define ASCR __REG(0x40F40000) /* Application Subsystem Power Status/Control Register */
1557 #define ARSR __REG(0x40F40004) /* Application Subsystem Reset Status Register */
1558 #define AD3ER __REG(0x40F40008) /* Application Subsystem D3 state Wakeup Enable Register */
1559 #define AD3SR __REG(0x40F4000C) /* Application Subsystem D3 state Wakeup Status Register */
1560 #define AD2D0ER __REG(0x40F40010) /* Application Subsystem D2 to D0 state Wakeup Enable Register */
1561 #define AD2D0SR __REG(0x40F40014) /* Application Subsystem D2 to D0 state Wakeup Status Register */
1562 #define AD2D1ER __REG(0x40F40018) /* Application Subsystem D2 to D1 state Wakeup Enable Register */
1563 #define AD2D1SR __REG(0x40F4001C) /* Application Subsystem D2 to D1 state Wakeup Status Register */
1564 #define AD1D0ER __REG(0x40F40020) /* Application Subsystem D1 to D0 state Wakeup Enable Register */
1565 #define AD1D0SR __REG(0x40F40024) /* Application Subsystem D1 to D0 state Wakeup Status Register */
1566 #define ASDCNT __REG(0x40F40028) /* Application Subsystem SRAM Drowsy Count Register */
1567 #define AD3R __REG(0x40F40030) /* Application Subsystem D3 State Configuration Register */
1568 #define AD2R __REG(0x40F40034) /* Application Subsystem D2 State Configuration Register */
1569 #define AD1R __REG(0x40F40038) /* Application Subsystem D1 State Configuration Register */
1571 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */
1572 #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
1573 #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
1574 #define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
1575 #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
1576 #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
1577 #define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
1578 #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
1579 #define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
1580 #define PCMD(x) __REG(0x40F50110 + x*4)
1581 #define PCMD0 __REG(0x40F50110 + 0 * 4)
1582 #define PCMD1 __REG(0x40F50110 + 1 * 4)
1583 #define PCMD2 __REG(0x40F50110 + 2 * 4)
1584 #define PCMD3 __REG(0x40F50110 + 3 * 4)
1585 #define PCMD4 __REG(0x40F50110 + 4 * 4)
1586 #define PCMD5 __REG(0x40F50110 + 5 * 4)
1587 #define PCMD6 __REG(0x40F50110 + 6 * 4)
1588 #define PCMD7 __REG(0x40F50110 + 7 * 4)
1589 #define PCMD8 __REG(0x40F50110 + 8 * 4)
1590 #define PCMD9 __REG(0x40F50110 + 9 * 4)
1591 #define PCMD10 __REG(0x40F50110 + 10 * 4)
1592 #define PCMD11 __REG(0x40F50110 + 11 * 4)
1593 #define PCMD12 __REG(0x40F50110 + 12 * 4)
1594 #define PCMD13 __REG(0x40F50110 + 13 * 4)
1595 #define PCMD14 __REG(0x40F50110 + 14 * 4)
1596 #define PCMD15 __REG(0x40F50110 + 15 * 4)
1597 #define PCMD16 __REG(0x40F50110 + 16 * 4)
1598 #define PCMD17 __REG(0x40F50110 + 17 * 4)
1599 #define PCMD18 __REG(0x40F50110 + 18 * 4)
1600 #define PCMD19 __REG(0x40F50110 + 19 * 4)
1601 #define PCMD20 __REG(0x40F50110 + 20 * 4)
1602 #define PCMD21 __REG(0x40F50110 + 21 * 4)
1603 #define PCMD22 __REG(0x40F50110 + 22 * 4)
1604 #define PCMD23 __REG(0x40F50110 + 23 * 4)
1605 #define PCMD24 __REG(0x40F50110 + 24 * 4)
1606 #define PCMD25 __REG(0x40F50110 + 25 * 4)
1607 #define PCMD26 __REG(0x40F50110 + 26 * 4)
1608 #define PCMD27 __REG(0x40F50110 + 27 * 4)
1609 #define PCMD28 __REG(0x40F50110 + 28 * 4)
1610 #define PCMD29 __REG(0x40F50110 + 29 * 4)
1611 #define PCMD30 __REG(0x40F50110 + 30 * 4)
1612 #define PCMD31 __REG(0x40F50110 + 31 * 4)
1614 #define PCMD_MBC (1<<12)
1615 #define PCMD_DCE (1<<11)
1616 #define PCMD_LC (1<<10)
1617 #define PCMD_SQC (3<<8) /* only 00 and 01 are valid */
1619 #define PVCR_FVC (0x1 << 28)
1620 #define PVCR_VCSA (0x1<<14)
1621 #define PVCR_CommandDelay (0xf80)
1622 #define PVCR_ReadPointer (0x01f00000)
1623 #define PVCR_SlaveAddress (0x7f)
1627 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */
1628 #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
1629 #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
1630 #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
1631 #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
1632 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
1633 #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
1634 #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
1635 #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
1636 #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
1637 #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
1638 #define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
1639 #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
1641 #define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
1642 #define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */
1643 #define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */
1644 #define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */
1645 #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
1646 #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
1647 #define PCMD(x) __REG2(0x40F00080, (x)<<2)
1648 #define PCMD0 __REG(0x40F00080 + 0 * 4)
1649 #define PCMD1 __REG(0x40F00080 + 1 * 4)
1650 #define PCMD2 __REG(0x40F00080 + 2 * 4)
1651 #define PCMD3 __REG(0x40F00080 + 3 * 4)
1652 #define PCMD4 __REG(0x40F00080 + 4 * 4)
1653 #define PCMD5 __REG(0x40F00080 + 5 * 4)
1654 #define PCMD6 __REG(0x40F00080 + 6 * 4)
1655 #define PCMD7 __REG(0x40F00080 + 7 * 4)
1656 #define PCMD8 __REG(0x40F00080 + 8 * 4)
1657 #define PCMD9 __REG(0x40F00080 + 9 * 4)
1658 #define PCMD10 __REG(0x40F00080 + 10 * 4)
1659 #define PCMD11 __REG(0x40F00080 + 11 * 4)
1660 #define PCMD12 __REG(0x40F00080 + 12 * 4)
1661 #define PCMD13 __REG(0x40F00080 + 13 * 4)
1662 #define PCMD14 __REG(0x40F00080 + 14 * 4)
1663 #define PCMD15 __REG(0x40F00080 + 15 * 4)
1664 #define PCMD16 __REG(0x40F00080 + 16 * 4)
1665 #define PCMD17 __REG(0x40F00080 + 17 * 4)
1666 #define PCMD18 __REG(0x40F00080 + 18 * 4)
1667 #define PCMD19 __REG(0x40F00080 + 19 * 4)
1668 #define PCMD20 __REG(0x40F00080 + 20 * 4)
1669 #define PCMD21 __REG(0x40F00080 + 21 * 4)
1670 #define PCMD22 __REG(0x40F00080 + 22 * 4)
1671 #define PCMD23 __REG(0x40F00080 + 23 * 4)
1672 #define PCMD24 __REG(0x40F00080 + 24 * 4)
1673 #define PCMD25 __REG(0x40F00080 + 25 * 4)
1674 #define PCMD26 __REG(0x40F00080 + 26 * 4)
1675 #define PCMD27 __REG(0x40F00080 + 27 * 4)
1676 #define PCMD28 __REG(0x40F00080 + 28 * 4)
1677 #define PCMD29 __REG(0x40F00080 + 29 * 4)
1678 #define PCMD30 __REG(0x40F00080 + 30 * 4)
1679 #define PCMD31 __REG(0x40F00080 + 31 * 4)
1681 #define PCMD_MBC (1<<12)
1682 #define PCMD_DCE (1<<11)
1683 #define PCMD_LC (1<<10)
1684 /* FIXME: PCMD_SQC need be checked. */
1685 #define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
1686 bit 9 should be 0 all day. */
1687 #define PVCR_VCSA (0x1<<14)
1688 #define PVCR_CommandDelay (0xf80)
1689 #define PCFR_PI2C_EN (0x1 << 6)
1691 #define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
1692 #define PSSR_RDH (1 << 5) /* Read Disable Hold */
1693 #define PSSR_PH (1 << 4) /* Peripheral Control Hold */
1694 #define PSSR_VFS (1 << 2) /* VDD Fault Status */
1695 #define PSSR_BFS (1 << 1) /* Battery Fault Status */
1696 #define PSSR_SSS (1 << 0) /* Software Sleep Status */
1698 #define PCFR_RO (1 << 15) /* RDH Override */
1699 #define PCFR_PO (1 << 14) /* PH Override */
1700 #define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
1701 #define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
1702 #define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
1703 #define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
1704 #define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
1705 #define PCFR_DS (1 << 3) /* Deep Sleep Mode */
1706 #define PCFR_FS (1 << 2) /* Float Static Chip Selects */
1707 #define PCFR_FP (1 << 1) /* Float PCMCIA controls */
1708 #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
1710 #define RCSR_GPR (1 << 3) /* GPIO Reset */
1711 #define RCSR_SMR (1 << 2) /* Sleep Mode */
1712 #define RCSR_WDR (1 << 1) /* Watchdog Reset */
1713 #define RCSR_HWR (1 << 0) /* Hardware Reset */
1714 #endif /* CONFIG_CPU_MONAHANS */
1717 * SSP Serial Port Registers
1720 #define SSCR0 __REG(0x41000000) /* SSP Control Register 0 */
1721 #define SSCR1 __REG(0x41000004) /* SSP Control Register 1 */
1722 #define SSSR __REG(0x41000008) /* SSP Status Register */
1723 #define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */
1724 #define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
1726 #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
1727 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
1728 #define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
1729 #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
1730 #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
1731 #define SSCR0_National (0x2 << 4) /* National Microwire */
1732 #define SSCR0_ECS (1 << 6) /* External clock select */
1733 #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
1734 #define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
1735 #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
1737 #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
1738 #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
1739 #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
1740 #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
1741 #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
1742 #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
1743 #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
1744 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
1745 #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
1746 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
1748 #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
1749 #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
1750 #define SSSR_BSY (1 << 4) /* SSP Busy */
1751 #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
1752 #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
1753 #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
1757 * MultiMediaCard (MMC) controller
1760 #define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */
1761 #define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */
1762 #define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */
1763 #define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */
1764 #define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */
1765 #define MMC_RESTO __REG(0x41100014) /* Expected response time out */
1766 #define MMC_RDTO __REG(0x41100018) /* Expected data read time out */
1767 #define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */
1768 #define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */
1769 #define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */
1770 #define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */
1771 #define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */
1772 #define MMC_CMD __REG(0x41100030) /* Index of current command */
1773 #define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */
1774 #define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */
1775 #define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */
1776 #define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */
1777 #define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */
1780 * MultiMediaCard (MMC2) controller
1783 #define MMC2_STRPCL __REG_2(0x42000000) /* Control to start and stop MMC clock */
1784 #define MMC2_STAT __REG_2(0x42000004) /* MMC Status Register (read only) */
1785 #define MMC2_CLKRT __REG_2(0x42000008) /* MMC clock rate */
1786 #define MMC2_SPI __REG_2(0x4200000c) /* SPI mode control bits */
1787 #define MMC2_CMDAT __REG_2(0x42000010) /* Command/response/data sequence control */
1788 #define MMC2_RESTO __REG_2(0x42000014) /* Expected response time out */
1789 #define MMC2_RDTO __REG_2(0x42000018) /* Expected data read time out */
1790 #define MMC2_BLKLEN __REG_2(0x4200001c) /* Block length of data transaction */
1791 #define MMC2_NOB __REG_2(0x42000020) /* Number of blocks, for block mode */
1792 #define MMC2_PRTBUF __REG_2(0x42000024) /* Partial MMC_TXFIFO FIFO written */
1793 #define MMC2_I_MASK __REG_2(0x42000028) /* Interrupt Mask */
1794 #define MMC2_I_REG __REG_2(0x4200002c) /* Interrupt Register (read only) */
1795 #define MMC2_CMD __REG_2(0x42000030) /* Index of current command */
1796 #define MMC2_ARGH __REG_2(0x42000034) /* MSW part of the current command argument */
1797 #define MMC2_ARGL __REG_2(0x42000038) /* LSW part of the current command argument */
1798 #define MMC2_RES __REG_2(0x4200003c) /* Response FIFO (read only) */
1799 #define MMC2_RXFIFO __REG_2(0x42000040) /* Receive FIFO (read only) */
1800 #define MMC2_TXFIFO __REG_2(0x42000044) /* Transmit FIFO (write only) */
1805 #if defined(CONFIG_CPU_MONAHANS)
1806 #define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
1807 #define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
1808 #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
1809 #define CKENA __REG(0x4134000C) /* A Clock Enable Register */
1810 #define CKENB __REG(0x41340010) /* B Clock Enable Register */
1811 #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
1813 #define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */
1814 #define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */
1815 #define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */
1816 #define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */
1817 #define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */
1818 #define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1819 #define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */
1820 #define ACCR_XPDIS (1 << 31)
1821 #define ACCR_SPDIS (1 << 30)
1822 #define ACCR_13MEND1 (1 << 27)
1823 #define ACCR_D0CS (1 << 26)
1824 #define ACCR_13MEND2 (1 << 21)
1825 #define ACCR_PCCE (1 << 11)
1827 #define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */
1828 #define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */
1829 #define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */
1830 #define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */
1831 #define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */
1832 #define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */
1833 #define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */
1834 #define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */
1835 #define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */
1836 #define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */
1837 #define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */
1838 #define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */
1839 #define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */
1840 #define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */
1841 #define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */
1842 #define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */
1843 #define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */
1844 #define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */
1845 #define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */
1846 #define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */
1847 #define CKENA_9_SMC (1 << 9) /* Static Memory Controller */
1848 #define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */
1849 #define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */
1850 #define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */
1851 #define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */
1852 #define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */
1853 #define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */
1854 #define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */
1856 #define CKENB_8_1WIRE ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */
1857 #define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */
1858 #define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */
1859 #define CKENB_4_I2C ((1 << 4) + 32) /* I2C Unit Clock Enable */
1860 #define CKENB_1_PWM1 ((1 << 1) + 32) /* PWM2 & PWM3 Clock Enable */
1861 #define CKENB_0_PWM0 ((1 << 0) + 32) /* PWM0 & PWM1 Clock Enable */
1863 #else /* if defined CONFIG_CPU_MONAHANS */
1865 #define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
1866 #define CKEN __REG(0x41300004) /* Clock Enable Register */
1867 #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
1868 #define CCSR __REG(0x4130000C) /* Core Clock Status Register */
1870 #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1871 #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
1872 #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
1874 #define CKEN31_AC97 (1 << 31)
1875 #define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */
1876 #define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
1877 #define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */
1878 #define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */
1879 #define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
1880 #define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
1881 #define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
1882 #define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */
1883 #define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
1884 #define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
1885 #define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
1886 #define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
1887 #define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
1888 #define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
1889 #define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
1890 #define CKEN9_OSTIMER (1 << 9) /* OS Timer Unit Clock Enable */
1891 #define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
1892 #define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
1893 #define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
1894 #define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
1895 #define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
1896 #define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
1897 #define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */
1898 #define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
1899 #define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
1900 #define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
1902 #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
1903 #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
1905 #if !defined(CONFIG_PXA27X)
1906 #define CCCR_L09 (0x1F)
1907 #define CCCR_L27 (0x1)
1908 #define CCCR_L32 (0x2)
1909 #define CCCR_L36 (0x3)
1910 #define CCCR_L40 (0x4)
1911 #define CCCR_L45 (0x5)
1913 #define CCCR_M1 (0x1 << 5)
1914 #define CCCR_M2 (0x2 << 5)
1915 #define CCCR_M4 (0x3 << 5)
1917 #define CCCR_N10 (0x2 << 7)
1918 #define CCCR_N15 (0x3 << 7)
1919 #define CCCR_N20 (0x4 << 7)
1920 #define CCCR_N25 (0x5 << 7)
1921 #define CCCR_N30 (0x6 << 7)
1924 #endif /* CONFIG_CPU_MONAHANS */
1929 #ifndef CONFIG_CPU_MONAHANS
1931 #define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */
1932 #define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */
1933 #define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */
1934 #define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */
1935 #define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
1936 #define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
1937 #define LCSR __REG(0x44000038) /* LCD Controller Status Register */
1938 #define LCSR0 __REG(0x44000038) /* LCD Controller Status Register */
1939 #define LCSR1 __REG(0x44000034) /* LCD Controller Status Register */
1940 #define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */
1941 #define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
1942 #define TMEDCR __REG(0x44000044) /* TMED Control Register */
1944 #define LCCR3_1BPP (0 << 24)
1945 #define LCCR3_2BPP (1 << 24)
1946 #define LCCR3_4BPP (2 << 24)
1947 #define LCCR3_8BPP (3 << 24)
1948 #define LCCR3_16BPP (4 << 24)
1949 #define LCCR3_18BPP (6 << 24) /* packed pixel format */
1950 #define LCCR3_19BPP (8 << 24) /* packed pixel format */
1951 #define LCCR3_24BPP (9 << 24)
1952 #define LCCR3_25BPP (10<< 24)
1954 #define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
1955 #define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
1956 #define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */
1957 #define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */
1958 #define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */
1959 #define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */
1960 #define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */
1961 #define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */
1965 #define LCCR0 __REG_2(0x44000000) /* LCD Controller Control Register 0 */
1966 #define LCCR1 __REG_2(0x44000004) /* LCD Controller Control Register 1 */
1967 #define LCCR2 __REG_2(0x44000008) /* LCD Controller Control Register 2 */
1968 #define LCCR3 __REG_2(0x4400000C) /* LCD Controller Control Register 3 */
1969 #define DFBR0 __REG_2(0x44000020) /* DMA Channel 0 Frame Branch Register */
1970 #define DFBR1 __REG_2(0x44000024) /* DMA Channel 1 Frame Branch Register */
1971 #define LCSR __REG_2(0x44000038) /* LCD Controller Status Register */
1972 #define LCSR1 __REG_2(0x44000034) /* LCD Controller Status Register */
1973 #define LIIDR __REG_2(0x4400003C) /* LCD Controller Interrupt ID Register */
1974 #define TMEDRGBR __REG_2(0x44000040) /* TMED RGB Seed Register */
1975 #define TMEDCR __REG_2(0x44000044) /* TMED Control Register */
1977 #define LCCR3_1BPP (0 << 24)
1978 #define LCCR3_2BPP (1 << 24)
1979 #define LCCR3_4BPP (2 << 24)
1980 #define LCCR3_8BPP (3 << 24)
1981 #define LCCR3_16BPP (4 << 24)
1982 #define LCCR3_18BPP (6 << 24) /* packed pixel format */
1983 #define LCCR3_19BPP (8 << 24) /* packed pixel format */
1984 #define LCCR3_24BPP (9 << 24)
1985 #define LCCR3_25BPP (10<< 24)
1987 #define FDADR0 __REG_2(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
1988 #define FSADR0 __REG_2(0x44000204) /* DMA Channel 0 Frame Source Address Register */
1989 #define FIDR0 __REG_2(0x44000208) /* DMA Channel 0 Frame ID Register */
1990 #define LDCMD0 __REG_2(0x4400020C) /* DMA Channel 0 Command Register */
1991 #define FDADR1 __REG_2(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */
1992 #define FSADR1 __REG_2(0x44000214) /* DMA Channel 1 Frame Source Address Register */
1993 #define FIDR1 __REG_2(0x44000218) /* DMA Channel 1 Frame ID Register */
1994 #define LDCMD1 __REG_2(0x4400021C) /* DMA Channel 1 Command Register */
1998 #define LCCR0_ENB (1 << 0) /* LCD Controller enable */
1999 #define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */
2000 #define LCCR0_Color (LCCR0_CMS*0) /* Color display */
2001 #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
2002 #define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display */
2004 #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
2005 #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
2007 #define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
2008 #define LCCR0_SFM (1 << 4) /* Start of frame mask */
2009 #define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
2010 #define LCCR0_EFM (1 << 6) /* End of Frame mask */
2011 #define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
2012 #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
2013 #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
2014 #define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome */
2016 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
2018 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
2020 #define LCCR0_DIS (1 << 10) /* LCD Disable */
2021 #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
2022 #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
2023 #define LCCR0_PDD_S 12
2024 #define LCCR0_BM (1 << 20) /* Branch mask */
2025 #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
2026 #define LCCR0_LCDT (1 << 22) /* LCD Panel Type */
2027 #define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */
2028 #define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */
2030 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
2031 #define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
2032 (((Pixel) - 1) << FShft (LCCR1_PPL))
2034 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
2035 #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
2036 /* pulse Width [1..64 Tpix] */ \
2037 (((Tpix) - 1) << FShft (LCCR1_HSW))
2039 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
2040 /* count - 1 [Tpix] */
2041 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
2042 /* [1..256 Tpix] */ \
2043 (((Tpix) - 1) << FShft (LCCR1_ELW))
2045 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
2046 /* Wait count - 1 [Tpix] */
2047 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
2048 /* [1..256 Tpix] */ \
2049 (((Tpix) - 1) << FShft (LCCR1_BLW))
2052 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
2053 #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
2054 (((Line) - 1) << FShft (LCCR2_LPP))
2056 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
2057 /* Width - 1 [Tln] (L_FCLK) */
2058 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
2059 /* Width [1..64 Tln] */ \
2060 (((Tln) - 1) << FShft (LCCR2_VSW))
2062 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
2064 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
2065 /* [0..255 Tln] */ \
2066 ((Tln) << FShft (LCCR2_EFW))
2068 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
2069 /* Wait count [Tln] */
2070 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
2071 /* [0..255 Tln] */ \
2072 ((Tln) << FShft (LCCR2_BFW))
2075 #define LCCR3_PCD (0xff) /* Pixel clock divisor */
2076 #define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */
2077 #define LCCR3_ACB_S 8
2080 #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
2081 #define LCCR3_API_S 16
2082 #define LCCR3_VSP (1 << 20) /* vertical sync polarity */
2083 #define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
2084 #define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */
2085 #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
2086 #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
2088 #define LCCR3_OEP (1 << 23) /* Output Enable Polarity (L_BIAS, */
2089 /* active display mode) */
2090 #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
2091 #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
2094 #define LCCR3_BPP (7 << 24) /* bits per pixel */
2095 #define LCCR3_BPP_S 24
2097 #define LCCR3_DPC (1 << 27) /* double pixel clock mode */
2100 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
2101 #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \
2102 (((Div) << FShft (LCCR3_PCD)))
2105 #define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
2106 #define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \
2107 (((Bpp) << FShft (LCCR3_BPP)))
2109 #define LCCR3_ACB Fld (8, 8) /* AC Bias */
2110 #define LCCR3_Acb(Acb) /* BAC Bias */ \
2111 (((Acb) << FShft (LCCR3_ACB)))
2113 #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
2114 /* pulse active High */
2115 #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
2117 #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
2119 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
2122 #define LCSR_LDD (1 << 0) /* LCD Disable Done */
2123 #define LCSR_SOF (1 << 1) /* Start of frame */
2124 #define LCSR_BER (1 << 2) /* Bus error */
2125 #define LCSR_ABC (1 << 3) /* AC Bias count */
2126 #define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
2127 #define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
2128 #define LCSR_OU (1 << 6) /* output FIFO underrun */
2129 #define LCSR_QD (1 << 7) /* quick disable */
2130 #define LCSR_EOF (1 << 8) /* end of frame */
2131 #define LCSR_BS (1 << 9) /* branch status */
2132 #define LCSR_SINT (1 << 10) /* subsequent interrupt */
2134 #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
2136 #define LCSR_LDD (1 << 0) /* LCD Disable Done */
2137 #define LCSR_SOF (1 << 1) /* Start of frame */
2138 #define LCSR_BER (1 << 2) /* Bus error */
2139 #define LCSR_ABC (1 << 3) /* AC Bias count */
2140 #define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
2141 #define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
2142 #define LCSR_OU (1 << 6) /* output FIFO underrun */
2143 #define LCSR_QD (1 << 7) /* quick disable */
2144 #define LCSR_EOF (1 << 8) /* end of frame */
2145 #define LCSR_BS (1 << 9) /* branch status */
2146 #define LCSR_SINT (1 << 10) /* subsequent interrupt */
2148 #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
2150 /* Overlay1 & Overlay2 & Hardware Cursor */
2151 #define LCSR1_SOF1 (1 << 0)
2152 #define LCSR1_SOF2 (1 << 1)
2153 #define LCSR1_SOF3 (1 << 2)
2154 #define LCSR1_SOF4 (1 << 3)
2155 #define LCSR1_SOF5 (1 << 4)
2156 #define LCSR1_SOF6 (1 << 5)
2158 #define LCSR1_EOF1 (1 << 8)
2159 #define LCSR1_EOF2 (1 << 9)
2160 #define LCSR1_EOF3 (1 << 10)
2161 #define LCSR1_EOF4 (1 << 11)
2162 #define LCSR1_EOF5 (1 << 12)
2163 #define LCSR1_EOF6 (1 << 13)
2165 #define LCSR1_BS1 (1 << 16)
2166 #define LCSR1_BS2 (1 << 17)
2167 #define LCSR1_BS3 (1 << 18)
2168 #define LCSR1_BS4 (1 << 19)
2169 #define LCSR1_BS5 (1 << 20)
2170 #define LCSR1_BS6 (1 << 21)
2172 #define LCSR1_IU2 (1 << 25)
2173 #define LCSR1_IU3 (1 << 26)
2174 #define LCSR1_IU4 (1 << 27)
2175 #define LCSR1_IU5 (1 << 28)
2176 #define LCSR1_IU6 (1 << 29)
2178 #define LDCMD_SOFINT (1 << 22)
2179 #define LDCMD_EOFINT (1 << 21)
2181 #define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */
2182 #define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */
2184 #define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */
2185 #define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */
2186 #define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */
2187 #define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */
2188 #define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */
2189 #define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */
2191 #define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */
2192 #define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */
2193 #define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */
2194 #define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */
2195 #define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */
2196 #define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */
2198 #define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */
2199 #define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */
2200 #define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */
2201 #define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */
2202 #define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */
2203 #define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */
2205 #define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */
2206 #define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */
2207 #define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */
2208 #define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */
2209 #define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */
2210 #define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */
2212 #define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */
2213 #define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */
2214 #define CCR_CEN (1<<31) /* Enable bit for Cursor */
2217 #define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */
2218 #define LCCR5 __REG(0x44000014) /* LCD Controller Control Register 5 */
2219 #define FBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
2220 #define FBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
2221 #define FBR2 __REG(0x44000028) /* DMA Channel 2 Frame Branch Register */
2222 #define FBR3 __REG(0x4400002C) /* DMA Channel 3 Frame Branch Register */
2223 #define FBR4 __REG(0x44000030) /* DMA Channel 4 Frame Branch Register */
2224 #define FDADR2 __REG(0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */
2225 #define FSADR2 __REG(0x44000224) /* DMA Channel 2 Frame Source Address Register */
2226 #define FIDR2 __REG(0x44000228) /* DMA Channel 2 Frame ID Register */
2227 #define LDCMD2 __REG(0x4400022C) /* DMA Channel 2 Command Register */
2228 #define FDADR3 __REG(0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */
2229 #define FSADR3 __REG(0x44000234) /* DMA Channel 3 Frame Source Address Register */
2230 #define FIDR3 __REG(0x44000238) /* DMA Channel 3 Frame ID Register */
2231 #define LDCMD3 __REG(0x4400023C) /* DMA Channel 3 Command Register */
2232 #define FDADR4 __REG(0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */
2233 #define FSADR4 __REG(0x44000244) /* DMA Channel 4 Frame Source Address Register */
2234 #define FIDR4 __REG(0x44000248) /* DMA Channel 4 Frame ID Register */
2235 #define LDCMD4 __REG(0x4400024C) /* DMA Channel 4 Command Register */
2236 #define FDADR5 __REG(0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */
2237 #define FSADR5 __REG(0x44000254) /* DMA Channel 5 Frame Source Address Register */
2238 #define FIDR5 __REG(0x44000258) /* DMA Channel 5 Frame ID Register */
2239 #define LDCMD5 __REG(0x4400025C) /* DMA Channel 5 Command Register */
2241 #define OVL1C1 __REG(0x44000050) /* Overlay 1 Control Register 1 */
2242 #define OVL1C2 __REG(0x44000060) /* Overlay 1 Control Register 2 */
2243 #define OVL2C1 __REG(0x44000070) /* Overlay 2 Control Register 1 */
2244 #define OVL2C2 __REG(0x44000080) /* Overlay 2 Control Register 2 */
2245 #define CCR __REG(0x44000090) /* Cursor Control Register */
2247 #define FBR5 __REG(0x44000110) /* DMA Channel 5 Frame Branch Register */
2248 #define FBR6 __REG(0x44000114) /* DMA Channel 6 Frame Branch Register */
2251 * Touch screen interface
2253 #ifdef CONFIG_CPU_MONAHANS
2254 #define ADCD __REG(0x41c00000) /*Analog-to-Digital Converter Data register*/
2255 #define ADCS __REG(0x41c00004) /*Analog-to-Digital Converter Setup register*/
2256 #define ADCE __REG(0x41c00008) /*Analog-to-Digital Converter Enable register*/
2263 #ifndef CONFIG_CPU_MONAHANS
2264 #define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */
2265 #define MDCNFG_OFFSET 0x0
2266 #define MDREFR_OFFSET 0x4
2267 #define MSC0_OFFSET 0x8
2268 #define MSC1_OFFSET 0xC
2269 #define MSC2_OFFSET 0x10
2270 #define MECR_OFFSET 0x14
2271 #define SXLCR_OFFSET 0x18
2272 #define SXCNFG_OFFSET 0x1C
2273 #define FLYCNFG_OFFSET 0x20
2274 #define SXMRS_OFFSET 0x24
2275 #define MCMEM0_OFFSET 0x28
2276 #define MCMEM1_OFFSET 0x2C
2277 #define MCATT0_OFFSET 0x30
2278 #define MCATT1_OFFSET 0x34
2279 #define MCIO0_OFFSET 0x38
2280 #define MCIO1_OFFSET 0x3C
2281 #define MDMRS_OFFSET 0x40
2283 #define MDCNFG __REG((0x48000000) /* SDRAM Configuration Register 0 */
2284 #define MDCNFG_DE0 0x00000001
2285 #define MDCNFG_DE1 0x00000002
2286 #define MDCNFG_DE2 0x00010000
2287 #define MDCNFG_DE3 0x00020000
2288 #define MDCNFG_DWID0 0x00000004
2291 #ifdef CONFIG_CPU_MONAHANS
2292 /* Static Memory Controller Registers */
2293 #define MSC0 __REG_2(0x4A000008) /* Static Memory Control Register 0 */
2294 #define MSC1 __REG_2(0x4A00000C) /* Static Memory Control Register 1 */
2295 #define MECR __REG_2(0x4A000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
2296 #define SXCNFG __REG_2(0x4A00001C) /* Synchronous Static Memory Control Register */
2297 #define MCMEM0 __REG_2(0x4A000028) /* Card interface Common Memory Space Socket 0 Timing */
2298 #define MCATT0 __REG_2(0x4A000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
2299 #define MCIO0 __REG_2(0x4A000038) /* Card interface I/O Space Socket 0 Timing Configuration */
2300 #define MEMCLKCFG __REG_2(0x4A000068) /* SCLK speed configuration */
2301 #define CSADRCFG0 __REG_2(0x4A000080) /* Address Configuration for chip select 0 */
2302 #define CSADRCFG1 __REG_2(0x4A000084) /* Address Configuration for chip select 1 */
2303 #define CSADRCFG2 __REG_2(0x4A000088) /* Address Configuration for chip select 2 */
2304 #define CSADRCFG3 __REG_2(0x4A00008C) /* Address Configuration for chip select 3 */
2305 #define CSADRCFG_P __REG_2(0x4A000090) /* Address Configuration for pcmcia card interface */
2306 #define CSMSADRCFG __REG_2(0x4A0000A0) /* Master Address Configuration Register */
2308 /* Dynamic Memory Controller Registers */
2309 #define MDCNFG __REG_2(0x48100000) /* SDRAM Configuration Register 0 */
2310 #define MDREFR __REG_2(0x48100004) /* SDRAM Refresh Control Register */
2311 #define FLYCNFG __REG_2(0x48100020) /* Fly-by DMA DVAL[1:0] polarities */
2312 #define MDMRS __REG_2(0x48100040) /* MRS value to be written to SDRAM */
2313 #define DDR_SCAL __REG_2(0x48100050) /* Software Delay Line Calibration/Configuration for external DDR memory. */
2314 #define DDR_HCAL __REG_2(0x48100060) /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
2315 #define DMCIER __REG_2(0x48100070) /* Dynamic MC Interrupt Enable Register. */
2316 #define DMCISR __REG_2(0x48100078) /* Dynamic MC Interrupt Status Register. */
2317 #define DDR_DLS __REG_2(0x48100080) /* DDR Delay Line Value Status register for external DDR memory. */
2318 #define EMPI __REG_2(0x48100090) /* EMPI Control Register */
2319 #define RCOMP __REG_2(0x48100100)
2320 #define PAD_MA __REG_2(0x48100110)
2321 #define PAD_MDMSB __REG_2(0x48100114)
2322 #define PAD_MDLSB __REG_2(0x48100118)
2323 #define PAD_DMEM __REG_2(0x4810011c)
2324 #define PAD_SDCLK __REG_2(0x48100120)
2325 #define PAD_SDCS __REG_2(0x48100124)
2326 #define PAD_SMEM __REG_2(0x48100128)
2327 #define PAD_SCLK __REG_2(0x4810012C)
2330 /* Data Flash Controller Registers */
2332 #define NDCR __REG_2(0x43100000) /* Data Flash Control register */
2333 #define NDTR0CS0 __REG_2(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
2334 #define NDTR0CS1 __REG_2(0x43100008) /* Data Controller Timing Parameter 0 Register for ND_nCS1 */
2335 #define NDTR1CS0 __REG_2(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
2336 #define NDTR1CS1 __REG_2(0x43100010) /* Data Controller Timing Parameter 1 Register for ND_nCS1 */
2337 #define NDSR __REG_2(0x43100014) /* Data Controller Status Register */
2338 #define NDPCR __REG_2(0x43100018) /* Data Controller Page Count Register */
2339 #define NDBDR0 __REG_2(0x4310001C) /* Data Controller Bad Block Register 0 */
2340 #define NDBDR1 __REG_2(0x43100020) /* Data Controller Bad Block Register 1 */
2341 #define NDDB __REG_2(0x43100040) /* Data Controller Data Buffer */
2342 #define NDCB0 __REG_2(0x43100048) /* Data Controller Command Buffer0 */
2343 #define NDCB1 __REG_2(0x4310004C) /* Data Controller Command Buffer1 */
2344 #define NDCB2 __REG_2(0x43100050) /* Data Controller Command Buffer2 */
2346 #define NDCR_SPARE_EN (0x1<<31)
2347 #define NDCR_ECC_EN (0x1<<30)
2348 #define NDCR_DMA_EN (0x1<<29)
2349 #define NDCR_ND_RUN (0x1<<28)
2350 #define NDCR_DWIDTH_C (0x1<<27)
2351 #define NDCR_DWIDTH_M (0x1<<26)
2352 #define NDCR_PAGE_SZ (0x3<<24)
2353 #define NDCR_NCSX (0x1<<23)
2354 #define NDCR_ND_MODE (0x3<<21)
2355 #define NDCR_NAND_MODE 0x0
2356 #define NDCR_CLR_PG_CNT (0x1<<20)
2357 #define NDCR_CLR_ECC (0x1<<19)
2358 #define NDCR_RD_ID_CNT (0x7<<16)
2359 #define NDCR_RA_START (0x1<<15)
2360 #define NDCR_PG_PER_BLK (0x1<<14)
2361 #define NDCR_ND_ARB_EN (0x1<<12)
2363 #define NDSR_RDY (0x1<<11)
2364 #define NDSR_CS0_PAGED (0x1<<10)
2365 #define NDSR_CS1_PAGED (0x1<<9)
2366 #define NDSR_CS0_CMDD (0x1<<8)
2367 #define NDSR_CS1_CMDD (0x1<<7)
2368 #define NDSR_CS0_BBD (0x1<<6)
2369 #define NDSR_CS1_BBD (0x1<<5)
2370 #define NDSR_BDERR (0x1<<4)
2371 #define NDSR_SBERR (0x1<<3)
2372 #define NDSR_WRDREQ (0x1<<2)
2373 #define NDSR_RDDREQ (0x1<<1)
2374 #define NDSR_WRCMDREQ (0x1)
2376 #define NDCB0_AUTO_RS (0x1<<25)
2377 #define NDCB0_CSEL (0x1<<24)
2378 #define NDCB0_CMD_TYPE (0x7<<21)
2379 #define NDCB0_NC (0x1<<20)
2380 #define NDCB0_DBC (0x1<<19)
2381 #define NDCB0_ADDR_CYC (0x7<<16)
2382 #define NDCB0_CMD2 (0xff<<8)
2383 #define NDCB0_CMD1 (0xff)
2384 #define MCMEM(s) MCMEM0
2385 #define MCATT(s) MCATT0
2386 #define MCIO(s) MCIO0
2387 #define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
2388 #else /* CONFIG_CPU_MONAHANS */
2390 /* mk: defined @2253 #define MDCNFG __REG(0x48000000) /\* SDRAM Configuration Register 0 *\/ */
2391 #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
2392 #define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
2393 #define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
2394 #define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
2395 #define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
2396 #define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
2397 #define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
2398 #define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
2399 #define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
2400 #define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
2401 #define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
2402 #define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
2403 #define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
2404 #define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
2405 #define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
2406 #define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
2409 * More handy macros for PCMCIA
2411 * Arg is socket number
2413 #define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
2414 #define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
2415 #define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
2417 /* MECR register defines */
2418 #define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
2419 #define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
2421 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
2422 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
2423 #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
2424 #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
2425 #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
2426 #define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
2427 #define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
2428 #define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
2429 #define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
2430 #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
2431 #define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
2432 #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
2433 #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
2436 #ifdef CONFIG_PXA27X
2438 #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
2440 #define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
2441 #define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
2442 #define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
2443 #define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
2444 #define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
2445 #define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
2446 #define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
2447 #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
2448 #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
2453 #define KPC __REG(0x41500000) /* Keypad Interface Control register */
2454 #define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */
2455 #define KPREC __REG(0x41500010) /* Keypad Interface Rotary Encoder register */
2456 #define KPMK __REG(0x41500018) /* Keypad Interface Matrix Key register */
2457 #define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */
2458 #define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
2459 #define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
2460 #define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
2461 #define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
2462 #define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
2464 #define KPC_AS (0x1 << 30) /* Automatic Scan bit */
2465 #define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
2466 #define KPC_MI (0x1 << 22) /* Matrix interrupt bit */
2467 #define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */
2468 #define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */
2469 #define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */
2470 #define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */
2471 #define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */
2472 #define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */
2473 #define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */
2474 #define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */
2475 #define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */
2476 #define KPC_MS_ALL (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7)
2477 #define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */
2478 #define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */
2479 #define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Keypad Debounce Select */
2480 #define KPC_DI (0x1 << 5) /* Direct key interrupt bit */
2481 #define KPC_RE_ZERO_DEB (0x1 << 4) /* Rotary Encoder Zero Debounce */
2482 #define KPC_REE1 (0x1 << 3) /* Rotary Encoder1 Enable */
2483 #define KPC_REE0 (0x1 << 2) /* Rotary Encoder0 Enable */
2484 #define KPC_DE (0x1 << 1) /* Direct Keypad Enable */
2485 #define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */
2487 #define KPDK_DKP (0x1 << 31)
2488 #define KPDK_DK7 (0x1 << 7)
2489 #define KPDK_DK6 (0x1 << 6)
2490 #define KPDK_DK5 (0x1 << 5)
2491 #define KPDK_DK4 (0x1 << 4)
2492 #define KPDK_DK3 (0x1 << 3)
2493 #define KPDK_DK2 (0x1 << 2)
2494 #define KPDK_DK1 (0x1 << 1)
2495 #define KPDK_DK0 (0x1 << 0)
2497 #define KPREC_OF1 (0x1 << 31)
2498 #define kPREC_UF1 (0x1 << 30)
2499 #define KPREC_OF0 (0x1 << 15)
2500 #define KPREC_UF0 (0x1 << 14)
2502 #define KPMK_MKP (0x1 << 31)
2503 #define KPAS_SO (0x1 << 31)
2504 #define KPASMKPx_SO (0x1 << 31)
2507 * UHC: USB Host Controller (OHCI-like) register definitions
2509 #define UHC_BASE_PHYS (0x4C000000)
2510 #define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
2511 #define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
2512 #define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
2513 #define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
2514 #define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
2515 #define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
2516 #define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
2517 #define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
2518 #define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
2519 #define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
2520 #define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
2521 #define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
2522 #define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
2523 #define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
2524 #define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
2525 #define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
2526 #define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
2527 #define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
2528 #define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
2529 #define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
2530 #define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
2531 #define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
2532 #define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
2533 #define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
2534 #define UHCRHPS(x) __REG2(0x4C000050, (x)<<2)
2536 #define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
2537 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
2538 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
2539 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
2540 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
2541 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
2542 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
2543 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
2544 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
2545 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
2547 #define UHCHR __REG(0x4C000064) /* UHC Reset Register */
2548 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
2549 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
2550 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
2551 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */
2552 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
2553 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
2554 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
2555 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
2556 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
2557 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
2558 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
2560 #define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
2561 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
2562 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
2563 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
2564 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
2565 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
2567 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
2568 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
2570 #define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
2572 /* Camera Interface */
2573 #define CICR0 __REG(0x50000000)
2574 #define CICR1 __REG(0x50000004)
2575 #define CICR2 __REG(0x50000008)
2576 #define CICR3 __REG(0x5000000C)
2577 #define CICR4 __REG(0x50000010)
2578 #define CISR __REG(0x50000014)
2579 #define CIFR __REG(0x50000018)
2580 #define CITOR __REG(0x5000001C)
2581 #define CIBR0 __REG(0x50000028)
2582 #define CIBR1 __REG(0x50000030)
2583 #define CIBR2 __REG(0x50000038)
2585 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
2586 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
2587 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
2588 #define CICR0_ENB (1 << 28) /* Camera interface enable */
2589 #define CICR0_DIS (1 << 27) /* Camera interface disable */
2590 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
2591 #define CICR0_TOM (1 << 9) /* Time-out mask */
2592 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
2593 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
2594 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
2595 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
2596 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
2597 #define CICR0_CDM (1 << 3) /* Disable-done mask */
2598 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
2599 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
2600 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
2602 #define CICR1_TBIT (1 << 31) /* Transparency bit */
2603 #define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */
2604 #define CICR1_PPL (0x3f << 15) /* Pixels per line mask */
2605 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
2606 #define CICR1_RGB_F (1 << 11) /* RGB format */
2607 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
2608 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
2609 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
2610 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
2611 #define CICR1_DW (0x7 << 0) /* Data width mask */
2613 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
2615 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
2617 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
2618 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
2620 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
2623 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
2625 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
2627 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
2628 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
2630 #define CICR3_LPF (0x3ff << 0) /* Lines per frame mask */
2632 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
2633 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
2634 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
2635 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
2636 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
2637 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
2638 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
2639 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
2641 #define CISR_FTO (1 << 15) /* FIFO time-out */
2642 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
2643 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
2644 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
2645 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
2646 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
2647 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
2648 #define CISR_EOL (1 << 8) /* End of line */
2649 #define CISR_PAR_ERR (1 << 7) /* Parity error */
2650 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
2651 #define CISR_SOF (1 << 5) /* Start of frame */
2652 #define CISR_CDD (1 << 4) /* Camera interface disable done */
2653 #define CISR_EOF (1 << 3) /* End of frame */
2654 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
2655 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
2656 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
2658 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
2659 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
2660 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
2661 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
2662 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
2663 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
2664 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
2665 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
2667 #define SRAM_SIZE 0x40000 /* 4x64K */
2669 #define SRAM_MEM_PHYS 0x5C000000
2671 #define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */
2672 #define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */
2674 #define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */
2675 #define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */
2676 #define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */
2677 #define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */
2679 #define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */
2680 #define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */
2681 #define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */
2682 #define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */
2684 #define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */
2685 #define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */
2686 #define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */
2687 #define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */
2689 #define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */
2690 #define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */
2691 #define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */
2692 #define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */
2694 #define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */
2695 #define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */
2696 #define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */
2697 #define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */
2699 #define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */
2701 #define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */
2702 #define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */
2703 #define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */
2705 #define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */
2706 #define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */
2707 #define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */
2709 #define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */
2710 #define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */
2711 #define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */
2713 #define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */
2714 #define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */
2715 #define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */
2720 #ifdef CONFIG_CPU_MONAHANS
2722 #define SRAM_SIZE 0xC0000 /* 4x64K */
2723 #define SRAM_MEM_PHYS 0x5C000000
2725 /* GPIO alternate function assignments */
2726 #define APPS_PAD_BASE 0x40E10000
2728 /* MFPR regsiter locations for each pin */
2729 #define GPIO0_MFPR (APPS_PAD_BASE + 0x0124)
2730 #define GPIO1_MFPR (APPS_PAD_BASE + 0x0128)
2731 #define GPIO2_MFPR (APPS_PAD_BASE + 0x012C)
2732 #define GPIO3_MFPR (APPS_PAD_BASE + 0x0130)
2733 #define GPIO4_MFPR (APPS_PAD_BASE + 0x0134)
2734 #define GPIO5_MFPR (APPS_PAD_BASE + 0x028C)
2735 #define GPIO6_MFPR (APPS_PAD_BASE + 0x0290)
2736 #define GPIO7_MFPR (APPS_PAD_BASE + 0x0294)
2737 #define GPIO8_MFPR (APPS_PAD_BASE + 0x0298)
2738 #define GPIO9_MFPR (APPS_PAD_BASE + 0x029C)
2739 #define GPIO10_MFPR (APPS_PAD_BASE + 0x0458)
2740 #define GPIO11_MFPR (APPS_PAD_BASE + 0x02A0)
2741 #define GPIO12_MFPR (APPS_PAD_BASE + 0x02A4)
2742 #define GPIO13_MFPR (APPS_PAD_BASE + 0x02A8)
2743 #define GPIO14_MFPR (APPS_PAD_BASE + 0x02AC)
2744 #define GPIO15_MFPR (APPS_PAD_BASE + 0x02B0)
2745 #define GPIO16_MFPR (APPS_PAD_BASE + 0x02B4)
2746 #define GPIO17_MFPR (APPS_PAD_BASE + 0x02B8)
2747 #define GPIO18_MFPR (APPS_PAD_BASE + 0x02BC)
2748 #define GPIO19_MFPR (APPS_PAD_BASE + 0x02C0)
2749 #define GPIO20_MFPR (APPS_PAD_BASE + 0x02C4)
2750 #define GPIO21_MFPR (APPS_PAD_BASE + 0x02C8)
2751 #define GPIO22_MFPR (APPS_PAD_BASE + 0x02CC)
2752 #define GPIO23_MFPR (APPS_PAD_BASE + 0x02D0)
2753 #define GPIO24_MFPR (APPS_PAD_BASE + 0x02D4)
2754 #define GPIO25_MFPR (APPS_PAD_BASE + 0x02D8)
2755 #define GPIO26_MFPR (APPS_PAD_BASE + 0x02DC)
2756 #define GPIO27_MFPR (APPS_PAD_BASE + 0x0400)
2757 #define GPIO28_MFPR (APPS_PAD_BASE + 0x0404)
2758 #define GPIO29_MFPR (APPS_PAD_BASE + 0x0408)
2759 #define GPIO30_MFPR (APPS_PAD_BASE + 0x040C)
2760 #define GPIO31_MFPR (APPS_PAD_BASE + 0x0410)
2761 #define GPIO32_MFPR (APPS_PAD_BASE + 0x0414)
2762 #define GPIO33_MFPR (APPS_PAD_BASE + 0x0418)
2763 #define GPIO34_MFPR (APPS_PAD_BASE + 0x041C)
2764 #define GPIO35_MFPR (APPS_PAD_BASE + 0x0420)
2765 #define GPIO36_MFPR (APPS_PAD_BASE + 0x0424)
2766 #define GPIO37_MFPR (APPS_PAD_BASE + 0x0428)
2767 #define GPIO38_MFPR (APPS_PAD_BASE + 0x042C)
2768 #define GPIO39_MFPR (APPS_PAD_BASE + 0x0430)
2769 #define GPIO40_MFPR (APPS_PAD_BASE + 0x0434)
2770 #define GPIO41_MFPR (APPS_PAD_BASE + 0x0438)
2771 #define GPIO42_MFPR (APPS_PAD_BASE + 0x043C)
2772 #define GPIO43_MFPR (APPS_PAD_BASE + 0x0440)
2773 #define GPIO44_MFPR (APPS_PAD_BASE + 0x0444)
2774 #define GPIO45_MFPR (APPS_PAD_BASE + 0x0448)
2775 #define GPIO46_MFPR (APPS_PAD_BASE + 0x044C)
2776 #define GPIO47_MFPR (APPS_PAD_BASE + 0x0450)
2777 #define GPIO48_MFPR (APPS_PAD_BASE + 0x0454)
2778 #define GPIO49_MFPR (APPS_PAD_BASE + 0x045C)
2779 #define GPIO50_MFPR (APPS_PAD_BASE + 0x0460)
2780 #define GPIO51_MFPR (APPS_PAD_BASE + 0x0464)
2781 #define GPIO52_MFPR (APPS_PAD_BASE + 0x0468)
2782 #define GPIO53_MFPR (APPS_PAD_BASE + 0x046C)
2783 #define GPIO54_MFPR (APPS_PAD_BASE + 0x0470)
2784 #define GPIO55_MFPR (APPS_PAD_BASE + 0x0474)
2785 #define GPIO56_MFPR (APPS_PAD_BASE + 0x0478)
2786 #define GPIO57_MFPR (APPS_PAD_BASE + 0x047C)
2787 #define GPIO58_MFPR (APPS_PAD_BASE + 0x0480)
2788 #define GPIO59_MFPR (APPS_PAD_BASE + 0x0484)
2789 #define GPIO60_MFPR (APPS_PAD_BASE + 0x0488)
2790 #define GPIO61_MFPR (APPS_PAD_BASE + 0x048C)
2791 #define GPIO62_MFPR (APPS_PAD_BASE + 0x0490)
2792 #define GPIO63_MFPR (APPS_PAD_BASE + 0x04B4)
2793 #define GPIO64_MFPR (APPS_PAD_BASE + 0x04B8)
2794 #define GPIO65_MFPR (APPS_PAD_BASE + 0x04BC)
2795 #define GPIO66_MFPR (APPS_PAD_BASE + 0x04C0)
2796 #define GPIO67_MFPR (APPS_PAD_BASE + 0x04C4)
2797 #define GPIO68_MFPR (APPS_PAD_BASE + 0x04C8)
2798 #define GPIO69_MFPR (APPS_PAD_BASE + 0x04CC)
2799 #define GPIO70_MFPR (APPS_PAD_BASE + 0x04D0)
2800 #define GPIO71_MFPR (APPS_PAD_BASE + 0x04D4)
2801 #define GPIO72_MFPR (APPS_PAD_BASE + 0x04D8)
2802 #define GPIO73_MFPR (APPS_PAD_BASE + 0x04DC)
2803 #define GPIO74_MFPR (APPS_PAD_BASE + 0x04F0)
2804 #define GPIO75_MFPR (APPS_PAD_BASE + 0x04F4)
2805 #define GPIO76_MFPR (APPS_PAD_BASE + 0x04F8)
2806 #define GPIO77_MFPR (APPS_PAD_BASE + 0x04FC)
2807 #define GPIO78_MFPR (APPS_PAD_BASE + 0x0500)
2808 #define GPIO79_MFPR (APPS_PAD_BASE + 0x0504)
2809 #define GPIO80_MFPR (APPS_PAD_BASE + 0x0508)
2810 #define GPIO81_MFPR (APPS_PAD_BASE + 0x050C)
2811 #define GPIO82_MFPR (APPS_PAD_BASE + 0x0510)
2812 #define GPIO83_MFPR (APPS_PAD_BASE + 0x0514)
2813 #define GPIO84_MFPR (APPS_PAD_BASE + 0x0518)
2814 #define GPIO85_MFPR (APPS_PAD_BASE + 0x051C)
2815 #define GPIO86_MFPR (APPS_PAD_BASE + 0x0520)
2816 #define GPIO87_MFPR (APPS_PAD_BASE + 0x0524)
2817 #define GPIO88_MFPR (APPS_PAD_BASE + 0x0528)
2818 #define GPIO89_MFPR (APPS_PAD_BASE + 0x052C)
2819 #define GPIO90_MFPR (APPS_PAD_BASE + 0x0530)
2820 #define GPIO91_MFPR (APPS_PAD_BASE + 0x0534)
2821 #define GPIO92_MFPR (APPS_PAD_BASE + 0x0538)
2822 #define GPIO93_MFPR (APPS_PAD_BASE + 0x053C)
2823 #define GPIO94_MFPR (APPS_PAD_BASE + 0x0540)
2824 #define GPIO95_MFPR (APPS_PAD_BASE + 0x0544)
2825 #define GPIO96_MFPR (APPS_PAD_BASE + 0x0548)
2826 #define GPIO97_MFPR (APPS_PAD_BASE + 0x054C)
2827 #define GPIO98_MFPR (APPS_PAD_BASE + 0x0550)
2828 #define GPIO99_MFPR (APPS_PAD_BASE + 0x0600)
2829 #define GPIO100_MFPR (APPS_PAD_BASE + 0x0604)
2830 #define GPIO101_MFPR (APPS_PAD_BASE + 0x0608)
2831 #define GPIO102_MFPR (APPS_PAD_BASE + 0x060C)
2832 #define GPIO103_MFPR (APPS_PAD_BASE + 0x0610)
2833 #define GPIO104_MFPR (APPS_PAD_BASE + 0x0614)
2834 #define GPIO105_MFPR (APPS_PAD_BASE + 0x0618)
2835 #define GPIO106_MFPR (APPS_PAD_BASE + 0x061C)
2836 #define GPIO107_MFPR (APPS_PAD_BASE + 0x0620)
2837 #define GPIO108_MFPR (APPS_PAD_BASE + 0x0624)
2838 #define GPIO109_MFPR (APPS_PAD_BASE + 0x0628)
2839 #define GPIO110_MFPR (APPS_PAD_BASE + 0x062C)
2840 #define GPIO111_MFPR (APPS_PAD_BASE + 0x0630)
2841 #define GPIO112_MFPR (APPS_PAD_BASE + 0x0634)
2842 #define GPIO113_MFPR (APPS_PAD_BASE + 0x0638)
2843 #define GPIO114_MFPR (APPS_PAD_BASE + 0x063C)
2844 #define GPIO115_MFPR (APPS_PAD_BASE + 0x0640)
2845 #define GPIO116_MFPR (APPS_PAD_BASE + 0x0644)
2846 #define GPIO117_MFPR (APPS_PAD_BASE + 0x0648)
2847 #define GPIO118_MFPR (APPS_PAD_BASE + 0x064C)
2848 #define GPIO119_MFPR (APPS_PAD_BASE + 0x0650)
2849 #define GPIO120_MFPR (APPS_PAD_BASE + 0x0654)
2850 #define GPIO121_MFPR (APPS_PAD_BASE + 0x0658)
2851 #define GPIO122_MFPR (APPS_PAD_BASE + 0x065C)
2852 #define GPIO123_MFPR (APPS_PAD_BASE + 0x0660)
2853 #define GPIO124_MFPR (APPS_PAD_BASE + 0x0664)
2854 #define GPIO125_MFPR (APPS_PAD_BASE + 0x0668)
2855 #define GPIO126_MFPR (APPS_PAD_BASE + 0x066C)
2856 #define GPIO127_MFPR (APPS_PAD_BASE + 0x0670)
2857 #define GPIO0_2_MFPR (APPS_PAD_BASE + 0x0674) /* MFPR for GPIO0_2 */
2858 #define GPIO1_2_MFPR (APPS_PAD_BASE + 0x0678) /* MFPR for GPIO1_2 */
2859 #define GPIO2_2_MFPR (APPS_PAD_BASE + 0x067C) /* MFPR for GPIO2_2 */
2860 #define GPIO3_2_MFPR (APPS_PAD_BASE + 0x0680) /* MFPR for GPIO3_2 */
2861 #define GPIO4_2_MFPR (APPS_PAD_BASE + 0x0684) /* MFPR for GPIO4_2 */
2862 #define GPIO5_2_MFPR (APPS_PAD_BASE + 0x0688) /* MFPR for GPIO5_2 */
2863 #define GPIO6_2_MFPR (APPS_PAD_BASE + 0x0494) /* MFPR for GPIO6_2 */
2864 #define GPIO7_2_MFPR (APPS_PAD_BASE + 0x0498) /* MFPR for GPIO7_2 */
2865 #define GPIO8_2_MFPR (APPS_PAD_BASE + 0x049C) /* MFPR for GPIO8_2 */
2866 #define GPIO9_2_MFPR (APPS_PAD_BASE + 0x04A0) /* MFPR for GPIO9_2 */
2867 #define GPIO10_2_MFPR (APPS_PAD_BASE + 0x04A4) /* MFPR for GPIO10_2 */
2868 #define GPIO11_2_MFPR (APPS_PAD_BASE + 0x04A8) /* MFPR for GPIO11_2 */
2869 #define GPIO12_2_MFPR (APPS_PAD_BASE + 0x04AC) /* MFPR for GPIO12_2 */
2870 #define GPIO13_2_MFPR (APPS_PAD_BASE + 0x04B0) /* MFPR for GPIO13_2 */
2871 #define GPIO14_2_MFPR (APPS_PAD_BASE + 0x04E0) /* MFPR for GPIO14_2 */
2872 #define GPIO15_2_MFPR (APPS_PAD_BASE + 0x04E4) /* MFPR for GPIO15_2 */
2873 #define GPIO16_2_MFPR (APPS_PAD_BASE + 0x04E8) /* MFPR for GPIO16_2 */
2874 #define GPIO17_2_MFPR (APPS_PAD_BASE + 0x04EC) /* MFPR for GPIO17_2 */
2876 #define PIN_nXCVREN_MFPR (APPS_PAD_BASE + 0x0138)
2877 #define PIN_ND_CLE_MFPR (APPS_PAD_BASE + 0x0204)
2878 #define PIN_DF_nADV1_ALE_MFPR (APPS_PAD_BASE + 0x0208)
2879 #define PIN_DF_SCLK_S_MFPR (APPS_PAD_BASE + 0x020C)
2880 #define PIN_DF_SCLK_E_MFPR (APPS_PAD_BASE + 0x0210)
2881 #define PIN_nBE0_MFPR (APPS_PAD_BASE + 0x0214)
2882 #define PIN_nBE1_MFPR (APPS_PAD_BASE + 0x0218)
2883 #define PIN_DF_nADV2_ALE_MFPR (APPS_PAD_BASE + 0x021C)
2884 #define PIN_DF_INT_RnB_MFPR (APPS_PAD_BASE + 0x0220)
2885 #define PIN_DF_nCS0_MFPR (APPS_PAD_BASE + 0x0224)
2886 #define PIN_DF_nCS1_MFPR (APPS_PAD_BASE + 0x0228)
2887 #define PIN_DF_nWE_MFPR (APPS_PAD_BASE + 0x022C)
2888 #define PIN_DF_nRE_nOE_MFPR (APPS_PAD_BASE + 0x0230)
2889 #define PIN_nLUA_MFPR (APPS_PAD_BASE + 0x0234)
2890 #define PIN_nLLA_MFPR (APPS_PAD_BASE + 0x0238)
2891 #define PIN_DF_ADDR0_MFPR (APPS_PAD_BASE + 0x023C)
2892 #define PIN_DF_ADDR1_MFPR (APPS_PAD_BASE + 0x0240)
2893 #define PIN_DF_ADDR2_MFPR (APPS_PAD_BASE + 0x0244)
2894 #define PIN_DF_ADDR3_MFPR (APPS_PAD_BASE + 0x0248)
2895 #define PIN_DF_IO0_MFPR (APPS_PAD_BASE + 0x024C)
2896 #define PIN_DF_IO1_MFPR (APPS_PAD_BASE + 0x0254)
2897 #define PIN_DF_IO2_MFPR (APPS_PAD_BASE + 0x025C)
2898 #define PIN_DF_IO3_MFPR (APPS_PAD_BASE + 0x0264)
2899 #define PIN_DF_IO4_MFPR (APPS_PAD_BASE + 0x026C)
2900 #define PIN_DF_IO5_MFPR (APPS_PAD_BASE + 0x0274)
2901 #define PIN_DF_IO6_MFPR (APPS_PAD_BASE + 0x027C)
2902 #define PIN_DF_IO7_MFPR (APPS_PAD_BASE + 0x0294)
2903 #define PIN_DF_IO8_MFPR (APPS_PAD_BASE + 0x0298)
2904 #define PIN_DF_IO9_MFPR (APPS_PAD_BASE + 0x029C)
2905 #define PIN_DF_IO10_MFPR (APPS_PAD_BASE + 0x0260)
2906 #define PIN_DF_IO11_MFPR (APPS_PAD_BASE + 0x0268)
2907 #define PIN_DF_IO12_MFPR (APPS_PAD_BASE + 0x0270)
2908 #define PIN_DF_IO13_MFPR (APPS_PAD_BASE + 0x0278)
2909 #define PIN_DF_IO14_MFPR (APPS_PAD_BASE + 0x0280)
2910 #define PIN_DF_IO15_MFPR (APPS_PAD_BASE + 0x0288)
2912 /* GPIO mode encodings: Direction, Number, MFPR value */
2914 #define MFPR_PS 0x80000000 /* MFPR bit 15: pull_sel */
2915 #define MFPR_PUE 0x40000000 /* MFPR bit 14: pullup_en */
2916 #define MFPR_PDE 0x20000000 /* MFPR bit 13: pulldown_en */
2917 #define MFPR_DF1 0x00000000 /* MFPR bit 12-10: drive, fast 1ma */
2918 #define MFPR_DF2 0x04000000 /* MFPR bit 12-10: drive, fast 2ma */
2919 #define MFPR_DF3 0x08000000 /* MFPR bit 12-10: drive, fast 3ma */
2920 #define MFPR_DF4 0x0c000000 /* MFPR bit 12-10: drive, fast 4ma */
2921 #define MFPR_DS6 0x10000000 /* MFPR bit 12-10: drive, slow 6ma */
2922 #define MFPR_DF6 0x14000000 /* MFPR bit 12-10: drive, fast 6ma */
2923 #define MFPR_DS10 0x18000000 /* MFPR bit 12-10: drive, slow 10ma */
2924 #define MFPR_DF10 0x1c000000 /* MFPR bit 12-10: drive, fast 10ma */
2925 #define MFPR_SS 0x02000000 /* MFPR bit 9: sleep_sel */
2926 #define MFPR_SD 0x01000000 /* MFPR bit 8: sleep_data */
2927 #define MFPR_SE 0x00800000 /* MFPR bit 7: sleep_oe */
2928 #define MFPR_EC 0x00400000 /* MFPR bit 6: edge_clear */
2929 #define MFPR_EF 0x00200000 /* MFPR bit 5: edge_fall_en */
2930 #define MFPR_ER 0x00100000 /* MFPR bit 4: edge_rise_en */
2931 #define MFPR_ALT0 0x00000000 /* MFPR bit 2-0: alternate function 0 */
2932 #define MFPR_ALT1 0x00010000 /* MFPR bit 2-0: alternate function 1 */
2933 #define MFPR_ALT2 0x00020000 /* MFPR bit 2-0: alternate function 2 */
2934 #define MFPR_ALT3 0x00030000 /* MFPR bit 2-0: alternate function 3 */
2935 #define MFPR_ALT4 0x00040000 /* MFPR bit 2-0: alternate function 4 */
2936 #define MFPR_ALT5 0x00050000 /* MFPR bit 2-0: alternate function 5 */
2937 #define MFPR_ALT6 0x00060000 /* MFPR bit 2-0: alternate function 6 */
2938 #define MFPR_ALT7 0x00070000 /* MFPR bit 2-0: alternate function 7 */
2939 #define GPIO_MD_MASK_NR 0x0000ffff
2940 #define GPIO_MD_MASK_MFPR 0xffff0000
2941 #define GPIO_MD_SHIFT_MFPR 16
2943 #define GPIO3_NCS_2 (3|MFPR_DS6|MFPR_ALT1)
2944 #define GPIO11_PWM0 (11|MFPR_DS6|MFPR_ALT1)
2945 #define GPIO12_PWM1 (12|MFPR_DS6|MFPR_ALT1)
2946 #define GPIO14_LCD_BACKLIGHT_PWM3 (14|MFPR_DS6|MFPR_ALT1)
2948 #define GPIO18_MMC_DAT_0 (18|MFPR_DS6|MFPR_ALT4)
2949 #define GPIO19_MMC_DAT_1 (19|MFPR_DS6|MFPR_ALT4)
2950 #define GPIO20_MMC_DAT_2 (20|MFPR_DS6|MFPR_ALT4)
2951 #define GPIO21_MMC_DAT_3 (21|MFPR_DS6|MFPR_ALT4)
2952 #define GPIO22_CLK_MMC (22|MFPR_DS6|MFPR_ALT4)
2953 #define GPIO23_MMC_CMD (23|MFPR_DS6|MFPR_ALT4)
2954 #define GPIO24_MMC2_DAT_0 (24|MFPR_DS6|MFPR_ALT4)
2955 #define GPIO25_MMC2_DAT_1 (25|MFPR_DS6|MFPR_ALT4)
2956 #define GPIO26_MMC2_DAT_2 (26|MFPR_DS6|MFPR_ALT4)
2957 #define GPIO27_MMC2_DAT_3 (27|MFPR_DS6|MFPR_ALT4)
2958 #define GPIO28_CLK_MMC2 (28|MFPR_DS6|MFPR_ALT4)
2959 #define GPIO29_MMC2_CMD (29|MFPR_DS6|MFPR_ALT4)
2960 #define GPIO30_CLK_MMC (30|MFPR_DS6|MFPR_ALT4)
2961 #define GPIO31_MMC_CMD (31|MFPR_DS6|MFPR_ALT4)
2962 #define GPIO34_AC97_SYSCLK (34|MFPR_DF6|MFPR_ALT1)
2963 #define GPIO35_AC97_SDATA_IN0 (35|MFPR_DF6|MFPR_ALT1)
2964 #define GPIO36_AC97_SDATA_IN1 (36|MFPR_DF6|MFPR_ALT1)
2965 #define GPIO37_AC97_SDATA_OUT (37|MFPR_DF6|MFPR_ALT1)
2966 #define GPIO38_AC97_SYNC (38|MFPR_DF6|MFPR_ALT1)
2967 #define GPIO39_AC97_BITCLK (39|MFPR_DF6|MFPR_ALT1)
2968 #define GPIO40_AC97_RESET_N (40|MFPR_DF6|MFPR_ALT1)
2969 #define GPIO41_FF_UART1_RXD (41|MFPR_DS6|MFPR_ALT2)
2970 #define GPIO42_FF_UART1_TXD (42|MFPR_DS6|MFPR_ALT2)
2971 #define GPIO43_FF_UART1_CTS (43|MFPR_DS6|MFPR_ALT2)
2972 #define GPIO44_FF_UART1_DCD (44|MFPR_DF10|MFPR_SD|MFPR_ALT2)
2973 #define GPIO45_FF_UART1_DSR (45|MFPR_DS6|MFPR_ALT2)
2974 #define GPIO46_FF_UART1_RI (46|MFPR_DS6|MFPR_ALT2)
2975 #define GPIO47_FF_UART1_DTR (47|MFPR_DS6|MFPR_ALT2)
2976 #define GPIO48_FF_UART1_RTS (48|MFPR_DS6|MFPR_ALT2)
2977 #define GPIO49_CIF_DD0 (49|MFPR_DF6|MFPR_ALT1)
2978 #define GPIO50_CIF_DD1 (50|MFPR_DF6|MFPR_ALT1)
2979 #define GPIO51_CIF_DD2 (51|MFPR_DF6|MFPR_ALT1)
2980 #define GPIO52_CIF_DD3 (52|MFPR_DF6|MFPR_ALT1)
2981 #define GPIO53_CIF_DD4 (53|MFPR_DF6|MFPR_ALT1)
2982 #define GPIO54_CIF_DD5 (54|MFPR_DF6|MFPR_ALT1)
2983 #define GPIO55_CIF_DD6 (55|MFPR_DF6|MFPR_ALT1)
2984 #define GPIO56_CIF_DD7 (56|MFPR_DF6|MFPR_ALT1)
2985 #define GPIO57_CIF_DD8 (57|MFPR_DF6|MFPR_ALT1)
2986 #define GPIO58_CIF_DD9 (58|MFPR_DF6|MFPR_ALT1)
2987 #define GPIO59_CIF_MCLK (59|MFPR_DF6|MFPR_ALT1)
2988 #define GPIO60_CIF_PCLK (60|MFPR_DF6|MFPR_ALT1)
2989 #define GPIO61_CIF_LV (61|MFPR_DF6|MFPR_ALT1)
2990 #define GPIO62_CIF_FV (62|MFPR_DF6|MFPR_ALT1)
2991 #define GPIO63_LCD_LDD_8 (63|MFPR_DF6|MFPR_ALT1)
2992 #define GPIO64_LCD_LDD_9 (64|MFPR_DF6|MFPR_ALT1)
2993 #define GPIO65_LCD_LDD_10 (65|MFPR_DF6|MFPR_ALT1)
2994 #define GPIO66_LCD_LDD_11 (66|MFPR_DF6|MFPR_ALT1)
2995 #define GPIO67_LCD_LDD_12 (67|MFPR_DF6|MFPR_ALT1)
2996 #define GPIO68_LCD_LDD_13 (68|MFPR_DF6|MFPR_ALT1)
2997 #define GPIO69_LCD_LDD_14 (69|MFPR_DF6|MFPR_ALT1)
2998 #define GPIO70_LCD_LDD_15 (70|MFPR_DF6|MFPR_ALT1)
2999 #define GPIO71_LCD_LDD_16 (71|MFPR_DF6|MFPR_ALT1)
3000 #define GPIO72_LCD_LDD_17 (72|MFPR_DF6|MFPR_ALT1)
3001 #define GPIO73_LCD_CS (73|MFPR_DF6|MFPR_ALT2)
3002 #define GPIO74_LCD_VSYNC (74|MFPR_DF6|MFPR_ALT2)
3003 #define GPIO89_SSP3_SCLK (89|MFPR_DS6|MFPR_ALT1)
3004 #define GPIO90_SSP3_SFRM (90|MFPR_DS6|MFPR_ALT1)
3005 #define GPIO91_SSP3_TXD (91|MFPR_DS6|MFPR_ALT1)
3006 #define GPIO92_SSP3_RXD (92|MFPR_DS6|MFPR_ALT1)
3007 #define GPIO93_SSP4_SCLK (93|MFPR_DS6|MFPR_ALT1)
3008 #define GPIO94_SSP4_SFRM (94|MFPR_DS6|MFPR_ALT1)
3009 #define GPIO95_SSP4_TXD (95|MFPR_DS6|MFPR_ALT1)
3010 #define GPIO96_SSP4_RXD (96|MFPR_DS6|MFPR_ALT1)
3011 #define GPIO100_USB_P2_4 (100|MFPR_DS6|MFPR_ALT2)
3012 #define GPIO101_USB_P2_8 (101|MFPR_DS6|MFPR_ALT2)
3013 #define GPIO102_USB_P2_3 (102|MFPR_DS6|MFPR_ALT2)
3014 #define GPIO103_USB_P2_5 (103|MFPR_DS6|MFPR_ALT2)
3015 #define GPIO104_USB_P2_7 (104|MFPR_DS6|MFPR_ALT2)
3016 #define GPIO105_KP_DKIN_0 (105|MFPR_DS6|MFPR_ALT2)
3017 #define GPIO106_KP_DKIN_1 (106|MFPR_DS6|MFPR_ALT2)
3018 #define GPIO107_STD_UART3_TXD (107|MFPR_DS6|MFPR_ALT1)
3019 #define GPIO108_STD_UART3_RXD (108|MFPR_DS6|MFPR_ALT1)
3020 #define GPIO109_BT_UART2_RTS (109|MFPR_DS6|MFPR_ALT1)
3021 #define GPIO110_BT_UART2_RXD (110|MFPR_DS6|MFPR_ALT1)
3022 #define GPIO111_BT_UART2_TXD (111|MFPR_DS6|MFPR_ALT1)
3023 #define GPIO112_BT_UART2_CTS (112|MFPR_DS6|MFPR_ALT1)
3024 #define GPIO113_KP_MKIN_0 (113|MFPR_DS6|MFPR_ALT1)
3025 #define GPIO114_KP_MKIN_1 (114|MFPR_DS6|MFPR_ALT1)
3026 #define GPIO115_KP_MKIN_2 (115|MFPR_DS6|MFPR_ALT1)
3027 #define GPIO116_KP_MKIN_3 (116|MFPR_DS6|MFPR_ALT1)
3028 #define GPIO117_KP_MKIN_4 (117|MFPR_DS6|MFPR_ALT1)
3029 #define GPIO118_KP_MKIN_5 (118|MFPR_DS6|MFPR_ALT1)
3030 #define GPIO119_KP_MKIN_6 (119|MFPR_DS6|MFPR_ALT1)
3031 #define GPIO120_KP_MKIN_7 (120|MFPR_DS6|MFPR_ALT1)
3032 #define GPIO121_KP_MKOUT_0 (121|MFPR_DS6|MFPR_ALT1)
3033 #define GPIO122_KP_MKOUT_1 (122|MFPR_DS6|MFPR_ALT1)
3034 #define GPIO123_KP_MKOUT_2 (123|MFPR_DS6|MFPR_ALT1)
3035 #define GPIO124_KP_MKOUT_3 (124|MFPR_DS6|MFPR_ALT1)
3036 #define GPIO125_KP_MKOUT_4 (125|MFPR_DS6|MFPR_ALT1)
3037 #define GPIO126_KP_MKOUT_5 (126|MFPR_DS6|MFPR_ALT1)
3038 #define GPIO127_KP_MKOUT_6 (127|MFPR_DS6|MFPR_ALT1)
3039 #define GPIO5_2_KP_MKOUT_7 (133|MFPR_DS6|MFPR_ALT1)
3040 #define GPIO6_2_LCD_LDD_0 (134|MFPR_DS6|MFPR_ALT1)
3041 #define GPIO7_2_LCD_LDD_1 (135|MFPR_DS6|MFPR_ALT1)
3042 #define GPIO8_2_LCD_LDD_2 (136|MFPR_DS6|MFPR_ALT1)
3043 #define GPIO9_2_LCD_LDD_3 (137|MFPR_DS6|MFPR_ALT1)
3044 #define GPIO10_2_LCD_LDD_4 (138|MFPR_DS6|MFPR_ALT1)
3045 #define GPIO11_2_LCD_LDD_5 (139|MFPR_DS6|MFPR_ALT1)
3046 #define GPIO12_2_LCD_LDD_6 (140|MFPR_DS6|MFPR_ALT1)
3047 #define GPIO13_2_LCD_LDD_7 (141|MFPR_DS6|MFPR_ALT1)
3048 #define GPIO14_2_LCD_FCLK (142|MFPR_DS6|MFPR_ALT1)
3049 #define GPIO15_2_LCD_LCLK (143|MFPR_DS6|MFPR_ALT1)
3050 #define GPIO16_2_LCD_PCLK (144|MFPR_DS6|MFPR_ALT1)
3051 #define GPIO17_2_LCD_BIAS (145|MFPR_DS6|MFPR_ALT1)
3053 /* Internal System Bus Arbiter */
3054 #define ARB_CNTRL1 __REG_2(0x4600FE00) /* PX1 Bus Arbiter Control Register */
3055 #define ARB_CNTRL2 __REG_2(0x4600FE80) /* PX2 Bus Arbiter Control Register */
3060 #define KPC __REG(0x41500000) /* Keypad Interface Control register */
3061 #define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */
3062 #define KPREC __REG(0x41500010) /* Keypad Interface Rotary Encoder register */
3063 #define KPMK __REG(0x41500018) /* Keypad Interface Matrix Key register */
3064 #define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */
3065 #define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
3066 #define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
3067 #define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
3068 #define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
3069 #define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
3071 #define KPC_AS (0x1 << 30) /* Automatic Scan bit */
3072 #define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
3073 #define KPC_MI (0x1 << 22) /* Matrix interrupt bit */
3074 #define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */
3075 #define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */
3076 #define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */
3077 #define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */
3078 #define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */
3079 #define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */
3080 #define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */
3081 #define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */
3082 #define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */
3083 #define KPC_MS_ALL (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7)
3084 #define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */
3085 #define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */
3086 #define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Keypad Debounce Select */
3087 #define KPC_DI (0x1 << 5) /* Direct key interrupt bit */
3088 #define KPC_RE_ZERO_DEB (0x1 << 4) /* Rotary Encoder Zero Debounce */
3089 #define KPC_REE1 (0x1 << 3) /* Rotary Encoder1 Enable */
3090 #define KPC_REE0 (0x1 << 2) /* Rotary Encoder0 Enable */
3091 #define KPC_DE (0x1 << 1) /* Direct Keypad Enable */
3092 #define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */
3094 #define KPDK_DKP (0x1 << 31)
3095 #define KPDK_DK7 (0x1 << 7)
3096 #define KPDK_DK6 (0x1 << 6)
3097 #define KPDK_DK5 (0x1 << 5)
3098 #define KPDK_DK4 (0x1 << 4)
3099 #define KPDK_DK3 (0x1 << 3)
3100 #define KPDK_DK2 (0x1 << 2)
3101 #define KPDK_DK1 (0x1 << 1)
3102 #define KPDK_DK0 (0x1 << 0)
3104 #define KPREC_OF1 (0x1 << 31)
3105 #define kPREC_UF1 (0x1 << 30)
3106 #define KPREC_OF0 (0x1 << 15)
3107 #define KPREC_UF0 (0x1 << 14)
3109 #define KPMK_MKP (0x1 << 31)
3110 #define KPAS_SO (0x1 << 31)
3111 #define KPASMKPx_SO (0x1 << 31)
3114 * UHC: USB Host Controller (OHCI-like) register definitions
3116 #define UHC_BASE_PHYS (0x4C000000)
3117 #define UHCREV __REG_2(0x4C000000) /* UHC HCI Spec Revision */
3118 #define UHCHCON __REG_2(0x4C000004) /* UHC Host Control Register */
3119 #define UHCCOMS __REG_2(0x4C000008) /* UHC Command Status Register */
3120 #define UHCINTS __REG_2(0x4C00000C) /* UHC Interrupt Status Register */
3121 #define UHCINTE __REG_2(0x4C000010) /* UHC Interrupt Enable */
3122 #define UHCINTD __REG_2(0x4C000014) /* UHC Interrupt Disable */
3123 #define UHCHCCA __REG_2(0x4C000018) /* UHC Host Controller Comm. Area */
3124 #define UHCPCED __REG_2(0x4C00001C) /* UHC Period Current Endpt Descr */
3125 #define UHCCHED __REG_2(0x4C000020) /* UHC Control Head Endpt Descr */
3126 #define UHCCCED __REG_2(0x4C000024) /* UHC Control Current Endpt Descr */
3127 #define UHCBHED __REG_2(0x4C000028) /* UHC Bulk Head Endpt Descr */
3128 #define UHCBCED __REG_2(0x4C00002C) /* UHC Bulk Current Endpt Descr */
3129 #define UHCDHEAD __REG_2(0x4C000030) /* UHC Done Head */
3130 #define UHCFMI __REG_2(0x4C000034) /* UHC Frame Interval */
3131 #define UHCFMR __REG_2(0x4C000038) /* UHC Frame Remaining */
3132 #define UHCFMN __REG_2(0x4C00003C) /* UHC Frame Number */
3133 #define UHCPERS __REG_2(0x4C000040) /* UHC Periodic Start */
3134 #define UHCLS __REG_2(0x4C000044) /* UHC Low Speed Threshold */
3135 #define UHCRHDA __REG_2(0x4C000048) /* UHC Root Hub Descriptor A */
3136 #define UHCRHDB __REG_2(0x4C00004C) /* UHC Root Hub Descriptor B */
3137 #define UHCRHS __REG_2(0x4C000050) /* UHC Root Hub Status */
3138 #define UHCRHPS1 __REG_2(0x4C000054) /* UHC Root Hub Port 1 Status */
3139 #define UHCRHPS2 __REG_2(0x4C000058) /* UHC Root Hub Port 2 Status */
3140 #define UHCRHPS3 __REG_2(0x4C00005C) /* UHC Root Hub Port 3 Status */
3141 #define UHCRHPS(x) __REG2_2(0x4C000050, (x)<<2)
3143 #define UHCSTAT __REG_2(0x4C000060) /* UHC Status Register */
3144 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
3145 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
3146 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
3147 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
3148 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
3149 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
3150 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
3151 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
3152 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
3154 #define UHCHR __REG_2(0x4C000064) /* UHC Reset Register */
3155 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
3156 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
3157 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
3158 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */
3159 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
3160 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
3161 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
3162 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
3163 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
3164 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
3165 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
3167 #define UHCHIE __REG_2(0x4C000068) /* UHC Interrupt Enable Register*/
3168 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
3169 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
3170 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
3171 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
3172 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
3174 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
3175 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
3177 #define UHCHIT __REG_2(0x4C00006C) /* UHC Interrupt Test register */
3179 /* Camera Interface / Quick Capture Interface */
3180 #define CICR0 __REG_3(0x50000000) /* Control register 0 */
3181 #define CICR1 __REG_3(0x50000004) /* Control register 1 */
3182 #define CICR2 __REG_3(0x50000008) /* Control register 2 */
3183 #define CICR3 __REG_3(0x5000000C) /* Control register 3 */
3184 #define CICR4 __REG_3(0x50000010) /* Control register 4 */
3185 #define CISR __REG_3(0x50000014) /* Status register */
3186 #define CITOR __REG_3(0x5000001C) /* Time-Out register */
3187 #define CIBR0 __REG_3(0x50000028) /* Channel 0 Receive Buffer */
3188 #define CIBR1 __REG_3(0x50000030) /* Channel 1 Receive Buffer */
3189 #define CIBR2 __REG_3(0x50000038) /* Channel 2 Receive Buffer */
3190 #define CIBR3 __REG_3(0x50000040) /* Channel 3 Receive Buffer */
3192 #define CIPSS __REG_3(0x50000064) /* Pixel Substitution Status register */
3193 #define CIPBUF __REG_3(0x50000068) /* Pixel Substitution Buffer */
3194 #define CIHST __REG_3(0x5000006C) /* Histogram Configuration */
3195 #define CISUM __REG_3(0x50000070) /* Histogram Summation register */
3196 #define CICCR __REG_3(0x50000074) /* Compander Configuration */
3197 #define CISSC __REG_3(0x5000007C) /* Spatial Scaling Configuration */
3199 #define CICMR __REG_3(0x50000090) /* Color Management register */
3200 #define CICMC0 __REG_3(0x50000094) /* Color Management Coefficients 0 */
3201 #define CICMC1 __REG_3(0x50000098) /* Color Management Coefficients 1 */
3202 #define CICMC2 __REG_3(0x5000009C) /* Color Management Coefficients 2 */
3204 #define CIFR0 __REG_3(0x500000B0) /* FIFO Control register 0 */
3205 #define CIFR1 __REG_3(0x500000B4) /* FIFO Control register 1 */
3206 #define CIFSR __REG_3(0x500000C0) /* FIFO Status register */
3208 #define CIDADR0 __REG_3(0x50000240) /* DMA Descriptor Address Channel 0 register */
3209 #define CIDADR1 __REG_3(0x50000250) /* DMA Descriptor Address Channel 1 register */
3210 #define CIDADR2 __REG_3(0x50000260) /* DMA Descriptor Address Channel 2 register */
3211 #define CIDADR3 __REG_3(0x50000270) /* DMA Descriptor Address Channel 3 register */
3212 #define CITADR0 __REG_3(0x50000244) /* DMA Target Address Channel 0 register */
3213 #define CITADR1 __REG_3(0x50000254) /* DMA Target Address Channel 1 register */
3214 #define CITADR2 __REG_3(0x50000264) /* DMA Target Address Channel 2 register */
3215 #define CITADR3 __REG_3(0x50000274) /* DMA Target Address Channel 3 register */
3216 #define CISADR0 __REG_3(0x50000248) /* DMA Source Address Channel 0 register */
3217 #define CISADR1 __REG_3(0x50000258) /* DMA Source Address Channel 1 register */
3218 #define CISADR2 __REG_3(0x50000268) /* DMA Source Address Channel 2 register */
3219 #define CISADR3 __REG_3(0x50000278) /* DMA Source Address Channel 3 register */
3220 #define CICMD0 __REG_3(0x5000024C) /* DMA Command Channel 0 register*/
3221 #define CICMD1 __REG_3(0x5000025C) /* DMA Command Channel 1 register*/
3222 #define CICMD2 __REG_3(0x5000026C) /* DMA Command Channel 2 register*/
3223 #define CICMD3 __REG_3(0x5000027C) /* DMA Command Channel 3 register*/
3224 #define CIDBR0 __REG_3(0x50000220) /* DMA Branch Channel 0 register*/
3225 #define CIDBR1 __REG_3(0x50000224) /* DMA Branch Channel 1 register*/
3226 #define CIDBR2 __REG_3(0x50000228) /* DMA Branch Channel 2 register*/
3227 #define CIDBR3 __REG_3(0x5000022C) /* DMA Branch Channel 3 register*/
3228 #define CIDCSR0 __REG_3(0x50000200) /* DMA Ctrl/Status Channel 0 register*/
3229 #define CIDCSR1 __REG_3(0x50000204) /* DMA Ctrl/Status Channel 1 register*/
3230 #define CIDCSR2 __REG_3(0x50000208) /* DMA Ctrl/Status Channel 2 register*/
3231 #define CIDCSR3 __REG_3(0x5000020C) /* DMA Ctrl/Status Channel 3 register*/
3233 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
3234 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
3235 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
3236 #define CICR0_ENB (1 << 28) /* Camera interface enable */
3237 #define CICR0_DIS (1 << 27) /* Camera interface disable */
3238 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
3239 #define CICR0_TOM (1 << 9) /* Time-out mask */
3240 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
3241 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
3242 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
3243 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
3244 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
3245 #define CICR0_CDM (1 << 3) /* Disable-done mask */
3246 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
3247 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
3248 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
3250 #define CICR1_TBIT (1 << 31) /* Transparency bit */
3251 #define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */
3252 #define CICR1_PPL (0x3f << 15) /* Pixels per line mask */
3253 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
3254 #define CICR1_RGB_F (1 << 11) /* RGB format */
3255 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
3256 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
3257 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
3258 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
3259 #define CICR1_DW (0x7 << 0) /* Data width mask */
3261 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
3263 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
3265 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
3266 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
3268 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
3271 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
3273 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
3275 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
3276 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
3278 #define CICR3_LPF (0x3ff << 0) /* Lines per frame mask */
3280 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
3281 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
3282 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
3283 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
3284 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
3285 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
3286 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
3287 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
3289 #define CISR_FTO (1 << 15) /* FIFO time-out */
3290 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
3291 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
3292 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
3293 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
3294 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
3295 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
3296 #define CISR_EOL (1 << 8) /* End of line */
3297 #define CISR_PAR_ERR (1 << 7) /* Parity error */
3298 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
3299 #define CISR_SOF (1 << 5) /* Start of frame */
3300 #define CISR_CDD (1 << 4) /* Camera interface disable done */
3301 #define CISR_EOF (1 << 3) /* End of frame */
3302 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
3303 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
3304 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
3306 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
3307 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
3308 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
3309 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
3310 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
3311 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
3312 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
3313 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
3315 #endif /* CONFIG_CPU_MONAHANS */
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