include/configs/M54418TWR.h

   1 /*
   2  * Configuation settings for the Freescale MCF54418 TWR board.
   3  *
   4  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54418TWR_H
  15 #define _M54418TWR_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M54418TWR        /* M54418TWR board */
  22
  23 #define CONFIG_MCFUART
  24 #define CONFIG_SYS_UART_PORT            (0)
  25 #define CONFIG_BAUDRATE         115200
  26 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600 , 19200 , 38400 , 57600, 115200 }
  27
  28 #undef CONFIG_WATCHDOG
  29
  30 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  31
  32 /*
  33  * BOOTP options
  34  */
  35 #define CONFIG_BOOTP_BOOTFILESIZE
  36 #define CONFIG_BOOTP_BOOTPATH
  37 #define CONFIG_BOOTP_GATEWAY
  38 #define CONFIG_BOOTP_HOSTNAME
  39
  40 /* Command line configuration */
  41 #include <config_cmd_default.h>
  42
  43 #define CONFIG_CMD_BOOTD
  44 #define CONFIG_CMD_CACHE
  45 #undef CONFIG_CMD_DATE
  46 #define CONFIG_CMD_DHCP
  47 #define CONFIG_CMD_ELF
  48 #undef CONFIG_CMD_FLASH
  49 #undef CONFIG_CMD_I2C
  50 #undef CONFIG_CMD_JFFS2
  51 #undef CONFIG_CMD_UBI
  52 #define CONFIG_CMD_MEMORY
  53 #define CONFIG_CMD_MISC
  54 #define CONFIG_CMD_MII
  55 #undef CONFIG_CMD_NAND
  56 #define CONFIG_CMD_NFS
  57 #define CONFIG_CMD_PING
  58 #define CONFIG_CMD_REGINFO
  59 #define CONFIG_CMD_SPI
  60 #define CONFIG_CMD_SF
  61 #undef CONFIG_CMD_IMLS
  62
  63 #undef CONFIG_CMD_LOADB
  64 #undef CONFIG_CMD_LOADS
  65
  66 /*
  67  * NAND FLASH
  68  */
  69 #ifdef CONFIG_CMD_NAND
  70 #define CONFIG_JFFS2_NAND
  71 #define CONFIG_NAND_FSL_NFC
  72 #define CONFIG_SYS_NAND_BASE            0xFC0FC000
  73 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  74 #define NAND_MAX_CHIPS                  CONFIG_SYS_MAX_NAND_DEVICE
  75 #define CONFIG_SYS_NAND_SELECT_DEVICE
  76 #endif
  77
  78 /* Network configuration */
  79 #define CONFIG_MCFFEC
  80 #ifdef CONFIG_MCFFEC
  81 #define CONFIG_NET_MULTI                1
  82 #define CONFIG_MII                      1
  83 #define CONFIG_MII_INIT         1
  84 #define CONFIG_SYS_DISCOVER_PHY
  85 #define CONFIG_SYS_RX_ETH_BUFFER        2
  86 #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
  87 #define CONFIG_SYS_TX_ETH_BUFFER        2
  88 #define CONFIG_HAS_ETH1
  89
  90 #define CONFIG_SYS_FEC0_PINMUX          0
  91 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  92 #define CONFIG_SYS_FEC1_PINMUX          0
  93 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
  94 #define MCFFEC_TOUT_LOOP                50000
  95 #define CONFIG_SYS_FEC0_PHYADDR 0
  96 #define CONFIG_SYS_FEC1_PHYADDR 1
  97
  98 #define CONFIG_BOOTDELAY                2       /* autoboot after 5 seconds */
  99
 100 #ifdef  CONFIG_SYS_NAND_BOOT
 101 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \
 102                                 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
 103                                 "-(jffs2) console=ttyS0,115200"
 104 #else
 105 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot="     \
 106                                 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \
 107                                 __stringify(CONFIG_IPADDR) "  ip="      \
 108                                 __stringify(CONFIG_IPADDR) ":"  \
 109                                 __stringify(CONFIG_SERVERIP)":" \
 110                                 __stringify(CONFIG_GATEWAYIP)": "       \
 111                                 __stringify(CONFIG_NETMASK)             \
 112                                 "::eth0:off:rw console=ttyS0,115200"
 113 #endif
 114
 115 #define CONFIG_ETHPRIME "FEC0"
 116 #define CONFIG_IPADDR           192.168.1.2
 117 #define CONFIG_NETMASK          255.255.255.0
 118 #define CONFIG_SERVERIP 192.168.1.1
 119 #define CONFIG_GATEWAYIP        192.168.1.1
 120
 121 #define CONFIG_SYS_FEC_BUF_USE_SRAM
 122 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
 123 #ifndef CONFIG_SYS_DISCOVER_PHY
 124 #define FECDUPLEX       FULL
 125 #define FECSPEED        _100BASET
 126 #define LINKSTATUS      1
 127 #else
 128 #define LINKSTATUS      0
 129 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 130 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 131 #endif
 132 #endif                  /* CONFIG_SYS_DISCOVER_PHY */
 133 #endif
 134
 135 #define CONFIG_HOSTNAME         M54418TWR
 136
 137 #if defined(CONFIG_CF_SBF)
 138 /* ST Micro serial flash */
 139 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
 140 #define CONFIG_EXTRA_ENV_SETTINGS               \
 141         "netdev=eth0\0"                         \
 142         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 143         "loadaddr=0x40010000\0"                 \
 144         "sbfhdr=sbfhdr.bin\0"                   \
 145         "uboot=u-boot.bin\0"                    \
 146         "load=tftp ${loadaddr} ${sbfhdr};"      \
 147         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
 148         "upd=run load; run prog\0"              \
 149         "prog=sf probe 0:1 1000000 3;"          \
 150         "sf erase 0 40000;"                     \
 151         "sf write ${loadaddr} 0 40000;"         \
 152         "save\0"                                \
 153         ""
 154 #elif defined(CONFIG_SYS_NAND_BOOT)
 155 #define CONFIG_EXTRA_ENV_SETTINGS               \
 156         "netdev=eth0\0"                         \
 157         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 158         "loadaddr=0x40010000\0"                 \
 159         "u-boot=u-boot.bin\0"                   \
 160         "load=tftp ${loadaddr} ${u-boot};\0"    \
 161         "upd=run load; run prog\0"              \
 162         "prog=nand device 0;"                   \
 163         "nand erase 0 40000;"                   \
 164         "nb_update ${loadaddr} ${filesize};"    \
 165         "save\0"                                \
 166         ""
 167 #else
 168 #define CONFIG_SYS_UBOOT_END    0x3FFFF
 169 #define CONFIG_EXTRA_ENV_SETTINGS               \
 170         "netdev=eth0\0"                         \
 171         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 172         "loadaddr=40010000\0"                   \
 173         "u-boot=u-boot.bin\0"                   \
 174         "load=tftp ${loadaddr) ${u-boot}\0"     \
 175         "upd=run load; run prog\0"              \
 176         "prog=prot off mram" " ;"       \
 177         "cp.b ${loadaddr} 0 ${filesize};"       \
 178         "save\0"                                \
 179         ""
 180 #endif
 181
 182 /* Realtime clock */
 183 #undef CONFIG_MCFRTC
 184 #define CONFIG_RTC_MCFRRTC
 185 #define CONFIG_SYS_MCFRRTC_BASE         0xFC0A8000
 186
 187 /* Timer */
 188 #define CONFIG_MCFTMR
 189 #undef CONFIG_MCFPIT
 190
 191 /* I2c */
 192 #undef CONFIG_SYS_FSL_I2C
 193 #undef CONFIG_HARD_I2C          /* I2C with hardware support */
 194 #undef  CONFIG_SYS_I2C_SOFT     /* I2C bit-banged */
 195 /* I2C speed and slave address  */
 196 #define CONFIG_SYS_I2C_SPEED            80000
 197 #define CONFIG_SYS_I2C_SLAVE            0x7F
 198 #define CONFIG_SYS_I2C_OFFSET           0x58000
 199 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 200
 201 /* DSPI and Serial Flash */
 202 #define CONFIG_CF_SPI
 203 #define CONFIG_CF_DSPI
 204 #define CONFIG_SERIAL_FLASH
 205 #define CONFIG_HARD_SPI
 206 #define CONFIG_SYS_SBFHDR_SIZE          0x7
 207 #ifdef CONFIG_CMD_SPI
 208 #       define CONFIG_SPI_FLASH
 209 #       define CONFIG_SPI_FLASH_ATMEL
 210
 211 #       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
 212                                          DSPI_CTAR_PCSSCK_1CLK | \
 213                                          DSPI_CTAR_PASC(0) | \
 214                                          DSPI_CTAR_PDT(0) | \
 215                                          DSPI_CTAR_CSSCK(0) | \
 216                                          DSPI_CTAR_ASC(0) | \
 217                                          DSPI_CTAR_DT(1))
 218 #       define CONFIG_SYS_DSPI_CTAR1    (CONFIG_SYS_DSPI_CTAR0)
 219 #       define CONFIG_SYS_DSPI_CTAR2    (CONFIG_SYS_DSPI_CTAR0)
 220 #endif
 221
 222 /* Input, PCI, Flexbus, and VCO */
 223 #define CONFIG_EXTRA_CLOCK
 224
 225 #define CONFIG_PRAM                     2048    /* 2048 KB */
 226
 227 /* HUSH */
 228 #define CONFIG_SYS_HUSH_PARSER          1
 229 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 230
 231 #define CONFIG_SYS_PROMPT               "-> "
 232 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 233
 234 #if defined(CONFIG_CMD_KGDB)
 235 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 236 #else
 237 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 238 #endif
 239 /* Print Buffer Size */
 240 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 241                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 242 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 243 /* Boot Argument Buffer Size    */
 244 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 245
 246 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 247
 248 #define CONFIG_SYS_MBAR         0xFC000000
 249
 250 /*
 251  * Low Level Configuration Settings
 252  * (address mappings, register initial values, etc.)
 253  * You should know what you are doing if you make changes here.
 254  */
 255
 256 /*-----------------------------------------------------------------------
 257  * Definitions for initial stack pointer and data area (in DPRAM)
 258  */
 259 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 260 /* End of used area in internal SRAM */
 261 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
 262 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 263 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - \
 264                                         GENERATED_GBL_DATA_SIZE) - 32)
 265 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 266 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 267
 268 /*-----------------------------------------------------------------------
 269  * Start addresses for the final memory configuration
 270  * (Set up by the startup code)
 271  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 272  */
 273 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 274 #define CONFIG_SYS_SDRAM_SIZE           128     /* SDRAM size in MB */
 275
 276 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE + 0x400)
 277 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 278 #define CONFIG_SYS_DRAM_TEST
 279
 280 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
 281 #define CONFIG_SERIAL_BOOT
 282 #endif
 283
 284 #if defined(CONFIG_SERIAL_BOOT)
 285 #define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
 286 #else
 287 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 288 #endif
 289
 290 #define CONFIG_SYS_BOOTPARAMS_LEN       (64 * 1024)
 291 /* Reserve 256 kB for Monitor */
 292 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)
 293 /* Reserve 256 kB for malloc() */
 294 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 295
 296 /*
 297  * For booting Linux, the board info and command line data
 298  * have to be in the first 8 MB of memory, since this is
 299  * the maximum mapped by the Linux kernel during initialization ??
 300  */
 301 /* Initial Memory map for Linux */
 302 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
 303                                 (CONFIG_SYS_SDRAM_SIZE << 20))
 304
 305 /* Configuration for environment
 306  * Environment is embedded in u-boot in the second sector of the flash
 307  */
 308 #if !defined(CONFIG_SERIAL_BOOT)  /*MRAM boot*/
 309 #define CONFIG_SYS_NO_FLASH
 310 #define CONFIG_ENV_IS_IN_MRAM   1
 311 #define CONFIG_ENV_ADDR         (0x40000 - 0x1000) /*MRAM size 40000*/
 312 #define CONFIG_ENV_SIZE         0x1000
 313 #endif
 314
 315 #if defined(CONFIG_CF_SBF)
 316 #define CONFIG_SYS_NO_FLASH
 317 #define CONFIG_ENV_IS_IN_SPI_FLASH      1
 318 #define CONFIG_ENV_SPI_CS               1
 319 #define CONFIG_ENV_OFFSET               0x40000
 320 #define CONFIG_ENV_SIZE         0x2000
 321 #define CONFIG_ENV_SECT_SIZE            0x10000
 322 #endif
 323 #if defined(CONFIG_SYS_NAND_BOOT)
 324 #define CONFIG_SYS_NO_FLASH
 325 #define CONFIG_ENV_IS_NOWHERE
 326 #define CONFIG_ENV_OFFSET       0x80000
 327 #define CONFIG_ENV_SIZE 0x20000
 328 #define CONFIG_ENV_SECT_SIZE    0x20000
 329 #endif
 330 #undef CONFIG_ENV_OVERWRITE
 331
 332 /* FLASH organization */
 333 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 334
 335 #undef CONFIG_SYS_FLASH_CFI
 336 #ifdef CONFIG_SYS_FLASH_CFI
 337
 338 #define CONFIG_FLASH_CFI_DRIVER 1
 339 /* Max size that the board might have */
 340 #define CONFIG_SYS_FLASH_SIZE           0x1000000
 341 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 342 /* max number of memory banks */
 343 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 344 /* max number of sectors on one chip */
 345 #define CONFIG_SYS_MAX_FLASH_SECT       270
 346 /* "Real" (hardware) sectors protection */
 347 #define CONFIG_SYS_FLASH_PROTECTION
 348 #define CONFIG_SYS_FLASH_CHECKSUM
 349 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_CS0_BASE }
 350 #else
 351 /* max number of sectors on one chip */
 352 #define CONFIG_SYS_MAX_FLASH_SECT       270
 353 /* max number of sectors on one chip */
 354 #define CONFIG_SYS_MAX_FLASH_BANKS      0
 355 #endif
 356
 357 /*
 358  * This is setting for JFFS2 support in u-boot.
 359  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 360  */
 361 #ifdef CONFIG_CMD_JFFS2
 362 #define CONFIG_JFFS2_DEV                "nand0"
 363 #define CONFIG_JFFS2_PART_OFFSET        (0x800000)
 364 #define CONFIG_CMD_MTDPARTS
 365 #define CONFIG_MTD_DEVICE
 366 #define MTDIDS_DEFAULT          "nand0=m54418twr.nand"
 367
 368 #define MTDPARTS_DEFAULT        "mtdparts=m54418twr.nand:1m(data),"     \
 369                                                 "7m(kernel),"           \
 370                                                 "-(rootfs)"
 371
 372 #endif
 373
 374 #ifdef CONFIG_CMD_UBI
 375 #define CONFIG_CMD_MTDPARTS
 376 #define CONFIG_MTD_DEVICE       /* needed for mtdparts command */
 377 #define CONFIG_MTD_PARTITIONS   /* mtdparts and UBI support */
 378 #define CONFIG_RBTREE
 379 #define MTDIDS_DEFAULT          "nand0=NAND"
 380 #define MTDPARTS_DEFAULT        "mtdparts=NAND:1m(u-boot),"     \
 381                                         "-(ubi)"
 382 #endif
 383 /* Cache Configuration */
 384 #define CONFIG_SYS_CACHELINE_SIZE       16
 385 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 386                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 387 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 388                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 389 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 390 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 391 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 392                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 393                                          CF_ACR_EN | CF_ACR_SM_ALL)
 394 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 395                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 396 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 397                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 398                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 399
 400 #define CACR_STATUS     (CONFIG_SYS_INIT_RAM_ADDR + \
 401                         CONFIG_SYS_INIT_RAM_SIZE - 12)
 402
 403 /*-----------------------------------------------------------------------
 404  * Memory bank definitions
 405  */
 406 /*
 407  * CS0 - NOR Flash 16MB
 408  * CS1 - Available
 409  * CS2 - Available
 410  * CS3 - Available
 411  * CS4 - Available
 412  * CS5 - Available
 413  */
 414
 415  /* Flash */
 416 #define CONFIG_SYS_CS0_BASE             0x00000000
 417 #define CONFIG_SYS_CS0_MASK             0x000F0101
 418 #define CONFIG_SYS_CS0_CTRL             0x00001D60
 419
 420 #endif                          /* _M54418TWR_H */