include/configs/M54451EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF54451 EVB board.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54451EVB_H
  15 #define _M54451EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M54451EVB        /* M54451EVB board */
  22
  23 #define CONFIG_DISPLAY_BOARDINFO
  24
  25 #define CONFIG_MCFUART
  26 #define CONFIG_SYS_UART_PORT            (0)
  27 #define CONFIG_BAUDRATE         115200
  28
  29 #undef CONFIG_WATCHDOG
  30
  31 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  32
  33 /*
  34  * BOOTP options
  35  */
  36 #define CONFIG_BOOTP_BOOTFILESIZE
  37 #define CONFIG_BOOTP_BOOTPATH
  38 #define CONFIG_BOOTP_GATEWAY
  39 #define CONFIG_BOOTP_HOSTNAME
  40
  41 /* Command line configuration */
  42 #include <config_cmd_default.h>
  43
  44 #define CONFIG_CMD_BOOTD
  45 #define CONFIG_CMD_CACHE
  46 #define CONFIG_CMD_DATE
  47 #define CONFIG_CMD_DHCP
  48 #define CONFIG_CMD_ELF
  49 #define CONFIG_CMD_FLASH
  50 #define CONFIG_CMD_I2C
  51 #undef CONFIG_CMD_JFFS2
  52 #define CONFIG_CMD_MEMORY
  53 #define CONFIG_CMD_MISC
  54 #define CONFIG_CMD_MII
  55 #define CONFIG_CMD_NFS
  56 #define CONFIG_CMD_PING
  57 #define CONFIG_CMD_REGINFO
  58 #define CONFIG_CMD_SPI
  59 #define CONFIG_CMD_SF
  60
  61 #undef CONFIG_CMD_LOADB
  62 #undef CONFIG_CMD_LOADS
  63
  64 /* Network configuration */
  65 #define CONFIG_MCFFEC
  66 #ifdef CONFIG_MCFFEC
  67 #       define CONFIG_MII               1
  68 #       define CONFIG_MII_INIT          1
  69 #       define CONFIG_SYS_DISCOVER_PHY
  70 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  71 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  72
  73 #       define CONFIG_SYS_FEC0_PINMUX   0
  74 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  75 #       define MCFFEC_TOUT_LOOP 50000
  76
  77 #       define CONFIG_BOOTDELAY 1       /* autoboot after 5 seconds */
  78 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
  79 #       define CONFIG_ETHPRIME          "FEC0"
  80 #       define CONFIG_IPADDR            192.162.1.2
  81 #       define CONFIG_NETMASK           255.255.255.0
  82 #       define CONFIG_SERVERIP          192.162.1.1
  83 #       define CONFIG_GATEWAYIP         192.162.1.1
  84
  85 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  86 #       ifndef CONFIG_SYS_DISCOVER_PHY
  87 #               define FECDUPLEX        FULL
  88 #               define FECSPEED         _100BASET
  89 #       else
  90 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  91 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  92 #               endif
  93 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  94 #endif
  95
  96 #define CONFIG_HOSTNAME         M54451EVB
  97 #ifdef CONFIG_SYS_STMICRO_BOOT
  98 /* ST Micro serial flash */
  99 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
 100 #define CONFIG_EXTRA_ENV_SETTINGS               \
 101         "netdev=eth0\0"                         \
 102         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 103         "loadaddr=0x40010000\0"                 \
 104         "sbfhdr=sbfhdr.bin\0"                   \
 105         "uboot=u-boot.bin\0"                    \
 106         "load=tftp ${loadaddr} ${sbfhdr};"      \
 107         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
 108         "upd=run load; run prog\0"              \
 109         "prog=sf probe 0:1 1000000 3;"          \
 110         "sf erase 0 30000;"                     \
 111         "sf write ${loadaddr} 0 30000;"         \
 112         "save\0"                                \
 113         ""
 114 #else
 115 #define CONFIG_SYS_UBOOT_END    0x3FFFF
 116 #define CONFIG_EXTRA_ENV_SETTINGS               \
 117         "netdev=eth0\0"                         \
 118         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 119         "loadaddr=40010000\0"                   \
 120         "u-boot=u-boot.bin\0"                   \
 121         "load=tftp ${loadaddr) ${u-boot}\0"     \
 122         "upd=run load; run prog\0"              \
 123         "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END)    \
 124         "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;"       \
 125         "cp.b ${loadaddr} 0 ${filesize};"       \
 126         "save\0"                                \
 127         ""
 128 #endif
 129
 130 /* Realtime clock */
 131 #define CONFIG_MCFRTC
 132 #undef RTC_DEBUG
 133 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 134
 135 /* Timer */
 136 #define CONFIG_MCFTMR
 137 #undef CONFIG_MCFPIT
 138
 139 /* I2c */
 140 #define CONFIG_SYS_I2C
 141 #define CONFIG_SYS_I2C_FSL
 142 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 143 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 144 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 145 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 146
 147 /* DSPI and Serial Flash */
 148 #define CONFIG_CF_SPI
 149 #define CONFIG_CF_DSPI
 150 #define CONFIG_SERIAL_FLASH
 151 #define CONFIG_HARD_SPI
 152 #define CONFIG_SYS_SBFHDR_SIZE          0x7
 153 #ifdef CONFIG_CMD_SPI
 154 #       define CONFIG_SPI_FLASH_STMICRO
 155
 156 #       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
 157                                          DSPI_CTAR_PCSSCK_1CLK | \
 158                                          DSPI_CTAR_PASC(0) | \
 159                                          DSPI_CTAR_PDT(0) | \
 160                                          DSPI_CTAR_CSSCK(0) | \
 161                                          DSPI_CTAR_ASC(0) | \
 162                                          DSPI_CTAR_DT(1))
 163 #       define CONFIG_SYS_DSPI_CTAR1    (CONFIG_SYS_DSPI_CTAR0)
 164 #       define CONFIG_SYS_DSPI_CTAR2    (CONFIG_SYS_DSPI_CTAR0)
 165 #endif
 166
 167 /* Input, PCI, Flexbus, and VCO */
 168 #define CONFIG_EXTRA_CLOCK
 169
 170 #define CONFIG_PRAM                     2048    /* 2048 KB */
 171
 172 #define CONFIG_SYS_PROMPT               "-> "
 173 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 174
 175 #if defined(CONFIG_CMD_KGDB)
 176 #define CONFIG_SYS_CBSIZE                       1024    /* Console I/O Buffer Size */
 177 #else
 178 #define CONFIG_SYS_CBSIZE                       256     /* Console I/O Buffer Size */
 179 #endif
 180 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 181 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 182 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 183
 184 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 185
 186 #define CONFIG_SYS_MBAR                 0xFC000000
 187
 188 /*
 189  * Low Level Configuration Settings
 190  * (address mappings, register initial values, etc.)
 191  * You should know what you are doing if you make changes here.
 192  */
 193
 194 /*-----------------------------------------------------------------------
 195  * Definitions for initial stack pointer and data area (in DPRAM)
 196  */
 197 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 198 #define CONFIG_SYS_INIT_RAM_SIZE        0x8000  /* Size of used area in internal SRAM */
 199 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 200 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 201 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 202 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 203
 204 /*-----------------------------------------------------------------------
 205  * Start addresses for the final memory configuration
 206  * (Set up by the startup code)
 207  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 208  */
 209 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 210 #define CONFIG_SYS_SDRAM_SIZE           128     /* SDRAM size in MB */
 211 #define CONFIG_SYS_SDRAM_CFG1           0x33633F30
 212 #define CONFIG_SYS_SDRAM_CFG2           0x57670000
 213 #define CONFIG_SYS_SDRAM_CTRL           0xE20D2C00
 214 #define CONFIG_SYS_SDRAM_EMOD           0x80810000
 215 #define CONFIG_SYS_SDRAM_MODE           0x008D0000
 216 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0x44
 217
 218 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 219 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 220
 221 #ifdef CONFIG_CF_SBF
 222 #       define CONFIG_SERIAL_BOOT
 223 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 224 #else
 225 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 226 #endif
 227 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 228 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 229
 230 /* Reserve 256 kB for malloc() */
 231 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 232 /*
 233  * For booting Linux, the board info and command line data
 234  * have to be in the first 8 MB of memory, since this is
 235  * the maximum mapped by the Linux kernel during initialization ??
 236  */
 237 /* Initial Memory map for Linux */
 238 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 239
 240 /* Configuration for environment
 241  * Environment is not embedded in u-boot. First time runing may have env
 242  * crc error warning if there is no correct environment on the flash.
 243  */
 244 #if defined(CONFIG_SYS_STMICRO_BOOT)
 245 #       define CONFIG_ENV_IS_IN_SPI_FLASH       1
 246 #       define CONFIG_ENV_SPI_CS                1
 247 #       define CONFIG_ENV_OFFSET                0x20000
 248 #       define CONFIG_ENV_SIZE          0x2000
 249 #       define CONFIG_ENV_SECT_SIZE     0x10000
 250 #else
 251 #       define CONFIG_ENV_IS_IN_FLASH   1
 252 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 253 #       define CONFIG_ENV_SIZE          0x2000
 254 #       define CONFIG_ENV_SECT_SIZE     0x20000
 255 #endif
 256 #undef CONFIG_ENV_OVERWRITE
 257
 258 /* FLASH organization */
 259 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 260
 261 #define CONFIG_SYS_FLASH_CFI
 262 #ifdef CONFIG_SYS_FLASH_CFI
 263
 264 #       define CONFIG_FLASH_CFI_DRIVER  1
 265 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 266 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 267 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 268 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 269 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 270 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 271 #       define CONFIG_SYS_FLASH_CHECKSUM
 272 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE }
 273
 274 #endif
 275
 276 /*
 277  * This is setting for JFFS2 support in u-boot.
 278  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 279  */
 280 #ifdef CONFIG_CMD_JFFS2
 281 #       define CONFIG_JFFS2_DEV         "nor0"
 282 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 283 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 284 #endif
 285
 286 /* Cache Configuration */
 287 #define CONFIG_SYS_CACHELINE_SIZE               16
 288
 289 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 290                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 291 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 292                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 293 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 294 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 295 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 296                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 297                                          CF_ACR_EN | CF_ACR_SM_ALL)
 298 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 299                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 300 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 301                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 302                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 303
 304 /*-----------------------------------------------------------------------
 305  * Memory bank definitions
 306  */
 307 /*
 308  * CS0 - NOR Flash 16MB
 309  * CS1 - Available
 310  * CS2 - Available
 311  * CS3 - Available
 312  * CS4 - Available
 313  * CS5 - Available
 314  */
 315
 316  /* Flash */
 317 #define CONFIG_SYS_CS0_BASE             0x00000000
 318 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 319 #define CONFIG_SYS_CS0_CTRL             0x00004D80
 320
 321 #define CONFIG_SYS_SPANSION_BASE        CONFIG_SYS_CS0_BASE
 322
 323 #endif                          /* _M54451EVB_H */