include/configs/adp-ag101.h

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 #include <asm/arch/ag101.h>
  28
  29 /*
  30  * CPU and Board Configuration Options
  31  */
  32 #define CONFIG_ADP_AG101
  33
  34 #define CONFIG_USE_INTERRUPT
  35
  36 #define CONFIG_SKIP_LOWLEVEL_INIT
  37
  38 /*
  39  * Definitions related to passing arguments to kernel.
  40  */
  41 #define CONFIG_CMDLINE_TAG                      /* send commandline to Kernel */
  42 #define CONFIG_SETUP_MEMORY_TAGS        /* send memory definition to kernel */
  43 #define CONFIG_INITRD_TAG                       /* send initrd params */
  44
  45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  46 #define CONFIG_MEM_REMAP
  47 #endif
  48
  49 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  50 #define CONFIG_SYS_TEXT_BASE    0x03200000
  51 #else
  52 #define CONFIG_SYS_TEXT_BASE    0x00000000
  53 #endif
  54
  55 /*
  56  * Timer
  57  */
  58
  59 /*
  60  * According to the discussion in u-boot mailing list before,
  61  * CONFIG_SYS_HZ at 1000 is mandatory.
  62  */
  63 #define CONFIG_SYS_HZ           1000
  64 #define CONFIG_SYS_CLK_FREQ     48000000
  65 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  66
  67 /*
  68  * Use Externel CLOCK or PCLK
  69  */
  70 #undef CONFIG_FTRTC010_EXTCLK
  71
  72 #ifndef CONFIG_FTRTC010_EXTCLK
  73 #define CONFIG_FTRTC010_PCLK
  74 #endif
  75
  76 #ifdef CONFIG_FTRTC010_EXTCLK
  77 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  78 #else
  79 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  80 #endif
  81
  82 #define TIMER_LOAD_VAL  0xffffffff
  83
  84 /*
  85  * Real Time Clock
  86  */
  87 #define CONFIG_RTC_FTRTC010
  88
  89 /*
  90  * Real Time Clock Divider
  91  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  92  */
  93 #define OSC_5MHZ                        (5*1000000)
  94 #define OSC_CLK                         (2*OSC_5MHZ)
  95 #define RTC_DIV_COUNT                   (OSC_CLK/OSC_5MHZ)
  96
  97 /*
  98  * Serial console configuration
  99  */
 100
 101 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
 102 #define CONFIG_BAUDRATE                 38400
 103 #define CONFIG_CONS_INDEX               1
 104 #define CONFIG_SYS_NS16550
 105 #define CONFIG_SYS_NS16550_SERIAL
 106 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
 107 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 108 #define CONFIG_SYS_NS16550_CLK          ((46080000 * 20) / 25)  /* AG101 */
 109
 110 /*
 111  * Ethernet
 112  */
 113 #define CONFIG_FTMAC100
 114
 115 #define CONFIG_BOOTDELAY        3
 116
 117 /*
 118  * SD (MMC) controller
 119  */
 120 #define CONFIG_MMC
 121 #define CONFIG_CMD_MMC
 122 #define CONFIG_GENERIC_MMC
 123 #define CONFIG_DOS_PARTITION
 124 #define CONFIG_FTSDC010
 125 #define CONFIG_FTSDC010_NUMBER          1
 126 #define CONFIG_FTSDC010_SDIO
 127 #define CONFIG_CMD_FAT
 128 #define CONFIG_CMD_EXT2
 129
 130 /*
 131  * Command line configuration.
 132  */
 133 #include <config_cmd_default.h>
 134
 135 #define CONFIG_CMD_CACHE
 136 #define CONFIG_CMD_DATE
 137 #define CONFIG_CMD_PING
 138
 139 /*
 140  * Miscellaneous configurable options
 141  */
 142 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 143 #define CONFIG_SYS_PROMPT       "NDS32 # "      /* Monitor Command Prompt */
 144 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 145
 146 /* Print Buffer Size */
 147 #define CONFIG_SYS_PBSIZE       \
 148         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 149
 150 /* max number of command args */
 151 #define CONFIG_SYS_MAXARGS      16
 152
 153 /* Boot Argument Buffer Size */
 154 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 155
 156 /*
 157  * Size of malloc() pool
 158  */
 159 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
 160 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
 161
 162 /*
 163  * size in bytes reserved for initial data
 164  */
 165 #define CONFIG_SYS_GBL_DATA_SIZE        128
 166
 167 /*
 168  * AHB Controller configuration
 169  */
 170 #define CONFIG_FTAHBC020S
 171
 172 #ifdef CONFIG_FTAHBC020S
 173 #include <faraday/ftahbc020s.h>
 174
 175 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
 176 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
 177
 178 /*
 179  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
 180  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
 181  * in C language.
 182  */
 183 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
 184         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
 185                                         FTAHBC020S_SLAVE_BSR_SIZE(0xb))
 186 #endif
 187
 188 /*
 189  * Watchdog
 190  */
 191 #define CONFIG_FTWDT010_WATCHDOG
 192
 193 /*
 194  * PMU Power controller configuration
 195  */
 196 #define CONFIG_PMU
 197 #define CONFIG_FTPMU010_POWER
 198
 199 #ifdef CONFIG_FTPMU010_POWER
 200 #include <faraday/ftpmu010.h>
 201 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS          0x0E
 202 #define CONFIG_SYS_FTPMU010_SDRAMHTC    (FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
 203                                          FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
 204                                          FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
 205                                          FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
 206                                          FTPMU010_SDRAMHTC_CKE_DCSR      | \
 207                                          FTPMU010_SDRAMHTC_DQM_DCSR      | \
 208                                          FTPMU010_SDRAMHTC_SDCLK_DCSR)
 209 #endif
 210
 211 /*
 212  * SDRAM controller configuration
 213  */
 214 #define CONFIG_FTSDMC021
 215
 216 #ifdef CONFIG_FTSDMC021
 217 #include <faraday/ftsdmc021.h>
 218
 219 #define CONFIG_SYS_FTSDMC021_TP1        (FTSDMC021_TP1_TRP(1)   |       \
 220                                          FTSDMC021_TP1_TRCD(1)  |       \
 221                                          FTSDMC021_TP1_TRF(3)   |       \
 222                                          FTSDMC021_TP1_TWR(1)   |       \
 223                                          FTSDMC021_TP1_TCL(2))
 224
 225 #define CONFIG_SYS_FTSDMC021_TP2        (FTSDMC021_TP2_INI_PREC(4) |    \
 226                                          FTSDMC021_TP2_INI_REFT(8) |    \
 227                                          FTSDMC021_TP2_REF_INTV(0x180))
 228
 229 /*
 230  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
 231  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
 232  * C language.
 233  */
 234 #define CONFIG_SYS_FTSDMC021_CR1        (FTSDMC021_CR1_DDW(2)    |      \
 235                                          FTSDMC021_CR1_DSZ(3)    |      \
 236                                          FTSDMC021_CR1_MBW(2)    |      \
 237                                          FTSDMC021_CR1_BNKSIZE(6))
 238
 239 #define CONFIG_SYS_FTSDMC021_CR2        (FTSDMC021_CR2_IPREC     |      \
 240                                          FTSDMC021_CR2_IREF      |      \
 241                                          FTSDMC021_CR2_ISMR)
 242
 243 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
 244 #define CONFIG_SYS_FTSDMC021_BANK0_BSR  (FTSDMC021_BANK_ENABLE   |      \
 245                                          CONFIG_SYS_FTSDMC021_BANK0_BASE)
 246
 247 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
 248         (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
 249 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE   |      \
 250                 CONFIG_SYS_FTSDMC021_BANK1_BASE)
 251
 252 #endif
 253
 254 /*
 255  * Physical Memory Map
 256  */
 257 #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
 258 #define PHYS_SDRAM_0            0x00000000      /* SDRAM Bank #1 */
 259 #if defined(CONFIG_MEM_REMAP)
 260 #define PHYS_SDRAM_0_AT_INIT    0x10000000      /* SDRAM Bank #1 before remap*/
 261 #endif
 262 #else   /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
 263 #define PHYS_SDRAM_0            0x10000000      /* SDRAM Bank #1 */
 264 #endif
 265 #define PHYS_SDRAM_1 \
 266         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
 267
 268 #define CONFIG_NR_DRAM_BANKS    2               /* we have 2 bank of DRAM */
 269 #define PHYS_SDRAM_0_SIZE       0x04000000      /* 64 MB */
 270 #define PHYS_SDRAM_1_SIZE       0x04000000      /* 64 MB */
 271
 272 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 273
 274 #ifdef CONFIG_MEM_REMAP
 275 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 276                                         GENERATED_GBL_DATA_SIZE)
 277 #else
 278 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 279                                         GENERATED_GBL_DATA_SIZE)
 280 #endif /* CONFIG_MEM_REMAP */
 281
 282 /*
 283  * Load address and memory test area should agree with
 284  * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
 285  */
 286 #define CONFIG_SYS_LOAD_ADDR            0x300000
 287
 288 /* memtest works on 63 MB in DRAM */
 289 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_0
 290 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_0 + 0x03F00000)
 291
 292 /*
 293  * Static memory controller configuration
 294  */
 295 #define CONFIG_FTSMC020
 296
 297 #ifdef CONFIG_FTSMC020
 298 #include <faraday/ftsmc020.h>
 299
 300 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 301 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 302         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 303         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 304 }
 305 #else
 306 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 307         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 308 }
 309 #endif
 310
 311 /*
 312  * There are 2 bank connected to FTSMC020 on ADP-AG101.
 313  * You can use jumper and switch to force it booted from ROM or FLASH.
 314  * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH.
 315  * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled.
 316  */
 317 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 318 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 319                                          FTSMC020_BANK_SIZE_32M |       \
 320                                          FTSMC020_BANK_MBW_32)
 321
 322 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 323                                          FTSMC020_TPR_AST(1)    |       \
 324                                          FTSMC020_TPR_CTW(1)    |       \
 325                                          FTSMC020_TPR_ATI(1)    |       \
 326                                          FTSMC020_TPR_AT2(1)    |       \
 327                                          FTSMC020_TPR_WTC(1)    |       \
 328                                          FTSMC020_TPR_AHT(1)    |       \
 329                                          FTSMC020_TPR_TRNA(1))
 330 #endif
 331
 332 /*
 333  * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0.
 334  * 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM,
 335  *    Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition.
 336  * 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH.
 337  */
 338 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_SIZE_32M           |     \
 339                                  FTSMC020_BANK_MBW_32)
 340
 341 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_RBE      |        \
 342                                  FTSMC020_TPR_AST(3)   |        \
 343                                  FTSMC020_TPR_CTW(3)   |        \
 344                                  FTSMC020_TPR_ATI(0xf) |        \
 345                                  FTSMC020_TPR_AT2(3)   |        \
 346                                  FTSMC020_TPR_WTC(3)   |        \
 347                                  FTSMC020_TPR_AHT(3)   |        \
 348                                  FTSMC020_TPR_TRNA(0xf))
 349
 350 #define FTSMC020_BANK1_CONFIG   (FTSMC020_BANK_ENABLE   |       \
 351                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 352                                  FTSMC020_BANK_SIZE_32M |       \
 353                                  FTSMC020_BANK_MBW_32)
 354
 355 #define FTSMC020_BANK1_TIMING   (FTSMC020_TPR_RBE       |       \
 356                                  FTSMC020_TPR_AST(1)    |       \
 357                                  FTSMC020_TPR_CTW(1)    |       \
 358                                  FTSMC020_TPR_ATI(1)    |       \
 359                                  FTSMC020_TPR_AT2(1)    |       \
 360                                  FTSMC020_TPR_WTC(1)    |       \
 361                                  FTSMC020_TPR_AHT(1)    |       \
 362                                  FTSMC020_TPR_TRNA(1))
 363 #endif /* CONFIG_FTSMC020 */
 364
 365 /*
 366  * FLASH and environment organization
 367  */
 368 /* use CFI framework */
 369 #define CONFIG_SYS_FLASH_CFI
 370 #define CONFIG_FLASH_CFI_DRIVER
 371
 372 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 373 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 374
 375 /* support JEDEC */
 376
 377 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 378 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 379 #define PHYS_FLASH_1                    0x80400000      /* BANK 1 */
 380 #else   /* !CONFIG_SKIP_LOWLEVEL_INIT */
 381 #ifdef CONFIG_MEM_REMAP
 382 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 383 #else
 384 #define PHYS_FLASH_1                    0x00000000      /* BANK 0 */
 385 #endif  /* CONFIG_MEM_REMAP */
 386 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
 387
 388 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 389 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 390 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 391
 392 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 393 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 394
 395 /* max number of memory banks */
 396 /*
 397  * There are 4 banks supported for this Controller,
 398  * but we have only 1 bank connected to flash on board
 399  */
 400 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 401
 402 /* max number of sectors on one chip */
 403 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2*2)
 404 #define CONFIG_ENV_SECT_SIZE            CONFIG_FLASH_SECTOR_SIZE
 405 #define CONFIG_SYS_MAX_FLASH_SECT       128
 406
 407 /* environments */
 408 #define CONFIG_ENV_IS_IN_FLASH
 409 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + 0x40000)
 410 #define CONFIG_ENV_SIZE                 8192
 411 #define CONFIG_ENV_OVERWRITE
 412
 413 #endif  /* __CONFIG_H */