include/configs/cm_t35.h

   1 /*
   2  * (C) Copyright 2011 CompuLab, Ltd.
   3  * Mike Rapoport <mike@compulab.co.il>
   4  * Igor Grinberg <grinberg@compulab.co.il>
   5  *
   6  * Based on omap3_beagle.h
   7  * (C) Copyright 2006-2008
   8  * Texas Instruments.
   9  * Richard Woodruff <r-woodruff2@ti.com>
  10  * Syed Mohammed Khasim <x0khasim@ti.com>
  11  *
  12  * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * High Level Configuration Options
  22  */
  23 #define CONFIG_OMAP     /* in a TI OMAP core */
  24 #define CONFIG_OMAP34XX /* which is a 34XX */
  25 #define CONFIG_OMAP_GPIO
  26 #define CONFIG_CM_T3X   /* working with CM-T35 and CM-T3730 */
  27
  28 #define CONFIG_SYS_TEXT_BASE    0x80008000
  29
  30 #define CONFIG_SDRC     /* The chip has SDRC controller */
  31
  32 #include <asm/arch/cpu.h>               /* get chip and board defs */
  33 #include <asm/arch/omap3.h>
  34
  35 /*
  36  * Display CPU and Board information
  37  */
  38 #define CONFIG_DISPLAY_CPUINFO
  39 #define CONFIG_DISPLAY_BOARDINFO
  40
  41 /* Clock Defines */
  42 #define V_OSCK                  26000000        /* Clock output from T2 */
  43 #define V_SCLK                  (V_OSCK >> 1)
  44
  45 #define CONFIG_MISC_INIT_R
  46
  47 #define CONFIG_OF_LIBFDT                1
  48 /*
  49  * The early kernel mapping on ARM currently only maps from the base of DRAM
  50  * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
  51  * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
  52  * so that leaves DRAM base to DRAM base + 0x4000 available.
  53  */
  54 #define CONFIG_SYS_BOOTMAPSZ            0x4000
  55
  56 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  57 #define CONFIG_SETUP_MEMORY_TAGS
  58 #define CONFIG_INITRD_TAG
  59 #define CONFIG_REVISION_TAG
  60 #define CONFIG_SERIAL_TAG
  61
  62 /*
  63  * Size of malloc() pool
  64  */
  65 #define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
  66                                         /* Sector */
  67 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + (128 << 10))
  68
  69 /*
  70  * Hardware drivers
  71  */
  72
  73 /*
  74  * NS16550 Configuration
  75  */
  76 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  77
  78 #define CONFIG_SYS_NS16550
  79 #define CONFIG_SYS_NS16550_SERIAL
  80 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  81 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  82
  83 /*
  84  * select serial console configuration
  85  */
  86 #define CONFIG_CONS_INDEX               3
  87 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  88 #define CONFIG_SERIAL3                  3       /* UART3 */
  89
  90 /* allow to overwrite serial and ethaddr */
  91 #define CONFIG_ENV_OVERWRITE
  92 #define CONFIG_BAUDRATE                 115200
  93 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  94                                         115200}
  95
  96 #define CONFIG_GENERIC_MMC
  97 #define CONFIG_MMC
  98 #define CONFIG_OMAP_HSMMC
  99 #define CONFIG_DOS_PARTITION
 100
 101 /* USB */
 102 #define CONFIG_USB_OMAP3
 103 #define CONFIG_USB_EHCI
 104 #define CONFIG_USB_EHCI_OMAP
 105 #define CONFIG_USB_ULPI
 106 #define CONFIG_USB_ULPI_VIEWPORT_OMAP
 107 #define CONFIG_USB_STORAGE
 108 #define CONFIG_MUSB_UDC
 109 #define CONFIG_TWL4030_USB
 110 #define CONFIG_CMD_USB
 111
 112 /* USB device configuration */
 113 #define CONFIG_USB_DEVICE
 114 #define CONFIG_USB_TTY
 115 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 116
 117 /* commands to include */
 118 #include <config_cmd_default.h>
 119
 120 #define CONFIG_CMD_CACHE
 121 #define CONFIG_CMD_EXT2         /* EXT2 Support                 */
 122 #define CONFIG_CMD_FAT          /* FAT support                  */
 123 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
 124 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 125 #define CONFIG_MTD_PARTITIONS
 126 #define MTDIDS_DEFAULT          "nand0=nand"
 127 #define MTDPARTS_DEFAULT        "mtdparts=nand:512k(x-loader),"\
 128                                 "1920k(u-boot),256k(u-boot-env),"\
 129                                 "4m(kernel),-(fs)"
 130
 131 #define CONFIG_CMD_I2C          /* I2C serial bus support       */
 132 #define CONFIG_CMD_MMC          /* MMC support                  */
 133 #define CONFIG_CMD_NAND         /* NAND support                 */
 134 #define CONFIG_CMD_DHCP
 135 #define CONFIG_CMD_PING
 136
 137 #undef CONFIG_CMD_FLASH         /* flinfo, erase, protect       */
 138 #undef CONFIG_CMD_FPGA          /* FPGA configuration Support   */
 139 #undef CONFIG_CMD_IMLS          /* List all found images        */
 140
 141 #define CONFIG_SYS_NO_FLASH
 142 #define CONFIG_HARD_I2C
 143 #define CONFIG_SYS_I2C_SPEED            100000
 144 #define CONFIG_SYS_I2C_SLAVE            1
 145 #define CONFIG_DRIVER_OMAP34XX_I2C
 146 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 147 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 148 #define CONFIG_I2C_MULTI_BUS
 149
 150 /*
 151  * TWL4030
 152  */
 153 #define CONFIG_TWL4030_POWER
 154 #define CONFIG_TWL4030_LED
 155
 156 /*
 157  * Board NAND Info.
 158  */
 159 #define CONFIG_SYS_NAND_QUIET_TEST
 160 #define CONFIG_NAND_OMAP_GPMC
 161 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 162                                                         /* to access nand */
 163 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 164                                                         /* to access nand at */
 165                                                         /* CS0 */
 166 #define GPMC_NAND_ECC_LP_x8_LAYOUT
 167
 168 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 169                                                         /* devices */
 170 /* Environment information */
 171 #define CONFIG_BOOTDELAY                10
 172 #define CONFIG_ZERO_BOOTDELAY_CHECK
 173
 174 #define CONFIG_EXTRA_ENV_SETTINGS \
 175         "loadaddr=0x82000000\0" \
 176         "usbtty=cdc_acm\0" \
 177         "console=ttyS2,115200n8\0" \
 178         "mpurate=500\0" \
 179         "vram=12M\0" \
 180         "dvimode=1024x768MR-16@60\0" \
 181         "defaultdisplay=dvi\0" \
 182         "mmcdev=0\0" \
 183         "mmcroot=/dev/mmcblk0p2 rw\0" \
 184         "mmcrootfstype=ext4 rootwait\0" \
 185         "nandroot=/dev/mtdblock4 rw\0" \
 186         "nandrootfstype=ubifs\0" \
 187         "mmcargs=setenv bootargs console=${console} " \
 188                 "mpurate=${mpurate} " \
 189                 "vram=${vram} " \
 190                 "omapfb.mode=dvi:${dvimode} " \
 191                 "omapfb.debug=y " \
 192                 "omapdss.def_disp=${defaultdisplay} " \
 193                 "root=${mmcroot} " \
 194                 "rootfstype=${mmcrootfstype}\0" \
 195         "nandargs=setenv bootargs console=${console} " \
 196                 "mpurate=${mpurate} " \
 197                 "vram=${vram} " \
 198                 "omapfb.mode=dvi:${dvimode} " \
 199                 "omapfb.debug=y " \
 200                 "omapdss.def_disp=${defaultdisplay} " \
 201                 "root=${nandroot} " \
 202                 "rootfstype=${nandrootfstype}\0" \
 203         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 204         "bootscript=echo Running bootscript from mmc ...; " \
 205                 "source ${loadaddr}\0" \
 206         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 207         "mmcboot=echo Booting from mmc ...; " \
 208                 "run mmcargs; " \
 209                 "bootm ${loadaddr}\0" \
 210         "nandboot=echo Booting from nand ...; " \
 211                 "run nandargs; " \
 212                 "nand read ${loadaddr} 2a0000 400000; " \
 213                 "bootm ${loadaddr}\0" \
 214
 215 #define CONFIG_BOOTCOMMAND \
 216         "mmc dev ${mmcdev}; if mmc rescan; then " \
 217                 "if run loadbootscript; then " \
 218                         "run bootscript; " \
 219                 "else " \
 220                         "if run loaduimage; then " \
 221                                 "run mmcboot; " \
 222                         "else run nandboot; " \
 223                         "fi; " \
 224                 "fi; " \
 225         "else run nandboot; fi"
 226
 227 /*
 228  * Miscellaneous configurable options
 229  */
 230 #define CONFIG_AUTO_COMPLETE
 231 #define CONFIG_CMDLINE_EDITING
 232 #define CONFIG_TIMESTAMP
 233 #define CONFIG_SYS_AUTOLOAD             "no"
 234 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 235 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 236 #define CONFIG_SYS_PROMPT               "CM-T3x # "
 237 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 238 /* Print Buffer Size */
 239 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 240                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 241 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 242 /* Boot Argument Buffer Size */
 243 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 244
 245 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 246                                                                 /* works on */
 247 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 248                                         0x01F00000) /* 31MB */
 249
 250 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 251                                                         /* load address */
 252
 253 /*
 254  * OMAP3 has 12 GP timers, they can be driven by the system clock
 255  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 256  * This rate is divided by a local divisor.
 257  */
 258 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 259 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 260 #define CONFIG_SYS_HZ                   1000
 261
 262 /*-----------------------------------------------------------------------
 263  * Physical Memory Map
 264  */
 265 #define CONFIG_NR_DRAM_BANKS    1       /* CS1 is never populated */
 266 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 267
 268 /*-----------------------------------------------------------------------
 269  * FLASH and environment organization
 270  */
 271
 272 /* **** PISMO SUPPORT *** */
 273 /* Configure the PISMO */
 274 #define PISMO1_NAND_SIZE                GPMC_SIZE_128M
 275
 276 /* Monitor at start of flash */
 277 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 278 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 279
 280 #define CONFIG_ENV_IS_IN_NAND
 281 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 282 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 283 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 284
 285 #if defined(CONFIG_CMD_NET)
 286 #define CONFIG_SMC911X
 287 #define CONFIG_SMC911X_32_BIT
 288 #define CM_T3X_SMC911X_BASE     0x2C000000
 289 #define SB_T35_SMC911X_BASE     (CM_T3X_SMC911X_BASE + (16 << 20))
 290 #define CONFIG_SMC911X_BASE     CM_T3X_SMC911X_BASE
 291 #endif /* (CONFIG_CMD_NET) */
 292
 293 /* additions for new relocation code, must be added to all boards */
 294 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 295 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 296 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 297 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR +     \
 298                                          CONFIG_SYS_INIT_RAM_SIZE -     \
 299                                          GENERATED_GBL_DATA_SIZE)
 300
 301 /* Status LED */
 302 #define CONFIG_STATUS_LED               /* Status LED enabled */
 303 #define CONFIG_BOARD_SPECIFIC_LED
 304 #define STATUS_LED_GREEN                0
 305 #define STATUS_LED_BIT                  STATUS_LED_GREEN
 306 #define STATUS_LED_STATE                STATUS_LED_ON
 307 #define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
 308 #define STATUS_LED_BOOT                 STATUS_LED_BIT
 309 #define GREEN_LED_GPIO                  186 /* CM-T35 Green LED is GPIO186 */
 310
 311 #define CONFIG_SPLASHIMAGE_GUARD
 312
 313 /* GPIO banks */
 314 #ifdef CONFIG_STATUS_LED
 315 #define CONFIG_OMAP3_GPIO_6     /* GPIO186 is in GPIO bank 6  */
 316 #endif
 317
 318 /* Display Configuration */
 319 #define CONFIG_OMAP3_GPIO_2
 320 #define CONFIG_VIDEO_OMAP3
 321 #define LCD_BPP         LCD_COLOR16
 322
 323 #define CONFIG_LCD
 324 #define CONFIG_SPLASH_SCREEN
 325 #define CONFIG_CMD_BMP
 326 #define CONFIG_BMP_16BPP
 327
 328 #endif /* __CONFIG_H */