include/configs/coreboot.h

   1 /*
   2  * Copyright (c) 2011 The Chromium OS Authors.
   3  * (C) Copyright 2008
   4  * Graeme Russ, graeme.russ@gmail.com.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <asm/ibmpc.h>
  26 /*
  27  * board/config.h - configuration options, board specific
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37 #define CONFIG_SYS_COREBOOT
  38 #define CONFIG_SHOW_BOOT_PROGRESS
  39 #define CONFIG_LAST_STAGE_INIT
  40 #define CONFIG_X86_NO_RESET_VECTOR
  41 #define CONFIG_SYS_VSNPRINTF
  42 #define CONFIG_ZBOOT_32
  43
  44 /*-----------------------------------------------------------------------
  45  * Watchdog Configuration
  46  */
  47 #undef CONFIG_WATCHDOG
  48 #undef CONFIG_HW_WATCHDOG
  49
  50 /* SATA AHCI storage */
  51
  52 #define CONFIG_SCSI_AHCI
  53
  54 #ifdef CONFIG_SCSI_AHCI
  55 #define CONFIG_SYS_64BIT_LBA
  56 #define CONFIG_SATA_INTEL               1
  57 #define CONFIG_SCSI_DEV_LIST            {PCI_VENDOR_ID_INTEL, \
  58                         PCI_DEVICE_ID_INTEL_NM10_AHCI},       \
  59         {PCI_VENDOR_ID_INTEL,           \
  60                         PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
  61         {PCI_VENDOR_ID_INTEL, \
  62                         PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
  63         {PCI_VENDOR_ID_INTEL,           \
  64                         PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
  65
  66 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     2
  67 #define CONFIG_SYS_SCSI_MAX_LUN         1
  68 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  69                                          CONFIG_SYS_SCSI_MAX_LUN)
  70 #endif
  71
  72 /* Generic TPM interfaced through LPC bus */
  73 #define CONFIG_GENERIC_LPC_TPM
  74 #define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
  75
  76 /*-----------------------------------------------------------------------
  77  * Real Time Clock Configuration
  78  */
  79 #define CONFIG_RTC_MC146818
  80 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS  0
  81 #define CONFIG_SYS_ISA_IO      CONFIG_SYS_ISA_IO_BASE_ADDRESS
  82
  83 /*-----------------------------------------------------------------------
  84  * Serial Configuration
  85  */
  86 #define CONFIG_CONS_INDEX               1
  87 #define CONFIG_SYS_NS16550
  88 #define CONFIG_SYS_NS16550_SERIAL
  89 #define CONFIG_SYS_NS16550_REG_SIZE     1
  90 #define CONFIG_SYS_NS16550_CLK          1843200
  91 #define CONFIG_BAUDRATE                 9600
  92 #define CONFIG_SYS_BAUDRATE_TABLE       {300, 600, 1200, 2400, 4800, \
  93                                          9600, 19200, 38400, 115200}
  94 #define CONFIG_SYS_NS16550_COM1 UART0_BASE
  95 #define CONFIG_SYS_NS16550_COM2 UART1_BASE
  96 #define CONFIG_SYS_NS16550_PORT_MAPPED
  97
  98 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,eserial0\0" \
  99                                         "stdout=vga,eserial0,cbmem\0" \
 100                                         "stderr=vga,eserial0,cbmem\0"
 101
 102 #define CONFIG_CONSOLE_MUX
 103 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 104 #define CONFIG_SYS_STDIO_DEREGISTER
 105 #define CONFIG_CBMEM_CONSOLE
 106
 107 /* max. 1 IDE bus       */
 108 #define CONFIG_SYS_IDE_MAXBUS           1
 109 /* max. 1 drive per IDE bus */
 110 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS * 1)
 111
 112 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_ISA_IO_BASE_ADDRESS
 113 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x01f0
 114 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0170
 115 #define CONFIG_SYS_ATA_DATA_OFFSET      0
 116 #define CONFIG_SYS_ATA_REG_OFFSET       0
 117 #define CONFIG_SYS_ATA_ALT_OFFSET       0x200
 118
 119
 120 #define CONFIG_SUPPORT_VFAT
 121 /************************************************************
 122  * ATAPI support (experimental)
 123  ************************************************************/
 124 #define CONFIG_ATAPI
 125
 126 /************************************************************
 127  * DISK Partition support
 128  ************************************************************/
 129 #define CONFIG_EFI_PARTITION
 130 #define CONFIG_DOS_PARTITION
 131 #define CONFIG_MAC_PARTITION
 132 #define CONFIG_ISO_PARTITION            /* Experimental */
 133
 134 #define CONFIG_CMD_PART
 135 #define CONFIG_CMD_CBFS
 136 #define CONFIG_CMD_EXT4
 137 #define CONFIG_CMD_EXT4_WRITE
 138 #define CONFIG_PARTITION_UUIDS
 139
 140 /*-----------------------------------------------------------------------
 141  * Video Configuration
 142  */
 143 #define CONFIG_VIDEO
 144 #define CONFIG_VIDEO_COREBOOT
 145 #define CONFIG_VIDEO_SW_CURSOR
 146 #define VIDEO_FB_16BPP_WORD_SWAP
 147 #define CONFIG_I8042_KBD
 148 #define CONFIG_CFB_CONSOLE
 149 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 150
 151 /* x86 GPIOs are accessed through a PCI device */
 152 #define CONFIG_INTEL_ICH6_GPIO
 153
 154 /*-----------------------------------------------------------------------
 155  * Command line configuration.
 156  */
 157 #include <config_cmd_default.h>
 158
 159 #define CONFIG_CMD_BDI
 160 #define CONFIG_CMD_BOOTD
 161 #define CONFIG_CMD_CONSOLE
 162 #define CONFIG_CMD_DATE
 163 #define CONFIG_CMD_ECHO
 164 #undef CONFIG_CMD_FLASH
 165 #define CONFIG_CMD_FPGA
 166 #define CONFIG_CMD_GPIO
 167 #define CONFIG_CMD_IMI
 168 #undef CONFIG_CMD_IMLS
 169 #define CONFIG_CMD_IRQ
 170 #define CONFIG_CMD_ITEST
 171 #define CONFIG_CMD_LOADB
 172 #define CONFIG_CMD_LOADS
 173 #define CONFIG_CMD_MEMORY
 174 #define CONFIG_CMD_MISC
 175 #define CONFIG_CMD_NET
 176 #undef CONFIG_CMD_NFS
 177 #define CONFIG_CMD_PCI
 178 #define CONFIG_CMD_PING
 179 #define CONFIG_CMD_RUN
 180 #define CONFIG_CMD_SAVEENV
 181 #define CONFIG_CMD_SETGETDCR
 182 #define CONFIG_CMD_SOURCE
 183 #define CONFIG_CMD_XIMG
 184 #define CONFIG_CMD_IDE
 185 #define CONFIG_CMD_FAT
 186 #define CONFIG_CMD_EXT2
 187
 188 #define CONFIG_CMD_ZBOOT
 189
 190 #define CONFIG_BOOTDELAY        2
 191 #define CONFIG_BOOTARGS         "root=/dev/mtdblock0 console=ttyS0,9600"
 192
 193 #if defined(CONFIG_CMD_KGDB)
 194 #define CONFIG_KGDB_BAUDRATE                    115200
 195 #define CONFIG_KGDB_SER_INDEX                   2
 196 #endif
 197
 198 /*
 199  * Miscellaneous configurable options
 200  */
 201 #define CONFIG_SYS_LONGHELP
 202 #define CONFIG_SYS_PROMPT                       "boot > "
 203 #define CONFIG_SYS_CBSIZE                       256
 204 #define CONFIG_SYS_PBSIZE                       (CONFIG_SYS_CBSIZE + \
 205                                                  sizeof(CONFIG_SYS_PROMPT) + \
 206                                                  16)
 207 #define CONFIG_SYS_MAXARGS                      16
 208 #define CONFIG_SYS_BARGSIZE                     CONFIG_SYS_CBSIZE
 209
 210 #define CONFIG_SYS_MEMTEST_START                0x00100000
 211 #define CONFIG_SYS_MEMTEST_END                  0x01000000
 212 #define CONFIG_SYS_LOAD_ADDR                    0x100000
 213 #define CONFIG_SYS_HZ                           1000
 214 #define CONFIG_SYS_X86_ISR_TIMER
 215
 216 /*-----------------------------------------------------------------------
 217  * SDRAM Configuration
 218  */
 219 #define CONFIG_NR_DRAM_BANKS                    4
 220
 221 /* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
 222 #undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
 223 #undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
 224 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
 225 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
 226
 227 /*-----------------------------------------------------------------------
 228  * CPU Features
 229  */
 230
 231 #define CONFIG_SYS_GENERIC_TIMER
 232 #define CONFIG_SYS_PCAT_INTERRUPTS
 233 #define CONFIG_SYS_NUM_IRQS                     16
 234
 235 /*-----------------------------------------------------------------------
 236  * Memory organization:
 237  * 32kB Stack
 238  * 16kB Cache-As-RAM @ 0x19200000
 239  * 256kB Monitor
 240  * (128kB + Environment Sector Size) malloc pool
 241  */
 242 #define CONFIG_SYS_STACK_SIZE                   (32 * 1024)
 243 #define CONFIG_SYS_CAR_ADDR                     0x19200000
 244 #define CONFIG_SYS_CAR_SIZE                     (16 * 1024)
 245 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 246 #define CONFIG_SYS_MONITOR_LEN                  (256 * 1024)
 247 #define CONFIG_SYS_MALLOC_LEN                   (0x20000 + 128 * 1024)
 248
 249
 250 /* allow to overwrite serial and ethaddr */
 251 #define CONFIG_ENV_OVERWRITE
 252
 253 /*-----------------------------------------------------------------------
 254  * FLASH configuration
 255  */
 256 #define CONFIG_SYS_NO_FLASH
 257 #undef CONFIG_FLASH_CFI_DRIVER
 258 #define CONFIG_SYS_MAX_FLASH_SECT               1
 259 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 260
 261 /*-----------------------------------------------------------------------
 262  * Environment configuration
 263  */
 264 #define CONFIG_ENV_IS_NOWHERE
 265 #define CONFIG_ENV_SIZE                 0x01000
 266
 267 /*-----------------------------------------------------------------------
 268  * PCI configuration
 269  */
 270 #define CONFIG_PCI
 271
 272 #define CONFIG_EXTRA_ENV_SETTINGS \
 273         CONFIG_STD_DEVICES_SETTINGS
 274
 275 #endif  /* __CONFIG_H */