include/configs/eb_cpux9k2.h

   1 /*
   2  * (C) Copyright 2008-2009
   3  * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
   4  * Jens Scharsig <esw@bus-elektronik.de>
   5  *
   6  * Configuation settings for the EB+CPUx9K2 board.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef _CONFIG_EB_CPUx9K2_H_
  28 #define _CONFIG_EB_CPUx9K2_H_
  29
  30 /*--------------------------------------------------------------------------*/
  31
  32 #define CONFIG_AT91RM9200               /* It's an Atmel AT91RM9200 SoC */
  33 #define CONFIG_EB_CPUX9K2               /* on an EP+CPUX9K2 Board       */
  34 #define USE_920T_MMU
  35
  36 #define CONFIG_VERSION_VARIABLE
  37 #define CONFIG_IDENT_STRING     " on EB+CPUx9K2"
  38
  39 #include <asm/hardware.h>       /* needed for port definitions */
  40
  41 #define CONFIG_MISC_INIT_R
  42 #define CONFIG_BOARD_EARLY_INIT_F
  43
  44 #define MACH_TYPE_EB_CPUX9K2            1977
  45 #define CONFIG_MACH_TYPE                MACH_TYPE_EB_CPUX9K2
  46
  47 #define CONFIG_SYS_CACHELINE_SIZE       32
  48 #define CONFIG_SYS_DCACHE_OFF
  49
  50 /*--------------------------------------------------------------------------*/
  51 #ifndef CONFIG_RAMBOOT
  52 #define CONFIG_SYS_TEXT_BASE            0x00000000
  53 #else
  54 #define CONFIG_SKIP_LOWLEVEL_INIT
  55 #define CONFIG_SYS_TEXT_BASE            0x21f00000
  56 #endif
  57 #define CONFIG_SYS_LOAD_ADDR            0x21000000  /* default load address */
  58
  59 #define CONFIG_SYS_BOOT_SIZE            0x00 /* 0 KBytes */
  60 #define CONFIG_SYS_U_BOOT_BASE          PHYS_FLASH_1
  61 #define CONFIG_SYS_U_BOOT_SIZE          0x60000 /* 384 KBytes */
  62
  63 #define CONFIG_BOOT_RETRY_TIME          30
  64 #define CONFIG_CMDLINE_EDITING
  65
  66 #define CONFIG_SYS_PROMPT       "U-Boot> "      /* Monitor Command Prompt */
  67 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
  68 #define CONFIG_SYS_MAXARGS      32              /* max number of command args */
  69 #define CONFIG_SYS_PBSIZE       \
  70         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  71
  72 /*
  73  * ARM asynchronous clock
  74  */
  75
  76 #define AT91C_MAIN_CLOCK        179404800       /* from 12.288 MHz * 73 / 5 */
  77 #define AT91C_MASTER_CLOCK      (AT91C_MAIN_CLOCK / 3)
  78 #define CONFIG_SYS_HZ           1000
  79 #define CONFIG_SYS_HZ_CLOCK     (AT91C_MASTER_CLOCK / 2)
  80
  81 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock */
  82
  83 #define CONFIG_CMDLINE_TAG              1
  84 #define CONFIG_SETUP_MEMORY_TAGS        1
  85 #define CONFIG_INITRD_TAG               1
  86
  87 #define CONFIG_SYS_USE_MAIN_OSCILLATOR  1
  88 /* flash */
  89 #define CONFIG_SYS_EBI_CFGR_VAL         0x00000000
  90 #define CONFIG_SYS_SMC_CSR0_VAL         0x00003284 /* 16bit, 2 TDF, 4 WS */
  91
  92 /* clocks */
  93 #define CONFIG_SYS_PLLAR_VAL            0x20483E05 /* 179.4048 MHz for PCK */
  94 #define CONFIG_SYS_PLLBR_VAL            0x104C3E0A /* 47.3088 MHz (for USB) */
  95 #define CONFIG_SYS_MCKR_VAL             0x00000202 /* PCK/3 = MCK Clock */
  96
  97 /*
  98  * Size of malloc() pool
  99  */
 100
 101 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 520*1024)
 102
 103 /*
 104  * sdram
 105  */
 106
 107 #define CONFIG_NR_DRAM_BANKS            1
 108
 109 #define CONFIG_SYS_SDRAM_BASE           0x20000000
 110 #define CONFIG_SYS_SDRAM_SIZE           0x04000000  /* 64 megs */
 111 #define CONFIG_SYS_INIT_SP_ADDR         0x00204000  /* use internal SRAM */
 112
 113 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
 114 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 115                                         CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
 116                                         CONFIG_SYS_MALLOC_LEN)
 117
 118 #define CONFIG_SYS_PIOC_ASR_VAL         0xFFFF0000 /* PIOC as D16/D31 */
 119 #define CONFIG_SYS_PIOC_BSR_VAL         0x00000000
 120 #define CONFIG_SYS_PIOC_PDR_VAL         0xFFFF0000
 121 #define CONFIG_SYS_EBI_CSA_VAL          0x00000002 /* CS1=SDRAM */
 122 #define CONFIG_SYS_SDRC_CR_VAL          0x2188c159 /* set up the SDRAM */
 123 #define CONFIG_SYS_SDRAM                0x20000000 /* address of the SDRAM */
 124 #define CONFIG_SYS_SDRAM1               0x20000080 /* address of the SDRAM */
 125 #define CONFIG_SYS_SDRAM_VAL            0x00000000 /* value written to SDRAM */
 126 #define CONFIG_SYS_SDRC_MR_VAL          0x00000002 /* Precharge All */
 127 #define CONFIG_SYS_SDRC_MR_VAL1         0x00000004 /* refresh */
 128 #define CONFIG_SYS_SDRC_MR_VAL2         0x00000003 /* Load Mode Register */
 129 #define CONFIG_SYS_SDRC_MR_VAL3         0x00000000 /* Normal Mode */
 130 #define CONFIG_SYS_SDRC_TR_VAL          0x000002E0 /* Write refresh rate */
 131
 132 /*
 133  * Command line configuration
 134  */
 135
 136 #include <config_cmd_default.h>
 137
 138 #define CONFIG_CMD_BMP
 139 #define CONFIG_CMD_DATE
 140 #define CONFIG_CMD_DHCP
 141 #define CONFIG_CMD_I2C
 142 #define CONFIG_CMD_JFFS2
 143 #define CONFIG_CMD_MII
 144 #define CONFIG_CMD_NAND
 145 #define CONFIG_CMD_PING
 146 #define CONFIG_I2C_CMD_NO_FLAT
 147 #define CONFIG_I2C_CMD_TREE
 148 #define CONFIG_CMD_USB
 149 #define CONFIG_CMD_FAT
 150
 151 #define CONFIG_SYS_LONGHELP
 152
 153 /*
 154  * Filesystems
 155  */
 156
 157 #define CONFIG_JFFS2_NAND               1
 158
 159 #ifndef CONFIG_JFFS2_CMDLINE
 160 #define CONFIG_JFFS2_DEV                "nand0"
 161 #define CONFIG_JFFS2_PART_OFFSET        0
 162 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 163 #else
 164 #define MTDIDS_DEFAULT          "nor0=0,nand0=1"
 165 #define MTDPARTS_DEFAULT        "mtdparts="                             \
 166                                         "0:"                            \
 167                                         "384k(U-Boot),"                 \
 168                                         "128k(Env),"                    \
 169                                         "128k(Splash),"                 \
 170                                         "4M(Kernel),"                   \
 171                                         "-(FS)"                         \
 172                                         ";"                             \
 173                                         "1:"                            \
 174                                         "-(jffs2)"
 175 #endif /* CONFIG_JFFS2_CMDLINE */
 176
 177 /*
 178  * Hardware drivers
 179  */
 180 #define CONFIG_USB_ATMEL
 181 #define CONFIG_USB_OHCI_NEW
 182 #define CONFIG_AT91C_PQFP_UHPBUG
 183 #define CONFIG_USB_STORAGE
 184 #define CONFIG_DOS_PARTITION
 185 #define CONFIG_ISO_PARTITION
 186 #define CONFIG_EFI_PARTITION
 187
 188 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      1
 189 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 190 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00300000
 191 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91rm9200"
 192
 193 /*
 194  * UART/CONSOLE
 195  */
 196
 197 #define CONFIG_BAUDRATE 115200
 198 #define CONFIG_ATMEL_USART
 199 #define CONFIG_USART_BASE       ATMEL_BASE_DBGU
 200 #define CONFIG_USART_ID         0/* ignored in arm */
 201
 202 /*
 203  * network
 204  */
 205
 206 #define CONFIG_NET_RETRY_COUNT          10
 207 #define CONFIG_RESET_PHY_R              1
 208
 209 #define CONFIG_DRIVER_AT91EMAC          1
 210 #define CONFIG_DRIVER_AT91EMAC_QUIET    1
 211 #define CONFIG_SYS_RX_ETH_BUFFER        8
 212 #define CONFIG_MII                      1
 213
 214 /*
 215  * BOOTP options
 216  */
 217 #define CONFIG_BOOTP_BOOTFILESIZE
 218 #define CONFIG_BOOTP_BOOTPATH
 219 #define CONFIG_BOOTP_GATEWAY
 220 #define CONFIG_BOOTP_HOSTNAME
 221
 222 /*
 223  * I2C-Bus
 224  */
 225
 226 #define CONFIG_SYS_I2C_SPEED            50000
 227 #define CONFIG_SYS_I2C_SLAVE            0               /* not used */
 228
 229 #ifndef CONFIG_HARD_I2C
 230 #define CONFIG_SOFT_I2C
 231
 232 /* Software  I2C driver configuration */
 233
 234 #define AT91_PIN_SDA                    (1<<25)         /* AT91C_PIO_PA25 */
 235 #define AT91_PIN_SCL                    (1<<26)         /* AT91C_PIO_PA26 */
 236
 237 #define CONFIG_SYS_I2C_INIT_BOARD
 238
 239 #define I2C_INIT        i2c_init_board();
 240 #define I2C_ACTIVE      writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
 241 #define I2C_TRISTATE    writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
 242 #define I2C_READ        ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
 243 #define I2C_SDA(bit)                                            \
 244         if (bit)                                                \
 245                 writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr);      \
 246         else                                                    \
 247                 writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
 248 #define I2C_SCL(bit)                                            \
 249         if (bit)                                                \
 250                 writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr);     \
 251         else                                                    \
 252                 writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
 253
 254 #define I2C_DELAY       udelay(2500000/CONFIG_SYS_I2C_SPEED)
 255
 256 #endif  /* CONFIG_HARD_I2C */
 257
 258 /* I2C-RTC */
 259
 260 #ifdef CONFIG_CMD_DATE
 261 #define CONFIG_RTC_DS1338
 262 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 263 #endif
 264
 265 /* EEPROM */
 266
 267 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 268 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 269
 270 /* FLASH organization */
 271
 272 /*  NOR-FLASH */
 273 #define CONFIG_FLASH_SHOW_PROGRESS      45
 274
 275 #define CONFIG_FLASH_CFI_DRIVER 1
 276
 277 #define PHYS_FLASH_1                    0x10000000
 278 #define PHYS_FLASH_SIZE                 0x01000000  /* 16 megs main flash */
 279 #define CONFIG_SYS_FLASH_CFI            1
 280 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 281
 282 #define CONFIG_SYS_FLASH_PROTECTION     1
 283 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 284 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 285 #define CONFIG_SYS_MAX_FLASH_SECT       512
 286 #define CONFIG_SYS_FLASH_ERASE_TOUT     6000
 287 #define CONFIG_SYS_FLASH_WRITE_TOUT     2000
 288
 289 /* NAND */
 290
 291 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 292 #define CONFIG_SYS_NAND_BASE            0x40000000
 293 #define CONFIG_SYS_NAND_DBW_8           1
 294
 295 /* Status LED's */
 296
 297 #define CONFIG_STATUS_LED               1
 298 #define CONFIG_BOARD_SPECIFIC_LED       1
 299
 300 #define STATUS_LED_BOOT                 1
 301 #define STATUS_LED_ACTIVE               0
 302
 303 #define STATUS_LED_BIT                  1       /* AT91C_PIO_PD0 green LED */
 304 #define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
 305 #define STATUS_LED_STATE                STATUS_LED_OFF          /* BLINKING */
 306 #define STATUS_LED_BIT1                 2       /* AT91C_PIO_PD1  red LED */
 307 #define STATUS_LED_STATE1               STATUS_LED_ON           /* BLINKING */
 308 #define STATUS_LED_PERIOD1              (CONFIG_SYS_HZ / 4)
 309
 310 #define CONFIG_VIDEO                    1
 311
 312 /* Options */
 313
 314 #ifdef CONFIG_VIDEO
 315
 316 #define CONFIG_VIDEO_VCXK                       1
 317
 318 #define CONFIG_SPLASH_SCREEN                    1
 319
 320 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       4
 321 #define CONFIG_SYS_VCXK_BASE    0x30000000
 322
 323 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         (1<<3)
 324 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        piob
 325 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         odr
 326
 327 #define CONFIG_SYS_VCXK_ENABLE_PIN              (1<<5)
 328 #define CONFIG_SYS_VCXK_ENABLE_PORT             piob
 329 #define CONFIG_SYS_VCXK_ENABLE_DDR              oer
 330
 331 #define CONFIG_SYS_VCXK_REQUEST_PIN             (1<<2)
 332 #define CONFIG_SYS_VCXK_REQUEST_PORT            piob
 333 #define CONFIG_SYS_VCXK_REQUEST_DDR             oer
 334
 335 #define CONFIG_SYS_VCXK_INVERT_PIN              (1<<4)
 336 #define CONFIG_SYS_VCXK_INVERT_PORT             piob
 337 #define CONFIG_SYS_VCXK_INVERT_DDR              oer
 338
 339 #define CONFIG_SYS_VCXK_RESET_PIN               (1<<6)
 340 #define CONFIG_SYS_VCXK_RESET_PORT              piob
 341 #define CONFIG_SYS_VCXK_RESET_DDR               oer
 342
 343 #endif  /* CONFIG_VIDEO */
 344
 345 /* Environment */
 346
 347 #define CONFIG_BOOTDELAY                5
 348
 349 #define CONFIG_ENV_IS_IN_FLASH          1
 350 #define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0x60000)
 351 #define CONFIG_ENV_SIZE                 0x20000 /* sectors are 128K here */
 352
 353 #define CONFIG_BAUDRATE                 115200
 354
 355 #define CONFIG_BOOTCOMMAND              "run nfsboot"
 356
 357 #define CONFIG_NFSBOOTCOMMAND                                           \
 358                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 359                 "run bootargsdefaults;"                                 \
 360                 "set bootargs $(bootargs) boot=nfs "                    \
 361                 ";echo $(bootargs)"                                     \
 362         ";bootm"
 363
 364 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 365         "displaywidth=256\0"                                            \
 366         "displayheight=512\0"                                           \
 367         "displaybsteps=1023\0"                                          \
 368         "ubootaddr=10000000\0"                                          \
 369         "splashimage=10080000\0"                                        \
 370         "kerneladdr=100A0000\0"                                         \
 371         "kernelsize=00400000\0"                                         \
 372         "rootfsaddr=104A0000\0"                                         \
 373         "copy_addr=21200000\0"                                          \
 374         "rootfssize=00B60000\0"                                         \
 375         "bootargsdefaults=set bootargs "                                \
 376                 "console=ttyS0,115200 "                                 \
 377                 "video=vcxk_fb:xres:${displaywidth},"                   \
 378                         "yres:${displayheight},"                        \
 379                         "bres:${displaybsteps} "                        \
 380                 "mem=62M "                                              \
 381                 "panic=10 "                                             \
 382                 "uboot=\\\"${ver}\\\" "                                 \
 383                 "\0"                                                    \
 384         "update_kernel=protect off $(kerneladdr) +$(kernelsize);"       \
 385                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 386                 "erase $(kerneladdr) +$(kernelsize);"                   \
 387                 "cp.b $(fileaddr) $(kerneladdr) $(filesize);"           \
 388                 "protect on $(kerneladdr) +$(kernelsize)"               \
 389                 "\0"                                                    \
 390         "update_root=protect off $(rootfsaddr) +$(rootfssize);"         \
 391                 "dhcp $(copy_addr) rfs;"                                \
 392                 "erase $(rootfsaddr) +$(rootfssize);"                   \
 393                 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);"           \
 394                 "\0"                                                    \
 395         "update_uboot=protect off 10000000 1005FFFF;"                   \
 396                 "dhcp $(copy_addr) u-boot_eb_cpux9k2;"                  \
 397                 "erase 10000000 1005FFFF;"                              \
 398                 "cp.b $(fileaddr) $(ubootaddr) $(filesize);"            \
 399                 "protect on 10000000 1005FFFF;reset\0"                  \
 400         "update_splash=protect off $(splashimage) +20000;"              \
 401                 "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;"              \
 402                 "erase $(splashimage) +20000;"                          \
 403                 "cp.b $(fileaddr) 10080000 $(filesize);"                \
 404                 "protect on $(splashimage) +20000;reset\0"              \
 405         "emergency=run bootargsdefaults;"                               \
 406                 "set bootargs $(bootargs) root=initramfs boot=emergency " \
 407                 ";bootm $(kerneladdr)\0"                                \
 408         "netemergency=run bootargsdefaults;"                            \
 409                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 410                 "set bootargs $(bootargs) root=initramfs boot=emergency " \
 411                 ";bootm $(copy_addr)\0"                                 \
 412         "norboot=run bootargsdefaults;"                                 \
 413                 "set bootargs $(bootargs) root=initramfs boot=local "   \
 414                 ";bootm $(kerneladdr)\0"                                \
 415         "nandboot=run bootargsdefaults;"                                \
 416                 "set bootargs $(bootargs) root=initramfs boot=nand "    \
 417                 ";bootm $(kerneladdr)\0"                                \
 418         " "
 419
 420 /*--------------------------------------------------------------------------*/
 421
 422 #endif
 423
 424 /* EOF */