include/configs/eb_cpux9k2.h

   1 /*
   2  * (C) Copyright 2008-2009
   3  * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
   4  * Jens Scharsig <esw@bus-elektronik.de>
   5  *
   6  * Configuation settings for the EB+CPUx9K2 board.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef _CONFIG_EB_CPUx9K2_H_
  28 #define _CONFIG_EB_CPUx9K2_H_
  29
  30 /*--------------------------------------------------------------------------*/
  31
  32 #define CONFIG_AT91RM9200               /* It's an Atmel AT91RM9200 SoC */
  33 #define CONFIG_EB_CPUX9K2               /* on an EP+CPUX9K2 Board       */
  34 #define USE_920T_MMU
  35
  36 #define CONFIG_VERSION_VARIABLE
  37 #define CONFIG_IDENT_STRING     " on EB+CPUx9K2"
  38
  39 #include <asm/hardware.h>       /* needed for port definitions */
  40
  41 #define CONFIG_MISC_INIT_R
  42 #define CONFIG_BOARD_EARLY_INIT_F
  43
  44 #define MACH_TYPE_EB_CPUX9K2            1977
  45 #define CONFIG_MACH_TYPE                MACH_TYPE_EB_CPUX9K2
  46 /*--------------------------------------------------------------------------*/
  47 #define CONFIG_SYS_TEXT_BASE            0x00000000
  48 #define CONFIG_SYS_LOAD_ADDR            0x21000000  /* default load address */
  49
  50 #define CONFIG_SYS_BOOT_SIZE            0x00 /* 0 KBytes */
  51 #define CONFIG_SYS_U_BOOT_BASE          PHYS_FLASH_1
  52 #define CONFIG_SYS_U_BOOT_SIZE          0x60000 /* 384 KBytes */
  53
  54
  55 #define CONFIG_BOOT_RETRY_TIME          30
  56 #define CONFIG_CMDLINE_EDITING
  57
  58 #define CONFIG_SYS_PROMPT       "U-Boot> "      /* Monitor Command Prompt */
  59 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
  60 #define CONFIG_SYS_MAXARGS      32              /* max number of command args */
  61 #define CONFIG_SYS_PBSIZE       \
  62         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  63
  64 /*
  65  * ARM asynchronous clock
  66  */
  67
  68 #define AT91C_MAIN_CLOCK        179404800       /* from 12.288 MHz * 73 / 5 */
  69 #define AT91C_MASTER_CLOCK      (AT91C_MAIN_CLOCK / 3)
  70 #define CONFIG_SYS_HZ           1000
  71 #define CONFIG_SYS_HZ_CLOCK     (AT91C_MASTER_CLOCK / 2)
  72
  73 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock */
  74
  75 #define CONFIG_CMDLINE_TAG              1
  76 #define CONFIG_SETUP_MEMORY_TAGS        1
  77 #define CONFIG_INITRD_TAG               1
  78
  79 #define CONFIG_SYS_USE_MAIN_OSCILLATOR  1
  80 /* flash */
  81 #define CONFIG_SYS_EBI_CFGR_VAL         0x00000000
  82 #define CONFIG_SYS_SMC_CSR0_VAL         0x00003284 /* 16bit, 2 TDF, 4 WS */
  83
  84 /* clocks */
  85 #define CONFIG_SYS_PLLAR_VAL            0x20483E05 /* 179.4048 MHz for PCK */
  86 #define CONFIG_SYS_PLLBR_VAL            0x104C3E0A /* 47.3088 MHz (for USB) */
  87 #define CONFIG_SYS_MCKR_VAL             0x00000202 /* PCK/3 = MCK Clock */
  88
  89 /*
  90  * Size of malloc() pool
  91  */
  92
  93 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 520*1024)
  94
  95 /*
  96  * sdram
  97  */
  98
  99 #define CONFIG_NR_DRAM_BANKS            1
 100
 101 #define CONFIG_SYS_SDRAM_BASE           0x20000000
 102 #define CONFIG_SYS_SDRAM_SIZE           0x04000000  /* 64 megs */
 103 #define CONFIG_SYS_INIT_SP_ADDR         0x00204000  /* use internal SRAM */
 104
 105 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
 106 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 107                                         CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
 108                                         CONFIG_SYS_MALLOC_LEN)
 109
 110 #define CONFIG_SYS_PIOC_ASR_VAL         0xFFFF0000 /* PIOC as D16/D31 */
 111 #define CONFIG_SYS_PIOC_BSR_VAL         0x00000000
 112 #define CONFIG_SYS_PIOC_PDR_VAL         0xFFFF0000
 113 #define CONFIG_SYS_EBI_CSA_VAL          0x00000002 /* CS1=SDRAM */
 114 #define CONFIG_SYS_SDRC_CR_VAL          0x2188c159 /* set up the SDRAM */
 115 #define CONFIG_SYS_SDRAM                0x20000000 /* address of the SDRAM */
 116 #define CONFIG_SYS_SDRAM1               0x20000080 /* address of the SDRAM */
 117 #define CONFIG_SYS_SDRAM_VAL            0x00000000 /* value written to SDRAM */
 118 #define CONFIG_SYS_SDRC_MR_VAL          0x00000002 /* Precharge All */
 119 #define CONFIG_SYS_SDRC_MR_VAL1         0x00000004 /* refresh */
 120 #define CONFIG_SYS_SDRC_MR_VAL2         0x00000003 /* Load Mode Register */
 121 #define CONFIG_SYS_SDRC_MR_VAL3         0x00000000 /* Normal Mode */
 122 #define CONFIG_SYS_SDRC_TR_VAL          0x000002E0 /* Write refresh rate */
 123
 124 /*
 125  * Command line configuration
 126  */
 127
 128 #include <config_cmd_default.h>
 129
 130 #define CONFIG_CMD_BMP
 131 #define CONFIG_CMD_DATE
 132 #define CONFIG_CMD_DHCP
 133 #define CONFIG_CMD_I2C
 134 #define CONFIG_CMD_JFFS2
 135 #define CONFIG_CMD_MII
 136 #define CONFIG_CMD_NAND
 137 #define CONFIG_CMD_PING
 138 #define CONFIG_I2C_CMD_NO_FLAT
 139 #define CONFIG_I2C_CMD_TREE
 140 #define CONFIG_CMD_USB
 141 #define CONFIG_CMD_FAT
 142
 143 #define CONFIG_SYS_LONGHELP
 144
 145 /*
 146  * Filesystems
 147  */
 148
 149 #define CONFIG_JFFS2_NAND               1
 150
 151 #ifndef CONFIG_JFFS2_CMDLINE
 152 #define CONFIG_JFFS2_DEV                "nand0"
 153 #define CONFIG_JFFS2_PART_OFFSET        0
 154 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 155 #else
 156 #define MTDIDS_DEFAULT          "nor0=0,nand0=1"
 157 #define MTDPARTS_DEFAULT        "mtdparts="                             \
 158                                         "0:"                            \
 159                                         "384k(U-Boot),"                 \
 160                                         "128k(Env),"                    \
 161                                         "128k(Splash),"                 \
 162                                         "4M(Kernel),"                   \
 163                                         "-(FS)"                         \
 164                                         ";"                             \
 165                                         "1:"                            \
 166                                         "-(jffs2)"
 167 #endif /* CONFIG_JFFS2_CMDLINE */
 168
 169 /*
 170  * Hardware drivers
 171  */
 172 #define CONFIG_USB_ATMEL
 173 #define CONFIG_USB_OHCI_NEW
 174 #define CONFIG_AT91C_PQFP_UHPBUG
 175 #define CONFIG_USB_STORAGE
 176 #define CONFIG_DOS_PARTITION
 177 #define CONFIG_ISO_PARTITION
 178 #define CONFIG_EFI_PARTITION
 179
 180 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      1
 181 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 182 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00300000
 183 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91rm9200"
 184
 185 /*
 186  * UART/CONSOLE
 187  */
 188
 189 #define CONFIG_BAUDRATE 115200
 190 #define CONFIG_ATMEL_USART
 191 #define CONFIG_USART_BASE       ATMEL_BASE_DBGU
 192 #define CONFIG_USART_ID         0/* ignored in arm */
 193
 194 /*
 195  * network
 196  */
 197
 198 #define CONFIG_NET_RETRY_COUNT          10
 199 #define CONFIG_RESET_PHY_R              1
 200
 201 #define CONFIG_DRIVER_AT91EMAC          1
 202 #define CONFIG_DRIVER_AT91EMAC_QUIET    1
 203 #define CONFIG_SYS_RX_ETH_BUFFER        8
 204 #define CONFIG_MII                      1
 205
 206 /*
 207  * BOOTP options
 208  */
 209 #define CONFIG_BOOTP_BOOTFILESIZE
 210 #define CONFIG_BOOTP_BOOTPATH
 211 #define CONFIG_BOOTP_GATEWAY
 212 #define CONFIG_BOOTP_HOSTNAME
 213
 214 /*
 215  * I2C-Bus
 216  */
 217
 218 #define CONFIG_SYS_I2C_SPEED            50000
 219 #define CONFIG_SYS_I2C_SLAVE            0               /* not used */
 220
 221 #ifndef CONFIG_HARD_I2C
 222 #define CONFIG_SOFT_I2C
 223
 224 /* Software  I2C driver configuration */
 225
 226 #define AT91_PIN_SDA                    (1<<25)         /* AT91C_PIO_PA25 */
 227 #define AT91_PIN_SCL                    (1<<26)         /* AT91C_PIO_PA26 */
 228
 229 #define CONFIG_SYS_I2C_INIT_BOARD
 230
 231 #define I2C_INIT        i2c_init_board();
 232 #define I2C_ACTIVE      writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
 233 #define I2C_TRISTATE    writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
 234 #define I2C_READ        ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
 235 #define I2C_SDA(bit)                                            \
 236         if (bit)                                                \
 237                 writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr);      \
 238         else                                                    \
 239                 writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
 240 #define I2C_SCL(bit)                                            \
 241         if (bit)                                                \
 242                 writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr);     \
 243         else                                                    \
 244                 writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
 245
 246 #define I2C_DELAY       udelay(2500000/CONFIG_SYS_I2C_SPEED)
 247
 248 #endif  /* CONFIG_HARD_I2C */
 249
 250 /* I2C-RTC */
 251
 252 #ifdef CONFIG_CMD_DATE
 253 #define CONFIG_RTC_DS1338
 254 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 255 #endif
 256
 257 /* EEPROM */
 258
 259 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 260 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 261
 262 /* FLASH organization */
 263
 264 /*  NOR-FLASH */
 265 #define CONFIG_FLASH_SHOW_PROGRESS      45
 266
 267 #define CONFIG_FLASH_CFI_DRIVER 1
 268
 269 #define PHYS_FLASH_1                    0x10000000
 270 #define PHYS_FLASH_SIZE                 0x01000000  /* 16 megs main flash */
 271 #define CONFIG_SYS_FLASH_CFI            1
 272 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 273
 274 #define CONFIG_SYS_FLASH_PROTECTION     1
 275 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 276 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 277 #define CONFIG_SYS_MAX_FLASH_SECT       512
 278 #define CONFIG_SYS_FLASH_ERASE_TOUT     6000
 279 #define CONFIG_SYS_FLASH_WRITE_TOUT     2000
 280
 281 /* NAND */
 282
 283 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 284 #define CONFIG_SYS_NAND_BASE            0x40000000
 285 #define CONFIG_SYS_NAND_DBW_8           1
 286
 287 /* Status LED's */
 288
 289 #define CONFIG_STATUS_LED               1
 290 #define CONFIG_BOARD_SPECIFIC_LED       1
 291
 292 #define STATUS_LED_BOOT                 1
 293 #define STATUS_LED_ACTIVE               0
 294
 295 #define STATUS_LED_BIT                  1       /* AT91C_PIO_PD0 green LED */
 296 #define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
 297 #define STATUS_LED_STATE                STATUS_LED_OFF          /* BLINKING */
 298 #define STATUS_LED_BIT1                 2       /* AT91C_PIO_PD1  red LED */
 299 #define STATUS_LED_STATE1               STATUS_LED_ON           /* BLINKING */
 300 #define STATUS_LED_PERIOD1              (CONFIG_SYS_HZ / 4)
 301
 302 #define CONFIG_VIDEO                    1
 303
 304 /* Options */
 305
 306 #ifdef CONFIG_VIDEO
 307
 308 #define CONFIG_VIDEO_VCXK                       1
 309
 310 #define CONFIG_SPLASH_SCREEN                    1
 311
 312 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       4
 313 #define CONFIG_SYS_VCXK_BASE    0x30000000
 314
 315 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         (1<<3)
 316 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        piob
 317 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         odr
 318
 319 #define CONFIG_SYS_VCXK_ENABLE_PIN              (1<<5)
 320 #define CONFIG_SYS_VCXK_ENABLE_PORT             piob
 321 #define CONFIG_SYS_VCXK_ENABLE_DDR              oer
 322
 323 #define CONFIG_SYS_VCXK_REQUEST_PIN             (1<<2)
 324 #define CONFIG_SYS_VCXK_REQUEST_PORT            piob
 325 #define CONFIG_SYS_VCXK_REQUEST_DDR             oer
 326
 327 #define CONFIG_SYS_VCXK_INVERT_PIN              (1<<4)
 328 #define CONFIG_SYS_VCXK_INVERT_PORT             piob
 329 #define CONFIG_SYS_VCXK_INVERT_DDR              oer
 330
 331 #define CONFIG_SYS_VCXK_RESET_PIN               (1<<6)
 332 #define CONFIG_SYS_VCXK_RESET_PORT              piob
 333 #define CONFIG_SYS_VCXK_RESET_DDR               oer
 334
 335 #endif  /* CONFIG_VIDEO */
 336
 337 /* Environment */
 338
 339 #define CONFIG_BOOTDELAY                5
 340
 341 #define CONFIG_ENV_IS_IN_FLASH          1
 342 #define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0x60000)
 343 #define CONFIG_ENV_SIZE                 0x20000 /* sectors are 128K here */
 344
 345 #define CONFIG_BAUDRATE                 115200
 346
 347 #define CONFIG_BOOTCOMMAND              "run nfsboot"
 348
 349 #define CONFIG_NFSBOOTCOMMAND                                           \
 350                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 351                 "run bootargsdefaults;"                                 \
 352                 "set bootargs $(bootargs) boot=nfs "                    \
 353                 ";echo $(bootargs)"                                     \
 354         ";bootm"
 355
 356 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 357         "displaywidth=256\0"                                            \
 358         "displayheight=512\0"                                           \
 359         "displaybsteps=1023\0"                                          \
 360         "ubootaddr=10000000\0"                                          \
 361         "splashimage=10080000\0"                                        \
 362         "kerneladdr=100A0000\0"                                         \
 363         "kernelsize=00400000\0"                                         \
 364         "rootfsaddr=104A0000\0"                                         \
 365         "copy_addr=21200000\0"                                          \
 366         "rootfssize=00B60000\0"                                         \
 367         "bootargsdefaults=set bootargs "                                \
 368                 "console=ttyS0,115200 "                                 \
 369                 "video=vcxk_fb:xres:${displaywidth},"                   \
 370                         "yres:${displayheight},"                        \
 371                         "bres:${displaybsteps} "                        \
 372                 "mem=62M "                                              \
 373                 "panic=10 "                                             \
 374                 "uboot=\\\"${ver}\\\" "                                 \
 375                 "\0"                                                    \
 376         "update_kernel=protect off $(kerneladdr) +$(kernelsize);"       \
 377                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 378                 "erase $(kerneladdr) +$(kernelsize);"                   \
 379                 "cp.b $(fileaddr) $(kerneladdr) $(filesize);"           \
 380                 "protect on $(kerneladdr) +$(kernelsize)"               \
 381                 "\0"                                                    \
 382         "update_root=protect off $(rootfsaddr) +$(rootfssize);"         \
 383                 "dhcp $(copy_addr) rfs;"                                \
 384                 "erase $(rootfsaddr) +$(rootfssize);"                   \
 385                 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);"           \
 386                 "\0"                                                    \
 387         "update_uboot=protect off 10000000 1005FFFF;"                   \
 388                 "dhcp $(copy_addr) u-boot_eb_cpux9k2;"                  \
 389                 "erase 10000000 1005FFFF;"                              \
 390                 "cp.b $(fileaddr) $(ubootaddr) $(filesize);"            \
 391                 "protect on 10000000 1005FFFF;reset\0"                  \
 392         "update_splash=protect off $(splashimage) +20000;"              \
 393                 "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;"              \
 394                 "erase $(splashimage) +20000;"                          \
 395                 "cp.b $(fileaddr) 10080000 $(filesize);"                \
 396                 "protect on $(splashimage) +20000;reset\0"              \
 397         "emergency=run bootargsdefaults;"                               \
 398                 "set bootargs $(bootargs) root=initramfs boot=emergency " \
 399                 ";bootm $(kerneladdr)\0"                                \
 400         "netemergency=run bootargsdefaults;"                            \
 401                 "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 402                 "set bootargs $(bootargs) root=initramfs boot=emergency " \
 403                 ";bootm $(copy_addr)\0"                                 \
 404         "norboot=run bootargsdefaults;"                                 \
 405                 "set bootargs $(bootargs) root=initramfs boot=local "   \
 406                 ";bootm $(kerneladdr)\0"                                \
 407         "nandboot=run bootargsdefaults;"                                \
 408                 "set bootargs $(bootargs) root=initramfs boot=nand "    \
 409                 ";bootm $(kerneladdr)\0"                                \
 410         " "
 411
 412 /*--------------------------------------------------------------------------*/
 413
 414 #endif
 415
 416 /* EOF */