2 * (C) Copyright 2008-2009
3 * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
4 * Jens Scharsig <esw@bus-elektronik.de>
6 * Configuation settings for the EB+CPUx9K2 board.
8 * SPDX-License-Identifier: GPL-2.0+
11 #ifndef _CONFIG_EB_CPUx9K2_H_
12 #define _CONFIG_EB_CPUx9K2_H_
14 /*--------------------------------------------------------------------------*/
16 #define CONFIG_AT91RM9200 /* It's an Atmel AT91RM9200 SoC */
17 #define CONFIG_EB_CPUX9K2 /* on an EP+CPUX9K2 Board */
20 #define CONFIG_VERSION_VARIABLE
21 #define CONFIG_IDENT_STRING " on EB+CPUx9K2"
23 #include <asm/hardware.h> /* needed for port definitions */
25 #define CONFIG_MISC_INIT_R
26 #define CONFIG_BOARD_EARLY_INIT_F
28 #define MACH_TYPE_EB_CPUX9K2 1977
29 #define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2
31 #define CONFIG_SYS_CACHELINE_SIZE 32
32 #define CONFIG_SYS_DCACHE_OFF
34 /*--------------------------------------------------------------------------*/
35 #ifndef CONFIG_RAMBOOT
36 #define CONFIG_SYS_TEXT_BASE 0x00000000
38 #define CONFIG_SKIP_LOWLEVEL_INIT
39 #define CONFIG_SYS_TEXT_BASE 0x21800000
41 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
42 #define CONFIG_STANDALONE_LOAD_ADDR 0x21000000
44 #define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
45 #define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
46 #define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
48 #define CONFIG_BOOT_RETRY_TIME 30
49 #define CONFIG_CMDLINE_EDITING
51 #define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
52 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
53 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
54 #define CONFIG_SYS_PBSIZE \
55 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
58 * ARM asynchronous clock
61 #define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */
62 #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
63 #define CONFIG_SYS_HZ 1000
64 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
66 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
68 #define CONFIG_CMDLINE_TAG 1
69 #define CONFIG_SETUP_MEMORY_TAGS 1
70 #define CONFIG_INITRD_TAG 1
72 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
74 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
75 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
78 #define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */
79 #define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */
80 #define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */
83 * Size of malloc() pool
86 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
92 #define CONFIG_NR_DRAM_BANKS 1
94 #define CONFIG_SYS_SDRAM_BASE 0x20000000
95 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
96 #define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */
98 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
99 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
100 CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
101 CONFIG_SYS_MALLOC_LEN)
103 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */
104 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
105 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
106 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
107 #define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */
108 #define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
109 #define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
110 #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
111 #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
112 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
113 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
114 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
115 #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
118 * Command line configuration
121 #include <config_cmd_default.h>
123 #define CONFIG_CMD_BMP
124 #define CONFIG_CMD_DATE
125 #define CONFIG_CMD_DHCP
126 #define CONFIG_CMD_I2C
127 #define CONFIG_CMD_MII
128 #define CONFIG_CMD_NAND
129 #define CONFIG_CMD_PING
130 #define CONFIG_I2C_CMD_TREE
131 #define CONFIG_CMD_USB
132 #define CONFIG_CMD_FAT
133 #define CONFIG_CMD_UBI
134 #define CONFIG_CMD_MTDPARTS
135 #define CONFIG_CMD_UBIFS
137 #define CONFIG_SYS_LONGHELP
143 #define CONFIG_FLASH_CFI_MTD
144 #define CONFIG_MTD_DEVICE
145 #define CONFIG_MTD_PARTITIONS
146 #define CONFIG_RBTREE
149 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
150 #define MTDPARTS_DEFAULT "mtdparts=" \
165 #define CONFIG_USB_ATMEL
166 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
167 #define CONFIG_USB_OHCI_NEW
168 #define CONFIG_AT91C_PQFP_UHPBUG
169 #define CONFIG_USB_STORAGE
170 #define CONFIG_DOS_PARTITION
171 #define CONFIG_ISO_PARTITION
172 #define CONFIG_EFI_PARTITION
174 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
175 #define CONFIG_SYS_USB_OHCI_CPU_INIT
176 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00300000
177 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
183 #define CONFIG_BAUDRATE 115200
184 #define CONFIG_ATMEL_USART
185 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
186 #define CONFIG_USART_ID 0/* ignored in arm */
192 #define CONFIG_NET_RETRY_COUNT 10
193 #define CONFIG_RESET_PHY_R 1
195 #define CONFIG_DRIVER_AT91EMAC 1
196 #define CONFIG_DRIVER_AT91EMAC_QUIET 1
197 #define CONFIG_SYS_RX_ETH_BUFFER 8
203 #define CONFIG_BOOTP_BOOTFILESIZE
204 #define CONFIG_BOOTP_BOOTPATH
205 #define CONFIG_BOOTP_GATEWAY
206 #define CONFIG_BOOTP_HOSTNAME
212 #define CONFIG_SYS_I2C
213 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
214 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
215 #define CONFIG_SYS_I2C_SOFT_SLAVE 0
217 /* Software I2C driver configuration */
219 #define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */
220 #define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */
222 #define CONFIG_SYS_I2C_INIT_BOARD
224 #define I2C_INIT i2c_init_board();
225 #define I2C_ACTIVE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
226 #define I2C_TRISTATE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
227 #define I2C_READ ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
228 #define I2C_SDA(bit) \
230 writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr); \
232 writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
233 #define I2C_SCL(bit) \
235 writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr); \
237 writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
239 #define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SOFT_SPEED)
243 #ifdef CONFIG_CMD_DATE
244 #define CONFIG_RTC_DS1338
245 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
250 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
251 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
253 /* FLASH organization */
256 #define CONFIG_FLASH_SHOW_PROGRESS 45
258 #define CONFIG_FLASH_CFI_DRIVER 1
260 #define PHYS_FLASH_1 0x10000000
261 #define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main flash */
262 #define CONFIG_SYS_FLASH_CFI 1
263 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
265 #define CONFIG_SYS_FLASH_PROTECTION 1
266 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
267 #define CONFIG_SYS_MAX_FLASH_BANKS 1
268 #define CONFIG_SYS_MAX_FLASH_SECT 512
269 #define CONFIG_SYS_FLASH_ERASE_TOUT 6000
270 #define CONFIG_SYS_FLASH_WRITE_TOUT 2000
274 #define CONFIG_SYS_MAX_NAND_DEVICE 1
275 #define CONFIG_SYS_NAND_BASE 0x40000000
276 #define CONFIG_SYS_NAND_DBW_8 1
280 #define CONFIG_STATUS_LED 1
281 #define CONFIG_BOARD_SPECIFIC_LED 1
283 #define STATUS_LED_BOOT 1
284 #define STATUS_LED_ACTIVE 0
286 #define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */
287 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
288 #define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */
289 #define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red LED */
290 #define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */
291 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4)
293 #define CONFIG_VIDEO 1
299 #define CONFIG_VIDEO_VCXK 1
301 #define CONFIG_SPLASH_SCREEN 1
303 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4
304 #define CONFIG_SYS_VCXK_BASE 0x30000000
306 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3)
307 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT piob
308 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR odr
310 #define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5)
311 #define CONFIG_SYS_VCXK_ENABLE_PORT piob
312 #define CONFIG_SYS_VCXK_ENABLE_DDR oer
314 #define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2)
315 #define CONFIG_SYS_VCXK_REQUEST_PORT piob
316 #define CONFIG_SYS_VCXK_REQUEST_DDR oer
318 #define CONFIG_SYS_VCXK_INVERT_PIN (1<<4)
319 #define CONFIG_SYS_VCXK_INVERT_PORT piob
320 #define CONFIG_SYS_VCXK_INVERT_DDR oer
322 #define CONFIG_SYS_VCXK_RESET_PIN (1<<6)
323 #define CONFIG_SYS_VCXK_RESET_PORT piob
324 #define CONFIG_SYS_VCXK_RESET_DDR oer
326 #endif /* CONFIG_VIDEO */
330 #define CONFIG_BOOTDELAY 5
332 #define CONFIG_ENV_IS_IN_FLASH 1
333 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x80000)
334 #define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
336 #define CONFIG_BAUDRATE 115200
338 #define CONFIG_BOOTCOMMAND "run nfsboot"
340 #define CONFIG_NFSBOOTCOMMAND \
341 "dhcp $(copy_addr) uImage_cpux9k2;" \
342 "run bootargsdefaults;" \
343 "set bootargs $(bootargs) boot=nfs " \
344 ";echo $(bootargs)" \
347 #define CONFIG_EXTRA_ENV_SETTINGS \
348 "displaywidth=256\0" \
349 "displayheight=512\0" \
350 "displaybsteps=1023\0" \
351 "ubootaddr=10000000\0" \
352 "splashimage=100A0000\0" \
353 "kerneladdr=100C0000\0" \
354 "kernelsize=00400000\0" \
355 "rootfsaddr=10520000\0" \
356 "copy_addr=21200000\0" \
357 "rootfssize=00AE0000\0" \
358 "mtdids=" MTDIDS_DEFAULT "\0" \
359 "mtdparts=" MTDPARTS_DEFAULT "\0" \
360 "bootargsdefaults=set bootargs " \
361 "console=ttyS0,115200 " \
362 "video=vcxk_fb:xres:${displaywidth}," \
363 "yres:${displayheight}," \
364 "bres:${displaybsteps} " \
367 "uboot=\\\"${ver}\\\" " \
369 "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
370 "dhcp $(copy_addr) uImage_cpux9k2;" \
371 "erase $(kerneladdr) +$(kernelsize);" \
372 "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
373 "protect on $(kerneladdr) +$(kernelsize)" \
375 "update_root=protect off $(rootfsaddr) +$(rootfssize);" \
376 "dhcp $(copy_addr) rfs;" \
377 "erase $(rootfsaddr) +$(rootfssize);" \
378 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
380 "update_uboot=protect off 10000000 1007FFFF;" \
381 "dhcp $(copy_addr) u-boot_eb_cpux9k2;" \
382 "erase 10000000 1007FFFF;" \
383 "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
384 "protect on 10000000 1007FFFF;reset\0" \
385 "update_splash=protect off $(splashimage) +20000;" \
386 "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \
387 "erase $(splashimage) +20000;" \
388 "cp.b $(fileaddr) $(splashimage) $(filesize);" \
389 "protect on $(splashimage) +20000;reset\0" \
390 "emergency=run bootargsdefaults;" \
391 "set bootargs $(bootargs) root=initramfs boot=emergency " \
392 ";bootm $(kerneladdr)\0" \
393 "netemergency=run bootargsdefaults;" \
394 "dhcp $(copy_addr) uImage_cpux9k2;" \
395 "set bootargs $(bootargs) root=initramfs boot=emergency " \
396 ";bootm $(copy_addr)\0" \
397 "norboot=run bootargsdefaults;" \
398 "set bootargs $(bootargs) root=initramfs boot=local " \
399 ";bootm $(kerneladdr)\0" \
400 "nandboot=run bootargsdefaults;" \
401 "set bootargs $(bootargs) root=initramfs boot=nand " \
402 ";bootm $(kerneladdr)\0" \
405 /*--------------------------------------------------------------------------*/