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Move default y configs out of arch/board Kconfig
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1 /*
2  * Palm LifeDrive configuration file
3  *
4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 /*
13  * High Level Board Configuration Options
14  */
15 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
16 #define CONFIG_PALMLD           1       /* Palm LifeDrive board */
17
18 /* we will never enable dcache, because we have to setup MMU first */
19 #define CONFIG_SYS_DCACHE_OFF
20
21 /*
22  * Environment settings
23  */
24 #define CONFIG_ENV_OVERWRITE
25 #define CONFIG_SYS_MALLOC_LEN           (128*1024)
26 #define CONFIG_SYS_TEXT_BASE    0x0
27
28 #define CONFIG_BOOTCOMMAND                                              \
29         "if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then "   \
30                 "source 0xa0000000; "                                   \
31         "else "                                                         \
32                 "bootm 0x0x60000; "                                     \
33         "fi; "
34 #define CONFIG_BOOTARGS                 "console=tty0 console=ttyS0,9600"
35 #define CONFIG_TIMESTAMP
36 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
37 #define CONFIG_CMDLINE_TAG
38 #define CONFIG_SETUP_MEMORY_TAGS
39
40 #define CONFIG_LZMA                     /* LZMA compression support */
41
42 /*
43  * Serial Console Configuration
44  */
45 #define CONFIG_PXA_SERIAL
46 #define CONFIG_FFUART                   1
47 #define CONFIG_CONS_INDEX               3
48 #define CONFIG_BAUDRATE                 9600
49
50 /*
51  * Bootloader Components Configuration
52  */
53 #include <config_cmd_default.h>
54
55 #undef  CONFIG_CMD_NFS
56 #define CONFIG_CMD_ENV
57 #undef  CONFIG_CMD_IMLS
58 #define CONFIG_CMD_MMC
59 #define CONFIG_CMD_IDE
60 #define CONFIG_LCD
61 #define CONFIG_PXA_LCD
62
63 /*
64  * MMC Card Configuration
65  */
66 #ifdef  CONFIG_CMD_MMC
67 #define CONFIG_MMC
68 #define CONFIG_GENERIC_MMC
69 #define CONFIG_PXA_MMC_GENERIC
70 #define CONFIG_SYS_MMC_BASE             0xF0000000
71 #define CONFIG_CMD_FAT
72 #define CONFIG_CMD_EXT2
73 #define CONFIG_DOS_PARTITION
74 #endif
75
76 /*
77  * LCD
78  */
79 #ifdef CONFIG_LCD
80 #define CONFIG_LQ038J7DH53
81 #define CONFIG_VIDEO_LOGO
82 #define CONFIG_CMD_BMP
83 #define CONFIG_SPLASH_SCREEN
84 #define CONFIG_SPLASH_SCREEN_ALIGN
85 #define CONFIG_VIDEO_BMP_GZIP
86 #define CONFIG_VIDEO_BMP_RLE8
87 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
88 #endif
89
90 /*
91  * KGDB
92  */
93 #ifdef  CONFIG_CMD_KGDB
94 #define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
95 #endif
96
97 /*
98  * HUSH Shell Configuration
99  */
100 #define CONFIG_SYS_HUSH_PARSER          1
101
102 #define CONFIG_SYS_LONGHELP
103 #ifdef  CONFIG_SYS_HUSH_PARSER
104 #define CONFIG_SYS_PROMPT               "$ "
105 #endif
106 #define CONFIG_SYS_CBSIZE               256
107 #define CONFIG_SYS_PBSIZE               \
108         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
109 #define CONFIG_SYS_MAXARGS              16
110 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
111 #define CONFIG_SYS_DEVICE_NULLDEV       1
112
113 /*
114  * Clock Configuration
115  */
116 #define CONFIG_SYS_CPUSPEED             0x210           /* 416MHz ; N=2,L=16 */
117
118 /*
119  * DRAM Map
120  */
121 #define CONFIG_NR_DRAM_BANKS            1               /* 1 bank of DRAM */
122 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
123 #define PHYS_SDRAM_1_SIZE               0x02000000      /* 32 MB */
124
125 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
126 #define CONFIG_SYS_DRAM_SIZE            0x02000000      /* 32 MB DRAM */
127
128 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
129 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
130
131 #define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
132
133 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
134 #define CONFIG_SYS_INIT_SP_ADDR         (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
135
136 /*
137  * NOR FLASH
138  */
139 #ifdef  CONFIG_CMD_FLASH
140 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
141 #define PHYS_FLASH_SIZE                 0x00080000      /* 512 KB */
142 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
143
144 #define CONFIG_SYS_FLASH_CFI
145 #define CONFIG_FLASH_CFI_DRIVER         1
146
147 #define CONFIG_FLASH_CFI_LEGACY
148 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
149
150 #define CONFIG_SYS_MONITOR_BASE         0
151 #define CONFIG_SYS_MONITOR_LEN          0x40000
152
153 #define CONFIG_SYS_MAX_FLASH_BANKS      1
154 #define CONFIG_SYS_MAX_FLASH_SECT       256
155
156 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
157
158 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000
159 #define CONFIG_SYS_FLASH_WRITE_TOUT     240000
160 #define CONFIG_SYS_FLASH_LOCK_TOUT      240000
161 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    240000
162 #define CONFIG_SYS_FLASH_PROTECTION
163
164 #define CONFIG_ENV_IS_IN_FLASH          1
165 #define CONFIG_ENV_SECT_SIZE            0x10000
166 #else
167 #define CONFIG_SYS_NO_FLASH
168 #define CONFIG_ENV_IS_NOWHERE
169 #endif
170
171 #define CONFIG_ENV_ADDR                 0x40000
172 #define CONFIG_ENV_SIZE                 0x4000
173
174 /*
175  * IDE
176  */
177 #ifdef  CONFIG_CMD_IDE
178 #define CONFIG_LBA48
179 #undef  CONFIG_IDE_LED
180 #undef  CONFIG_IDE_RESET
181
182 #define __io
183
184 #define CONFIG_SYS_IDE_MAXBUS           1
185 #define CONFIG_SYS_IDE_MAXDEVICE        1
186
187 #define CONFIG_SYS_ATA_BASE_ADDR        0x20000000
188 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0
189
190 #define CONFIG_SYS_ATA_DATA_OFFSET      0x10
191 #define CONFIG_SYS_ATA_REG_OFFSET       0x10
192 #define CONFIG_SYS_ATA_ALT_OFFSET       0x10
193
194 #define CONFIG_SYS_ATA_STRIDE           1
195 #endif
196
197 /*
198  * GPIO settings
199  */
200 #define CONFIG_SYS_GAFR0_L_VAL  0x00000000
201 #define CONFIG_SYS_GAFR0_U_VAL  0xa5180012
202 #define CONFIG_SYS_GAFR1_L_VAL  0x69988056
203 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa580aa
204 #define CONFIG_SYS_GAFR2_L_VAL  0x6aaaaaaa
205 #define CONFIG_SYS_GAFR2_U_VAL  0x01040001
206 #define CONFIG_SYS_GAFR3_L_VAL  0x540a950c
207 #define CONFIG_SYS_GAFR3_U_VAL  0x00000009
208 #define CONFIG_SYS_GPCR0_VAL    0x00000000
209 #define CONFIG_SYS_GPCR1_VAL    0x00000000
210 #define CONFIG_SYS_GPCR2_VAL    0x00000000
211 #define CONFIG_SYS_GPCR3_VAL    0x00000000
212 #define CONFIG_SYS_GPDR0_VAL    0xc26b0000
213 #define CONFIG_SYS_GPDR1_VAL    0xfcdfaa93
214 #define CONFIG_SYS_GPDR2_VAL    0x7bbaffff
215 #define CONFIG_SYS_GPDR3_VAL    0x006ff38d
216 #define CONFIG_SYS_GPSR0_VAL    0x0d9e45ee
217 #define CONFIG_SYS_GPSR1_VAL    0x03affdae
218 #define CONFIG_SYS_GPSR2_VAL    0x07554000
219 #define CONFIG_SYS_GPSR3_VAL    0x01bc0785
220
221 #define CONFIG_SYS_PSSR_VAL     0x30
222
223 /*
224  * Clock settings
225  */
226 #define CONFIG_SYS_CKEN         0x01ffffff
227 #define CONFIG_SYS_CCCR         0x02000210
228
229 /*
230  * Memory settings
231  */
232 #define CONFIG_SYS_MSC0_VAL     0x7ff844c8
233 #define CONFIG_SYS_MSC1_VAL     0x7ff86ab4
234 #define CONFIG_SYS_MSC2_VAL     0x7ff87ff8
235 #define CONFIG_SYS_MDCNFG_VAL   0x0B880acd
236 #define CONFIG_SYS_MDREFR_VAL   0x201fa031
237 #define CONFIG_SYS_MDMRS_VAL    0x00320032
238 #define CONFIG_SYS_FLYCNFG_VAL  0x00000000
239 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
240
241 /*
242  * PCMCIA and CF Interfaces
243  */
244 #define CONFIG_SYS_MECR_VAL     0x00000003
245 #define CONFIG_SYS_MCMEM0_VAL   0x0001c391
246 #define CONFIG_SYS_MCMEM1_VAL   0x0001c391
247 #define CONFIG_SYS_MCATT0_VAL   0x0001c391
248 #define CONFIG_SYS_MCATT1_VAL   0x0001c391
249 #define CONFIG_SYS_MCIO0_VAL    0x00014611
250 #define CONFIG_SYS_MCIO1_VAL    0x0001c391
251
252 #endif  /* __CONFIG_H */