include/configs/xsengine.h

   1 /*
   2  * (C) Copyright 2002
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2002
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /* High Level Configuration Options */
  32 #define CONFIG_PXA250                   1               /* This is an PXA250 CPU    */
  33 #define CONFIG_XSENGINE                 1
  34 #define CONFIG_MMC                      1
  35 #define CONFIG_DOS_PARTITION            1
  36 #define BOARD_LATE_INIT                 1
  37 #undef  CONFIG_USE_IRQ                                  /* we don't need IRQ/FIQ stuff */
  38 #define CONFIG_SYS_HZ                   1000
  39 #define CONFIG_SYS_CPUSPEED                     0x161           /* set core clock to 400/200/100 MHz */
  40
  41 #define CONFIG_NR_DRAM_BANKS            1               /* we have 1 bank of DRAM */
  42 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
  43 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
  44 #define PHYS_SDRAM_2                    0xa4000000      /* SDRAM Bank #2 */
  45 #define PHYS_SDRAM_2_SIZE               0x00000000      /* 0 MB */
  46 #define PHYS_SDRAM_3                    0xa8000000      /* SDRAM Bank #3 */
  47 #define PHYS_SDRAM_3_SIZE               0x00000000      /* 0 MB */
  48 #define PHYS_SDRAM_4                    0xac000000      /* SDRAM Bank #4 */
  49 #define PHYS_SDRAM_4_SIZE               0x00000000      /* 0 MB */
  50 #define CONFIG_SYS_DRAM_BASE                    0xa0000000
  51 #define CONFIG_SYS_DRAM_SIZE                    0x04000000
  52
  53 /* FLASH organization */
  54 #define CONFIG_SYS_MAX_FLASH_BANKS              1               /* max number of memory banks           */
  55 #define CONFIG_SYS_MAX_FLASH_SECT               128             /* max number of sectors on one chip    */
  56 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
  57 #define PHYS_FLASH_2                    0x00000000      /* Flash Bank #2 */
  58 #define PHYS_FLASH_SECT_SIZE            0x00020000      /* 127 KB sectors */
  59 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
  60
  61 /*
  62  * JFFS2 partitions
  63  */
  64 /* No command line, one static partition, whole device */
  65 #undef CONFIG_JFFS2_CMDLINE
  66 #define CONFIG_JFFS2_DEV                "nor0"
  67 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
  68 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
  69
  70 /* mtdparts command line support */
  71 /* Note: fake mtd_id used, no linux mtd map file */
  72 /*
  73 #define CONFIG_JFFS2_CMDLINE
  74 #define MTDIDS_DEFAULT          "nor0=xsengine-0"
  75 #define MTDPARTS_DEFAULT        "mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)"
  76 */
  77
  78 /* Environment settings */
  79 #define CONFIG_ENV_OVERWRITE
  80 #define CONFIG_ENV_IS_IN_FLASH             1
  81 #define CONFIG_ENV_ADDR                    (PHYS_FLASH_1 + 0x40000)     /* Addr of Environment Sector (after monitor)*/
  82 #define CONFIG_ENV_SECT_SIZE               PHYS_FLASH_SECT_SIZE         /* Size of the Environment Sector */
  83 #define CONFIG_ENV_SIZE                    0x4000                               /* 16kB Total Size of Environment Sector */
  84
  85 /* timeout values are in ticks */
  86 #define CONFIG_SYS_FLASH_ERASE_TOUT             (75*CONFIG_SYS_HZ)      /* Timeout for Flash Erase */
  87 #define CONFIG_SYS_FLASH_WRITE_TOUT             (50*CONFIG_SYS_HZ)      /* Timeout for Flash Write */
  88
  89 /* Size of malloc() pool */
  90 #define CONFIG_SYS_MALLOC_LEN                   (CONFIG_ENV_SIZE + 256*1024)
  91 #define CONFIG_SYS_GBL_DATA_SIZE                128             /* size in bytes reserved for initial data */
  92
  93 /* Hardware drivers */
  94 #define CONFIG_DRIVER_SMC91111
  95 #define CONFIG_SMC91111_BASE            0x04000300
  96 #define CONFIG_SMC_USE_32_BIT           1
  97
  98 /* select serial console configuration */
  99 #define CONFIG_FFUART                   1
 100
 101 /* allow to overwrite serial and ethaddr */
 102 #define CONFIG_BAUDRATE                 115200
 103
 104 /*
 105  * BOOTP options
 106  */
 107 #define CONFIG_BOOTP_BOOTFILESIZE
 108 #define CONFIG_BOOTP_BOOTPATH
 109 #define CONFIG_BOOTP_GATEWAY
 110 #define CONFIG_BOOTP_HOSTNAME
 111
 112
 113 /*
 114  * Command line configuration.
 115  */
 116 #include <config_cmd_default.h>
 117
 118 #define CONFIG_CMD_MMC
 119 #define CONFIG_CMD_FAT
 120 #define CONFIG_CMD_PING
 121 #define CONFIG_CMD_JFFS2
 122
 123
 124 #define CONFIG_BOOTDELAY                3
 125 #define CONFIG_ETHADDR                  FF:FF:FF:FF:FF:FF
 126 #define CONFIG_NETMASK                  255.255.255.0
 127 #define CONFIG_IPADDR                   192.168.1.50
 128 #define CONFIG_SERVERIP                 192.168.1.2
 129 #define CONFIG_BOOTARGS                 "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
 130 #define CONFIG_CMDLINE_TAG
 131
 132 /* Miscellaneous configurable options */
 133 #define CONFIG_SYS_HUSH_PARSER                  1
 134 #define CONFIG_SYS_PROMPT_HUSH_PS2              "> "
 135 #define CONFIG_SYS_LONGHELP                                                             /* undef to save memory */
 136 #define CONFIG_SYS_PROMPT                       "XS-Engine u-boot> "                    /* Monitor Command Prompt */
 137 #define CONFIG_SYS_CBSIZE                       256                                     /* Console I/O Buffer Size */
 138 #define CONFIG_SYS_PBSIZE                       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 139 #define CONFIG_SYS_MAXARGS                      16                                      /* max number of command args */
 140 #define CONFIG_SYS_BARGSIZE                     CONFIG_SYS_CBSIZE                               /* Boot Argument Buffer Size */
 141 #define CONFIG_SYS_MEMTEST_START                0xA0400000                              /* memtest works on     */
 142 #define CONFIG_SYS_MEMTEST_END                  0xA0800000                              /* 4 ... 8 MB in DRAM   */
 143 #undef  CONFIG_SYS_CLKS_IN_HZ                                                           /* everything, incl board info, in Hz */
 144 #define CONFIG_SYS_BAUDRATE_TABLE               { 9600, 19200, 38400, 57600, 115200 }   /* valid baudrates */
 145 #define CONFIG_SYS_MMC_BASE                     0xF0000000
 146 #define CONFIG_SYS_LOAD_ADDR                    0xA0000000                              /* load kernel to this address   */
 147
 148 /* Stack sizes - The stack sizes are set up in start.S using the settings below */
 149 #define CONFIG_STACKSIZE                (128*1024)      /* regular stack */
 150 #ifdef  CONFIG_USE_IRQ
 151 #define CONFIG_STACKSIZE_IRQ            (4*1024)        /* IRQ stack */
 152 #define CONFIG_STACKSIZE_FIQ            (4*1024)        /* FIQ stack */
 153 #endif
 154
 155 /* GP set register */
 156 #define CONFIG_SYS_GPSR0_VAL                    0x0000A000      /* CS1, PROG(FPGA) */
 157 #define CONFIG_SYS_GPSR1_VAL                    0x00020000      /* nPWE */
 158 #define CONFIG_SYS_GPSR2_VAL                    0x0000C000      /* CS2, CS3 */
 159
 160 /* GP clear register */
 161 #define CONFIG_SYS_GPCR0_VAL                    0x00000000
 162 #define CONFIG_SYS_GPCR1_VAL                    0x00000000
 163 #define CONFIG_SYS_GPCR2_VAL                    0x00000000
 164
 165 /* GP direction register */
 166 #define CONFIG_SYS_GPDR0_VAL                    0x0000A000      /* CS1, PROG(FPGA) */
 167 #define CONFIG_SYS_GPDR1_VAL                    0x00022A80      /* nPWE, FFUART + BTUART pins */
 168 #define CONFIG_SYS_GPDR2_VAL                    0x0000C000      /* CS2, CS3 */
 169
 170 /* GP rising edge detect register */
 171 #define CONFIG_SYS_GRER0_VAL                    0x00000000
 172 #define CONFIG_SYS_GRER1_VAL                    0x00000000
 173 #define CONFIG_SYS_GRER2_VAL                    0x00000000
 174
 175 /* GP falling edge detect register */
 176 #define CONFIG_SYS_GFER0_VAL                    0x00000000
 177 #define CONFIG_SYS_GFER1_VAL                    0x00000000
 178 #define CONFIG_SYS_GFER2_VAL                    0x00000000
 179
 180 /* GP alternate function register */
 181 #define CONFIG_SYS_GAFR0_L_VAL                  0x80000000      /* CS1 */
 182 #define CONFIG_SYS_GAFR0_U_VAL                  0x00000010      /* RDY */
 183 #define CONFIG_SYS_GAFR1_L_VAL                  0x09988050      /* FFUART + BTUART pins */
 184 #define CONFIG_SYS_GAFR1_U_VAL                  0x00000008      /* nPWE */
 185 #define CONFIG_SYS_GAFR2_L_VAL                  0xA0000000      /* CS2, CS3 */
 186 #define CONFIG_SYS_GAFR2_U_VAL                  0x00000000
 187
 188 #define CONFIG_SYS_PSSR_VAL                     0x00000020      /* Power manager sleep status */
 189 #define CONFIG_SYS_CCCR_VAL                     0x00000161      /* 100 MHz memory, 400 MHz CPU  */
 190 #define CONFIG_SYS_CKEN_VAL                     0x000000C0      /* BTUART and FFUART enabled    */
 191 #define CONFIG_SYS_ICMR_VAL                     0x00000000      /* No interrupts enabled        */
 192
 193 /* Memory settings */
 194 #define CONFIG_SYS_MSC0_VAL                     0x25F425F0
 195
 196 /* MDCNFG: SDRAM Configuration Register */
 197 #define CONFIG_SYS_MDCNFG_VAL                   0x000009C9
 198
 199 /* MDREFR: SDRAM Refresh Control Register */
 200 #define CONFIG_SYS_MDREFR_VAL                   0x00018018
 201
 202 /* MDMRS: Mode Register Set Configuration Register */
 203 #define CONFIG_SYS_MDMRS_VAL                    0x00220022
 204
 205 #endif  /* __CONFIG_H */