lib_i386/ic/sc520.c

   1 /*
   2  * (C) Copyright 2002
   3  * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* stuff specific for the sc520,
  25  * but idependent of implementation */
  26
  27
  28 #include <common.h>
  29 #include <config.h>
  30 #include <pci.h>
  31 #include <asm/io.h>
  32 #include <asm/pci.h>
  33 #include <asm/ic/sc520.h>
  34
  35 /*
  36  * utility functions for boards based on the AMD sc520
  37  *
  38  * void write_mmcr_byte(u16 mmcr, u8 data)
  39  * void write_mmcr_word(u16 mmcr, u16 data)
  40  * void write_mmcr_long(u16 mmcr, u32 data)
  41  *
  42  * u8   read_mmcr_byte(u16 mmcr)
  43  * u16  read_mmcr_word(u16 mmcr)
  44  * u32  read_mmcr_long(u16 mmcr)
  45  *
  46  * void init_sc520(void)
  47  * unsigned long init_sc520_dram(void)
  48  * void pci_sc520_init(struct pci_controller *hose)
  49  *
  50  * void reset_timer(void)
  51  * ulong get_timer(ulong base)
  52  * void set_timer(ulong t)
  53  * void udelay(unsigned long usec)
  54  *
  55  */
  56
  57 static u32 mmcr_base= 0xfffef000;
  58
  59 void write_mmcr_byte(u16 mmcr, u8 data)
  60 {
  61         writeb(data, mmcr+mmcr_base);
  62 }
  63
  64 void write_mmcr_word(u16 mmcr, u16 data)
  65 {
  66         writew(data, mmcr+mmcr_base);
  67 }
  68
  69 void write_mmcr_long(u16 mmcr, u32 data)
  70 {
  71         writel(data, mmcr+mmcr_base);
  72 }
  73
  74 u8 read_mmcr_byte(u16 mmcr)
  75 {
  76         return readb(mmcr+mmcr_base);
  77 }
  78
  79 u16 read_mmcr_word(u16 mmcr)
  80 {
  81         return readw(mmcr+mmcr_base);
  82 }
  83
  84 u32 read_mmcr_long(u16 mmcr)
  85 {
  86         return readl(mmcr+mmcr_base);
  87 }
  88
  89
  90 void init_sc520(void)
  91 {
  92         DECLARE_GLOBAL_DATA_PTR;
  93
  94         /* Set the UARTxCTL register at it's slower,
  95          * baud clock giving us a 1.8432 MHz reference
  96          */
  97         write_mmcr_byte(SC520_UART1CTL, 7);
  98         write_mmcr_byte(SC520_UART2CTL, 7);
  99
 100         /* first set the timer pin mapping */
 101         write_mmcr_byte(SC520_CLKSEL, 0x72);    /* no clock frequency selected, use 1.1892MHz */
 102
 103         /* enable PCI bus arbitrer */
 104         write_mmcr_byte(SC520_SYSARBCTL,0x02);  /* enable concurrent mode */
 105
 106         write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */
 107         write_mmcr_word(SC520_HBCTL,0x04);      /* enable posted-writes */
 108
 109
 110         if (CFG_SC520_HIGH_SPEED) {
 111                 write_mmcr_byte(SC520_CPUCTL, 0x2);     /* set it to 133 MHz and write back */
 112                 gd->cpu_clk = 133000000;
 113                 printf("## CPU Speed set to 133MHz\n");
 114         } else {
 115                 write_mmcr_byte(SC520_CPUCTL, 1);       /* set CPU to 100 MHz and write back cache */
 116                 printf("## CPU Speed set to 100MHz\n");
 117                 gd->cpu_clk = 100000000;
 118         }
 119
 120
 121         /* wait at least one millisecond */
 122         asm("movl       $0x2000,%%ecx\n"
 123             "wait_loop: pushl %%ecx\n"
 124             "popl       %%ecx\n"
 125             "loop wait_loop\n": : : "ecx");
 126
 127         /* turn on the SDRAM write buffer */
 128         write_mmcr_byte(SC520_DBCTL, 0x11);
 129
 130         /* turn on the cache and disable write through */
 131         asm("movl       %%cr0, %%eax\n"
 132             "andl       $0x9fffffff, %%eax\n"
 133             "movl       %%eax, %%cr0\n"  : : : "eax");
 134 }
 135
 136 unsigned long init_sc520_dram(void)
 137 {
 138         DECLARE_GLOBAL_DATA_PTR;
 139         bd_t *bd = gd->bd;
 140
 141         u32 dram_present=0;
 142         u32 dram_ctrl;
 143
 144         int val;
 145
 146         int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
 147         int refresh_rate        = CFG_SDRAM_REFRESH_RATE;
 148         int ras_cas_delay       = CFG_SDRAM_RAS_CAS_DELAY;
 149
 150         /* set SDRAM speed here */
 151
 152         refresh_rate/=78;
 153         if (refresh_rate<=1) {
 154                 val = 0;  /* 7.8us */
 155         } else if (refresh_rate==2) {
 156                 val = 1;  /* 15.6us */
 157         } else if (refresh_rate==3 || refresh_rate==4) {
 158                 val = 2;  /* 31.2us */
 159         } else {
 160                 val = 3;  /* 62.4us */
 161         }
 162         write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
 163
 164         val = read_mmcr_byte(SC520_DRCTMCTL);
 165         val &= 0xf0;
 166
 167         if (cas_precharge_delay==3) {
 168                 val |= 0x04;   /* 3T */
 169         } else if (cas_precharge_delay==4) {
 170                 val |= 0x08;   /* 4T */
 171         } else if (cas_precharge_delay>4) {
 172                 val |= 0x0c;
 173         }
 174
 175         if (ras_cas_delay > 3) {
 176                 val |= 2;
 177         } else {
 178                 val |= 1;
 179         }
 180         write_mmcr_byte(SC520_DRCTMCTL, val);
 181
 182
 183         /* We read-back the configuration of the dram
 184          * controller that the assembly code wrote */
 185         dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
 186
 187
 188         bd->bi_dram[0].start = 0;
 189         if (dram_ctrl & 0x80) {
 190                 /* bank 0 enabled */
 191                 dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
 192                 bd->bi_dram[0].size = bd->bi_dram[1].start;
 193
 194         } else {
 195                 bd->bi_dram[0].size = 0;
 196                 bd->bi_dram[1].start = bd->bi_dram[0].start;
 197         }
 198
 199         if (dram_ctrl & 0x8000) {
 200                 /* bank 1 enabled */
 201                 dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
 202                 bd->bi_dram[1].size = bd->bi_dram[2].start -  bd->bi_dram[1].start;
 203         } else {
 204                 bd->bi_dram[1].size = 0;
 205                 bd->bi_dram[2].start = bd->bi_dram[1].start;
 206         }
 207
 208         if (dram_ctrl & 0x800000) {
 209                 /* bank 2 enabled */
 210                 dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
 211                 bd->bi_dram[2].size = bd->bi_dram[3].start -  bd->bi_dram[2].start;
 212         } else {
 213                 bd->bi_dram[2].size = 0;
 214                 bd->bi_dram[3].start = bd->bi_dram[2].start;
 215         }
 216
 217         if (dram_ctrl & 0x80000000) {
 218                 /* bank 3 enabled */
 219                 dram_present  = (dram_ctrl & 0x7f000000) >> 2;
 220                 bd->bi_dram[3].size = dram_present -  bd->bi_dram[3].start;
 221         } else {
 222                 bd->bi_dram[3].size = 0;
 223         }
 224
 225
 226 #if 0
 227         printf("Configured %d bytes of dram\n", dram_present);
 228 #endif
 229         gd->ram_size = dram_present;
 230
 231         return dram_present;
 232 }
 233
 234
 235 #ifdef CONFIG_PCI
 236
 237
 238
 239 void pci_sc520_init(struct pci_controller *hose)
 240 {
 241         hose->first_busno = 0;
 242         hose->last_busno = 0xff;
 243
 244         /* System memory space */
 245         pci_set_region(hose->regions + 0,
 246                        SC520_PCI_MEMORY_BUS,
 247                        SC520_PCI_MEMORY_PHYS,
 248                        SC520_PCI_MEMORY_SIZE,
 249                        PCI_REGION_MEM | PCI_REGION_MEMORY);
 250
 251         /* PCI memory space */
 252         pci_set_region(hose->regions + 1,
 253                        SC520_PCI_MEM_BUS,
 254                        SC520_PCI_MEM_PHYS,
 255                        SC520_PCI_MEM_SIZE,
 256                        PCI_REGION_MEM);
 257
 258         /* ISA/PCI memory space */
 259         pci_set_region(hose->regions + 2,
 260                        SC520_ISA_MEM_BUS,
 261                        SC520_ISA_MEM_PHYS,
 262                        SC520_ISA_MEM_SIZE,
 263                        PCI_REGION_MEM);
 264
 265         /* PCI I/O space */
 266         pci_set_region(hose->regions + 3,
 267                        SC520_PCI_IO_BUS,
 268                        SC520_PCI_IO_PHYS,
 269                        SC520_PCI_IO_SIZE,
 270                        PCI_REGION_IO);
 271
 272         /* ISA/PCI I/O space */
 273         pci_set_region(hose->regions + 4,
 274                        SC520_ISA_IO_BUS,
 275                        SC520_ISA_IO_PHYS,
 276                        SC520_ISA_IO_SIZE,
 277                        PCI_REGION_IO);
 278
 279         hose->region_count = 5;
 280
 281         pci_setup_type1(hose,
 282                         SC520_REG_ADDR,
 283                         SC520_REG_DATA);
 284
 285         pci_register_hose(hose);
 286
 287         hose->last_busno = pci_hose_scan(hose);
 288
 289         /* enable target memory acceses on host brige */
 290         pci_write_config_word(0, PCI_COMMAND,
 291                               PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 292
 293 }
 294
 295
 296 #endif
 297
 298 #ifdef CFG_TIMER_SC520
 299
 300
 301 void reset_timer(void)
 302 {
 303         write_mmcr_word(SC520_GPTMR0CNT, 0);
 304         write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
 305
 306 }
 307
 308 ulong get_timer(ulong base)
 309 {
 310         /* fixme: 30 or 33 */
 311         return  read_mmcr_word(SC520_GPTMR0CNT) / 33;
 312 }
 313
 314 void set_timer(ulong t)
 315 {
 316         /* FixMe: use two cascade coupled timers */
 317         write_mmcr_word(SC520_GPTMR0CTL, 0x4001);
 318         write_mmcr_word(SC520_GPTMR0CNT, t*33);
 319         write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
 320 }
 321
 322
 323 void udelay(unsigned long usec)
 324 {
 325         int m=0;
 326         long u;
 327
 328         read_mmcr_word(SC520_SWTMRMILLI);
 329         read_mmcr_word(SC520_SWTMRMICRO);
 330
 331 #if 0
 332         /* do not enable this line, udelay is used in the serial driver -> recursion */
 333         printf("udelay: %ld m.u %d.%d  tm.tu %d.%d\n", usec, m, u, tm, tu);
 334 #endif
 335         while (1) {
 336
 337                 m += read_mmcr_word(SC520_SWTMRMILLI);
 338                 u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
 339
 340                 if (usec <= u) {
 341                         break;
 342                 }
 343         }
 344 }
 345
 346 #endif
 347
 348