1 From 935e15094d78db20b01d5026aaa3dacef541e338 Mon Sep 17 00:00:00 2001
2 From: Terry Lv <r65388@freescale.com>
3 Date: Mon, 17 Aug 2009 15:20:54 +0800
4 Subject: [PATCH] ENGR00115046: Add new MMC config option for mx35.
6 Add new MMC config option for mx35.
8 Signed-off-by: Terry Lv <r65388@freescale.com>
11 include/configs/mx35_3stack.h | 27 +----
12 include/configs/mx35_3stack_mmc.h | 253 +++++++++++++++++++++++++++++++++++++
13 3 files changed, 257 insertions(+), 28 deletions(-)
15 diff --git a/Makefile b/Makefile
16 index 56b447e..ed10cb9 100644
19 @@ -3238,8 +3238,9 @@ mx31pdk_nand_config : unconfig
20 Mx31_3stack_config : unconfig
21 @$(MKCONFIG) $(@:_config=) arm arm1136 mx31_3stack freescale mx31
23 -mx35_3stack_config : unconfig
24 - @$(MKCONFIG) $(@:_config=) arm arm1136 mx35_3stack freescale mx35
26 +mx35_3stack_mmc_config: unconfig
27 + @$(MKCONFIG) $(@:_config=) arm arm1136 mx35_3stack freescale mx35
29 imx51_config : unconfig
30 @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 imx51 freescale mx51
31 diff --git a/include/configs/mx35_3stack.h b/include/configs/mx35_3stack.h
32 index 796fb03..9939964 100644
33 --- a/include/configs/mx35_3stack.h
34 +++ b/include/configs/mx35_3stack.h
36 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
37 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
43 -#define CONFIG_FSL_MMC 1
46 -#define CONFIG_CMD_MMC
48 -#if defined(CONFIG_FSL_MMC)
49 - #define CONFIG_FLASH_HEADER 1
50 - #define CONFIG_FLASH_HEADER_OFFSET 0x400
51 - #define CONFIG_FLASH_HEADER_BARKER 0xB1
54 -#define CONFIG_DOS_PARTITION 1
55 -#define CONFIG_CMD_FAT 1
56 -#define CONFIG_MMC_BASE 0x0
59 /*-----------------------------------------------------------------------
60 * FLASH and environment organization
64 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
66 -#if defined(CONFIG_FSL_MMC)
67 - #define CONFIG_FSL_ENV_IN_MMC
68 -#elif defined(CONFIG_CMD_NAND)
69 +#if defined(CONFIG_CMD_NAND)
70 #define CONFIG_FSL_ENV_IN_NAND
72 #define CONFIG_ENV_IS_IN_FLASH 1
74 #if defined(CONFIG_FSL_ENV_IN_NAND)
75 #define CONFIG_ENV_IS_IN_NAND 1
76 #define CONFIG_ENV_OFFSET 0x100000
77 -#elif defined(CONFIG_FSL_ENV_IN_MMC)
78 - #define CONFIG_ENV_IS_IN_MMC 1
79 - #define CONFIG_ENV_OFFSET (1024 * 1024)
80 #elif defined(CONFIG_FSL_ENV_IS_IN_FLASH)
81 #define CONFIG_ENV_IS_IN_FLASH 1
83 diff --git a/include/configs/mx35_3stack_mmc.h b/include/configs/mx35_3stack_mmc.h
85 index 0000000..d4bf467
87 +++ b/include/configs/mx35_3stack_mmc.h
90 + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
92 + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
94 + * Configuration settings for the MX31ADS Freescale board.
96 + * This program is free software; you can redistribute it and/or
97 + * modify it under the terms of the GNU General Public License as
98 + * published by the Free Software Foundation; either version 2 of
99 + * the License, or (at your option) any later version.
101 + * This program is distributed in the hope that it will be useful,
102 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
103 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
104 + * GNU General Public License for more details.
106 + * You should have received a copy of the GNU General Public License
107 + * along with this program; if not, write to the Free Software
108 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
109 + * MA 02111-1307 USA
115 +#include <asm/arch/mx35.h>
117 + /* High Level Configuration Options */
118 +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
119 +#define CONFIG_MXC 1
120 +#define CONFIG_MX35 1 /* in a mx31 */
121 +#define CONFIG_MX35_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
122 +#define CONFIG_MX35_CLK32 32768
124 +#define CONFIG_DISPLAY_CPUINFO
125 +#define CONFIG_DISPLAY_BOARDINFO
127 +#define BOARD_LATE_INIT
129 + * Disabled for now due to build problems under Debian and a significant increase
130 + * in the final file size: 144260 vs. 109536 Bytes.
133 +#define CONFIG_OF_LIBFDT 1
134 +#define CONFIG_FIT 1
135 +#define CONFIG_FIT_VERBOSE 1
138 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
139 +#define CONFIG_REVISION_TAG 1
140 +#define CONFIG_SETUP_MEMORY_TAGS 1
141 +#define CONFIG_INITRD_TAG 1
144 + * Size of malloc() pool
146 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
147 +#define CONFIG_SYS_GBL_DATA_SIZE 128/* size in bytes reserved for initial data */
152 +#define CONFIG_HARD_I2C 1
153 +#define CONFIG_I2C_MXC 1
154 +#define CONFIG_SYS_I2C_PORT I2C_BASE_ADDR
155 +#define CONFIG_SYS_I2C_SPEED 100000
156 +#define CONFIG_SYS_I2C_SLAVE 0xfe
158 +#define CONFIG_MX35_UART UART1_BASE_ADDR
160 +/* allow to overwrite serial and ethaddr */
161 +#define CONFIG_ENV_OVERWRITE
162 +#define CONFIG_CONS_INDEX 1
163 +#define CONFIG_BAUDRATE 115200
164 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
166 +/***********************************************************
167 + * Command definition
168 + ***********************************************************/
170 +#include <config_cmd_default.h>
172 +#define CONFIG_CMD_PING
173 +#define CONFIG_CMD_DHCP
174 +/*#define CONFIG_CMD_SPI*/
175 +/*#define CONFIG_CMD_DATE*/
176 +#define CONFIG_CMD_NAND
178 +#define CONFIG_CMD_I2C
179 +#define CONFIG_CMD_MII
181 +#define CONFIG_BOOTDELAY 3
183 +#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
185 +#define CONFIG_EXTRA_ENV_SETTINGS \
187 + "ethprime=smc911x\0" \
188 + "uboot_addr=0xa0000000\0" \
189 + "uboot=u-boot.bin\0" \
190 + "kernel=uImage\0" \
191 + "nfsroot=/opt/eldk/arm\0" \
192 + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
193 + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
194 + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
195 + "bootcmd=run bootcmd_net\0" \
196 + "bootcmd_net=run bootargs_base bootargs_nfs; " \
197 + "tftpboot ${loadaddr} ${kernel}; bootm\0" \
198 + "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
199 + "protect off ${uboot_addr} 0xa003ffff; " \
200 + "erase ${uboot_addr} 0xa003ffff; " \
201 + "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
202 + "setenv filesize; saveenv\0"
205 +#define CONFIG_DRIVER_SMC911X 1
206 +#define CONFIG_DRIVER_SMC911X_16_BIT 1
207 +#define CONFIG_DRIVER_SMC911X_BASE CS5_BASE_ADDR
209 +#define CONFIG_HAS_ETH1
210 +#define CONFIG_NET_MULTI 1
211 +#define CONFIG_MXC_FEC
213 +#define CONFIG_DISCOVER_PHY
215 +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
216 +#define CONFIG_FEC0_PINMUX -1
217 +#define CONFIG_FEC0_PHY_ADDR 0x1F
218 +#define CONFIG_FEC0_MIIBASE -1
221 + * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
222 + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
223 + * controller inverted. The controller is capable of detecting and correcting
224 + * this, but it needs 4 network packets for that. Which means, at startup, you
225 + * will not receive answers to the first 4 packest, unless there have been some
226 + * broadcasts on the network, or your board is on a hub. Reducing the ARP
227 + * timeout from default 5 seconds to 200ms we speed up the initial TFTP
228 + * transfer, should the user wish one, significantly.
230 +#define CONFIG_ARP_TIMEOUT 200UL
233 + * Miscellaneous configurable options
235 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
236 +#define CONFIG_SYS_PROMPT "MX35 U-Boot > "
237 +#define CONFIG_AUTO_COMPLETE
238 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
239 +/* Print Buffer Size */
240 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
241 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
242 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
244 +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
245 +#define CONFIG_SYS_MEMTEST_END 0x10000
247 +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
249 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
251 +#define CONFIG_SYS_HZ CONFIG_MX35_CLK32/* use 32kHz clock as source */
253 +#define CONFIG_CMDLINE_EDITING 1
255 +/*-----------------------------------------------------------------------
258 + * The stack sizes are set up in start.S using the settings below
260 +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
262 +/*-----------------------------------------------------------------------
263 + * Physical Memory Map
265 +#define CONFIG_NR_DRAM_BANKS 1
266 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR
267 +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
272 +#define CONFIG_FSL_MMC
273 +#define CONFIG_MMC 1
274 +#define CONFIG_CMD_MMC
276 +#define CONFIG_FLASH_HEADER 1
277 +#define CONFIG_FLASH_HEADER_OFFSET 0x400
278 +#define CONFIG_FLASH_HEADER_BARKER 0xB1
280 +#define CONFIG_DOS_PARTITION 1
281 +#define CONFIG_CMD_FAT 1
282 +#define CONFIG_MMC_BASE 0x0
284 +/*-----------------------------------------------------------------------
285 + * FLASH and environment organization
287 +#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
288 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
289 +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
290 +/* Monitor at beginning of flash */
291 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
292 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 256KiB */
294 +#define CONFIG_ENV_SECT_SIZE (128 * 1024)
295 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
297 +/* Address and size of Redundant Environment Sector */
298 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
299 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
302 + * S29WS256N NOR flash has 4 32KiB small sectors at the beginning and at the
303 + * end. The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low
304 + * 4 sectors, if we put environment next to it, we will have to occupy 128KiB
305 + * for it. Putting it at the top of flash we use only 32KiB.
307 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
309 +#if defined(CONFIG_CMD_MMC)
310 + #define CONFIG_ENV_IS_IN_MMC 1
311 + #define CONFIG_ENV_OFFSET (768 * 1024)
312 +#elif defined(CONFIG_CMD_NAND)
313 + #define CONFIG_ENV_IS_IN_NAND 1
314 + #define CONFIG_ENV_OFFSET 0x100000
316 + #define CONFIG_ENV_IS_IN_FLASH 1
319 +/*-----------------------------------------------------------------------
320 + * CFI FLASH driver setup
322 +#define CONFIG_SYS_FLASH_CFI 1/* Flash memory is CFI compliant */
323 +#define CONFIG_FLASH_CFI_DRIVER 1/* Use drivers/cfi_flash.c */
324 +/* A non-standard buffered write algorithm */
325 +#define CONFIG_FLASH_SPANSION_S29WS_N 1
326 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* Use buffered writes (~10x faster) */
327 +#define CONFIG_SYS_FLASH_PROTECTION 1/* Use hardware sector protection */
329 +/*-----------------------------------------------------------------------
330 + * NAND FLASH driver setup
332 +#define NAND_MAX_CHIPS 1
333 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
334 +#define CONFIG_SYS_NAND_BASE 0x40000000
338 +#undef CONFIG_JFFS2_CMDLINE
339 +#define CONFIG_JFFS2_DEV "nor0"
341 +#endif /* __CONFIG_H */