1 From c3b0a8706e5b3eb84875830e9acaa80cac088c14 Mon Sep 17 00:00:00 2001
2 From: Terry Lv <r65388@freescale.com>
3 Date: Wed, 6 Jan 2010 15:57:26 +0800
4 Subject: [PATCH] ENGR00119834: Change PDR0 clock settings for mx35 TO2
6 The IPU_HND_BYP bit is different in mx35 to1 and to2.
7 Change the value of this bit for mx35 to2.
9 Signed-off-by: Terry Lv <r65388@freescale.com>
11 board/freescale/mx35_3stack/lowlevel_init.S | 5 +----
12 1 files changed, 1 insertions(+), 4 deletions(-)
14 diff --git a/board/freescale/mx35_3stack/lowlevel_init.S b/board/freescale/mx35_3stack/lowlevel_init.S
15 index 9608aa5..e984306 100644
16 --- a/board/freescale/mx35_3stack/lowlevel_init.S
17 +++ b/board/freescale/mx35_3stack/lowlevel_init.S
19 ldr r1, =CCM_PPLL_300_HZ
20 str r1, [r0, #CLKCTL_PPCTL]
22 - ldr r1, [r0, #CLKCTL_PDR0]
23 - orr r1, r1, #0x800000
24 - str r1, [r0, #CLKCTL_PDR0]
26 ldr r1, =CCM_PDR0_CONFIG
27 + bic r1, r1, #0x800000
28 str r1, [r0, #CLKCTL_PDR0]
30 ldr r1, [r0, #CLKCTL_CGR0]