patches/0094-ENGR00121731-Add-mmu-l1cache-l2cache-support-for.patch

   1 From 8df54067b614e6debb4a4c4a89dd108c70b42e71 Mon Sep 17 00:00:00 2001
   2 From: Terry Lv <r65388@freescale.com>
   3 Date: Thu, 18 Mar 2010 18:43:28 +0800
   4 Subject: [PATCH] ENGR00121731: Add mmu, l1cache, l2cache support for mx53
   5
   6 Add mmu, l1cache, l2cache support for mx53.
   7
   8 Signed-off-by: Terry Lv <r65388@freescale.com>
   9 ---
  10  board/freescale/mx53_evk/mx53_evk.c |   74 +++++++++++++++
  11  cpu/arm_cortexa8/mx51/generic.c     |    2 +
  12  cpu/arm_cortexa8/mx53/generic.c     |   19 ++++
  13  include/asm-arm/arch-mx53/mmu.h     |  174 +++++++++++++++++++++++++++++++++++
  14  include/configs/mx53_evk.h          |    5 +
  15  5 files changed, 274 insertions(+), 0 deletions(-)
  16
  17 diff --git a/board/freescale/mx53_evk/mx53_evk.c b/board/freescale/mx53_evk/mx53_evk.c
  18 index 1acfcc8..fd8587e 100644
  19 --- a/board/freescale/mx53_evk/mx53_evk.c
  20 +++ b/board/freescale/mx53_evk/mx53_evk.c
  21 @@ -39,6 +39,11 @@
  22  #include <fsl_esdhc.h>
  23  #endif
  24
  25 +#ifdef CONFIG_ARCH_MMU
  26 +#include <asm/mmu.h>
  27 +#include <asm/arch/mmu.h>
  28 +#endif
  29 +
  30  DECLARE_GLOBAL_DATA_PTR;
  31
  32  static u32 system_rev;
  33 @@ -93,6 +98,75 @@ inline int is_soc_rev(int rev)
  34         return (system_rev & 0xFF) - rev;
  35  }
  36
  37 +#ifdef CONFIG_ARCH_MMU
  38 +void board_mmu_init(void)
  39 +{
  40 +       unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
  41 +       unsigned long i;
  42 +
  43 +       /*
  44 +       * Set the TTB register
  45 +       */
  46 +       asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
  47 +
  48 +       /*
  49 +       * Set the Domain Access Control Register
  50 +       */
  51 +       i = ARM_ACCESS_DACR_DEFAULT;
  52 +       asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
  53 +
  54 +       /*
  55 +       * First clear all TT entries - ie Set them to Faulting
  56 +       */
  57 +       memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
  58 +       /* Actual   Virtual  Size   Attributes          Function */
  59 +       /* Base     Base     MB     cached? buffered?  access permissions */
  60 +       /* xxx00000 xxx00000 */
  61 +       X_ARM_MMU_SECTION(0x000, 0x000, 0x10,
  62 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  63 +                       ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */
  64 +       X_ARM_MMU_SECTION(0x070, 0x070, 0x010,
  65 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  66 +                       ARM_ACCESS_PERM_RW_RW); /* IRAM */
  67 +       X_ARM_MMU_SECTION(0x100, 0x100, 0x040,
  68 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  69 +                       ARM_ACCESS_PERM_RW_RW); /* SATA */
  70 +       X_ARM_MMU_SECTION(0x180, 0x180, 0x100,
  71 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  72 +                       ARM_ACCESS_PERM_RW_RW); /* IPUv3M */
  73 +       X_ARM_MMU_SECTION(0x200, 0x200, 0x200,
  74 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  75 +                       ARM_ACCESS_PERM_RW_RW); /* GPU */
  76 +       X_ARM_MMU_SECTION(0x400, 0x400, 0x300,
  77 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  78 +                       ARM_ACCESS_PERM_RW_RW); /* periperals */
  79 +       X_ARM_MMU_SECTION(0x700, 0x700, 0x400,
  80 +                       ARM_CACHEABLE, ARM_BUFFERABLE,
  81 +                       ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
  82 +       X_ARM_MMU_SECTION(0x700, 0xB00, 0x400,
  83 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  84 +                       ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
  85 +       X_ARM_MMU_SECTION(0xF00, 0xF00, 0x100,
  86 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  87 +                       ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
  88 +       X_ARM_MMU_SECTION(0xF7F, 0xF7F, 0x040,
  89 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  90 +                       ARM_ACCESS_PERM_RW_RW); /* NAND Flash buffer */
  91 +       X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001,
  92 +                       ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
  93 +                       ARM_ACCESS_PERM_RW_RW); /* iRam */
  94 +
  95 +       /* Workaround for arm errata #709718 */
  96 +       /* Setup PRRR so device is always mapped to non-shared */
  97 +       asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
  98 +       i &= (~(3 << 0x10));
  99 +       asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
 100 +
 101 +       /* Enable MMU */
 102 +       MMU_ON();
 103 +}
 104 +#endif
 105 +
 106  int dram_init(void)
 107  {
 108         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 109 diff --git a/cpu/arm_cortexa8/mx51/generic.c b/cpu/arm_cortexa8/mx51/generic.c
 110 index 0762c03..eb1a023 100644
 111 --- a/cpu/arm_cortexa8/mx51/generic.c
 112 +++ b/cpu/arm_cortexa8/mx51/generic.c
 113 @@ -26,7 +26,9 @@
 114  #include <common.h>
 115  #include <asm/arch/mx51.h>
 116  #include <asm/errno.h>
 117 +#ifdef CONFIG_ARCH_CPU_INIT
 118  #include <asm/cache-cp15.h>
 119 +#endif
 120  #include "crm_regs.h"
 121
 122  enum pll_clocks {
 123 diff --git a/cpu/arm_cortexa8/mx53/generic.c b/cpu/arm_cortexa8/mx53/generic.c
 124 index 01220c3..f75d15a 100644
 125 --- a/cpu/arm_cortexa8/mx53/generic.c
 126 +++ b/cpu/arm_cortexa8/mx53/generic.c
 127 @@ -24,6 +24,9 @@
 128  #include <asm/arch/mx53.h>
 129  #include <asm/errno.h>
 130  #include "crm_regs.h"
 131 +#ifdef CONFIG_ARCH_CPU_INIT
 132 +#include <asm/cache-cp15.h>
 133 +#endif
 134
 135  enum pll_clocks {
 136         PLL1_CLK = MXC_DPLL1_BASE,
 137 @@ -336,6 +339,7 @@ int cpu_eth_init(bd_t *bis)
 138         int rc = -ENODEV;
 139  #if defined(CONFIG_MXC_FEC)
 140         char *env = NULL;
 141 +
 142         rc = mxc_fec_initialize(bis);
 143
 144         env = getenv("fec_addr");
 145 @@ -345,3 +349,18 @@ int cpu_eth_init(bd_t *bis)
 146         return rc;
 147  }
 148
 149 +#if defined(CONFIG_ARCH_CPU_INIT)
 150 +int arch_cpu_init(void)
 151 +{
 152 +       icache_enable();
 153 +       dcache_enable();
 154 +
 155 +#ifdef CONFIG_L2_OFF
 156 +       l2_cache_disable();
 157 +#else
 158 +       l2_cache_enable();
 159 +#endif
 160 +       return 0;
 161 +}
 162 +#endif
 163 +
 164 diff --git a/include/asm-arm/arch-mx53/mmu.h b/include/asm-arm/arch-mx53/mmu.h
 165 new file mode 100644
 166 index 0000000..5fa2fc0
 167 --- /dev/null
 168 +++ b/include/asm-arm/arch-mx53/mmu.h
 169 @@ -0,0 +1,174 @@
 170 +/*
 171 + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 172 + */
 173 +
 174 +/*
 175 + * The code contained herein is licensed under the GNU General Public
 176 + * License. You may obtain a copy of the GNU General Public License
 177 + * Version 2 or later at the following locations:
 178 + *
 179 + * http://www.opensource.org/licenses/gpl-license.html
 180 + * http://www.gnu.org/copyleft/gpl.html
 181 + */
 182 +
 183 +#ifndef __ARM_ARCH_MMU_H
 184 +#define __ARM_ARCH_MMU_H
 185 +
 186 +#include <linux/types.h>
 187 +
 188 +/*
 189 + * Translation Table Base Bit Masks
 190 + */
 191 +#define ARM_TRANSLATION_TABLE_MASK               0xFFFFC000
 192 +
 193 +/*
 194 + * Domain Access Control Bit Masks
 195 + */
 196 +#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num)    (0x0 << (domain_num)*2)
 197 +#define ARM_ACCESS_TYPE_CLIENT(domain_num)       (0x1 << (domain_num)*2)
 198 +#define ARM_ACCESS_TYPE_MANAGER(domain_num)      (0x3 << (domain_num)*2)
 199 +
 200 +struct ARM_MMU_FIRST_LEVEL_FAULT {
 201 +       unsigned int id:2;
 202 +       unsigned int sbz:30;
 203 +};
 204 +
 205 +#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
 206 +
 207 +struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
 208 +       unsigned int id:2;
 209 +       unsigned int imp:2;
 210 +       unsigned int domain:4;
 211 +       unsigned int sbz:1;
 212 +       unsigned int base_address:23;
 213 +};
 214 +
 215 +#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
 216 +
 217 +struct ARM_MMU_FIRST_LEVEL_SECTION {
 218 +       unsigned int id:2;
 219 +       unsigned int b:1;
 220 +       unsigned int c:1;
 221 +       unsigned int imp:1;
 222 +       unsigned int domain:4;
 223 +       unsigned int sbz0:1;
 224 +       unsigned int ap:2;
 225 +       unsigned int sbz1:8;
 226 +       unsigned int base_address:12;
 227 +};
 228 +
 229 +#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
 230 +
 231 +struct ARM_MMU_FIRST_LEVEL_RESERVED {
 232 +       unsigned int id:2;
 233 +       unsigned int sbz:30;
 234 +};
 235 +
 236 +#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
 237 +
 238 +#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
 239 +       (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
 240 +
 241 +#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
 242 +
 243 +#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,           \
 244 +                       cacheable, bufferable, perm)                    \
 245 +       {                                                               \
 246 +       register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;             \
 247 +       desc.word = 0;                                                  \
 248 +       desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;               \
 249 +       desc.section.domain = 0;                                        \
 250 +       desc.section.c = (cacheable);                                   \
 251 +       desc.section.b = (bufferable);                                  \
 252 +       desc.section.ap = (perm);                                       \
 253 +       desc.section.base_address = (actual_base);                      \
 254 +       *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
 255 +                               = desc.word;                            \
 256 +       }
 257 +
 258 +#define X_ARM_MMU_SECTION(abase, vbase, size, cache, buff, access)     \
 259 +       {                                                               \
 260 +               int i; int j = abase; int k = vbase;                    \
 261 +               for (i = size; i > 0 ; i--, j++, k++)                   \
 262 +                       ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
 263 +       }
 264 +
 265 +union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
 266 +       unsigned long word;
 267 +       struct ARM_MMU_FIRST_LEVEL_FAULT fault;
 268 +       struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
 269 +       struct ARM_MMU_FIRST_LEVEL_SECTION section;
 270 +       struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
 271 +};
 272 +
 273 +#define ARM_UNCACHEABLE                0
 274 +#define ARM_CACHEABLE          1
 275 +#define ARM_UNBUFFERABLE       0
 276 +#define ARM_BUFFERABLE         1
 277 +
 278 +#define ARM_ACCESS_PERM_NONE_NONE      0
 279 +#define ARM_ACCESS_PERM_RO_NONE                0
 280 +#define ARM_ACCESS_PERM_RO_RO          0
 281 +#define ARM_ACCESS_PERM_RW_NONE                1
 282 +#define ARM_ACCESS_PERM_RW_RO          2
 283 +#define ARM_ACCESS_PERM_RW_RW          3
 284 +
 285 +/*
 286 + * Initialization for the Domain Access Control Register
 287 + */
 288 +#define ARM_ACCESS_DACR_DEFAULT      ( \
 289 +       ARM_ACCESS_TYPE_MANAGER(0)    | \
 290 +       ARM_ACCESS_TYPE_NO_ACCESS(1)  | \
 291 +       ARM_ACCESS_TYPE_NO_ACCESS(2)  | \
 292 +       ARM_ACCESS_TYPE_NO_ACCESS(3)  | \
 293 +       ARM_ACCESS_TYPE_NO_ACCESS(4)  | \
 294 +       ARM_ACCESS_TYPE_NO_ACCESS(5)  | \
 295 +       ARM_ACCESS_TYPE_NO_ACCESS(6)  | \
 296 +       ARM_ACCESS_TYPE_NO_ACCESS(7)  | \
 297 +       ARM_ACCESS_TYPE_NO_ACCESS(8)  | \
 298 +       ARM_ACCESS_TYPE_NO_ACCESS(9)  | \
 299 +       ARM_ACCESS_TYPE_NO_ACCESS(10) | \
 300 +       ARM_ACCESS_TYPE_NO_ACCESS(11) | \
 301 +       ARM_ACCESS_TYPE_NO_ACCESS(12) | \
 302 +       ARM_ACCESS_TYPE_NO_ACCESS(13) | \
 303 +       ARM_ACCESS_TYPE_NO_ACCESS(14) | \
 304 +       ARM_ACCESS_TYPE_NO_ACCESS(15))
 305 +
 306 +/*
 307 + * Translate the virtual address of ram space to physical address
 308 + * It is dependent on the implementation of mmu_init
 309 + */
 310 +inline void *iomem_to_phys(unsigned long virt)
 311 +{
 312 +       if (virt >= 0xB0000000)
 313 +               return (void *)((virt - 0xB0000000) + PHYS_SDRAM_1);
 314 +
 315 +       return (void *)virt;
 316 +}
 317 +
 318 +/*
 319 + * remap the physical address of ram space to uncacheable virtual address space
 320 + * It is dependent on the implementation of hal_mmu_init
 321 + */
 322 +void *__ioremap(unsigned long offset, size_t size, unsigned long flags)
 323 +{
 324 +       if (1 == flags) {
 325 +               if (offset >= PHYS_SDRAM_1 &&
 326 +                       offset < (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
 327 +                       return (void *)(offset - PHYS_SDRAM_1) + 0xB0000000;
 328 +               else
 329 +                       return NULL;
 330 +       } else
 331 +               return (void *)offset;
 332 +}
 333 +
 334 +/*
 335 + * Remap the physical address of ram space to uncacheable virtual address space
 336 + * It is dependent on the implementation of hal_mmu_init
 337 + */
 338 +void __iounmap(void *addr)
 339 +{
 340 +       return;
 341 +}
 342 +
 343 +#endif
 344 diff --git a/include/configs/mx53_evk.h b/include/configs/mx53_evk.h
 345 index 010ac76..17650d8 100644
 346 --- a/include/configs/mx53_evk.h
 347 +++ b/include/configs/mx53_evk.h
 348 @@ -36,6 +36,9 @@
 349
 350  #define CONFIG_SKIP_RELOCATE_UBOOT
 351
 352 +#define CONFIG_ARCH_CPU_INIT
 353 +#define CONFIG_ARCH_MMU
 354 +
 355  #define CONFIG_MX53_HCLK_FREQ  24000000        /* RedBoot says 26MHz */
 356
 357  #define CONFIG_DISPLAY_CPUINFO
 358 @@ -197,6 +200,8 @@
 359  #define CONFIG_NR_DRAM_BANKS   1
 360  #define PHYS_SDRAM_1           CSD0_BASE_ADDR
 361  #define PHYS_SDRAM_1_SIZE      (1024 * 1024 * 1024)
 362 +#define iomem_valid_addr(addr, size) \
 363 +       (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
 364
 365  /*-----------------------------------------------------------------------
 366   * FLASH and environment organization
 367 --
 368 1.5.4.4
 369