1 From c3dfebadafa09e722f5e0872691f9473f560e9de Mon Sep 17 00:00:00 2001
2 From: Jason <r64343@freescale.com>
3 Date: Thu, 1 Apr 2010 11:14:40 +0800
4 Subject: [PATCH] ENGR00122203 UBOOT: Add MX53 ARM2 board support
6 Both EVK and ARM2 board using the same machine id.
7 Currently, use system_rev to diff ARM2 board. DDR freq
8 for ARM2 has been set to 400M, but 300M on EVK.
10 Signed-off-by:Jason Liu <r64343@freescale.com>
13 board/freescale/mx53_evk/flash_header.S | 71 +++++++++
14 board/freescale/mx53_evk/lowlevel_init.S | 67 +++++----
15 board/freescale/mx53_evk/mx53_evk.c | 6 +-
16 include/configs/mx53_arm2.h | 238 ++++++++++++++++++++++++++++++
17 include/configs/mx53_evk.h | 8 +-
18 6 files changed, 354 insertions(+), 37 deletions(-)
20 diff --git a/Makefile b/Makefile
21 index fc90ef7..aa0317a 100644
24 @@ -3255,6 +3255,7 @@ mx51_3stack_android_config \
25 mx51_3stack_config : unconfig
26 @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51_3stack freescale mx51
29 mx53_evk_config : unconfig
30 @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_evk freescale mx53
32 diff --git a/board/freescale/mx53_evk/flash_header.S b/board/freescale/mx53_evk/flash_header.S
33 index 459c01e..38497c8 100644
34 --- a/board/freescale/mx53_evk/flash_header.S
35 +++ b/board/freescale/mx53_evk/flash_header.S
36 @@ -52,6 +52,7 @@ boot_data: .word 0x77800000
37 image_len: .word 256 * 1024
40 +#ifdef CONFIG_MX53_EVK
41 dcd_hdr: .word 0x400802D2 /* Tag=0xD2, Len=64*8 + 4 + 4, Ver=0x40 */
42 write_dcd_cmd: .word 0x040402CC /* Tag=0xCC, Len=64*8 + 4, Param=4 */
44 @@ -120,4 +121,74 @@ MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x01c, 0x00468039)
45 MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x020, 0x00005800)
46 MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x058, 0x00033337)
47 MXC_DCD_ITEM(64, ESDCTL_BASE_ADDR + 0x01c, 0x00000000)
50 +dcd_hdr: .word 0x400002D2 /* Tag=0xD2, Len=63*8 + 4 + 4, Ver=0x40 */
51 +write_dcd_cmd: .word 0x04FC01CC /* Tag=0xCC, Len=63*8 + 4, Param=4 */
54 +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00380000)
55 +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x558, 0x00380040)
56 +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x560, 0x00380000)
57 +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x564, 0x00380040)
58 +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x568, 0x00380040)
59 +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x570, 0x00380000)
60 +MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x574, 0x00380000)
61 +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x578, 0x00380000)
62 +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x57c, 0x00380040)
63 +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00380040)
64 +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x584, 0x00380000)
65 +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x588, 0x00380000)
66 +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x590, 0x00380040)
67 +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x594, 0x00380000)
68 +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x6f0, 0x00380000)
69 +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x6f4, 0x00000200)
70 +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000)
71 +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x714, 0x00000000)
72 +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x718, 0x00380000)
73 +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x71c, 0x00380000)
74 +MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x720, 0x00380000)
75 +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x724, 0x02000000)
76 +MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x728, 0x00380000)
77 +MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x72c, 0x00380000)
78 +MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x088, 0x2d313331)
79 +MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x090, 0x40363333)
80 +MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x0f8, 0x00000800)
81 +MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x07c, 0x020c0211)
82 +MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x080, 0x014c0155)
83 +MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x018, 0x00001710)
84 +MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x000, 0xc4110000)
85 +MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x00c, 0x4d5122d2)
86 +MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x010, 0x92d18a22)
87 +MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x014, 0x00c70092)
88 +MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2)
89 +MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x030, 0x009f000e)
90 +MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x008, 0x12272000)
91 +MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x004, 0x00030012)
92 +MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x01c, 0x04008010)
93 +MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x00008032)
94 +MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x00008033)
95 +MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x00008031)
96 +MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x0b5280b0)
97 +MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x04008010)
98 +MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x00008020)
99 +MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x00008020)
100 +MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x0a528030)
101 +MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x01c, 0x03c68031)
102 +MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x01c, 0x00468031)
103 +MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x01c, 0x04008018)
104 +MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a)
105 +MXC_DCD_ITEM(52, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b)
106 +MXC_DCD_ITEM(53, ESDCTL_BASE_ADDR + 0x01c, 0x00008039)
107 +MXC_DCD_ITEM(54, ESDCTL_BASE_ADDR + 0x01c, 0x0b528138)
108 +MXC_DCD_ITEM(55, ESDCTL_BASE_ADDR + 0x01c, 0x04008018)
109 +MXC_DCD_ITEM(56, ESDCTL_BASE_ADDR + 0x01c, 0x00008028)
110 +MXC_DCD_ITEM(57, ESDCTL_BASE_ADDR + 0x01c, 0x00008028)
111 +MXC_DCD_ITEM(58, ESDCTL_BASE_ADDR + 0x01c, 0x0a528038)
112 +MXC_DCD_ITEM(59, ESDCTL_BASE_ADDR + 0x01c, 0x03c68039)
113 +MXC_DCD_ITEM(60, ESDCTL_BASE_ADDR + 0x01c, 0x00468039)
114 +MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x020, 0x00005800)
115 +MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x058, 0x00033337)
116 +MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x01c, 0x00000000)
119 diff --git a/board/freescale/mx53_evk/lowlevel_init.S b/board/freescale/mx53_evk/lowlevel_init.S
120 index c67c584..d5e9f66 100644
121 --- a/board/freescale/mx53_evk/lowlevel_init.S
122 +++ b/board/freescale/mx53_evk/lowlevel_init.S
124 .endm /* init_aips */
126 .macro setup_pll pll, freq
130 - str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
131 + str r1, [r0, #PLL_DP_CTL]
133 - str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
134 + str r1, [r0, #PLL_DP_CONFIG]
136 - str r3, [r2, #PLL_DP_OP]
137 - str r3, [r2, #PLL_DP_HFS_OP]
138 + ldr r1, W_DP_OP_\freq
139 + str r1, [r0, #PLL_DP_OP]
140 + str r1, [r0, #PLL_DP_HFS_OP]
142 - str r4, [r2, #PLL_DP_MFD]
143 - str r4, [r2, #PLL_DP_HFS_MFD]
144 + ldr r1, W_DP_MFD_\freq
145 + str r1, [r0, #PLL_DP_MFD]
146 + str r1, [r0, #PLL_DP_HFS_MFD]
148 - str r5, [r2, #PLL_DP_MFN]
149 - str r5, [r2, #PLL_DP_HFS_MFN]
150 + ldr r1, W_DP_MFN_\freq
151 + str r1, [r0, #PLL_DP_MFN]
152 + str r1, [r0, #PLL_DP_HFS_MFN]
155 - str r1, [r2, #PLL_DP_CTL]
156 -1: ldr r1, [r2, #PLL_DP_CTL]
157 + str r1, [r0, #PLL_DP_CTL]
158 +1: ldr r1, [r0, #PLL_DP_CTL]
164 str r1, [r0, #CLKCTL_CCSR]
167 - mov r4, #DP_MFD_800
168 - mov r5, #DP_MFN_800
169 setup_pll PLL1_BASE_ADDR, 800
172 - mov r4, #DP_MFD_400
173 - mov r5, #DP_MFN_400
174 setup_pll PLL3_BASE_ADDR, 400
176 /* Switch peripheral to PLL3 */
178 ldr r1, CCM_VAL_0x00015154
179 str r1, [r0, #CLKCTL_CBCMR]
180 ldr r1, CCM_VAL_0x02888945
181 - orr r1, r1, #(1 << 16) /* Set DDR divider to run at 200MHz */
182 + orr r1, r1, #(1 << 16)
183 str r1, [r0, #CLKCTL_CBCDR]
184 - /* make sure mux & divider change is effective */
185 + /* make sure change is effective */
186 1: ldr r1, [r0, #CLKCTL_CDHIPR]
191 - mov r4, #DP_MFD_600
192 - mov r5, #DP_MFN_600
193 - setup_pll PLL2_BASE_ADDR, 600
194 + setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ
196 /* Switch peripheral to PLL2 */
197 ldr r0, CCM_BASE_ADDR_W
198 - ldr r1, CCM_VAL_0x00809145 /* AHB is 120MHz, from PLL2 */
199 - orr r1, r1, #(1 << 16) /* Set DDR divider to run at 300MHz */
200 - orr r1, r1, #(2 << 19) /* Set AXI_B divider to run at 200MHz */
201 + ldr r1, CCM_VAL_0x00808145
202 + orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10)
203 + orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16)
204 + orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19)
205 str r1, [r0, #CLKCTL_CBCDR]
207 ldr r1, CCM_VAL_0x00016154
208 str r1, [r0, #CLKCTL_CBCMR]
210 - /* make sure mux change is effective */
211 + /* make sure change is effective */
212 1: ldr r1, [r0, #CLKCTL_CDHIPR]
217 - mov r4, #DP_MFD_216
218 - mov r5, #DP_MFN_216
219 setup_pll PLL3_BASE_ADDR, 216
221 /* Set the platform clock dividers */
223 ldr r1, PLATFORM_CLOCK_DIV_W
224 str r1, [r0, #PLATFORM_ICGC]
227 ldr r0, CCM_BASE_ADDR_W
229 str r1, [r0, #CLKCTL_CACRR]
230 @@ -209,8 +200,20 @@ lowlevel_init:
231 /* Board level setting value */
232 CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
233 CCM_VAL_0x00016154: .word 0x00016154
234 -CCM_VAL_0x00809145: .word 0x00809145
235 +CCM_VAL_0x00808145: .word 0x00808145
236 CCM_VAL_0x00015154: .word 0x00015154
237 CCM_VAL_0x02888945: .word 0x02888945
238 +W_DP_OP_800: .word DP_OP_800
239 +W_DP_MFD_800: .word DP_MFD_800
240 +W_DP_MFN_800: .word DP_MFN_800
241 +W_DP_OP_600: .word DP_OP_600
242 +W_DP_MFD_600: .word DP_MFD_600
243 +W_DP_MFN_600: .word DP_MFN_600
244 +W_DP_OP_400: .word DP_OP_400
245 +W_DP_MFD_400: .word DP_MFD_400
246 +W_DP_MFN_400: .word DP_MFN_400
247 +W_DP_OP_216: .word DP_OP_216
248 +W_DP_MFD_216: .word DP_MFD_216
249 +W_DP_MFN_216: .word DP_MFN_216
250 PLATFORM_BASE_ADDR_W: .word ARM_BASE_ADDR
251 PLATFORM_CLOCK_DIV_W: .word 0x00000124
252 diff --git a/board/freescale/mx53_evk/mx53_evk.c b/board/freescale/mx53_evk/mx53_evk.c
253 index 9661df6..9526b2d 100644
254 --- a/board/freescale/mx53_evk/mx53_evk.c
255 +++ b/board/freescale/mx53_evk/mx53_evk.c
256 @@ -107,7 +107,7 @@ static inline void setup_soc_rev(void)
257 system_rev = 0x53000 | CHIP_REV_1_0;
260 -static inline void set_board_rev(int rev)
261 +static inline void setup_board_rev(int rev)
263 system_rev |= (rev & 0xF) << 8;
265 @@ -495,7 +495,9 @@ int board_init(void)
270 +#ifdef CONFIG_MX53_ARM2
271 + setup_board_rev(1);
273 gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK; /* board id for linux */
274 /* address of boot parameters */
275 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
276 diff --git a/include/configs/mx53_arm2.h b/include/configs/mx53_arm2.h
278 index 0000000..5517459
280 +++ b/include/configs/mx53_arm2.h
283 + * Copyright (C) 2010 Freescale Semiconductor, Inc.
285 + * Configuration settings for the MX53-ARM2 Freescale board.
287 + * This program is free software; you can redistribute it and/or
288 + * modify it under the terms of the GNU General Public License as
289 + * published by the Free Software Foundation; either version 2 of
290 + * the License, or (at your option) any later version.
292 + * This program is distributed in the hope that it will be useful,
293 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
294 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
295 + * GNU General Public License for more details.
297 + * You should have received a copy of the GNU General Public License
298 + * along with this program; if not, write to the Free Software
299 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
300 + * MA 02111-1307 USA
306 +#include <asm/arch/mx53.h>
308 + /* High Level Configuration Options */
309 +#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */
312 +#define CONFIG_MX53_ARM2
313 +#define CONFIG_FLASH_HEADER
314 +#define CONFIG_FLASH_HEADER_OFFSET 0x400
316 +#define CONFIG_SKIP_RELOCATE_UBOOT
318 +#define CONFIG_ARCH_CPU_INIT
319 +#define CONFIG_ARCH_MMU
321 +#define CONFIG_MX53_HCLK_FREQ 24000000
322 +#define CONFIG_SYS_PLL2_FREQ 400
323 +#define CONFIG_SYS_AHB_PODF 2
324 +#define CONFIG_SYS_AXIA_PODF 0
325 +#define CONFIG_SYS_AXIB_PODF 1
327 +#define CONFIG_DISPLAY_CPUINFO
328 +#define CONFIG_DISPLAY_BOARDINFO
330 +#define CONFIG_SYS_64BIT_VSPRINTF
332 +#define BOARD_LATE_INIT
334 + * Disabled for now due to build problems under Debian and a significant
335 + * increase in the final file size: 144260 vs. 109536 Bytes.
338 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
339 +#define CONFIG_REVISION_TAG 1
340 +#define CONFIG_SETUP_MEMORY_TAGS 1
341 +#define CONFIG_INITRD_TAG 1
344 + * Size of malloc() pool
346 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
347 +/* size in bytes reserved for initial data */
348 +#define CONFIG_SYS_GBL_DATA_SIZE 128
353 +#define CONFIG_MX53_UART 1
354 +#define CONFIG_MX53_UART1 1
356 +/* allow to overwrite serial and ethaddr */
357 +#define CONFIG_ENV_OVERWRITE
358 +#define CONFIG_CONS_INDEX 1
359 +#define CONFIG_BAUDRATE 115200
360 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
362 +/***********************************************************
363 + * Command definition
364 + ***********************************************************/
366 +#include <config_cmd_default.h>
368 +#define CONFIG_CMD_PING
369 +#define CONFIG_CMD_DHCP
370 +#define CONFIG_CMD_MII
371 +#define CONFIG_CMD_NET
372 +#define CONFIG_NET_RETRY_COUNT 100
373 +#define CONFIG_NET_MULTI 1
374 +#define CONFIG_BOOTP_SUBNETMASK
375 +#define CONFIG_BOOTP_GATEWAY
376 +#define CONFIG_BOOTP_DNS
378 +#define CONFIG_CMD_MMC
379 +#define CONFIG_CMD_ENV
381 +#undef CONFIG_CMD_IMLS
383 +#define CONFIG_BOOTDELAY 3
385 +#define CONFIG_PRIME "FEC0"
387 +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
388 +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
390 +#define CONFIG_EXTRA_ENV_SETTINGS \
392 + "ethprime=FEC0\0" \
393 + "uboot=u-boot.bin\0" \
394 + "kernel=uImage\0" \
395 + "nfsroot=/opt/eldk/arm\0" \
396 + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
397 + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
398 + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
399 + "bootcmd_net=run bootargs_base bootargs_nfs; " \
400 + "tftpboot ${loadaddr} ${kernel}; bootm\0" \
401 + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \
402 + "root=/dev/mmcblk0p2 rootwait\0" \
403 + "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \
404 + "bootcmd=run bootcmd_net\0" \
407 +#define CONFIG_ARP_TIMEOUT 200UL
410 + * Miscellaneous configurable options
412 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
413 +#define CONFIG_SYS_PROMPT "ARM2 U-Boot > "
414 +#define CONFIG_AUTO_COMPLETE
415 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
416 +/* Print Buffer Size */
417 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
418 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
419 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
421 +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
422 +#define CONFIG_SYS_MEMTEST_END 0x10000
424 +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
426 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
428 +#define CONFIG_SYS_HZ 1000
430 +#define CONFIG_CMDLINE_EDITING 1
432 +#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
433 +#define CONFIG_FEC0_PINMUX -1
434 +#define CONFIG_FEC0_PHY_ADDR -1
435 +#define CONFIG_FEC0_MIIBASE -1
437 +#define CONFIG_MXC_FEC
439 +#define CONFIG_MII_GASKET
440 +#define CONFIG_DISCOVER_PHY
445 +#define CONFIG_CMD_I2C 1
446 +#define CONFIG_HARD_I2C 1
447 +#define CONFIG_I2C_MXC 1
448 +#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
449 +#define CONFIG_SYS_I2C_SPEED 100000
450 +#define CONFIG_SYS_I2C_SLAVE 0xfe
456 +#define CONFIG_FSL_SF 1
457 +#define CONFIG_CMD_SPI
458 +#define CONFIG_CMD_SF
459 +#define CONFIG_SPI_FLASH_IMX_ATMEL 1
460 +#define CONFIG_SPI_FLASH_CS 1
461 +#define CONFIG_IMX_ECSPI
462 +#define IMX_CSPI_VER_2_3 1
463 +#define MAX_SPI_BYTES (64 * 4)
468 +#ifdef CONFIG_CMD_MMC
469 + #define CONFIG_MMC 1
470 + #define CONFIG_GENERIC_MMC
471 + #define CONFIG_IMX_MMC
472 + #define CONFIG_SYS_FSL_ESDHC_NUM 2
473 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0
474 + #define CONFIG_SYS_MMC_ENV_DEV 1
475 + #define CONFIG_DOS_PARTITION 1
476 + #define CONFIG_CMD_FAT 1
477 + #define CONFIG_CMD_EXT2 1
479 +/*-----------------------------------------------------------------------
482 + * The stack sizes are set up in start.S using the settings below
484 +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
486 +/*-----------------------------------------------------------------------
487 + * Physical Memory Map
489 +#define CONFIG_NR_DRAM_BANKS 1
490 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR
491 +#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
492 +#define iomem_valid_addr(addr, size) \
493 + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
495 +/*-----------------------------------------------------------------------
496 + * FLASH and environment organization
498 +#define CONFIG_SYS_NO_FLASH
500 +/* Monitor at beginning of flash */
501 +#define CONFIG_FSL_ENV_IN_MMC
503 +#define CONFIG_ENV_SECT_SIZE (128 * 1024)
504 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
506 +#if defined(CONFIG_FSL_ENV_IN_NAND)
507 + #define CONFIG_ENV_IS_IN_NAND 1
508 + #define CONFIG_ENV_OFFSET 0x100000
509 +#elif defined(CONFIG_FSL_ENV_IN_MMC)
510 + #define CONFIG_ENV_IS_IN_MMC 1
511 + #define CONFIG_ENV_OFFSET (768 * 1024)
512 +#elif defined(CONFIG_FSL_ENV_IN_SF)
513 + #define CONFIG_ENV_IS_IN_SPI_FLASH 1
514 + #define CONFIG_ENV_SPI_CS 1
515 + #define CONFIG_ENV_OFFSET (768 * 1024)
517 + #define CONFIG_ENV_IS_NOWHERE 1
519 +#endif /* __CONFIG_H */
520 diff --git a/include/configs/mx53_evk.h b/include/configs/mx53_evk.h
521 index b327a92..85bd02f 100644
522 --- a/include/configs/mx53_evk.h
523 +++ b/include/configs/mx53_evk.h
526 /* High Level Configuration Options */
527 #define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */
528 -#define CONFIG_SYS_APCS_GNU
532 #define CONFIG_MX53_EVK
534 #define CONFIG_ARCH_CPU_INIT
535 #define CONFIG_ARCH_MMU
537 -#define CONFIG_MX53_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
538 +#define CONFIG_MX53_HCLK_FREQ 24000000
539 +#define CONFIG_SYS_PLL2_FREQ 600
540 +#define CONFIG_SYS_AHB_PODF 4
541 +#define CONFIG_SYS_AXIA_PODF 1
542 +#define CONFIG_SYS_AXIB_PODF 2
544 #define CONFIG_DISPLAY_CPUINFO
545 #define CONFIG_DISPLAY_BOARDINFO