1 From 06397921bf3d9cf8cf56ccdffab5397867dce1d1 Mon Sep 17 00:00:00 2001
2 From: Jason Liu <r64343@freescale.com>
3 Date: Thu, 8 Jul 2010 02:57:44 +0800
4 Subject: [PATCH] ENGR00124954 MX50: init sys by ROM plug-in feature
6 Use ROM plug-in feature to init DDR and re-config PLL1 to
7 800Mhz due to ROM set it to 799Mhz. Plug-in has the following benifit
8 from ROM team comments,
9 1. DCD size limitation issue, plugin can be the size of OCRAM
10 free space region which is 72KB.
11 2. Safe environment to re-configure PLL1 (without impacting SDRAM)
12 as the plugin runs from OCRAM. This could get around the issue
13 of some boards running with ARM @ 192MHz due to the incorrect
14 GPIO configuration for Low Power Boot.
15 3. Ability to have one bootloader binary for both LPDDR1 & LPDDR2 platforms.
17 Signed-off-by: Jason Liu <r64343@freescale.com>
19 board/freescale/mx50_arm2/flash_header.S | 1059 +++++++++++++++++++++---------
20 1 files changed, 752 insertions(+), 307 deletions(-)
22 diff --git a/board/freescale/mx50_arm2/flash_header.S b/board/freescale/mx50_arm2/flash_header.S
23 index aa246df..fbab4f5 100644
24 --- a/board/freescale/mx50_arm2/flash_header.S
25 +++ b/board/freescale/mx50_arm2/flash_header.S
27 # error "Must define the offset of flash header"
30 -#define CPU_2_BE_32(l) \
31 - ((((l) & 0x000000FF) << 24) | \
32 - (((l) & 0x0000FF00) << 8) | \
33 - (((l) & 0x00FF0000) >> 8) | \
34 - (((l) & 0xFF000000) >> 24))
36 -#define MXC_DCD_ITEM(i, addr, val) \
38 - .word CPU_2_BE_32(addr) ; \
39 - .word CPU_2_BE_32(val) ; \
41 -#define DCDGEN_CHECKDATA(i,addr,mask,count) \
43 - .word CPU_2_BE_32(addr) ;\
44 - .word CPU_2_BE_32(mask) ;\
45 - .word CPU_2_BE_32(count) ;\
47 .section ".text.flasheader", "x"
49 .org CONFIG_FLASH_HEADER_OFFSET
50 -ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
51 -app_code_jump_v: .word _start
53 -dcd_ptr: .word dcd_hdr
54 -boot_data_ptr: .word boot_data
55 -self_ptr: .word ivt_header
56 -app_code_csf: .word 0x0
59 -boot_data: .word TEXT_BASE
60 -image_len: .word _end - TEXT_BASE
63 -#if defined(CONFIG_LPDDR2)
64 +/* First IVT to copy the plugin that initializes the system into OCRAM */
65 +ivt_header: .long 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
66 +app_code_jump_v: .long 0xF8006458 /* Plugin entry point */
69 +boot_data_ptr: .long 0xF8006420
70 +self_ptr: .long 0xF8006400
71 +app_code_csf: .long 0x0 /* reserve 4K for csf */
73 +boot_data: .long 0xF8006000
74 +image_len: .long 8*1024 /* Can copy upto 72K, OCRAM free space */
75 +plugin: .long 0x1 /* Enable plugin flag */
77 +/* Second IVT to give entry point into the bootloader copied to DDR */
78 +ivt2_header: .long 0x402000D1 //Tag=0xD1, Len=0x0020, Ver=0x40
79 +app2_code_jump_v: .long _start // Entry point for the bootloader
82 +boot_data2_ptr: .long boot_data2
83 +self_ptr2: .long ivt2_header
84 +app_code_csf2: .long 0x0 // reserve 4K for csf
86 +boot_data2: .long TEXT_BASE
87 +image_len2: .long _end - TEXT_BASE
90 +/*=============================================================================
91 + * Here starts the plugin code
92 + *===========================================================================*/
95 +/* Save the return address and the function arguments */
98 +/*=============================================================================
99 + *init script for codex LPDDR1-200MHz CPU board
100 + *===========================================================================*/
102 +/* Setup PLL1 to be 800 MHz */
103 + ldr r0, =CCM_BASE_ADDR
105 +/* Switch ARM domain to be clocked from LP-APM */
107 + str r1, [r0, #CLKCTL_CCSR]
109 + ldr r0, =PLL1_BASE_ADDR
111 + str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
113 + str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
116 + str r1, [r0, #PLL_DP_OP]
117 + str r1, [r0, #PLL_DP_HFS_OP]
119 + ldr r1, =DP_MFD_800
120 + str r1, [r0, #PLL_DP_MFD]
121 + str r1, [r0, #PLL_DP_HFS_MFD]
123 + ldr r1, =DP_MFN_800
124 + str r1, [r0, #PLL_DP_MFN]
125 + str r1, [r0, #PLL_DP_HFS_MFN]
127 + /* Now restart PLL */
129 + str r1, [r0, #PLL_DP_CTL]
131 + ldr r1, [r0, #PLL_DP_CTL]
135 +/* Switch ARM back to PLL1 */
136 + ldr r0, =CCM_BASE_ADDR
138 + str r1, [r0,#CLKCTL_CCSR]
140 +/*=============================================================================
141 + * Enable all clocks (they are disabled by ROM code)
142 + *===========================================================================*/
144 + mov r1, #0xffffffff
145 + str r1, [r0, #0x68]
146 + str r1, [r0, #0x6c]
147 + str r1, [r0, #0x70]
148 + str r1, [r0, #0x74]
149 + str r1, [r0, #0x78]
150 + str r1, [r0, #0x7c]
151 + str r1, [r0, #0x80]
152 + str r1, [r0, #0x84]
154 -/* DCD for LPDDR2 board */
156 -/* Tag=0xD2, Len=4 + 76 + 16 + 844 + 26 = 966 (0x03c6), Ver=0x40. */
157 -dcd_hdr: .word 0x40c603D2
159 -/* Tag = 0xCC, Len = 9*8 + 4 = 76(0x4C), Param = 4 */
160 -write_ccm_dcd_cmd: .word 0x044C00CC
162 -MXC_DCD_ITEM(01, 0x53fd4068 , 0xffffffff)
163 -MXC_DCD_ITEM(02, 0x53fd406c , 0xffffffff)
164 -MXC_DCD_ITEM(03, 0x53fd4070 , 0xffffffff)
165 -MXC_DCD_ITEM(04, 0x53fd4074 , 0xffffffff)
166 -MXC_DCD_ITEM(05, 0x53fd4078 , 0xffffffff)
167 -MXC_DCD_ITEM(06, 0x53fd407c , 0xffffffff)
168 -MXC_DCD_ITEM(07, 0x53fd4080 , 0xffffffff)
169 -MXC_DCD_ITEM(08, 0x53fd4084 , 0xffffffff)
170 -MXC_DCD_ITEM(09, 0x53FD4098 , 0x80000003)
172 -/* poll for completion of CCM_CSR2 for update: use dummy write to wait */
173 -/* Tag = 0xCF, Len = 1*12 + 4 = 16(0x10), Param = 4(Mast & Set bit are zero) */
174 -check_data_dcd_cmd: .word 0x241000CF
175 -/* loop 0x1FFFFFFF times to make sure bit 2(ddr_clk_ref_pll_bsy) is cleared */
176 -DCDGEN_CHECKDATA(1, CCM_BASE_ADDR + 0x8c, 0x04, 0x1FFFFFFF)
178 -/* Tag=0xCC, Len=105*8 + 4 = 844(0x034C), Param=4 */
179 -write_dcd_cmd: .word 0x044C03CC
181 -MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x6ac, 0x04000000)
182 -MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x6a4, 0x00380000)
183 -MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x668, 0x00380000)
184 -MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x698, 0x00380000)
185 -MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x6a0, 0x00380000)
186 -MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x6a8, 0x00380000)
187 -MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x6b4, 0x00380000)
188 -MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x498, 0x00380000)
189 -MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x49c, 0x00380000)
190 -MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4f0, 0x00380000)
191 -MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x500, 0x00380000)
192 -MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x4c8, 0x00380000)
193 -MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x528, 0x00380000)
194 -MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x4f4, 0x00380000)
195 -MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x4fc, 0x00380000)
196 -MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4cc, 0x00380000)
197 -MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x524, 0x00380000)
199 -MXC_DCD_ITEM(18, DATABAHN_BASE_ADDR + 0x000, 0x00000500)
200 -MXC_DCD_ITEM(19, DATABAHN_BASE_ADDR + 0x004, 0x00000000)
201 -MXC_DCD_ITEM(20, DATABAHN_BASE_ADDR + 0x008, 0x0000001b)
202 -MXC_DCD_ITEM(21, DATABAHN_BASE_ADDR + 0x00c, 0x0000d056)
203 -MXC_DCD_ITEM(22, DATABAHN_BASE_ADDR + 0x010, 0x0000010b)
204 -MXC_DCD_ITEM(23, DATABAHN_BASE_ADDR + 0x014, 0x00000a6b)
205 -MXC_DCD_ITEM(24, DATABAHN_BASE_ADDR + 0x018, 0x02020d0c)
206 -MXC_DCD_ITEM(25, DATABAHN_BASE_ADDR + 0x01c, 0x0c110302)
207 -MXC_DCD_ITEM(26, DATABAHN_BASE_ADDR + 0x020, 0x05020503)
208 -MXC_DCD_ITEM(27, DATABAHN_BASE_ADDR + 0x024, 0x00000105)
209 -MXC_DCD_ITEM(28, DATABAHN_BASE_ADDR + 0x028, 0x01000403)
210 -MXC_DCD_ITEM(29, DATABAHN_BASE_ADDR + 0x02c, 0x09040501)
211 -MXC_DCD_ITEM(30, DATABAHN_BASE_ADDR + 0x030, 0x02000000)
212 -MXC_DCD_ITEM(31, DATABAHN_BASE_ADDR + 0x034, 0x00000e02)
213 -MXC_DCD_ITEM(32, DATABAHN_BASE_ADDR + 0x038, 0x00000006)
214 -MXC_DCD_ITEM(33, DATABAHN_BASE_ADDR + 0x03c, 0x00002301)
215 -MXC_DCD_ITEM(34, DATABAHN_BASE_ADDR + 0x040, 0x00050408)
216 -MXC_DCD_ITEM(35, DATABAHN_BASE_ADDR + 0x044, 0x00000300)
217 -MXC_DCD_ITEM(36, DATABAHN_BASE_ADDR + 0x048, 0x00260026)
218 -MXC_DCD_ITEM(37, DATABAHN_BASE_ADDR + 0x04c, 0x00010000)
220 -MXC_DCD_ITEM(38, DATABAHN_BASE_ADDR + 0x05c, 0x02000000)
221 -MXC_DCD_ITEM(39, DATABAHN_BASE_ADDR + 0x060, 0x00000002)
222 -MXC_DCD_ITEM(40, DATABAHN_BASE_ADDR + 0x064, 0x00000000)
223 -MXC_DCD_ITEM(41, DATABAHN_BASE_ADDR + 0x068, 0x00000000)
224 -MXC_DCD_ITEM(42, DATABAHN_BASE_ADDR + 0x06c, 0x00040042)
225 -MXC_DCD_ITEM(43, DATABAHN_BASE_ADDR + 0x070, 0x00000001)
226 -MXC_DCD_ITEM(44, DATABAHN_BASE_ADDR + 0x074, 0x00000000)
227 -MXC_DCD_ITEM(45, DATABAHN_BASE_ADDR + 0x078, 0x00040042)
228 -MXC_DCD_ITEM(46, DATABAHN_BASE_ADDR + 0x07c, 0x00000001)
229 -MXC_DCD_ITEM(47, DATABAHN_BASE_ADDR + 0x080, 0x010b0000)
230 -MXC_DCD_ITEM(48, DATABAHN_BASE_ADDR + 0x084, 0x00000060)
231 -MXC_DCD_ITEM(49, DATABAHN_BASE_ADDR + 0x088, 0x02400018)
232 -MXC_DCD_ITEM(50, DATABAHN_BASE_ADDR + 0x08c, 0x01000e00)
233 -MXC_DCD_ITEM(51, DATABAHN_BASE_ADDR + 0x090, 0x0a010101)
234 -MXC_DCD_ITEM(52, DATABAHN_BASE_ADDR + 0x094, 0x01011f1f)
235 -MXC_DCD_ITEM(53, DATABAHN_BASE_ADDR + 0x098, 0x01010101)
236 -MXC_DCD_ITEM(54, DATABAHN_BASE_ADDR + 0x09c, 0x00030101)
237 -MXC_DCD_ITEM(55, DATABAHN_BASE_ADDR + 0x0a0, 0x00010000)
238 -MXC_DCD_ITEM(56, DATABAHN_BASE_ADDR + 0x0a4, 0x00010000)
239 -MXC_DCD_ITEM(57, DATABAHN_BASE_ADDR + 0x0a8, 0x00000000)
240 -MXC_DCD_ITEM(58, DATABAHN_BASE_ADDR + 0x0ac, 0x0000ffff)
241 -MXC_DCD_ITEM(59, DATABAHN_BASE_ADDR + 0x0c8, 0x02020101)
242 -MXC_DCD_ITEM(60, DATABAHN_BASE_ADDR + 0x0cc, 0x01000000)
243 -MXC_DCD_ITEM(61, DATABAHN_BASE_ADDR + 0x0d0, 0x01000201)
244 -MXC_DCD_ITEM(62, DATABAHN_BASE_ADDR + 0x0d4, 0x00000200)
245 -MXC_DCD_ITEM(63, DATABAHN_BASE_ADDR + 0x0d8, 0x00000102)
246 -MXC_DCD_ITEM(64, DATABAHN_BASE_ADDR + 0x0dc, 0x0000ffff)
247 -MXC_DCD_ITEM(65, DATABAHN_BASE_ADDR + 0x0e0, 0x0000ffff)
248 -MXC_DCD_ITEM(66, DATABAHN_BASE_ADDR + 0x0e4, 0x02020000)
249 -MXC_DCD_ITEM(67, DATABAHN_BASE_ADDR + 0x0e8, 0x02020202)
250 -MXC_DCD_ITEM(68, DATABAHN_BASE_ADDR + 0x0ec, 0x00000202)
251 -MXC_DCD_ITEM(69, DATABAHN_BASE_ADDR + 0x0f0, 0x01010064)
252 -MXC_DCD_ITEM(70, DATABAHN_BASE_ADDR + 0x0f4, 0x01010101)
253 -MXC_DCD_ITEM(71, DATABAHN_BASE_ADDR + 0x0f8, 0x00010101)
254 -MXC_DCD_ITEM(72, DATABAHN_BASE_ADDR + 0x0fc, 0x00000064)
255 -MXC_DCD_ITEM(73, DATABAHN_BASE_ADDR + 0x100, 0x00000000)
256 -MXC_DCD_ITEM(74, DATABAHN_BASE_ADDR + 0x104, 0x02000802)
257 -MXC_DCD_ITEM(75, DATABAHN_BASE_ADDR + 0x108, 0x04080000)
258 -MXC_DCD_ITEM(76, DATABAHN_BASE_ADDR + 0x10c, 0x04080408)
259 -MXC_DCD_ITEM(77, DATABAHN_BASE_ADDR + 0x110, 0x04080408)
260 -MXC_DCD_ITEM(78, DATABAHN_BASE_ADDR + 0x114, 0x03060408)
261 -MXC_DCD_ITEM(79, DATABAHN_BASE_ADDR + 0x118, 0x01010002)
262 -MXC_DCD_ITEM(80, DATABAHN_BASE_ADDR + 0x11c, 0x00000000)
264 -MXC_DCD_ITEM(81, DATABAHN_BASE_ADDR + 0x200, 0x00000000)
265 -MXC_DCD_ITEM(82, DATABAHN_BASE_ADDR + 0x204, 0x00000000)
266 -MXC_DCD_ITEM(83, DATABAHN_BASE_ADDR + 0x208, 0xf5003a27)
267 -MXC_DCD_ITEM(84, DATABAHN_BASE_ADDR + 0x20c, 0x074002e1)
268 -MXC_DCD_ITEM(85, DATABAHN_BASE_ADDR + 0x210, 0xf5003a27)
269 -MXC_DCD_ITEM(86, DATABAHN_BASE_ADDR + 0x214, 0x074002e1)
270 -MXC_DCD_ITEM(87, DATABAHN_BASE_ADDR + 0x218, 0xf5003a27)
271 -MXC_DCD_ITEM(88, DATABAHN_BASE_ADDR + 0x21c, 0x074002e1)
272 -MXC_DCD_ITEM(89, DATABAHN_BASE_ADDR + 0x220, 0xf5003a27)
273 -MXC_DCD_ITEM(90, DATABAHN_BASE_ADDR + 0x224, 0x074002e1)
274 -MXC_DCD_ITEM(91, DATABAHN_BASE_ADDR + 0x228, 0xf5003a27)
275 -MXC_DCD_ITEM(92, DATABAHN_BASE_ADDR + 0x22c, 0x074002e1)
276 -MXC_DCD_ITEM(93, DATABAHN_BASE_ADDR + 0x230, 0x00000000)
277 -MXC_DCD_ITEM(94, DATABAHN_BASE_ADDR + 0x234, 0x00810006)
278 -MXC_DCD_ITEM(95, DATABAHN_BASE_ADDR + 0x238, 0x20099414)
279 -MXC_DCD_ITEM(96, DATABAHN_BASE_ADDR + 0x23c, 0x000a1401)
280 -MXC_DCD_ITEM(97, DATABAHN_BASE_ADDR + 0x240, 0x20099414)
281 -MXC_DCD_ITEM(98, DATABAHN_BASE_ADDR + 0x244, 0x000a1401)
282 -MXC_DCD_ITEM(99, DATABAHN_BASE_ADDR + 0x248, 0x20099414)
283 -MXC_DCD_ITEM(100, DATABAHN_BASE_ADDR + 0x24c, 0x000a1401)
284 -MXC_DCD_ITEM(101, DATABAHN_BASE_ADDR + 0x250, 0x20099414)
285 -MXC_DCD_ITEM(102, DATABAHN_BASE_ADDR + 0x254, 0x000a1401)
286 -MXC_DCD_ITEM(103, DATABAHN_BASE_ADDR + 0x258, 0x20099414)
287 -MXC_DCD_ITEM(104, DATABAHN_BASE_ADDR + 0x25c, 0x000a1401)
288 -MXC_DCD_ITEM(105, DATABAHN_BASE_ADDR + 0x000, 0x00000501)
291 -/* poll for completion of HW_DRAM_CTL42 for DDR inti completion */
292 -/* Tag = 0xCF, Len = 1*12 + 4 = 16(0x10), Param = 4 (Mast & Set bit are zero) */
293 -check_ddr_init_dcd_cmd: .word 0x341000CF
294 -/* loop 0x1FFFFFFF times to make sure bit 4 (int_status) is set */
295 -DCDGEN_CHECKDATA(2, DATABAHN_BASE_ADDR + 0xa8, 0x10, 0x1FFFFFFF)
296 +#if defined(CONFIG_LPDDR2)
298 +/* DDR clock setting -- Set DDR to be div 3 to get 266MHz */
299 +/* setmem /32 0x53FD4098 = 0x80000003 */
300 + ldr r1, =0x80000003
301 + str r1, [r0, #0x98]
303 +/* poll to make sure DDR dividers take effect */
305 + ldr r1, [r0, #0x8c]
309 +/*=============================================================================
311 + *===========================================================================*/
312 + ldr r0, =0x53fa8000
313 + mov r1, #0x04000000
314 + str r1, [r0, #0x6ac]
315 + mov r2, #0x00380000
316 + str r2, [r0, #0x6a4]
317 + str r2, [r0, #0x668]
318 + str r2, [r0, #0x698]
319 + str r2, [r0, #0x6a0]
320 + str r2, [r0, #0x6a8]
321 + str r2, [r0, #0x6b4]
322 + str r2, [r0, #0x498]
323 + str r2, [r0, #0x49c]
324 + str r2, [r0, #0x4f0]
325 + str r2, [r0, #0x500]
326 + str r2, [r0, #0x4c8]
327 + str r2, [r0, #0x528]
328 + str r2, [r0, #0x4f4]
329 + str r2, [r0, #0x4fc]
330 + str r2, [r0, #0x4cc]
331 + str r2, [r0, #0x524]
333 +/*=============================================================================
335 + *===========================================================================*/
337 + ldr r0, =DATABAHN_BASE_ADDR
338 +/* setmem /32 0x14000000 = 0x00000500 */
339 + ldr r1, =0x00000500
341 +/* setmem /32 0x14000004 = 0x00000000 */
342 + ldr r1, =0x00000000
344 +/* setmem /32 0x14000008 = 0x0000001b */
345 + ldr r1, =0x0000001b
347 +/* setmem /32 0x1400000c = 0x0000d056 */
348 + ldr r1, =0x0000d056
350 +/* setmem /32 0x14000010 = 0x0000010b */
351 + ldr r1, =0x0000010b
353 +/* setmem /32 0x14000014 = 0x00000a6b */
354 + ldr r1, =0x00000a6b
355 + str r1, [r0, #0x14]
356 +/* setmem /32 0x14000018 = 0x02020d0c */
357 + ldr r1, =0x02020d0c
358 + str r1, [r0, #0x18]
359 +/* setmem /32 0x1400001c = 0x0c110302 */
360 + ldr r1, =0x0c110302
361 + str r1, [r0, #0x1c]
362 +/* setmem /32 0x14000020 = 0x05020503 */
363 + ldr r1, =0x05020503
364 + str r1, [r0, #0x20]
365 +/* setmem /32 0x14000024 = 0x00000105 */
366 + ldr r1, =0x00000105
367 + str r1, [r0, #0x24]
368 +/* setmem /32 0x14000028 = 0x01000403 */
369 + ldr r1, =0x01000403
370 + str r1, [r0, #0x28]
371 +/* setmem /32 0x1400002c = 0x09040501 */
372 + ldr r1, =0x09040501
373 + str r1, [r0, #0x2c]
374 +/* setmem /32 0x14000030 = 0x02000000 */
375 + ldr r1, =0x02000000
376 + str r1, [r0, #0x30]
377 +/* setmem /32 0x14000034 = 0x00000e02 */
378 + ldr r1, =0x00000e02
379 + str r1, [r0, #0x34]
380 +/* setmem /32 0x14000038 = 0x00000006 */
381 + ldr r1, =0x00000006
382 + str r1, [r0, #0x38]
383 +/* setmem /32 0x1400003c = 0x00002301 */
384 + ldr r1, =0x00002301
385 + str r1, [r0, #0x3c]
386 +/* setmem /32 0x14000040 = 0x00050408 */
387 + ldr r1, =0x00050408
388 + str r1, [r0, #0x40]
389 +/* setmem /32 0x14000044 = 0x00000300 */
390 + ldr r1, =0x00000300
391 + str r1, [r0, #0x44]
392 +/* setmem /32 0x14000048 = 0x00260026 */
393 + ldr r1, =0x00260026
394 + str r1, [r0, #0x48]
395 +/* setmem /32 0x1400004c = 0x00010000 */
396 + ldr r1, =0x00010000
397 + str r1, [r0, #0x4c]
398 +/* setmem /32 0x1400005c = 0x02000000 */
399 + ldr r1, =0x02000000
400 + str r1, [r0, #0x5c]
401 +/* setmem /32 0x14000060 = 0x00000002 */
402 + ldr r1, =0x00000002
403 + str r1, [r0, #0x60]
404 +/* setmem /32 0x14000064 = 0x00000000 */
405 + ldr r1, =0x00000000
406 + str r1, [r0, #0x64]
407 +/* setmem /32 0x14000068 = 0x00000000 */
408 + ldr r1, =0x00000000
409 + str r1, [r0, #0x68]
410 +/* setmem /32 0x1400006c = 0x00040042 */
411 + ldr r1, =0x00040042
412 + str r1, [r0, #0x6c]
413 +/* setmem /32 0x14000070 = 0x00000001 */
414 + ldr r1, =0x00000001
415 + str r1, [r0, #0x70]
416 +/* setmem /32 0x14000074 = 0x00000000 */
417 + ldr r1, =0x00000001
418 + str r1, [r0, #0x74]
419 +/* setmem /32 0x14000078 = 0x00040042 */
420 + ldr r1, =0x00040042
421 + str r1, [r0, #0x78]
422 +/* setmem /32 0x1400007c = 0x00000001 */
423 + ldr r1, =0x00000001
424 + str r1, [r0, #0x7c]
425 +/* setmem /32 0x14000080 = 0x010b0000 */
426 + ldr r1, =0x010b0000
427 + str r1, [r0, #0x80]
428 +/* setmem /32 0x14000084 = 0x00000060 */
429 + ldr r1, =0x00000060
430 + str r1, [r0, #0x84]
431 +/* setmem /32 0x14000088 = 0x02400018 */
432 + ldr r1, =0x02400018
433 + str r1, [r0, #0x88]
434 +/* setmem /32 0x1400008c = 0x01000e00 */
435 + ldr r1, =0x01000e00
436 + str r1, [r0, #0x8c]
437 +/* setmem /32 0x14000090 = 0x0a010101 */
438 + ldr r1, =0x0a010101
439 + str r1, [r0, #0x90]
440 +/* setmem /32 0x14000094 = 0x01011f1f */
441 + ldr r1, =0x01011f1f
442 + str r1, [r0, #0x94]
443 +/* setmem /32 0x14000098 = 0x01010101 */
444 + ldr r1, =0x01010101
445 + str r1, [r0, #0x98]
446 +/* setmem /32 0x1400009c = 0x00030101 */
447 + ldr r1, =0x00030101
448 + str r1, [r0, #0x9c]
449 +/* setmem /32 0x140000a0 = 0x00010000 */
450 + ldr r1, =0x00010000
451 + str r1, [r0, #0xa0]
452 +/* setmem /32 0x140000a4 = 0x00010000 */
453 + ldr r1, =0x00010000
454 + str r1, [r0, #0xa4]
455 +/* setmem /32 0x140000a8 = 0x00000000 */
456 + ldr r1, =0x00000000
457 + str r1, [r0, #0xa8]
458 +/* setmem /32 0x140000ac = 0x0000ffff */
459 + ldr r1, =0x0000ffff
460 + str r1, [r0, #0xac]
461 +/* setmem /32 0x140000c8 = 0x02020101 */
462 + ldr r1, =0x02020101
463 + str r1, [r0, #0xc8]
464 +/* setmem /32 0x140000cc = 0x01000000 */
465 + ldr r1, =0x01000000
466 + str r1, [r0, #0xcc]
467 +/* setmem /32 0x140000d0 = 0x01000201 */
468 + ldr r1, =0x01000201
469 + str r1, [r0, #0xd0]
470 +/* setmem /32 0x140000d4 = 0x00000200 */
471 + ldr r1, =0x00000200
472 + str r1, [r0, #0xd4]
473 +/* setmem /32 0x140000d8 = 0x00000102 */
474 + ldr r1, =0x00000102
475 + str r1, [r0, #0xd8]
476 +/* setmem /32 0x140000dc = 0x0000ffff */
477 + ldr r1, =0x0000ffff
478 + str r1, [r0, #0xdc]
479 +/* setmem /32 0x140000e0 = 0x0000ffff */
480 + ldr r1, =0x0000ffff
481 + str r1, [r0, #0xdc]
482 +/* setmem /32 0x140000e4 = 0x02020000 */
483 + ldr r1, =0x02020000
484 + str r1, [r0, #0xe4]
485 +/* setmem /32 0x140000e8 = 0x02020202 */
486 + ldr r1, =0x02020202
487 + str r1, [r0, #0xe8]
488 +/* setmem /32 0x140000ec = 0x00000202 */
489 + ldr r1, =0x00000202
490 + str r1, [r0, #0xec]
491 +/* setmem /32 0x140000f0 = 0x01010064 */
492 + ldr r1, =0x01010064
493 + str r1, [r0, #0xf0]
494 +/* setmem /32 0x140000f4 = 0x01010101 */
495 + ldr r1, =0x01010101
496 + str r1, [r0, #0xf4]
497 +/* setmem /32 0x140000f8 = 0x00010101 */
498 + ldr r1, =0x00010101
499 + str r1, [r0, #0xf8]
500 +/* setmem /32 0x140000fc = 0x00000064 */
501 + ldr r1, =0x00000064
502 + str r1, [r0, #0xfc]
503 +/* setmem /32 0x14000100 = 0x00000000 */
504 + ldr r1, =0x00000000
505 + str r1, [r0, #0x100]
506 +/* setmem /32 0x14000104 = 0x02000802 */
507 + ldr r1, =0x02000802
508 + str r1, [r0, #0x104]
509 +/* setmem /32 0x14000108 = 0x04080000 */
510 + ldr r1, =0x04080000
511 + str r1, [r0, #0x108]
512 +/* setmem /32 0x1400010c = 0x04080408 */
513 + ldr r1, =0x04080408
514 + str r1, [r0, #0x10c]
515 +/* setmem /32 0x14000110 = 0x04080408 */
516 + ldr r1, =0x04080408
517 + str r1, [r0, #0x110]
518 +/* setmem /32 0x14000114 = 0x03060408 */
519 + ldr r1, =0x03060408
520 + str r1, [r0, #0x114]
521 +/* setmem /32 0x14000118 = 0x01010002 */
522 + ldr r1, =0x01010002
523 + str r1, [r0, #0x118]
524 +/* setmem /32 0x1400011c = 0x00000000 */
525 + ldr r1, =0x00000000
526 + str r1, [r0, #0x11c]
527 +/* setmem /32 0x14000200 = 0x00000000 */
528 + ldr r1, =0x00000000
529 + str r1, [r0, #0x200]
530 +/* setmem /32 0x14000204 = 0x00000000 */
531 + ldr r1, =0x00000000
532 + str r1, [r0, #0x204]
533 +/* setmem /32 0x14000208 = 0xf5003a27 */
534 + ldr r1, =0xf5003a27
535 + str r1, [r0, #0x208]
536 +/* setmem /32 0x1400020c = 0x074002e1 */
537 + ldr r1, =0x074002e1
538 + str r1, [r0, #0x20c]
539 +/* setmem /32 0x14000210 = 0xf5003a27 */
540 + ldr r1, =0xf5003a27
541 + str r1, [r0, #0x210]
542 +/* setmem /32 0x14000214 = 0x074002e1 */
543 + ldr r1, =0x074002e1
544 + str r1, [r0, #0x214]
545 +/* setmem /32 0x14000218 = 0xf5003a27 */
546 + ldr r1, =0xf5003a27
547 + str r1, [r0, #0x218]
548 +/* setmem /32 0x1400021c = 0x074002e1 */
549 + ldr r1, =0x074002e1
550 + str r1, [r0, #0x21c]
551 +/* setmem /32 0x14000220 = 0xf5003a27 */
552 + ldr r1, =0xf5003a27
553 + str r1, [r0, #0x220]
554 +/* setmem /32 0x14000224 = 0x074002e1 */
555 + ldr r1, =0x074002e1
556 + str r1, [r0, #0x224]
557 +/* setmem /32 0x14000228 = 0xf5003a27 */
558 + ldr r1, =0xf5003a27
559 + str r1, [r0, #0x228]
560 +/* setmem /32 0x1400022c = 0x074002e1 */
561 + ldr r1, =0x074002e1
562 + str r1, [r0, #0x22c]
563 +/* setmem /32 0x14000230 = 0x00000000 */
564 + ldr r1, =0x00000000
565 + str r1, [r0, #0x230]
566 +/* setmem /32 0x14000234 = 0x00810006 */
567 + ldr r1, =0x00810006
568 + str r1, [r0, #0x234]
569 +/* setmem /32 0x14000238 = 0x20099414 */
570 + ldr r1, =0x20099414
571 + str r1, [r0, #0x238]
572 +/* setmem /32 0x1400023c = 0x000a1401 */
573 + ldr r1, =0x000a1401
574 + str r1, [r0, #0x23c]
575 +/* setmem /32 0x14000240 = 0x20099414 */
576 + ldr r1, =0x20099414
577 + str r1, [r0, #0x240]
578 +/* setmem /32 0x14000244 = 0x000a1401 */
579 + ldr r1, =0x000a1401
580 + str r1, [r0, #0x244]
581 +/* setmem /32 0x14000248 = 0x20099414 */
582 + ldr r1, =0x20099414
583 + str r1, [r0, #0x248]
584 +/* setmem /32 0x1400024c = 0x000a1401 */
585 + ldr r1, =0x000a1401
586 + str r1, [r0, #0x24c]
587 +/* setmem /32 0x14000250 = 0x20099414 */
588 + ldr r1, =0x20099414
589 + str r1, [r0, #0x250]
590 +/* setmem /32 0x14000254 = 0x000a1401 */
591 + ldr r1, =0x000a1401
592 + str r1, [r0, #0x254]
593 +/* setmem /32 0x14000258 = 0x20099414 */
594 + ldr r1, =0x000a1401
595 + str r1, [r0, #0x258]
596 +/* setmem /32 0x1400025c = 0x000a1401 */
597 + ldr r1, =0x000a1401
598 + str r1, [r0, #0x25c]
601 +/* setmem /32 0x14000000 = 0x00000501 // bit[0]: start */
602 + ldr r1, =0x00000501
604 +/* poll to make sure it is done */
606 + ldr r1, [r0, #0xa8]
611 -/* DCD for mDDR board */
613 -/* Tag=0xD2, Len=4 + 76 + 16 + 796 + 26 = 908 (03A4), Ver=0x40. */
614 -dcd_hdr: .word 0x408C03D2
616 -/* Tag = 0xCC, Len = 9*8 + 4 = 76(0x4C), Param = 4 */
617 -write_ccm_dcd_cmd: .word 0x044C00CC
619 -MXC_DCD_ITEM(01, 0x53fd4068 , 0xffffffff)
620 -MXC_DCD_ITEM(02, 0x53fd406c , 0xffffffff)
621 -MXC_DCD_ITEM(03, 0x53fd4070 , 0xffffffff)
622 -MXC_DCD_ITEM(04, 0x53fd4074 , 0xffffffff)
623 -MXC_DCD_ITEM(05, 0x53fd4078 , 0xffffffff)
624 -MXC_DCD_ITEM(06, 0x53fd407c , 0xffffffff)
625 -MXC_DCD_ITEM(07, 0x53fd4080 , 0xffffffff)
626 -MXC_DCD_ITEM(08, 0x53fd4084 , 0xffffffff)
627 -MXC_DCD_ITEM(09, 0x53FD4098 , 0x80000004)
629 -/* poll for completion of CCM_CSR2 for update: use dummy write to wait */
630 -/* Tag = 0xCF, Len = 1*12 + 4 = 16(0x10), Param = 4(Mast & Set bit are zero) */
631 -check_data_dcd_cmd: .word 0x241000CF
632 -/* loop 0x1FFFFFFF times to make sure bit 2(ddr_clk_ref_pll_bsy) is cleared */
633 -DCDGEN_CHECKDATA(1, CCM_BASE_ADDR + 0x8c, 0x04, 0x1FFFFFFF)
635 -write_dcd_cmd: .word 0x041C03CC /* Tag=0xCC, Len=99*8 + 4, Param=4 */
637 -MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x6ac, 0x02000000)
638 -MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x668, 0x00200000)
639 -MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x66c, 0x00000000)
640 -MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x670, 0x00000000)
641 -MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x68c, 0x00000000)
642 -MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x698, 0x00200000)
643 -MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x6a0, 0x00200000)
644 -MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x6a4, 0x00200000)
645 -MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x6a8, 0x00200000)
646 -MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x6b4, 0x00200000)
648 -MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x498, 0x00200000)
649 -MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x49c, 0x00200000)
650 -MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x4c8, 0x00200000)
651 -MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x4cc, 0x00200000)
652 -MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x4f0, 0x00200000)
653 -MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4f4, 0x00200000)
654 -MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4fc, 0x00200000)
655 -MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x500, 0x00200000)
656 -MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x524, 0x00200000)
657 -MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x528, 0x00200000)
659 -MXC_DCD_ITEM(21, DATABAHN_BASE_ADDR + 0x000, 0x00000100)
660 -MXC_DCD_ITEM(22, DATABAHN_BASE_ADDR + 0x008, 0x00009c40)
661 -MXC_DCD_ITEM(23, DATABAHN_BASE_ADDR + 0x014, 0x02000000)
662 -MXC_DCD_ITEM(24, DATABAHN_BASE_ADDR + 0x018, 0x01010706)
663 -MXC_DCD_ITEM(25, DATABAHN_BASE_ADDR + 0x01c, 0x080b0201)
664 -MXC_DCD_ITEM(26, DATABAHN_BASE_ADDR + 0x020, 0x02000303)
665 -MXC_DCD_ITEM(27, DATABAHN_BASE_ADDR + 0x024, 0x0136b002)
666 -MXC_DCD_ITEM(28, DATABAHN_BASE_ADDR + 0x028, 0x01000101)
667 -MXC_DCD_ITEM(29, DATABAHN_BASE_ADDR + 0x02c, 0x06030301)
668 -MXC_DCD_ITEM(30, DATABAHN_BASE_ADDR + 0x030, 0x00000000)
669 -MXC_DCD_ITEM(31, DATABAHN_BASE_ADDR + 0x034, 0x00000a02)
670 -MXC_DCD_ITEM(32, DATABAHN_BASE_ADDR + 0x038, 0x00000003)
671 -MXC_DCD_ITEM(33, DATABAHN_BASE_ADDR + 0x03c, 0x00001401)
672 -MXC_DCD_ITEM(34, DATABAHN_BASE_ADDR + 0x040, 0x0005030f)
673 -MXC_DCD_ITEM(35, DATABAHN_BASE_ADDR + 0x044, 0x00000200)
674 -MXC_DCD_ITEM(36, DATABAHN_BASE_ADDR + 0x048, 0x00180018)
675 -MXC_DCD_ITEM(37, DATABAHN_BASE_ADDR + 0x04c, 0x00010000)
676 -MXC_DCD_ITEM(38, DATABAHN_BASE_ADDR + 0x05c, 0x01000000)
677 -MXC_DCD_ITEM(39, DATABAHN_BASE_ADDR + 0x060, 0x00000001)
678 -MXC_DCD_ITEM(40, DATABAHN_BASE_ADDR + 0x064, 0x00000000)
679 -MXC_DCD_ITEM(41, DATABAHN_BASE_ADDR + 0x068, 0x00320000)
680 -MXC_DCD_ITEM(42, DATABAHN_BASE_ADDR + 0x06c, 0x00000000)
681 -MXC_DCD_ITEM(43, DATABAHN_BASE_ADDR + 0x070, 0x00000000)
682 -MXC_DCD_ITEM(44, DATABAHN_BASE_ADDR + 0x074, 0x00320000)
683 -MXC_DCD_ITEM(45, DATABAHN_BASE_ADDR + 0x080, 0x02000000)
684 -MXC_DCD_ITEM(46, DATABAHN_BASE_ADDR + 0x084, 0x00000100)
685 -MXC_DCD_ITEM(47, DATABAHN_BASE_ADDR + 0x088, 0x02400040)
686 -MXC_DCD_ITEM(48, DATABAHN_BASE_ADDR + 0x08c, 0x01000000)
687 -MXC_DCD_ITEM(49, DATABAHN_BASE_ADDR + 0x090, 0x0a000100)
688 -MXC_DCD_ITEM(50, DATABAHN_BASE_ADDR + 0x094, 0x01011f1f)
689 -MXC_DCD_ITEM(51, DATABAHN_BASE_ADDR + 0x098, 0x01010101)
690 -MXC_DCD_ITEM(52, DATABAHN_BASE_ADDR + 0x09c, 0x00030101)
691 -MXC_DCD_ITEM(53, DATABAHN_BASE_ADDR + 0x0a4, 0x00010000)
692 -MXC_DCD_ITEM(54, DATABAHN_BASE_ADDR + 0x0ac, 0x0000ffff)
693 -MXC_DCD_ITEM(55, DATABAHN_BASE_ADDR + 0x0c8, 0x02020101)
694 -MXC_DCD_ITEM(56, DATABAHN_BASE_ADDR + 0x0cc, 0x00000000)
695 -MXC_DCD_ITEM(57, DATABAHN_BASE_ADDR + 0x0d0, 0x01000202)
696 -MXC_DCD_ITEM(58, DATABAHN_BASE_ADDR + 0x0d4, 0x02030302)
697 -MXC_DCD_ITEM(59, DATABAHN_BASE_ADDR + 0x0d8, 0x00000001)
698 -MXC_DCD_ITEM(60, DATABAHN_BASE_ADDR + 0x0dc, 0x0000ffff) /* sync mode */
699 -MXC_DCD_ITEM(61, DATABAHN_BASE_ADDR + 0x0e0, 0x0000ffff)
700 -MXC_DCD_ITEM(62, DATABAHN_BASE_ADDR + 0x0e4, 0x02020000)
701 -MXC_DCD_ITEM(63, DATABAHN_BASE_ADDR + 0x0e8, 0x02020202)
702 -MXC_DCD_ITEM(64, DATABAHN_BASE_ADDR + 0x0ec, 0x00000202)
703 -MXC_DCD_ITEM(65, DATABAHN_BASE_ADDR + 0x0f0, 0x01010064)
704 -MXC_DCD_ITEM(66, DATABAHN_BASE_ADDR + 0x0f4, 0x01010101)
705 -MXC_DCD_ITEM(67, DATABAHN_BASE_ADDR + 0x0f8, 0x00010101)
706 -MXC_DCD_ITEM(68, DATABAHN_BASE_ADDR + 0x0fc, 0x00000064)
707 -MXC_DCD_ITEM(69, DATABAHN_BASE_ADDR + 0x104, 0x02000602)
708 -MXC_DCD_ITEM(70, DATABAHN_BASE_ADDR + 0x108, 0x06120000)
709 -MXC_DCD_ITEM(71, DATABAHN_BASE_ADDR + 0x10c, 0x06120612)
710 -MXC_DCD_ITEM(72, DATABAHN_BASE_ADDR + 0x110, 0x06120612)
711 -MXC_DCD_ITEM(73, DATABAHN_BASE_ADDR + 0x114, 0x01030612)
712 -MXC_DCD_ITEM(74, DATABAHN_BASE_ADDR + 0x118, 0x01010002)
714 -MXC_DCD_ITEM(75, DATABAHN_BASE_ADDR + 0x200, 0x00000000)
715 -MXC_DCD_ITEM(76, DATABAHN_BASE_ADDR + 0x204, 0x00000000)
716 -MXC_DCD_ITEM(77, DATABAHN_BASE_ADDR + 0x208, 0xf5002725)
717 -MXC_DCD_ITEM(78, DATABAHN_BASE_ADDR + 0x20c, 0x070002d0)
718 -MXC_DCD_ITEM(79, DATABAHN_BASE_ADDR + 0x210, 0xf5002725)
719 -MXC_DCD_ITEM(80, DATABAHN_BASE_ADDR + 0x214, 0x074002d0)
720 -MXC_DCD_ITEM(81, DATABAHN_BASE_ADDR + 0x218, 0xf5002725)
721 -MXC_DCD_ITEM(82, DATABAHN_BASE_ADDR + 0x21c, 0x074002d0)
722 -MXC_DCD_ITEM(83, DATABAHN_BASE_ADDR + 0x220, 0xf5002725)
723 -MXC_DCD_ITEM(84, DATABAHN_BASE_ADDR + 0x224, 0x074002d0)
724 -MXC_DCD_ITEM(85, DATABAHN_BASE_ADDR + 0x228, 0xf5002725)
725 -MXC_DCD_ITEM(86, DATABAHN_BASE_ADDR + 0x22c, 0x074002d0)
726 -MXC_DCD_ITEM(87, DATABAHN_BASE_ADDR + 0x230, 0x00000000)
727 -MXC_DCD_ITEM(88, DATABAHN_BASE_ADDR + 0x234, 0x00800006)
728 -MXC_DCD_ITEM(89, DATABAHN_BASE_ADDR + 0x238, 0x200e1014)
729 -MXC_DCD_ITEM(90, DATABAHN_BASE_ADDR + 0x23c, 0x000d9f01)
730 -MXC_DCD_ITEM(91, DATABAHN_BASE_ADDR + 0x240, 0x200e1014)
731 -MXC_DCD_ITEM(92, DATABAHN_BASE_ADDR + 0x244, 0x000d9f01)
732 -MXC_DCD_ITEM(93, DATABAHN_BASE_ADDR + 0x248, 0x200e1014)
733 -MXC_DCD_ITEM(94, DATABAHN_BASE_ADDR + 0x24c, 0x000d9f01)
734 -MXC_DCD_ITEM(95, DATABAHN_BASE_ADDR + 0x250, 0x200e1014)
735 -MXC_DCD_ITEM(96, DATABAHN_BASE_ADDR + 0x254, 0x000d9f01)
736 -MXC_DCD_ITEM(97, DATABAHN_BASE_ADDR + 0x258, 0x200e1014)
737 -MXC_DCD_ITEM(98, DATABAHN_BASE_ADDR + 0x25c, 0x000d9f01)
738 -MXC_DCD_ITEM(99, DATABAHN_BASE_ADDR + 0x000, 0x00000101)
741 -/* poll for completion of HW_DRAM_CTL42 for DDR inti completion */
742 -/* Tag = 0xCF, Len = 1*12 + 4 = 16(0x10), Param = 4 (Mast & Set bit are zero) */
743 -check_ddr_init_dcd_cmd: .word 0x341000CF
744 -/* loop 0x1FFFFFFF times to make sure bit 4 (int_status) is set */
745 -DCDGEN_CHECKDATA(2, DATABAHN_BASE_ADDR + 0xa8, 0x10, 0x1FFFFFFF)
746 +/*==================================================================
748 + *=================================================================*/
750 +/* DDR clock setting -- Set DDR to be div 4 to get 200MHz */
751 +/* setmem /32 0x53FD4098 = 0x80000004 */
752 + ldr r1, =0x80000004
753 + str r1, [r0, #0x98]
755 +/* poll to make sure DDR dividers take effect */
757 + ldr r1, [r0, #0x8c]
761 +/*==================================================================
763 + *=================================================================*/
764 + ldr r0, =0x53fa8600
765 + mov r1, #0x02000000
766 + mov r3, #0x00200000
768 + str r1, [r0, #0xac]
769 + str r2, [r0, #0x6c]
770 + str r2, [r0, #0x8c]
771 + str r3, [r0, #0xa4]
772 + str r3, [r0, #0x68]
773 + str r3, [r0, #0x98]
774 + str r3, [r0, #0xa0]
775 + str r3, [r0, #0xa8]
776 + str r3, [r0, #0xb4]
778 + ldr r0, =0x53fa8400
779 + str r3, [r0, #0x98]
780 + str r3, [r0, #0x9c]
781 + str r3, [r0, #0xf0]
782 + str r3, [r0, #0x100]
783 + str r3, [r0, #0xc8]
784 + str r3, [r0, #0x128]
785 + str r3, [r0, #0xf4]
786 + str r3, [r0, #0xfc]
787 + str r3, [r0, #0xcc]
788 + str r3, [r0, #0x124]
789 + str r2, [r0, #0x270]
791 +/*==============================================================
793 + *=============================================================*/
794 + ldr r0, =DATABAHN_BASE_ADDR
795 +/* setmem /32 0x14000000 = 0x00000100 */
796 + ldr r1, =0x00000100
798 +/* setmem /32 0x14000008 = 0x00009c40 */
799 + ldr r1, =0x00009c40
801 +/* setmem /32 0x14000014 = 0x02000000 */
802 + ldr r1, =0x02000000
803 + str r1, [r0, #0x14]
804 +/* setmem /32 0x14000018 = 0x01010706 */
805 + ldr r1, =0x01010706
806 + str r1, [r0, #0x018]
807 +/* setmem /32 0x1400001c = 0x080b0201 */
808 + ldr r1, =0x080b0201
809 + str r1, [r0, #0x01c]
810 +/* setmem /32 0x14000020 = 0x02000303 */
811 + ldr r1, =0x02000303
812 + str r1, [r0, #0x020]
813 +/* setmem /32 0x14000024 = 0x0136b002 */
814 + ldr r1, =0x0136b002
815 + str r1, [r0, #0x024]
816 +/* setmem /32 0x14000028 = 0x01000101 */
817 + ldr r1, =0x01000101
818 + str r1, [r0, #0x028]
819 +/* setmem /32 0x1400002c = 0x06030301 */
820 + ldr r1, =0x06030301
821 + str r1, [r0, #0x02c]
822 +/* setmem /32 0x14000030 = 0x00000000 */
823 + ldr r1, =0x00000000
824 + str r1, [r0, #0x030]
825 +/* setmem /32 0x14000034 = 0x00000a02 */
826 + ldr r1, =0x00000a02
827 + str r1, [r0, #0x034]
828 +/* setmem /32 0x14000038 = 0x00000003 */
829 + ldr r1, =0x00000003
830 + str r1, [r0, #0x038]
831 +/* setmem /32 0x1400003c = 0x00001401 */
832 + ldr r1, =0x00001401
833 + str r1, [r0, #0x03c]
834 +/* setmem /32 0x14000040 = 0x0005030f */
835 + ldr r1, =0x0005030f
836 + str r1, [r0, #0x040]
837 +/* setmem /32 0x14000044 = 0x00000200 */
838 + ldr r1, =0x00000200
839 + str r1, [r0, #0x044]
840 +/* setmem /32 0x14000048 = 0x00180018 */
841 + ldr r1, =0x00180018
842 + str r1, [r0, #0x048]
843 +/* setmem /32 0x1400004c = 0x00010000 */
844 + ldr r1, =0x00010000
845 + str r1, [r0, #0x04c]
846 +/* setmem /32 0x1400005c = 0x01000000 */
847 + ldr r1, =0x01000000
848 + str r1, [r0, #0x05c]
849 +/* setmem /32 0x14000060 = 0x00000001 */
850 + ldr r1, =0x00000001
851 + str r1, [r0, #0x060]
852 +/* setmem /32 0x14000064 = 0x00000000 */
853 + ldr r1, =0x00000000
854 + str r1, [r0, #0x064]
855 +/* setmem /32 0x14000068 = 0x00320000 */
856 + ldr r1, =0x00320000
857 + str r1, [r0, #0x068]
858 +/* setmem /32 0x1400006c = 0x00000000 */
859 + ldr r1, =0x00000000
860 + str r1, [r0, #0x06c]
861 +/* setmem /32 0x14000070 = 0x00000000 */
862 + ldr r1, =0x00000000
863 + str r1, [r0, #0x070]
864 +/* setmem /32 0x14000074 = 0x00320000 */
865 + ldr r1, =0x00320000
866 + str r1, [r0, #0x074]
867 +/* setmem /32 0x14000080 = 0x02000000 */
868 + ldr r1, =0x02000000
869 + str r1, [r0, #0x080]
870 +/* setmem /32 0x14000084 = 0x00000100 */
871 + ldr r1, =0x00000100
872 + str r1, [r0, #0x084]
873 +/* setmem /32 0x14000088 = 0x02400040 */
874 + ldr r1, =0x02400040
875 + str r1, [r0, #0x088]
876 +/* setmem /32 0x1400008c = 0x01000000 */
877 + ldr r1, =0x01000000
878 + str r1, [r0, #0x08c]
879 +/* setmem /32 0x14000090 = 0x0a000100 */
880 + ldr r1, =0x0a000100
881 + str r1, [r0, #0x090]
882 +/* setmem /32 0x14000094 = 0x01011f1f */
883 + ldr r1, =0x01011f1f
884 + str r1, [r0, #0x094]
885 +/* setmem /32 0x14000098 = 0x01010101 */
886 + ldr r1, =0x01010101
887 + str r1, [r0, #0x098]
888 +/* setmem /32 0x1400009c = 0x00030101 */
889 + ldr r1, =0x00030101
890 + str r1, [r0, #0x09c]
891 +/* setmem /32 0x140000a4 = 0x00010000 */
892 + ldr r1, =0x00010000
893 + str r1, [r0, #0x0a4]
894 +/* setmem /32 0x140000ac = 0x0000ffff */
895 + ldr r1, =0x0000ffff
896 + str r1, [r0, #0x0ac]
897 +/* setmem /32 0x140000c8 = 0x02020101 */
898 + ldr r1, =0x02020101
899 + str r1, [r0, #0x0c8]
900 +/* setmem /32 0x140000cc = 0x00000000 */
901 + ldr r1, =0x00000000
902 + str r1, [r0, #0x0cc]
903 +/* setmem /32 0x140000d0 = 0x01000202 */
904 + ldr r1, =0x01000202
905 + str r1, [r0, #0x0d0]
906 +/* setmem /32 0x140000d4 = 0x02030302 */
907 + ldr r1, =0x02030302
908 + str r1, [r0, #0x0d4]
909 +/* setmem /32 0x140000d8 = 0x00000001 */
910 + ldr r1, =0x00000001
911 + str r1, [r0, #0x0d8]
912 +/* setmem /32 0x140000dc = 0x0000ffff */
913 + ldr r1, =0x0000ffff
914 + str r1, [r0, #0x0dc]
915 +/* setmem /32 0x140000e0 = 0x0000ffff */
916 + ldr r1, =0x0000ffff
917 + str r1, [r0, #0x0e0]
918 +/* setmem /32 0x140000e4 = 0x02020000 */
919 + ldr r1, =0x02020000
920 + str r1, [r0, #0x0e4]
921 +/* setmem /32 0x140000e8 = 0x02020202 */
922 + ldr r1, =0x02020202
923 + str r1, [r0, #0x0e8]
924 +/* setmem /32 0x140000ec = 0x00000202 */
925 + ldr r1, =0x00000202
926 + str r1, [r0, #0x0ec]
927 +/* setmem /32 0x140000f0 = 0x01010064 */
928 + ldr r1, =0x01010064
929 + str r1, [r0, #0x0f0]
930 +/* setmem /32 0x140000f4 = 0x01010101 */
931 + ldr r1, =0x01010101
932 + str r1, [r0, #0x0f4]
933 +/* setmem /32 0x140000f8 = 0x00010101 */
934 + ldr r1, =0x00010101
935 + str r1, [r0, #0x0f8]
936 +/* setmem /32 0x140000fc = 0x00000064 */
937 + ldr r1, =0x00000064
938 + str r1, [r0, #0x0fc]
939 +/* setmem /32 0x14000104 = 0x02000602 */
940 + ldr r1, =0x02000602
941 + str r1, [r0, #0x0104]
942 +/* setmem /32 0x14000108 = 0x06120000 */
943 + ldr r1, =0x06120000
944 + str r1, [r0, #0x0108]
945 +/* setmem /32 0x1400010c = 0x06120612 */
946 + ldr r1, =0x06120612
947 + str r1, [r0, #0x010c]
948 +/* setmem /32 0x14000110 = 0x06120612 */
949 + ldr r1, =0x06120612
950 + str r1, [r0, #0x0110]
951 +/* setmem /32 0x14000114 = 0x01030612 */
952 + ldr r1, =0x01030612
953 + str r1, [r0, #0x0114]
954 +/* setmem /32 0x14000118 = 0x01010002 */
955 + ldr r1, =0x01010002
956 + str r1, [r0, #0x0118]
958 +/*=============================================================
960 + *===========================================================*/
962 +/* setmem /32 0x14000200 = 0x00000000 */
963 + ldr r1, =0x00000000
964 + str r1, [r0, #0x200]
965 +/* setmem /32 0x14000204 = 0x00000000 */
966 + ldr r1, =0x00000000
967 + str r1, [r0, #0x0204]
969 +/* setmem /32 0x14000208 = 0xf5002725 */
970 + ldr r1, =0xf5002725
971 + str r1, [r0, #0x0208]
972 +/* setmem /32 0x14000210 = 0xf5002725 */
973 + ldr r1, =0xf5002725
974 + str r1, [r0, #0x210]
975 +/* setmem /32 0x14000218 = 0xf5002725 */
976 + ldr r1, =0xf5002725
977 + str r1, [r0, #0x218]
978 +/* setmem /32 0x14000220 = 0xf5002725 */
979 + ldr r1, =0xf5002725
980 + str r1, [r0, #0x0220]
981 +/* setmem /32 0x14000228 = 0xf5002725 */
982 + ldr r1, =0xf5002725
983 + str r1, [r0, #0x0228]
985 +/* setmem /32 0x1400020c = 0x070002d0 */
986 + ldr r1, =0x070002d0
987 + str r1, [r0, #0x020c]
989 +/* setmem /32 0x14000214 = 0x074002d0 */
990 + ldr r1, =0x074002d0
991 + str r1, [r0, #0x0214]
993 +/* setmem /32 0x1400021c = 0x074002d0 */
994 + ldr r1, =0x074002d0
995 + str r1, [r0, #0x021c]
997 +/* setmem /32 0x14000224 = 0x074002d0 */
998 + ldr r1, =0x074002d0
999 + str r1, [r0, #0x0224]
1001 +/* setmem /32 0x1400022c = 0x074002d0 */
1002 + ldr r1, =0x074002d0
1003 + str r1, [r0, #0x022c]
1004 +/* setmem /32 0x14000230 = 0x00000000 */
1005 + ldr r1, =0x00000000
1006 + str r1, [r0, #0x0230]
1007 +/* setmem /32 0x14000234 = 0x00800006 */
1008 + ldr r1, =0x00800006
1009 + str r1, [r0, #0x0234]
1011 +/* setmem /32 0x14000238 = 0x200e1014 */
1012 + ldr r1, =0x200e1014
1013 + str r1, [r0, #0x0238]
1014 +/* setmem /32 0x14000240 = 0x200e1014 */
1015 + ldr r1, =0x200e1014
1016 + str r1, [r0, #0x0240]
1017 +/* setmem /32 0x14000248 = 0x200e1014 */
1018 + ldr r1, =0x200e1014
1019 + str r1, [r0, #0x0248]
1020 +/* setmem /32 0x14000250 = 0x200e1014 */
1021 + ldr r1, =0x200e1014
1022 + str r1, [r0, #0x0250]
1023 +/* setmem /32 0x14000258 = 0x200e1014 */
1024 + ldr r1, =0x200e1014
1025 + str r1, [r0, #0x0258]
1027 +/* setmem /32 0x1400023c = 0x000d9f01 */
1028 + ldr r1, =0x000d9f01
1029 + str r1, [r0, #0x023c]
1030 +/* setmem /32 0x14000244 = 0x000d9f01 */
1031 + ldr r1, =0x000d9f01
1032 + str r1, [r0, #0x0244]
1033 +/* setmem /32 0x1400024c = 0x000d9f01 */
1034 + ldr r1, =0x000d9f01
1035 + str r1, [r0, #0x024c]
1036 +/* setmem /32 0x14000254 = 0x000d9f01 */
1037 + ldr r1, =0x000d9f01
1038 + str r1, [r0, #0x0254]
1039 +/* setmem /32 0x1400025c = 0x000d9f01 */
1040 + ldr r1, =0x000d9f01
1041 + str r1, [r0, #0x025c]
1044 +/* setmem /32 0x14000000 = 0x00000101 // bit[0]: start */
1045 + ldr r1, =0x00000101
1046 + str r1, [r0, #0x0]
1047 +/* poll to make sure it is done */
1049 + ldr r1, [r0, #0xa8]
1050 + ands r1, r1, #0x10
1056 + * The following is to fill in those arguments for this ROM function
1057 + * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
1059 + * This function is used to copy data from the storage media into DDR.
1061 + * start - Initial (possibly partial) image load address on entry.
1062 + * Final image load address on exit.
1063 + * bytes - Initial (possibly partial) image size on entry.
1064 + * Final image size on exit.
1065 + * boot_data - Initial @ref ivt Boot Data load address.
1067 + adr r0, DDR_DEST_ADDR
1071 +before_calling_rom___pu_irom_hwcnfg_setup:
1074 + blx r4 // This address might change in future ROM versions
1075 +after_calling_rom___pu_irom_hwcnfg_setup:
1078 +/* To return to ROM from plugin, we need to fill in these argument.
1079 + * Here is what need to do:
1080 + * Need to construct the paramters for this function before return to ROM:
1081 + * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
1084 + ldr r3, DDR_DEST_ADDR
1088 + mov r3, #0x400 /* Point to the second IVT table at offset 0x42C */
1092 + bx lr /* return back to ROM code */
1094 +DDR_DEST_ADDR: .word 0x77800000
1095 +COPY_SIZE: .word 0x40000
1096 +BOOT_DATA: .word 0x77800000
1097 + .word 0x40000 /*data be copied by pu_irom_hwcnfg_setup()*/
projects / karo-tx-uboot.git / blob