imx: mx6: ccm: Change the clock settings for i.MX6QP

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / clock.c

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index dfd5e08a0276e3dbf7f225926dd37cc889889d02..836fe8f52a46cb95c59b88a893cb86f4ac96149f 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -172,7 +172,7 @@ void enable_usboh3_clk(unsigned char enable)
 
 }
 
-#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
+#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
 void enable_enet_clk(unsigned char enable)
 {
        u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
@@ -196,25 +196,6 @@ void enable_uart_clk(unsigned char enable)
 }
 #endif
 
-#ifdef CONFIG_SPI
-/* spi_num can be from 0 - 4 */
-int enable_cspi_clock(unsigned char enable, unsigned spi_num)
-{
-       u32 mask;
-
-       if (spi_num > 4)
-               return -EINVAL;
-
-       mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
-       if (enable)
-               setbits_le32(&imx_ccm->CCGR1, mask);
-       else
-               clrbits_le32(&imx_ccm->CCGR1, mask);
-
-       return 0;
-}
-#endif
-
 #ifdef CONFIG_MMC
 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 {
@@ -234,23 +215,40 @@ int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 #endif
 
 #ifdef CONFIG_SYS_I2C_MXC
-/* i2c_num can be from 0 - 2 */
+/* i2c_num can be from 0 - 3 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
        u32 reg;
        u32 mask;
+       u32 *addr;
 
-       if (i2c_num > 2)
+       if (i2c_num > 3)
                return -EINVAL;
-
-       mask = MXC_CCM_CCGR_CG_MASK
-               << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
-       reg = __raw_readl(&imx_ccm->CCGR2);
-       if (enable)
-               reg |= mask;
-       else
-               reg &= ~mask;
-       __raw_writel(reg, &imx_ccm->CCGR2);
+       if (i2c_num < 3) {
+               mask = MXC_CCM_CCGR_CG_MASK
+                       << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
+                       + (i2c_num << 1));
+               reg = __raw_readl(&imx_ccm->CCGR2);
+               if (enable)
+                       reg |= mask;
+               else
+                       reg &= ~mask;
+               __raw_writel(reg, &imx_ccm->CCGR2);
+       } else {
+               if (is_cpu_type(MXC_CPU_MX6SX)) {
+                       mask = MXC_CCM_CCGR6_I2C4_MASK;
+                       addr = &imx_ccm->CCGR6;
+               } else {
+                       mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
+                       addr = &imx_ccm->CCGR1;
+               }
+               reg = __raw_readl(addr);
+               if (enable)
+                       reg |= mask;
+               else
+                       reg &= ~mask;
+               __raw_writel(reg, addr);
+       }
        return 0;
 }
 #endif
@@ -437,10 +435,12 @@ static u32 get_ipg_per_clk(void)
        u32 reg, perclk_podf;
 
        reg = __raw_readl(&imx_ccm->cscmr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
-       if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
-               return MXC_HCLK; /* OSC 24Mhz */
-#endif
+       if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
+           is_mx6dqp()) {
+               if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
+                       return MXC_HCLK; /* OSC 24Mhz */
+       }
+
        perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 
        return get_ipg_clk() / (perclk_podf + 1);
@@ -451,10 +451,13 @@ static u32 get_uart_clk(void)
        u32 reg, uart_podf;
        u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
        reg = __raw_readl(&imx_ccm->cscdr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
-       if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
-               freq = MXC_HCLK;
-#endif
+
+       if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
+           is_mx6dqp()) {
+               if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+                       freq = MXC_HCLK;
+       }
+
        reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
        uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 
@@ -466,8 +469,13 @@ static u32 get_cspi_clk(void)
        u32 reg, cspi_podf;
 
        reg = __raw_readl(&imx_ccm->cscdr2);
-       reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
-       cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+       cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
+                    MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+       if (is_mx6dqp()) {
+               if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
+                       return MXC_HCLK / (cspi_podf + 1);
+       }
 
        return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 }
@@ -617,7 +625,7 @@ static int set_nfc_clk(u32 ref, u32 freq_khz)
        return 0;
 }
 
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
 static u32 get_mmdc_ch0_clk(void)
 {
        u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
@@ -657,7 +665,7 @@ static u32 get_mmdc_ch0_clk(void)
 }
 #endif
 
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
 /* qspi_num can be from 0 - 1 */
 void enable_qspi_clk(int qspi_num)
 {
@@ -740,7 +748,7 @@ int enable_fec_anatop_clock(enum enet_freq freq)
        reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
        writel(reg, &anatop->pll_enet);
 
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX
        /*
         * Set enet ahb clock to 200MHz
         * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
@@ -841,7 +849,7 @@ static int enable_enet_pll(uint32_t en)
        return 0;
 }
 
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 static void ungate_sata_clock(void)
 {
        struct mxc_ccm_reg *const imx_ccm =
@@ -861,7 +869,7 @@ static void ungate_pcie_clock(void)
        setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 }
 
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 int enable_sata_clock(void)
 {
        ungate_sata_clock();
@@ -916,7 +924,7 @@ int enable_pcie_clock(void)
        clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 
        /* Party time! Ungate the clock to the PCIe. */
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
        ungate_sata_clock();
 #endif
        ungate_pcie_clock();
@@ -1379,7 +1387,7 @@ int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
        return CMD_RET_FAILURE;
 }
 
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX
 void enable_ipu_clock(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;