imx: mx6: ccm: Change the clock settings for i.MX6QP

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index fc5cce9db8ff501cfa0468bd52f5667045c5fb76..546a275c01683f6142e291f30ea5e85a0efc06ec 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -87,12 +87,12 @@ u32 get_cpu_rev(void)
        struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
        u32 reg = readl(&anatop->digprog_sololite);
        u32 type = ((reg >> 16) & 0xff);
-       u32 major;
+       u32 major, cfg = 0;
 
        if (type != MXC_CPU_MX6SL) {
                reg = readl(&anatop->digprog);
                struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
-               u32 cfg = readl(&scu->config) & 3;
+               cfg = readl(&scu->config) & 3;
                type = ((reg >> 16) & 0xff);
                if (type == MXC_CPU_MX6DL) {
                        if (!cfg)
@@ -106,6 +106,13 @@ u32 get_cpu_rev(void)
 
        }
        major = ((reg >> 8) & 0xff);
+       if ((major >= 1) &&
+           ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
+               major--;
+               type = MXC_CPU_MX6QP;
+               if (cfg == 1)
+                       type = MXC_CPU_MX6DP;
+       }
        reg &= 0xff;            /* mx6 silicon revision */
        return (type << 12) | (reg + (0x10 * (major + 1)));
 }
@@ -531,9 +538,12 @@ static void set_ahb_rate(u32 val)
 static void clear_mmdc_ch_mask(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+       u32 reg;
+       reg = readl(&mxc_ccm->ccdr);
 
        /* Clear MMDC channel mask */
-       writel(0, &mxc_ccm->ccdr);
+       reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+       writel(reg, &mxc_ccm->ccdr);
 }
 
 static void init_bandgap(void)