Tegra: Configure L2 cache control reg properly.

[karo-tx-uboot.git] / arch / arm / cpu / tegra-common / Makefile

diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile
index 8e95c7ee1d367fd03b3dbb650941594fdb08f421..4e0301c66ae792e3923601a85e3cce362fc5026f 100644 (file)
--- a/arch/arm/cpu/tegra-common/Makefile
+++ b/arch/arm/cpu/tegra-common/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
 LIB    = $(obj)libcputegra-common.o
 
 SOBJS += lowlevel_init.o
-COBJS-y        += ap.o board.o sys_info.o timer.o clock.o
+COBJS-y        += ap.o board.o sys_info.o timer.o clock.o cache.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS-y))