+/* NAND Clock Control Register bits */
+#define CLK_NAND_SLC (1 << 0)
+#define CLK_NAND_MLC (1 << 1)
+#define CLK_NAND_SLC_SELECT (1 << 2)
+#define CLK_NAND_MLC_INT (1 << 5)
+
+/* SSP Clock Control Register bits */
+#define CLK_SSP0_ENABLE_CLOCK (1 << 0)
+
+/* SDRAMCLK register bits */
+#define CLK_SDRAM_DDR_SEL (1 << 1)
+