ddr: altera: sequencer: Wrap IO_* macros

[karo-tx-uboot.git] / arch / arm / mach-socfpga / include / mach / sdram.h

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index eb409348c37e4257d31855d93351fed4a2c66b32..9d0e0833e551f8a42783830f08f0c7d3ea00e30b 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -17,6 +17,7 @@ const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
 void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
 void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
 const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
+const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
 
 #define SDR_CTRLGRP_ADDRESS    (SOCFPGA_SDR_ADDRESS | 0x5000)
 
@@ -180,6 +181,24 @@ struct socfpga_sdram_rw_mgr_config {
        u8      mem_virtual_groups_per_write_dqs;
 };
 
+struct socfpga_sdram_io_config {
+       u16     delay_per_opa_tap;
+       u8      delay_per_dchain_tap;
+       u8      delay_per_dqs_en_dchain_tap;
+       u8      dll_chain_length;
+       u8      dqdqs_out_phase_max;
+       u8      dqs_en_delay_max;
+       u8      dqs_en_delay_offset;
+       u8      dqs_en_phase_max;
+       u8      dqs_in_delay_max;
+       u8      dqs_in_reserve;
+       u8      dqs_out_reserve;
+       u8      io_in_delay_max;
+       u8      io_out1_delay_max;
+       u8      io_out2_delay_max;
+       u8      shift_dqs_en_when_shift_dqs;
+};
+
 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22