karo: tx53: configure SDRAM size via boards.cfg

[karo-tx-uboot.git] / board / karo / tx53 / lowlevel_init.S

diff --git a/board/karo/tx53/lowlevel_init.S b/board/karo/tx53/lowlevel_init.S
index 555b5d57308399d78cb82577251f1ec8b8dd57b0..15f2245c41b77ea65e894e08f1829a4932fcae91 100644 (file)
--- a/board/karo/tx53/lowlevel_init.S
+++ b/board/karo/tx53/lowlevel_init.S
@@ -8,13 +8,7 @@
 #define LED_MUX_MODE           0x11
 
 #define SDRAM_CLK              CONFIG_SYS_SDRAM_CLK
-
-#ifdef PHYS_SDRAM_2_SIZE
-#define SDRAM_SIZE             (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
-#else
-#define SDRAM_SIZE             PHYS_SDRAM_1_SIZE
-#endif
-
+#define SDRAM_SIZE             (CONFIG_SYS_SDRAM_SIZE / SZ_1M)
 
 #define REG_CCGR0              0x68
 #define REG_CCGR1              0x6c
@@ -150,11 +144,7 @@ dcd_end:
 #define ESDOR_CLK_PERIOD_ns            (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */
 
 /* DDR3 SDRAM */
-#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
-#define BANK_ADDR_BITS                 2
-#else
-#define BANK_ADDR_BITS                 1
-#endif
+#define BANK_ADDR_BITS                 CONFIG_NR_DRAM_BANKS
 #define SDRAM_BURST_LENGTH             8
 #define RALAT                          5
 #define WALAT                          0
@@ -346,8 +336,7 @@ fcb_start:
        .org    0x68
        .word   0x0     /* primary image starting page number */
        .word   0x0     /* secondary image starting page number */
-       .word   0x6b
-       .word   0x6b
+       .org    0x78
        .word   0x0     /* DBBT start page (0 == NO DBBT) */
        .word   0       /* Bad block marker offset in main area (unused) */
        .org    0xac
@@ -373,7 +362,7 @@ app_code_csf:
 boot_data:
        .long   fcb_start
 image_len:
-       .long   CONFIG_U_BOOT_IMG_SIZE
+       .long   __uboot_img_end - fcb_start
 plugin:
        .word   0
 ivt_end:
@@ -410,8 +399,8 @@ dcd_hdr:
        MXC_DCD_ITEM(0x53fd4020, 0xb6b12f0a)    /* CSCMR2 */
        MXC_DCD_ITEM(0x53fd4024, 0x00080b18)    /* CSCDR1 */
 
-#define DDR_SEL_VAL    2
-#define DSE_VAL                5
+#define DDR_SEL_VAL    0
+#define DSE_VAL                6
 #define ODT_VAL                2
 
 #define DDR_SEL_SHIFT  25