karo: tx6: configure all relevant PMIC registers

[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c

diff --git a/board/karo/tx6/tx6qdl.c b/board/karo/tx6/tx6qdl.c
index 8300076658ff7b10bf756ca82a5d8fe818b21de6..87ff82bb892b750f3a3cd9c14797fa064f220598 100644 (file)
--- a/board/karo/tx6/tx6qdl.c
+++ b/board/karo/tx6/tx6qdl.c
@@ -71,7 +71,7 @@ char __csf_data[0] __attribute__((section(".__csf_data")));
 #define TX6_FEC_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
                                             PAD_CTL_SPEED_MED |        \
                                             PAD_CTL_DSE_40ohm |        \
-                                            PAD_CTL_SRE_FAST)
+                                            PAD_CTL_SRE_SLOW)
 #define TX6_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
                                             PAD_CTL_SPEED_MED |        \
                                             PAD_CTL_DSE_34ohm |        \
@@ -121,7 +121,10 @@ static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
        /* FEC functions */
        MX6_PAD_ENET_MDC__ENET_MDC | TX6_FEC_PAD_CTRL,
        MX6_PAD_ENET_MDIO__ENET_MDIO | TX6_FEC_PAD_CTRL,
-       MX6_PAD_GPIO_16__ENET_REF_CLK | TX6_FEC_PAD_CTRL,
+       MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
+                                                    PAD_CTL_SPEED_LOW |
+                                                    PAD_CTL_DSE_80ohm |
+                                                    PAD_CTL_SRE_SLOW),
        MX6_PAD_ENET_RX_ER__ENET_RX_ER | TX6_FEC_PAD_CTRL,
        MX6_PAD_ENET_CRS_DV__ENET_RX_EN | TX6_FEC_PAD_CTRL,
        MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | TX6_FEC_PAD_CTRL,
@@ -457,10 +460,10 @@ static struct pmic_regs rn5t567_regs[] = {
        { RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, },
        { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
        { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
-       { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
-       { RN5T567_DC2CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
-       { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
-       { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
+       { RN5T567_DC1CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
+       { RN5T567_DC2CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
+       { RN5T567_DC3CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
+       { RN5T567_DC4CTL, DCnCTL_EN | DCnMODE_SLP(MODE_PSM), },
        { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
        { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
        { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
@@ -470,7 +473,7 @@ static struct pmic_regs rn5t567_regs[] = {
        { RN5T567_LDODIS, 0x1c, ~0x1f, },
        { RN5T567_INTPOL, 0, },
        { RN5T567_INTEN, 0x3, },
-       { RN5T567_IREN, 0xf, },
+       { RN5T567_DCIREN, 0xf, },
        { RN5T567_EN_GPIR, 0, },
 };
 #endif
@@ -1293,10 +1296,13 @@ void lcd_ctrl_init(void *lcdbase)
                panel_info.vl_bpix = LCD_COLOR32;
        }
 
-       p->pixclock = KHZ2PICOS(refresh *
-               (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
-               (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
-                               1000);
+       if (refresh_set || p->pixclock == 0)
+               p->pixclock = KHZ2PICOS(refresh *
+                                       (p->xres + p->left_margin +
+                                        p->right_margin + p->hsync_len) *
+                                       (p->yres + p->upper_margin +
+                                        p->lower_margin + p->vsync_len) /
+                                       1000);
        debug("Pixel clock set to %lu.%03lu MHz\n",
              PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);