writel(0x00000000, &fec->eth->gaddr2);
/* Do not access reserved register for i.MX6UL */
writel(0x00000000, &fec->eth->gaddr2);
/* Do not access reserved register for i.MX6UL */
/* FIFO receive start register */
writel(0x520, &fec->eth->r_fstart);
#endif
/* FIFO receive start register */
writel(0x520, &fec->eth->r_fstart);
#endif