* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
* Copyright (C) 2010 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#include <asm/arch/mx6x_pins.h>
-#include <asm/arch/iomux-v3.h>
+#include <asm/imx-common/iomux-v3.h>
#include "ehci.h"
-#include "ehci-core.h"
#define USB_OTGREGS_OFFSET 0x000
#define USB_H1REGS_OFFSET 0x200
#define USBPHY_CTRL_CLKGATE 0x40000000
#define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
#define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
+#define USBPHY_CTRL_OTG_ID 0x08000000
#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
-
+#define USBNC_OFFSET 0x200
+#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
+#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
+#define UCTRL_PM (1 << 9) /* OTG Power Mask */
#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
/* USBCMD */
-#define UH1_USBCMD_OFFSET 0x140
#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
#define UCMD_RESET (1 << 1) /* controller reset */
-static void usbh1_internal_phy_clock_gate(int on)
+#if defined(CONFIG_SOC_MX6)
+static const unsigned phy_bases[] = {
+ USB_PHY0_BASE_ADDR,
+ USB_PHY1_BASE_ADDR,
+};
+
+static void usb_internal_phy_clock_gate(int index, int on)
{
- void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
+ void __iomem *phy_reg;
+
+ if (index >= ARRAY_SIZE(phy_bases))
+ return;
+ phy_reg = (void __iomem *)phy_bases[index];
phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
- __raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
+ writel(USBPHY_CTRL_CLKGATE, phy_reg);
}
-static void usbh1_power_config(void)
+static void usb_power_config(int index)
{
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+ void __iomem *chrg_detect;
+ void __iomem *pll_480_ctrl_clr;
+ void __iomem *pll_480_ctrl_set;
+
+ switch (index) {
+ case 0:
+ chrg_detect = &anatop->usb1_chrg_detect;
+ pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
+ pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
+ break;
+ case 1:
+ chrg_detect = &anatop->usb2_chrg_detect;
+ pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
+ pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
+ break;
+ default:
+ return;
+ }
/*
- * Some phy and power's special controls for host1
+ * Some phy and power's special controls
* 1. The external charger detector needs to be disabled
* or the signal at DP will be poor
- * 2. The PLL's power and output to usb for host 1
+ * 2. The PLL's power and output to usb
* is totally controlled by IC, so the Software only needs
* to enable them at initializtion.
*/
- __raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
+ writel(ANADIG_USB2_CHRG_DETECT_EN_B |
ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
- &anatop->usb2_chrg_detect);
+ chrg_detect);
- __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
- &anatop->usb2_pll_480_ctrl_clr);
+ writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
+ pll_480_ctrl_clr);
- __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
+ writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
ANADIG_USB2_PLL_480_CTRL_POWER |
ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
- &anatop->usb2_pll_480_ctrl_set);
+ pll_480_ctrl_set);
}
-static int usbh1_phy_enable(void)
+static int wait_for_bit(u32 *reg, const u32 mask, bool set)
{
- void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
- void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
- void __iomem *usb_cmd = (void __iomem *)(USBOH3_USB_BASE_ADDR +
- USB_H1REGS_OFFSET +
- UH1_USBCMD_OFFSET);
u32 val;
+ const unsigned int timeout = 10000;
+ unsigned long start = get_timer(0);
+
+ while(1) {
+ val = readl(reg);
+ if (!set)
+ val = ~val;
+
+ if ((val & mask) == mask)
+ return 0;
+
+ if (get_timer(start) > timeout)
+ break;
+
+ udelay(1);
+ }
+
+ debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
+ __func__, reg, mask, set);
+
+ return -ETIMEDOUT;
+}
+
+/* Return 0 : host node, <>0 : device mode */
+static int usb_phy_enable(int index, struct usb_ehci *ehci)
+{
+ void __iomem *phy_reg;
+ void __iomem *phy_ctrl;
+ void __iomem *usb_cmd;
+ int ret;
+
+ if (index >= ARRAY_SIZE(phy_bases))
+ return 0;
+
+ phy_reg = (void __iomem *)phy_bases[index];
+ phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+ usb_cmd = (void __iomem *)&ehci->usbcmd;
/* Stop then Reset */
- val = __raw_readl(usb_cmd);
- val &= ~UCMD_RUN_STOP;
- __raw_writel(val, usb_cmd);
- while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
- ;
-
- val = __raw_readl(usb_cmd);
- val |= UCMD_RESET;
- __raw_writel(val, usb_cmd);
- while (__raw_readl(usb_cmd) & UCMD_RESET)
- ;
+ clrbits_le32(usb_cmd, UCMD_RUN_STOP);
+ ret = wait_for_bit(usb_cmd, UCMD_RUN_STOP, 0);
+ if (ret)
+ return ret;
+
+ setbits_le32(usb_cmd, UCMD_RESET);
+ ret = wait_for_bit(usb_cmd, UCMD_RESET, 0);
+ if (ret)
+ return ret;
/* Reset USBPHY module */
- val = __raw_readl(phy_ctrl);
- val |= USBPHY_CTRL_SFTRST;
- __raw_writel(val, phy_ctrl);
+ setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
udelay(10);
/* Remove CLKGATE and SFTRST */
- val = __raw_readl(phy_ctrl);
- val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
- __raw_writel(val, phy_ctrl);
+ clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
udelay(10);
/* Power up the PHY */
- __raw_writel(0, phy_reg + USBPHY_PWD);
+ writel(0, phy_reg + USBPHY_PWD);
/* enable FS/LS device */
- val = __raw_readl(phy_reg + USBPHY_CTRL);
- val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
- __raw_writel(val, phy_reg + USBPHY_CTRL);
+ setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
+ USBPHY_CTRL_ENUTMILEVEL3);
return 0;
}
-static void usbh1_oc_config(void)
+int usb_phy_mode(int port)
{
- void __iomem *usb_base = (void __iomem *)USBOH3_USB_BASE_ADDR;
- void __iomem *usbother_base = usb_base + USB_OTHERREGS_OFFSET;
+ void __iomem *phy_reg;
+ void __iomem *phy_ctrl;
u32 val;
- val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
+ phy_reg = (void __iomem *)phy_bases[port];
+ phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+ val = readl(phy_ctrl);
+
+ if (val & USBPHY_CTRL_OTG_ID)
+ return USB_INIT_DEVICE;
+ else
+ return USB_INIT_HOST;
+}
+
+/* Base address for this IP block is 0x02184800 */
+struct usbnc_regs {
+ u32 ctrl[4]; /* otg/host1-3 */
+ u32 uh2_hsic_ctrl;
+ u32 uh3_hsic_ctrl;
+ u32 otg_phy_ctrl_0;
+ u32 uh1_phy_ctrl_0;
+};
+#elif defined(CONFIG_SOC_MX7)
+struct usbnc_regs {
+ u32 ctrl1;
+ u32 ctrl2;
+ u32 reserve1[10];
+ u32 phy_cfg1;
+ u32 phy_cfg2;
+ u32 phy_status;
+ u32 reserve2[4];
+ u32 adp_cfg1;
+ u32 adp_cfg2;
+ u32 adp_status;
+};
+
+static void usb_power_config(int index)
+{
+ struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+ (0x10000 * index) + USBNC_OFFSET);
+ void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
+
+ /* Enable usb_otg_id detection */
+ setbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
+}
+
+int usb_phy_mode(int port)
+{
+ struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+ (0x10000 * port) + USBNC_OFFSET);
+ void __iomem *status = (void __iomem *)(&usbnc->phy_status);
+ u32 val;
+
+ val = readl(status);
+
+ if (val & USBNC_PHYSTATUS_ID_DIG)
+ return USB_INIT_DEVICE;
+ else
+ return USB_INIT_HOST;
+}
+#endif
+
+static void usb_oc_config(int index)
+{
+#if defined(CONFIG_SOC_MX6)
+ struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+ USB_OTHERREGS_OFFSET);
+ void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
+#elif defined(CONFIG_SOC_MX7)
+ struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+ (0x10000 * index) + USBNC_OFFSET);
+ void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
+#endif
+
#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
/* mx6qarm2 seems to required a different setting*/
- val &= ~UCTRL_OVER_CUR_POL;
+ clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
#else
- val |= UCTRL_OVER_CUR_POL;
+ setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
+#endif
+
+#if defined(CONFIG_SOC_MX6)
+ setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
+#elif defined(CONFIG_SOC_MX7)
+ setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM);
#endif
- __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
+}
- val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
- val |= UCTRL_OVER_CUR_DIS;
- __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
+/**
+ * board_ehci_hcd_init - override usb phy mode
+ * @port: usb host/otg port
+ *
+ * Target board specific, override usb_phy_mode.
+ * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
+ * left disconnected in this case usb_phy_mode will not be able to identify
+ * the phy mode that usb port is used.
+ * Machine file overrides board_usb_phy_mode.
+ *
+ * Return: USB_INIT_DEVICE or USB_INIT_HOST
+ */
+int __weak board_usb_phy_mode(int port)
+{
+ return usb_phy_mode(port);
}
-int ehci_hcd_init(void)
+/**
+ * board_ehci_hcd_init - set usb vbus voltage
+ * @port: usb otg port
+ *
+ * Target board specific, setup iomux pad to setup supply vbus voltage
+ * for usb otg port. Machine board file overrides board_ehci_hcd_init
+ *
+ * Return: 0 Success
+ */
+int __weak board_ehci_hcd_init(int port)
{
- struct usb_ehci *ehci;
+ return 0;
+}
+/**
+ * board_ehci_power - enables/disables usb vbus voltage
+ * @port: usb otg port
+ * @on: on/off vbus voltage
+ *
+ * Enables/disables supply vbus voltage for usb otg port.
+ * Machine board file overrides board_ehci_power
+ *
+ * Return: 0 Success
+ */
+int __weak board_ehci_power(int port, int on)
+{
+ return 0;
+}
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ enum usb_init_type type;
+#if defined(CONFIG_SOC_MX6)
+ u32 controller_spacing = 0x200;
+#elif defined(CONFIG_SOC_MX7)
+ u32 controller_spacing = 0x10000;
+#endif
+ struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
+ (controller_spacing * index));
+
+ if (index > 3)
+ return -EINVAL;
enable_usboh3_clk(1);
mdelay(1);
/* Do board specific initialization */
- board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
-
-#if CONFIG_MXC_USB_PORT == 1
- /* USB Host 1 */
- usbh1_power_config();
- usbh1_oc_config();
- usbh1_internal_phy_clock_gate(1);
- usbh1_phy_enable();
-#else
-#error "MXC USB port not yet supported"
+ board_ehci_hcd_init(index);
+
+ usb_power_config(index);
+ usb_oc_config(index);
+
+#if defined(CONFIG_SOC_MX6)
+ usb_internal_phy_clock_gate(index, 1);
+ usb_phy_enable(index, ehci);
#endif
+ type = board_usb_phy_mode(index);
- ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
- (0x200 * CONFIG_MXC_USB_PORT));
- hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
- hcor = (struct ehci_hcor *)((uint32_t)hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
- setbits_le32(&ehci->usbmode, CM_HOST);
+ *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+
+ if ((type == init) || (type == USB_INIT_DEVICE))
+ board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
+ if (type != init)
+ return -ENODEV;
+ if (type == USB_INIT_DEVICE)
+ return 0;
- __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+ setbits_le32(&ehci->usbmode, CM_HOST);
+ writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
setbits_le32(&ehci->portsc, USB_EN);
mdelay(10);
return 0;
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
projects / karo-tx-uboot.git / blobdiff