+commit 8e64d6efd8d778a5f83d8bff9cd273a86dcc182f
+Author: Heiko Schocher <hs@denx.de>
+Date: Wed Mar 31 08:34:51 2010 +0200
+
+ net, doc: How to setup MAC address correctly
+
+ As this seems unclear, document how the flow of setting up
+ the MAC address is correct.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+ Text changed slightly, adding input from Mike Frysinger.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit b78b48c6a0c34b2991e31fc4548aaf773d34f2b3
+Author: Heiko Schocher <hs@denx.de>
+Date: Wed Mar 31 08:34:46 2010 +0200
+
+ net, fec_mxc: only setup the device enetaddr with eeprom value
+
+ Only fill the device enetaddr with the contents of the eeprom,
+ do not program it in MAC address registers
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+ Acked-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit d5a64237d58ded31c2eed455c7a346e1c85f5565
+Author: Felix Radensky <felix@embedded-sol.com>
+Date: Tue Mar 30 15:02:13 2010 +0300
+
+ doc: Fix ramdisk examples in doc/uImage.FIT/multi.its
+
+ The ramdisk sections in doc/uImage.FIT/multi.its lack
+ load address and entry point properties. Using examples
+ from this file will result in unbootable image, u-boot
+ will issue the following error messages:
+
+ Can't get ramdisk subimage load address!
+ Ramdisk image is corrupt or invalid
+
+ This patch adds missing properties to ramdisk sections.
+
+ Signed-off-by: Felix Radensky <felix@embedded-sol.com>
+
+commit 2d2018f3db5ed834bc1ee208a2c6212fdf00bca1
+Author: Heiko Schocher <heiko.schocher@invitel.hu>
+Date: Wed Mar 24 13:22:50 2010 +0100
+
+ jffs2, suen3: Fix compiler warning
+
+ $ ./MAKEALL suen3
+ jffs2_1pass.c: In function 'get_fl_mem':
+ jffs2_1pass.c:399: warning: unused variable 'id'
+ jffs2_1pass.c: In function 'get_node_mem':
+ jffs2_1pass.c:423: warning: unused variable 'id'
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+ Tested-by: Tom <Tom.Rix@windriver.com>
+
+commit 9ff32d8ccf0e23b5577c25610f001af8d761b4a2
+Author: Timur Tabi <timur@freescale.com>
+Date: Mon Mar 29 12:51:07 2010 -0500
+
+ mpc86xx: set the DDR BATs after calculating true DDR size
+
+ After determining how much DDR is actually in the system, set DBAT0 and
+ IBAT0 accordingly. This ensures that the CPU won't attempt to access
+ (via speculation) addresses outside of actual memory.
+
+ On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
+ and kept that way. If the system has less than 2GB of memory (typical for
+ an MPC8610 HPCD), the CPU may attempt to access this memory during
+ speculation. The zlib code is notorious for generating such memory reads,
+ and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
+ check (without this patch).
+
+ Currently we are limited to power of two sized DDR since we only use a
+ single bat. If a non-power of two size is used that is less than
+ CONFIG_MAX_MEM_MAPPED u-boot will crash.
+
+ Signed-off-by: Timur Tabi <timur@freescale.com>
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 33f57bd553edf29dffef5a6c7d76e169c79a6049
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Fri Mar 26 15:14:43 2010 -0500
+
+ 85xx: Fix enabling of L1 cache parity on secondary cores
+
+ Use the same code between primary and secondary cores to init the
+ L1 cache. We were not enabling cache parity on the secondary cores.
+
+ Also, reworked the L1 cache init code to match the e500mc L2 init code
+ that first invalidates the cache and locks. Than enables the cache and
+ makes sure its enabled before continuing.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 1a332da61df9c38b567359af114daeaaaefaead8
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Mar 29 15:30:46 2010 +0200
+
+ ppc4xx: Fix problem with I2C bus >= 1 initialization
+
+ This patch fixes a problem introduced with patch eb5eb2b0
+ [ppc4xx: Cleanup PPC4xx I2C infrastructure]. We need to assign the I2C
+ base address to the "i2c" pointer inside of the controller loop.
+ Otherwise controller 0 is initialized multiple times instead of
+ initializing each I2C controller sequentially.
+
+ Tested on Katmai.
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Acked-by: Heiko Schocher <hs@denx.de>
+
+commit 24de2f4be00f81c58270d0df47296bf3a3601cef
+Author: Heiko Schocher <hs@denx.de>
+Date: Mon Mar 29 13:15:48 2010 +0200
+
+ bootm, linux: fix booting Multi-File Image with "kernel+ramdisk+fdt"
+
+ Booting a "Multi-File Image" including a linux kernel, ramdisk and
+ fdt, generated with
+
+ mkimage -A ppc \
+ -O linux \
+ -T multi \
+ -C gzip \
+ -a 00000000 \
+ -e 00000000 \
+ -n "kernel-2.6+initrd+dtb" \
+ -d "vmlinux.bin.gz:ramdisk_image.gz:board.dtb" \
+ multi.bin
+
+ actually fails, because ramdisk start and end addresses
+ didn;t get initialized. This patch fixes this issue.
+
+ Tested on the KUP4K board.
+
+ Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 2883cc2d48e99fd1873ef8af03fee7966611b735
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Mar 28 00:25:14 2010 +0100
+
+ Prepare 2010.03-rc3
+
+ Update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 060f28532b09dd3d2c78423bdd809ac768a27629
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Mar 25 14:07:23 2010 +0100
+
+ cmd_usb.c: print debug messages only when DEBUG is defined
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a574cff121b1479c8e962b7a2a29310020387260
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Mar 24 12:19:19 2010 +0100
+
+ ml300: remove support for broken, orphaned board
+
+ The ml300 board has a number of issues, but nobody cares about this
+ long-orphaned board any more. Remove it.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Acked-by: Michal Simek <monstr@monstr.eu>
+
+commit 04387d24a17b1ee13024dd4779da4b84d47c65cc
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Mar 27 23:37:46 2010 +0100
+
+ mkimage: fix Segmentation Fault when run without "-n name" option
+
+ The restructuring of the mkimage command in commit 89a4d6b1 ("tools:
+ mkimage: split code into core, default and FIT image specific")
+ introduced a bug that caused mkimage to segfault when run without
+ "-n name" option. Initialize the imagename entry to prevent that.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit c40c94a3d20a8616264c2dfcda85279185d69aeb
+Author: Renato Andreola <renato.andreola@imagos.it>
+Date: Wed Mar 24 23:00:47 2010 +0800
+
+ cfi_flash: precision and underflow problem in tout calculation
+
+ With old configuration it could happen tout=0 if CONFIG_SYS_HZ<1000.
+
+ Signed-off-by: Renato Andreola <renato.andreola@imagos.it>
+ Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
+ Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit c550afada5fcad426aa6a219a329feb9eedae8b2
+Author: Rupjyoti Sarmah <rsarmah@appliedmicro.com>
+Date: Wed Mar 24 16:52:02 2010 +0530
+
+ ppc4xx fix unstable 440EPx bootstrap options
+
+ 440EPx fixed bootstrap options A, B, D, and E sets PLL FWDVA to a value = 1.
+ This results in the PLLOUTB being greater than the CPU clock frequency
+ resulting unstable 440EPx operation resulting in various software hang
+ conditions.
+
+ This patch reprograms the FWDVA satisfying the requirement of setting FWDVB
+ to a value greater than 1 while using one of the four deafult bootstrap options.
+
+ Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com>
+ Acked-by : Victor Gallardo <vgallardo@appliedmicro.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit fb508b8b39a52a4063d098f5a9b4355bc5b30c14
+Author: Matthias Fuchs <matthias.fuchs@esd.eu>
+Date: Wed Mar 24 10:16:20 2010 +0100
+
+ at91: Get rid of some warnings when building for otc570
+
+ The soft-i2c code for AT91 defines I2C_SOFT_DECLARATIONS
+ for direct access by dereferencing a pio pointer.
+ The OTC570 platform uses the AT91 gpio API so it does not
+ need the pio variable.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
+
+commit acb13868936a28502782a16e1edaec378e494a29
+Author: Alessandro Rubini <rubini@unipv.it>
+Date: Sat Mar 13 17:44:08 2010 +0100
+
+ lcd: make 16bpp work
+
+ Support for 16bpp was supposed to be in the code but was not working.
+ This makes it work and has been tested in the nhk8815 board.
+
+ Signed-off-by: Alessandro Rubini <rubini@unipv.it>
+ Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 152dda3d94e97ede7af3f9560a59a659384d4585
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Mar 22 23:25:00 2010 +0100
+
+ Prepare v2010.03-rc2
+
+ Update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit d650da2dd4af99967aabc43cccbd8f160eb4cea6
+Author: Matthias Kaehlcke <matthias@kaehlcke.net>
+Date: Tue Mar 9 22:13:33 2010 +0100
+
+ ep93xx timer: Fix resolution of get_ticks()
+
+ ep93xx timer: Make get_ticks() return a value in CONFIG_SYS_HZ resolution,
+ as announced by get_tbclk()
+
+ Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
+
+commit 7e67fb5bf27a07d3b8d6b97c76f7195f7d68af58
+Author: Matthias Kaehlcke <matthias@kaehlcke.net>
+Date: Tue Mar 9 22:13:20 2010 +0100
+
+ ep93xx timer: Fix possible overflow in usecs_to_ticks()
+
+ ep93xx timer: Use 64-bit values in usecs_to_ticks() in order to avoid
+ overflows in intermediate values
+
+ Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
+
+commit daa989b47297c9f73426783599c286ef3a1f3f49
+Author: Asen Dimov <dimov@ronetix.at>
+Date: Thu Mar 18 13:41:47 2010 +0200
+
+ correct a syntax typo in at91_matrix.h
+
+ Signed-off-by: Asen Dimov <dimov@ronetix.at>
+
+commit 322ff395c9aec7b87a2211fe4333fdf44377c564
+Author: Jeff Angielski <jeff@theptrgroup.com>
+Date: Wed Mar 17 15:09:26 2010 -0400
+
+ env: fix endian ordering in crc table
+
+ The crc table was being built as little endian for big endian
+ targets. This would cause fw_printenv to always fail with
+ "Warning: Bad CRC, using default environment" messages.
+
+ Signed-off-by: Jeff Angielski <jeff@theptrgroup.com>
+ Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
+
+commit 51c2ac9bb574c1420b993615268392b0c1f829f6
+Author: Anatolij Gustschin <agust@denx.de>
+Date: Tue Mar 16 17:10:08 2010 +0100
+
+ mpc5121: cpu/mpc512x/diu.c: fix warnings
+
+ Fix warnings while compiling with CONFIG_VIDEO enabled:
+
+ diu.c: In function 'video_hw_init':
+ diu.c:158: warning: 'return' with no value, in function returning non-void
+ diu.c:162: warning: format '%ld' expects type 'long int', but argument 6 has type 'int'
+ diu.c:162: warning: format '%ld' expects type 'long int', but argument 7 has type 'int'
+
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit a74908161a1b37d780d3a826a86807bbc50a3857
+Author: Anatolij Gustschin <agust@denx.de>
+Date: Tue Mar 16 15:29:33 2010 +0100
+
+ console.c: fix problem with splashimage
+
+ If a board uses cfb_console driver and splash image
+ and also defines CONFIG_SILENT_CONSOLE, the user is
+ locked out even if "silent" is not set. It is not
+ possible to get any output, neither on vga console
+ device nor on serial console after redirecting the
+ output to the serial console, since the GD_FLG_SILENT
+ flag remains set.
+
+ Fix the problem by redirecting the output from frame
+ buffer to serial console if splashimage is used.
+ Only suppress the output if "silent" environment
+ variable was set and don't set the GD_FLG_SILENT
+ flag arbitrarily.
+
+ Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 5647f78d04174b0b99857d2a7cbf25141bd14a45
+Author: Thomas Weber <swirl@gmx.li>
+Date: Sat Mar 13 23:14:45 2010 +0100
+
+ mod change 755 => 644 for multiple files
+
+ I executed 'find . -name "*.[chS]" -perm 755 -exec chmod 644 {} \;'
+
+ Signed-off-by: Thomas Weber <swirl@gmx.li>
+ Add some more: neither Makefile nor config.mk need execute permissions.
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 99c006a320ceb9ea19135ac1512e4a81e8bebb72
+Author: Stefano Babic <sbabic@denx.de>
+Date: Sat Mar 13 21:09:00 2010 +0100
+
+ mxcmmc: fix warnings due to access 32 bit registers with 16 bit accessors
+
+ Some registers of the mxcmmc driver were accessed using
+ 16 bit accessor functions, because only the LSB is
+ significant. This is not needed and generates
+ warnings.
+
+ Signed-off-by: Stefano Babic <sbabic@denx.de>
+
+commit c96f86eefc215b67dd222694ce2b6f60e6a42b0b
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jan 17 23:55:53 2010 +0100
+
+ TFTP: allow for adjustable retransmission timout
+
+ So far, TFTP negotiated a fixed retransmission timeout of 5 seconds.
+ In some cases (busy networks, slow TFTP servers) this caused very
+ slow transfers. A new environment variable "tftptimeout" allows to
+ set this timeout. Lowering this value may make downloads succeed
+ faster in networks with high packet loss rates or with unreliable
+ TFTP servers.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Ben Warren <biggerbadderben@gmail.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 252b404d954f91499a4477a3e1064eb237ce5a1c
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Mar 9 14:27:25 2010 +0100
+
+ Fix PCI_BASE_ADDRESS_5 handling in pci_hose_config_device()
+
+ Signed-off-by: FUJITA Kazutoshi <fujita@soum.co.jp>
+ Signed-off-by: <wd@denx.de>
+ Acked-by: Stefan Roese <sr@denx.de>
+
+commit 9d90a93d367272ee65550c0c9f82615cec967c70
+Author: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
+Date: Thu Feb 25 14:03:08 2010 +0100
+
+ cmd_mmc remove \n
+
+ This patch removes the \n after the help message for mmcinfo.
+ This resulted in an empty line being displayed after the mmcinfo line
+ when the help command was given.
+
+ Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
+
+commit 67c7189dd35cb368ef665126fd17816581bd2e92
+Author: Renato Andreola <renato.andreola@imagos.it>
+Date: Tue Mar 16 16:01:29 2010 -0400
+
+ nios2: Added support to YANU UART
+
+ Signed-off-by: Scott McNutt <smcnutt@psyent.com>
+
+commit 1e67fb32fbdae7949bb423c9e20b3f77c0a61663
+Author: Thomas Chou <thomas@wytron.com.tw>
+Date: Tue Mar 16 12:12:48 2010 -0400
+
+ nios2: use generic unaligned.h
+
+ Signed-off-by: Scott McNutt <smcnutt@psyent.com>
+
+commit 05022629a2ca6c385dc390d32c20aa27cf5d915a
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Jan 21 05:01:15 2010 -0500
+
+ asm-blackfin/unaligned.h: add for zlib code
+
+ The new zlib code wants asm/unaligned.h, so have the Blackfin version pull
+ in the asm-generic/unaligned.h.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 3adc1fda38a6aacd4aaf3c2c9cc62a1e69e6de17
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Jan 21 05:01:14 2010 -0500
+
+ asm-generic/unaligned.h: dynamic default unaligned accesses
+
+ This is based on the asm-arm/unaligned.h, but made generic so all arches
+ that cannot do unaligned accesses can utilize it.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit be129aa71882421ad0b50cd3762915d10ace27ad
+Author: Matthias Weisser <matthias.weisser@graf-syteco.de>
+Date: Tue Jan 12 12:06:31 2010 +0100
+
+ video: Fix console display when splashscreen is used
+
+ If a splashscreen is used the console scrolling used the
+ scroll size as needed when a logo was displayed. This
+ patch sets the scroll size to the whole screen if
+ a splashscreen is shown.
+
+ Signed-off-by: Matthias Weisser <matthias.weisser@graf-syteco.de>
+
+commit 93910edb595a88d394da3eb2cf5148096155dfe9
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Mar 12 23:06:04 2010 +0100
+
+ Prepare v2010.03-rc1
+
+ Coding style cleanup, update CHANGELOG.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit 4e72fb15c9073129e05820cc9c54f54bc4985835
Author: Wolfgang Denk <wd@denx.de>
Date: Fri Mar 12 22:11:00 2010 +0100
N: Andre Schwarz
E: andre.schwarz@matrix-vision.de
-D: Support for Matrix Vision boards (MVBLM7/MVBC_P)
+D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR)
N: Robert Schwebel
E: r.schwebel@pengutronix.de
E: martinwinistoerfer@gmx.ch
D: Port to MPC555/556 microcontrollers and support for cmi board
+N: David Wu
+E: support@arcturusnetworks.com
+D: Mercury Security EP2500
+W: http://www.arcturusnetworks.com
+
N: Ming-Len Wu
E: minglen_wu@techware.com.tw
D: Motorola MX1ADS board support
Wolfgang Denk <wd@denx.de>
- IceCube_5100 MGT5100
IceCube_5200 MPC5200
ARIA MPC5121e
mvbc_p MPC5200
mvblm7 MPC8343
+ mvsmr MPC5200
Jon Smirl <jonsmirl@gmail.com>
eb_cpux9k2 ARM920T (AT91RM9200 SoC)
+Heiko Schocher <hs@denx.de>
+
+ magnesium i.MX27
+
Robert Schwebel <r.schwebel@pengutronix.de>
csb226 xscale
M5475EVB mcf547x_8x
M5485EVB mcf547x_8x
+Wolfgang Wegner <w.wegner@astro-kom.de>
+
+ astro_mcf5373l MCF5373L
+
#########################################################################
# AVR32 Systems: #
# #
BF561-ACVILON BF561
+Brent Kandetzki <brentk@teleco.com>
+
+ IP04 BF532
+
#########################################################################
# End of MAINTAINERS list #
#########################################################################
EVAL5200 \
fo300 \
galaxy5200 \
- icecube_5100 \
icecube_5200 \
inka4x0 \
ipek01 \
motionpro \
munices \
MVBC_P \
+ MVSMR \
o2dnt \
pcm030 \
pf5200 \
PM520 \
TB5200 \
- Total5100 \
Total5200 \
Total5200_Rev2 \
TQM5200 \
MIP405 \
MIP405T \
ML2 \
- ml300 \
ml507 \
ml507_flash \
neo \
edb9315a \
imx27lite \
lpd7a400 \
+ magnesium \
mv88f6281gtw_ge \
mx1ads \
mx1fs2 \
#########################################################################
LIST_coldfire=" \
+ astro_mcf5373l \
cobra5272 \
EB+MCF-EV123 \
EB+MCF-EV123_internal \
cm-bf548 \
cm-bf561 \
ibf-dsp561 \
+ ip04 \
tcm-bf518 \
tcm-bf537 \
"
#
-# (C) Copyright 2000-2009
+# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
VERSION = 2010
PATCHLEVEL = 03
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION =
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
#########################################################################
# U-Boot objects....order is important (i.e. start must be first)
-OBJS = cpu/$(CPU)/start.o
+OBJS = $(CPUDIR)/start.o
ifeq ($(CPU),i386)
-OBJS += cpu/$(CPU)/start16.o
-OBJS += cpu/$(CPU)/resetvec.o
+OBJS += $(CPUDIR)/start16.o
+OBJS += $(CPUDIR)/resetvec.o
endif
ifeq ($(CPU),ppc4xx)
-OBJS += cpu/$(CPU)/resetvec.o
+OBJS += $(CPUDIR)/resetvec.o
endif
ifeq ($(CPU),mpc85xx)
-OBJS += cpu/$(CPU)/resetvec.o
+OBJS += $(CPUDIR)/resetvec.o
endif
OBJS := $(addprefix $(obj),$(OBJS))
-LIBS = lib_generic/libgeneric.a
-LIBS += lib_generic/lzma/liblzma.a
-LIBS += lib_generic/lzo/liblzo.a
+LIBS = lib/libgeneric.a
+LIBS += lib/lzma/liblzma.a
+LIBS += lib/lzo/liblzo.a
LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
"board/$(VENDOR)/common/lib$(VENDOR).a"; fi)
-LIBS += cpu/$(CPU)/lib$(CPU).a
+LIBS += $(CPUDIR)/lib$(CPU).a
ifdef SOC
-LIBS += cpu/$(CPU)/$(SOC)/lib$(SOC).a
+LIBS += $(CPUDIR)/$(SOC)/lib$(SOC).a
endif
ifeq ($(CPU),ixp)
-LIBS += cpu/ixp/npe/libnpe.a
+LIBS += arch/arm/cpu/ixp/npe/libnpe.a
endif
-LIBS += lib_$(ARCH)/lib$(ARCH).a
+LIBS += arch/$(ARCH)/lib/lib$(ARCH).a
LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a fs/yaffs2/libyaffs2.a \
fs/ubifs/libubifs.a
endif
ifeq ($(CPU),mpc85xx)
LIBS += drivers/qe/qe.a
-LIBS += cpu/mpc8xxx/ddr/libddr.a
-LIBS += cpu/mpc8xxx/lib8xxx.a
+LIBS += arch/ppc/cpu/mpc8xxx/ddr/libddr.a
+LIBS += arch/ppc/cpu/mpc8xxx/lib8xxx.a
endif
ifeq ($(CPU),mpc86xx)
-LIBS += cpu/mpc8xxx/ddr/libddr.a
-LIBS += cpu/mpc8xxx/lib8xxx.a
+LIBS += arch/ppc/cpu/mpc8xxx/ddr/libddr.a
+LIBS += arch/ppc/cpu/mpc8xxx/lib8xxx.a
endif
LIBS += drivers/rtc/librtc.a
LIBS += drivers/serial/libserial.a
LIBS += drivers/video/libvideo.a
LIBS += drivers/watchdog/libwatchdog.a
LIBS += common/libcommon.a
-LIBS += libfdt/libfdt.a
+LIBS += lib/libfdt/libfdt.a
LIBS += api/libapi.a
LIBS += post/libpost.a
# Add GCC lib
ifdef USE_PRIVATE_LIBGCC
ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
-PLATFORM_LIBGCC = -L $(OBJTREE)/lib_$(ARCH) -lgcc
+PLATFORM_LIBGCC = -L $(OBJTREE)/arch/$(ARCH)/lib -lgcc
else
PLATFORM_LIBGCC = -L $(USE_PRIVATE_LIBGCC) -lgcc
endif
endif
$(OBJS): depend
- $(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@))
+ $(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@))
$(LIBS): depend $(SUBDIRS)
$(MAKE) -C $(dir $(subst $(obj),,$@))
# Explicitly make _depend in subdirs containing multiple targets to prevent
# parallel sub-makes creating .depend files simultaneously.
depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
- for dir in $(SUBDIRS) cpu/$(CPU) $(dir $(LDSCRIPT)) ; do \
+ for dir in $(SUBDIRS) $(CPUDIR) $(dir $(LDSCRIPT)) ; do \
$(MAKE) -C $$dir _depend ; done
TAG_SUBDIRS = $(SUBDIRS)
icecube_5200_LOWBOOT08_config \
icecube_5200_DDR_config \
icecube_5200_DDR_LOWBOOT_config \
-icecube_5200_DDR_LOWBOOT08_config \
-icecube_5100_config: unconfig
+icecube_5200_DDR_LOWBOOT08_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/icecube
@[ -z "$(findstring LOWBOOT_,$@)" ] || \
{ echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h ; \
$(XECHO) "... DDR memory revision" ; \
}
- @[ -z "$(findstring 5200,$@)" ] || \
- { echo "#define CONFIG_MPC5200" >>$(obj)include/config.h ; \
- $(XECHO) "... with MPC5200 processor" ; \
- }
- @[ -z "$(findstring 5100,$@)" ] || \
- { echo "#define CONFIG_MGT5100" >>$(obj)include/config.h ; \
- $(XECHO) "... with MGT5100 processor" ; \
- }
@$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
jupiter_config: unconfig
@mkdir -p $(obj)board/icecube
@ echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h
@ $(XECHO) "... DDR memory revision"
- @ echo "#define CONFIG_MPC5200" >>$(obj)include/config.h
@ echo "#define CONFIG_LITE5200B" >>$(obj)include/config.h
@[ -z "$(findstring _PM_,$@)" ] || \
{ echo "#define CONFIG_LITE5200B_PM" >>$(obj)include/config.h ; \
{ echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \
$(XECHO) "... with LOWBOOT configuration" ; \
}
- @ $(XECHO) "... with MPC5200B processor"
@$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
mcc200_config \
{ echo "#define CONFIG_MVBC_P" >>$(obj)include/config.h; }
@$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p matrix_vision
+MVSMR_config: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/matrix_vision/mvsmr
+ @$(MKCONFIG) $(@:_config=) ppc mpc5xxx mvsmr matrix_vision
+
o2dnt_config: unconfig
@$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt
@ echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
@$(MKCONFIG) -n $@ -a TOP5200 ppc mpc5xxx top5200 emk
-Total5100_config \
Total5200_config \
Total5200_lowboot_config \
Total5200_Rev2_config \
Total5200_Rev2_lowboot_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/total5200
- @[ -z "$(findstring 5100,$@)" ] || \
- { echo "#define CONFIG_MGT5100" >>$(obj)include/config.h ; \
- $(XECHO) "... with MGT5100 processor" ; \
- }
- @[ -z "$(findstring 5200,$@)" ] || \
- { echo "#define CONFIG_MPC5200" >>$(obj)include/config.h ; \
- $(XECHO) "... with MPC5200 processor" ; \
- }
@[ -n "$(findstring Rev,$@)" ] || \
{ echo "#define CONFIG_TOTAL5200_REV 1" >>$(obj)include/config.h ; \
$(XECHO) "... revision 1 board" ; \
ML2_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml2
-ml300_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx
-
ml507_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
@mkdir -p $(obj)include $(obj)board/xilinx/ml507
## Coldfire
#########################################################################
+astro_mcf5373l_config \
+astro_mcf5373l_RAM_config : unconfig
+ @$(MKCONFIG) -t $(@:_config=) astro_mcf5373l m68k mcf532x mcf5373l astro
+
M5208EVBE_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5208evbe freescale
@echo "TEXT_BASE = 0xF0000000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
@$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
+EP2500_config: unconfig
+ @$(MKCONFIG) $(@:_config=) m68k mcf52x2 ep2500 Mercury
+
idmr_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 idmr
davinci_dm6467evm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci
+magnesium_config \
imx27lite_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27
tcm-bf518 tcm-bf537
# Misc third party boards
-BFIN_BOARDS += bf537-minotaur bf537-srv1 bf561-acvilon blackstamp
+BFIN_BOARDS += bf537-minotaur bf537-srv1 bf561-acvilon blackstamp ip04
# I-SYST Micromodule
BFIN_BOARDS += ibf-dsp561
$(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
$(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \
$(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \
- $(obj)lib_blackfin/u-boot.lds \
+ $(obj)arch/blackfin/lib/u-boot.lds \
$(obj)u-boot.lds \
- $(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
+ $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
@rm -f $(obj)u-boot.kwb
@rm -f $(obj)u-boot.imx
@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
- @rm -f $(obj)cpu/mpc824x/bedbug_603e.c
+ @rm -f $(obj)arch/ppc/cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
Directory Hierarchy:
====================
-- api Machine/arch independent API for external apps
-- board Board dependent files
-- common Misc architecture independent functions
-- cpu CPU specific files
- - 74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs
- - arm720t Files specific to ARM 720 CPUs
- - arm920t Files specific to ARM 920 CPUs
- - at91rm9200 Files specific to Atmel AT91RM9200 CPU
- - imx Files specific to Freescale MC9328 i.MX CPUs
- - s3c24x0 Files specific to Samsung S3C24X0 CPUs
- - arm925t Files specific to ARM 925 CPUs
- - arm926ejs Files specific to ARM 926 CPUs
- - arm1136 Files specific to ARM 1136 CPUs
- - at32ap Files specific to Atmel AVR32 AP CPUs
- - blackfin Files specific to Analog Devices Blackfin CPUs
- - i386 Files specific to i386 CPUs
- - ixp Files specific to Intel XScale IXP CPUs
- - leon2 Files specific to Gaisler LEON2 SPARC CPU
- - leon3 Files specific to Gaisler LEON3 SPARC CPU
- - mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs
- - mcf5227x Files specific to Freescale ColdFire MCF5227x CPUs
- - mcf532x Files specific to Freescale ColdFire MCF5329 CPUs
- - mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs
- - mcf547x_8x Files specific to Freescale ColdFire MCF547x_8x CPUs
- - mips Files specific to MIPS CPUs
- - mpc5xx Files specific to Freescale MPC5xx CPUs
- - mpc5xxx Files specific to Freescale MPC5xxx CPUs
- - mpc8xx Files specific to Freescale MPC8xx CPUs
- - mpc8220 Files specific to Freescale MPC8220 CPUs
- - mpc824x Files specific to Freescale MPC824x CPUs
- - mpc8260 Files specific to Freescale MPC8260 CPUs
- - mpc85xx Files specific to Freescale MPC85xx CPUs
- - nios Files specific to Altera NIOS CPUs
- - nios2 Files specific to Altera Nios-II CPUs
- - ppc4xx Files specific to AMCC PowerPC 4xx CPUs
- - pxa Files specific to Intel XScale PXA CPUs
- - s3c44b0 Files specific to Samsung S3C44B0 CPUs
- - sa1100 Files specific to Intel StrongARM SA1100 CPUs
-- disk Code for disk drive partition handling
-- doc Documentation (don't expect too much)
-- drivers Commonly used device drivers
-- examples Example code for standalone applications, etc.
-- fs Filesystem code (cramfs, ext2, jffs2, etc.)
-- include Header Files
-- lib_arm Files generic to ARM architecture
-- lib_avr32 Files generic to AVR32 architecture
-- lib_blackfin Files generic to Blackfin architecture
-- lib_generic Files generic to all architectures
-- lib_i386 Files generic to i386 architecture
-- lib_m68k Files generic to m68k architecture
-- lib_microblaze Files generic to microblaze architecture
-- lib_mips Files generic to MIPS architecture
-- lib_nios Files generic to NIOS architecture
-- lib_nios2 Files generic to NIOS2 architecture
-- lib_ppc Files generic to PowerPC architecture
-- lib_sh Files generic to SH architecture
-- lib_sparc Files generic to SPARC architecture
-- libfdt Library files to support flattened device trees
-- net Networking code
-- post Power On Self Test
-- rtc Real Time Clock drivers
-- tools Tools to build S-Record or U-Boot images, etc.
+/arch Architecture specific files
+ /arm Files generic to ARM architecture
+ /cpu CPU specific files
+ /arm720t Files specific to ARM 720 CPUs
+ /arm920t Files specific to ARM 920 CPUs
+ /at91rm9200 Files specific to Atmel AT91RM9200 CPU
+ /imx Files specific to Freescale MC9328 i.MX CPUs
+ /s3c24x0 Files specific to Samsung S3C24X0 CPUs
+ /arm925t Files specific to ARM 925 CPUs
+ /arm926ejs Files specific to ARM 926 CPUs
+ /arm1136 Files specific to ARM 1136 CPUs
+ /ixp Files specific to Intel XScale IXP CPUs
+ /pxa Files specific to Intel XScale PXA CPUs
+ /s3c44b0 Files specific to Samsung S3C44B0 CPUs
+ /sa1100 Files specific to Intel StrongARM SA1100 CPUs
+ /lib Architecture specific library files
+ /avr32 Files generic to AVR32 architecture
+ /cpu CPU specific files
+ /lib Architecture specific library files
+ /blackfin Files generic to Analog Devices Blackfin architecture
+ /cpu CPU specific files
+ /lib Architecture specific library files
+ /i386 Files generic to i386 architecture
+ /cpu CPU specific files
+ /lib Architecture specific library files
+ /m68k Files generic to m68k architecture
+ /cpu CPU specific files
+ /mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs
+ /mcf5227x Files specific to Freescale ColdFire MCF5227x CPUs
+ /mcf532x Files specific to Freescale ColdFire MCF5329 CPUs
+ /mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs
+ /mcf547x_8x Files specific to Freescale ColdFire MCF547x_8x CPUs
+ /lib Architecture specific library files
+ /microblaze Files generic to microblaze architecture
+ /cpu CPU specific files
+ /lib Architecture specific library files
+ /mips Files generic to MIPS architecture
+ /cpu CPU specific files
+ /lib Architecture specific library files
+ /nios Files generic to Altera NIOS architecture
+ /cpu CPU specific files
+ /lib Architecture specific library files
+ /nios2 Files generic to Altera NIOS2 architecture
+ /cpu CPU specific files
+ /lib Architecture specific library files
+ /ppc Files generic to PowerPC architecture
+ /cpu CPU specific files
+ /74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs
+ /mpc5xx Files specific to Freescale MPC5xx CPUs
+ /mpc5xxx Files specific to Freescale MPC5xxx CPUs
+ /mpc8xx Files specific to Freescale MPC8xx CPUs
+ /mpc8220 Files specific to Freescale MPC8220 CPUs
+ /mpc824x Files specific to Freescale MPC824x CPUs
+ /mpc8260 Files specific to Freescale MPC8260 CPUs
+ /mpc85xx Files specific to Freescale MPC85xx CPUs
+ /ppc4xx Files specific to AMCC PowerPC 4xx CPUs
+ /lib Architecture specific library files
+ /sh Files generic to SH architecture
+ /cpu CPU specific files
+ /sh2 Files specific to sh2 CPUs
+ /sh3 Files specific to sh3 CPUs
+ /sh4 Files specific to sh4 CPUs
+ /lib Architecture specific library files
+ /sparc Files generic to SPARC architecture
+ /cpu CPU specific files
+ /leon2 Files specific to Gaisler LEON2 SPARC CPU
+ /leon3 Files specific to Gaisler LEON3 SPARC CPU
+ /lib Architecture specific library files
+/api Machine/arch independent API for external apps
+/board Board dependent files
+/common Misc architecture independent functions
+/disk Code for disk drive partition handling
+/doc Documentation (don't expect too much)
+/drivers Commonly used device drivers
+/examples Example code for standalone applications, etc.
+/fs Filesystem code (cramfs, ext2, jffs2, etc.)
+/include Header Files
+/lib Files generic to all architectures
+ /libfdt Library files to support flattened device trees
+ /lzma Library files to support LZMA decompression
+ /lzo Library files to support LZO decompression
+/net Networking code
+/post Power On Self Test
+/rtc Real Time Clock drivers
+/tools Tools to build S-Record or U-Boot images, etc.
Software Configuration:
=======================
images, gzipped BMP images can be displayed via the
splashscreen support or the bmp command.
+- Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8
+
+ If this option is set, 8-bit RLE compressed BMP images
+ can be displayed via the splashscreen support or the
+ bmp command.
+
- Compression support:
CONFIG_BZIP2
to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
the CPU's i2c node address).
- Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c)
- sets the CPU up as a master node and so its address should
- therefore be cleared to 0 (See, eg, MPC823e User's Manual
- p.16-473). So, set CONFIG_SYS_I2C_SLAVE to 0.
+ Now, the u-boot i2c code for the mpc8xx
+ (arch/ppc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
+ and so its address should therefore be cleared to 0 (See,
+ eg, MPC823e User's Manual p.16-473). So, set
+ CONFIG_SYS_I2C_SLAVE to 0.
CONFIG_SYS_I2C_INIT_MPC5XXX
13 common/image.c Start multifile image verification
14 common/image.c No initial ramdisk, no multifile, continue.
- 15 lib_<arch>/bootm.c All preparation done, transferring control to OS
+ 15 arch/<arch>/lib/bootm.c All preparation done, transferring control to OS
- -30 lib_ppc/board.c Fatal error, hang the system
+ -30 arch/ppc/lib/board.c Fatal error, hang the system
-31 post/post.c POST test failed, detected by post_output_backlog()
-32 post/post.c POST test failed, detected by post_run_single()
CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
- Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
+ Overrides the default PCI memory map in arch/ppc/cpu/mpc8260/pci.c if set.
- CONFIG_PCI_DISABLE_PCIE:
Disable PCI-Express on systems where it is supported but not
# For EABI, make sure to provide raise()
ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
# This file is parsed several times; make sure to add only once.
-ifeq (,$(findstring lib_arm/eabi_compat.o,$(PLATFORM_LIBS)))
-PLATFORM_LIBS += $(OBJTREE)/lib_arm/eabi_compat.o
+ifeq (,$(findstring arch/arm/lib/eabi_compat.o,$(PLATFORM_LIBS)))
+PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o
endif
endif
-LDSCRIPT := $(SRCTREE)/cpu/$(CPU)/u-boot.lds
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
. = ALIGN(4);
.text :
{
- cpu/arm1136/start.o (.text)
+ arch/arm/cpu/arm1136/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/arm1176/start.o (.text)
+ arch/arm/cpu/arm1176/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/arm720t/start.o (.text)
+ arch/arm/cpu/arm720t/start.o (.text)
*(.text)
}
/*
* Cirrus Logic EP93xx timer support.
*
- * Copyright (C) 2009, 2010
- * Matthias Kaehlcke <matthias@kaehlcke.net>
+ * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (C) 2004, 2005
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
static struct ep93xx_timer
{
unsigned long long ticks;
- unsigned long last_update;
+ unsigned long last_read;
} timer;
-static inline unsigned long clk_to_systicks(unsigned long long clk_ticks)
-{
- unsigned long long sys_ticks = (clk_ticks * CONFIG_SYS_HZ);
- do_div(sys_ticks, TIMER_FREQ);
-
- return (unsigned long)sys_ticks;
-}
-
static inline unsigned long long usecs_to_ticks(unsigned long usecs)
{
unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
return ticks;
}
-static inline unsigned long read_timer(void)
+static inline void read_timer(void)
{
- struct timer_regs *timer = (struct timer_regs *)TIMER_BASE;
+ struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
+ const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
+
+ if (now >= timer.last_read)
+ timer.ticks += now - timer.last_read;
+ else
+ /* an overflow occurred */
+ timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
- return TIMER_MAX_VAL - readl(&timer->timer3.value);
+ timer.last_read = now;
}
/*
*/
unsigned long long get_ticks(void)
{
- const unsigned long now = read_timer();
+ unsigned long long sys_ticks;
- if (now >= timer.last_update)
- timer.ticks += now - timer.last_update;
- else
- /* an overflow occurred */
- timer.ticks += TIMER_MAX_VAL - timer.last_update + now;
+ read_timer();
- timer.last_update = now;
+ sys_ticks = timer.ticks * CONFIG_SYS_HZ;
+ do_div(sys_ticks, TIMER_FREQ);
- return clk_to_systicks(timer.ticks);
+ return sys_ticks;
}
unsigned long get_timer_masked(void)
void reset_timer_masked(void)
{
- timer.last_update = read_timer();
+ read_timer();
timer.ticks = 0;
}
void __udelay(unsigned long usec)
{
- /* read the timer and update timer.ticks */
- get_ticks();
+ unsigned long long target;
+
+ read_timer();
- const unsigned long long target = timer.ticks + usecs_to_ticks(usec);
+ target = timer.ticks + usecs_to_ticks(usec);
while (timer.ticks < target)
- get_ticks();
+ read_timer();
}
int timer_init(void)
{
- struct timer_regs *timer = (struct timer_regs *)TIMER_BASE;
+ struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
- /* use timer 3 with 508KHz and free running */
- writel(TIMER_CLKSEL, &timer->timer3.control);
+ /* use timer 3 with 508KHz and free running, not enabled now */
+ writel(TIMER_CLKSEL, &timer_regs->timer3.control);
- /* set initial timer value 3 */
- writel(TIMER_MAX_VAL, &timer->timer3.load);
+ /* set initial timer value */
+ writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
/* Enable the timer */
writel(TIMER_ENABLE | TIMER_CLKSEL,
- &timer->timer3.control);
+ &timer_regs->timer3.control);
reset_timer_masked();
. = ALIGN(4);
.text :
{
- cpu/arm920t/start.o (.text)
+ arch/arm/cpu/arm920t/start.o (.text)
/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
. = 0x1000;
LONG(0x53555243)
. = ALIGN(4);
.text :
{
- cpu/arm920t/start.o (.text)
+ arch/arm/cpu/arm920t/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/arm925t/start.o (.text)
+ arch/arm/cpu/arm925t/start.o (.text)
*(.text)
}
if (mckr & AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
- mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == AT91SAM9_PMC_MDIV_3
+ mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
+ (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
? freq / 3
: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#else
MX27OBJS = reset.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-SRCS += $(addprefix $(SRCTREE)/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c))
+SRCS += $(addprefix $(SRCTREE)/arch/arm/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS))
all: $(obj).depend $(LIB)
#endif /* CONFIG_FEC_MXC */
#ifdef CONFIG_MXC_MMC
+void mx27_sd1_init_pins(void)
+{
+ int i;
+ unsigned int mode[] = {
+ PE18_PF_SD1_D0,
+ PE19_PF_SD1_D1,
+ PE20_PF_SD1_D2,
+ PE21_PF_SD1_D3,
+ PE22_PF_SD1_CMD,
+ PE23_PF_SD1_CLK,
+ };
+
+ for (i = 0; i < ARRAY_SIZE(mode); i++)
+ imx_gpio_mode(mode[i]);
+
+}
+
void mx27_sd2_init_pins(void)
{
int i;
#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
-/* macro to read the 32 bit timer: since it decrements, we invert read value */
-#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
+/* macro to read the decrementing 32 bit timer as an increasing count */
+#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
/* Configure a free-running, auto-wrap counter with no prescaler */
int timer_init(void)
/* Restart counting from 0 */
void reset_timer(void)
{
- writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); /* Immediate effect */
+ ulong val;
+ writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
+ /*
+ * The load-register isn't really immediate: it changes on clock
+ * edges, so we must wait for our newly-written value to appear.
+ * Since we might miss reading 0, wait for any change in value.
+ */
+ val = READ_TIMER();
+ while (READ_TIMER() == val)
+ ;
}
/* Return how many HZ passed since "base" */
. = ALIGN(4);
.text :
{
- cpu/arm926ejs/start.o (.text)
+ arch/arm/cpu/arm926ejs/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/lh7a40x/start.o (.text)
+ arch/arm/cpu/arm946es/start.o (.text)
*(.text)
}
/* Switch peripheral to PLL 3 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x000010C0
+ orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x19239145
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x000020C0
+ orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
mov r3, #DP_OP_216
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
ldr r1, =0x000020C2
+ orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
- ldr r1, =0x59E35100
+ ldr r1, =CONFIG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
/* Restore the default values in the Gate registers */
. = ALIGN(4);
.text :
{
- cpu/arm_cortexa8/start.o
+ arch/arm/cpu/arm_cortexa8/start.o
*(.text)
}
* Copyright (C) 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
*
- * based on cpu/arm_cortexa8/omap3/cache.S
+ * based on arch/arm/cpu/arm_cortexa8/omap3/cache.S
*
* See file CREDITS for list of people who contributed to this
* project.
. = ALIGN(4);
.text :
{
- cpu/arm_cortexa8/start.o (.text)
+ arch/arm/cpu/arm_cortexa8/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/arm946es/start.o (.text)
+ arch/arm/cpu/arm_intcm/start.o (.text)
*(.text)
}
LIB := $(obj)libnpe.a
-LOCAL_CFLAGS += -I$(TOPDIR)/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux
+LOCAL_CFLAGS += -I$(TOPDIR)/arch/arm/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux
CFLAGS += $(LOCAL_CFLAGS)
HOSTCFLAGS += $(LOCAL_CFLAGS)
. = ALIGN(4);
.text :
{
- cpu/ixp/start.o(.text)
+ arch/arm/cpu/ixp/start.o(.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/arm_intcm/start.o (.text)
+ arch/arm/cpu/lh7a40x/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/pxa/start.o (.text)
+ arch/arm/cpu/pxa/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/s3c44b0/start.o (.text)
+ arch/arm/cpu/s3c44b0/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/sa1100/start.o (.text)
+ arch/arm/cpu/sa1100/start.o (.text)
*(.text)
}
*/
#if defined(CONFIG_NETARM)
-#include <asm-arm/arch-arm720t/netarm_registers.h>
+#include <asm/arch-arm720t/netarm_registers.h>
#elif defined(CONFIG_IMPA7)
/* include IMPA7 specific hardware file if there was one */
#elif defined(CONFIG_EP7312)
#define AT91_PMC_IXR_PCKRDY3 0x00000800
#ifdef CONFIG_AT91_LEGACY
-
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
+#endif
+
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
+#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
+#endif
+
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
+#ifdef CONFIG_AT91_LEGACY
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
+#endif
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
-
+#ifdef CONFIG_AT91_LEGACY
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
+#endif
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
-
+#ifdef CONFIG_AT91_LEGACY
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
+#endif
#define AT91_PMC_DIV (0xff << 0) /* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
+#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
+#endif
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
#define AT91_PMC_PDIV_1 (0 << 12)
#define AT91_PMC_PDIV_2 (1 << 12)
+#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
+#endif
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
+#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
+#endif
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
-
+#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
-
#endif /* CONFIG_AT91_LEGACY */
#endif
#define AT91_PIO_BASE 0xfffff400
#define AT91_PMC_BASE 0xfffffc00
#define AT91_RSTC_BASE 0xfffffd00
+#define AT91_RTT_BASE 0xfffffd20
#define AT91_PIT_BASE 0xfffffd30
#define AT91_WDT_BASE 0xfffffd40
+#define AT91_GPR_BASE 0xfffffd50
#ifdef CONFIG_AT91_LEGACY
#define AT91_PIO_BASE 0xfffff400
#define AT91_PMC_BASE 0xfffffc00
#define AT91_RSTC_BASE 0xfffffd00
+#define AT91_RTT_BASE 0xfffffd20
#define AT91_PIT_BASE 0xfffffd30
#define AT91_WDT_BASE 0xfffffd40
+#define AT91_GPBR_BASE 0xfffffd50
#ifdef CONFIG_AT91_LEGACY
#define AT91_PIO_BASE 0xfffff200
#define AT91_PMC_BASE 0xfffffc00
#define AT91_RSTC_BASE 0xfffffd00
+#define AT91_RTT0_BASE 0xfffffd20
#define AT91_PIT_BASE 0xfffffd30
#define AT91_WDT_BASE 0xfffffd40
+#define AT91_RTT1_BASE 0xfffffd50
+#define AT91_GPBR_BASE 0xfffffd60
#ifdef CONFIG_AT91_LEGACY
#include <asm/arch/hardware.h>
-typedef struct davinci_emif_regs {
- dv_reg ERCSR;
- dv_reg AWCCR;
- dv_reg SDBCR;
- dv_reg SDRCR;
- dv_reg AB1CR;
- dv_reg AB2CR;
- dv_reg AB3CR;
- dv_reg AB4CR;
- dv_reg SDTIMR;
- dv_reg DDRSR;
- dv_reg DDRPHYCR;
- dv_reg DDRPHYSR;
- dv_reg TOTAR;
- dv_reg TOTACTR;
- dv_reg DDRPHYID_REV;
- dv_reg SDSRETR;
- dv_reg EIRR;
- dv_reg EIMR;
- dv_reg EIMSR;
- dv_reg EIMCR;
- dv_reg IOCTRLR;
- dv_reg IOSTATR;
- u_int8_t RSVD0[8];
- dv_reg NANDFCR;
- dv_reg NANDFSR;
- u_int8_t RSVD1[8];
- dv_reg NANDFECC[4];
- u_int8_t RSVD2[60];
- dv_reg NAND4BITECCLOAD;
- dv_reg NAND4BITECC1;
- dv_reg NAND4BITECC2;
- dv_reg NAND4BITECC3;
- dv_reg NAND4BITECC4;
- dv_reg NANDERRADD1;
- dv_reg NANDERRADD2;
- dv_reg NANDERRVAL1;
- dv_reg NANDERRVAL2;
-} emif_registers;
-
-typedef emif_registers *emifregs;
+struct davinci_emif_regs {
+ u_int32_t ercsr;
+ u_int32_t awccr;
+ u_int32_t sdbcr;
+ u_int32_t sdrcr;
+ u_int32_t ab1cr;
+ u_int32_t ab2cr;
+ u_int32_t ab3cr;
+ u_int32_t ab4cr;
+ u_int32_t sdtimr;
+ u_int32_t ddrsr;
+ u_int32_t ddrphycr;
+ u_int32_t ddrphysr;
+ u_int32_t totar;
+ u_int32_t totactr;
+ u_int32_t ddrphyid_rev;
+ u_int32_t sdsretr;
+ u_int32_t eirr;
+ u_int32_t eimr;
+ u_int32_t eimsr;
+ u_int32_t eimcr;
+ u_int32_t ioctrlr;
+ u_int32_t iostatr;
+ u_int8_t rsvd0[8];
+ u_int32_t nandfcr;
+ u_int32_t nandfsr;
+ u_int8_t rsvd1[8];
+ u_int32_t nandfecc[4];
+ u_int8_t rsvd2[60];
+ u_int32_t nand4biteccload;
+ u_int32_t nand4bitecc[4];
+ u_int32_t nanderradd1;
+ u_int32_t nanderradd2;
+ u_int32_t nanderrval1;
+ u_int32_t nanderrval2;
+};
#define davinci_emif_regs \
((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
*/
#if defined(CONFIG_LPC2292)
-#include <asm-arm/arch-lpc2292/lpc2292_registers.h>
+#include <asm/arch-lpc2292/lpc2292_registers.h>
#else
#error No hardware file defined for this configuration
#endif
#endif /* CONFIG_FEC_MXC */
#ifdef CONFIG_MXC_MMC
+extern void mx27_sd1_init_pins(void);
extern void mx27_sd2_init_pins(void);
#endif /* CONFIG_MXC_MMC */
/*
- * needed for cpu/arm_cortexa8/mx51/lowlevel_init.S
+ * needed for arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S
*
* These should be auto-generated
*/
#define MACH_TYPE_AQUILA 2676
#define MACH_TYPE_SPARK_SLS_HW2 2677
#define MACH_TYPE_ESATA_SHEEVAPLUG 2678
-#define MACH_TYPE_SURF7X30 2679
+#define MACH_TYPE_MSM7X30_SURF 2679
#define MACH_TYPE_MICRO2440 2680
#define MACH_TYPE_AM2440 2681
#define MACH_TYPE_TQ2440 2682
#define MACH_TYPE_QSD8X50_FFA 2710
#define MACH_TYPE_QSD8X50A_SURF 2711
#define MACH_TYPE_QSD8X50A_FFA 2712
-#define MACH_TYPE_XGCP10 2713
+#define MACH_TYPE_ADX_XGCP10 2713
#define MACH_TYPE_MCGWUMTS2A 2714
#define MACH_TYPE_MOBIKT 2715
#define MACH_TYPE_MX53_EVK 2716
#define MACH_TYPE_IGEP0030 2717
#define MACH_TYPE_AXELL_H40_H50_CTRL 2718
+#define MACH_TYPE_DTCOMMOD 2719
+#define MACH_TYPE_GOULD 2720
+#define MACH_TYPE_SIBERIA 2721
+#define MACH_TYPE_SBC3530 2722
+#define MACH_TYPE_QARM 2723
+#define MACH_TYPE_MIPS 2724
+#define MACH_TYPE_MX27GRB 2725
+#define MACH_TYPE_SBC8100 2726
+#define MACH_TYPE_SAARB 2727
+#define MACH_TYPE_OMAP3MINI 2728
+#define MACH_TYPE_CNMBOOK7SE 2729
+#define MACH_TYPE_CATAN 2730
+#define MACH_TYPE_HARMONY 2731
+#define MACH_TYPE_TONGA 2732
+#define MACH_TYPE_CYBOOK_ORIZON 2733
+#define MACH_TYPE_HTCRHODIUMCDMA 2734
+#define MACH_TYPE_EPC_G45 2735
+#define MACH_TYPE_EPC_LPC3250 2736
+#define MACH_TYPE_MXC91341EVB 2737
+#define MACH_TYPE_RTW1000 2738
+#define MACH_TYPE_BOBCAT 2739
+#define MACH_TYPE_TRIZEPS6 2740
+#define MACH_TYPE_MSM7X30_FLUID 2741
+#define MACH_TYPE_NEDAP9263 2742
+#define MACH_TYPE_NETGEAR_MS2110 2743
+#define MACH_TYPE_BMX 2744
+#define MACH_TYPE_NETSTREAM 2745
+#define MACH_TYPE_VPNEXT_RCU 2746
+#define MACH_TYPE_VPNEXT_MPU 2747
+#define MACH_TYPE_BCMRING_TABLET_V1 2748
+#define MACH_TYPE_SGARM10 2749
+#define MACH_TYPE_CM_T3517 2750
+#define MACH_TYPE_OMAP3_CPS 2751
+#define MACH_TYPE_AXAR1500_RECEIVER 2752
+#define MACH_TYPE_WBD222 2753
+#define MACH_TYPE_MT65XX 2754
+#define MACH_TYPE_MSM8X60_SURF 2755
+#define MACH_TYPE_MSM8X60_SIM 2756
+#define MACH_TYPE_VMC300 2757
+#define MACH_TYPE_TCC8000_SDK 2758
+#define MACH_TYPE_NANOS 2759
+#define MACH_TYPE_STAMP9G10 2760
+#define MACH_TYPE_STAMP9G45 2761
+#define MACH_TYPE_H6053 2762
+#define MACH_TYPE_SMINT01 2763
+#define MACH_TYPE_PRTLVT2 2764
+#define MACH_TYPE_AP420 2765
+#define MACH_TYPE_HTCSHIFT 2766
+#define MACH_TYPE_DAVINCI_DM365_FC 2767
+#define MACH_TYPE_MSM8X55_SURF 2768
+#define MACH_TYPE_MSM8X55_FFA 2769
+#define MACH_TYPE_ESL_VAMANA 2770
+#define MACH_TYPE_SBC35 2771
+#define MACH_TYPE_MPX6446 2772
+#define MACH_TYPE_OREO_CONTROLLER 2773
+#define MACH_TYPE_KOPIN_MODELS 2774
+#define MACH_TYPE_TTC_VISION2 2775
+#define MACH_TYPE_CNS3420VB 2776
+#define MACH_TYPE_LPC2 2777
+#define MACH_TYPE_OLYMPUS 2778
+#define MACH_TYPE_VORTEX 2779
+#define MACH_TYPE_S5PC200 2780
+#define MACH_TYPE_ECUCORE_9263 2781
+#define MACH_TYPE_SMDKC200 2782
+#define MACH_TYPE_EMSISO_SX27 2783
+#define MACH_TYPE_APX_SOM9G45_EK 2784
+#define MACH_TYPE_SONGSHAN 2785
+#define MACH_TYPE_TIANSHAN 2786
+#define MACH_TYPE_VPX500 2787
+#define MACH_TYPE_AM3517SAM 2788
+#define MACH_TYPE_SKAT91_SIM508 2789
+#define MACH_TYPE_SKAT91_S3E 2790
+#define MACH_TYPE_OMAP4_PANDA 2791
+#define MACH_TYPE_DF7220 2792
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
# else
# define machine_arch_type MACH_TYPE_HYNET_INE
# endif
-# define machine_is_hynet_ine() (machine_arch_type == MACH_TYPE_HYNET_INE)
+# define machine_is_argonst_foundation() (machine_arch_type == MACH_TYPE_HYNET_INE)
#else
-# define machine_is_hynet_ine() (0)
+# define machine_is_argonst_foundation() (0)
#endif
#ifdef CONFIG_MACH_HYNET_APP
# else
# define machine_arch_type MACH_TYPE_OREO
# endif
-# define machine_is_oreo() (machine_arch_type == MACH_TYPE_OREO)
+# define machine_is_oreo_camera() (machine_arch_type == MACH_TYPE_OREO)
#else
-# define machine_is_oreo() (0)
+# define machine_is_oreo_camera() (0)
#endif
#ifdef CONFIG_MACH_SMDK6442
# define machine_is_sheeva_esata() (0)
#endif
-#ifdef CONFIG_MACH_SURF7X30
+#ifdef CONFIG_MACH_MSM7X30_SURF
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_SURF7X30
+# define machine_arch_type MACH_TYPE_MSM7X30_SURF
# endif
-# define machine_is_msm7x30_surf() (machine_arch_type == MACH_TYPE_SURF7X30)
+# define machine_is_msm7x30_surf() (machine_arch_type == MACH_TYPE_MSM7X30_SURF)
#else
# define machine_is_msm7x30_surf() (0)
#endif
# define machine_is_qsd8x50a_ffa() (0)
#endif
-#ifdef CONFIG_MACH_XGCP10
+#ifdef CONFIG_MACH_ADX_XGCP10
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_XGCP10
+# define machine_arch_type MACH_TYPE_ADX_XGCP10
# endif
-# define machine_is_adx_xgcp10() (machine_arch_type == MACH_TYPE_XGCP10)
+# define machine_is_adx_xgcp10() (machine_arch_type == MACH_TYPE_ADX_XGCP10)
#else
# define machine_is_adx_xgcp10() (0)
#endif
# define machine_is_axell_h40_h50_ctrl() (0)
#endif
+#ifdef CONFIG_MACH_DTCOMMOD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DTCOMMOD
+# endif
+# define machine_is_dtcommod() (machine_arch_type == MACH_TYPE_DTCOMMOD)
+#else
+# define machine_is_dtcommod() (0)
+#endif
+
+#ifdef CONFIG_MACH_GOULD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GOULD
+# endif
+# define machine_is_gould() (machine_arch_type == MACH_TYPE_GOULD)
+#else
+# define machine_is_gould() (0)
+#endif
+
+#ifdef CONFIG_MACH_SIBERIA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SIBERIA
+# endif
+# define machine_is_siberia() (machine_arch_type == MACH_TYPE_SIBERIA)
+#else
+# define machine_is_siberia() (0)
+#endif
+
+#ifdef CONFIG_MACH_SBC3530
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SBC3530
+# endif
+# define machine_is_sbc3530() (machine_arch_type == MACH_TYPE_SBC3530)
+#else
+# define machine_is_sbc3530() (0)
+#endif
+
+#ifdef CONFIG_MACH_QARM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_QARM
+# endif
+# define machine_is_qarm() (machine_arch_type == MACH_TYPE_QARM)
+#else
+# define machine_is_qarm() (0)
+#endif
+
+#ifdef CONFIG_MACH_MIPS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MIPS
+# endif
+# define machine_is_mips() (machine_arch_type == MACH_TYPE_MIPS)
+#else
+# define machine_is_mips() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX27GRB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX27GRB
+# endif
+# define machine_is_mx27grb() (machine_arch_type == MACH_TYPE_MX27GRB)
+#else
+# define machine_is_mx27grb() (0)
+#endif
+
+#ifdef CONFIG_MACH_SBC8100
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SBC8100
+# endif
+# define machine_is_sbc8100() (machine_arch_type == MACH_TYPE_SBC8100)
+#else
+# define machine_is_sbc8100() (0)
+#endif
+
+#ifdef CONFIG_MACH_SAARB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SAARB
+# endif
+# define machine_is_saarb() (machine_arch_type == MACH_TYPE_SAARB)
+#else
+# define machine_is_saarb() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3MINI
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3MINI
+# endif
+# define machine_is_omap3mini() (machine_arch_type == MACH_TYPE_OMAP3MINI)
+#else
+# define machine_is_omap3mini() (0)
+#endif
+
+#ifdef CONFIG_MACH_CNMBOOK7SE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CNMBOOK7SE
+# endif
+# define machine_is_cnmbook7se() (machine_arch_type == MACH_TYPE_CNMBOOK7SE)
+#else
+# define machine_is_cnmbook7se() (0)
+#endif
+
+#ifdef CONFIG_MACH_CATAN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CATAN
+# endif
+# define machine_is_catan() (machine_arch_type == MACH_TYPE_CATAN)
+#else
+# define machine_is_catan() (0)
+#endif
+
+#ifdef CONFIG_MACH_HARMONY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HARMONY
+# endif
+# define machine_is_harmony() (machine_arch_type == MACH_TYPE_HARMONY)
+#else
+# define machine_is_harmony() (0)
+#endif
+
+#ifdef CONFIG_MACH_TONGA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TONGA
+# endif
+# define machine_is_tonga() (machine_arch_type == MACH_TYPE_TONGA)
+#else
+# define machine_is_tonga() (0)
+#endif
+
+#ifdef CONFIG_MACH_CYBOOK_ORIZON
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CYBOOK_ORIZON
+# endif
+# define machine_is_cybook_orizon() (machine_arch_type == MACH_TYPE_CYBOOK_ORIZON)
+#else
+# define machine_is_cybook_orizon() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCRHODIUMCDMA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCRHODIUMCDMA
+# endif
+# define machine_is_htcrhodiumcdma() (machine_arch_type == MACH_TYPE_HTCRHODIUMCDMA)
+#else
+# define machine_is_htcrhodiumcdma() (0)
+#endif
+
+#ifdef CONFIG_MACH_EPC_G45
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EPC_G45
+# endif
+# define machine_is_epc_g45() (machine_arch_type == MACH_TYPE_EPC_G45)
+#else
+# define machine_is_epc_g45() (0)
+#endif
+
+#ifdef CONFIG_MACH_EPC_LPC3250
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EPC_LPC3250
+# endif
+# define machine_is_epc_lpc3250() (machine_arch_type == MACH_TYPE_EPC_LPC3250)
+#else
+# define machine_is_epc_lpc3250() (0)
+#endif
+
+#ifdef CONFIG_MACH_MXC91341EVB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MXC91341EVB
+# endif
+# define machine_is_mxc91341evb() (machine_arch_type == MACH_TYPE_MXC91341EVB)
+#else
+# define machine_is_mxc91341evb() (0)
+#endif
+
+#ifdef CONFIG_MACH_RTW1000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_RTW1000
+# endif
+# define machine_is_rtw1000() (machine_arch_type == MACH_TYPE_RTW1000)
+#else
+# define machine_is_rtw1000() (0)
+#endif
+
+#ifdef CONFIG_MACH_BOBCAT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BOBCAT
+# endif
+# define machine_is_bobcat() (machine_arch_type == MACH_TYPE_BOBCAT)
+#else
+# define machine_is_bobcat() (0)
+#endif
+
+#ifdef CONFIG_MACH_TRIZEPS6
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TRIZEPS6
+# endif
+# define machine_is_trizeps6() (machine_arch_type == MACH_TYPE_TRIZEPS6)
+#else
+# define machine_is_trizeps6() (0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X30_FLUID
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MSM7X30_FLUID
+# endif
+# define machine_is_msm7x30_fluid() (machine_arch_type == MACH_TYPE_MSM7X30_FLUID)
+#else
+# define machine_is_msm7x30_fluid() (0)
+#endif
+
+#ifdef CONFIG_MACH_NEDAP9263
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NEDAP9263
+# endif
+# define machine_is_nedap9263() (machine_arch_type == MACH_TYPE_NEDAP9263)
+#else
+# define machine_is_nedap9263() (0)
+#endif
+
+#ifdef CONFIG_MACH_NETGEAR_MS2110
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NETGEAR_MS2110
+# endif
+# define machine_is_netgear_ms2110() (machine_arch_type == MACH_TYPE_NETGEAR_MS2110)
+#else
+# define machine_is_netgear_ms2110() (0)
+#endif
+
+#ifdef CONFIG_MACH_BMX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BMX
+# endif
+# define machine_is_bmx() (machine_arch_type == MACH_TYPE_BMX)
+#else
+# define machine_is_bmx() (0)
+#endif
+
+#ifdef CONFIG_MACH_NETSTREAM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NETSTREAM
+# endif
+# define machine_is_netstream() (machine_arch_type == MACH_TYPE_NETSTREAM)
+#else
+# define machine_is_netstream() (0)
+#endif
+
+#ifdef CONFIG_MACH_VPNEXT_RCU
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VPNEXT_RCU
+# endif
+# define machine_is_vpnext_rcu() (machine_arch_type == MACH_TYPE_VPNEXT_RCU)
+#else
+# define machine_is_vpnext_rcu() (0)
+#endif
+
+#ifdef CONFIG_MACH_VPNEXT_MPU
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VPNEXT_MPU
+# endif
+# define machine_is_vpnext_mpu() (machine_arch_type == MACH_TYPE_VPNEXT_MPU)
+#else
+# define machine_is_vpnext_mpu() (0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING_TABLET_V1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BCMRING_TABLET_V1
+# endif
+# define machine_is_bcmring_tablet_v1() (machine_arch_type == MACH_TYPE_BCMRING_TABLET_V1)
+#else
+# define machine_is_bcmring_tablet_v1() (0)
+#endif
+
+#ifdef CONFIG_MACH_SGARM10
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SGARM10
+# endif
+# define machine_is_sgarm10() (machine_arch_type == MACH_TYPE_SGARM10)
+#else
+# define machine_is_sgarm10() (0)
+#endif
+
+#ifdef CONFIG_MACH_CM_T3517
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CM_T3517
+# endif
+# define machine_is_cm_t3517() (machine_arch_type == MACH_TYPE_CM_T3517)
+#else
+# define machine_is_cm_t3517() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_CPS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_CPS
+# endif
+# define machine_is_omap3_cps() (machine_arch_type == MACH_TYPE_OMAP3_CPS)
+#else
+# define machine_is_omap3_cps() (0)
+#endif
+
+#ifdef CONFIG_MACH_AXAR1500_RECEIVER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AXAR1500_RECEIVER
+# endif
+# define machine_is_axar1500_receiver() (machine_arch_type == MACH_TYPE_AXAR1500_RECEIVER)
+#else
+# define machine_is_axar1500_receiver() (0)
+#endif
+
+#ifdef CONFIG_MACH_WBD222
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WBD222
+# endif
+# define machine_is_wbd222() (machine_arch_type == MACH_TYPE_WBD222)
+#else
+# define machine_is_wbd222() (0)
+#endif
+
+#ifdef CONFIG_MACH_MT65XX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MT65XX
+# endif
+# define machine_is_mt65xx() (machine_arch_type == MACH_TYPE_MT65XX)
+#else
+# define machine_is_mt65xx() (0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X60_SURF
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MSM8X60_SURF
+# endif
+# define machine_is_msm8x60_surf() (machine_arch_type == MACH_TYPE_MSM8X60_SURF)
+#else
+# define machine_is_msm8x60_surf() (0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X60_SIM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MSM8X60_SIM
+# endif
+# define machine_is_msm8x60_sim() (machine_arch_type == MACH_TYPE_MSM8X60_SIM)
+#else
+# define machine_is_msm8x60_sim() (0)
+#endif
+
+#ifdef CONFIG_MACH_VMC300
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VMC300
+# endif
+# define machine_is_vmc300() (machine_arch_type == MACH_TYPE_VMC300)
+#else
+# define machine_is_vmc300() (0)
+#endif
+
+#ifdef CONFIG_MACH_TCC8000_SDK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TCC8000_SDK
+# endif
+# define machine_is_tcc8000_sdk() (machine_arch_type == MACH_TYPE_TCC8000_SDK)
+#else
+# define machine_is_tcc8000_sdk() (0)
+#endif
+
+#ifdef CONFIG_MACH_NANOS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NANOS
+# endif
+# define machine_is_nanos() (machine_arch_type == MACH_TYPE_NANOS)
+#else
+# define machine_is_nanos() (0)
+#endif
+
+#ifdef CONFIG_MACH_STAMP9G10
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_STAMP9G10
+# endif
+# define machine_is_stamp9g10() (machine_arch_type == MACH_TYPE_STAMP9G10)
+#else
+# define machine_is_stamp9g10() (0)
+#endif
+
+#ifdef CONFIG_MACH_STAMP9G45
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_STAMP9G45
+# endif
+# define machine_is_stamp9g45() (machine_arch_type == MACH_TYPE_STAMP9G45)
+#else
+# define machine_is_stamp9g45() (0)
+#endif
+
+#ifdef CONFIG_MACH_H6053
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_H6053
+# endif
+# define machine_is_h6053() (machine_arch_type == MACH_TYPE_H6053)
+#else
+# define machine_is_h6053() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMINT01
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMINT01
+# endif
+# define machine_is_smint01() (machine_arch_type == MACH_TYPE_SMINT01)
+#else
+# define machine_is_smint01() (0)
+#endif
+
+#ifdef CONFIG_MACH_PRTLVT2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PRTLVT2
+# endif
+# define machine_is_prtlvt2() (machine_arch_type == MACH_TYPE_PRTLVT2)
+#else
+# define machine_is_prtlvt2() (0)
+#endif
+
+#ifdef CONFIG_MACH_AP420
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AP420
+# endif
+# define machine_is_ap420() (machine_arch_type == MACH_TYPE_AP420)
+#else
+# define machine_is_ap420() (0)
+#endif
+
+#ifdef CONFIG_MACH_HTCSHIFT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HTCSHIFT
+# endif
+# define machine_is_htcclio() (machine_arch_type == MACH_TYPE_HTCSHIFT)
+#else
+# define machine_is_htcclio() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM365_FC
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAVINCI_DM365_FC
+# endif
+# define machine_is_davinci_dm365_fc() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_FC)
+#else
+# define machine_is_davinci_dm365_fc() (0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X55_SURF
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MSM8X55_SURF
+# endif
+# define machine_is_msm8x55_surf() (machine_arch_type == MACH_TYPE_MSM8X55_SURF)
+#else
+# define machine_is_msm8x55_surf() (0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X55_FFA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MSM8X55_FFA
+# endif
+# define machine_is_msm8x55_ffa() (machine_arch_type == MACH_TYPE_MSM8X55_FFA)
+#else
+# define machine_is_msm8x55_ffa() (0)
+#endif
+
+#ifdef CONFIG_MACH_ESL_VAMANA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ESL_VAMANA
+# endif
+# define machine_is_esl_vamana() (machine_arch_type == MACH_TYPE_ESL_VAMANA)
+#else
+# define machine_is_esl_vamana() (0)
+#endif
+
+#ifdef CONFIG_MACH_SBC35
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SBC35
+# endif
+# define machine_is_sbc35() (machine_arch_type == MACH_TYPE_SBC35)
+#else
+# define machine_is_sbc35() (0)
+#endif
+
+#ifdef CONFIG_MACH_MPX6446
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MPX6446
+# endif
+# define machine_is_mpx6446() (machine_arch_type == MACH_TYPE_MPX6446)
+#else
+# define machine_is_mpx6446() (0)
+#endif
+
+#ifdef CONFIG_MACH_OREO_CONTROLLER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OREO_CONTROLLER
+# endif
+# define machine_is_oreo_controller() (machine_arch_type == MACH_TYPE_OREO_CONTROLLER)
+#else
+# define machine_is_oreo_controller() (0)
+#endif
+
+#ifdef CONFIG_MACH_KOPIN_MODELS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_KOPIN_MODELS
+# endif
+# define machine_is_kopin_models() (machine_arch_type == MACH_TYPE_KOPIN_MODELS)
+#else
+# define machine_is_kopin_models() (0)
+#endif
+
+#ifdef CONFIG_MACH_TTC_VISION2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TTC_VISION2
+# endif
+# define machine_is_ttc_vision2() (machine_arch_type == MACH_TYPE_TTC_VISION2)
+#else
+# define machine_is_ttc_vision2() (0)
+#endif
+
+#ifdef CONFIG_MACH_CNS3420VB
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CNS3420VB
+# endif
+# define machine_is_cns3420vb() (machine_arch_type == MACH_TYPE_CNS3420VB)
+#else
+# define machine_is_cns3420vb() (0)
+#endif
+
+#ifdef CONFIG_MACH_LPC2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_LPC2
+# endif
+# define machine_is_lpc2() (machine_arch_type == MACH_TYPE_LPC2)
+#else
+# define machine_is_lpc2() (0)
+#endif
+
+#ifdef CONFIG_MACH_OLYMPUS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OLYMPUS
+# endif
+# define machine_is_olympus() (machine_arch_type == MACH_TYPE_OLYMPUS)
+#else
+# define machine_is_olympus() (0)
+#endif
+
+#ifdef CONFIG_MACH_VORTEX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VORTEX
+# endif
+# define machine_is_vortex() (machine_arch_type == MACH_TYPE_VORTEX)
+#else
+# define machine_is_vortex() (0)
+#endif
+
+#ifdef CONFIG_MACH_S5PC200
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_S5PC200
+# endif
+# define machine_is_s5pc200() (machine_arch_type == MACH_TYPE_S5PC200)
+#else
+# define machine_is_s5pc200() (0)
+#endif
+
+#ifdef CONFIG_MACH_ECUCORE_9263
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ECUCORE_9263
+# endif
+# define machine_is_ecucore_9263() (machine_arch_type == MACH_TYPE_ECUCORE_9263)
+#else
+# define machine_is_ecucore_9263() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMDKC200
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMDKC200
+# endif
+# define machine_is_smdkc200() (machine_arch_type == MACH_TYPE_SMDKC200)
+#else
+# define machine_is_smdkc200() (0)
+#endif
+
+#ifdef CONFIG_MACH_EMSISO_SX27
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EMSISO_SX27
+# endif
+# define machine_is_emsiso_sx27() (machine_arch_type == MACH_TYPE_EMSISO_SX27)
+#else
+# define machine_is_emsiso_sx27() (0)
+#endif
+
+#ifdef CONFIG_MACH_APX_SOM9G45_EK
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_APX_SOM9G45_EK
+# endif
+# define machine_is_apx_som9g45_ek() (machine_arch_type == MACH_TYPE_APX_SOM9G45_EK)
+#else
+# define machine_is_apx_som9g45_ek() (0)
+#endif
+
+#ifdef CONFIG_MACH_SONGSHAN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SONGSHAN
+# endif
+# define machine_is_songshan() (machine_arch_type == MACH_TYPE_SONGSHAN)
+#else
+# define machine_is_songshan() (0)
+#endif
+
+#ifdef CONFIG_MACH_TIANSHAN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TIANSHAN
+# endif
+# define machine_is_tianshan() (machine_arch_type == MACH_TYPE_TIANSHAN)
+#else
+# define machine_is_tianshan() (0)
+#endif
+
+#ifdef CONFIG_MACH_VPX500
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VPX500
+# endif
+# define machine_is_vpx500() (machine_arch_type == MACH_TYPE_VPX500)
+#else
+# define machine_is_vpx500() (0)
+#endif
+
+#ifdef CONFIG_MACH_AM3517SAM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_AM3517SAM
+# endif
+# define machine_is_am3517sam() (machine_arch_type == MACH_TYPE_AM3517SAM)
+#else
+# define machine_is_am3517sam() (0)
+#endif
+
+#ifdef CONFIG_MACH_SKAT91_SIM508
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SKAT91_SIM508
+# endif
+# define machine_is_skat91_sim508() (machine_arch_type == MACH_TYPE_SKAT91_SIM508)
+#else
+# define machine_is_skat91_sim508() (0)
+#endif
+
+#ifdef CONFIG_MACH_SKAT91_S3E
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SKAT91_S3E
+# endif
+# define machine_is_skat91_s3e() (machine_arch_type == MACH_TYPE_SKAT91_S3E)
+#else
+# define machine_is_skat91_s3e() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP4_PANDA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP4_PANDA
+# endif
+# define machine_is_omap4_panda() (machine_arch_type == MACH_TYPE_OMAP4_PANDA)
+#else
+# define machine_is_omap4_panda() (0)
+#endif
+
+#ifdef CONFIG_MACH_DF7220
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DF7220
+# endif
+# define machine_is_df7220() (machine_arch_type == MACH_TYPE_DF7220)
+#else
+# define machine_is_df7220() (0)
+#endif
+
/*
* These have not yet been registered
*/
CROSS_COMPILE ?= bfin-uclinux-
-STANDALONE_LOAD_ADDR = 0x1000
+STANDALONE_LOAD_ADDR = 0x1000 -m elf32bfin
CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU)))
CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
-LDFLAGS += --gc-sections
+LDFLAGS += --gc-sections -m elf32bfin
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
ifneq (,$(CONFIG_BFIN_CPU))
LDR_FLAGS += --bmode $(subst BFIN_BOOT_,,$(CONFIG_BFIN_BOOT_MODE))
LDR_FLAGS += --use-vmas
-LDR_FLAGS += --initcode $(obj)cpu/$(CPU)/initcode.o
+LDR_FLAGS += --initcode $(obj)$(CPUDIR)/initcode.o
ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_UART)
LDR_FLAGS-$(CONFIG_ENV_IS_EMBEDDED_IN_LDR) += \
--punchit $$(($(CONFIG_ENV_OFFSET))):$$(($(CONFIG_ENV_SIZE))):$(obj)env-ldr.o
LDR_FLAGS += $(LDR_FLAGS-y)
ifeq ($(wildcard $(TOPDIR)/board/$(BOARD)/u-boot.lds*),)
-LDSCRIPT = $(obj)lib_$(ARCH)/u-boot.lds.S
+LDSCRIPT = $(obj)arch/$(ARCH)/lib/u-boot.lds.S
endif
# define BFIN_BOOT_SPI_SSEL 1
#endif
+/* There is no Blackfin/NetBSD port */
+#undef CONFIG_BOOTM_NETBSD
+
/* We rarely use interrupts, so favor throughput over latency */
#define CONFIG_BFIN_INS_LOWOVERHEAD
--- /dev/null
+/*
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _BFIN_PTRACE_H
+#define _BFIN_PTRACE_H
+
+/*
+ * GCC defines register number like this:
+ * -----------------------------
+ * 0 - 7 are data registers R0-R7
+ * 8 - 15 are address registers P0-P7
+ * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
+ * 32 - 33 A registers A0 & A1
+ * 34 - status register
+ * -----------------------------
+ *
+ * We follows above, except:
+ * 32-33 --- Low 32-bit of A0&1
+ * 34-35 --- High 8-bit of A0&1
+ */
+
+#ifndef __ASSEMBLY__
+
+struct task_struct;
+
+/* this struct defines the way the registers are stored on the
+ stack during a system call. */
+
+struct pt_regs {
+ long orig_pc;
+ long ipend;
+ long seqstat;
+ long rete;
+ long retn;
+ long retx;
+ long pc; /* PC == RETI */
+ long rets;
+ long reserved; /* Used as scratch during system calls */
+ long astat;
+ long lb1;
+ long lb0;
+ long lt1;
+ long lt0;
+ long lc1;
+ long lc0;
+ long a1w;
+ long a1x;
+ long a0w;
+ long a0x;
+ long b3;
+ long b2;
+ long b1;
+ long b0;
+ long l3;
+ long l2;
+ long l1;
+ long l0;
+ long m3;
+ long m2;
+ long m1;
+ long m0;
+ long i3;
+ long i2;
+ long i1;
+ long i0;
+ long usp;
+ long fp;
+ long p5;
+ long p4;
+ long p3;
+ long p2;
+ long p1;
+ long p0;
+ long r7;
+ long r6;
+ long r5;
+ long r4;
+ long r3;
+ long r2;
+ long r1;
+ long r0;
+ long orig_r0;
+ long orig_p0;
+ long syscfg;
+};
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+#define PTRACE_GETREGS 12
+#define PTRACE_SETREGS 13 /* ptrace signal */
+
+#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */
+#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */
+#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */
+
+#define PS_S (0x0002)
+
+#ifdef __KERNEL__
+
+/* user_mode returns true if only one bit is set in IPEND, other than the
+ master interrupt enable. */
+#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
+#define instruction_pointer(regs) ((regs)->pc)
+#define user_stack_pointer(regs) ((regs)->usp)
+#define profile_pc(regs) instruction_pointer(regs)
+extern void show_regs(struct pt_regs *);
+
+#define arch_has_single_step() (1)
+extern void user_enable_single_step(struct task_struct *);
+/* see arch/blackfin/kernel/ptrace.c about this redirect */
+#define user_disable_single_step(child) ptrace_disable(child)
+
+/*
+ * Get the address of the live pt_regs for the specified task.
+ * These are saved onto the top kernel stack when the process
+ * is not running.
+ *
+ * Note: if a user thread is execve'd from kernel space, the
+ * kernel stack will not be empty on entry to the kernel, so
+ * ptracing these tasks will fail.
+ */
+#define task_pt_regs(task) \
+ (struct pt_regs *) \
+ ((unsigned long)task_stack_page(task) + \
+ (THREAD_SIZE - sizeof(struct pt_regs)))
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ */
+
+#define PT_R0 204
+#define PT_R1 200
+#define PT_R2 196
+#define PT_R3 192
+#define PT_R4 188
+#define PT_R5 184
+#define PT_R6 180
+#define PT_R7 176
+#define PT_P0 172
+#define PT_P1 168
+#define PT_P2 164
+#define PT_P3 160
+#define PT_P4 156
+#define PT_P5 152
+#define PT_FP 148
+#define PT_USP 144
+#define PT_I0 140
+#define PT_I1 136
+#define PT_I2 132
+#define PT_I3 128
+#define PT_M0 124
+#define PT_M1 120
+#define PT_M2 116
+#define PT_M3 112
+#define PT_L0 108
+#define PT_L1 104
+#define PT_L2 100
+#define PT_L3 96
+#define PT_B0 92
+#define PT_B1 88
+#define PT_B2 84
+#define PT_B3 80
+#define PT_A0X 76
+#define PT_A0W 72
+#define PT_A1X 68
+#define PT_A1W 64
+#define PT_LC0 60
+#define PT_LC1 56
+#define PT_LT0 52
+#define PT_LT1 48
+#define PT_LB0 44
+#define PT_LB1 40
+#define PT_ASTAT 36
+#define PT_RESERVED 32
+#define PT_RETS 28
+#define PT_PC 24
+#define PT_RETX 20
+#define PT_RETN 16
+#define PT_RETE 12
+#define PT_SEQSTAT 8
+#define PT_IPEND 4
+
+#define PT_ORIG_R0 208
+#define PT_ORIG_P0 212
+#define PT_SYSCFG 216
+#define PT_TEXT_ADDR 220
+#define PT_TEXT_END_ADDR 224
+#define PT_DATA_ADDR 228
+#define PT_FDPIC_EXEC 232
+#define PT_FDPIC_INTERP 236
+
+#endif /* _BFIN_PTRACE_H */
--- /dev/null
+/*
+ * Copyright 2004-2009 Analog Devices Inc.
+ * 2001 Lineo, Inc
+ * Tony Kou
+ * 1993 Hamish Macdonald
+ *
+ * Licensed under the GPL-2
+ */
+
+#ifndef _BFIN_TRAPS_H
+#define _BFIN_TRAPS_H
+
+#define VEC_SYS (0)
+#define VEC_EXCPT01 (1)
+#define VEC_EXCPT02 (2)
+#define VEC_EXCPT03 (3)
+#define VEC_EXCPT04 (4)
+#define VEC_EXCPT05 (5)
+#define VEC_EXCPT06 (6)
+#define VEC_EXCPT07 (7)
+#define VEC_EXCPT08 (8)
+#define VEC_EXCPT09 (9)
+#define VEC_EXCPT10 (10)
+#define VEC_EXCPT11 (11)
+#define VEC_EXCPT12 (12)
+#define VEC_EXCPT13 (13)
+#define VEC_EXCPT14 (14)
+#define VEC_EXCPT15 (15)
+#define VEC_STEP (16)
+#define VEC_OVFLOW (17)
+#define VEC_UNDEF_I (33)
+#define VEC_ILGAL_I (34)
+#define VEC_CPLB_VL (35)
+#define VEC_MISALI_D (36)
+#define VEC_UNCOV (37)
+#define VEC_CPLB_M (38)
+#define VEC_CPLB_MHIT (39)
+#define VEC_WATCH (40)
+#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
+#define VEC_MISALI_I (42)
+#define VEC_CPLB_I_VL (43)
+#define VEC_CPLB_I_M (44)
+#define VEC_CPLB_I_MHIT (45)
+#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
+/* The hardware reserves (63) for future use - we use it to tell our
+ * normal exception handling code we have a hardware error
+ */
+#define VEC_HWERR (63)
+
+#endif /* _BFIN_TRAPS_H */
static void display_global_data(void)
{
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
bd_t *bd;
+
+#ifndef CONFIG_DEBUG_EARLY_SERIAL
+ return;
+#endif
+
bd = gd->bd;
printf(" gd: %p\n", gd);
printf(" |-flags: %lx\n", gd->flags);
printf(" |-baudrate: %lu\n", gd->baudrate);
printf(" |-have_console: %lx\n", gd->have_console);
printf(" |-ram_size: %lx\n", gd->ram_size);
- printf(" |-reloc_off: %lx\n", gd->reloc_off);
printf(" |-env_addr: %lx\n", gd->env_addr);
printf(" |-env_valid: %lx\n", gd->env_valid);
printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
printf(" |-bi_flashstart: %lx\n", bd->bi_flashstart);
printf(" |-bi_flashsize: %lx\n", bd->bi_flashsize);
printf(" \\-bi_flashoffset: %lx\n", bd->bi_flashoffset);
-#endif
}
#define CPLB_PAGE_SIZE (4 * 1024 * 1024)
* "continue" and != 0 means "fatal error, hang the system".
*/
+extern int watchdog_init(void);
extern int exception_init(void);
extern int irq_init(void);
extern int timer_init(void);
dcache_enable();
#endif
+#ifdef CONFIG_WATCHDOG
+ serial_early_puts("Setting up external watchdog\n");
+ watchdog_init();
+#endif
+
#ifdef DEBUG
if (CONFIG_SYS_GBL_DATA_SIZE < sizeof(*gd))
hang();
/*
* U-boot - u-boot.lds.S
*
- * Copyright (c) 2005-2008 Analog Device Inc.
+ * Copyright (c) 2005-2010 Analog Device Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#include <asm/blackfin.h>
#undef ALIGN
#undef ENTRY
-#undef bfin
#ifndef LDS_BOARD_TEXT
# define LDS_BOARD_TEXT
{
.text.pre :
{
- cpu/blackfin/start.o (.text .text.*)
+ arch/blackfin/cpu/start.o (.text .text.*)
LDS_BOARD_TEXT
} >ram_code
.text.init :
{
- cpu/blackfin/initcode.o (.text .text.*)
+ arch/blackfin/cpu/initcode.o (.text .text.*)
} >ram_code
__initcode_lma = LOADADDR(.text.init);
__initcode_len = SIZEOF(.text.init);
.data :
{
- . = ALIGN(256);
+ . = ALIGN(4);
*(.data .data.*)
*(.data1)
*(.sdata)
#ifndef __ASM_INTERRUPT_H_
#define __ASM_INTERRUPT_H_ 1
-/* cpu/i386/interrupts.c */
+/* arch/i386/cpu/interrupts.c */
void set_vector(u8 intnum, void *routine);
-/* lib_i386/interupts.c */
+/* arch/i386/lib/interupts.c */
void disable_irq(int irq);
void enable_irq(int irq);
typedef void (timer_fnc_t) (void);
int register_timer_isr (timer_fnc_t *isr_func);
-/* Architecture specific - can be in cpu/i386/, lib_i386/, or $(BOARD)/ */
+/* Architecture specific - can be in arch/i386/cpu/, arch/i386/lib/, or $(BOARD)/ */
int timer_init(void);
/* cpu/.../interrupts.c */
void isa_unmap_rom(u32 addr);
u32 isa_map_rom(u32 bus_addr, int size);
-/* lib_i386/... */
+/* arch/i386/lib/... */
int video_bios_init(void);
int video_init(void);
return (0);
}
-void uart_port_conf(void)
+void uart_port_conf(int port)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CONFIG_SYS_UART_PORT) {
+ switch (port) {
case 0:
gpio->par_uart &=
- (GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK);
+ (GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK);
gpio->par_uart |=
(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
break;
case 1:
gpio->par_uart &=
- (GPIO_PAR_UART_U1TXD_MASK & GPIO_PAR_UART_U1RXD_MASK);
+ (GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK);
gpio->par_uart |=
(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
break;
case 2:
gpio->par_dspi &=
- (GPIO_PAR_DSPI_SIN_MASK & GPIO_PAR_DSPI_SOUT_MASK);
+ (GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK);
gpio->par_dspi =
(GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
break;
switch (cs) {
case 0:
- gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_MASK;
+ gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_UNMASK;
gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
break;
case 2:
- gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+ gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
break;
}
gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
break;
case 2:
- gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+ gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
break;
}
}
#include <config.h>
#include <timestamp.h>
#include "version.h"
+#include <asm/cache.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
#endif
-/* last three long word reserved for cache status */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
-#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
-
#define _START _start
#define _FAULT _fault
movec %d0, %RAMBAR1
#endif
+ /* invalidate and disable cache */
+ move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ move.l #0, %d0
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+
/* initialize general use internal ram */
move.l #0, %d0
move.l #(ICACHE_STATUS), %a1 /* icache */
move.l #(DCACHE_STATUS), %a2 /* icache */
- move.l #(CACR_STATUS), %a3 /* CACR */
move.l %d0, (%a1)
move.l %d0, (%a2)
- move.l %d0, (%a3)
-
- /* invalidate and disable cache */
- move.l #0x01000000, %d0 /* Invalidate cache cmd */
- movec %d0, %CACR /* Invalidate cache */
- move.l #0, %d0
- movec %d0, %ACR0
- movec %d0, %ACR1
/* set stackpointer to end of internal ram to get some stackspace for
the first c-code */
addql #4,%sp
RESTORE_ALL
-/*------------------------------------------------------------------------------*/
-/* cache functions */
- .globl icache_enable
-icache_enable:
- move.l #0x01200000, %d0 /* Invalid cache */
- movec %d0, %CACR
-
- move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0
- movec %d0, %ACR0
-
- move.l #0x81600610, %d0 /* Enable cache */
- movec %d0, %CACR
-
- move.l #(ICACHE_STATUS), %a1
- moveq #1, %d0
- move.l %d0, (%a1)
- rts
-
- .globl icache_disable
-icache_disable:
- move.l #0x01F00000, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Invalidate icache */
- clr.l %d0
- movec %d0, %ACR0
- movec %d0, %ACR1
-
- move.l #(ICACHE_STATUS), %a1
- moveq #0, %d0
- move.l %d0, (%a1)
- rts
-
- .globl icache_status
-icache_status:
- move.l #(ICACHE_STATUS), %a1
- move.l (%a1), %d0
- rts
-
- .globl icache_invalid
-icache_invalid:
- move.l #0x80600610, %d0 /* Invalidate icache */
- movec %d0, %CACR /* Enable and invalidate cache */
- rts
-
- .globl dcache_enable
-dcache_enable:
- move.l #0x01200000, %d0 /* Invalid cache */
- movec %d0, %CACR
-
- move.l #0x81300610, %d0
- movec %d0, %CACR
-
- move.l #(DCACHE_STATUS), %a1
- moveq #1, %d0
- move.l %d0, (%a1)
- rts
-
- .globl dcache_disable
-dcache_disable:
- move.l #0x81600610, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Invalidate icache */
-
- move.l #(DCACHE_STATUS), %a1
- moveq #0, %d0
- move.l %d0, (%a1)
- rts
-
- .globl dcache_invalid
-dcache_invalid:
- move.l #0x81100610, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable and invalidate cache */
- rts
-
- .globl dcache_status
-dcache_status:
- move.l #(DCACHE_STATUS), %a1
- move.l (%a1), %d0
- rts
-
/*------------------------------------------------------------------------------*/
.globl version_string
return (0);
}
-void uart_port_conf(void)
+void uart_port_conf(int port)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CONFIG_SYS_UART_PORT) {
+ switch (port) {
case 0:
- gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+ gpio->par_uart &= ~(GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+ gpio->par_uart |= (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
break;
case 1:
- gpio->par_uart =
- (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
+ gpio->par_uart &=
+ ~(GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
+ gpio->par_uart |=
+ (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
break;
case 2:
- gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+ gpio->par_uart &= ~(GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+ gpio->par_uart |= (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
+ gpio->feci2c &=
+ ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
+ gpio->feci2c |=
+ (GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
+#endif
break;
}
}
if (setclear) {
gpio->par_feci2c |=
- (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
+ (GPIO_PAR_FECI2C_EMDC_FECEMDC |
+ GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
} else {
gpio->par_feci2c &=
~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
#include <config.h>
#include <timestamp.h>
#include "version.h"
+#include <asm/cache.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
movec %d0, %RAMBAR1
/* invalidate and disable cache */
- move.l #0x01000000, %d0 /* Invalidate cache cmd */
+ move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
nop
move.l #0, %d0
/* initialize general use internal ram */
move.l #0, %d0
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2
+ move.l #(ICACHE_STATUS), %a1 /* icache */
+ move.l #(DCACHE_STATUS), %a2 /* icache */
move.l %d0, (%a1)
move.l %d0, (%a2)
addql #4,%sp
RESTORE_ALL
-/*------------------------------------------------------------------------------*/
-/* cache functions */
- .globl icache_enable
-icache_enable:
- move.l #0x01000000, %d0 /* Invalidate cache cmd */
- movec %d0, %CACR /* Invalidate cache */
- nop
- move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
- movec %d0, %ACR0 /* Enable cache */
- move.l #(CONFIG_SYS_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */
- movec %d0, %ACR1 /* Enable cache */
-
- move.l #0x80400100, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable cache */
- nop
-
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
- moveq #1, %d0
- move.l %d0, (%a1)
- rts
-
- .globl icache_disable
-icache_disable:
- move.l #0x00000100, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Disable cache */
- clr.l %d0 /* Setup cache mask */
- movec %d0, %ACR0
- movec %d0, %ACR1
-
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
- moveq #0, %d0
- move.l %d0, (%a1)
- rts
-
- .globl icache_status
-icache_status:
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
- move.l (%a1), %d0
- rts
-
- .globl icache_invalid
-icache_invalid:
- move.l #0x80600100, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable cache */
- nop
- rts
-
- .globl dcache_enable
-dcache_enable:
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
- moveq #1, %d0
- move.l %d0, (%a1)
- rts
-
- /* No dcache, just a dummy function */
- .globl dcache_disable
-dcache_disable:
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
- moveq #0, %d0
- move.l %d0, (%a1)
- rts
-
- .globl dcache_status
-dcache_status:
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
- move.l (%a1), %d0
- rts
-
/*------------------------------------------------------------------------------*/
.globl version_string
* MCF5282 additionals
* (C) Copyright 2005
* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
+ * (c) Copyright 2010
+ * Arcturus Networks Inc. <www.arcturusnetworks.com>
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
return (0);
}
-void uart_port_conf(void)
+void uart_port_conf(int port)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CONFIG_SYS_UART_PORT) {
+ switch (port) {
case 0:
- gpio->par_uart &= GPIO_PAR_UART0_MASK;
+ gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
break;
case 1:
- gpio->par_uart &= GPIO_PAR_UART0_MASK;
+ gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
break;
case 2:
#ifdef CONFIG_SYS_UART2_PRI_GPIO
gpio->par_timer &=
- (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK);
+ (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK);
gpio->par_timer |=
(GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
#endif
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
gpio->par_feci2c &=
- (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK);
+ (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK);
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
#endif
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
gpio->par_feci2c &=
- (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
+ (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
#endif
GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
} else {
gpio->par_fec &=
- (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK);
- gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK;
+ (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK);
+ gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK;
}
return 0;
}
return (0);
}
-void uart_port_conf(void)
+void uart_port_conf(int port)
{
+ volatile u32 *par = (u32 *) MMAP_PAR;
+
/* Setup Ports: */
- switch (CONFIG_SYS_UART_PORT) {
- case 0:
- break;
+ switch (port) {
case 1:
+ *par &= 0xFFE7FFFF;
+ *par |= 0x00180000;
break;
case 2:
+ *par &= 0xFFFFFFFC;
+ *par &= 0x00000003;
break;
}
}
return (0);
}
-void uart_port_conf(void)
+void uart_port_conf(int port)
{
+ u16 temp;
+
/* Setup Ports: */
- switch (CONFIG_SYS_UART_PORT) {
+ switch (port) {
case 0:
- mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
- MCF_GPIO_PAR_UART_U0RXD);
+ temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3;
+ temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD);
+ mbar_writeShort(MCF_GPIO_PAR_UART, temp);
break;
case 1:
- mbar_writeShort(MCF_GPIO_PAR_UART,
- MCF_GPIO_PAR_UART_U1RXD_UART1 |
- MCF_GPIO_PAR_UART_U1TXD_UART1);
+ temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF;
+ temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1);
+ mbar_writeShort(MCF_GPIO_PAR_UART, temp);
break;
case 2:
- mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
+ temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF;
+ temp |= (0x3000);
+ mbar_writeShort(MCF_GPIO_PAR_UART, temp);
break;
}
}
return (0);
}
-void uart_port_conf(void)
+void uart_port_conf(int port)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CONFIG_SYS_UART_PORT) {
+ switch (port) {
case 0:
gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
return (0);
}
-void uart_port_conf(void)
+void uart_port_conf(int port)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CONFIG_SYS_UART_PORT) {
+ switch (port) {
case 0:
+ gpio->par_uart &= ~UART0_ENABLE_MASK;
gpio->par_uart |= UART0_ENABLE_MASK;
break;
case 1:
+ gpio->par_uart &= ~UART1_ENABLE_MASK;
gpio->par_uart |= UART1_ENABLE_MASK;
break;
case 2:
+ gpio->par_uart &= ~UART2_ENABLE_MASK;
gpio->par_uart |= UART2_ENABLE_MASK;
break;
}
#ifdef CONFIG_SYS_PTCPAR
MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
#endif
+#if defined(CONFIG_SYS_PORTTC)
+ MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
+#endif
+#if defined(CONFIG_SYS_DDRTC)
+ MCFGPIO_DDRTC = CONFIG_SYS_DDRTC;
+#endif
#ifdef CONFIG_SYS_PTDPAR
MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
#endif
MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
#endif
+#if defined(CONFIG_SYS_DDRD)
+ MCFGPIO_DDRD = CONFIG_SYS_DDRD;
+#endif
#ifdef CONFIG_SYS_DDRUA
MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
#endif
return (0);
}
-void uart_port_conf(void)
+void uart_port_conf(int port)
{
/* Setup Ports: */
- switch (CONFIG_SYS_UART_PORT) {
+ switch (port) {
case 0:
MCFGPIO_PUAPAR &= 0xFc;
MCFGPIO_PUAPAR |= 0x03;
return (0);
}
-void uart_port_conf(void)
+void uart_port_conf(int port)
{
- /* Setup Ports: */
- switch (CONFIG_SYS_UART_PORT) {
- case 0:
- break;
- case 1:
- break;
- }
}
#endif /* #if defined(CONFIG_M5249) */
#include <config.h>
#include <timestamp.h>
#include "version.h"
+#include <asm/cache.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
#endif
-
#define _START _start
#define _FAULT _fault
movec %d0, %RAMBAR1
#endif
+ /* initialize general use internal ram */
+ move.l #0, %d0
+ move.l #(ICACHE_STATUS), %a1 /* icache */
+ move.l #(DCACHE_STATUS), %a2 /* icache */
+ move.l %d0, (%a1)
+ move.l %d0, (%a2)
+
/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
cmp.l %a2, %a1
bne 7b
-#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
- /* patch the 3 accesspoints to 3 ichache_state */
- /* quick and dirty */
-
- move.l %a0,%d1
- add.l #(icache_state - CONFIG_SYS_MONITOR_BASE),%d1
- move.l %a0,%a1
- add.l #(icache_state_access_1+2 - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %d1,(%a1)
- move.l %a0,%a1
- add.l #(icache_state_access_2+2 - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %d1,(%a1)
- move.l %a0,%a1
- add.l #(icache_state_access_3+2 - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %d1,(%a1)
-#endif
-
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
addql #4,%sp
RESTORE_ALL
-/*------------------------------------------------------------------------------*/
-/* cache functions */
-#ifdef CONFIG_M5208
- .globl icache_enable
-icache_enable:
- move.l #0x01000000, %d0 /* Invalidate cache cmd */
- movec %d0, %CACR /* Invalidate cache */
- move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup cache mask */
- movec %d0, %ACR0 /* Enable cache */
-
- move.l #0x80000200, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable cache */
- nop
-
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
- moveq #1, %d0
- move.l %d0, (%a1)
- rts
-#endif
-
-#ifdef CONFIG_M5271
- .globl icache_enable
-icache_enable:
- move.l #0x01000000, %d0 /* Invalidate cache cmd */
- movec %d0, %CACR /* Invalidate cache */
- move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
- movec %d0, %ACR0 /* Enable cache */
-
- move.l #0x80000200, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable cache */
- nop
-
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
- moveq #1, %d0
- move.l %d0, (%a1)
- rts
-#endif
-
-#ifdef CONFIG_M5272
- .globl icache_enable
-icache_enable:
- move.l #0x01000000, %d0 /* Invalidate cache cmd */
- movec %d0, %CACR /* Invalidate cache */
- move.l #0x0000c000, %d0 /* Setup cache mask */
- movec %d0, %ACR0 /* Enable cache */
- move.l #0xff00c000, %d0 /* Setup cache mask */
- movec %d0, %ACR1 /* Enable cache */
- move.l #0x80000100, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable cache */
- moveq #1, %d0
- move.l %d0, icache_state
- rts
-#endif
-
-#if defined(CONFIG_M5275)
-/*
- * Instruction cache only
- */
- .globl icache_enable
-icache_enable:
- move.l #0x01400000, %d0 /* Invalidate cache cmd */
- movec %d0, %CACR /* Invalidate cache */
- move.l #0x0000c000, %d0 /* Setup SDRAM caching */
- movec %d0, %ACR0 /* Enable cache */
- move.l #0x00000000, %d0 /* No other caching */
- movec %d0, %ACR1 /* Enable cache */
- move.l #0x80400100, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable cache */
- moveq #1, %d0
- move.l %d0, icache_state
- rts
-#endif
-
-#ifdef CONFIG_M5282
- .globl icache_enable
-icache_enable:
- move.l #0x01000000, %d0 /* Invalidate cache cmd */
- movec %d0, %CACR /* Invalidate cache */
- move.l #0x0000c000, %d0 /* Setup cache mask */
- movec %d0, %ACR0 /* Enable cache */
- move.l #0xff00c000, %d0 /* Setup cache mask */
- movec %d0, %ACR1 /* Enable cache */
- move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
- movec %d0, %CACR /* Enable cache */
- moveq #1, %d0
-icache_state_access_1:
- move.l %d0, icache_state
- rts
-#endif
-
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
- .globl icache_enable
-icache_enable:
- /*
- * Note: The 5249 Documentation doesn't give a bit position for CINV!
- * From the 5272 and the 5307 documentation, I have deduced that it is
- * probably CACR[24]. Should someone say something to Motorola?
- * ~Jeremy
- */
- move.l #0x01000000, %d0 /* Invalidate whole cache */
- move.c %d0,%CACR
- move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */
- move.c %d0, %ACR0
- move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */
- move.c %d0, %ACR1
- move.l #0x90000200, %d0 /* Set cache enable cmd */
- move.c %d0,%CACR
- moveq #1, %d0
- move.l %d0, icache_state
- rts
-#endif
-
- .globl icache_disable
-icache_disable:
- move.l #0x00000100, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable cache */
- clr.l %d0 /* Setup cache mask */
- movec %d0, %ACR0 /* Enable cache */
- movec %d0, %ACR1 /* Enable cache */
- moveq #0, %d0
-icache_state_access_2:
- move.l %d0, icache_state
- rts
-
- .globl icache_status
-icache_status:
-icache_state_access_3:
- move.l #(icache_state), %a0
- move.l (%a0), %d0
- rts
-
- .data
-icache_state:
- .long 0 /* cache is diabled on inirialization */
-
- .globl dcache_enable
-dcache_enable:
- /* dummy function */
- rts
-
- .globl dcache_disable
-dcache_disable:
- /* dummy function */
- rts
-
- .globl dcache_status
-dcache_status:
- /* dummy function */
- rts
-
/*------------------------------------------------------------------------------*/
.globl version_string
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+
+cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5301x:=$(shell grep CONFIG_MCF5301x $(TOPDIR)/include/$(cfg))
+is532x:=$(shell grep CONFIG_MCF532x $(TOPDIR)/include/$(cfg))
+
ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
+
+ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x)))
+PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC
+endif
+ifneq (,$(findstring CONFIG_MCF532x,$(is532x)))
PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC
+endif
+
else
PLATFORM_CPPFLAGS += -m5307 -fPIC
endif
return (0);
}
-void uart_port_conf(void)
+void uart_port_conf(int port)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CONFIG_SYS_UART_PORT) {
+ switch (port) {
case 0:
- gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+ gpio->par_uart &= ~(GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+ gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
break;
case 1:
#ifdef CONFIG_SYS_UART1_ALT1_GPIO
gpio->par_simp1h &=
- ~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK);
+ ~(GPIO_PAR_SIMP1H_DATA1_UNMASK |
+ GPIO_PAR_SIMP1H_VEN1_UNMASK);
gpio->par_simp1h |=
(GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
#elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
gpio->par_ssih &=
- ~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK);
+ ~(GPIO_PAR_SSIH_RXD_UNMASK | GPIO_PAR_SSIH_TXD_UNMASK);
gpio->par_ssih |=
(GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
#endif
gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
gpio->par_dspih &=
- ~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK);
+ ~(GPIO_PAR_DSPIH_SIN_UNMASK | GPIO_PAR_DSPIH_SOUT_UNMASK);
gpio->par_dspih |=
(GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
gpio->par_feci2c &=
- ~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
+ ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
gpio->par_feci2c |=
(GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
#endif
if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
gpio->par_fec &=
~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
- gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK;
+ gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_UNMASK;
} else {
gpio->par_fec &=
~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
- gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK;
+ gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_UNMASK;
}
}
return 0;
return (0);
}
-void uart_port_conf(void)
+void uart_port_conf(int port)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CONFIG_SYS_UART_PORT) {
+ switch (port) {
case 0:
- gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+ gpio->par_uart &= ~(GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+ gpio->par_uart |= (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
break;
case 1:
- gpio->par_uart =
+ gpio->par_uart &=
+ ~(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
+ gpio->par_uart |=
(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
break;
case 2:
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
gpio->par_timer &= 0x0F;
gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
+#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
+ gpio->par_feci2c &= 0xFF00;
+ gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
+#elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
+ gpio->par_ssi &= 0xF0FF;
+ gpio->par_ssi |= (GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
+#endif
break;
}
}
PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
PLL_PDR_OUTDIV4(USBDIV - 1);
- pll->pcr &= PLL_PCR_FBDIV_MASK;
+ pll->pcr &= PLL_PCR_FBDIV_UNMASK;
pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
#endif
#ifdef CONFIG_MCF532x
#include <config.h>
#include <timestamp.h>
#include "version.h"
+#include <asm/cache.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
movec %d0, %RAMBAR1
/* invalidate and disable cache */
- move.l #0x01000000, %d0 /* Invalidate cache cmd */
+ move.l #CF_CACR_CINVA, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
/* initialize general use internal ram */
move.l #0, %d0
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2
+ move.l #(ICACHE_STATUS), %a1 /* icache */
+ move.l #(DCACHE_STATUS), %a2 /* icache */
move.l %d0, (%a1)
move.l %d0, (%a2)
RESTORE_ALL
/*------------------------------------------------------------------------------*/
-/* cache functions */
- .globl icache_enable
-icache_enable:
- move.l #0x01000000, %d0 /* Invalidate cache cmd */
- movec %d0, %CACR /* Invalidate cache */
- move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000 + ((CONFIG_SYS_SDRAM_SIZE & 0x1fe0) << 11)), %d0
- movec %d0, %ACR0 /* Enable cache */
-
- move.l #0x80000200, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable cache */
- nop
-
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
- moveq #1, %d0
- move.l %d0, (%a1)
- rts
-
- .globl icache_disable
-icache_disable:
- move.l #0x01000000, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Disable cache */
- clr.l %d0 /* Setup cache mask */
- movec %d0, %ACR0
- movec %d0, %ACR1
-
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
- moveq #0, %d0
- move.l %d0, (%a1)
- rts
-
- .globl icache_status
-icache_status:
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
- move.l (%a1), %d0
- rts
-
- .globl icache_invalid
-icache_invalid:
- move.l #0x81000200, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable cache */
- rts
-
- .globl dcache_enable
-dcache_enable:
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
- moveq #1, %d0
- move.l %d0, (%a1)
- rts
-
- /* No dcache, just a dummy function */
- .globl dcache_disable
-dcache_disable:
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
- moveq #0, %d0
- move.l %d0, (%a1)
- rts
-
- .globl dcache_status
-dcache_status:
- move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
- move.l (%a1), %d0
- rts
-
-/*------------------------------------------------------------------------------*/
-
.globl version_string
version_string:
.ascii U_BOOT_VERSION
#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
+#include <asm/processor.h>
#include <asm/rtc.h>
#if defined(CONFIG_CMD_NET)
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
#endif
+ /*
+ * now the flash base address is no longer at 0 (Newer ColdFire family
+ * boot at address 0 instead of 0xFFnn_nnnn). The vector table must
+ * also move to the new location.
+ */
+ if (CONFIG_SYS_CS0_BASE != 0)
+ setvbr(CONFIG_SYS_CS0_BASE);
+
#ifdef CONFIG_FSL_I2C
gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
#endif
return (0);
}
-void uart_port_conf(void)
+void uart_port_conf(int port)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CONFIG_SYS_UART_PORT) {
+ switch (port) {
case 0:
- gpio->par_uart =
+ gpio->par_uart &=
+ ~(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+ gpio->par_uart |=
(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
break;
case 1:
- gpio->par_uart =
+#ifdef CONFIG_SYS_UART1_PRI_GPIO
+ gpio->par_uart &=
+ ~(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+ gpio->par_uart |=
(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+#elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
+ gpio->par_ssi &=
+ (GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK);
+ gpio->par_ssi |=
+ (GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
+#endif
+ break;
+ case 2:
+#if defined(CONFIG_SYS_UART2_ALT1_GPIO)
+ gpio->par_timer &=
+ (GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK);
+ gpio->par_timer |=
+ (GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
+#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
+ gpio->par_timer &=
+ (GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK);
+ gpio->par_timer |=
+ (GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
+#endif
break;
}
}
~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
- gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
+ gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK;
else
- gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
+ gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK;
}
return 0;
}
#include <config.h>
#include <timestamp.h>
#include "version.h"
+#include <asm/cache.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
#endif
-/* last three long word reserved for cache status */
-#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
-
#define _START _start
#define _FAULT _fault
/* initialize general use internal ram */
move.l #0, %d0
- move.l #(CACR_STATUS), %a1 /* CACR */
- move.l #(ICACHE_STATUS), %a2 /* icache */
- move.l #(DCACHE_STATUS), %a3 /* dcache */
+ move.l #(ICACHE_STATUS), %a1 /* icache */
+ move.l #(DCACHE_STATUS), %a2 /* dcache */
move.l %d0, (%a1)
move.l %d0, (%a2)
- move.l %d0, (%a3)
/* invalidate and disable cache */
- move.l #0x01004100, %d0 /* Invalidate cache cmd */
+ move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
/* initialize general use internal ram */
move.l #0, %d0
- move.l #(CACR_STATUS), %a1 /* CACR */
- move.l #(ICACHE_STATUS), %a2 /* icache */
- move.l #(DCACHE_STATUS), %a3 /* dcache */
+ move.l #(ICACHE_STATUS), %a1 /* icache */
+ move.l #(DCACHE_STATUS), %a2 /* dcache */
move.l %d0, (%a1)
move.l %d0, (%a2)
- move.l %d0, (%a3)
/* invalidate and disable cache */
- move.l #0x01004100, %d0 /* Invalidate cache cmd */
+ move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
addql #4,%sp
RESTORE_ALL
-/*------------------------------------------------------------------------------*/
-/* cache functions */
- .globl icache_enable
-icache_enable:
- move.l #(CACR_STATUS), %a1 /* read CACR Status */
- move.l (%a1), %d1
-
- move.l #0x00040100, %d0 /* Invalidate icache */
- movec %d0, %CACR
-
- move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup icache */
- movec %d0, %ACR2
-
- move.l #0x04088020, %d0 /* Enable bcache and icache */
- movec %d0, %CACR
-
- move.l #(ICACHE_STATUS), %a1
- moveq #1, %d0
- move.l %d0, (%a1)
- rts
-
- .globl icache_disable
-icache_disable:
- move.l #(CACR_STATUS), %a1 /* read CACR Status */
- move.l (%a1), %d0
-
- move.l #0xFFF77BFF, %d0
- or.l #0x00040100, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Invalidate icache */
- clr.l %d0
- movec %d0, %ACR2
- movec %d0, %ACR3
-
- move.l #(ICACHE_STATUS), %a1
- moveq #0, %d0
- move.l %d0, (%a1)
- rts
-
- .globl icache_status
-icache_status:
- move.l #(ICACHE_STATUS), %a1
- move.l (%a1), %d0
- rts
-
- .globl icache_invalid
-icache_invalid:
- move.l #(CACR_STATUS), %a1 /* read CACR Status */
- move.l (%a1), %d0
-
- move.l #0x00040100, %d0 /* Invalidate icache */
- movec %d0, %CACR /* Enable and invalidate cache */
- rts
-
- .globl dcache_enable
-dcache_enable:
- move.l #(CACR_STATUS), %a1 /* read CACR Status */
- move.l (%a1), %d1
-
- move.l #0x01040100, %d0
- movec %d0, %CACR /* Invalidate dcache */
-
- move.l #0x80088020, %d0 /* Enable bcache and icache */
- movec %d0, %CACR
-
- move.l #(DCACHE_STATUS), %a1
- moveq #1, %d0
- move.l %d0, (%a1)
- rts
-
- .globl dcache_disable
-dcache_disable:
- move.l #(CACR_STATUS), %a1 /* read CACR Status */
- move.l (%a1), %d0
-
- and.l #0x7FFFFFFF, %d0
- or.l #0x01000000, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Disable dcache */
- clr.l %d0
- movec %d0, %ACR0
- movec %d0, %ACR1
-
- move.l #(DCACHE_STATUS), %a1
- moveq #0, %d0
- move.l %d0, (%a1)
- rts
-
- .globl dcache_invalid
-dcache_invalid:
- move.l #(CACR_STATUS), %a1 /* read CACR Status */
- move.l (%a1), %d0
-
- move.l #0x81088020, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable and invalidate cache */
- rts
-
- .globl dcache_status
-dcache_status:
- move.l #(DCACHE_STATUS), %a1
- move.l (%a1), %d0
- rts
-
/*------------------------------------------------------------------------------*/
.globl version_string
return (0);
}
-void uart_port_conf(void)
+void uart_port_conf(int port)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
/* Setup Ports: */
- switch (CONFIG_SYS_UART_PORT) {
+ switch (port) {
case 0:
gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
break;
#include <config.h>
#include <timestamp.h>
#include "version.h"
+#include <asm/cache.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
#endif
-/* last three long word reserved for cache status */
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
-#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
-
#define _START _start
#define _FAULT _fault
move.l #0, %d0
move.l #(ICACHE_STATUS), %a1 /* icache */
move.l #(DCACHE_STATUS), %a2 /* icache */
- move.l #(CACR_STATUS), %a3 /* CACR */
move.l %d0, (%a1)
move.l %d0, (%a2)
- move.l %d0, (%a3)
/* set stackpointer to end of internal ram to get some stackspace for the
first c-code */
addql #4,%sp
RESTORE_ALL
-/*------------------------------------------------------------------------------*/
-/* cache functions */
- .globl icache_enable
-icache_enable:
- move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0
- movec %d0, %ACR2 /* Enable cache */
-
- move.l #0x020C8100, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable cache */
- nop
-
- move.l #(ICACHE_STATUS), %a1
- moveq #1, %d0
- move.l %d0, (%a1)
- rts
-
- .globl icache_disable
-icache_disable:
- move.l #0x000C8100, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Disable cache */
- clr.l %d0 /* Setup cache mask */
- movec %d0, %ACR2
- movec %d0, %ACR3
-
- move.l #(ICACHE_STATUS), %a1
- moveq #0, %d0
- move.l %d0, (%a1)
- rts
-
- .globl icache_invalid
-icache_invalid:
- move.l #0x000C8100, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Enable cache */
- rts
-
- .globl icache_status
-icache_status:
- move.l #(ICACHE_STATUS), %a1
- move.l (%a1), %d0
- rts
-
- .globl dcache_enable
-dcache_enable:
- bsr icache_disable
-
- move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0
- movec %d0, %ACR0 /* Enable cache */
-
- move.l #0xA30C8100, %d0 /* Invalidate cache cmd */
- movec %d0, %CACR /* Invalidate cache */
-
- move.l #(DCACHE_STATUS), %a1
- moveq #1, %d0
- move.l %d0, (%a1)
- rts
-
- .globl dcache_disable
-dcache_disable:
- move.l #0xA30C8100, %d0 /* Setup cache mask */
- movec %d0, %CACR /* Disable cache */
- clr.l %d0 /* Setup cache mask */
- movec %d0, %ACR0
- movec %d0, %ACR1
-
- move.l #(DCACHE_STATUS), %a1
- moveq #0, %d0
- move.l %d0, (%a1)
- rts
-
- .globl dcache_status
-dcache_status:
- move.l #(DCACHE_STATUS), %a1
- move.l (%a1), %d0
- rts
-
/*------------------------------------------------------------------------------*/
.globl version_string
--- /dev/null
+/*
+ * ColdFire cache
+ *
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
+ defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x)
+#define CONFIG_CF_V2
+#endif
+
+#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x)
+#define CONFIG_CF_V3
+#endif
+
+#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
+#define CONFIG_CF_V4
+#if defined(CONFIG_MCF5441x)
+#define CONFIG_CF_V4E /* Four Extra ACRn */
+#endif
+#endif
+
+/* ***** CACR ***** */
+/* V2 Core */
+#ifdef CONFIG_CF_V2
+
+#define CF_CACR_CENB (1 << 31)
+#define CF_CACR_CPD (1 << 28)
+#define CF_CACR_CFRZ (1 << 27)
+#define CF_CACR_CEIB (1 << 10)
+#define CF_CACR_DCM (1 << 9)
+#define CF_CACR_DBWE (1 << 8)
+
+#if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253)
+#define CF_CACR_DWP (1 << 6)
+#else
+#define CF_CACR_CINV (1 << 24)
+#define CF_CACR_DISI (1 << 23)
+#define CF_CACR_DISD (1 << 22)
+#define CF_CACR_INVI (1 << 21)
+#define CF_CACR_INVD (1 << 20)
+#define CF_CACR_DWP (1 << 5)
+#define CF_CACR_EUSP (1 << 4)
+#endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */
+
+#endif /* CONFIG_CF_V2 */
+
+/* V3 Core */
+#ifdef CONFIG_CF_V3
+
+#define CF_CACR_EC (1 << 31)
+#define CF_CACR_ESB (1 << 29)
+#define CF_CACR_DPI (1 << 28)
+#define CF_CACR_HLCK (1 << 27)
+#define CF_CACR_CINVA (1 << 24)
+#define CF_CACR_DNFB (1 << 10)
+#define CF_CACR_DCM_UNMASK 0xFFFFFCFF
+#define CF_CACR_DCM_WT (0 << 8)
+#define CF_CACR_DCM_CB (1 << 8)
+#define CF_CACR_DCM_P (2 << 8)
+#define CF_CACR_DCM_IP (3 << 8)
+#define CF_CACR_DW (1 << 5)
+#define CF_CACR_EUSP (1 << 4)
+
+#endif /* CONFIG_CF_V3 */
+
+/* V4 Core */
+#ifdef CONFIG_CF_V4
+
+#define CF_CACR_DEC (1 << 31)
+#define CF_CACR_DW (1 << 30)
+#define CF_CACR_DESB (1 << 29)
+#define CF_CACR_DDPI (1 << 28)
+#define CF_CACR_DHLCK (1 << 27)
+#define CF_CACR_DDCM_UNMASK (0xF9FFFFFF)
+#define CF_CACR_DDCM_WT (0 << 25)
+#define CF_CACR_DDCM_CB (1 << 25)
+#define CF_CACR_DDCM_P (2 << 25)
+#define CF_CACR_DDCM_IP (3 << 25)
+#define CF_CACR_DCINVA (1 << 24)
+
+#define CF_CACR_DDSP (1 << 23)
+#define CF_CACR_BEC (1 << 19)
+#define CF_CACR_BCINVA (1 << 18)
+#define CF_CACR_IEC (1 << 15)
+#define CF_CACR_DNFB (1 << 13)
+#define CF_CACR_IDPI (1 << 12)
+#define CF_CACR_IHLCK (1 << 11)
+#define CF_CACR_IDCM (1 << 10)
+#define CF_CACR_ICINVA (1 << 8)
+#define CF_CACR_IDSP (1 << 7)
+#define CF_CACR_EUSP (1 << 5)
+
+#ifdef CONFIG_MCF5445x
+#define CF_CACR_IVO (1 << 20)
+#define CF_CACR_SPA (1 << 14)
+#else
+#define CF_CACR_DF (1 << 4)
+#endif
+
+#endif /* CONFIG_CF_V4 */
+
+/* ***** ACR ***** */
+#define CF_ACR_ADR_UNMASK (0x00FFFFFF)
+#define CF_ACR_ADR(x) ((x & 0xFF) << 24)
+#define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF)
+#define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16)
+#define CF_ACR_EN (1 << 15)
+#define CF_ACR_SM_UNMASK (0xFFFF9FFF)
+#define CF_ACR_SM_UM (0 << 13)
+#define CF_ACR_SM_SM (1 << 13)
+#define CF_ACR_SM_ALL (3 << 13)
+#define CF_ACR_WP (1 << 2)
+
+/* V2 Core */
+#ifdef CONFIG_CF_V2
+#define CF_ACR_CM (1 << 6)
+#define CF_ACR_BWE (1 << 5)
+#else
+/* V3 & V4 */
+#define CF_ACR_CM_UNMASK (0xFFFFFF9F)
+#define CF_ACR_CM_WT (0 << 5)
+#define CF_ACR_CM_CB (1 << 5)
+#define CF_ACR_CM_P (2 << 5)
+#define CF_ACR_CM_IP (3 << 5)
+#endif /* CONFIG_CF_V2 */
+
+/* V4 Core */
+#ifdef CONFIG_CF_V4
+#define CF_ACR_AMM (1 << 10)
+#define CF_ACR_SP (1 << 3)
+#endif /* CONFIG_CF_V4 */
+
+
+#ifndef CONFIG_SYS_CACHE_ICACR
+#define CONFIG_SYS_CACHE_ICACR 0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_DCACR
+#ifdef CONFIG_SYS_CACHE_ICACR
+#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR
+#else
+#define CONFIG_SYS_CACHE_DCACR 0
+#endif
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR0
+#define CONFIG_SYS_CACHE_ACR0 0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR1
+#define CONFIG_SYS_CACHE_ACR1 0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR2
+#define CONFIG_SYS_CACHE_ACR2 0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR3
+#define CONFIG_SYS_CACHE_ACR3 0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR4
+#define CONFIG_SYS_CACHE_ACR4 0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR5
+#define CONFIG_SYS_CACHE_ACR5 0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR6
+#define CONFIG_SYS_CACHE_ACR6 0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR7
+#define CONFIG_SYS_CACHE_ACR7 0
+#endif
+
+#define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16)
+
+#ifndef __ASSEMBLY__ /* put C only stuff in this section */
+
+void icache_invalid(void);
+void dcache_invalid(void);
+
+#endif
+
+#endif /* __CACHE_H */
#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000)
#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000)
+#define MMAP_PAR (CONFIG_SYS_MBAR2 + 0x0000019C)
#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440)
#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00)
#define PACR_TP 1
#define SCM_BMT_BME (0x00000008)
-#define SCM_BMT_BMT_MASK (0x07)
#define SCM_BMT_BMT(x) ((x) & 0x07)
#define SCM_BMT_BMT1024 (0x0000)
#define SCM_BMT_BMT512 (0x0001)
#define CCM_CCR_PLL_MODE (0x0002)
#define CCM_CCR_RESERVED (0x0001)
-#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6)
+#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
#define CCM_CIR_PRN(x) ((x) & 0x003F)
/* *** General Purpose I/O (GPIO) *** */
#define GPIO_PAR_FBCTL_OE (0x10)
#define GPIO_PAR_FBCTL_TA (0x08)
#define GPIO_PAR_FBCTL_RWB (0x04)
-#define GPIO_PAR_FBCTL_TS_MASK (0xFC)
+#define GPIO_PAR_FBCTL_TS_UNMASK (0xFC)
#define GPIO_PAR_FBCTL_TS_TS (0x03)
#define GPIO_PAR_FBCTL_TS_DMA (0x02)
#define GPIO_PAR_CS3 (0x08)
#define GPIO_PAR_CS2 (0x04)
-#define GPIO_PAR_CS1_MASK (0xFC)
+#define GPIO_PAR_CS1_UNMASK (0xFC)
#define GPIO_PAR_CS1_CS1 (0x03)
#define GPIO_PAR_CS1_SDCS1 (0x02)
-#define GPIO_PAR_FECI2C_RMII_MASK (0x0F)
-#define GPIO_PAR_FECI2C_MDC_MASK (0x3F)
+#define GPIO_PAR_FECI2C_RMII_UNMASK (0x0F)
+#define GPIO_PAR_FECI2C_MDC_UNMASK (0x3F)
#define GPIO_PAR_FECI2C_MDC_MDC (0xC0)
#define GPIO_PAR_FECI2C_MDC_SCL (0x80)
#define GPIO_PAR_FECI2C_MDC_U2TXD (0x40)
-#define GPIO_PAR_FECI2C_MDIO_MASK (0xCF)
+#define GPIO_PAR_FECI2C_MDIO_UNMASK (0xCF)
#define GPIO_PAR_FECI2C_MDIO_MDIO (0x30)
#define GPIO_PAR_FECI2C_MDIO_SDA (0x20)
#define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10)
-#define GPIO_PAR_FECI2C_I2C_MASK (0xF0)
-#define GPIO_PAR_FECI2C_SCL_MASK (0xF3)
+#define GPIO_PAR_FECI2C_I2C_UNMASK (0xF0)
+#define GPIO_PAR_FECI2C_SCL_UNMASK (0xF3)
#define GPIO_PAR_FECI2C_SCL_SCL (0x0C)
#define GPIO_PAR_FECI2C_SCL_U2RXD (0x04)
-#define GPIO_PAR_FECI2C_SDA_MASK (0xFC)
+#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFC)
#define GPIO_PAR_FECI2C_SDA_SDA (0x03)
#define GPIO_PAR_FECI2C_SDA_U2TXD (0x01)
-#define GPIO_PAR_QSPI_PCS2_MASK (0x3F)
+#define GPIO_PAR_QSPI_PCS2_UNMASK (0x3F)
#define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0)
#define GPIO_PAR_QSPI_PCS2_DACK0 (0x80)
#define GPIO_PAR_QSPI_PCS2_U2RTS (0x40)
-#define GPIO_PAR_QSPI_DIN_MASK (0xCF)
+#define GPIO_PAR_QSPI_DIN_UNMASK (0xCF)
#define GPIO_PAR_QSPI_DIN_DIN (0x30)
#define GPIO_PAR_QSPI_DIN_DREQ0 (0x20)
#define GPIO_PAR_QSPI_DIN_U2CTS (0x10)
-#define GPIO_PAR_QSPI_DOUT_MASK (0xF3)
+#define GPIO_PAR_QSPI_DOUT_UNMASK (0xF3)
#define GPIO_PAR_QSPI_DOUT_DOUT (0x0C)
#define GPIO_PAR_QSPI_DOUT_SDA (0x08)
-#define GPIO_PAR_QSPI_SCK_MASK (0xFC)
+#define GPIO_PAR_QSPI_SCK_UNMASK (0xFC)
#define GPIO_PAR_QSPI_SCK_SCK (0x03)
#define GPIO_PAR_QSPI_SCK_SCL (0x02)
#define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4)
#define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2)
#define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03)
-#define GPIO_PAR_TMR_TIN3_MASK (0x3F)
+#define GPIO_PAR_TMR_TIN3_UNMASK (0x3F)
#define GPIO_PAR_TMR_TIN3_TIN3 (0xC0)
#define GPIO_PAR_TMR_TIN3_TOUT3 (0x80)
#define GPIO_PAR_TMR_TIN3_U2CTS (0x40)
-#define GPIO_PAR_TMR_TIN2_MASK (0xCF)
+#define GPIO_PAR_TMR_TIN2_UNMASK (0xCF)
#define GPIO_PAR_TMR_TIN2_TIN2 (0x30)
#define GPIO_PAR_TMR_TIN2_TOUT2 (0x20)
#define GPIO_PAR_TMR_TIN2_U2RTS (0x10)
-#define GPIO_PAR_TMR_TIN1_MASK (0xF3)
+#define GPIO_PAR_TMR_TIN1_UNMASK (0xF3)
#define GPIO_PAR_TMR_TIN1_TIN1 (0x0C)
#define GPIO_PAR_TMR_TIN1_TOUT1 (0x08)
#define GPIO_PAR_TMR_TIN1_U2RXD (0x04)
-#define GPIO_PAR_TMR_TIN0_MASK (0xFC)
+#define GPIO_PAR_TMR_TIN0_UNMASK (0xFC)
#define GPIO_PAR_TMR_TIN0_TIN0 (0x03)
#define GPIO_PAR_TMR_TIN0_TOUT0 (0x02)
#define GPIO_PAR_TMR_TIN0_U2TXD (0x01)
-#define GPIO_PAR_UART1_MASK (0xF03F)
-#define GPIO_PAR_UART0_MASK (0xFFC0)
-#define GPIO_PAR_UART_U1CTS_MASK (0xF3FF)
+#define GPIO_PAR_UART1_UNMASK (0xF03F)
+#define GPIO_PAR_UART0_UNMASK (0xFFC0)
+#define GPIO_PAR_UART_U1CTS_UNMASK (0xF3FF)
#define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00)
#define GPIO_PAR_UART_U1CTS_TIN1 (0x0800)
#define GPIO_PAR_UART_U1CTS_PCS1 (0x0400)
-#define GPIO_PAR_UART_U1RTS_MASK (0xFCFF)
+#define GPIO_PAR_UART_U1RTS_UNMASK (0xFCFF)
#define GPIO_PAR_UART_U1RTS_U1RTS (0x0300)
#define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200)
#define GPIO_PAR_UART_U1RTS_PCS1 (0x0100)
#define GPIO_PAR_UART_U1TXD (0x0080)
#define GPIO_PAR_UART_U1RXD (0x0040)
-#define GPIO_PAR_UART_U0CTS_MASK (0xFFCF)
+#define GPIO_PAR_UART_U0CTS_UNMASK (0xFFCF)
#define GPIO_PAR_UART_U0CTS_U0CTS (0x0030)
#define GPIO_PAR_UART_U0CTS_TIN0 (0x0020)
#define GPIO_PAR_UART_U0CTS_PCS0 (0x0010)
-#define GPIO_PAR_UART_U0RTS_MASK (0xFFF3)
+#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFF3)
#define GPIO_PAR_UART_U0RTS_U0RTS (0x000C)
#define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008)
#define GPIO_PAR_UART_U0RTS_PCS0 (0x0004)
#define GPIO_PAR_UART_U0TXD (0x0002)
#define GPIO_PAR_UART_U0RXD (0x0001)
-#define GPIO_PAR_FEC_7W_MASK (0xF3)
+#define GPIO_PAR_FEC_7W_UNMASK (0xF3)
#define GPIO_PAR_FEC_7W_FEC (0x0C)
#define GPIO_PAR_FEC_7W_U1RTS (0x04)
-#define GPIO_PAR_FEC_MII_MASK (0xFC)
+#define GPIO_PAR_FEC_MII_UNMASK (0xFC)
#define GPIO_PAR_FEC_MII_FEC (0x03)
#define GPIO_PAR_FEC_MII_UnCTS (0x01)
#define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4)
#define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2)
#define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03)
-#define GPIO_MSCR_FB_FBCLK_MASK (0x3F)
-#define GPIO_MSCR_FB_DUP_MASK (0xCF)
-#define GPIO_MSCR_FB_DLO_MASK (0xF3)
-#define GPIO_MSCR_FB_ADRCTL_MASK (0xFC)
+#define GPIO_MSCR_FB_FBCLK_UNMASK (0x3F)
+#define GPIO_MSCR_FB_DUP_UNMASK (0xCF)
+#define GPIO_MSCR_FB_DLO_UNMASK (0xF3)
+#define GPIO_MSCR_FB_ADRCTL_UNMASK (0xFC)
#define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4)
#define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2)
#define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03)
-#define GPIO_MSCR_SDR_SDCLKB_MASK (0xCF)
-#define GPIO_MSCR_SDR_SDCLK_MASK (0xF3)
-#define GPIO_MSCR_SDR_SDRAM_MASK (0xFC)
+#define GPIO_MSCR_SDR_SDCLKB_UNMASK (0xCF)
+#define GPIO_MSCR_SDR_SDCLK_UNMASK (0xF3)
+#define GPIO_MSCR_SDR_SDRAM_UNMASK (0xFC)
#define MSCR_25VDDR (0x03)
#define MSCR_18VDDR_FULL (0x02)
#define MSCR_18VDDR_HALF (0x00)
#define GPIO_DSCR_I2C(x) ((x) & 0x03)
-#define GPIO_DSCR_I2C_MASK (0xFC)
+#define GPIO_DSCR_I2C_UNMASK (0xFC)
#define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4)
-#define GPIO_DSCR_MISC_DBG_MASK (0xCF)
+#define GPIO_DSCR_MISC_DBG_UNMASK (0xCF)
#define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2)
-#define GPIO_DSCR_MISC_RSTOUT_MASK (0xF3)
+#define GPIO_DSCR_MISC_RSTOUT_UNMASK (0xF3)
#define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03)
-#define GPIO_DSCR_MISC_TIMER_MASK (0xFC)
+#define GPIO_DSCR_MISC_TIMER_UNMASK (0xFC)
#define GPIO_DSCR_FEC(x) ((x) & 0x03)
-#define GPIO_DSCR_FEC_MASK (0xFC)
+#define GPIO_DSCR_FEC_UNMASK (0xFC)
#define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4)
-#define GPIO_DSCR_UART_UART1_MASK (0xCF)
+#define GPIO_DSCR_UART_UART1_UNMASK (0xCF)
#define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2)
-#define GPIO_DSCR_UART_UART0_MASK (0xF3)
+#define GPIO_DSCR_UART_UART0_UNMASK (0xF3)
#define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03)
-#define GPIO_DSCR_UART_IRQ_MASK (0xFC)
+#define GPIO_DSCR_UART_IRQ_UNMASK (0xFC)
#define GPIO_DSCR_QSPI(x) ((x) & 0x03)
-#define GPIO_DSCR_QSPI_MASK (0xFC)
+#define GPIO_DSCR_QSPI_UNMASK (0xFC)
#define DSCR_50PF (0x03)
#define DSCR_30PF (0x02)
/* *** Phase Locked Loop (PLL) *** */
#define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4)
-#define PLL_PODR_CPUDIV_MASK (0x0F)
+#define PLL_PODR_CPUDIV_UNMASK (0x0F)
#define PLL_PODR_BUSDIV(x) ((x) & 0x0F)
-#define PLL_PODR_BUSDIV_MASK (0xF0)
+#define PLL_PODR_BUSDIV_UNMASK (0xF0)
#define PLL_PCR_DITHEN (0x80)
#define PLL_PCR_DITHDEV(x) ((x) & 0x07)
-#define PLL_PCR_DITHDEV_MASK (0xF8)
+#define PLL_PCR_DITHDEV_UNMASK (0xF8)
#endif /* __M520X__ */
/* Bit definitions and macros for CCR */
#define CCM_CCR_DRAMSEL (0x0100)
-#define CCM_CCR_CSC_MASK (0xFF3F)
+#define CCM_CCR_CSC_UNMASK (0xFF3F)
#define CCM_CCR_CSC_FBCS5_CS4 (0x00C0)
#define CCM_CCR_CSC_FBCS5_A22 (0x0080)
#define CCM_CCR_CSC_FB_A23_A22 (0x0040)
#define CCM_CCR_LIMP (0x0020)
#define CCM_CCR_LOAD (0x0010)
-#define CCM_CCR_BOOTPS_MASK (0xFFF3)
+#define CCM_CCR_BOOTPS_UNMASK (0xFFF3)
#define CCM_CCR_BOOTPS_PS16 (0x0008)
#define CCM_CCR_BOOTPS_PS8 (0x0004)
#define CCM_CCR_BOOTPS_PS32 (0x0000)
#define CCM_CCR_OSCMODE_OSCBYPASS (0x0002)
/* Bit definitions and macros for RCON */
-#define CCM_RCON_CSC_MASK (0xFF3F)
+#define CCM_RCON_CSC_UNMASK (0xFF3F)
#define CCM_RCON_CSC_FBCS5_CS4 (0x00C0)
#define CCM_RCON_CSC_FBCS5_A22 (0x0080)
#define CCM_RCON_CSC_FB_A23_A22 (0x0040)
#define CCM_RCON_LIMP (0x0020)
#define CCM_RCON_LOAD (0x0010)
-#define CCM_RCON_BOOTPS_MASK (0xFFF3)
+#define CCM_RCON_BOOTPS_UNMASK (0xFFF3)
#define CCM_RCON_BOOTPS_PS16 (0x0008)
#define CCM_RCON_BOOTPS_PS8 (0x0004)
#define CCM_RCON_BOOTPS_PS32 (0x0000)
#define CCM_RCON_OSCMODE_OSCBYPASS (0x0002)
/* Bit definitions and macros for CIR */
-#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */
-#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */
-#define CCM_CIR_PIN_MASK (0xFFC0)
-#define CCM_CIR_PRN_MASK (0x003F)
+#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
+#define CCM_CIR_PRN(x) ((x) & 0x003F)
#define CCM_CIR_PIN_MCF52277 (0x0000)
/* Bit definitions and macros for MISCCR */
* General Purpose I/O Module (GPIO)
*********************************************************************/
/* Bit definitions and macros for PAR_BE */
-#define GPIO_PAR_BE_MASK (0x0F)
+#define GPIO_PAR_BE_UNMASK (0x0F)
#define GPIO_PAR_BE_BE3_BE3 (0x08)
#define GPIO_PAR_BE_BE3_GPIO (0x00)
#define GPIO_PAR_BE_BE2_BE2 (0x04)
#define GPIO_PAR_FBCTL_OE (0x80)
#define GPIO_PAR_FBCTL_TA (0x40)
#define GPIO_PAR_FBCTL_RW (0x20)
-#define GPIO_PAR_FBCTL_TS_MASK (0xE7)
+#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7)
#define GPIO_PAR_FBCTL_TS_FBTS (0x18)
#define GPIO_PAR_FBCTL_TS_DMAACK (0x10)
#define GPIO_PAR_FBCTL_TS_GPIO (0x00)
/* Bit definitions and macros for PAR_FECI2C */
-#define GPIO_PAR_I2C_SCL_MASK (0xF3)
+#define GPIO_PAR_I2C_SCL_UNMASK (0xF3)
#define GPIO_PAR_I2C_SCL_SCL (0x0C)
#define GPIO_PAR_I2C_SCL_CANTXD (0x08)
#define GPIO_PAR_I2C_SCL_U2TXD (0x04)
#define GPIO_PAR_I2C_SCL_GPIO (0x00)
-#define GPIO_PAR_I2C_SDA_MASK (0xFC)
+#define GPIO_PAR_I2C_SDA_UNMASK (0xFC)
#define GPIO_PAR_I2C_SDA_SDA (0x03)
#define GPIO_PAR_I2C_SDA_CANRXD (0x02)
#define GPIO_PAR_I2C_SDA_U2RXD (0x01)
#define GPIO_PAR_I2C_SDA_GPIO (0x00)
/* Bit definitions and macros for PAR_UART */
-#define GPIO_PAR_UART_U1CTS_MASK (0x3FFF)
+#define GPIO_PAR_UART_U1CTS_UNMASK (0x3FFF)
#define GPIO_PAR_UART_U1CTS_U1CTS (0xC000)
#define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000)
#define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000)
#define GPIO_PAR_UART_U1CTS_GPIO (0x0000)
-#define GPIO_PAR_UART_U1RTS_MASK (0xCFFF)
+#define GPIO_PAR_UART_U1RTS_UNMASK (0xCFFF)
#define GPIO_PAR_UART_U1RTS_U1RTS (0x3000)
#define GPIO_PAR_UART_U1RTS_SSIFS (0x2000)
#define GPIO_PAR_UART_U1RTS_LCDPS (0x1000)
#define GPIO_PAR_UART_U1RTS_GPIO (0x0000)
-#define GPIO_PAR_UART_U1RXD_MASK (0xF3FF)
+#define GPIO_PAR_UART_U1RXD_UNMASK (0xF3FF)
#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
#define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800)
#define GPIO_PAR_UART_U1RXD_GPIO (0x0000)
-#define GPIO_PAR_UART_U1TXD_MASK (0xFCFF)
+#define GPIO_PAR_UART_U1TXD_UNMASK (0xFCFF)
#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
#define GPIO_PAR_UART_U1TXD_SSITXD (0x0200)
#define GPIO_PAR_UART_U1TXD_GPIO (0x0000)
-#define GPIO_PAR_UART_U0CTS_MASK (0xFF3F)
+#define GPIO_PAR_UART_U0CTS_UNMASK (0xFF3F)
#define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0)
#define GPIO_PAR_UART_U0CTS_T1OUT (0x0080)
#define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040)
#define GPIO_PAR_UART_U0CTS_GPIO (0x0000)
-#define GPIO_PAR_UART_U0RTS_MASK (0xFFCF)
+#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFCF)
#define GPIO_PAR_UART_U0RTS_U0RTS (0x0030)
#define GPIO_PAR_UART_U0RTS_T1IN (0x0020)
#define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010)
#define GPIO_PAR_UART_U0RTS_GPIO (0x0000)
-#define GPIO_PAR_UART_U0RXD_MASK (0xFFF3)
+#define GPIO_PAR_UART_U0RXD_UNMASK (0xFFF3)
#define GPIO_PAR_UART_U0RXD_U0RXD (0x000C)
#define GPIO_PAR_UART_U0RXD_CANRX (0x0008)
#define GPIO_PAR_UART_U0RXD_GPIO (0x0000)
-#define GPIO_PAR_UART_U0TXD_MASK (0xFFFC)
+#define GPIO_PAR_UART_U0TXD_UNMASK (0xFFFC)
#define GPIO_PAR_UART_U0TXD_U0TXD (0x0003)
#define GPIO_PAR_UART_U0TXD_CANTX (0x0002)
#define GPIO_PAR_UART_U0TXD_GPIO (0x0000)
/* Bit definitions and macros for PAR_DSPI */
-#define GPIO_PAR_DSPI_PCS0_MASK (0x3F)
+#define GPIO_PAR_DSPI_PCS0_UNMASK (0x3F)
#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0)
#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80)
#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
-#define GPIO_PAR_DSPI_SIN_MASK (0xCF)
+#define GPIO_PAR_DSPI_SIN_UNMASK (0xCF)
#define GPIO_PAR_DSPI_SIN_SIN (0x30)
#define GPIO_PAR_DSPI_SIN_U2RXD (0x20)
#define GPIO_PAR_DSPI_SIN_GPIO (0x00)
-#define GPIO_PAR_DSPI_SOUT_MASK (0xF3)
+#define GPIO_PAR_DSPI_SOUT_UNMASK (0xF3)
#define GPIO_PAR_DSPI_SOUT_SOUT (0x0C)
#define GPIO_PAR_DSPI_SOUT_U2TXD (0x08)
#define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
-#define GPIO_PAR_DSPI_SCK_MASK (0xFC)
+#define GPIO_PAR_DSPI_SCK_UNMASK (0xFC)
#define GPIO_PAR_DSPI_SCK_SCK (0x03)
#define GPIO_PAR_DSPI_SCK_U2CTS (0x02)
#define GPIO_PAR_DSPI_SCK_GPIO (0x00)
/* Bit definitions and macros for PAR_TIMER */
-#define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
+#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F)
#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
#define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40)
#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
+#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF)
#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
#define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10)
#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
+#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3)
#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04)
#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
+#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC)
#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
#define GPIO_PAR_TIMER_T0IN_LCDREV (0x01)
#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
/* Bit definitions and macros for GPIO_PAR_LCDCTL */
-#define GPIO_PAR_LCDCTL_ACDOE_MASK (0xE7)
+#define GPIO_PAR_LCDCTL_ACDOE_UNMASK (0xE7)
#define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18)
#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10)
#define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00)
#define GPIO_PAR_LCDCTL_LSCLK (0x01)
/* Bit definitions and macros for PAR_IRQ */
-#define GPIO_PAR_IRQ_IRQ4_MASK (0xF3)
+#define GPIO_PAR_IRQ_IRQ4_UNMASK (0xF3)
#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C)
#define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08)
#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
-#define GPIO_PAR_IRQ_IRQ1_MASK (0xFC)
+#define GPIO_PAR_IRQ_IRQ1_UNMASK (0xFC)
#define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03)
#define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02)
#define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01)
#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
/* Bit definitions and macros for GPIO_PAR_LCDH */
-#define GPIO_PAR_LCDH_LD17_MASK (0xFFFFF3FF)
+#define GPIO_PAR_LCDH_LD17_UNMASK (0xFFFFF3FF)
#define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00)
#define GPIO_PAR_LCDH_LD17_LD11 (0x00000800)
#define GPIO_PAR_LCDH_LD17_GPIO (0x00000000)
-#define GPIO_PAR_LCDH_LD16_MASK (0xFFFFFCFF)
+#define GPIO_PAR_LCDH_LD16_UNMASK (0xFFFFFCFF)
#define GPIO_PAR_LCDH_LD16_LD16 (0x00000300)
#define GPIO_PAR_LCDH_LD16_LD10 (0x00000200)
#define GPIO_PAR_LCDH_LD16_GPIO (0x00000000)
-#define GPIO_PAR_LCDH_LD15_MASK (0xFFFFFF3F)
+#define GPIO_PAR_LCDH_LD15_UNMASK (0xFFFFFF3F)
#define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0)
#define GPIO_PAR_LCDH_LD15_LD9 (0x00000080)
#define GPIO_PAR_LCDH_LD15_GPIO (0x00000000)
-#define GPIO_PAR_LCDH_LD14_MASK (0xFFFFFFCF)
+#define GPIO_PAR_LCDH_LD14_UNMASK (0xFFFFFFCF)
#define GPIO_PAR_LCDH_LD14_LD14 (0x00000030)
#define GPIO_PAR_LCDH_LD14_LD8 (0x00000020)
#define GPIO_PAR_LCDH_LD14_GPIO (0x00000000)
-#define GPIO_PAR_LCDH_LD13_MASK (0xFFFFFFF3)
+#define GPIO_PAR_LCDH_LD13_UNMASK (0xFFFFFFF3)
#define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C)
#define GPIO_PAR_LCDH_LD13_CANTX (0x00000008)
#define GPIO_PAR_LCDH_LD13_GPIO (0x00000000)
-#define GPIO_PAR_LCDH_LD12_MASK (0xFFFFFFFC)
+#define GPIO_PAR_LCDH_LD12_UNMASK (0xFFFFFFFC)
#define GPIO_PAR_LCDH_LD12_LD12 (0x00000003)
#define GPIO_PAR_LCDH_LD12_CANRX (0x00000002)
#define GPIO_PAR_LCDH_LD12_GPIO (0x00000000)
/* Bit definitions and macros for GPIO_PAR_LCDL */
-#define GPIO_PAR_LCDL_LD11_MASK (0x3FFFFFFF)
+#define GPIO_PAR_LCDL_LD11_UNMASK (0x3FFFFFFF)
#define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000)
#define GPIO_PAR_LCDL_LD11_LD7 (0x80000000)
#define GPIO_PAR_LCDL_LD11_GPIO (0x00000000)
-#define GPIO_PAR_LCDL_LD10_MASK (0xCFFFFFFF)
+#define GPIO_PAR_LCDL_LD10_UNMASK (0xCFFFFFFF)
#define GPIO_PAR_LCDL_LD10_LD10 (0x30000000)
#define GPIO_PAR_LCDL_LD10_LD6 (0x20000000)
#define GPIO_PAR_LCDL_LD10_GPIO (0x00000000)
-#define GPIO_PAR_LCDL_LD9_MASK (0xF3FFFFFF)
+#define GPIO_PAR_LCDL_LD9_UNMASK (0xF3FFFFFF)
#define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000)
#define GPIO_PAR_LCDL_LD9_LD5 (0x08000000)
#define GPIO_PAR_LCDL_LD9_GPIO (0x00000000)
-#define GPIO_PAR_LCDL_LD8_MASK (0xFCFFFFFF)
+#define GPIO_PAR_LCDL_LD8_UNMASK (0xFCFFFFFF)
#define GPIO_PAR_LCDL_LD8_LD8 (0x03000000)
#define GPIO_PAR_LCDL_LD8_LD4 (0x02000000)
#define GPIO_PAR_LCDL_LD8_GPIO (0x00000000)
-#define GPIO_PAR_LCDL_LD7_MASK (0xFF3FFFFF)
+#define GPIO_PAR_LCDL_LD7_UNMASK (0xFF3FFFFF)
#define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000)
#define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000)
#define GPIO_PAR_LCDL_LD7_GPIO (0x00000000)
-#define GPIO_PAR_LCDL_LD6_MASK (0xFFCFFFFF)
+#define GPIO_PAR_LCDL_LD6_UNMASK (0xFFCFFFFF)
#define GPIO_PAR_LCDL_LD6_LD6 (0x00300000)
#define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000)
#define GPIO_PAR_LCDL_LD6_GPIO (0x00000000)
-#define GPIO_PAR_LCDL_LD5_MASK (0xFFF3FFFF)
+#define GPIO_PAR_LCDL_LD5_UNMASK (0xFFF3FFFF)
#define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000)
#define GPIO_PAR_LCDL_LD5_LD3 (0x00080000)
#define GPIO_PAR_LCDL_LD5_GPIO (0x00000000)
-#define GPIO_PAR_LCDL_LD4_MASK (0xFFFCFFFF)
+#define GPIO_PAR_LCDL_LD4_UNMASK (0xFFFCFFFF)
#define GPIO_PAR_LCDL_LD4_LD4 (0x00030000)
#define GPIO_PAR_LCDL_LD4_LD2 (0x00020000)
#define GPIO_PAR_LCDL_LD4_GPIO (0x00000000)
-#define GPIO_PAR_LCDL_LD3_MASK (0xFFFF3FFF)
+#define GPIO_PAR_LCDL_LD3_UNMASK (0xFFFF3FFF)
#define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000)
#define GPIO_PAR_LCDL_LD3_LD1 (0x00008000)
#define GPIO_PAR_LCDL_LD3_GPIO (0x00000000)
-#define GPIO_PAR_LCDL_LD2_MASK (0xFFFFCFFF)
+#define GPIO_PAR_LCDL_LD2_UNMASK (0xFFFFCFFF)
#define GPIO_PAR_LCDL_LD2_LD2 (0x00003000)
#define GPIO_PAR_LCDL_LD2_LD0 (0x00002000)
#define GPIO_PAR_LCDL_LD2_GPIO (0x00000000)
-#define GPIO_PAR_LCDL_LD1_MASK (0xFFFFF3FF)
+#define GPIO_PAR_LCDL_LD1_UNMASK (0xFFFFF3FF)
#define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00)
#define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800)
#define GPIO_PAR_LCDL_LD1_GPIO (0x00000000)
-#define GPIO_PAR_LCDL_LD0_MASK (0xFFFFFCFF)
+#define GPIO_PAR_LCDL_LD0_UNMASK (0xFFFFFCFF)
#define GPIO_PAR_LCDL_LD0_LD0 (0x00000300)
#define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200)
#define GPIO_PAR_LCDL_LD0_GPIO (0x00000000)
/* Bit definitions and macros for MSCR_FB */
-#define GPIO_MSCR_FB_DUPPER_MASK (0xCF)
+#define GPIO_MSCR_FB_DUPPER_UNMASK (0xCF)
#define GPIO_MSCR_FB_DUPPER_25V_33V (0x30)
#define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20)
#define GPIO_MSCR_FB_DUPPER_OD (0x10)
#define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00)
-#define GPIO_MSCR_FB_DLOWER_MASK (0xF3)
+#define GPIO_MSCR_FB_DLOWER_UNMASK (0xF3)
#define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C)
#define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08)
#define GPIO_MSCR_FB_DLOWER_OD (0x04)
#define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00)
-#define GPIO_MSCR_FB_ADDRCTL_MASK (0xFC)
+#define GPIO_MSCR_FB_ADDRCTL_UNMASK (0xFC)
#define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03)
#define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02)
#define GPIO_MSCR_FB_ADDRCTL_OD (0x01)
#define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00)
/* Bit definitions and macros for MSCR_SDRAM */
-#define GPIO_MSCR_SDRAM_SDCLKB_MASK (0xCF)
+#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK (0xCF)
#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30)
#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20)
#define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10)
#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00)
-#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3)
+#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3)
#define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C)
#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08)
#define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04)
#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00)
-#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC)
+#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC)
#define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03)
#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02)
#define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01)
#define CCM_RCON_MODE (0x0001)
/* Bit definitions and macros for CCM_CIR */
-#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
-#define CCM_CIR_PRN(x) ((x)&0x003F)
+#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
+#define CCM_CIR_PRN(x) ((x) & 0x003F)
/*********************************************************************
* PLL Clock Module
#define CCM_MISCCR_PLL_LOCK (0x2000)
#define CCM_MISCCR_LIMP (0x1000)
#define CCM_MISCCR_BME (0x8000)
-#define CCM_MISCCR_BMT_MASK (0xF8FF)
+#define CCM_MISCCR_BMT_UNMASK (0xF8FF)
#define CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8)
#define CCM_MISCCR_BMT_512 (0x0700)
#define CCM_MISCCR_BMT_1024 (0x0600)
#define GPIO_PAR_CS5 (0x40)
#define GPIO_PAR_CS4 (0x10)
-#define GPIO_PAR_CS1_MASK (0xF3)
+#define GPIO_PAR_CS1_UNMASK (0xF3)
#define GPIO_PAR_CS1_CS1 (0x0C)
#define GPIO_PAR_CS1_SDCS1 (0x08)
-#define GPIO_PAR_CS0_MASK (0xFC)
+#define GPIO_PAR_CS0_UNMASK (0xFC)
#define GPIO_PAR_CS0_CS0 (0x03)
#define GPIO_PAR_CS0_CS4 (0x02)
-#define GPIO_PAR_DSPIH_SIN_MASK (0x3F)
+#define GPIO_PAR_DSPIH_SIN_UNMASK (0x3F)
#define GPIO_PAR_DSPIH_SIN (0xC0)
#define GPIO_PAR_DSPIH_SIN_U2RXD (0x80)
-#define GPIO_PAR_DSPIH_SOUT_MASK (0xCF)
+#define GPIO_PAR_DSPIH_SOUT_UNMASK (0xCF)
#define GPIO_PAR_DSPIH_SOUT (0x30)
#define GPIO_PAR_DSPIH_SOUT_U2TXD (0x20)
-#define GPIO_PAR_DSPIH_SCK_MASK (0xF3)
+#define GPIO_PAR_DSPIH_SCK_UNMASK (0xF3)
#define GPIO_PAR_DSPIH_SCK (0x0C)
#define GPIO_PAR_DSPIH_SCK_U2CTS (0x08)
-#define GPIO_PAR_DSPIH_PCS0_MASK (0xFC)
+#define GPIO_PAR_DSPIH_PCS0_UNMASK (0xFC)
#define GPIO_PAR_DSPIH_PCS0 (0x03)
#define GPIO_PAR_DSPIH_PCS0_U2RTS (0x02)
-#define GPIO_PAR_DSPIL_PCS1_MASK (0x3F)
+#define GPIO_PAR_DSPIL_PCS1_UNMASK (0x3F)
#define GPIO_PAR_DSPIL_PCS1 (0xC0)
-#define GPIO_PAR_DSPIL_PCS2_MASK (0xCF)
+#define GPIO_PAR_DSPIL_PCS2_UNMASK (0xCF)
#define GPIO_PAR_DSPIL_PCS2 (0x30)
#define GPIO_PAR_DSPIL_PCS2_USBH_OC (0x20)
-#define GPIO_PAR_DSPIL_PCS3_MASK (0xF3)
+#define GPIO_PAR_DSPIL_PCS3_UNMASK (0xF3)
#define GPIO_PAR_DSPIL_PCS3 (0x0C)
#define GPIO_PAR_DSPIL_PCS3_USBH_EN (0x08)
#define GPIO_PAR_FEC0_RMII_FEC (0x01)
/* GPIO_PAR_FECI2C */
-#define GPIO_PAR_FECI2C_RMII0_MASK (0x3F)
+#define GPIO_PAR_FECI2C_RMII0_UNMASK (0x3F)
#define GPIO_PAR_FECI2C_MDC0 (0x80)
#define GPIO_PAR_FECI2C_MDIO0 (0x40)
-#define GPIO_PAR_FECI2C_RMII1_MASK (0xCF)
+#define GPIO_PAR_FECI2C_RMII1_UNMASK (0xCF)
#define GPIO_PAR_FECI2C_MDC1 (0x20)
#define GPIO_PAR_FECI2C_MDIO1 (0x10)
-#define GPIO_PAR_FECI2C_SDA_MASK (0xF3)
+#define GPIO_PAR_FECI2C_SDA_UNMASK (0xF3)
#define GPIO_PAR_FECI2C_SDA(x) (((x) & 0x03) << 2)
#define GPIO_PAR_FECI2C_SDA_SDA (0x0C)
#define GPIO_PAR_FECI2C_SDA_U2TXD (0x08)
#define GPIO_PAR_FECI2C_SDA_MDIO1 (0x04)
-#define GPIO_PAR_FECI2C_SCL_MASK (0xFC)
+#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFC)
#define GPIO_PAR_FECI2C_SCL(x) ((x) & 0x03)
#define GPIO_PAR_FECI2C_SCL_SCL (0x03)
#define GPIO_PAR_FECI2C_SCL_U2RXD (0x02)
#define GPIO_PAR_FECI2C_SCL_MDC1 (0x01)
-#define GPIO_PAR_IRQ0H_IRQ07_MASK (0x3F)
-#define GPIO_PAR_IRQ0H_IRQ06_MASK (0xCF)
+#define GPIO_PAR_IRQ0H_IRQ07_UNMASK (0x3F)
+#define GPIO_PAR_IRQ0H_IRQ06_UNMASK (0xCF)
#define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN (0x10)
-#define GPIO_PAR_IRQ0H_IRQ04_MASK (0xFC)
+#define GPIO_PAR_IRQ0H_IRQ04_UNMASK (0xFC)
#define GPIO_PAR_IRQ0H_IRQ04_DREQ0 (0x02)
-#define GPIO_PAR_IRQ0L_IRQ01_MASK (0xF3)
+#define GPIO_PAR_IRQ0L_IRQ01_UNMASK (0xF3)
#define GPIO_PAR_IRQ0L_IRQ01_DREQ1 (0x08)
#define GPIO_PAR_IRQ1H_IRQ17_DDATA3 (0x40)
#define GPIO_PAR_IRQ1L_IRQ11_PST1 (0x04)
#define GPIO_PAR_IRQ1L_IRQ10_PST0 (0x01)
-#define GPIO_PAR_SIMP1H_DATA1_MASK (0x3F)
+#define GPIO_PAR_SIMP1H_DATA1_UNMASK (0x3F)
#define GPIO_PAR_SIMP1H_DATA1_SIMDATA1 (0xC0)
#define GPIO_PAR_SIMP1H_DATA1_SSITXD (0x80)
#define GPIO_PAR_SIMP1H_DATA1_U1TXD (0x40)
-#define GPIO_PAR_SIMP1H_VEN1_MASK (0xCF)
+#define GPIO_PAR_SIMP1H_VEN1_UNMASK (0xCF)
#define GPIO_PAR_SIMP1H_VEN1_SIMVEN1 (0x30)
#define GPIO_PAR_SIMP1H_VEN1_SSIRXD (0x20)
#define GPIO_PAR_SIMP1H_VEN1_U1RXD (0x10)
-#define GPIO_PAR_SIMP1H_RST1_MASK (0xF3)
+#define GPIO_PAR_SIMP1H_RST1_UNMASK (0xF3)
#define GPIO_PAR_SIMP1H_RST1_SIMRST1 (0x0C)
#define GPIO_PAR_SIMP1H_RST1_SSIFS (0x08)
#define GPIO_PAR_SIMP1H_RST1_U1RTS (0x04)
-#define GPIO_PAR_SIMP1H_PD1_MASK (0xFC)
+#define GPIO_PAR_SIMP1H_PD1_UNMASK (0xFC)
#define GPIO_PAR_SIMP1H_PD1_SIMPD1 (0x03)
#define GPIO_PAR_SIMP1H_PD1_SSIBCLK (0x02)
#define GPIO_PAR_SIMP1H_PD1_U1CTS (0x01)
-#define GPIO_PAR_SIMP1L_CLK_MASK (0x3F)
+#define GPIO_PAR_SIMP1L_CLK_UNMASK (0x3F)
#define GPIO_PAR_SIMP1L_CLK_CLK1 (0xC0)
#define GPIO_PAR_SIMP1L_CLK_SSIMCLK (0x80)
#define GPIO_PAR_TIN2(x) (((x) & 0x03) << 4)
#define GPIO_PAR_TIN1(x) (((x) & 0x03) << 2)
#define GPIO_PAR_TIN0(x) ((x) & 0x03)
-#define GPIO_PAR_TIN3_MASK (0x3F)
+#define GPIO_PAR_TIN3_UNMASK (0x3F)
#define GPIO_PAR_TIN3_TIN3 (0xC0)
#define GPIO_PAR_TIN3_TOUT3 (0x80)
#define GPIO_PAR_TIN3_IRQ03 (0x40)
-#define GPIO_PAR_TIN2_MASK (0xCF)
+#define GPIO_PAR_TIN2_UNMASK (0xCF)
#define GPIO_PAR_TIN2_TIN2 (0x30)
#define GPIO_PAR_TIN2_TOUT2 (0x20)
#define GPIO_PAR_TIN2_IRQ02 (0x10)
-#define GPIO_PAR_TIN1_MASK (0xF3)
+#define GPIO_PAR_TIN1_UNMASK (0xF3)
#define GPIO_PAR_TIN1_TIN1 (0x0C)
#define GPIO_PAR_TIN1_TOUT1 (0x08)
#define GPIO_PAR_TIN1_DACK1 (0x04)
-#define GPIO_PAR_TIN0_MASK (0xFC)
+#define GPIO_PAR_TIN0_UNMASK (0xFC)
#define GPIO_PAR_TIN0_TIN0 (0x03)
#define GPIO_PAR_TIN0_TOUT0 (0x02)
#define GPIO_PAR_TIN0_CODEC_ALTCLK (0x01)
#define GPIO_PAR_UART_U0RXD (0x10)
#define GPIO_PAR_UART_RTS0(x) (((x) & 0x03) << 2)
#define GPIO_PAR_UART_CTS0(x) ((x) & 0x03)
-#define GPIO_PAR_UART_RTS0_MASK (0xF3)
+#define GPIO_PAR_UART_RTS0_UNMASK (0xF3)
#define GPIO_PAR_UART_RTS0_U0RTS (0x0C)
#define GPIO_PAR_UART_RTS0_USBO_VBOC (0x08)
-#define GPIO_PAR_UART_CTS0_MASK (0xFC)
+#define GPIO_PAR_UART_CTS0_UNMASK (0xFC)
#define GPIO_PAR_UART_CTS0_U0CTS (0x03)
#define GPIO_PAR_UART_CTS0_USB0_VBEN (0x02)
#define GPIO_PAR_UART_CTS0_USB_PULLUP (0x01)
#define GPIO_PAR_SSIH_TXD(x) (((x) & 0x03) << 4)
#define GPIO_PAR_SSIH_FS(x) (((x) & 0x03) << 2)
#define GPIO_PAR_SSIH_MCLK(x) ((x) & 0x03)
-#define GPIO_PAR_SSIH_RXD_MASK (0x3F)
+#define GPIO_PAR_SSIH_RXD_UNMASK (0x3F)
#define GPIO_PAR_SSIH_RXD_SSIRXD (0xC0)
#define GPIO_PAR_SSIH_RXD_U1RXD (0x40)
-#define GPIO_PAR_SSIH_TXD_MASK (0xCF)
+#define GPIO_PAR_SSIH_TXD_UNMASK (0xCF)
#define GPIO_PAR_SSIH_TXD_SSIRXD (0x30)
#define GPIO_PAR_SSIH_TXD_U1TXD (0x10)
-#define GPIO_PAR_SSIH_FS_MASK (0xF3)
+#define GPIO_PAR_SSIH_FS_UNMASK (0xF3)
#define GPIO_PAR_SSIH_FS_SSIFS (0x0C)
#define GPIO_PAR_SSIH_FS_U1RTS (0x04)
-#define GPIO_PAR_SSIH_MCLK_MASK (0xFC)
+#define GPIO_PAR_SSIH_MCLK_UNMASK (0xFC)
#define GPIO_PAR_SSIH_MCLK_SSIMCLK (0x03)
#define GPIO_PAR_SSIH_MCLK_SSICLKIN (0x01)
-#define GPIO_PAR_SSIL_MASK (0x3F)
+#define GPIO_PAR_SSIL_UNMASK (0x3F)
#define GPIO_PAR_SSIL_BCLK (0xC0)
#define GPIO_PAR_SSIL_U1CTS (0x40)
#define GPIO_MSCR_MSCR2(x) (((x) & 0x07) << 5)
#define GPIO_MSCR_MSCR3(x) (((x) & 0x07) << 5)
#define GPIO_MSCR_MSCR4(x) (((x) & 0x07) << 5)
-#define GPIO_MSCR_MSCRn_MASK (0x1F)
+#define GPIO_MSCR_MSCRn_UNMASK (0x1F)
#define GPIO_MSCR_MSCRn_SDR (0xE0)
#define GPIO_MSCR_MSCRn_25VDDR (0x60)
#define GPIO_MSCR_MSCRn_18VDDR_FULL (0x20)
#define GPIO_MSCR_MSCRn_18VDDR_HALF (0x00)
#define GPIO_MSCR_MSCR5(x) (((x) & 0x07) << 2)
-#define GPIO_MSCR_MSCR5_MASK (0xE3)
+#define GPIO_MSCR_MSCR5_UNMASK (0xE3)
#define GPIO_MSCR_MSCR5_SDR (0x1C)
#define GPIO_MSCR_MSCR5_25VDDR (0x0C)
#define GPIO_MSCR_MSCR5_18VDDR_FULL (0x04)
#define GPIO_MSCR_MSCR5_18VDDR_HALF (0x00)
-#define GPIO_SRCR_DSPI_MASK (0xFC)
+#define GPIO_SRCR_DSPI_UNMASK (0xFC)
#define GPIO_SRCR_DSPI(x) ((x) & 0x03)
-#define GPIO_SRCR_I2C_MASK (0xFC)
+#define GPIO_SRCR_I2C_UNMASK (0xFC)
#define GPIO_SRCR_I2C(x) ((x) & 0x03)
-#define GPIO_SRCR_IRQ_IRQ0_MASK (0xF3)
+#define GPIO_SRCR_IRQ_IRQ0_UNMASK (0xF3)
#define GPIO_SRCR_IRQ_IRQ0(x) (((x) & 0x03) << 2)
-#define GPIO_SRCR_IRQ_IRQ1DBG_MASK (0xFC)
+#define GPIO_SRCR_IRQ_IRQ1DBG_UNMASK (0xFC)
#define GPIO_SRCR_IRQ_IRQ1DBG(x) ((x) & 0x03)
-#define GPIO_SRCR_SIM_SIMP0_MASK (0xF3)
+#define GPIO_SRCR_SIM_SIMP0_UNMASK (0xF3)
#define GPIO_SRCR_SIM_SIMP0(x) (((x) & 0x03) << 2)
-#define GPIO_SRCR_SIM_SIMP1_MASK (0xFC)
+#define GPIO_SRCR_SIM_SIMP1_UNMASK (0xFC)
#define GPIO_SRCR_SIM_SIMP1(x) ((x) & 0x03)
-#define GPIO_SRCR_TIMER_MASK (0xFC)
+#define GPIO_SRCR_TIMER_UNMASK (0xFC)
#define GPIO_SRCR_TIMER(x) ((x) & 0x03)
-#define GPIO_SRCR_UART2_MASK (0xF3)
+#define GPIO_SRCR_UART2_UNMASK (0xF3)
#define GPIO_SRCR_UART2(x) (((x) & 0x03) << 2)
-#define GPIO_SRCR_UART0_MASK (0xFC)
+#define GPIO_SRCR_UART0_UNMASK (0xFC)
#define GPIO_SRCR_UART0(x) ((x) & 0x03)
-#define GPIO_SRCR_SDHC_MASK (0xFC)
+#define GPIO_SRCR_SDHC_UNMASK (0xFC)
#define GPIO_SRCR_SDHC(x) ((x) & 0x03)
-#define GPIO_SRCR_SSI_MASK (0xFC)
+#define GPIO_SRCR_SSI_UNMASK (0xFC)
#define GPIO_SRCR_SSI(x) ((x) & 0x03)
#define SRCR_HIGHEST (0x03)
#define SRCR_LOW (0x01)
#define SRCR_LOWEST (0x00)
-#define GPIO_DSCR_FEC_RMIICLK_MASK (0xCF)
+#define GPIO_DSCR_FEC_RMIICLK_UNMASK (0xCF)
#define GPIO_DSCR_FEC_RMIICLK(x) (((x) & 0x03) << 4)
-#define GPIO_DSCR_FEC_RMII0_MASK (0xF3)
+#define GPIO_DSCR_FEC_RMII0_UNMASK (0xF3)
#define GPIO_DSCR_FEC_RMII0(x) (((x) & 0x03) << 2)
-#define GPIO_DSCR_FEC_RMII1_MASK (0xFC)
+#define GPIO_DSCR_FEC_RMII1_UNMASK (0xFC)
#define GPIO_DSCR_FEC_RMII1(x) ((x) & 0x03)
#define DSCR_50PF (0x03)
#define PLL_PCR_LOL_IRQ (0x00004000)
#define PLL_PCR_LOL_RE (0x00002000)
#define PLL_PCR_LOL_EN (0x00001000)
-#define PLL_PCR_REFDIV_MASK (0xFFFFF8FF)
+#define PLL_PCR_REFDIV_UNMASK (0xFFFFF8FF)
#define PLL_PCR_REFDIV(x) (((x) & 0x07) << 8)
-#define PLL_PCR_FBDIV_MASK (0xFFFFFFC0)
+#define PLL_PCR_FBDIV_UNMASK (0xFFFFFFC0)
#define PLL_PCR_FBDIV(x) ((x) & 0x3F)
-#define PLL_PDR_OUTDIV4_MASK (0x0FFF)
+#define PLL_PDR_OUTDIV4_UNMASK (0x0FFF)
#define PLL_PDR_OUTDIV4(x) (((x) & 0x0000000F) << 12)
-#define PLL_PDR_OUTDIV3_MASK (0xF0FF)
+#define PLL_PDR_OUTDIV3_UNMASK (0xF0FF)
#define PLL_PDR_OUTDIV3(x) (((x) & 0x0000000F) << 8)
-#define PLL_PDR_OUTDIV2_MASK (0xFF0F)
+#define PLL_PDR_OUTDIV2_UNMASK (0xFF0F)
#define PLL_PDR_OUTDIV2(x) (((x) & 0x0000000F) << 4)
-#define PLL_PDR_OUTDIV1_MASK (0xFFF0)
+#define PLL_PDR_OUTDIV1_UNMASK (0xFFF0)
#define PLL_PDR_OUTDIV1(x) ((x) & 0x0000000F)
#define PLL_PDR_USB(x) PLL_PDR_OUTDIV4(x)
#define PLL_PDR_SDRAM(x) PLL_PDR_OUTDIV3(x)
/* Bit definitions and macros for PAR_FEC */
#define GPIO_PAR_FEC_FEC0(x) (((x)&0x07))
#define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4)
-#define GPIO_PAR_FEC_FEC1_MASK (0x8F)
+#define GPIO_PAR_FEC_FEC1_UNMASK (0x8F)
#define GPIO_PAR_FEC_FEC1_MII (0x70)
#define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30)
#define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20)
#define GPIO_PAR_FEC_FEC1_ATA (0x10)
#define GPIO_PAR_FEC_FEC1_GPIO (0x00)
-#define GPIO_PAR_FEC_FEC0_MASK (0xF8)
+#define GPIO_PAR_FEC_FEC0_UNMASK (0xF8)
#define GPIO_PAR_FEC_FEC0_MII (0x07)
#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
#define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02)
#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2)
#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4)
#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
-#define GPIO_PAR_DMA_DACK1_MASK (0x3F)
+#define GPIO_PAR_DMA_DACK1_UNMASK (0x3F)
#define GPIO_PAR_DMA_DACK1_DACK1 (0xC0)
#define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40)
#define GPIO_PAR_DMA_DACK1_GPIO (0x00)
-#define GPIO_PAR_DMA_DREQ1_MASK (0xCF)
+#define GPIO_PAR_DMA_DREQ1_UNMASK (0xCF)
#define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30)
#define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10)
#define GPIO_PAR_DMA_DREQ1_GPIO (0x00)
-#define GPIO_PAR_DMA_DACK0_MASK (0xF3)
+#define GPIO_PAR_DMA_DACK0_UNMASK (0xF3)
#define GPIO_PAR_DMA_DACK0_DACK1 (0x0C)
#define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04)
#define GPIO_PAR_DMA_DACK0_GPIO (0x00)
#define GPIO_PAR_FBCTL_TA_GPIO (0x00)
#define GPIO_PAR_FBCTL_RW_RW (0x20)
#define GPIO_PAR_FBCTL_RW_GPIO (0x00)
-#define GPIO_PAR_FBCTL_TS_MASK (0xE7)
+#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7)
#define GPIO_PAR_FBCTL_TS_TS (0x18)
#define GPIO_PAR_FBCTL_TS_ALE (0x10)
#define GPIO_PAR_FBCTL_TS_TBST (0x08)
#define GPIO_PAR_BE_BS1 (0x04)
#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
-#define GPIO_PAR_BE_BE3_MASK (0x3F)
+#define GPIO_PAR_BE_BE3_UNMASK (0x3F)
#define GPIO_PAR_BE_BE3_BE3 (0xC0)
#define GPIO_PAR_BE_BE3_TSIZ1 (0x80)
#define GPIO_PAR_BE_BE3_GPIO (0x00)
-#define GPIO_PAR_BE_BE2_MASK (0xCF)
+#define GPIO_PAR_BE_BE2_UNMASK (0xCF)
#define GPIO_PAR_BE_BE2_BE2 (0x30)
#define GPIO_PAR_BE_BE2_TSIZ0 (0x20)
#define GPIO_PAR_BE_BE2_GPIO (0x00)
#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
-#define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
+#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F)
#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
#define GPIO_PAR_TIMER_T3IN_U2RXD (0x40)
#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
+#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF)
#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
#define GPIO_PAR_TIMER_T2IN_U2TXD (0x10)
#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
+#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3)
#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
#define GPIO_PAR_TIMER_T1IN_U2CTS (0x04)
#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
+#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC)
#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
#define GPIO_PAR_TIMER_T0IN_U2RTS (0x01)
/* Bit definitions and macros for PAR_USB */
#define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03))
#define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2)
-#define GPIO_PAR_USB_VBUSEN_MASK (0xF3)
+#define GPIO_PAR_USB_VBUSEN_UNMASK (0xF3)
#define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C)
#define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08)
#define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04)
#define GPIO_PAR_USB_VBUSEN_GPIO (0x00)
-#define GPIO_PAR_USB_VBUSOC_MASK (0xFC)
+#define GPIO_PAR_USB_VBUSOC_UNMASK (0xFC)
#define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03)
#define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01)
#define GPIO_PAR_USB_VBUSOC_GPIO (0x00)
#define GPIO_PAR_FECI2C_MDC0 (0x0040)
#define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8)
#define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10)
-#define GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF)
+#define GPIO_PAR_FECI2C_MDC1_UNMASK (0xF3FF)
#define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00)
#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800)
#define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000)
-#define GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF)
+#define GPIO_PAR_FECI2C_MDIO1_UNMASK (0xFCFF)
#define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300)
#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200)
#define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000)
#define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000)
#define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010)
#define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000)
-#define GPIO_PAR_FECI2C_SCL_MASK (0xFFF3)
+#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFFF3)
#define GPIO_PAR_FECI2C_SCL_SCL (0x000C)
#define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004)
#define GPIO_PAR_FECI2C_SCL_GPIO (0x0000)
-#define GPIO_PAR_FECI2C_SDA_MASK (0xFFFC)
+#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFFFC)
#define GPIO_PAR_FECI2C_SDA_SDA (0x0003)
#define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001)
#define GPIO_PAR_FECI2C_SDA_GPIO (0x0000)
#define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4)
#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6)
#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8)
-#define GPIO_PAR_SSI_BCLK_MASK (0xFCFF)
+#define GPIO_PAR_SSI_BCLK_UNMASK (0xFCFF)
#define GPIO_PAR_SSI_BCLK_BCLK (0x0300)
#define GPIO_PAR_SSI_BCLK_U1CTS (0x0200)
#define GPIO_PAR_SSI_BCLK_GPIO (0x0000)
-#define GPIO_PAR_SSI_FS_MASK (0xFF3F)
+#define GPIO_PAR_SSI_FS_UNMASK (0xFF3F)
#define GPIO_PAR_SSI_FS_FS (0x00C0)
#define GPIO_PAR_SSI_FS_U1RTS (0x0080)
#define GPIO_PAR_SSI_FS_GPIO (0x0000)
-#define GPIO_PAR_SSI_SRXD_MASK (0xFFCF)
+#define GPIO_PAR_SSI_SRXD_UNMASK (0xFFCF)
#define GPIO_PAR_SSI_SRXD_SRXD (0x0030)
#define GPIO_PAR_SSI_SRXD_U1RXD (0x0020)
#define GPIO_PAR_SSI_SRXD_GPIO (0x0000)
-#define GPIO_PAR_SSI_STXD_MASK (0xFFF3)
+#define GPIO_PAR_SSI_STXD_UNMASK (0xFFF3)
#define GPIO_PAR_SSI_STXD_STXD (0x000C)
#define GPIO_PAR_SSI_STXD_U1TXD (0x0008)
#define GPIO_PAR_SSI_STXD_GPIO (0x0000)
#define GPIO_PAR_PCI_GNT1 (0x0400)
#define GPIO_PAR_PCI_GNT2 (0x1000)
#define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14)
-#define GPIO_PAR_PCI_GNT3_MASK (0x3FFF)
+#define GPIO_PAR_PCI_GNT3_UNMASK (0x3FFF)
#define GPIO_PAR_PCI_GNT3_GNT3 (0xC000)
#define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000)
#define GPIO_PAR_PCI_GNT3_GPIO (0x0000)
#define GPIO_PAR_PCI_GNT1_GPIO (0x0000)
#define GPIO_PAR_PCI_GNT0_GNT0 (0x0100)
#define GPIO_PAR_PCI_GNT0_GPIO (0x0000)
-#define GPIO_PAR_PCI_REQ3_MASK (0xFF3F)
+#define GPIO_PAR_PCI_REQ3_UNMASK (0xFF3F)
#define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0)
#define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080)
#define GPIO_PAR_PCI_REQ3_GPIO (0x0000)
#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
#define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4)
#define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6)
-#define GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F)
+#define GPIO_MSCR_SDRAM_SDDATA_UNMASK (0x3F)
#define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0)
#define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80)
#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40)
#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00)
-#define GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF)
+#define GPIO_MSCR_SDRAM_SDDQS_UNMASK (0xCF)
#define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30)
#define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20)
#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10)
#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00)
-#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3)
+#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3)
#define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C)
#define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08)
#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04)
#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00)
-#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC)
+#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC)
#define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03)
#define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02)
#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01)
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/cache.h>
+
+volatile int *cf_icache_status = (int *)ICACHE_STATUS;
+volatile int *cf_dcache_status = (int *)DCACHE_STATUS;
+
+void flush_cache(ulong start_addr, ulong size)
+{
+ /* Must be implemented for all M68k processors with copy-back data cache */
+}
+
+int icache_status(void)
+{
+ return *cf_icache_status;
+}
+
+int dcache_status(void)
+{
+ return *cf_dcache_status;
+}
+
+void icache_enable(void)
+{
+ icache_invalid();
+
+ *cf_icache_status = 1;
+
+#ifdef CONFIG_CF_V4
+ __asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2));
+ __asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
+#elif defined(CONFIG_CF_V4e)
+ __asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
+ __asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
+#else
+ __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
+ __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
+#endif
+
+ __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR));
+}
+
+void icache_disable(void)
+{
+ u32 temp = 0;
+
+ *cf_icache_status = 0;
+ icache_invalid();
+
+#ifdef CONFIG_CF_V4
+ __asm__ __volatile__("movec %0, %%acr2"::"r"(temp));
+ __asm__ __volatile__("movec %0, %%acr3"::"r"(temp));
+#elif defined(CONFIG_CF_V4e)
+ __asm__ __volatile__("movec %0, %%acr6"::"r"(temp));
+ __asm__ __volatile__("movec %0, %%acr7"::"r"(temp));
+#else
+ __asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
+ __asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
+
+#endif
+}
+
+void icache_invalid(void)
+{
+ u32 temp;
+
+ temp = CONFIG_SYS_ICACHE_INV;
+ if (*cf_icache_status)
+ temp |= CONFIG_SYS_CACHE_ICACR;
+
+ __asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
+}
+
+/*
+ * data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x
+ * the dcache will be dummy in ColdFire V2 and V3
+ */
+void dcache_enable(void)
+{
+ dcache_invalid();
+ *cf_dcache_status = 1;
+
+#ifdef CONFIG_CF_V4
+ __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
+ __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
+#elif defined(CONFIG_CF_V4e)
+ __asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
+ __asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
+
+#endif
+
+ __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR));
+}
+
+void dcache_disable(void)
+{
+ u32 temp = 0;
+
+ *cf_dcache_status = 0;
+ dcache_invalid();
+
+ __asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
+
+#ifdef CONFIG_CF_V4
+ __asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
+ __asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
+#elif defined(CONFIG_CF_V4e)
+ __asm__ __volatile__("movec %0, %%acr4"::"r"(temp));
+ __asm__ __volatile__("movec %0, %%acr5"::"r"(temp));
+
+#endif
+}
+
+void dcache_invalid(void)
+{
+#ifdef CONFIG_CF_V4
+ u32 temp;
+
+ temp = CONFIG_SYS_DCACHE_INV;
+ if (*cf_dcache_status)
+ temp |= CONFIG_SYS_CACHE_DCACR;
+ if (*cf_icache_status)
+ temp |= CONFIG_SYS_CACHE_ICACR;
+
+ __asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
+#endif
+}
START = start.o
SOBJS = exceptions.o
-COBJS = cpu.o interrupts.o serial.o sysid.o traps.o epcs.o
+COBJS = cpu.o interrupts.o sysid.o traps.o epcs.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
if (assert) {
tmp = readl (&epcs->control);
- writel (&epcs->control, tmp | NIOS_SPI_SSO);
+ writel (tmp | NIOS_SPI_SSO, &epcs->control);
} else {
/* Let all bits shift out */
start = get_timer (0);
if (get_timer (start) > EPCS_TIMEOUT)
return (-1);
tmp = readl (&epcs->control);
- writel (&epcs->control, tmp & ~NIOS_SPI_SSO);
+ writel (tmp & ~NIOS_SPI_SSO, &epcs->control);
}
return (0);
}
while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0)
if (get_timer (start) > EPCS_TIMEOUT)
return (-1);
- writel (&epcs->txdata, c);
+ writel (c, &epcs->txdata);
return (0);
}
static struct epcs_devinfo_t devinfo[] = {
{ "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c },
{ "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c },
+ { "EPCS16", 0x14, 21, 32, 16, 8, 0x1c },
+ { "EPCS64", 0x16, 23,128, 16, 8, 0x1c },
{ 0, 0, 0, 0, 0, 0 }
};
}
/* Sector info */
- for (i=0; i<dev->num_sects; i++) {
+ for (i=0; (i < dev->num_sects) && (argc > 1); i++) {
erased = epcs_sect_erased (i, &tmp, dev);
- printf (" %d: %06x ",
+ if ((i & 0x03) == 0) printf ("\n");
+ printf ("%4d: %07x ",
i, i*(1<<dev->sz_sect) );
if (erased)
- printf ("erased\n");
+ printf ("E ");
else
- printf ("data @ 0x%06x\n", tmp);
+ printf (" ");
}
+ printf ("\n");
return;
}
void reset_timer (void)
{
+ nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
+
+ /* From Embedded Peripherals Handbook:
+ *
+ * "When the hardware is configured with Writeable period
+ * disabled, writing to one of the period_n registers causes
+ * the counter to reset to the fixed Timeout Period specified
+ * at system generation time."
+ *
+ * Here we force a reload to prevent early timeouts from
+ * get_timer() when the interrupt period is greater than
+ * than 1 msec.
+ *
+ * Simply write to periodl with its own value to force an
+ * internal counter reload, THEN reset the timestamp.
+ */
+ writel (readl (&tmr->periodl), &tmr->periodl);
timestamp = 0;
+
+ /* From Embedded Peripherals Handbook:
+ *
+ * "Writing to one of the period_n registers stops the internal
+ * counter, except when the hardware is configured with Start/Stop
+ * control bits off. If Start/Stop control bits is off, writing
+ * either register does not stop the counter."
+ *
+ * In order to accomodate either configuration, the control
+ * register is re-written. If the counter is stopped, it will
+ * be restarted. If it is running, the write is essentially
+ * a nop.
+ */
+ writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START,
+ &tmr->control);
+
}
ulong get_timer (ulong base)
/* Interrupt is cleared by writing anything to the
* status register.
*/
- writel (&tmr->status, 0);
+ writel (0, &tmr->status);
timestamp += CONFIG_SYS_NIOS_TMRMS;
#ifdef CONFIG_STATUS_LED
status_led_tick(timestamp);
{
nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
- writel (&tmr->status, 0);
- writel (&tmr->control, 0);
- writel (&tmr->control, NIOS_TIMER_STOP);
+ writel (0, &tmr->status);
+ writel (0, &tmr->control);
+ writel (NIOS_TIMER_STOP, &tmr->control);
#if defined(CONFIG_SYS_NIOS_TMRCNT)
- writel (&tmr->periodl, CONFIG_SYS_NIOS_TMRCNT & 0xffff);
- writel (&tmr->periodh, (CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff);
+ writel (CONFIG_SYS_NIOS_TMRCNT & 0xffff, &tmr->periodl);
+ writel ((CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff, &tmr->periodh);
#endif
- writel (&tmr->control, NIOS_TIMER_ITO | NIOS_TIMER_CONT |
- NIOS_TIMER_START );
+ writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START,
+ &tmr->control);
irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ, tmr_isr, (void *)tmr);
}
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#ifndef __ASM_NIOS2_SYSTEM_H_
-#define __ASM_NIOS2_SYSTEM_H_
-#endif /* __ASM_NIOS2_SYSTEM_H */
+#ifndef __ASM_NIOS2_BITOPS_H_
+#define __ASM_NIOS2_BITOPS_H_
+
+/* copied from linux-2.6/include/asm-generic/bitops */
+#include <asm/bitops/atomic.h>
+#include <asm/bitops/non-atomic.h>
+#include <asm/bitops/ffs.h>
+
+#endif /* __ASM_NIOS2_BITOPS_H */
--- /dev/null
+#ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_
+#define _ASM_GENERIC_BITOPS_ATOMIC_H_
+
+#include <asm/types.h>
+#include <asm/system.h>
+
+#ifdef CONFIG_SMP
+#include <asm/spinlock.h>
+#include <asm/cache.h> /* we use L1_CACHE_BYTES */
+
+/* Use an array of spinlocks for our atomic_ts.
+ * Hash function to index into a different SPINLOCK.
+ * Since "a" is usually an address, use one spinlock per cacheline.
+ */
+# define ATOMIC_HASH_SIZE 4
+# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
+
+extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
+
+/* Can't use raw_spin_lock_irq because of #include problems, so
+ * this is the substitute */
+#define _atomic_spin_lock_irqsave(l,f) do { \
+ raw_spinlock_t *s = ATOMIC_HASH(l); \
+ local_irq_save(f); \
+ __raw_spin_lock(s); \
+} while(0)
+
+#define _atomic_spin_unlock_irqrestore(l,f) do { \
+ raw_spinlock_t *s = ATOMIC_HASH(l); \
+ __raw_spin_unlock(s); \
+ local_irq_restore(f); \
+} while(0)
+
+
+#else
+# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
+# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
+#endif
+
+/*
+ * NMI events can occur at any time, including when interrupts have been
+ * disabled by *_irqsave(). So you can get NMI events occurring while a
+ * *_bit function is holding a spin lock. If the NMI handler also wants
+ * to do bit manipulation (and they do) then you can get a deadlock
+ * between the original caller of *_bit() and the NMI handler.
+ *
+ * by Keith Owens
+ */
+
+/**
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered. See __set_bit()
+ * if you do not require the atomic guarantees.
+ *
+ * Note: there are no guarantees that this function will not be reordered
+ * on non x86 architectures, so if you are writing portable code,
+ * make sure not to rely on its reordering guarantees.
+ *
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static inline void set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long flags;
+
+ _atomic_spin_lock_irqsave(p, flags);
+ *p |= mask;
+ _atomic_spin_unlock_irqrestore(p, flags);
+}
+
+/**
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered. However, it does
+ * not contain a memory barrier, so if it is used for locking purposes,
+ * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
+ * in order to ensure changes are visible on other processors.
+ */
+static inline void clear_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long flags;
+
+ _atomic_spin_lock_irqsave(p, flags);
+ *p &= ~mask;
+ _atomic_spin_unlock_irqrestore(p, flags);
+}
+
+/**
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to change
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered. It may be
+ * reordered on other architectures than x86.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static inline void change_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long flags;
+
+ _atomic_spin_lock_irqsave(p, flags);
+ *p ^= mask;
+ _atomic_spin_unlock_irqrestore(p, flags);
+}
+
+/**
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It may be reordered on other architectures than x86.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old;
+ unsigned long flags;
+
+ _atomic_spin_lock_irqsave(p, flags);
+ old = *p;
+ *p = old | mask;
+ _atomic_spin_unlock_irqrestore(p, flags);
+
+ return (old & mask) != 0;
+}
+
+/**
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It can be reorderdered on other architectures other than x86.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old;
+ unsigned long flags;
+
+ _atomic_spin_lock_irqsave(p, flags);
+ old = *p;
+ *p = old & ~mask;
+ _atomic_spin_unlock_irqrestore(p, flags);
+
+ return (old & mask) != 0;
+}
+
+/**
+ * test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to change
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old;
+ unsigned long flags;
+
+ _atomic_spin_lock_irqsave(p, flags);
+ old = *p;
+ *p = old ^ mask;
+ _atomic_spin_unlock_irqrestore(p, flags);
+
+ return (old & mask) != 0;
+}
+
+#endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */
--- /dev/null
+#ifndef _ASM_GENERIC_BITOPS_FFS_H_
+#define _ASM_GENERIC_BITOPS_FFS_H_
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static inline int ffs(int x)
+{
+ int r = 1;
+
+ if (!x)
+ return 0;
+ if (!(x & 0xffff)) {
+ x >>= 16;
+ r += 16;
+ }
+ if (!(x & 0xff)) {
+ x >>= 8;
+ r += 8;
+ }
+ if (!(x & 0xf)) {
+ x >>= 4;
+ r += 4;
+ }
+ if (!(x & 3)) {
+ x >>= 2;
+ r += 2;
+ }
+ if (!(x & 1)) {
+ x >>= 1;
+ r += 1;
+ }
+ return r;
+}
+
+#endif /* _ASM_GENERIC_BITOPS_FFS_H_ */
--- /dev/null
+#ifndef _ASM_GENERIC_BITOPS_NON_ATOMIC_H_
+#define _ASM_GENERIC_BITOPS_NON_ATOMIC_H_
+
+#include <asm/types.h>
+
+/**
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void __set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+ *p |= mask;
+}
+
+static inline void __clear_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+ *p &= ~mask;
+}
+
+/**
+ * __change_bit - Toggle a bit in memory
+ * @nr: the bit to change
+ * @addr: the address to start counting from
+ *
+ * Unlike change_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void __change_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+ *p ^= mask;
+}
+
+/**
+ * __test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail. You must protect multiple accesses with a lock.
+ */
+static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old = *p;
+
+ *p = old | mask;
+ return (old & mask) != 0;
+}
+
+/**
+ * __test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail. You must protect multiple accesses with a lock.
+ */
+static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old = *p;
+
+ *p = old & ~mask;
+ return (old & mask) != 0;
+}
+
+/* WARNING: non atomic and it can be reordered! */
+static inline int __test_and_change_bit(int nr,
+ volatile unsigned long *addr)
+{
+ unsigned long mask = BIT_MASK(nr);
+ unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+ unsigned long old = *p;
+
+ *p = old ^ mask;
+ return (old & mask) != 0;
+}
+
+/**
+ * test_bit - Determine whether a bit is set
+ * @nr: bit number to test
+ * @addr: Address to start counting from
+ */
+static inline int test_bit(int nr, const volatile unsigned long *addr)
+{
+ return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
+}
+
+#endif /* _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ */
({unsigned long val;\
asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
-#define writeb(addr,val)\
- asm volatile ("stbio %1, 0(%0)" : : "r" (addr), "r" (val))
-#define writew(addr,val)\
- asm volatile ("sthio %1, 0(%0)" : : "r" (addr), "r" (val))
-#define writel(addr,val)\
- asm volatile ("stwio %1, 0(%0)" : : "r" (addr), "r" (val))
+#define writeb(val,addr)\
+ asm volatile ("stbio %0, 0(%1)" : : "r" (val), "r" (addr))
+#define writew(val,addr)\
+ asm volatile ("sthio %0, 0(%1)" : : "r" (val), "r" (addr))
+#define writel(val,addr)\
+ asm volatile ("stwio %0, 0(%1)" : : "r" (val), "r" (addr))
#define inb(addr) readb(addr)
#define inw(addr) readw(addr)
#define inl(addr) readl(addr)
-#define outb(addr,val) writeb(addr,val)
-#define outw(addr,val) writew(addr,val)
-#define outl(addr,val) writel(addr,val)
+#define outb(val, addr) writeb(val,addr)
+#define outw(val, addr) writew(val,addr)
+#define outl(val, addr) writel(val,addr)
static inline void insb (unsigned long port, void *dst, unsigned long count)
{
--- /dev/null
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_NIOS2_SYSTEM_H_
+#define __ASM_NIOS2_SYSTEM_H_
+
+#define local_irq_enable() __asm__ __volatile__ ( \
+ "rdctl r8, status\n" \
+ "ori r8, r8, 1\n" \
+ "wrctl status, r8\n" \
+ : : : "r8")
+
+#define local_irq_disable() __asm__ __volatile__ ( \
+ "rdctl r8, status\n" \
+ "andi r8, r8, 0xfffe\n" \
+ "wrctl status, r8\n" \
+ : : : "r8")
+
+#define local_save_flags(x) __asm__ __volatile__ ( \
+ "rdctl r8, status\n" \
+ "mov %0, r8\n" \
+ : "=r" (x) : : "r8", "memory")
+
+#define local_irq_restore(x) __asm__ __volatile__ ( \
+ "mov r8, %0\n" \
+ "wrctl status, r8\n" \
+ : : "r" (x) : "r8", "memory")
+
+/* For spinlocks etc */
+#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } \
+ while (0)
+
+#define irqs_disabled() \
+({ \
+ unsigned long flags; \
+ local_save_flags(flags); \
+ ((flags & NIOS2_STATUS_PIE_MSK) == 0x0); \
+})
+
+#endif /* __ASM_NIOS2_SYSTEM_H */
board_late_init ();
#endif
+#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
+ puts ("Net: ");
+#endif
+ eth_initialize (bd);
+#endif
+
/* main_loop */
for (;;) {
WATCHDOG_RESET ();
#include <asm/byteorder.h>
#include <asm/cache.h>
+#define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */
+
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
{
- void (*kernel)(void) = (void (*)(void))images->ep;
+ void (*kernel)(int, int, int, char *) = (void *)images->ep;
+ char *commandline = getenv("bootargs");
+ ulong initrd_start = images->rd_start;
+ ulong initrd_end = images->rd_end;
if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
return 1;
/* flushes data and instruction caches before calling the kernel */
- flush_dcache (0,CONFIG_SYS_DCACHE_SIZE);
- flush_icache (0,CONFIG_SYS_ICACHE_SIZE);
+ disable_interrupts();
+ flush_dcache((ulong)kernel, CONFIG_SYS_DCACHE_SIZE);
+ flush_icache((ulong)kernel, CONFIG_SYS_ICACHE_SIZE);
- /* For now we assume the Microtronix linux ... which only
- * needs to be called ;-)
- */
- kernel ();
+ debug("bootargs=%s @ 0x%lx\n", commandline, (ulong)&commandline);
+ debug("initrd=0x%lx-0x%lx\n", (ulong)initrd_start, (ulong)initrd_end);
+ kernel(NIOS_MAGIC, initrd_start, initrd_end, commandline);
/* does not return */
return 1;
COBJS-y += serial.o
COBJS-y += speed.o
COBJS-${CONFIG_FSL_DIU_FB} += diu.o
-COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_diu_fb.o
-COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_logo_bmp.o
+COBJS-${CONFIG_FSL_DIU_FB} += ../../../../board/freescale/common/fsl_diu_fb.o
+COBJS-${CONFIG_FSL_DIU_FB} += ../../../../board/freescale/common/fsl_logo_bmp.o
COBJS-${CONFIG_CMD_IDE} += ide.o
COBJS-${CONFIG_IIM} += iim.o
COBJS-$(CONFIG_PCI) += pci.o
/*
- * needed for cpu/mpc512x/start.S
+ * needed for arch/ppc/cpu/mpc512x/start.S
*
* These should be auto-generated
*/
# Use default linker script.
# A board port can override this setting in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc512x/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc512x/u-boot.lds
#include <command.h>
#include <asm/io.h>
-#include "../../board/freescale/common/pixis.h"
-#include "../../board/freescale/common/fsl_diu_fb.h"
+#include "../../../../board/freescale/common/fsl_diu_fb.h"
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
#include <stdio_dev.h>
.plt : { *(.plt) }
.text :
{
- cpu/mpc512x/start.o (.text)
+ arch/ppc/cpu/mpc512x/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
#
#
-# File: cpu/mpc5xx/Makefile
+# File: arch/ppc/cpu/mpc5xx/Makefile
#
# Discription: Makefile to build mpc5xx cpu configuration.
# Will include top config.mk which itselfs
-# uses the definitions made in cpu/mpc5xx/config.mk
+# uses the definitions made in arch/ppc/cpu/mpc5xx/config.mk
#
PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc5xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xx/u-boot.lds
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc5xx/start.o (.text)
+ arch/ppc/cpu/mpc5xx/start.o (.text)
*(.text)
*(.got1)
LIB = $(obj)lib$(CPU).a
START = start.o
-SOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
+SOBJS = io.o firmware_sc_task_bestcomm.impl.o
COBJS = i2c.o traps.o cpu.o cpu_init.o ide.o interrupts.o \
loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot.lds
{
ulong clock = gd->cpu_clk;
char buf[32];
-#ifndef CONFIG_MGT5100
uint svr, pvr;
-#endif
puts ("CPU: ");
-#ifdef CONFIG_MGT5100
- puts (CPU_ID_STR);
- printf (" (JTAG ID %08lx)", *(vu_long *)MPC5XXX_CDM_JTAGID);
-#else
svr = get_svr();
pvr = get_pvr();
printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),
PVR_MAJ(pvr), PVR_MIN(pvr));
-#endif
printf (" at %s MHz\n", strmhz (buf, clock));
return 0;
}
(struct mpc5xxx_gpt *) MPC5XXX_GPT;
#endif /* CONFIG_WATCHDOG */
unsigned long addecr = (1 << 25); /* Boot_CS */
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100)
- addecr |= (1 << 22); /* SDRAM enable */
-#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
#endif
-#if defined(CONFIG_MPC5200)
addecr |= 1;
#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
#if defined(CONFIG_SYS_CS_DEADCYCLE)
out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
#endif
-#endif /* CONFIG_MPC5200 */
/* Enable chip selects */
-#if defined(CONFIG_MGT5100)
- out_be32(&mm->addecr, addecr);
-#elif defined(CONFIG_MPC5200)
out_be32(&mm->ipbi_ws_ctrl, addecr);
-#endif
out_be32(&lpb->cs_ctrl, (1 << 24));
/* Setup pin multiplexing */
out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
#endif
-#if defined(CONFIG_MPC5200)
/* enable timebase */
setbits_be32(&xlb->config, (1 << 13));
setbits_be32(&xlb->config, (1 << 15));
out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);
-# if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
/* Motorola reports IPB should better run at 133 MHz. */
-# if defined(CONFIG_MGT5100)
- setbits_be32(&mm->addecr, 1);
-# elif defined(CONFIG_MPC5200)
setbits_be32(&mm->ipbi_ws_ctrl, 1);
-# endif
/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
addecr = in_be32(&cdm->cfg);
addecr &= ~0x103;
-# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
+# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
addecr |= 0x01;
-# else
+# else
/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
addecr |= 0x02;
-# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
+# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
out_be32(&cdm->cfg, addecr);
-# endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
+#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
/* Configure the XLB Arbiter */
out_be32(&xlb->master_pri_enable, 0xff);
out_be32(&xlb->master_priority, 0x11111111);
-# if defined(CONFIG_SYS_XLB_PIPELINING)
+#if defined(CONFIG_SYS_XLB_PIPELINING)
/* Enable piplining */
clrbits_be32(&xlb->config, (1 << 31));
-# endif
+#endif
#if defined(CONFIG_WATCHDOG)
/* Charge the watchdog timer - prescaler = 64k, count = 64k*/
reset_5xxx_watchdog();
#endif /* CONFIG_WATCHDOG */
-
-#endif /* CONFIG_MPC5200 */
}
/*
(struct mpc5xxx_intr *) MPC5XXX_ICTL;
/* mask all interrupts */
-#if defined(CONFIG_MGT5100)
- out_be32(&intr->per_mask, 0xfffffc00);
-#elif defined(CONFIG_MPC5200)
out_be32(&intr->per_mask, 0xffffff00);
-#endif
setbits_be32(&intr->main_mask, 0x0001ffff);
clrbits_be32(&intr->ctrl, 0x00000f00);
/* route critical ints to normal ints */
#include <config.h>
-#if defined(CONFIG_MPC5200)
-
/* sas/sccg, gas target */
.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */
.section smartdmaTaskTable,"aw",@progbits /* Task tables */
.globl scEthernetXmit_CSave
scEthernetXmit_CSave: /* Task 1 context save space */
.space 128, 0x0
-
-#endif /* CONFIG_MPC5200 */
#include <common.h>
-#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200)
+#if defined(CONFIG_PCI)
#include <asm/processor.h>
#include <asm/io.h>
hose->last_busno = pci_hose_scan(hose);
}
-#endif /* CONFIG_PCI && CONFIG_MPC5200 */
+#endif /* CONFIG_PCI */
#define PSC_BASE MPC5XXX_PSC2
#elif CONFIG_PSC_CONSOLE == 3
#define PSC_BASE MPC5XXX_PSC3
-#elif defined(CONFIG_MGT5100)
-#error CONFIG_PSC_CONSOLE must be in 1, 2 or 3
#elif CONFIG_PSC_CONSOLE == 4
#define PSC_BASE MPC5XXX_PSC4
#elif CONFIG_PSC_CONSOLE == 5
#define PSC_BASE2 MPC5XXX_PSC2
#elif CONFIG_PSC_CONSOLE2 == 3
#define PSC_BASE2 MPC5XXX_PSC3
-#elif defined(CONFIG_MGT5100)
-#error CONFIG_PSC_CONSOLE2 must be in 1, 2 or 3
#elif CONFIG_PSC_CONSOLE2 == 4
#define PSC_BASE2 MPC5XXX_PSC4
#elif CONFIG_PSC_CONSOLE2 == 5
psc->command = PSC_SEL_MODE_REG_1;
/* select clock sources */
-#if defined(CONFIG_MGT5100)
- psc->psc_clock_select = 0xdd00;
- baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32;
-#elif defined(CONFIG_MPC5200)
psc->psc_clock_select = 0;
baseclk = (gd->ipb_clk + 16) / 32;
-#endif
/* switch to UART mode */
psc->sicr = 0;
/* configure parity, bit length and so on */
-#if defined(CONFIG_MGT5100)
- psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE;
-#elif defined(CONFIG_MPC5200)
psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
-#endif
psc->mode = PSC_MODE_ONE_STOP;
/* set up UART divisor */
#endif
unsigned long baseclk, div;
-#if defined(CONFIG_MGT5100)
- baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32;
-#elif defined(CONFIG_MPC5200)
baseclk = (gd->ipb_clk + 16) / 32;
-#endif
/* set up UART divisor */
div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
# if defined(CONFIG_SYS_RAMBOOT)
# error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT
# endif /* CONFIG_SYS_RAMBOOT */
-# if defined(CONFIG_MGT5100)
-# error CONFIG_SYS_LOWBOOT is incompatible with MGT5100
-# endif /* CONFIG_MGT5100 */
lis r4, CONFIG_SYS_DEFAULT_MBAR@h
lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
lis r3, CONFIG_SYS_MBAR@h
ori r3, r3, CONFIG_SYS_MBAR@l
-#if defined(CONFIG_MPC5200)
/* MBAR is mirrored into the MBAR SPR */
mtspr MBAR,r3
rlwinm r3, r3, 16, 16, 31
-#endif
-#if defined(CONFIG_MGT5100)
- rlwinm r3, r3, 17, 15, 31
-#endif
lis r4, CONFIG_SYS_DEFAULT_MBAR@h
stw r3, 0(r4)
#endif /* CONFIG_SYS_DEFAULT_MBAR */
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc5xxx/start.o (.text)
- cpu/mpc5xxx/traps.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/cpu/mpc5xxx/start.o (.text)
+ arch/ppc/cpu/mpc5xxx/traps.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
.plt : { *(.plt) }
.text :
{
- cpu/mpc5xxx/start.o (.text)
+ arch/ppc/cpu/mpc5xxx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
#define m16_swap(x) swap_16(x)
#define m32_swap(x) swap_32(x)
-#ifdef CONFIG_MPC5200
#define ohci_cpu_to_le16(x) (x)
#define ohci_cpu_to_le32(x) (x)
-#else
-#define ohci_cpu_to_le16(x) swap_16(x)
-#define ohci_cpu_to_le32(x) swap_32(x)
-#endif
/* global ohci_t */
static ohci_t gohci;
} else
td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
}
-#ifdef CONFIG_MPC5200
td_list->hwNextTD = 0;
-#endif
}
td_list->next_dl_td = td_rev;
#define NUM_INTS 32 /* part of the OHCI standard */
struct ohci_hcca {
__u32 int_table[NUM_INTS]; /* Interrupt ED table */
-#if defined(CONFIG_MPC5200)
__u16 pad1; /* set to 0 on each frame_no change */
__u16 frame_no; /* current frame number */
-#else
- __u16 frame_no; /* current frame number */
- __u16 pad1; /* set to 0 on each frame_no change */
-#endif
__u32 done_head; /* info returned for an interrupt */
u8 reserved_for_hc[116];
} __attribute__((aligned(256)));
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc8220/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc8220/u-boot.lds
.plt : { *(.plt) }
.text :
{
- cpu/mpc8220/start.o (.text)
+ arch/ppc/cpu/mpc8220/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc824x/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc824x/u-boot.lds
.plt : { *(.plt) }
.text :
{
- cpu/mpc8260/start.o (.text)
+ arch/ppc/cpu/mpc824x/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc8260/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc8260/u-boot.lds
.plt : { *(.plt) }
.text :
{
- cpu/mpc824x/start.o (.text)
+ arch/ppc/cpu/mpc8260/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
-ffixed-r2 -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc83xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc83xx/u-boot.lds
.plt : { *(.plt) }
.text :
{
- cpu/mpc83xx/start.o (.text)
+ arch/ppc/cpu/mpc83xx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
COBJS-$(CONFIG_MPC8569) += ddr-gen3.o
COBJS-$(CONFIG_P1011) += ddr-gen3.o
+COBJS-$(CONFIG_P1012) += ddr-gen3.o
+COBJS-$(CONFIG_P1013) += ddr-gen3.o
COBJS-$(CONFIG_P1020) += ddr-gen3.o
+COBJS-$(CONFIG_P1021) += ddr-gen3.o
+COBJS-$(CONFIG_P1022) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe)
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc85xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc85xx/u-boot.lds
/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
* Kumar Gala <kumar.gala@freescale.com>
*
* See file CREDITS for list of people who contributed to this
#ifndef CONFIG_E500MC
li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
+ mfspr r0,PVR
+ andi. r0,r0,0xff
+ cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
+ blt 1f
+ /* Set MBDD bit also */
+ ori r3, r3, HID1_MBDD@l
+1:
mtspr SPRN_HID1,r3
#endif
/* Enable branch prediction */
- li r3,0x201
+ lis r3,BUCSR_ENABLE@h
+ ori r3,r3,BUCSR_ENABLE@l
mtspr SPRN_BUCSR,r3
/* Ensure TB is 0 */
mttbu r3
/* Enable/invalidate the I-Cache */
- mfspr r0,SPRN_L1CSR1
- ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
- mtspr SPRN_L1CSR1,r0
+ lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
+ ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
+ mtspr SPRN_L1CSR1,r2
+1:
+ mfspr r3,SPRN_L1CSR1
+ and. r1,r3,r2
+ bne 1b
+
+ lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
+ ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
+ mtspr SPRN_L1CSR1,r3
isync
+2:
+ mfspr r3,SPRN_L1CSR1
+ andi. r1,r3,L1CSR1_ICE@l
+ beq 2b
/* Enable/invalidate the D-Cache */
- mfspr r0,SPRN_L1CSR0
- ori r0,r0,(L1CSR0_DCFI|L1CSR0_DCE)
- msync
- isync
- mtspr SPRN_L1CSR0,r0
+ lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
+ ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
+ mtspr SPRN_L1CSR0,r2
+1:
+ mfspr r3,SPRN_L1CSR0
+ and. r1,r3,r2
+ bne 1b
+
+ lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
+ ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
+ mtspr SPRN_L1CSR0,r3
isync
+2:
+ mfspr r3,SPRN_L1CSR0
+ andi. r1,r3,L1CSR0_DCE@l
+ beq 2b
#define toreset(x) (x - __secondary_start_page + 0xfffff000)
/*
- * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
* Copyright (C) 2003 Motorola,Inc.
*
* See file CREDITS for list of people who contributed to this
mtspr L1CSR2,r2
#endif
- lis r2,L1CSR0_CPE@H /* enable parity */
- ori r2,r2,L1CSR0_DCE
- mtspr L1CSR0,r2 /* enable L1 Dcache */
+ /* Enable/invalidate the I-Cache */
+ lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
+ ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
+ mtspr SPRN_L1CSR1,r2
+1:
+ mfspr r3,SPRN_L1CSR1
+ and. r1,r3,r2
+ bne 1b
+
+ lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
+ ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
+ mtspr SPRN_L1CSR1,r3
isync
- mtspr L1CSR1,r2 /* enable L1 Icache */
+2:
+ mfspr r3,SPRN_L1CSR1
+ andi. r1,r3,L1CSR1_ICE@l
+ beq 2b
+
+ /* Enable/invalidate the D-Cache */
+ lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
+ ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
+ mtspr SPRN_L1CSR0,r2
+1:
+ mfspr r3,SPRN_L1CSR0
+ and. r1,r3,r2
+ bne 1b
+
+ lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
+ ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
+ mtspr SPRN_L1CSR0,r3
isync
- msync
+2:
+ mfspr r3,SPRN_L1CSR0
+ andi. r1,r3,L1CSR0_DCE@l
+ beq 2b
/* Setup interrupt vectors */
lis r1,TEXT_BASE@h
#ifndef CONFIG_E500MC
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
+ mfspr r3,PVR
+ andi. r3,r3, 0xff
+ cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
+ blt 1f
+ /* Set MBDD bit also */
+ ori r0, r0, HID1_MBDD@l
+1:
mtspr HID1,r0
#endif
/* Enable Branch Prediction */
#if defined(CONFIG_BTB)
- li r0,0x201 /* BBFI = 1, BPEN = 1 */
- mtspr BUCSR,r0
+ lis r0,BUCSR_ENABLE@h
+ ori r0,r0,BUCSR_ENABLE@l
+ mtspr SPRN_BUCSR,r0
#endif
#if defined(CONFIG_SYS_INIT_DBCR)
.bootpg ADDR(.text) - 0x1000 :
{
- cpu/mpc85xx/start.o (.bootpg)
+ arch/ppc/cpu/mpc85xx/start.o (.bootpg)
} :text = 0xffff
. = ADDR(.text) + 0x80000;
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
- cpu/mpc85xx/start.o (.bootpg)
+ arch/ppc/cpu/mpc85xx/start.o (.bootpg)
} :text = 0xffff
.resetvec RESET_VECTOR_ADDRESS :
/*
- * Copyright 2006,2009 Freescale Semiconductor, Inc.
+ * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
}
+
+/*
+ * Set the DDR BATs to reflect the actual size of DDR.
+ *
+ * dram_size is the actual size of DDR, in bytes
+ *
+ * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
+ * are using a single BAT to cover DDR.
+ *
+ * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
+ * is not defined) then we might have a situation where U-Boot will attempt
+ * to relocated itself outside of the region mapped by DBAT0.
+ * This will cause a machine check.
+ *
+ * Currently we are limited to power of two sized DDR since we only use a
+ * single bat. If a non-power of two size is used that is less than
+ * CONFIG_MAX_MEM_MAPPED u-boot will crash.
+ *
+ */
+void setup_ddr_bat(phys_addr_t dram_size)
+{
+ unsigned long batu, bl;
+
+ bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
+
+ if (BATU_SIZE(bl) != dram_size) {
+ u64 sz = (u64)dram_size - BATU_SIZE(bl);
+ print_size(sz, " left unmapped\n");
+ }
+
+ batu = bl | BATU_VS | BATU_VP;
+ write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
+ write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
+}
/* Set up BAT registers */
void setup_bats(void)
{
+#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L)
write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L);
+#endif
+#if defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L);
+#endif
write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L);
write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L);
write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L);
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
- * This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c.
- * Basically this file contains cpu specific common code for 85xx/86xx
- * processors.
+ * This file is derived from arch/ppc/cpu/mpc85xx/cpu.c and
+ * arch/ppc/cpu/mpc86xx/cpu.c. Basically this file contains
+ * cpu specific common code for 85xx/86xx processors.
* See file CREDITS for list of people who contributed to this
* project.
*
CPU_TYPE_ENTRY(8572, 8572_E, 2),
CPU_TYPE_ENTRY(P1011, P1011, 1),
CPU_TYPE_ENTRY(P1011, P1011_E, 1),
+ CPU_TYPE_ENTRY(P1012, P1012, 1),
+ CPU_TYPE_ENTRY(P1012, P1012_E, 1),
+ CPU_TYPE_ENTRY(P1013, P1013, 1),
+ CPU_TYPE_ENTRY(P1013, P1013_E, 1),
CPU_TYPE_ENTRY(P1020, P1020, 2),
CPU_TYPE_ENTRY(P1020, P1020_E, 2),
+ CPU_TYPE_ENTRY(P1021, P1021, 2),
+ CPU_TYPE_ENTRY(P1021, P1021_E, 2),
+ CPU_TYPE_ENTRY(P1022, P1022, 2),
+ CPU_TYPE_ENTRY(P1022, P1022_E, 2),
CPU_TYPE_ENTRY(P2010, P2010, 1),
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
*/
/*
}
/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
-static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
+static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts)
{
unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
#if defined(CONFIG_FSL_DDR3)
- /* We need set BL/2 + 4 for BC4 or OTF */
- rrt = 4; /* BL/2 + 4 clocks */
- wwt = 4; /* BL/2 + 4 clocks */
+ if (popts->burst_length == DDR_BL8) {
+ /* We set BL/2 for fixed BL8 */
+ rrt = 0; /* BL/2 clocks */
+ wwt = 0; /* BL/2 clocks */
+ } else {
+ /* We need to set BL/2 + 2 to BC4 and OTF */
+ rrt = 2; /* BL/2 + 2 clocks */
+ wwt = 2; /* BL/2 + 2 clocks */
+ }
dll_lock = 1; /* tDLLK = 512 clocks from spec */
#endif
ddr->timing_cfg_4 = (0
set_ddr_sdram_clk_cntl(ddr, popts);
set_ddr_init_addr(ddr);
set_ddr_init_ext_addr(ddr);
- set_timing_cfg_4(ddr);
+ set_timing_cfg_4(ddr, popts);
set_timing_cfg_5(ddr);
set_ddr_zq_cntl(ddr, zq_en);
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
*/
#include <common.h>
/* Choose burst length. */
#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_E500MC)
+ popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
+ popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
+#else
popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
+#endif
#else
popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
#endif
/*
* Copyright 2009 Freescale Semiconductor, Inc.
*
- * This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c.
- * Basically this file contains cpu specific common code for 85xx/86xx
- * processors.
+ * This file is derived from arch/ppc/cpu/mpc85xx/cpu.c and
+ * arch/ppc/cpu/mpc86xx/cpu.c. Basically this file contains
+ * cpu specific common code for 85xx/86xx processors.
* See file CREDITS for list of people who contributed to this
* project.
*
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <pci.h>
struct pci_info {
- u16 cfg;
+ u32 cfg;
};
/* The cfg field is a bit mask in which each bit represents the value of
(1 << 7) | (1 << 0xe) | (1 << 0xf),
},
};
-#elif defined(CONFIG_P1011) || defined(CONFIG_P1020)
+#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
+ defined(CONFIG_P1012) || defined(CONFIG_P1021)
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCIE_1] = {
.cfg = (1 << 0xe),
},
};
+#elif defined(CONFIG_P1013) || defined(CONFIG_P1022)
+static struct pci_info pci_config_info[] =
+{
+ [LAW_TRGT_IF_PCIE_1] = {
+ .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xa) |
+ (1 << 0xb) | (1 << 0xd) | (1 << 0xe) |
+ (1 << 0xf) | (1 << 0x15) | (1 << 0x16) |
+ (1 << 0x17) | (1 << 0x18) | (1 << 0x19) |
+ (1 << 0x1a) | (1 << 0x1b) | (1 << 0x1c) |
+ (1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f),
+ },
+ [LAW_TRGT_IF_PCIE_2] = {
+ .cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) |
+ (1 << 9) | (1 << 0xa) | (1 << 0xb) | (1 << 0xd) |
+ (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
+ (1 << 0x18) | (1 << 0x1c),
+ },
+ [LAW_TRGT_IF_PCIE_3] = {
+ .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xd) |
+ (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | (1 << 0x18) |
+ (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
+ },
+};
#elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
static struct pci_info pci_config_info[] =
{
/*
- * cpu/ppc4xx/40x_spd_sdram.c
+ * arch/ppc/cpu/ppc4xx/40x_spd_sdram.c
* This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a
* SDRAM controller. Those are all current 405 PPC's.
*
/*
- * cpu/ppc4xx/44x_spd_ddr.c
+ * arch/ppc/cpu/ppc4xx/44x_spd_ddr.c
* This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
* DDR controller. Those are 440GP/GX/EP/GR.
*
/*
- * cpu/ppc4xx/44x_spd_ddr2.c
+ * arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c
* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
* DDR2 controller (non Denali Core). Those currently are:
*
/*
- * cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+ * arch/ppc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
* DDR2 controller (non Denali Core). Those currently are:
*
#include <pci.h>
#include <ppc4xx.h>
#include <asm/processor.h>
-#include <asm-ppc/io.h>
+#include <asm/io.h>
#include <asm/errno.h>
#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
COBJS += denali_spd_ddr2.o
COBJS += ecc.o
COBJS += fdt.o
-COBJS += i2c.o
COBJS += interrupts.o
COBJS += iop480_uart.o
ifdef CONFIG_CMD_REGINFO
endif
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/ppc4xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/ppc4xx/u-boot.lds
mtcpr(CPR0_SPCID, reg);
reset_needed = 1;
}
+ }
+
+ /* Get current value of FWDVA.*/
+ mfcpr(CPR0_PLLD, reg);
+ temp = (reg & PLLD_FWDVA_MASK) >> 16;
- /* Set reload inhibit so configuration will persist across
- * processor resets */
+ /*
+ * Check to see if FWDVA has been set to value of 1. if it has we must
+ * modify it.
+ */
+ if (temp == 1) {
+ mfcpr(CPR0_PLLD, reg);
+ /* Get current value of fbdv. */
+ temp = (reg & PLLD_FBDV_MASK) >> 24;
+ fbdv = temp ? temp : 32;
+ /* Get current value of lfbdv. */
+ temp = (reg & PLLD_LFBDV_MASK);
+ lfbdv = temp ? temp : 64;
+ /*
+ * Load register that contains current boot strapping option.
+ */
+ mfcpr(CPR0_ICFG, reg);
+ /* Shift strapping option into low 3 bits.*/
+ reg = (reg >> 28);
+
+ if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) ||
+ (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) {
+ /*
+ * Get current value of FWDVA. Assign current FWDVA to
+ * new FWDVB.
+ */
+ mfcpr(CPR0_PLLD, reg);
+ target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
+ fwdvb = target_fwdvb ? target_fwdvb : 8;
+ /*
+ * Get current value of FWDVB. Assign current FWDVB to
+ * new FWDVA.
+ */
+ target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
+ fwdva = target_fwdva ? target_fwdva : 16;
+ /*
+ * Update CPR0_PLLD with switched FWDVA and FWDVB.
+ */
+ reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
+ PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
+ reg |= ((fwdva == 16 ? 0 : fwdva) << 16) |
+ ((fwdvb == 8 ? 0 : fwdvb) << 8) |
+ ((fbdv == 32 ? 0 : fbdv) << 24) |
+ (lfbdv == 64 ? 0 : lfbdv);
+ mtcpr(CPR0_PLLD, reg);
+ /* Acknowledge that a reset is required. */
+ reset_needed = 1;
+ }
+ }
+
+ if (reset_needed) {
+ /*
+ * Set reload inhibit so configuration will persist across
+ * processor resets
+ */
mfcpr(CPR0_ICFG, reg);
reg &= ~CPR0_ICFG_RLI_MASK;
reg |= 1 << 31;
mtcpr(CPR0_ICFG, reg);
- }
- /* Reset processor if configuration changed */
- if (reset_needed) {
+ /* Reset processor if configuration changed */
__asm__ __volatile__ ("sync; isync");
mtspr(SPRN_DBCR0, 0x20000000);
}
/*
- * cpu/ppc4xx/denali_data_eye.c
+ * arch/ppc/cpu/ppc4xx/denali_data_eye.c
* Extracted from board/amcc/sequoia/sdram.c by Larry Johnson <lrj@acm.org>.
*
* (C) Copyright 2006
/*
- * cpu/ppc4xx/denali_spd_ddr2.c
+ * arch/ppc/cpu/ppc4xx/denali_spd_ddr2.c
* This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core
* DDR2 controller, specifically the 440EPx/GRx.
*
* (C) Copyright 2007-2008
* Larry Johnson, lrj@acm.org.
*
- * Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is...
+ * Based primarily on arch/ppc/cpu/ppc4xx/4xx_spd_ddr2.c, which is...
*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
/*----------------------------------------------------------------*/
/* TLB entry setup -- step thru tlbtab */
/*----------------------------------------------------------------*/
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE_REVA)
/*----------------------------------------------------------------*/
/* We have different TLB tables for revA and rev B of 440SPe */
/*----------------------------------------------------------------*/
#ifdef CONFIG_440
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
- cpu/ppc4xx/start.o (.bootpg)
+ arch/ppc/cpu/ppc4xx/start.o (.bootpg)
/*
* PPC440 board need a board specific object with the
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
#endif
#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
+ defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
#define CONFIG_MAX_CPUS 2
#elif defined(CONFIG_PPC_P4080)
#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \
| ((x & 0x0e00ULL) << 24) \
| ((x & 0x04ULL) << 30)))
-#define BATU_SIZE(x) (1UL << (fls((x & BATU_BL_MAX) >> 2) + 17))
+#define BATU_SIZE(x) (1ULL << (fls((x & BATU_BL_MAX) >> 2) + 17))
+
+/* bytes into BATU_BL */
+#define TO_BATU_BL(x) \
+ (u32)((((1ull << __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4)
/* Used to set up SDR1 register */
#define HASH_TABLE_SIZE_64K 0x00010000
#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
#define HID1_ASTME (1<<13) /* Address bus streaming mode */
#define HID1_ABE (1<<12) /* Address broadcast enable */
+#define HID1_MBDD (1<<6) /* optimized sync instruction */
#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
#ifndef CONFIG_BOOKE
#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
+#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
+#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */
#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
+#define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */
+#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */
+#define BUCSR_ENABLE (BUCSR_BBFI|BUCSR_BPEN)
#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
#define SPRN_PID1 0x279 /* Process ID Register 1 */
#define SVR_8572_E 0x80E800
#define SVR_P1011 0x80E500
#define SVR_P1011_E 0x80ED00
+#define SVR_P1012 0x80E501
+#define SVR_P1012_E 0x80ED01
+#define SVR_P1013 0x80E700
+#define SVR_P1013_E 0x80EF00
#define SVR_P1020 0x80E400
#define SVR_P1020_E 0x80EC00
+#define SVR_P1021 0x80E401
+#define SVR_P1021_E 0x80EC01
+#define SVR_P1022 0x80E600
+#define SVR_P1022_E 0x80EE00
#define SVR_P2010 0x80E300
#define SVR_P2010_E 0x80EB00
#define SVR_P2020 0x80E200
PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
PLATFORM_LDFLAGS += -e $(TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE)
-LDSCRIPT := $(SRCTREE)/cpu/$(CPU)/u-boot.lds
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
.text :
{
- cpu/sh2/start.o (.text)
+ arch/sh/cpu/sh2/start.o (.text)
. = ALIGN(8192);
common/env_embedded.o (.ppcenv)
. = ALIGN(8192);
.text :
{
- cpu/sh3/start.o (.text)
+ arch/sh/cpu/sh3/start.o (.text)
. = ALIGN(8192);
common/env_embedded.o (.ppcenv)
. = ALIGN(8192);
.text :
{
- cpu/sh4/start.o (.text)
+ arch/sh/cpu/sh4/start.o (.text)
. = ALIGN(8192);
common/env_embedded.o (.ppcenv)
. = ALIGN(8192);
--- /dev/null
+#include <asm-generic/errno.h>
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf52x2/start.o (.text)
+ arch/m68k/cpu/mcf52x2/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/string.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ lib/string.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
/* . = env_offset; */
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_generic/string.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/extable.o (.text)
- lib_ppc/time.o (.text)
- lib_ppc/ticks.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ lib/string.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/extable.o (.text)
+ arch/ppc/lib/time.o (.text)
+ arch/ppc/lib/ticks.o (.text)
. = env_offset;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
/* XXX ?
. = env_offset;
*/
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
/* XXX ?
. = env_offset;
*/
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
/* XXX ?
. = env_offset;
*/
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/time.o (.text)
. = env_offset;
common/env_embedded.o (.ppcenv)
TEXT_BASE = 0x00e00000
# include NPE ethernet driver
-BOARDLIBS = cpu/ixp/npe/libnpe.a
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a
LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
. = ALIGN (4);
.text : {
- cpu/ixp/start.o(.text)
- lib_generic/string.o(.text)
- lib_generic/vsprintf.o(.text)
- lib_arm/board.o(.text)
+ arch/arm/cpu/ixp/start.o(.text)
+ lib/string.o(.text)
+ lib/vsprintf.o(.text)
+ arch/arm/lib/board.o(.text)
common/dlmalloc.o(.text)
- cpu/ixp/cpu.o(.text)
+ arch/arm/cpu/ixp/cpu.o(.text)
. = env_offset;
common/env_embedded.o(.ppcenv)
* (.text)
TEXT_BASE = 0x00e00000
# include NPE ethernet driver
-BOARDLIBS = cpu/ixp/npe/libnpe.a
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a
LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
. = ALIGN (4);
.text : {
- cpu/ixp/start.o(.text)
- lib_generic/string.o(.text)
- lib_generic/vsprintf.o(.text)
- lib_arm/board.o(.text)
+ arch/arm/cpu/ixp/start.o(.text)
+ lib/string.o(.text)
+ lib/vsprintf.o(.text)
+ arch/arm/lib/board.o(.text)
common/dlmalloc.o(.text)
- cpu/ixp/cpu.o(.text)
+ arch/arm/cpu/ixp/cpu.o(.text)
. = env_offset;
common/env_embedded.o (.ppcenv)
TEXT_BASE = 0x00e00000
# include NPE ethernet driver
-BOARDLIBS = cpu/ixp/npe/libnpe.a
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a
LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
. = ALIGN (4);
.text : {
- cpu/ixp/start.o (.text)
- lib_generic/string.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_arm/board.o (.text)
+ arch/arm/cpu/ixp/start.o (.text)
+ lib/string.o (.text)
+ lib/vsprintf.o (.text)
+ arch/arm/lib/board.o (.text)
common/dlmalloc.o (.text)
- cpu/ixp/cpu.o (.text)
+ arch/arm/cpu/ixp/cpu.o (.text)
. = env_offset;
common/env_embedded.o (.ppcenv)
TEXT_BASE = 0x00e00000
# include NPE ethernet driver
-BOARDLIBS = cpu/ixp/npe/libnpe.a
+BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.a
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (unsigned char *) info->start[sect];
- writeb (addr, 0xaa);
- writeb (addr, 0x55);
- writeb (addr, 0x80);
- writeb (addr, 0xaa);
- writeb (addr, 0x55);
- writeb (addr2, 0x30);
+ writeb (0xaa, addr);
+ writeb (0x55, addr);
+ writeb (0x80, addr);
+ writeb (0xaa, addr);
+ writeb (0x55, addr);
+ writeb (0x30, addr2);
/* Now just wait for 0xff & provide some user
* feedback while we wait.
*/
return (2);
}
- writeb (cmd, 0xaa);
- writeb (cmd, 0x55);
- writeb (cmd, 0xa0);
- writeb (dst, b);
+ writeb (0xaa, cmd);
+ writeb (0x55, cmd);
+ writeb (0xa0, cmd);
+ writeb (b, dst);
/* Verify write */
start = get_timer (0);
val &= ~mask;
else
val |= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
void __led_set (led_id_t mask, int state)
val &= ~mask;
else
val |= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
void __led_toggle (led_id_t mask)
nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
val ^= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
{
.text :
{
- cpu/nios/start.o (.text)
+ arch/nios/cpu/start.o (.text)
*(.text)
}
__text_end = .;
{
.text :
{
- cpu/nios/start.o (.text)
+ arch/nios/cpu/start.o (.text)
*(.text)
}
__text_end = .;
{
.text :
{
- cpu/nios2/start.o (.text)
+ arch/nios/cpu2/start.o (.text)
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
{
.text :
{
- cpu/nios2/start.o (.text)
+ arch/nios/cpu2/start.o (.text)
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
{
.text :
{
- cpu/nios2/start.o (.text)
+ arch/nios/cpu2/start.o (.text)
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
#include <ppc_asm.tmpl>
#include <config.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
/**************************************************************************
* TLB TABLE
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
#define BOARD_ARCHES 4
/*
- * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
#if defined(CONFIG_ARCHES)
#include <ppc_asm.tmpl>
#include <config.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
/**************************************************************************
* TLB TABLE
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x20000);
#include <ppc_asm.tmpl>
#include <config.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
/**************************************************************************
* TLB TABLE
#include <ppc_asm.tmpl>
#include <config.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
/**************************************************************************
* TLB TABLE
}
/*
- * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
u32 ddr_wrdtr(u32 default_val) {
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
#include <ppc_asm.tmpl>
#include <config.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
/**************************************************************************
* TLB TABLE
}
/*
- * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
u32 ddr_clktr(u32 default_val) {
#include <ppc_asm.tmpl>
#include <config.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
/**************************************************************************
* TLB TABLE
#include <ppc_asm.tmpl>
#include <config.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
/**************************************************************************
* TLB TABLE
#include <ppc4xx.h>
#include <asm/processor.h>
#include <i2c.h>
-#include <asm-ppc/io.h>
+#include <asm/io.h>
int compare_to_true(char *str);
char *remove_l_w_space(char *in_str);
*/
#include <ppc_asm.tmpl>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
#include <config.h>
/*
extern void denali_core_search_data_eye(void);
#if defined(CONFIG_NAND_SPL)
-/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+/* Using arch/ppc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
* for the 4k NAND boot image so define bus_frequency to 133MHz here
* which is save for the refresh counter setup.
*/
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
.plt : { *(.plt) }
.text :
{
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
*(.text)
*(.got1)
#include <ppc_asm.tmpl>
#include <config.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
/**************************************************************************
* TLB TABLE
}
/*
- * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
static int ppc440spe_rev_a(void)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
board/amirix/ap1000/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
+ arch/ppc/cpu/ppc4xx/kgdb.o (.text)
+ arch/ppc/cpu/ppc4xx/traps.o (.text)
+ arch/ppc/cpu/ppc4xx/interrupts.o (.text)
+ arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/ppc/cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
+ lib/zlib.o (.text)
/* . = env_offset;*/
/* common/env_embedded.o(.text)*/
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
-#ifdef CONFIG_PCI
rc += pci_eth_init(bis);
-#endif
return rc;
}
#endif
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o fpga.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#ifndef __ASTRO_H__
+#define __ASTRO_H__
+
+/* in mcf5373l.c */
+int rs_serial_init(int port, int baud);
+void astro_put_char(char ch);
+int astro_is_char(void);
+int astro_get_char(void);
+
+/* in fpga.c */
+int astro5373l_altera_load(void);
+int astro5373l_xilinx_load(void);
+
+/* data structures used for communication (update.c) */
+typedef struct card_id {
+ char card_type;
+ char hardware_version;
+ char software_version;
+ char software_subversion; /* " ","a".."z" */
+ char fpga_version_altera;
+ char fpga_version_xilinx;
+} card_id_t;
+
+typedef struct {
+ unsigned char mode;
+ unsigned char deviation;
+ unsigned short freq;
+} __attribute__ ((packed)) output_params_t;
+
+typedef struct {
+ unsigned short satfreq;
+ unsigned char satdatallg;
+ unsigned short symbolrate;
+ unsigned char viterbirate;
+ unsigned char symbolrate_l;
+ output_params_t output_params;
+ unsigned char reserve;
+ unsigned char card_error;
+ unsigned short dummy_ts_id;
+ unsigned char dummy_pat_ver;
+ unsigned char dummy_sdt_ver;
+} __attribute__ ((packed)) parameters_t;
+
+#endif /* __ASTRO_H__ */
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
# MA 02111-1307 USA
#
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-TEXT_BASE = 0x04000000
+TEXT_BASE = $(CONFIG_TEXT_BASE)
-# Use board specific linker script
-LDSCRIPT := $(SRCTREE)/board/xilinx/ml300/u-boot.lds
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH,
+ * w.wegner@astro-kom.de
+ *
+ * based on the files by
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ * and
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */
+
+#include <common.h>
+#include <watchdog.h>
+#include <altera.h>
+#include <ACEX1K.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/immap_5329.h>
+#include <asm/io.h>
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int altera_pre_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+ unsigned char tmp_char;
+ unsigned short tmp_short;
+
+ /* first, set the required pins to GPIO function */
+ /* PAR_T0IN -> GPIO */
+ tmp_char = readb(&gpiop->par_timer);
+ tmp_char &= 0xfc;
+ writeb(tmp_char, &gpiop->par_timer);
+ /* all QSPI pins -> GPIO */
+ writew(0x0000, &gpiop->par_qspi);
+ /* U0RTS, U0CTS -> GPIO */
+ tmp_short = __raw_readw(&gpiop->par_uart);
+ tmp_short &= 0xfff3;
+ __raw_writew(tmp_short, &gpiop->par_uart);
+ /* all PWM pins -> GPIO */
+ writeb(0x00, &gpiop->par_pwm);
+ /* next, set data direction registers */
+ writeb(0x01, &gpiop->pddr_timer);
+ writeb(0x25, &gpiop->pddr_qspi);
+ writeb(0x0c, &gpiop->pddr_uart);
+ writeb(0x04, &gpiop->pddr_pwm);
+
+ /* ensure other SPI peripherals are deselected */
+ writeb(0x08, &gpiop->ppd_uart);
+ writeb(0x38, &gpiop->ppd_qspi);
+
+ /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
+ writeb(0xFB, &gpiop->pclrr_uart);
+ /* enable Altera configuration by clearing QSPI_CS2 and DT0IN */
+ writeb(0xFE, &gpiop->pclrr_timer);
+ writeb(0xDF, &gpiop->pclrr_qspi);
+ return FPGA_SUCCESS;
+}
+
+/* Set the state of CONFIG Pin */
+int altera_config_fn(int assert_config, int flush, int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ if (assert_config)
+ writeb(0x04, &gpiop->ppd_uart);
+ else
+ writeb(0xFB, &gpiop->pclrr_uart);
+ return FPGA_SUCCESS;
+}
+
+/* Returns the state of STATUS Pin */
+int altera_status_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ if (readb(&gpiop->ppd_pwm) & 0x08)
+ return FPGA_FAIL;
+ return FPGA_SUCCESS;
+}
+
+/* Returns the state of CONF_DONE Pin */
+int altera_done_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ if (readb(&gpiop->ppd_pwm) & 0x20)
+ return FPGA_FAIL;
+ return FPGA_SUCCESS;
+}
+
+/*
+ * writes the complete buffer to the FPGA
+ * writing the complete buffer in one function is much faster,
+ * then calling it for every bit
+ */
+int altera_write_fn(void *buf, size_t len, int flush, int cookie)
+{
+ size_t bytecount = 0;
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+ unsigned char *data = (unsigned char *)buf;
+ unsigned char val = 0;
+ int i;
+ int len_40 = len / 40;
+
+ while (bytecount < len) {
+ val = data[bytecount++];
+ i = 8;
+ do {
+ writeb(0xFB, &gpiop->pclrr_qspi);
+ if (val & 0x01)
+ writeb(0x01, &gpiop->ppd_qspi);
+ else
+ writeb(0xFE, &gpiop->pclrr_qspi);
+ writeb(0x04, &gpiop->ppd_qspi);
+ val >>= 1;
+ i--;
+ } while (i > 0);
+
+ if (bytecount % len_40 == 0) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ WATCHDOG_RESET();
+#endif
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+ putc('.'); /* let them know we are alive */
+#endif
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+ if (ctrlc())
+ return FPGA_FAIL;
+#endif
+ }
+ }
+ return FPGA_SUCCESS;
+}
+
+/* called, when programming is aborted */
+int altera_abort_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ writeb(0x20, &gpiop->ppd_qspi);
+ writeb(0x08, &gpiop->ppd_uart);
+ return FPGA_SUCCESS;
+}
+
+/* called, when programming was succesful */
+int altera_post_fn(int cookie)
+{
+ return altera_abort_fn(cookie);
+}
+
+/*
+ * Note that these are pointers to code that is in Flash. They will be
+ * relocated at runtime.
+ * FIXME: relocation not yet working for coldfire, see below!
+ */
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+ altera_pre_fn,
+ altera_config_fn,
+ altera_status_fn,
+ altera_done_fn,
+ altera_write_fn,
+ altera_abort_fn,
+ altera_post_fn
+};
+
+Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = {
+ {Altera_CYC2,
+ passive_serial,
+ 85903,
+ (void *)&altera_fns,
+ NULL,
+ 0}
+};
+
+/* Initialize the fpga. Return 1 on success, 0 on failure. */
+int astro5373l_altera_load(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+ /*
+ * I did not yet manage to get relocation work properly,
+ * so set stuff here instead of static initialisation:
+ */
+ altera_fns.pre = altera_pre_fn;
+ altera_fns.config = altera_config_fn;
+ altera_fns.status = altera_status_fn;
+ altera_fns.done = altera_done_fn;
+ altera_fns.write = altera_write_fn;
+ altera_fns.abort = altera_abort_fn;
+ altera_fns.post = altera_post_fn;
+ altera_fpga[i].iface_fns = (void *)&altera_fns;
+ fpga_add(fpga_altera, &altera_fpga[i]);
+ }
+ return 1;
+}
+
+/* Set the FPGA's PROG_B line to the specified level */
+int xilinx_pgm_fn(int assert, int flush, int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ if (assert)
+ writeb(0xFB, &gpiop->pclrr_uart);
+ else
+ writeb(0x04, &gpiop->ppd_uart);
+ return assert;
+}
+
+/*
+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
+ * asserted (low).
+ */
+int xilinx_init_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ return (readb(&gpiop->ppd_pwm) & 0x08) == 0;
+}
+
+/* Test the state of the active-high FPGA DONE pin */
+int xilinx_done_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ return (readb(&gpiop->ppd_pwm) & 0x20) >> 5;
+}
+
+/* Abort an FPGA operation */
+int xilinx_abort_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+ /* ensure all SPI peripherals and FPGAs are deselected */
+ writeb(0x08, &gpiop->ppd_uart);
+ writeb(0x01, &gpiop->ppd_timer);
+ writeb(0x38, &gpiop->ppd_qspi);
+ return FPGA_FAIL;
+}
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+int xilinx_pre_config_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+ unsigned char tmp_char;
+ unsigned short tmp_short;
+
+ /* first, set the required pins to GPIO function */
+ /* PAR_T0IN -> GPIO */
+ tmp_char = readb(&gpiop->par_timer);
+ tmp_char &= 0xfc;
+ writeb(tmp_char, &gpiop->par_timer);
+ /* all QSPI pins -> GPIO */
+ writew(0x0000, &gpiop->par_qspi);
+ /* U0RTS, U0CTS -> GPIO */
+ tmp_short = __raw_readw(&gpiop->par_uart);
+ tmp_short &= 0xfff3;
+ __raw_writew(tmp_short, &gpiop->par_uart);
+ /* all PWM pins -> GPIO */
+ writeb(0x00, &gpiop->par_pwm);
+ /* next, set data direction registers */
+ writeb(0x01, &gpiop->pddr_timer);
+ writeb(0x25, &gpiop->pddr_qspi);
+ writeb(0x0c, &gpiop->pddr_uart);
+ writeb(0x04, &gpiop->pddr_pwm);
+
+ /* ensure other SPI peripherals are deselected */
+ writeb(0x08, &gpiop->ppd_uart);
+ writeb(0x38, &gpiop->ppd_qspi);
+ writeb(0x01, &gpiop->ppd_timer);
+
+ /* CONFIG = 0, STATUS = 0 -> FPGA in reset state */
+ writeb(0xFB, &gpiop->pclrr_uart);
+ /* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */
+ writeb(0xF7, &gpiop->pclrr_uart);
+ writeb(0xDF, &gpiop->pclrr_qspi);
+ return 0;
+}
+
+/*
+ * FPGA post configuration function. Should perform a test if FPGA is running.
+ */
+int xilinx_post_config_fn(int cookie)
+{
+ int rc = 0;
+
+ /*
+ * no test yet
+ */
+ return rc;
+}
+
+int xilinx_clk_fn(int assert_clk, int flush, int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ if (assert_clk)
+ writeb(0x04, &gpiop->ppd_qspi);
+ else
+ writeb(0xFB, &gpiop->pclrr_qspi);
+ return assert_clk;
+}
+
+int xilinx_wr_fn(int assert_write, int flush, int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ if (assert_write)
+ writeb(0x01, &gpiop->ppd_qspi);
+ else
+ writeb(0xFE, &gpiop->pclrr_qspi);
+ return assert_write;
+}
+
+int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie)
+{
+ size_t bytecount = 0;
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+ unsigned char *data = (unsigned char *)buf;
+ unsigned char val = 0;
+ int i;
+ int len_40 = len / 40;
+
+ for (bytecount = 0; bytecount < len; bytecount++) {
+ val = *(data++);
+ for (i = 8; i > 0; i--) {
+ writeb(0xFB, &gpiop->pclrr_qspi);
+ if (val & 0x80)
+ writeb(0x01, &gpiop->ppd_qspi);
+ else
+ writeb(0xFE, &gpiop->pclrr_qspi);
+ writeb(0x04, &gpiop->ppd_qspi);
+ val <<= 1;
+ }
+ if (bytecount % len_40 == 0) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ WATCHDOG_RESET();
+#endif
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+ putc('.'); /* let them know we are alive */
+#endif
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+ if (ctrlc())
+ return FPGA_FAIL;
+#endif
+ }
+ }
+ return FPGA_SUCCESS;
+}
+
+/*
+ * Note that these are pointers to code that is in Flash. They will be
+ * relocated at runtime.
+ * FIXME: relocation not yet working for coldfire, see below!
+ */
+Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
+ xilinx_pre_config_fn,
+ xilinx_pgm_fn,
+ xilinx_clk_fn,
+ xilinx_init_fn,
+ xilinx_done_fn,
+ xilinx_wr_fn,
+ 0,
+ xilinx_fastwr_fn
+};
+
+Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
+ {Xilinx_Spartan3,
+ slave_serial,
+ XILINX_XC3S4000_SIZE,
+ (void *)&xilinx_fns,
+ 0}
+};
+
+/* Initialize the fpga. Return 1 on success, 0 on failure. */
+int astro5373l_xilinx_load(void)
+{
+ int i;
+
+ fpga_init();
+
+ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+ /*
+ * I did not yet manage to get relocation work properly,
+ * so set stuff here instead of static initialisation:
+ */
+ xilinx_fns.pre = xilinx_pre_config_fn;
+ xilinx_fns.pgm = xilinx_pgm_fn;
+ xilinx_fns.clk = xilinx_clk_fn;
+ xilinx_fns.init = xilinx_init_fn;
+ xilinx_fns.done = xilinx_done_fn;
+ xilinx_fns.wr = xilinx_wr_fn;
+ xilinx_fns.bwr = xilinx_fastwr_fn;
+ xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
+ fpga_add(fpga_xilinx, &xilinx_fpga[i]);
+ }
+ return 1;
+}
--- /dev/null
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/m5329.h>
+#include <asm/immap_5329.h>
+#include <asm/io.h>
+
+/* needed for astro bus: */
+#include <asm/uart.h>
+#include "astro.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+extern void uart_port_conf(void);
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("ASTRO MCF5373L (Urmel) Board\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+ sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
+
+ /*
+ * GPIO configuration for bus should be set correctly from reset,
+ * so we do not care! First, set up address space: at this point,
+ * we should be running from internal SRAM;
+ * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
+ * and do not care where it is
+ */
+ __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
+ &sdp->cs0);
+ __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
+ &sdp->cs1);
+ /*
+ * I am not sure from the data sheet, but it seems burst length
+ * has to be 8 for the 16 bit data bus we use;
+ * so these values are for BL = 8
+ */
+ __raw_writel(0x33211530, &sdp->cfg1);
+ __raw_writel(0x56570000, &sdp->cfg2);
+ /* send PrechargeALL, REF and IREF remain cleared! */
+ __raw_writel(0xE1462C02, &sdp->ctrl);
+ udelay(1);
+ /* refresh SDRAM twice */
+ __raw_writel(0xE1462C04, &sdp->ctrl);
+ udelay(1);
+ __raw_writel(0xE1462C04, &sdp->ctrl);
+ /* init MR */
+ __raw_writel(0x008D0000, &sdp->mode);
+ /* initialize EMR */
+ __raw_writel(0x80010000, &sdp->mode);
+ /* wait until DLL is locked */
+ udelay(1);
+ /*
+ * enable automatic refresh, lock mode register,
+ * clear iref and ipall
+ */
+ __raw_writel(0x71462C00, &sdp->ctrl);
+ /* Dummy write to start SDRAM */
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+#endif
+
+ /*
+ * for get_ram_size() to work, both CS areas have to be
+ * configured, i.e. CS1 has to be explicitely disabled, else
+ * probing for memory will cause the SDRAM bus to hang!
+ * (Do not rely on the SDCS register(s) being set to 0x00000000
+ * during reset as stated in the data sheet.)
+ */
+ return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE,
+ 0x80000000 - CONFIG_SYS_SDRAM_BASE);
+}
+
+#define UART_BASE MMAP_UART0
+int rs_serial_init(int port, int baud)
+{
+ uart_t *uart;
+ u32 counter;
+
+ switch (port) {
+ case 0:
+ uart = (uart_t *)(MMAP_UART0);
+ break;
+ case 1:
+ uart = (uart_t *)(MMAP_UART1);
+ break;
+ case 2:
+ uart = (uart_t *)(MMAP_UART2);
+ break;
+ default:
+ uart = (uart_t *)(MMAP_UART0);
+ }
+
+ uart_port_conf();
+
+ /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
+ writeb(UART_UCR_RESET_RX, &uart->ucr);
+ writeb(UART_UCR_RESET_TX, &uart->ucr);
+ writeb(UART_UCR_RESET_ERROR, &uart->ucr);
+ writeb(UART_UCR_RESET_MR, &uart->ucr);
+ __asm__ ("nop");
+
+ writeb(0, &uart->uimr);
+
+ /* write to CSR: RX/TX baud rate from timers */
+ writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
+
+ writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
+ writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
+
+ /* Setting up BaudRate */
+ counter = (u32) (gd->bus_clk / (baud));
+ counter >>= 5;
+
+ /* write to CTUR: divide counter upper byte */
+ writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1);
+ /* write to CTLR: divide counter lower byte */
+ writeb((u8) (counter & 0x00ff), &uart->ubg2);
+
+ writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
+
+ return 0;
+}
+
+void astro_put_char(char ch)
+{
+ uart_t *uart;
+ unsigned long timer;
+
+ uart = (uart_t *)(MMAP_UART0);
+ /*
+ * Wait for last character to go. Timeout of 6ms should
+ * be enough for our lowest baud rate of 2400.
+ */
+ timer = get_timer(0);
+ while (get_timer(timer) < 6) {
+ if (readb(&uart->usr) & UART_USR_TXRDY)
+ break;
+ }
+ writeb(ch, &uart->utb);
+
+ return;
+}
+
+int astro_is_char(void)
+{
+ uart_t *uart;
+
+ uart = (uart_t *)(MMAP_UART0);
+ return readb(&uart->usr) & UART_USR_RXRDY;
+}
+
+int astro_get_char(void)
+{
+ uart_t *uart;
+
+ uart = (uart_t *)(MMAP_UART0);
+ while (!(readb(&uart->usr) & UART_USR_RXRDY)) ;
+ return readb(&uart->urb);
+}
+
+int misc_init_r(void)
+{
+ int retval = 0;
+
+ puts("Configure Xilinx FPGA...");
+ retval = astro5373l_xilinx_load();
+ if (!retval) {
+ puts("failed!\n");
+ return retval;
+ }
+ puts("done\n");
+
+ puts("Configure Altera FPGA...");
+ retval = astro5373l_altera_load();
+ if (!retval) {
+ puts("failed!\n");
+ return retval;
+ }
+ puts("done\n");
+
+ return retval;
+}
* MA 02111-1307 USA
*/
-OUTPUT_ARCH(powerpc)
+OUTPUT_ARCH(m68k)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ arch/m68k/cpu/mcf532x/start.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/lib/interrupts.o (.text)
+ common/dlmalloc.o (.text)
+ lib/zlib.o (.text)
- common/env_embedded.o(.text)
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text)
*(.text)
+/* *(.fixup)*/
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
+ . = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
+
.reloc :
{
+ __got_start = .;
*(.got)
+ __got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
- . = ALIGN(4096);
+ . = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
- . = ALIGN(4096);
+ . = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
+ _sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
}
_end = . ;
PROVIDE (end = .);
* is something else than 0x00000000.
*/
-#if defined(CONFIG_MPC5200)
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
return dramsize;
}
-#elif defined(CONFIG_MGT5100)
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup and enable SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
- *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff; /* 2G */
- *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
- /* address select register */
- *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
- __asm__ volatile ("sync");
-
- /* find RAM size */
- sdram_start(0);
- test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* set SDRAM end address according to size */
- *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* Retrieve amount of SDRAM available */
- dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
-
int checkboard (void)
{
#if defined (CONFIG_TQM5200)
* Note that CS_BOOT cannot be cleared when
* executing in flash.
*/
-#if defined(CONFIG_MGT5100)
- *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
- *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-#endif
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}
#define SDRAM_DDR 0 /* is SDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */
/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
#define SDRAM_CONFIG2 0x8AD70000
/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE 0x008D0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xC2222600
-#define SDRAM_CONFIG2 0x88B70004
-#define SDRAM_ADDRSEL 0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
#include <config.h>
#include <command.h>
#include <asm/blackfin.h>
-#include <asm-blackfin/string.h>
+#include <asm/string.h>
#ifdef CONFIG_BF537_STAMP_LEDCMD
/* Define the command usage in a reusable way */
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
* is something else than 0x00000000.
*/
-#if defined(CONFIG_MPC5200)
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
return dramsize + dramsize2;
}
-#elif defined(CONFIG_MGT5100)
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup and enable SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
- *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
- *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
- /* address select register */
- *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
- __asm__ volatile ("sync");
-
- /* find RAM size */
- sdram_start(0);
- test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* set SDRAM end address according to size */
- *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* Retrieve amount of SDRAM available */
- dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
-
int checkboard (void)
{
puts ("Board: CANMB\n");
#define SDRAM_DDR 0 /* is SDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE 0x008D0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xC2222600
-#define SDRAM_CONFIG2 0x88B70004
-#define SDRAM_ADDRSEL 0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
return 0;
}
-#ifdef CONFIG_SMC91111
+#ifdef CONFIG_SMC911X
int board_eth_init(bd_t *bis)
{
- return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
}
#endif
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
.plt : { *(.plt) }
.text :
{
- cpu/mpc5xxx/start.o (.text)
+ arch/ppc/cpu/mpc5xxx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf52x2/start.o (.text)
- cpu/mcf52x2/cpu_init.o (.text)
- lib_m68k/traps.o (.text)
- cpu/mcf52x2/interrupts.o (.text)
+ arch/m68k/cpu/mcf52x2/start.o (.text)
+ arch/m68k/cpu/mcf52x2/cpu_init.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
common/env_embedded.o(.text)
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
- * in cpu/ppc4xx
+ * in arch/ppc/cpu/ppc4xx
*/
sdram_init();
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
- * in cpu/ppc4xx
+ * in arch/ppc/cpu/ppc4xx
*/
sdram_init();
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(2) |
DAVINCI_ABCR_ASIZE_8BIT),
- &davinci_emif_regs->AB2CR);
+ &davinci_emif_regs->ab2cr);
#endif
/* arch number of the board */
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Board-specific low level initialization code. Called at the very end
- * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
* initialization required.
*
* This program is free software; you can redistribute it and/or
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Board-specific low level initialization code. Called at the very end
- * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
* initialization required.
*
* This program is free software; you can redistribute it and/or
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Board-specific low level initialization code. Called at the very end
- * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
* initialization required.
*
* This program is free software; you can redistribute it and/or
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Board-specific low level initialization code. Called at the very end
- * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
* initialization required.
*
* For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer
#define BCSR_PCMCIA_PC0DRVEN 0x0010
#define BCSR_PCMCIA_PC0RST 0x0080
-/* In cpu/mips/cpu.c */
+/* In arch/mips/cpu/cpu.c */
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
int checkboard (void)
#
TEXT_BASE = 0x38040000
-CFLAGS_dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing
+CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing
PLATFORM_RELFLAGS += -fvisibility=hidden
PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
PLATFORM_LDFLAGS += -pic --emit-relocs -Bsymbolic -Bsymbolic-functions
-LDSCRIPT := $(SRCTREE)/cpu/arm920t/ep93xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
ifdef CONFIG_EDB9301
TEXT_BASE = 0x05700000
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
- * in cpu/ppc4xx
+ * in arch/ppc/cpu/ppc4xx
*/
sdram_init();
#define SDRAM_DDR 1 /* is DDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
. = env_offset;
common/env_embedded.o(.text)
*/
#include <ppc_asm.tmpl>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
#include <config.h>
/*
#define SDRAM_DDR 1 /* is DDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
#define SDRAM_DDR 1 /* is DDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
*/
#include <ppc_asm.tmpl>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
#include <config.h>
/*
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf52x2/start.o (.text)
- lib_m68k/traps.o (.text)
- cpu/mcf52x2/interrupts.o (.text)
+ arch/m68k/cpu/mcf52x2/start.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
- cpu/mpc8xx/serial.o (.text)
- cpu/mpc8xx/cpu_init.o (.text)
- cpu/mpc8xx/speed.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc8xx/serial.o (.text)
+ arch/ppc/cpu/mpc8xx/cpu_init.o (.text)
+ arch/ppc/cpu/mpc8xx/speed.o (.text)
common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
- cpu/mpc8xx/cpu.o (.text)
- cpu/mpc8xx/cpu_init.o (.text)
- cpu/mpc8xx/speed.o (.text)
- cpu/mpc8xx/serial.o (.text)
- lib_ppc/extable.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/string.o (.text)
- lib_generic/crc32.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc8xx/cpu.o (.text)
+ arch/ppc/cpu/mpc8xx/cpu_init.o (.text)
+ arch/ppc/cpu/mpc8xx/speed.o (.text)
+ arch/ppc/cpu/mpc8xx/serial.o (.text)
+ arch/ppc/lib/extable.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/string.o (.text)
+ lib/crc32.o (.text)
common/dlmalloc.o (.text)
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
/*. = DEFINED(env_offset) ? env_offset : .;*/
common/env_embedded.o (.ppcenv)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
COBJS-${CONFIG_FSL_VIA} += cds_via.o
COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o
COBJS-${CONFIG_FSL_PIXIS} += pixis.o
+COBJS-${CONFIG_FSL_NGPIXIS} += ngpixis.o
COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o
COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o
COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o
--- /dev/null
+/**
+ * Copyright 2010 Freescale Semiconductor
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ *
+ * A "switch" is black rectangular block on the motherboard. It contains
+ * eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that
+ * shadow the actual physical switches. There is also another set of
+ * registers (ENx) that tell the ngPIXIS which bits of SWx should actually be
+ * used to override the values of the bits in the physical switches.
+ *
+ * The following macros need to be defined:
+ *
+ * PIXIS_BASE - The virtual address of the base of the PIXIS register map
+ *
+ * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value
+ * is used in the PIXIS_SW() macro to determine which offset in
+ * the PIXIS register map corresponds to the physical switch that controls
+ * the boot bank.
+ *
+ * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use.
+ *
+ * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK.
+ *
+ * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to
+ * boot from the alternate bank.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+
+#include "ngpixis.h"
+
+/*
+ * Reset the board. This ignores the ENx registers.
+ */
+void pixis_reset(void)
+{
+ out_8(&pixis->rst, 0);
+
+ while (1);
+}
+
+/*
+ * Reset the board. Like pixis_reset(), but it honors the ENx registers.
+ */
+void pixis_bank_reset(void)
+{
+ out_8(&pixis->vctl, 0);
+ out_8(&pixis->vctl, 1);
+
+ while (1);
+}
+
+/**
+ * Set the boot bank to the power-on default bank
+ */
+void clear_altbank(void)
+{
+ /* Tell the ngPIXIS to use this the bits in the physical switch for the
+ * boot bank value, instead of the SWx register. We need to be careful
+ * only to set the bits in SWx that correspond to the boot bank.
+ */
+ clrbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void set_altbank(void)
+{
+ /* Program the alternate bank number into the SWx register.
+ */
+ clrsetbits_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK,
+ PIXIS_LBMAP_ALTBANK);
+
+ /* Tell the ngPIXIS to use this the bits in the SWx register for the
+ * boot bank value, instead of the physical switch. We need to be
+ * careful only to set the bits in SWx that correspond to the boot bank.
+ */
+ setbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
+}
+
+
+int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int i;
+ char *p_altbank = NULL;
+ char *unknown_param = NULL;
+
+ /* No args is a simple reset request.
+ */
+ if (argc <= 1)
+ pixis_reset();
+
+ for (i = 1; i < argc; i++) {
+ if (strcmp(argv[i], "altbank") == 0) {
+ p_altbank = argv[i];
+ continue;
+ }
+
+ unknown_param = argv[i];
+ }
+
+ if (unknown_param) {
+ printf("Invalid option: %s\n", unknown_param);
+ return 1;
+ }
+
+ if (p_altbank)
+ set_altbank();
+ else
+ clear_altbank();
+
+ pixis_bank_reset();
+
+ /* Shouldn't be reached. */
+ return 0;
+}
+
+U_BOOT_CMD(
+ pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
+ "Reset the board using the FPGA sequencer",
+ "- hard reset to default bank\n"
+ "pixis_reset altbank - reset to alternate bank\n"
+ );
--- /dev/null
+/**
+ * Copyright 2010 Freescale Semiconductor
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/* ngPIXIS register set. Hopefully, this won't change too much over time.
+ * Feel free to add board-specific #ifdefs where necessary.
+ */
+typedef struct ngpixis {
+ u8 id;
+ u8 arch;
+ u8 scver;
+ u8 csr;
+ u8 rst;
+ u8 res1;
+ u8 aux;
+ u8 spd;
+ u8 brdcfg0;
+ u8 dma;
+ u8 addr;
+ u8 res2[2];
+ u8 data;
+ u8 led;
+ u8 res3;
+ u8 vctl;
+ u8 vstat;
+ u8 vcfgen0;
+ u8 res4;
+ u8 ocmcsr;
+ u8 ocmmsg;
+ u8 gmdbg;
+ u8 res5[2];
+ u8 sclk[3];
+ u8 dclk[3];
+ u8 watch;
+ struct {
+ u8 sw;
+ u8 en;
+ } s[8];
+} ngpixis_t __attribute__ ((aligned(1)));
+
+/* Pointer to the PIXIS register set */
+#define pixis ((ngpixis_t *)PIXIS_BASE)
+
+/* The PIXIS SW register that corresponds to board switch X, where x >= 1 */
+#define PIXIS_SW(x) (pixis->s[(x) - 1].sw)
+
+/* The PIXIS EN register that corresponds to board switch X, where x >= 1 */
+#define PIXIS_EN(x) (pixis->s[(x) - 1].en)
/*
- * Copyright 2006 Freescale Semiconductor
+ * Copyright 2006,2010 Freescale Semiconductor
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
#include <common.h>
#include <command.h>
-#include <watchdog.h>
-#include <asm/cache.h>
#include <asm/io.h>
-#include "pixis.h"
-
-
-static ulong strfractoint(uchar *strptr);
-
+#define pixis_base (u8 *)PIXIS_BASE
/*
* Simple board reset.
*/
void pixis_reset(void)
{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
out_8(pixis_base + PIXIS_RST, 0);
-}
+ while (1);
+}
/*
* Per table 27, page 58 of MPC8641HPCN spec.
*/
-int set_px_sysclk(ulong sysclk)
+static int set_px_sysclk(unsigned long sysclk)
{
u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
switch (sysclk) {
case 33:
return 1;
}
-
-int set_px_mpxpll(ulong mpxpll)
+/* Set the CFG_SYSPLL bits
+ *
+ * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
+ * read_from_px_regs() is called.
+ */
+static int set_px_mpxpll(unsigned long mpxpll)
{
- u8 tmp;
- u8 val;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
switch (mpxpll) {
case 2:
case 4:
case 12:
case 14:
case 16:
- val = (u8) mpxpll;
- break;
- default:
- printf("Unsupported MPXPLL ratio.\n");
- return 0;
+ clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
+ return 1;
}
- tmp = in_8(pixis_base + PIXIS_VSPEED1);
- tmp = (tmp & 0xF0) | (val & 0x0F);
- out_8(pixis_base + PIXIS_VSPEED1, tmp);
-
- return 1;
+ printf("Unsupported MPXPLL ratio.\n");
+ return 0;
}
-
-int set_px_corepll(ulong corepll)
+static int set_px_corepll(unsigned long corepll)
{
- u8 tmp;
u8 val;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- switch ((int)corepll) {
+ switch (corepll) {
case 20:
val = 0x08;
break;
return 0;
}
- tmp = in_8(pixis_base + PIXIS_VSPEED0);
- tmp = (tmp & 0xE0) | (val & 0x1F);
- out_8(pixis_base + PIXIS_VSPEED0, tmp);
-
+ clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
return 1;
}
+#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
+#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
+#endif
-void read_from_px_regs(int set)
+/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
+ *
+ * The PIXIS can be programmed to look at either the on-board dip switches
+ * or various other PIXIS registers to determine the values for COREPLL,
+ * MPXPLL, and SYSCLK.
+ *
+ * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
+ * register that tells the pixis to use the various PIXIS register.
+ */
+static void read_from_px_regs(int set)
{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
if (set)
- tmp = tmp | mask;
+ tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
else
- tmp = tmp & ~mask;
+ tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
+
out_8(pixis_base + PIXIS_VCFGEN0, tmp);
}
+/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
+ * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
+ */
+#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
+#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
+#endif
-void read_from_px_regs_altbank(int set)
+/* Configure the source of the boot location
+ *
+ * The PIXIS can be programmed to look at either the on-board dip switches
+ * or the PX_VBOOT[LBMAP] register to determine where we should boot.
+ *
+ * If we want to boot from the alternate boot bank, we need to tell the PIXIS
+ * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
+ */
+static void read_from_px_regs_altbank(int set)
{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
if (set)
- tmp = tmp | mask;
+ tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
else
- tmp = tmp & ~mask;
+ tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
+
out_8(pixis_base + PIXIS_VCFGEN1, tmp);
}
+/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
+ * tells the PIXIS what the alternate flash bank is.
+ *
+ * Note that it's not really a mask. It contains the actual LBMAP bits that
+ * must be set to select the alternate bank. This code assumes that the
+ * primary bank has these bits set to 0, and the alternate bank has these
+ * bits set to 1.
+ */
#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
#endif
-void clear_altbank(void)
+/* Tell the PIXIS to boot from the default flash bank
+ *
+ * Program the default flash bank into the VBOOT register. This register is
+ * used only if PX_VCFGEN1[FLASH]=1.
+ */
+static void clear_altbank(void)
{
- u8 tmp;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- tmp = in_8(pixis_base + PIXIS_VBOOT);
- tmp &= ~CONFIG_SYS_PIXIS_VBOOT_MASK;
-
- out_8(pixis_base + PIXIS_VBOOT, tmp);
+ clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
}
-
-void set_altbank(void)
+/* Tell the PIXIS to boot from the alternate flash bank
+ *
+ * Program the alternate flash bank into the VBOOT register. This register is
+ * used only if PX_VCFGEN1[FLASH]=1.
+ */
+static void set_altbank(void)
{
- u8 tmp;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- tmp = in_8(pixis_base + PIXIS_VBOOT);
- tmp |= CONFIG_SYS_PIXIS_VBOOT_MASK;
-
- out_8(pixis_base + PIXIS_VBOOT, tmp);
+ setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
}
-
-void set_px_go(void)
+/* Reset the board with watchdog disabled.
+ *
+ * This respects the altbank setting.
+ */
+static void set_px_go(void)
{
- u8 tmp;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
+ /* Disable the VELA sequencer and watchdog */
+ clrbits_8(pixis_base + PIXIS_VCTL, 9);
- tmp = in_8(pixis_base + PIXIS_VCTL);
- tmp = tmp & 0x1E; /* clear GO bit */
- out_8(pixis_base + PIXIS_VCTL, tmp);
+ /* Reboot by starting the VELA sequencer */
+ setbits_8(pixis_base + PIXIS_VCTL, 0x1);
- tmp = in_8(pixis_base + PIXIS_VCTL);
- tmp = tmp | 0x01; /* set GO bit - start reset sequencer */
- out_8(pixis_base + PIXIS_VCTL, tmp);
+ while (1);
}
-
-void set_px_go_with_watchdog(void)
+/* Reset the board with watchdog enabled.
+ *
+ * This respects the altbank setting.
+ */
+static void set_px_go_with_watchdog(void)
{
- u8 tmp;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
+ /* Disable the VELA sequencer */
+ clrbits_8(pixis_base + PIXIS_VCTL, 1);
- tmp = in_8(pixis_base + PIXIS_VCTL);
- tmp = tmp & 0x1E;
- out_8(pixis_base + PIXIS_VCTL, tmp);
+ /* Enable the watchdog and reboot by starting the VELA sequencer */
+ setbits_8(pixis_base + PIXIS_VCTL, 0x9);
- tmp = in_8(pixis_base + PIXIS_VCTL);
- tmp = tmp | 0x09;
- out_8(pixis_base + PIXIS_VCTL, tmp);
+ while (1);
}
-
-int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
- int flag, int argc, char *argv[])
+/* Disable the watchdog
+ *
+ */
+static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *argv[])
{
- u8 tmp;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- tmp = in_8(pixis_base + PIXIS_VCTL);
- tmp = tmp & 0x1E;
- out_8(pixis_base + PIXIS_VCTL, tmp);
-
- /* setting VCTL[WDEN] to 0 to disable watch dog */
- tmp = in_8(pixis_base + PIXIS_VCTL);
- tmp &= ~0x08;
- out_8(pixis_base + PIXIS_VCTL, tmp);
+ /* Disable the VELA sequencer and the watchdog */
+ clrbits_8(pixis_base + PIXIS_VCTL, 9);
return 0;
}
);
#ifdef CONFIG_PIXIS_SGMII_CMD
-int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+
+/* Enable or disable SGMII mode for a TSEC
+ */
+static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int which_tsec = -1;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- uchar mask;
- uchar switch_mask;
+ unsigned char mask;
+ unsigned char switch_mask;
- if (argc > 2)
- if (strcmp(argv[1], "all") != 0)
- which_tsec = simple_strtoul(argv[1], NULL, 0);
+ if ((argc > 2) && (strcmp(argv[1], "all") != 0))
+ which_tsec = simple_strtoul(argv[1], NULL, 0);
switch (which_tsec) {
#ifdef CONFIG_TSEC1
" off - disables SGMII\n"
" switch - use switch settings"
);
+
#endif
/*
* FPGA register values.
* input: strptr i.e. argv[2]
*/
-
-static ulong strfractoint(uchar *strptr)
+static unsigned long strfractoint(char *strptr)
{
- int i, j, retval;
+ int i, j;
int mulconst;
- int intarr_len = 0, decarr_len = 0, no_dec = 0;
- ulong intval = 0, decval = 0;
- uchar intarr[3], decarr[3];
+ int intarr_len, no_dec = 0;
+ unsigned long intval = 0, decval = 0;
+ char intarr[3], decarr[3];
/* Assign the integer part to intarr[]
* If there is no decimal point i.e.
j++;
}
- decarr_len = j;
decarr[j] = '\0';
mulconst = 1;
- for (i = 0; i < decarr_len; i++)
+ for (i = 0; i < j; i++)
mulconst *= 10;
- decval = simple_strtoul((char *)decarr, NULL, 10);
+ decval = simple_strtoul(decarr, NULL, 10);
}
- intval = simple_strtoul((char *)intarr, NULL, 10);
+ intval = simple_strtoul(intarr, NULL, 10);
intval = intval * mulconst;
- retval = intval + decval;
-
- return retval;
+ return intval + decval;
}
-
-int
-pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned int i;
char *p_cf = NULL;
char *p_cf_mpxpll = NULL;
char *p_altbank = NULL;
char *p_wd = NULL;
- unsigned int unknown_param = 0;
+ int unknown_param = 0;
/*
* No args is a simple reset request.
*/
read_from_px_regs(0);
- if (p_altbank) {
+ if (p_altbank)
read_from_px_regs_altbank(0);
- }
+
clear_altbank();
/*
unsigned long mpxpll;
sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
- corepll = strfractoint((uchar *) p_cf_corepll);
+ corepll = strfractoint(p_cf_corepll);
mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
if (!(set_px_sysclk(sysclk)
/*
* Reset with watchdog specified.
*/
- if (p_wd) {
+ if (p_wd)
set_px_go_with_watchdog();
- } else {
+ else
set_px_go();
- }
/*
* Shouldn't be reached.
+++ /dev/null
-/*
- * Copyright 2006 Freescale Semiconductor
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-extern void pixis_reset(void);
-extern int set_px_sysclk(ulong sysclk);
-extern int set_px_mpxpll(ulong mpxpll);
-extern int set_px_corepll(ulong corepll);
-extern void read_from_px_regs(int set);
-extern void read_from_px_regs_altbank(int set);
-extern void set_altbank(void);
-extern void set_px_go(void);
-extern void set_px_go_with_watchdog(void);
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf52x2/start.o (.text)
- cpu/mcf52x2/libmcf52x2.a (.text)
- lib_m68k/libm68k.a (.text)
+ arch/m68k/cpu/mcf52x2/start.o (.text)
+ arch/m68k/cpu/mcf52x2/libmcf52x2.a (.text)
+ arch/m68k/lib/libm68k.a (.text)
common/dlmalloc.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf5227x/start.o (.text)
- cpu/mcf5227x/libmcf5227x.a (.text)
- lib_m68k/libm68k.a (.text)
- lib_generic/libgeneric.a (.text)
+ arch/m68k/cpu/mcf5227x/start.o (.text)
+ arch/m68k/cpu/mcf5227x/libmcf5227x.a (.text)
+ arch/m68k/lib/libm68k.a (.text)
+ lib/libgeneric.a (.text)
common/cmd_mem.o (.text)
common/main.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf5227x/start.o (.text)
+ arch/m68k/cpu/mcf5227x/start.o (.text)
*(.text)
*(.fixup)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf523x/start.o (.text)
- cpu/mcf523x/cpu_init.o (.text)
- lib_m68k/traps.o (.text)
- lib_m68k/interrupts.o (.text)
+ arch/m68k/cpu/mcf523x/start.o (.text)
+ arch/m68k/cpu/mcf523x/cpu_init.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/lib/interrupts.o (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf523x/start.o (.text)
- cpu/mcf523x/cpu.o (.text)
- cpu/mcf523x/cpu_init.o (.text)
- cpu/mcf523x/interrupts.o (.text)
- cpu/mcf523x/speed.o (.text)
- lib_m68k/libm68k.a (.text)
+ arch/m68k/cpu/mcf523x/start.o (.text)
+ arch/m68k/cpu/mcf523x/cpu.o (.text)
+ arch/m68k/cpu/mcf523x/cpu_init.o (.text)
+ arch/m68k/cpu/mcf523x/interrupts.o (.text)
+ arch/m68k/cpu/mcf523x/speed.o (.text)
+ arch/m68k/lib/libm68k.a (.text)
common/dlmalloc.o (.text)
common/cmd_bootm.o (.text)
common/cmd_flash.o (.text)
common/cmd_mem.o (.text)
common/console.o (.text)
common/main.o (.text)
- lib_generic/libgeneric.a (.text)
+ lib/libgeneric.a (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf52x2/start.o (.text)
- lib_m68k/traps.o (.text)
- cpu/mcf52x2/interrupts.o (.text)
+ arch/m68k/cpu/mcf52x2/start.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf52x2/start.o (.text)
- lib_m68k/traps.o (.text)
- cpu/mcf52x2/interrupts.o (.text)
+ arch/m68k/cpu/mcf52x2/start.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf52x2/start.o (.text)
- lib_m68k/traps.o (.text)
- cpu/mcf52x2/interrupts.o (.text)
+ arch/m68k/cpu/mcf52x2/start.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
MCF_GPIO_SDRAM_SDCS_11);
+ asm(" nop");
/*
* Check to see if the SDRAM has already been initialized
if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
/* Initialize DRAM Control Register: DCR */
mbar_writeShort(MCF_SDRAMC_DCR,
- MCF_SDRAMC_DCR_RTIM(0x01)
- | MCF_SDRAMC_DCR_RC(0x30));
+ MCF_SDRAMC_DCR_RTIM(2)
+ | MCF_SDRAMC_DCR_RC(0x2E));
+ asm(" nop");
/*
* Initialize DACR0
| MCF_SDRAMC_DACRn_CASL(1)
| MCF_SDRAMC_DACRn_CBM(3)
| MCF_SDRAMC_DACRn_PS(0));
+ asm(" nop");
/* Initialize DMR0 */
mbar_writeLong(MCF_SDRAMC_DMR0,
MCF_SDRAMC_DMRn_BAM_16M
| MCF_SDRAMC_DMRn_V);
+ asm(" nop");
/* Set IP bit in DACR */
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
| MCF_SDRAMC_DACRn_IP);
+ asm(" nop");
/* Wait at least 20ns to allow banks to precharge */
for (i = 0; i < 5; i++)
/* Write to this block to initiate precharge */
*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
+ asm(" nop");
/* Set RE bit in DACR */
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
/* Finish the configuration by issuing the MRS */
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
| MCF_SDRAMC_DACRn_MRS);
+ asm(" nop");
/*
* Write to the SDRAM Mode Register A0-A11 = 0x400
* Burst Length = 1
*/
*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
+ asm(" nop");
}
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf52x2/start.o (.text)
- lib_m68k/traps.o (.text)
- cpu/mcf52x2/interrupts.o (.text)
+ arch/m68k/cpu/mcf52x2/start.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf52x2/start.o (.text)
- lib_m68k/traps.o (.text)
- cpu/mcf52x2/interrupts.o (.text)
+ arch/m68k/cpu/mcf52x2/start.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf52x2/start.o (.text)
+ arch/m68k/cpu/mcf52x2/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/string.o (.text)
- lib_generic/zlib.o (.text)
+ lib/string.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf52x2/start.o (.text)
+ arch/m68k/cpu/mcf52x2/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/string.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/string.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf532x/start.o (.text)
- cpu/mcf532x/libmcf532x.a (.text)
- lib_m68k/libm68k.a (.text)
+ arch/m68k/cpu/mcf532x/start.o (.text)
+ arch/m68k/cpu/mcf532x/libmcf532x.a (.text)
+ arch/m68k/lib/libm68k.a (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf532x/start.o (.text)
- lib_m68k/traps.o (.text)
- lib_m68k/interrupts.o (.text)
+ arch/m68k/cpu/mcf532x/start.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/lib/interrupts.o (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf532x/start.o (.text)
- lib_m68k/traps.o (.text)
- lib_m68k/interrupts.o (.text)
+ arch/m68k/cpu/mcf532x/start.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/lib/interrupts.o (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf5445x/start.o (.text)
- cpu/mcf5445x/libmcf5445x.a (.text)
- lib_m68k/libm68k.a (.text)
+ arch/m68k/cpu/mcf5445x/start.o (.text)
+ arch/m68k/cpu/mcf5445x/libmcf5445x.a (.text)
+ arch/m68k/lib/libm68k.a (.text)
common/cmd_flash.o (.text)
common/dlmalloc.o (.text)
common/main.o (.text)
common/image.o (.text)
- lib_generic/libgeneric.a (.text)
+ lib/libgeneric.a (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf5445x/start.o (.text)
-/* cpu/mcf5445x/cpu_init.o (.text)
- cpu/mcf5445x/cpu.o (.text)
- cpu/mcf5445x/dspi.o (.text)
- cpu/mcf5445x/interrupt.o (.text)
- cpu/mcf5445x/speed.o (.text)
- lib_m68k/board.o (.text)
+ arch/m68k/cpu/mcf5445x/start.o (.text)
+/* arch/m68k/cpu/mcf5445x/cpu_init.o (.text)
+ arch/m68k/cpu/mcf5445x/cpu.o (.text)
+ arch/m68k/cpu/mcf5445x/dspi.o (.text)
+ arch/m68k/cpu/mcf5445x/interrupt.o (.text)
+ arch/m68k/cpu/mcf5445x/speed.o (.text)
+ arch/m68k/lib/board.o (.text)
common/serial.o (.text)
common/console.o (.text)
- lib_generic/display_options.o (.text)
+ lib/display_options.o (.text)
board/freescale/m54455evb/m54455evb.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_MASK) | 0x10;
+ gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
gpio->par_feci2c |=
(gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
info->flash_id = 0x01000000;
info->portwidth = 1;
info->chipwidth = 1;
- info->buffer_size = 32;
+ info->buffer_size = 1;
info->erase_blk_tout = 16384;
info->write_tout = 2;
info->buffer_write_tout = 5;
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf5445x/start.o (.text)
- lib_m68k/traps.o (.text)
- lib_m68k/interrupts.o (.text)
+ arch/m68k/cpu/mcf5445x/start.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/lib/interrupts.o (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf5445x/start.o (.text)
- lib_m68k/traps.o (.text)
- lib_m68k/interrupts.o (.text)
+ arch/m68k/cpu/mcf5445x/start.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/lib/interrupts.o (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
*(.text)
*(.fixup)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf5445x/start.o (.text)
+ arch/m68k/cpu/mcf5445x/start.o (.text)
*(.text)
*(.fixup)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf547x_8x/start.o (.text)
- lib_m68k/traps.o (.text)
- lib_m68k/interrupts.o (.text)
+ arch/m68k/cpu/mcf547x_8x/start.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/lib/interrupts.o (.text)
common/dlmalloc.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf547x_8x/start.o (.text)
- lib_m68k/traps.o (.text)
- lib_m68k/interrupts.o (.text)
+ arch/m68k/cpu/mcf547x_8x/start.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/lib/interrupts.o (.text)
common/dlmalloc.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
* We will over-ride the env_init called in board_init_f
* This is really a work-around because, the HLP bank 1
* where NVRAM resides is not visible during board_init_f
- * (lib_ppc/board.c)
+ * (arch/ppc/lib/board.c)
* Alternatively, we could use the I2C EEPROM at start-up to configure
* and enable all HLP banks and not just HLP 0 as is being done for
* Taiga Rev. 2.
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
ifndef NAND_SPL
ifeq ($(CONFIG_MK_NAND), y)
TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
-LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
+LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
endif
endif
#include <netdev.h>
#include <sata.h>
-#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
phys_size_t fixed_sdram(void);
#include <tsec.h>
#include <netdev.h>
-#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
int checkboard (void)
ifndef NAND_SPL
ifeq ($(CONFIG_MK_NAND), y)
TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
-LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
+LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
endif
endif
#include <tsec.h>
#include <netdev.h>
-#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
long int fixed_sdram(void);
#include <spd_sdram.h>
#include <netdev.h>
-#include "../common/pixis.h"
-
void sdram_init(void);
phys_size_t fixed_sdram(void);
void mpc8610hpcd_diu_init(void);
dram_size = fixed_sdram();
#endif
+ setup_ddr_bat(dram_size);
+
puts(" DDR: ");
return dram_size;
}
#ifdef CONFIG_FSL_DIU_FB
-#include "../common/pixis.h"
#include "../common/fsl_diu_fb.h"
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
.plt : { *(.plt) }
.text :
{
- cpu/mpc86xx/start.o (.text)
- cpu/mpc86xx/traps.o (.text)
- cpu/mpc86xx/interrupts.o (.text)
- cpu/mpc86xx/cpu_init.o (.text)
- cpu/mpc86xx/cpu.o (.text)
- cpu/mpc86xx/speed.o (.text)
+ arch/ppc/cpu/mpc86xx/start.o (.text)
+ arch/ppc/cpu/mpc86xx/traps.o (.text)
+ arch/ppc/cpu/mpc86xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu_init.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu.o (.text)
+ arch/ppc/cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
+ lib/zlib.o (.text)
*(.text)
*(.got1)
}
#include <fdt_support.h>
#include <netdev.h>
-#include "../common/pixis.h"
-
phys_size_t fixed_sdram(void);
int board_early_init_f(void)
dram_size = fixed_sdram();
#endif
+ setup_ddr_bat(dram_size);
+
puts(" DDR: ");
return dram_size;
}
.plt : { *(.plt) }
.text :
{
- cpu/mpc86xx/start.o (.text)
- cpu/mpc86xx/traps.o (.text)
- cpu/mpc86xx/interrupts.o (.text)
- cpu/mpc86xx/cpu_init.o (.text)
- cpu/mpc86xx/cpu.o (.text)
- cpu/mpc86xx/speed.o (.text)
+ arch/ppc/cpu/mpc86xx/start.o (.text)
+ arch/ppc/cpu/mpc86xx/traps.o (.text)
+ arch/ppc/cpu/mpc86xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu_init.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu.o (.text)
+ arch/ppc/cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
+ lib/zlib.o (.text)
drivers/bios_emulator/atibios.o (.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/arm1136/start.o (.text)
+ arch/arm/cpu/arm1136/start.o (.text)
board/freescale/mx31ads/libmx31ads.a (.text)
- lib_arm/libarm.a (.text)
+ arch/arm/lib/libarm.a (.text)
net/libnet.a (.text)
drivers/mtd/libmtd.a (.text)
# MA 02111-1307 USA
#
-LDSCRIPT = cpu/$(CPU)/$(SOC)/u-boot.lds
+LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds
TEXT_BASE = 0x97800000
IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
}
-static void setup_expio(void)
-{
- u32 reg;
- struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
- struct clkctl *pclkctl = (struct clkctl *)CCM_BASE_ADDR;
-
- /* CS5 setup */
- mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
- writel(0x00410089, &pweim[5].csgcr1);
- writel(0x00000002, &pweim[5].csgcr2);
-
- /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
- writel(0x32260000, &pweim[5].csrcr1);
-
- /* APR = 0 */
- writel(0x00000000, &pweim[5].csrcr2);
-
- /*
- * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
- * WCSA=0, WCSN=0
- */
- writel(0x72080F00, &pweim[5].cswcr1);
-
- mx51_io_board = (struct io_board_ctrl *)(CS5_BASE_ADDR +
- IO_BOARD_OFFSET);
- if ((readw(&mx51_io_board->id1) == 0xAAAA) &&
- (readw(&mx51_io_board->id2) == 0x5555)) {
- if (is_soc_rev(CHIP_REV_2_0) < 0) {
- reg = readl(&pclkctl->cbcdr);
- reg = (reg & (~0x70000)) | 0x30000;
- writel(reg, &pclkctl->cbcdr);
- /* make sure divider effective */
- while (readl(&pclkctl->cdhipr) != 0)
- ;
- writel(0x0, &pclkctl->ccdr);
- }
- } else {
- /* CS1 */
- writel(0x00410089, &pweim[1].csgcr1);
- writel(0x00000002, &pweim[1].csgcr2);
- /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
- writel(0x32260000, &pweim[1].csrcr1);
- /* APR=0 */
- writel(0x00000000, &pweim[1].csrcr2);
- /*
- * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
- * WEN=0, WCSA=0, WCSN=0
- */
- writel(0x72080F00, &pweim[1].cswcr1);
- mx51_io_board = (struct io_board_ctrl *)(CS1_BASE_ADDR +
- IO_BOARD_OFFSET);
- }
-
- /* Reset interrupt status reg */
- writew(0x1F, &(mx51_io_board->int_rest));
- writew(0x00, &(mx51_io_board->int_rest));
- writew(0xFFFF, &(mx51_io_board->int_mask));
-
- /* Reset the XUART and Ethernet controllers */
- reg = readw(&(mx51_io_board->sw_reset));
- reg |= 0x9;
- writew(reg, &(mx51_io_board->sw_reset));
- reg &= ~0x9;
- writew(reg, &(mx51_io_board->sw_reset));
-}
-
static void setup_iomux_fec(void)
{
/*FEC_MDIO*/
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
setup_iomux_uart();
- setup_expio();
setup_iomux_fec();
return 0;
}
};
#endif
-#define IO_BOARD_OFFSET (0x20000)
#endif
ifndef NAND_SPL
ifeq ($(CONFIG_MK_NAND), y)
TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
-LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
+LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
endif
endif
#include <asm/mp.h>
#include <netdev.h>
-#include "../common/pixis.h"
+#include "../common/ngpixis.h"
#include "../common/sgmii_riser.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
- u8 sw7;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
+ u8 sw;
puts("Board: P2020DS ");
#ifdef CONFIG_PHYS_64BIT
puts("(36-bit addrmap) ");
#endif
- printf("Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
- in_8(pixis_base + PIXIS_PVER));
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
- sw7 = in_8(pixis_base + PIXIS_SW(7));
- switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
- case 0:
- case 1:
- printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
- break;
- case 2:
- case 3:
- puts ("Promjet\n");
- break;
- }
+ sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
+ sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ /* The lower two bits are the actual vbank number */
+ printf("vBank: %d\n", sw & 3);
+ else
+ puts("Promjet\n");
return 0;
}
return gd->mem_clk;
}
-unsigned long
-calculate_board_sys_clk(ulong dummy)
+unsigned long calculate_board_sys_clk(ulong dummy)
{
ulong val;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- val = ics307_clk_freq(
- in_8(pixis_base + PIXIS_VSYSCLK0),
- in_8(pixis_base + PIXIS_VSYSCLK1),
- in_8(pixis_base + PIXIS_VSYSCLK2));
+ val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]),
+ in_8(&pixis->sclk[2]));
debug("sysclk val = %lu\n", val);
return val;
}
-unsigned long
-calculate_board_ddr_clk(ulong dummy)
+unsigned long calculate_board_ddr_clk(ulong dummy)
{
ulong val;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- val = ics307_clk_freq(
- in_8(pixis_base + PIXIS_VDDRCLK0),
- in_8(pixis_base + PIXIS_VDDRCLK1),
- in_8(pixis_base + PIXIS_VDDRCLK2));
+ val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]),
+ in_8(&pixis->dclk[2]));
debug("ddrclk val = %lu\n", val);
return val;
}
{
u8 i;
ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- i = in_8(pixis_base + PIXIS_SPD);
+ i = in_8(&pixis->spd);
i &= 0x07;
switch (i) {
{
u8 i;
ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
- i = in_8(pixis_base + PIXIS_SPD);
+ i = in_8(&pixis->spd);
i &= 0x38;
i >>= 3;
_text = .;
*(.start)
- cpu/leon3/start.o (.text)
+ arch/sparc/cpu/leon3/start.o (.text)
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
. = ALIGN(8192);
/* PROM CODE, Will be relocated to the end of memory,
_text = .;
*(.start)
- cpu/leon3/start.o (.text)
+ arch/sparc/cpu/leon3/start.o (.text)
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
. = ALIGN(8192);
/* PROM CODE, Will be relocated to the end of memory,
_text = .;
*(.start)
- cpu/leon3/start.o (.text)
+ arch/sparc/cpu/leon3/start.o (.text)
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
. = ALIGN(8192);
/* PROM CODE, Will be relocated to the end of memory,
_text = .;
*(.start)
- cpu/leon3/start.o (.text)
+ arch/sparc/cpu/leon3/start.o (.text)
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
. = ALIGN(8192);
/* PROM CODE, Will be relocated to the end of memory,
_text = .;
*(.start)
- cpu/leon2/start.o (.text)
+ arch/sparc/cpu/leon2/start.o (.text)
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
. = ALIGN(8192);
/* PROM CODE, Will be relocated to the end of memory,
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
-#include <asm-ppc/io.h>
+#include <asm/io.h>
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start(int hi_addr)
#include <ppc_asm.tmpl>
#include <config.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
/**************************************************************************
* TLB TABLE
/*
* Configure the MPC8XX I/O ports per the ioport configuration table
- * (taken from ./cpu/mpc8260/cpu_init.c)
+ * (taken from ./arch/ppc/cpu/mpc8260/cpu_init.c)
*/
void config_mpc8xx_ioports (volatile immap_t * immr)
{
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
}
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
}
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o(.text)
+ arch/ppc/cpu/mpc8xx/start.o(.text)
*(.text)
common/env_embedded.o(.text)
*(.got1)
return (SDRAM_SIZE);
}
-/* In cpu/mips/cpu.c */
+/* In arch/mips/cpu/cpu.c */
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
void set_ledcard(u32 value){
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
- lib_ppc/time.o (.text)
- lib_ppc/ticks.o (.text)
- lib_ppc/cache.o (.text)
- lib_generic/crc32.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/lib/time.o (.text)
+ arch/ppc/lib/ticks.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- lib_ppc/ppcstring.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
- lib_ppc/time.o (.text)
- lib_ppc/ticks.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/lib/time.o (.text)
+ arch/ppc/lib/ticks.o (.text)
. = env_offset;
common/env_embedded.o(.text)
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot-customlayout.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8260/start.o (.text)
+ arch/ppc/cpu/mpc8260/start.o (.text)
/*
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
. = env_offset;
*/
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
* is something else than 0x00000000.
*/
-#if defined(CONFIG_MPC5200)
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
return dramsize + dramsize2;
}
-#elif defined(CONFIG_MGT5100)
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup and enable SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
- *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
- *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
- /* address select register */
- *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
- __asm__ volatile ("sync");
-
- /* find RAM size */
- sdram_start(0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* set SDRAM end address according to size */
- *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* Retrieve amount of SDRAM available */
- dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
-
int checkboard (void)
{
#if defined (CONFIG_LITE5200B)
puts ("Board: Freescale Lite5200B\n");
-#elif defined(CONFIG_MPC5200)
+#else
puts ("Board: Motorola MPC5200 (IceCube)\n");
-#elif defined(CONFIG_MGT5100)
- puts ("Board: Motorola MGT5100 (IceCube)\n");
#endif
return 0;
}
* Note that CS_BOOT cannot be cleared when
* executing in flash.
*/
-#if defined(CONFIG_MGT5100)
- *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
- *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-#endif
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}
#define SDRAM_DDR 1 /* is DDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
#define SDRAM_DDR 1 /* is DDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
#define SDRAM_DDR 0 /* is SDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE 0x008D0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xC2222600
-#define SDRAM_CONFIG2 0x88B70004
-#define SDRAM_ADDRSEL 0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
/*
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mcf52x2/start.o (.text)
- lib_m68k/traps.o (.text)
- cpu/mcf52x2/interrupts.o (.text)
+ arch/m68k/cpu/mcf52x2/start.o (.text)
+ arch/m68k/lib/traps.o (.text)
+ arch/m68k/cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot-customlayout.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds
--- /dev/null
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2010 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+CFLAGS_lib_generic += -O2
+CFLAGS_lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
--- /dev/null
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2007 David Rowe,
+ * (c) 2006 Ivan Danov
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/net.h>
+
+int checkboard(void)
+{
+ printf("Board: IP04 IP-PBX\n");
+ printf(" http://www.rowetel.com/ucasterisk/ip04.html\n");
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+
+int misc_init_r(void)
+{
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(enetaddr);
+ eth_setenv_enetaddr("ethaddr", enetaddr);
+ }
+
+ return 0;
+}
+#endif
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
- lib_ppc/time.o (.text)
- lib_ppc/ticks.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/lib/time.o (.text)
+ arch/ppc/lib/ticks.o (.text)
/**
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- lib_ppc/ppcstring.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
- lib_ppc/time.o (.text)
- lib_ppc/ticks.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/lib/time.o (.text)
+ arch/ppc/lib/ticks.o (.text)
/**
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/*
* This function is run very early, out of flash, and before devices are
- * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
+ * initialized. It is called by arch/ppc/lib/board.c:board_init_f by virtue
* of being in the init_sequence array.
*
* The SDRAM has been initialized already -- start.S:start called
#endif
/*
- * This function is also called by lib_ppc/board.c:board_init_f (it is
+ * This function is also called by arch/ppc/lib/board.c:board_init_f (it is
* also in the init_sequence array) but later. Many more things are
* configured, but we are still running from flash.
*/
/* **** No more functions called by board_init_f. **** */
/*
- * This function is called by lib_ppc/board.c:board_init_r. At this
+ * This function is called by arch/ppc/lib/board.c:board_init_r. At this
* point, basic setup is done, U-Boot has been moved into SDRAM and
* PCI has been set up. From here we done late setup.
*/
/*
* this is even after checkboard. It returns the size of the SDRAM
* that we have installed. This function is called by board_init_f
- * in lib_ppc/board.c to initialize the memory and return what I
+ * in arch/ppc/lib/board.c to initialize the memory and return what I
* found.
*/
phys_size_t initdram (int board_type)
* Note that CS_BOOT cannot be cleared when
* executing in flash.
*/
-#if defined(CONFIG_MGT5100)
- *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
- *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-#endif
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}
*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
}
-#if defined(CONFIG_MPC5200)
*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-#endif
}
int update_flash_size (int flash_size)
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
*
- * Based in part on cpu/mpc8260/ether_scc.c.
+ * Based in part on arch/ppc/cpu/mpc8260/ether_scc.c.
*
* See file CREDITS for list of people who contributed to this
* project.
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
*
- * Based in part on cpu/mpc8xx/scc.c.
+ * Based in part on arch/ppc/cpu/mpc8xx/scc.c.
*
* See file CREDITS for list of people who contributed to this
* project.
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
*
- * Based in part on cpu/mpc8260/ether_scc.c.
+ * Based in part on arch/ppc/cpu/mpc8260/ether_scc.c.
*
* See file CREDITS for list of people who contributed to this
* project.
*/
#include <ppc_asm.tmpl>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
#include <config.h>
/**************************************************************************
.bootpg 0xF7FBF000 :
{
- cpu/ppc4xx/start.o (.bootpg)
+ arch/ppc/cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
/*
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
/*
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
int board_init (void)
{
struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+#if defined(CONFIG_SYS_NAND_LARGEPAGE)
+ struct system_control_regs *sc_regs =
+ (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
+#endif
gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
®s->port[PORTC].dr);
#endif
#ifdef CONFIG_MXC_MMC
+#if defined(CONFIG_MAGNESIUM)
+ mx27_sd1_init_pins();
+#else
mx27_sd2_init_pins();
#endif
+#endif
+#if defined(CONFIG_SYS_NAND_LARGEPAGE)
+ /*
+ * set in FMCR NF_FMS Bit(5) to 1
+ * (NAND Flash with 2 Kbyte page size)
+ */
+ writel(readl(&sc_regs->fmcr) | (1 << 5), &sc_regs->fmcr);
+#endif
return 0;
}
int checkboard(void)
{
- printf("LogicPD imx27lite\n");
+ puts ("Board: ");
+ puts(CONFIG_BOARDNAME);
return 0;
}
/*
* This the the zoom2, board specific, gpmc configuration for the
* quad uart on the debug board. The more general gpmc configurations
- * are setup at the cpu level in cpu/arm_cortexa8/omap3/mem.c
+ * are setup at the cpu level in arch/arm/cpu/arm_cortexa8/omap3/mem.c
*
* The details of the setting of the serial gpmc setup are not available.
* The values were provided by another party.
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
- * This file was adapted from cpu/mpc5xxx/serial.c
+ * This file was adapted from arch/ppc/cpu/mpc5xxx/serial.c
*
*/
/*
* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
*
- * Modified to use the routines in cpu/arm720t/lpc2292/flash.c by
+ * Modified to use the routines in arch/arm/cpu/arm720t/lpc2292/flash.c by
* Gary Jennejohn <garyj@denx,de>
*
* This program is free software; you can redistribute it and/or
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
#include <ppc_asm.tmpl>
#include <config.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
/**************************************************************************
* TLB TABLE
/*
- * linux/include/asm-arm/arch-at91/hardware.h
+ * linux/include/asm/arch-at91/hardware.h
*
* Copyright (C) 2003 SAN People
*
#define __M501SK_H
#ifndef __ASSEMBLY__
-#include <asm-arm/arch-at91rm9200/AT91RM9200.h>
+#include <asm/arch-at91rm9200/AT91RM9200.h>
#else
-#include <asm-arm/arch-at91rm9200/AT91RM9200_inc.h>
+#include <asm/arch-at91rm9200/AT91RM9200_inc.h>
#endif
#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) /* Pin Controlled by PA22 */
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004-2008
+# Matrix-Vision GmbH, info@matrix-vision.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o fpga.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+ @mkimage -T script -C none -n mvSMR_Script -d bootscript bootscript.img
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
--- /dev/null
+echo
+echo "==== running autoscript ===="
+echo
+setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}'
+setenv ramkernel 'setenv kernel_boot ${loadaddr}'
+setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}'
+setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}'
+setenv bootfromflash run flashkernel cpird addcons boot24
+setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel'
+if test ${console} = yes;
+then
+setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8'
+else
+setenv addcons 'setenv bootargs ${bootargs} console=tty0'
+fi
+setenv set_static_ip 'setenv ipaddr ${static_ipaddr}'
+setenv set_static_nm 'setenv netmask ${static_netmask}'
+setenv set_static_gw 'setenv gatewayip ${static_gateway}'
+setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}'
+if test ${servicemode} != yes;
+then
+ echo "=== forced flash mode ==="
+ run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
+fi
+if test ${autoscript_boot} != no;
+then
+ if test ${netboot} = yes;
+ then
+ bootp
+ if test $? = 0;
+ then
+ echo "=== bootp succeeded -> netboot ==="
+ run set_ip bootfromnet addcons boot24
+ else
+ echo "=== netboot failed ==="
+ fi
+ fi
+ echo "=== bootfromflash ==="
+ run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
+else
+ echo "=== boot stopped with autoscript_boot no ==="
+fi
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFF800000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+LDSCRIPT := $(SRCTREE)/board/matrix_vision/mvsmr/u-boot.lds
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2010
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvsmr.h"
+
+Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
+ fpga_pre_config_fn,
+ fpga_pgm_fn,
+ fpga_clk_fn,
+ fpga_init_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ 0
+};
+
+Xilinx_desc spartan3 = {
+ Xilinx_Spartan2,
+ slave_serial,
+ XILINX_XC3S200_SIZE,
+ (void *) &fpga_fns,
+ 0,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvsmr_init_fpga(void)
+{
+ fpga_init();
+ fpga_add(fpga_xilinx, &spartan3);
+
+ return 1;
+}
+
+int fpga_init_fn(int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+ if (in_be32(&gpio->simple_ival) & FPGA_CONFIG)
+ return 0;
+
+ return 1;
+}
+
+int fpga_done_fn(int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ int result = 0;
+
+ udelay(10);
+ if (in_be32(&gpio->simple_ival) & FPGA_DONE)
+ result = 1;
+
+ return result;
+}
+
+int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+ if (!assert)
+ setbits_8(&gpio->sint_dvo, FPGA_STATUS);
+ else
+ clrbits_8(&gpio->sint_dvo, FPGA_STATUS);
+
+ return assert;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+ if (assert_clk)
+ setbits_be32(&gpio->simple_dvo, FPGA_CCLK);
+ else
+ clrbits_be32(&gpio->simple_dvo, FPGA_CCLK);
+
+ return assert_clk;
+}
+
+int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+ if (assert_write)
+ setbits_be32(&gpio->simple_dvo, FPGA_DIN);
+ else
+ clrbits_be32(&gpio->simple_dvo, FPGA_DIN);
+
+ return assert_write;
+}
+
+int fpga_pre_config_fn(int cookie)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+ setbits_8(&gpio->sint_dvo, FPGA_STATUS);
+
+ return 0;
+}
/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
*
* See file CREDITS for list of people who contributed to this
* project.
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
*/
-#include <common.h>
+extern int mvsmr_init_fpga(void);
-void flush_cache (ulong start_addr, ulong size)
-{
- /* Must be implemented for all M68k processors with copy-back data cache */
-}
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_pre_config_fn(int cookie);
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2005-2010
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <malloc.h>
+#include <pci.h>
+#include <i2c.h>
+#include <fpga.h>
+#include <environment.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include "fpga.h"
+#include "mvsmr.h"
+#include "../common/mv_common.h"
+
+#define SDRAM_DDR 1
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x715f0f00
+#define SDRAM_CONFIG1 0xd3722930
+#define SDRAM_CONFIG2 0x46770000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start(int hi_addr)
+{
+ long hi_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 |
+ hi_bit);
+
+ /* precharge all banks */
+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
+ hi_bit);
+
+ /* set mode register: extended mode */
+ out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+
+ /* set mode register: reset DLL */
+ out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+
+ /* precharge all banks */
+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
+ hi_bit);
+
+ /* auto refresh */
+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 |
+ hi_bit);
+
+ /* set mode register */
+ out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+ /* normal operation */
+ out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
+}
+
+phys_addr_t initdram(int board_type)
+{
+ ulong dramsize = 0;
+ ulong test1,
+ test2;
+
+ /* setup SDRAM chip selects */
+ out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
+
+ /* setup config registers */
+ out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+ out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else
+ dramsize = test2;
+
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ if (dramsize > 0)
+ out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
+ __builtin_ffs(dramsize >> 20) - 1);
+ else
+ out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
+
+ return dramsize;
+}
+
+void mvsmr_init_gpio(void)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_wu_gpio *wu_gpio =
+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+ struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+ printf("Ports : 0x%08x\n", gpio->port_config);
+ printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
+
+ out_be32(&gpio->simple_ddr, SIMPLE_DDR);
+ out_be32(&gpio->simple_dvo, SIMPLE_DVO);
+ out_be32(&gpio->simple_ode, SIMPLE_ODE);
+ out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
+
+ out_8(&gpio->sint_ode, SINT_ODE);
+ out_8(&gpio->sint_ddr, SINT_DDR);
+ out_8(&gpio->sint_dvo, SINT_DVO);
+ out_8(&gpio->sint_inten, SINT_INTEN);
+ out_be16(&gpio->sint_itype, SINT_ITYPE);
+ out_8(&gpio->sint_gpioe, SINT_GPIOEN);
+
+ out_8(&wu_gpio->ode, WKUP_ODE);
+ out_8(&wu_gpio->ddr, WKUP_DIR);
+ out_8(&wu_gpio->dvo, WKUP_DO);
+ out_8(&wu_gpio->enable, WKUP_EN);
+
+ out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
+ out_be32(&timers->gpt1.emsr, 0x00000234);
+ out_be32(&timers->gpt2.emsr, 0x00000234);
+ out_be32(&timers->gpt3.emsr, 0x00000234);
+ out_be32(&timers->gpt4.emsr, 0x00000234);
+ out_be32(&timers->gpt5.emsr, 0x00000234);
+ out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
+ out_be32(&timers->gpt7.emsr, 0x00000024);
+}
+
+int misc_init_r(void)
+{
+ char *s = getenv("reset_env");
+
+ if (s) {
+ printf(" === FACTORY RESET ===\n");
+ mv_reset_environment();
+ saveenv();
+ }
+
+ return -1;
+}
+
+void mvsmr_get_dbg_present(void)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
+
+ if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
+ setenv("dbg_present", "no\0");
+ setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
+ } else {
+ setenv("dbg_present", "yes\0");
+ setenv("bootstopkey", "s\0");
+ setbits_8(&psc->command, PSC_RX_ENABLE);
+ }
+}
+
+void mvsmr_get_service_mode(void)
+{
+ struct mpc5xxx_wu_gpio *wu_gpio =
+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
+ if (in_8(&wu_gpio->ival) & SERVICE_MODE)
+ setenv("servicemode", "no\0");
+ else
+ setenv("servicemode", "yes\0");
+}
+
+int mvsmr_get_mac(void)
+{
+ unsigned char mac[6];
+ struct mpc5xxx_wu_gpio *wu_gpio =
+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
+ if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
+ setenv("lan_present", "no\0");
+ return -1;
+ } else
+ setenv("lan_present", "yes\0");
+
+ i2c_read(0x50, 0, 1, mac, 6);
+
+ eth_setenv_enetaddr("ethaddr", mac);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ mvsmr_init_gpio();
+ printf("Board: Matrix Vision mvSMR\n");
+
+ return 0;
+}
+
+void flash_preinit(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
+}
+
+void flash_afterinit(ulong size)
+{
+ out_be32((u32 *)MPC5XXX_BOOTCS_START,
+ START_REG(CONFIG_SYS_BOOTCS_START | size));
+ out_be32((u32 *)MPC5XXX_CS0_START,
+ START_REG(CONFIG_SYS_BOOTCS_START | size));
+ out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
+ STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
+ out_be32((u32 *)MPC5XXX_CS0_STOP,
+ STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
+}
+
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+ mvsmr_get_dbg_present();
+ mvsmr_get_service_mode();
+ mvsmr_init_fpga();
+ mv_load_fpga();
+ pci_mpc5xxx_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ if (!mvsmr_get_mac())
+ return cpu_eth_init(bis);
+
+ return pci_eth_init(bis);
+}
--- /dev/null
+#include <pci.h>
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0
+#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1
+#define FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2
+#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3
+#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4
+#define S_FPGA_DIN MPC5XXX_GPIO_SINT_PSC3_5
+#define S_FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_6
+#define S_FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_7
+#define S_FPGA_CONFIG MPC5XXX_GPIO_SINT_PSC3_8
+#define S_FPGA_STATUS MPC5XXX_GPIO_WKUP_PSC3_9
+
+#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0
+#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1
+#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2
+#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3
+#define SERVICE_MODE MPC5XXX_GPIO_WKUP_6
+#define FLASH_RBY MPC5XXX_GPIO_WKUP_7
+#define UART_EN1 MPC5XXX_GPIO_WKUP_PSC1_4
+#define LAN_PRSNT MPC5XXX_GPIO_WKUP_PSC2_4
+
+#define SIMPLE_DDR (FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\
+ S_FPGA_CCLK)
+#define SIMPLE_DVO (FPGA_CONFIG)
+#define SIMPLE_ODE (FPGA_CONFIG)
+#define SIMPLE_GPIOEN (FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\
+ S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT)
+
+#define SINT_ODE 0x1
+#define SINT_DDR 0x3
+#define SINT_DVO 0x1
+#define SINT_INTEN 0
+#define SINT_ITYPE 0
+#define SINT_GPIOEN (FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG)
+
+#define WKUP_ODE (MAN_RST | S_FPGA_STATUS)
+#define WKUP_DIR (MAN_RST | WD_TS | S_FPGA_STATUS)
+#define WKUP_DO (MAN_RST | WD_TS | S_FPGA_STATUS)
+#define WKUP_EN (MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\
+ FLASH_RBY | UART_EN1 | LAN_PRSNT)
--- /dev/null
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2010
+ * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the first two sectors (=8KB) of our S29GL flash chip */
+ cpu/mpc5xxx/start.o (.text)
+ cpu/mpc5xxx/traps.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/cache.o (.text)
+ lib_ppc/time.o (.text)
+
+ /* This is only needed to force failure if size of above code will ever */
+ /* increase and grow into reserved space. */
+ . = ALIGN(0x2000); /* location counter has to be 0x4000 now */
+ . += 0x4000; /* ->0x8000, i.e. move to env_offset */
+
+ . = env_offset; /* ld error as soon as above ALIGN misplaces lc */
+ common/env_embedded.o (.ppcenv)
+
+ *(.text)
+ *(.got1)
+ . = ALIGN(16);
+ *(.eh_frame)
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
#define SDRAM_DDR 1 /* is DDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
#define SDRAM_DDR 0 /* is SDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE 0x008D0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xC2222600
-#define SDRAM_CONFIG2 0x88B70004
-#define SDRAM_ADDRSEL 0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
#define SDRAM_DDR 0 /* is SDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE 0x008D0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xC2222600
-#define SDRAM_CONFIG2 0x88B70004
-#define SDRAM_ADDRSEL 0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
#include <atmel_lcdc.h>
#include <lcd.h>
-#include "../../../cpu/at32ap/hsmc3.h"
+#include "../../../arch/avr32/cpu/hsmc3.h"
#if defined(CONFIG_LCD)
/* 480x272x16 @ 72 Hz */
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
board/ml2/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
+ arch/ppc/cpu/ppc4xx/kgdb.o (.text)
+ arch/ppc/cpu/ppc4xx/traps.o (.text)
+ arch/ppc/cpu/ppc4xx/interrupts.o (.text)
+ arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/ppc/cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
+ lib/zlib.o (.text)
/* . = env_offset;*/
/* common/env_embedded.o(.text)*/
mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc824x/start.o (.text)
- lib_ppc/board.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/cpu/mpc824x/start.o (.text)
+ arch/ppc/lib/board.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
*(.got1)
. = ALIGN(16);
PROVIDE(_f_init_rom = .);
.init : {
- cpu/mpc824x/start.o (.text)
+ arch/ppc/cpu/mpc824x/start.o (.text)
*(.init)
} > ram
_init_size = SIZEOF(.init);
.plt : { *(.plt) }
.text :
{
- cpu/mpc824x/start.o (.text)
+ arch/ppc/cpu/mpc824x/start.o (.text)
common/board.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
. = env_offset;
common/env_embedded.o (.text)
mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
common/env_embedded.o(.text)
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot.lds
#define SDRAM_DDR 0 /* is SDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE 0x008D0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xC2222600
-#define SDRAM_CONFIG2 0x88B70004
-#define SDRAM_ADDRSEL 0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
.plt : { *(.plt) }
.text :
{
- cpu/mpc5xxx/start.o (.text)
+ arch/ppc/cpu/mpc5xxx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
}
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
}
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
#include <ppc4xx.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <asm-ppc/u-boot.h>
+#include <asm/u-boot.h>
#include "../common/nm.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* This function is run very early, out of flash, and before devices are
- * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
+ * initialized. It is called by arch/ppc/lib/board.c:board_init_f by virtue
* of being in the init_sequence array.
*
* The SDRAM has been initialized already -- start.S:start called
Startup sequence
----------------
-(cpu/ppc4xx/resetvec.S)
+(arch/ppc/cpu/ppc4xx/resetvec.S)
depending on configs option
call _start_440 _start_pci oder _start
-(cpu/ppc4xx/start.S)
+(arch/ppc/cpu/ppc4xx/start.S)
_start_440:
initialize register like
call cpu_init_f /* run low-level CPU init code (from Flash) */
call cpu_init_f
- board_init_f: (lib_ppc\board.c)
+ board_init_f: (arch/ppc/lib\board.c)
init_sequence defines a list of function to be called
board_early_init_f: (board/netstal/hcu5/hcu5.c)
We are using Bootstrap-Option A
* - board info struct
Save local variables to board info struct
call relocate_code() does not return
- relocate_code: (cpu/ppc4xx/start.S)
+ relocate_code: (arch/ppc/cpu/ppc4xx/start.S)
-------------------------------------------------------
From now on our copy is in RAM and we will run from there,
starting with board_init_r
-------------------------------------------------------
- board_init_r: (lib_ppc\board.c)
+ board_init_r: (arch/ppc/lib\board.c)
setup bd function pointers
trap_init
flash_init: (board/netstal/hcu5/flash.c)
/* setup for u-boot erase, update */
setup bd flash info
- cpu_init_r: (cpu/ppc4xx/cpu_init.c)
+ cpu_init_r: (arch/ppc/cpu/ppc4xx/cpu_init.c)
peripheral chip select in using defines like
CONFIG_SYS_EBC_PB0A, CONFIG_SYS_EBC_PB0C from hcu5.h
mem_malloc_init
Most of the HW specific code for the HCU5 may be found in
include/configs/hcu5.h
board/netstal/hcu5/*
-cpu/ppc4xx/*
-lib_ppc/*
+arch/ppc/cpu/ppc4xx/*
+arch/ppc/lib/*
include/ppc440.h
Drivers for serial etc are found under drivers/
/*
* This function is run very early, out of flash, and before devices are
- * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
+ * initialized. It is called by arch/ppc/lib/board.c:board_init_f by virtue
* of being in the init_sequence array.
*
* The SDRAM has been initialized already -- start.S:start called
#include <ppc4xx.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <asm-ppc/u-boot.h>
+#include <asm/u-boot.h>
#include "../common/nm.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* This function is run very early, out of flash, and before devices are
- * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
+ * initialized. It is called by arch/ppc/lib/board.c:board_init_f by virtue
* of being in the init_sequence array.
*
* The SDRAM has been initialized already -- start.S:start called
$(obj)crcit.o: crcit.c
$(HOSTCC) $(HOSTCFLAGS) -o $@ -c $<
-$(obj)crc32.o: $(SRCTREE)/lib_generic/crc32.c
+$(obj)crc32.o: $(SRCTREE)/lib/crc32.c
$(HOSTCC) $(HOSTCFLAGS) -DUSE_HOSTCC -I$(TOPDIR)/include \
-o $@ -c $<
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
#define BCSR_PCMCIA_PC0DRVEN 0x0010
#define BCSR_PCMCIA_PC0RST 0x0080
-/* In cpu/mips/cpu.c */
+/* In arch/mips/cpu/cpu.c */
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
int checkboard (void)
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
/*--------------------------------------------------------------------
- * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c
+ * GPIO's are alreay setup in arch/ppc/cpu/ppc4xx/cpu_init.c
* via define from board config file.
*-------------------------------------------------------------------*/
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
-#include <asm-ppc/io.h>
+#include <asm/io.h>
#include "mt46v32m16-75.h"
*/
#include <common.h>
-#include <asm-arm/mach-types.h>
+#include <asm/mach-types.h>
DECLARE_GLOBAL_DATA_PTR;
#define SDRAM_DDR 1 /* is DDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
#define SDRAM_DDR 0 /* is SDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE 0x008D0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xC2222600
-#define SDRAM_CONFIG2 0x88B70004
-#define SDRAM_ADDRSEL 0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
* is something else than 0x00000000.
*/
-#if defined(CONFIG_MPC5200)
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
return dramsize + dramsize2;
}
-#elif defined(CONFIG_MGT5100)
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup and enable SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
- *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
- *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
- /* address select register */
- *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
- __asm__ volatile ("sync");
-
- /* find RAM size */
- sdram_start(0);
- test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* set SDRAM end address according to size */
- *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* Retrieve amount of SDRAM available */
- dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
-
int checkboard (void)
{
-#if defined(CONFIG_MPC5200)
puts ("Board: MicroSys PM520 \n");
-#elif defined(CONFIG_MGT5100)
- puts ("Board: MicroSys PM510 \n");
-#endif
return 0;
}
* Note that CS_BOOT cannot be cleared when
* executing in flash.
*/
-#if defined(CONFIG_MGT5100)
- *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
- *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-#endif
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
#include <altera.h>
#include <ACEX1K.h>
#include <command.h>
-#include <asm-ppc/processor.h>
+#include <asm/processor.h>
#include <ppc440.h>
#include "fpga.h"
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (unsigned char *) info->start[sect];
- writeb (addr, 0xaa);
- writeb (addr, 0x55);
- writeb (addr, 0x80);
- writeb (addr, 0xaa);
- writeb (addr, 0x55);
- writeb (addr2, 0x30);
+ writeb (0xaa, addr);
+ writeb (0x55, addr);
+ writeb (0x80, addr);
+ writeb (0xaa, addr);
+ writeb (0x55, addr);
+ writeb (0x30, addr2);
/* Now just wait for 0xff & provide some user
* feedback while we wait.
*/
return (2);
}
- writeb (cmd, 0xaa);
- writeb (cmd, 0x55);
- writeb (cmd, 0xa0);
+ writeb (0xaa, cmd);
+ writeb (0x55, cmd);
+ writeb (0xa0, cmd);
writeb (dst, b);
/* Verify write */
{
.text :
{
- cpu/nios2/start.o (.text)
+ arch/nios/cpu2/start.o (.text)
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
val &= ~mask;
else
val |= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
void __led_set (led_id_t mask, int state)
val &= ~mask;
else
val |= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
void __led_toggle (led_id_t mask)
nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
val ^= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
{
.text :
{
- cpu/nios2/start.o (.text)
+ arch/nios/cpu2/start.o (.text)
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
. = ALIGN(4);
.text :
{
- cpu/mips/start.o (.text)
+ arch/mips/cpu/start.o (.text)
board/purple/lowlevel_init.o (.text)
- cpu/mips/cache.o (.text)
+ arch/mips/cpu/cache.o (.text)
common/main.o (.text)
common/dlmalloc.o (.text)
common/cmd_boot.o (.text)
- lib_generic/zlib.o (.text)
+ lib/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
/* XXX ?
. = env_offset;
*/
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/cpu_init.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/cpu_init.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
/***
. = env_offset;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
/* XXX ?
. = env_offset;
*/
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
#include <common.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
#include <asm/arch/io.h>
void coloured_LED_init(void)
{
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
+ writel(1 << AT91SAM9261_ID_PIOC, &pmc->pcer);
- at91_set_gpio_output(CONFIG_RED_LED, 1);
- at91_set_gpio_output(CONFIG_GREEN_LED, 1);
- at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+ at91_set_pio_output(CONFIG_RED_LED, 1);
+ at91_set_pio_output(CONFIG_GREEN_LED, 1);
+ at91_set_pio_output(CONFIG_YELLOW_LED, 1);
- at91_set_gpio_value(CONFIG_RED_LED, 0);
- at91_set_gpio_value(CONFIG_GREEN_LED, 1);
- at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+ at91_set_pio_value(CONFIG_RED_LED, 0);
+ at91_set_pio_value(CONFIG_GREEN_LED, 1);
+ at91_set_pio_value(CONFIG_YELLOW_LED, 1);
}
#include <common.h>
#include <asm/sizes.h>
#include <asm/arch/at91sam9261.h>
-#include <asm/arch/at91sam9261_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
#include <lcd.h>
static void pm9261_nand_hw_init(void)
{
unsigned long csa;
+ at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE;
+ at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* Enable CS3 */
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA,
- csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+ csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa);
/* Configure SMC CS3 for NAND/SmartMedia */
- at91_sys_write(AT91_SMC_SETUP(3),
- AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3),
- AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
- AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
- at91_sys_write(AT91_SMC_CYCLE(3),
- AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
- at91_sys_write(AT91_SMC_MODE(3),
- AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
- AT91_SMC_EXNWMODE_DISABLE |
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
- AT91_SMC_DBW_16 |
+ AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
- AT91_SMC_DBW_8 |
+ AT91_SMC_MODE_DBW_8 |
#endif
- AT91_SMC_TDF_(2));
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+
+ writel(1 << AT91SAM9261_ID_PIOA |
+ 1 << AT91SAM9261_ID_PIOC,
+ &pmc->pcer);
/* Configure RDY/BSY */
- at91_set_gpio_input(AT91_PIN_PA16, 1);
+ at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(AT91_PIN_PC14, 1);
+ at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
- at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
- at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
}
#endif
#ifdef CONFIG_DRIVER_DM9000
static void pm9261_dm9000_hw_init(void)
{
+ at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
/* Configure SMC CS2 for DM9000 */
- at91_sys_write(AT91_SMC_SETUP(2),
- AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(2),
- AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
- AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
- at91_sys_write(AT91_SMC_CYCLE(2),
- AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
- at91_sys_write(AT91_SMC_MODE(2),
- AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
- AT91_SMC_EXNWMODE_DISABLE |
- AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
- AT91_SMC_TDF_(1));
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[2].setup);
+
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
+ &smc->cs[2].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
+ &smc->cs[2].cycle);
+
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+ AT91_SMC_MODE_TDF_CYCLE(1),
+ &smc->cs[2].mode);
/* Configure Interrupt pin as input, no pull-up */
- at91_set_gpio_input(AT91_PIN_PA24, 0);
+ writel(1 << AT91SAM9261_ID_PIOA, &pmc->pcer);
+ at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
}
#endif
void lcd_enable(void)
{
- at91_set_gpio_value(AT91_PIN_PA22, 0); /* power up */
+ at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */
}
void lcd_disable(void)
{
- at91_set_gpio_value(AT91_PIN_PA22, 1); /* power down */
+ at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */
}
static void pm9261_lcd_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
- at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
- at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
- at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
- at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
- at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
- at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
- at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
- at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
- at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
- at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
- at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
- at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
- at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
- at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
- at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
- at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
- at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
- at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
- at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
- at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
- at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
-
- at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */
+ at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */
+ at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */
+ at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */
+ at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */
+ at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */
+ at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */
+ at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */
+ at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */
+ at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */
+
+ writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
gd->fb_base = AT91SAM9261_SRAM_BASE;
}
int board_init(void)
{
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
/* Enable Ctrlc */
console_init_f();
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
+ writel(1 << AT91SAM9261_ID_PIOA |
+ 1 << AT91SAM9261_ID_PIOC,
+ &pmc->pcer);
/* arch number of PM9261-Board */
gd->bd->bi_arch_number = MACH_TYPE_PM9261;
.plt : { *(.plt) }
.text :
{
- cpu/mpc8260/start.o (.text)
+ arch/ppc/cpu/mpc8260/start.o (.text)
*(.text)
*(.got1)
/*. = env_offset; */
. = ALIGN(4);
.text :
{
- cpu/arm1176/start.o (.text)
- cpu/arm1176/s3c64xx/cpu_init.o (.text)
+ arch/arm/cpu/arm1176/start.o (.text)
+ arch/arm/cpu/arm1176/s3c64xx/cpu_init.o (.text)
*(.text)
}
*/
/*
- * Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by
+ * Ported from arch/ppc/cpu/ppc4xx/i2c.c by AS HARNOIS by
* Travis B. Sawyer
* Sandburst Corporation.
*/
#include <i2c.h>
#include <command.h>
#include "ppc440gx_i2c.h"
-#include <asm-ppc/io.h>
+#include <asm/io.h>
#ifdef CONFIG_I2C_BUS1
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
board/sandburst/karef/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
+ arch/ppc/cpu/ppc4xx/kgdb.o (.text)
+ arch/ppc/cpu/ppc4xx/traps.o (.text)
+ arch/ppc/cpu/ppc4xx/interrupts.o (.text)
+ arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/ppc/cpu/ppc4xx/speed.o (.text)
drivers/net/4xx_enet.o (.text)
common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
+ lib/zlib.o (.text)
/* common/env_embedded.o(.text) */
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
board/sandburst/metrobox/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
+ arch/ppc/cpu/ppc4xx/kgdb.o (.text)
+ arch/ppc/cpu/ppc4xx/traps.o (.text)
+ arch/ppc/cpu/ppc4xx/interrupts.o (.text)
+ arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/ppc/cpu/ppc4xx/speed.o (.text)
drivers/net/4xx_enet.o (.text)
common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
+ lib/zlib.o (.text)
/* common/env_embedded.o(.text) */
.plt : { *(.plt) }
.text :
{
- cpu/mpc86xx/start.o (.text)
- cpu/mpc86xx/traps.o (.text)
- cpu/mpc86xx/interrupts.o (.text)
- cpu/mpc86xx/cpu_init.o (.text)
- cpu/mpc86xx/cpu.o (.text)
- cpu/mpc86xx/speed.o (.text)
+ arch/ppc/cpu/mpc86xx/start.o (.text)
+ arch/ppc/cpu/mpc86xx/traps.o (.text)
+ arch/ppc/cpu/mpc86xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu_init.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu.o (.text)
+ arch/ppc/cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
+ lib/zlib.o (.text)
*(.text)
*(.got1)
}
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
board/sc3/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
+ arch/ppc/cpu/ppc4xx/kgdb.o (.text)
+ arch/ppc/cpu/ppc4xx/traps.o (.text)
+ arch/ppc/cpu/ppc4xx/interrupts.o (.text)
+ arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/ppc/cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
+ lib/zlib.o (.text)
/* . = env_offset;*/
/* common/env_embedded.o(.text)*/
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
/*
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/lib/time.o (.text)
. = env_offset;
common/env_embedded.o(.text)
* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
*
* (C) Copyright 2007 Gary Jennejohn garyj@denx.de
- * Modified to use the routines in cpu/arm720t/lpc2292/flash.c.
+ * Modified to use the routines in arch/arm/cpu/arm720t/lpc2292/flash.c.
* Heavily modified to support the SMN42 board from Siemens
*
* This program is free software; you can redistribute it and/or
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
{
.text :
{
- cpu/nios/start.o (.text)
+ arch/nios/cpu/start.o (.text)
*(.text)
}
__text_end = .;
#endif
/* Why is the phy reset done _after_ the ethernet
- * initialization in lib_ppc/board.c?
+ * initialization in arch/ppc/lib/board.c?
* Do it here so it's done before the TSECs are used.
*/
reset_phy();
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/time.o (.text)
. = env_offset;
common/env_embedded.o (.ppcenv)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
-CFLAGS_lib_generic += -O2
-CFLAGS_lzma += -O2
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
#define SDRAM_DDR 0 /* is SDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE 0x008D0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xC2222600
-#define SDRAM_CONFIG2 0x88B70004
-#define SDRAM_ADDRSEL 0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
#define SDRAM_DDR 0 /* is SDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x514F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
-
-#else
-#error CONFIG_MPC5200 is not defined
-#endif
* is something else than 0x00000000.
*/
-#if defined(CONFIG_MPC5200)
long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
{
ulong dramsize = 0;
return dramsize + dramsize2;
}
-
-#elif defined(CONFIG_MGT5100)
-
-long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
-{
- ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup and enable SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
- *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
- *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
-
- /* address select register */
- *(vu_long *)MPC5XXX_SDRAM_XLBSEL = sdram_conf->addrsel;
- __asm__ volatile ("sync");
-
- /* find RAM size */
- mpc5xxx_sdram_start(sdram_conf, 0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- mpc5xxx_sdram_start(sdram_conf, 1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- mpc5xxx_sdram_start(sdram_conf, 0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* set SDRAM end address according to size */
- *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* Retrieve amount of SDRAM available */
- dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
ulong control;
ulong config1;
ulong config2;
-#if defined(CONFIG_MPC5200)
ulong tapdelay;
-#endif
-#if defined(CONFIG_MGT5100)
- ulong addrsel;
-#endif
} sdram_conf_t;
long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf);
sdram_conf.control = SDRAM_CONTROL;
sdram_conf.config1 = SDRAM_CONFIG1;
sdram_conf.config2 = SDRAM_CONFIG2;
-#if defined(CONFIG_MPC5200)
sdram_conf.tapdelay = 0;
-#endif
-#if defined(CONFIG_MGT5100)
- sdram_conf.addrsel = SDRAM_ADDRSEL;
-#endif
return mpc5xxx_sdram_init (&sdram_conf);
}
int checkboard (void)
{
-#if defined(CONFIG_MPC5200)
#if CONFIG_TOTAL5200_REV==2
puts ("Board: Total5200 Rev.2 ");
#else
puts ("Board: Total5200 ");
#endif
-#elif defined(CONFIG_MGT5100)
- puts ("Board: Total5100 ");
-#endif
/*
* Retrieve FPGA Revision.
return 0;
}
-#if defined(CONFIG_MGT5100)
-int board_early_init_r(void)
-{
- /*
- * Now, when we are in RAM, enable CS0
- * because CS_BOOT cannot be written.
- */
- *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
- *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_PCI
static struct pci_controller hose;
void video_get_info_str (int line_number, char *info)
{
if (line_number == 1) {
-#ifdef CONFIG_MGT5100
- strcpy (info, " Total5100");
-#elif CONFIG_TOTAL5200_REV==1
+#if CONFIG_TOTAL5200_REV==1
strcpy (info, " Total5200");
#elif CONFIG_TOTAL5200_REV==2
strcpy (info, " Total5200 Rev.2");
#define SDRAM_DDR 0 /* is SDR */
-#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */
/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
#define SDRAM_CONFIG2 0x8AD70000
/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE 0x008D0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xC2222600
-#define SDRAM_CONFIG2 0x88B70004
-#define SDRAM_ADDRSEL 0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <miiphy.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
#include <pci.h>
DECLARE_GLOBAL_DATA_PTR;
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_ppc/cache.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/ppc/lib/cache.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
$(obj)trab_fkt.srec: $(OBJS_FKT) $(LIB)
$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e trab_fkt $^ $(LIB) \
-L$(obj)../../examples/standalone -lstubs \
- -L$(obj)../../lib_generic -lgeneric \
+ -L$(obj)../../lib -lgeneric \
$(PLATFORM_LIBS)
$(OBJCOPY) -O srec $(<:.o=) $@
* (C) Copyright 2003
* Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
*
- * Based on cpu/arm920t/serial.c, by Gary Jennejohn
+ * Based on arch/arm/cpu/arm920t/serial.c, by Gary Jennejohn
* (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* (C) Copyright 2003
* Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
*
- * Based on cpu/arm920t/serial.c, by Gary Jennejohn
+ * Based on arch/arm/cpu/arm920t/serial.c, by Gary Jennejohn
* (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* This program is free software; you can redistribute it and/or modify
. = ALIGN(4);
.text :
{
- cpu/arm920t/start.o (.text)
- lib_generic/zlib.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/string.o (.text)
+ arch/arm/cpu/arm920t/start.o (.text)
+ lib/zlib.o (.text)
+ lib/crc32.o (.text)
+ lib/string.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/time.o (.text)
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
common/env_embedded.o(.text)
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot-customlayout.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
+ arch/ppc/lib/cache.o (.text)
+ arch/ppc/lib/time.o (.text)
/*
. = env_offset;
mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
common/env_embedded.o(.text)
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
- * in cpu/ppc4xx
+ * in arch/ppc/cpu/ppc4xx
*/
sdram_init();
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ arch/ppc/lib/ppcstring.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ lib/zlib.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
board/xes/xpedite1000/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
+ arch/ppc/cpu/ppc4xx/kgdb.o (.text)
+ arch/ppc/cpu/ppc4xx/traps.o (.text)
+ arch/ppc/cpu/ppc4xx/interrupts.o (.text)
+ arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/ppc/cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
+ lib/zlib.o (.text)
/* common/env_embedded.o(.text) */
.plt : { *(.plt) }
.text :
{
- cpu/mpc86xx/start.o (.text)
- cpu/mpc86xx/traps.o (.text)
- cpu/mpc86xx/interrupts.o (.text)
- cpu/mpc86xx/cpu_init.o (.text)
- cpu/mpc86xx/cpu.o (.text)
- cpu/mpc86xx/speed.o (.text)
+ arch/ppc/cpu/mpc86xx/start.o (.text)
+ arch/ppc/cpu/mpc86xx/traps.o (.text)
+ arch/ppc/cpu/mpc86xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu_init.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu.o (.text)
+ arch/ppc/cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
+ lib/crc32.o (.text)
+ arch/ppc/lib/extable.o (.text)
+ lib/zlib.o (.text)
*(.text)
*(.got1)
}
.text ALIGN(0x4):
{
__text_start = .;
- cpu/microblaze/start.o (.text)
+ arch/microblaze/cpu/start.o (.text)
*(.text)
__text_end = .;
}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-$(shell mkdir -p $(obj)../xilinx_enet)
-$(shell mkdir -p $(obj)../xilinx_iic)
-endif
-
-INCS := -I../common -I../xilinx_enet -I../xilinx_iic
-CFLAGS += $(INCS)
-HOSTCFLAGS += $(INCS)
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS = $(BOARD).o \
- serial.o \
- ../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \
- ../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \
- ../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \
- ../xilinx_enet/xemac_intr_dma.o ../xilinx_iic/iic_adapter.o \
- ../xilinx_iic/xiic_l.o ../common/xipif_v1_23_b.o \
- ../common/xbasic_types.o ../common/xdma_channel.o \
- ../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \
- ../common/xversion.o \
-
-SOBJS = init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $^
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * init.S: Stubs for U-Boot initialization
- *
- * Author: Xilinx, Inc.
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- *
- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
- * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
- * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
- * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
- * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
- * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
- * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
- * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
- * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
- * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
- * FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * Xilinx hardware products are not intended for use in life support
- * appliances, devices, or systems. Use in such applications is
- * expressly prohibited.
- *
- *
- * (c) Copyright 2002-2004 Xilinx Inc.
- * All rights reserved.
- *
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- */
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- blr
+++ /dev/null
-/*
- * ml300.c: U-Boot platform support for Xilinx ML300 board
- *
- * Author: Xilinx, Inc.
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- *
- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
- * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
- * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
- * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
- * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
- * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
- * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
- * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
- * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
- * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
- * FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * Xilinx hardware products are not intended for use in life support
- * appliances, devices, or systems. Use in such applications is
- * expressly prohibited.
- *
- *
- * (c) Copyright 2002-2004 Xilinx Inc.
- * All rights reserved.
- *
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/processor.h>
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-extern void convert_env(void);
-#endif
-
-int
-board_pre_init(void)
-{
- return 0;
-}
-
-int
-checkboard(void)
-{
- char tmp[64]; /* long enough for environment variables */
- char *s, *e;
- int i = getenv_r("L", tmp, sizeof (tmp));
-
- if (i < 0) {
- printf("### No HW ID - assuming ML300");
- } else {
- for (e = tmp; *e; ++e) {
- if (*e == ' ')
- break;
- }
-
- printf("### Board Serial# is ");
-
- for (s = tmp; s < e; ++s) {
- putc(*s);
- }
-
- }
- putc('\n');
-
- return (0);
-}
-
-phys_size_t
-initdram(int board_type)
-{
- return 128 * 1024 * 1024;
-}
-
-int
-testdram(void)
-{
- printf("test: xxx MB - ok\n");
-
- return (0);
-}
-
-/* implement functions originally in cpu/ppc4xx/speed.c */
-void
-get_sys_info(sys_info_t * sysInfo)
-{
- sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
-
- /* only correct if the PLB and OPB run at the same frequency */
- sysInfo->freqPLB = XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
- sysInfo->freqPCI = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 3;
-}
-
-ulong
-get_PCI_freq(void)
-{
- ulong val;
- PPC4xx_SYS_INFO sys_info;
-
- get_sys_info(&sys_info);
- val = sys_info.freqPCI;
- return val;
-}
-
-#ifdef CONFIG_MISC_INIT_R
-
-int
-misc_init_r()
-{
- /* convert env name and value to u-boot standard */
- convert_env();
- return 0;
-}
-
-#endif
+++ /dev/null
-/*
- * Author: Xilinx, Inc.
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- *
- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
- * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
- * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
- * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
- * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
- * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
- * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
- * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
- * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
- * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
- * FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * Xilinx hardware products are not intended for use in life support
- * appliances, devices, or systems. Use in such applications is
- * expressly prohibited.
- *
- *
- * (c) Copyright 2002-2004 Xilinx Inc.
- * All rights reserved.
- *
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <common.h>
-#include <asm/u-boot.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <config.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define USE_CHAN1 \
- ((defined XPAR_UARTNS550_0_BASEADDR) && (defined CONFIG_SYS_INIT_CHAN1))
-#define USE_CHAN2 \
- ((defined XPAR_UARTNS550_1_BASEADDR) && (defined CONFIG_SYS_INIT_CHAN2))
-
-#if USE_CHAN1
-#include <ns16550.h>
-#endif
-
-#if USE_CHAN1
-const NS16550_t COM_PORTS[] = { (NS16550_t) (XPAR_UARTNS550_0_BASEADDR + 3)
-#if USE_CHAN2
- , (NS16550_t) (XPAR_UARTNS550_1_BASEADDR + 3)
-#endif
-};
-#endif
-
-int
-serial_init(void)
-{
-#if USE_CHAN1
- int clock_divisor;
-
- clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate;
- (void) NS16550_init(COM_PORTS[0], clock_divisor);
-#if USE_CHAN2
- clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate;
- (void) NS16550_init(COM_PORTS[1], clock_divisor);
-#endif
-#endif
- return 0;
-
-}
-
-void
-serial_putc(const char c)
-{
- if (c == '\n')
- NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
-
- NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
-}
-
-int
-serial_getc(void)
-{
- return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-int
-serial_tstc(void)
-{
- return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-void
-serial_setbrg(void)
-{
-#if USE_CHAN1
- int clock_divisor;
-
- clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate;
- NS16550_reinit(COM_PORTS[0], clock_divisor);
-#if USE_CHAN2
- clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate;
- NS16550_reinit(COM_PORTS[1], clock_divisor);
-#endif
-#endif
-}
-
-void
-serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s++);
- }
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void
-kgdb_serial_init(void)
-{
-}
-
-void
-putDebugChar(int c)
-{
- serial_putc(c);
-}
-
-void
-putDebugStr(const char *str)
-{
- serial_puts(str);
-}
-
-int
-getDebugChar(void)
-{
- return serial_getc();
-}
-
-void
-kgdb_interruptible(int yes)
-{
- return;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-ENTRY(_start)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-/*
- cpu/ppc4xx/start.o (.text)
- board/xilinx/ml300/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- drivers/net/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-*/
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by libgen.
-* Version: Xilinx EDK 6.2 EDK_Gm.11
-* DO NOT EDIT.
-*
-* Copyright (c) 2003 Xilinx, Inc. All rights reserved.
-*
-* Description: Driver parameters
-*
-*******************************************************************/
-
-/******************************************************************/
-
-/* U-Boot Redefines */
-
-/******************************************************************/
-
-#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
-#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
-#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
-#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
-#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000)
-#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR
-#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
-#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
-#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
-#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
-#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
-#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
-#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
-#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
-#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
-#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
-
-/******************************************************************/
-
-#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
-#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
-#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
-
-/******************************************************************/
-
-#define XPAR_XPCI_NUM_INSTANCES 1
-#define XPAR_XPCI_CLOCK_HZ 33333333
-#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0
-#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000
-#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF
-#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000
-#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004
-#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000
-#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000
-#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF
-#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000
-#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF
-
-/******************************************************************/
-
-#define XPAR_XEMAC_NUM_INSTANCES 1
-#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
-#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
-#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
-#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
-#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
-
-/******************************************************************/
-
-#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0
-#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000
-#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7)
-#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1
-#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8)
-#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F)
-#define XPAR_XGPIO_NUM_INSTANCES 2
-
-/******************************************************************/
-
-#define XPAR_XIIC_NUM_INSTANCES 1
-#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
-#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
-#define XPAR_OPB_IIC_0_DEVICE_ID 0
-#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
-
-/******************************************************************/
-
-#define XPAR_XUARTNS550_NUM_INSTANCES 2
-#define XPAR_XUARTNS550_CLOCK_HZ 100000000
-#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
-#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
-#define XPAR_OPB_UART16550_0_DEVICE_ID 0
-#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000
-#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF
-#define XPAR_OPB_UART16550_1_DEVICE_ID 1
-
-/******************************************************************/
-
-#define XPAR_XSPI_NUM_INSTANCES 1
-#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000
-#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F
-#define XPAR_OPB_SPI_0_DEVICE_ID 0
-#define XPAR_OPB_SPI_0_FIFO_EXIST 1
-#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0
-#define XPAR_OPB_SPI_0_NUM_SS_BITS 1
-
-/******************************************************************/
-
-#define XPAR_XPS2_NUM_INSTANCES 2
-#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
-#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
-#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
-#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
-#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
-#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
-
-/******************************************************************/
-
-#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1
-#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000
-#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007
-#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0
-
-/******************************************************************/
-
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
-#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000
-#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF
-#define XPAR_PLB_DDR_0_BASEADDR 0x00000000
-#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF
-
-/******************************************************************/
-
-#define XPAR_XINTC_HAS_IPR 1
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18
-#define XPAR_XINTC_USE_DCR 0
-#define XPAR_XINTC_NUM_INSTANCES 1
-#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0
-#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF
-#define XPAR_DCR_INTC_0_DEVICE_ID 0
-#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000
-
-/******************************************************************/
-
-#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0
-#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1
-#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2
-#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3
-#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4
-#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5
-#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6
-#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7
-#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
-#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9
-#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10
-#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11
-#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12
-#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13
-#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14
-#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15
-#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16
-#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17
-
-/******************************************************************/
-
-#define XPAR_XTFT_NUM_INSTANCES 1
-#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
-#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
-#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
-
-/******************************************************************/
-
-#define XPAR_XSYSACE_MEM_WIDTH 8
-#define XPAR_XSYSACE_NUM_INSTANCES 1
-#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
-#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
-#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
-#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8
-
-/******************************************************************/
-
-#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
-
-/******************************************************************/
.bootpg 0xFFFFF000 :
{
- cpu/ppc4xx/start.o (.bootpg)
+ arch/ppc/cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
#include <ppc_asm.tmpl>
#include <config.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
.section .bootpg,"ax"
.globl tlbtab
.bootpg 0xFFFFF000 :
{
- cpu/ppc4xx/start.o (.bootpg)
+ arch/ppc/cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-
-#include <config.h>
-#include <common.h>
-#include <environment.h>
-#include <net.h>
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#include <i2c.h>
-#include "xiic_l.h"
-
-#define IIC_DELAY 5000
-
-static u8 envStep = 0; /* 0 means crc has not been read */
-const u8 hex[] = "0123456789ABCDEF"; /* lookup table for ML300 CRC */
-
-/************************************************************************
- * Use Xilinx provided driver to send data to EEPROM using iic bus.
- */
-static void
-send(u32 adr, u8 * data, u32 len)
-{
- u8 sendBuf[34]; /* first 2-bit is address and others are data */
- u32 pos, wlen;
- u32 ret;
-
- wlen = 32;
- for (pos = 0; pos < len; pos += 32) {
- if ((len - pos) < 32)
- wlen = len - pos;
-
- /* Put address and data bits together */
- sendBuf[0] = (u8) ((adr + pos) >> 8);
- sendBuf[1] = (u8) (adr + pos);
- memcpy(&sendBuf[2], &data[pos], wlen);
-
- /* Send to EEPROM through iic bus */
- ret = XIic_Send(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1,
- sendBuf, wlen + 2);
-
- udelay(IIC_DELAY);
- }
-}
-
-/************************************************************************
- * Use Xilinx provided driver to read data from EEPROM using the iic bus.
- */
-static void
-receive(u32 adr, u8 * data, u32 len)
-{
- u8 address[2];
- u32 ret;
-
- address[0] = (u8) (adr >> 8);
- address[1] = (u8) adr;
-
- /* Provide EEPROM address */
- ret =
- XIic_Send(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1, address,
- 2);
- /* Receive data from EEPROM */
- ret =
- XIic_Recv(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1, data, len);
-}
-
-/************************************************************************
- * Convert a hexadecimal string to its equivalent integer value.
- */
-static u8
-axtoi(u8 * hexStg)
-{
- u8 n; /* position in string */
- u8 m; /* position in digit[] to shift */
- u8 count; /* loop index */
- u8 intValue; /* integer value of hex string */
- u8 digit[2]; /* hold values to convert */
-
- for (n = 0; n < 2; n++) {
- if (hexStg[n] == '\0')
- break;
- if (hexStg[n] > 0x29 && hexStg[n] < 0x40)
- digit[n] = hexStg[n] & 0x0f;
- else if (hexStg[n] >= 'a' && hexStg[n] <= 'f')
- digit[n] = (hexStg[n] & 0x0f) + 9;
- else if (hexStg[n] >= 'A' && hexStg[n] <= 'F')
- digit[n] = (hexStg[n] & 0x0f) + 9;
- else
- break;
- }
-
- intValue = 0;
- count = n;
- m = n - 1;
- n = 0;
- while (n < count) {
- intValue = intValue | (digit[n] << (m << 2));
- m--; /* adjust the position to set */
- n++; /* next digit to process */
- }
-
- return (intValue);
-}
-
-/************************************************************************
- * Convert an integer string to its equivalent value.
- */
-static u8
-atoi(uchar * string)
-{
- u8 res = 0;
- while (*string >= '0' && *string <= '9') {
- res *= 10;
- res += *string - '0';
- string++;
- }
-
- return res;
-}
-
-/************************************************************************
- * Key-value pairs are separated by "=" sign.
- */
-static void
-findKey(uchar * buffer, int *loc, u8 len)
-{
- u32 i;
-
- for (i = 0; i < len; i++)
- if (buffer[i] == '=') {
- *loc = i;
- return;
- }
-
- /* return -1 is no "=" sign found */
- *loc = -1;
-}
-
-/************************************************************************
- * Compute a new ML300 CRC when user calls the saveenv command.
- * Also update EEPROM with new CRC value.
- */
-static u8
-update_crc(u32 len, uchar * data)
-{
- uchar temp[6] = { 'C', '=', 0x00, 0x00, 0x00, 0x00 };
- u32 crc; /* new crc value */
- u32 i;
-
- crc = 0;
-
- /* calculate new CRC */
- for (i = 0; i < len; i++)
- crc += data[i];
-
- /* CRC includes key for check sum */
- crc += 'C' + '=';
-
- /* compose new CRC to be updated */
- temp[2] = hex[(crc >> 4) & 0xf];
- temp[3] = hex[crc & 0xf];
-
- /* check to see if env size exceeded */
- if (len + 6 > ENV_SIZE) {
- printf("ERROR: not enough space to store CRC on EEPROM");
- return 1;
- }
-
- memcpy(data + len, temp, 6);
- return 0;
-}
-
-/************************************************************************
- * Read out ML300 CRC and compare it with a runtime calculated ML300 CRC.
- * If equal, then pass back a u-boot CRC value, otherwise pass back
- * junk to indicate CRC error.
-*/
-static void
-read_crc(uchar * buffer, int len)
-{
- u32 addr, n;
- u32 crc; /* runtime crc */
- u8 old[2] = { 0xff, 0xff }; /* current CRC in EEPROM */
- u8 stop; /* indication of end of env data */
- u8 pre; /* previous EEPROM data bit */
- int i, loc;
-
- addr = CONFIG_ENV_OFFSET; /* start from first env address */
- n = 0;
- pre = 1;
- stop = 1;
- crc = 0;
-
- /* calculate runtime CRC according to ML300 and read back
- old CRC stored in the EEPROM */
- while (n < CONFIG_ENV_SIZE) {
- receive(addr, buffer, len);
-
- /* found two null chars, end of env */
- if ((pre || buffer[0]) == 0)
- break;
-
- findKey(buffer, &loc, len);
-
- /* found old check sum, read and store old CRC */
- if ((loc == 0 && pre == 'C')
- || (loc > 0 && buffer[loc - 1] == 'C'))
- receive(addr + loc + 1, old, 2);
-
- pre = buffer[len - 1];
-
- /* calculate runtime ML300 CRC */
- crc += buffer[0];
- i = 1;
- do {
- crc += buffer[i];
- stop = buffer[i] || buffer[i - 1];
- i++;
- } while (stop && (i < len));
-
- if (stop == 0)
- break;
-
- n += len;
- addr += len;
- }
-
- /* exclude old CRC from runtime calculation */
- crc -= (old[0] + old[1]);
-
- /* match CRC values, send back u-boot CRC */
- if ((old[0] == hex[(crc >> 4) & 0xf])
- && (old[1] == hex[crc & 0xf])) {
- crc = 0;
- n = 0;
- addr =
- CONFIG_ENV_OFFSET - offsetof(env_t, crc) + offsetof(env_t,
- data);
- /* calculate u-boot crc */
- while (n < ENV_SIZE) {
- receive(addr, buffer, len);
- crc = crc32(crc, buffer, len);
- n += len;
- addr += len;
- }
-
- memcpy(buffer, &crc, 4);
- }
-}
-
-/************************************************************************
- * Convert IP address to hexadecimals.
- */
-static void
-ip_ml300(uchar * s, uchar * res)
-{
- char temp[2];
- u8 i;
-
- res[0] = 0x00;
-
- for (i = 0; i < 4; i++) {
- sprintf(temp, "%02x", atoi(s));
- s = (uchar *)strchr((char *)s, '.') + 1;
- strcat((char *)res, temp);
- }
-}
-
-/************************************************************************
- * Change 0xff (255), a dummy null char to 0x00.
- */
-static void
-change_null(uchar * s)
-{
- if (s != NULL) {
- change_null((uchar *)strchr((char *)s + 1, 255));
- *(strchr((char *)s, 255)) = '\0';
- }
-}
-
-/************************************************************************
- * Update environment variable name and values to u-boot standard.
- */
-void
-convert_env(void)
-{
- char *s; /* pointer to env value */
- char temp[20]; /* temp storage for addresses */
-
- /* E -> ethaddr */
- s = getenv("E");
- if (s != NULL) {
- sprintf(temp, "%c%c.%c%c.%c%c.%c%c.%c%c.%c%c",
- s[0], s[1], s[ 2], s[ 3],
- s[4], s[5], s[ 6], s[ 7],
- s[8], s[9], s[10], s[11] );
- setenv("ethaddr", temp);
- setenv("E", NULL);
- }
-
- /* L -> serial# */
- s = getenv("L");
- if (s != NULL) {
- setenv("serial#", s);
- setenv("L", NULL);
- }
-
- /* I -> ipaddr */
- s = getenv("I");
- if (s != NULL) {
- sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)),
- axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6)));
- setenv("ipaddr", temp);
- setenv("I", NULL);
- }
-
- /* S -> serverip */
- s = getenv("S");
- if (s != NULL) {
- sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)),
- axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6)));
- setenv("serverip", temp);
- setenv("S", NULL);
- }
-
- /* A -> bootargs */
- s = getenv("A");
- if (s != NULL) {
- setenv("bootargs", s);
- setenv("A", NULL);
- }
-
- /* F -> bootfile */
- s = getenv("F");
- if (s != NULL) {
- setenv("bootfile", s);
- setenv("F", NULL);
- }
-
- /* M -> bootcmd */
- s = getenv("M");
- if (s != NULL) {
- setenv("bootcmd", s);
- setenv("M", NULL);
- }
-
- /* Don't include C (CRC) */
- setenv("C", NULL);
-}
-
-/************************************************************************
- * Save user modified environment values back to EEPROM.
- */
-static void
-save_env(void)
-{
- char eprom[ENV_SIZE]; /* buffer to be written back to EEPROM */
- char *s, temp[20];
- char ff[] = { 0xff, 0x00 }; /* dummy null value */
- u32 len; /* length of env to be written to EEPROM */
-
- eprom[0] = 0x00;
-
- /* ethaddr -> E */
- s = getenv("ethaddr");
- if (s != NULL) {
- strcat(eprom, "E=");
- sprintf(temp, "%c%c%c%c%c%c%c%c%c%c%c%c",
- *s, *(s + 1), *(s + 3), *(s + 4), *(s + 6), *(s + 7),
- *(s + 9), *(s + 10), *(s + 12), *(s + 13), *(s + 15),
- *(s + 16));
- strcat(eprom, temp);
- strcat(eprom, ff);
- }
-
- /* serial# -> L */
- s = getenv("serial#");
- if (s != NULL) {
- strcat(eprom, "L=");
- strcat(eprom, s);
- strcat(eprom, ff);
- }
-
- /* ipaddr -> I */
- s = getenv("ipaddr");
- if (s != NULL) {
- strcat(eprom, "I=");
- ip_ml300((uchar *)s, (uchar *)temp);
- strcat(eprom, temp);
- strcat(eprom, ff);
- }
-
- /* serverip -> S */
- s = getenv("serverip");
- if (s != NULL) {
- strcat(eprom, "S=");
- ip_ml300((uchar *)s, (uchar *)temp);
- strcat(eprom, temp);
- strcat(eprom, ff);
- }
-
- /* bootargs -> A */
- s = getenv("bootargs");
- if (s != NULL) {
- strcat(eprom, "A=");
- strcat(eprom, s);
- strcat(eprom, ff);
- }
-
- /* bootfile -> F */
- s = getenv("bootfile");
- if (s != NULL) {
- strcat(eprom, "F=");
- strcat(eprom, s);
- strcat(eprom, ff);
- }
-
- /* bootcmd -> M */
- s = getenv("bootcmd");
- if (s != NULL) {
- strcat(eprom, "M=");
- strcat(eprom, s);
- strcat(eprom, ff);
- }
-
- len = strlen(eprom); /* find env length without crc */
- change_null((uchar *)eprom); /* change 0xff to 0x00 */
-
- /* update EEPROM env values if there is enough space */
- if (update_crc(len, (uchar *)eprom) == 0)
- send(CONFIG_ENV_OFFSET, (uchar *)eprom, len + 6);
-}
-
-/************************************************************************
- * U-boot call for EEPROM read associated activities.
- */
-int
-i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
-
- if (envStep == 0) {
- /* first read call is for crc */
- read_crc(buffer, len);
- ++envStep;
- return 0;
- } else if (envStep == 1) {
- /* then read out EEPROM content for runtime u-boot CRC calculation */
- receive(addr, buffer, len);
-
- if (addr + len - CONFIG_ENV_OFFSET == CONFIG_ENV_SIZE)
- /* end of runtime crc read */
- ++envStep;
- return 0;
- }
-
- if (len < 2) {
- /* when call getenv_r */
- receive(addr, buffer, len);
- } else if (addr + len < CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) {
- /* calling env_relocate(), but don't read out
- crc value from EEPROM */
- receive(addr, buffer + 4, len);
- } else {
- receive(addr, buffer + 4, len - 4);
- }
-
- return 0;
-
-}
-
-/************************************************************************
- * U-boot call for EEPROM write acativities.
- */
-int
-i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
- /* save env on last page write called by u-boot */
- if (addr + len >= CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
- save_env();
-
- return 0;
-}
-
-/************************************************************************
- * Dummy function.
- */
-int
-i2c_probe(uchar chip)
-{
- return 1;
-}
-
-#endif
static void print_num(const char *, ulong);
-#if !defined(CONFIG_ARM) || defined(CONFIG_CMD_NET)
+#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K)) || defined(CONFIG_CMD_NET)
static void print_eth(int idx);
#endif
printf ("%-12s= 0x%08lX\n", name, value);
}
-#if !defined(CONFIG_ARM) || defined(CONFIG_CMD_NET)
+#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K)) || defined(CONFIG_CMD_NET)
static void print_eth(int idx)
{
char name[10], *val;
}
#endif
+static int do_bmp_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ ulong addr;
-/*
- * Subroutine: do_bmp
- *
- * Description: Handler for 'bmp' command..
- *
- * Inputs: argv[1] contains the subcommand
- *
- * Return: None
- *
- */
-int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ switch (argc) {
+ case 1: /* use load_addr as default address */
+ addr = load_addr;
+ break;
+ case 2: /* use argument */
+ addr = simple_strtoul(argv[1], NULL, 16);
+ break;
+ default:
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ return (bmp_info(addr));
+}
+
+static int do_bmp_display(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
ulong addr;
int x = 0, y = 0;
switch (argc) {
- case 2: /* use load_addr as default address */
+ case 1: /* use load_addr as default address */
addr = load_addr;
break;
- case 3: /* use argument */
- addr = simple_strtoul(argv[2], NULL, 16);
+ case 2: /* use argument */
+ addr = simple_strtoul(argv[1], NULL, 16);
break;
- case 5:
- addr = simple_strtoul(argv[2], NULL, 16);
- x = simple_strtoul(argv[3], NULL, 10);
- y = simple_strtoul(argv[4], NULL, 10);
+ case 4:
+ addr = simple_strtoul(argv[1], NULL, 16);
+ x = simple_strtoul(argv[2], NULL, 10);
+ y = simple_strtoul(argv[3], NULL, 10);
break;
default:
cmd_usage(cmdtp);
return 1;
}
- /* Allow for short names
- * Adjust length if more sub-commands get added
- */
- if (strncmp(argv[1],"info",1) == 0) {
- return (bmp_info(addr));
- } else if (strncmp(argv[1],"display",1) == 0) {
- return (bmp_display(addr, x, y));
+ return (bmp_display(addr, x, y));
+}
+
+static cmd_tbl_t cmd_bmp_sub[] = {
+ U_BOOT_CMD_MKENT(info, 3, 0, do_bmp_info, "", ""),
+ U_BOOT_CMD_MKENT(display, 5, 0, do_bmp_display, "", ""),
+};
+
+/*
+ * Subroutine: do_bmp
+ *
+ * Description: Handler for 'bmp' command..
+ *
+ * Inputs: argv[1] contains the subcommand
+ *
+ * Return: None
+ *
+ */
+static int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ cmd_tbl_t *c;
+
+ /* Strip off leading 'bmp' command argument */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], &cmd_bmp_sub[0], ARRAY_SIZE(cmd_bmp_sub));
+
+ if (c) {
+ return c->cmd(cmdtp, flag, argc, argv);
} else {
cmd_usage(cmdtp);
return 1;
return 1;
}
- if ((images.os.type == IH_TYPE_KERNEL) &&
+ if (((images.os.type == IH_TYPE_KERNEL) ||
+ (images.os.type == IH_TYPE_MULTI)) &&
(images.os.os == IH_OS_LINUX)) {
/* find ramdisk */
ret = boot_get_ramdisk (argc, argv, &images, IH_INITRD_ARCH,
/* we overload the cmd field with our state machine info instead of a
* function pointer */
-cmd_tbl_t cmd_bootm_sub[] = {
+static cmd_tbl_t cmd_bootm_sub[] = {
U_BOOT_CMD_MKENT(start, 0, 1, (void *)BOOTM_STATE_START, "", ""),
U_BOOT_CMD_MKENT(loados, 0, 1, (void *)BOOTM_STATE_LOADOS, "", ""),
#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC)
#endif
+#define DISP_LINE_LEN 16
+
/* TODO: Implement architecture-specific get/set functions */
unsigned int __def_i2c_get_bus_speed(void)
{
int i2c_set_bus_speed(unsigned int)
__attribute__((weak, alias("__def_i2c_set_bus_speed")));
+/*
+ * get_alen: small parser helper function to get address length
+ * returns the address length,or 0 on error
+ */
+static uint get_alen(char *arg)
+{
+ int j;
+ int alen;
+
+ alen = 1;
+ for (j = 0; j < 8; j++) {
+ if (arg[j] == '.') {
+ alen = arg[j+1] - '0';
+ if (alen > 3) {
+ return 0;
+ }
+ break;
+ } else if (arg[j] == '\0')
+ break;
+ }
+ return alen;
+}
+
/*
* Syntax:
- * i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
+ * i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr}
*/
-#define DISP_LINE_LEN 16
-int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ u_char chip;
+ uint devaddr, alen, length;
+ u_char *memaddr;
+
+ if (argc != 5) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ /*
+ * I2C chip address
+ */
+ chip = simple_strtoul(argv[1], NULL, 16);
+
+ /*
+ * I2C data address within the chip. This can be 1 or
+ * 2 bytes long. Some day it might be 3 bytes long :-).
+ */
+ devaddr = simple_strtoul(argv[2], NULL, 16);
+ alen = get_alen(argv[2]);
+ if (alen == 0) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ /*
+ * Length is the number of objects, not number of bytes.
+ */
+ length = simple_strtoul(argv[3], NULL, 16);
+
+ /*
+ * memaddr is the address where to store things in memory
+ */
+ memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
+
+ if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) {
+ puts ("Error reading the chip.\n");
+ return 1;
+ }
+ return 0;
+}
+
+/*
+ * Syntax:
+ * i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
+ */
+static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
u_char chip;
uint addr, alen, length;
/*
* New command specified.
*/
- alen = 1;
/*
* I2C chip address
* 2 bytes long. Some day it might be 3 bytes long :-).
*/
addr = simple_strtoul(argv[2], NULL, 16);
- alen = 1;
- for (j = 0; j < 8; j++) {
- if (argv[2][j] == '.') {
- alen = argv[2][j+1] - '0';
- if (alen > 4) {
- cmd_usage(cmdtp);
- return 1;
- }
- break;
- } else if (argv[2][j] == '\0')
- break;
+ alen = get_alen(argv[2]);
+ if (alen == 0) {
+ cmd_usage(cmdtp);
+ return 1;
}
/*
* Syntax:
* i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
*/
-int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
uchar chip;
ulong addr;
uint alen;
uchar byte;
int count;
- int j;
if ((argc < 4) || (argc > 5)) {
cmd_usage(cmdtp);
* Address is always specified.
*/
addr = simple_strtoul(argv[2], NULL, 16);
- alen = 1;
- for (j = 0; j < 8; j++) {
- if (argv[2][j] == '.') {
- alen = argv[2][j+1] - '0';
- if (alen > 4) {
- cmd_usage(cmdtp);
- return 1;
- }
- break;
- } else if (argv[2][j] == '\0')
- break;
+ alen = get_alen(argv[2]);
+ if (alen == 0) {
+ cmd_usage(cmdtp);
+ return 1;
}
/*
* Syntax:
* i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count}
*/
-int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
uchar chip;
ulong addr;
uchar byte;
ulong crc;
ulong err;
- int j;
if (argc < 4) {
cmd_usage(cmdtp);
* Address is always specified.
*/
addr = simple_strtoul(argv[2], NULL, 16);
- alen = 1;
- for (j = 0; j < 8; j++) {
- if (argv[2][j] == '.') {
- alen = argv[2][j+1] - '0';
- if (alen > 4) {
- cmd_usage(cmdtp);
- return 1;
- }
- break;
- } else if (argv[2][j] == '\0')
- break;
+ alen = get_alen(argv[2]);
+ if (alen == 0) {
+ cmd_usage(cmdtp);
+ return 1;
}
/*
ulong data;
int size = 1;
int nbytes;
- int j;
extern char console_buffer[];
if (argc != 3) {
* Address is always specified.
*/
addr = simple_strtoul(argv[2], NULL, 16);
- alen = 1;
- for (j = 0; j < 8; j++) {
- if (argv[2][j] == '.') {
- alen = argv[2][j+1] - '0';
- if (alen > 4) {
- cmd_usage(cmdtp);
- return 1;
- }
- break;
- } else if (argv[2][j] == '\0')
- break;
+ alen = get_alen(argv[2]);
+ if (alen == 0) {
+ cmd_usage(cmdtp);
+ return 1;
}
}
* Syntax:
* i2c probe {addr}{.0, .1, .2}
*/
-int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int j;
#if defined(CONFIG_SYS_I2C_NOPROBES)
* {length} - Number of bytes to read
* {delay} - A DECIMAL number and defaults to 1000 uSec
*/
-int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
u_char chip;
ulong alen;
uint length;
u_char bytes[16];
int delay;
- int j;
if (argc < 3) {
cmd_usage(cmdtp);
* Address is always specified.
*/
addr = simple_strtoul(argv[2], NULL, 16);
- alen = 1;
- for (j = 0; j < 8; j++) {
- if (argv[2][j] == '.') {
- alen = argv[2][j+1] - '0';
- if (alen > 4) {
- cmd_usage(cmdtp);
- return 1;
- }
- break;
- } else if (argv[2][j] == '\0')
- break;
+ alen = get_alen(argv[2]);
+ if (alen == 0) {
+ cmd_usage(cmdtp);
+ return 1;
}
/*
* Syntax:
* i2c sdram {i2c_chip}
*/
-int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
enum { unknown, EDO, SDRAM, DDR2 } type;
#endif
#if defined(CONFIG_I2C_MUX)
-int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int ret=0;
#endif /* CONFIG_I2C_MUX */
#if defined(CONFIG_I2C_MULTI_BUS)
-int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int bus_idx, ret=0;
}
#endif /* CONFIG_I2C_MULTI_BUS */
-int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int speed, ret=0;
return ret;
}
-int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
- /* Strip off leading 'i2c' command argument */
- argc--;
- argv++;
+ return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
+}
+static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
+}
+
+static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ return 0;
+}
+
+static cmd_tbl_t cmd_i2c_sub[] = {
#if defined(CONFIG_I2C_MUX)
- if (!strncmp(argv[0], "bu", 2))
- return do_i2c_add_bus(cmdtp, flag, argc, argv);
+ U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_add_bus, "", ""),
#endif /* CONFIG_I2C_MUX */
- if (!strncmp(argv[0], "sp", 2))
- return do_i2c_bus_speed(cmdtp, flag, argc, argv);
+ U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
#if defined(CONFIG_I2C_MULTI_BUS)
- if (!strncmp(argv[0], "de", 2))
- return do_i2c_bus_num(cmdtp, flag, argc, argv);
+ U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
#endif /* CONFIG_I2C_MULTI_BUS */
- if (!strncmp(argv[0], "md", 2))
- return do_i2c_md(cmdtp, flag, argc, argv);
- if (!strncmp(argv[0], "mm", 2))
- return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
- if (!strncmp(argv[0], "mw", 2))
- return do_i2c_mw(cmdtp, flag, argc, argv);
- if (!strncmp(argv[0], "nm", 2))
- return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
- if (!strncmp(argv[0], "cr", 2))
- return do_i2c_crc(cmdtp, flag, argc, argv);
- if (!strncmp(argv[0], "pr", 2))
- return do_i2c_probe(cmdtp, flag, argc, argv);
- if (!strncmp(argv[0], "re", 2)) {
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- return 0;
- }
- if (!strncmp(argv[0], "lo", 2))
- return do_i2c_loop(cmdtp, flag, argc, argv);
+ U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
+ U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
+ U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
+ U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
+ U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
+ U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
+ U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
+ U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
#if defined(CONFIG_CMD_SDRAM)
- if (!strncmp(argv[0], "sd", 2))
- return do_sdram(cmdtp, flag, argc, argv);
+ U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
#endif
- cmd_usage(cmdtp);
- return 0;
+ U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
+};
+
+static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ cmd_tbl_t *c;
+
+ /* Strip off leading 'i2c' command argument */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
+
+ if (c) {
+ return c->cmd(cmdtp, flag, argc, argv);
+ } else {
+ cmd_usage(cmdtp);
+ return 1;
+ }
}
/***************************************************/
U_BOOT_CMD(
i2c, 6, 1, do_i2c,
"I2C sub-system",
- "speed [speed] - show or set I2C bus speed\n"
#if defined(CONFIG_I2C_MUX)
- "i2c bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\n"
+ "bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\ni2c "
#endif /* CONFIG_I2C_MUX */
+ "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
#if defined(CONFIG_I2C_MULTI_BUS)
"i2c dev [dev] - show or set current I2C bus\n"
#endif /* CONFIG_I2C_MULTI_BUS */
+ "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
"i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
"i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
"i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
"i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
- "i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
"i2c probe - show devices on the I2C bus\n"
+ "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
"i2c reset - re-init the I2C Controller\n"
- "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device"
#if defined(CONFIG_CMD_SDRAM)
- "\n"
- "i2c sdram chip - print SDRAM configuration information"
+ "i2c sdram chip - print SDRAM configuration information\n"
#endif
+ "i2c speed [speed] - show or set I2C bus speed"
);
#if defined(CONFIG_I2C_MUX)
-
-int i2c_mux_add_device(I2C_MUX_DEVICE *dev)
+static int i2c_mux_add_device(I2C_MUX_DEVICE *dev)
{
I2C_MUX_DEVICE *devtmp = i2c_mux_devices;
* @param num device number
* @return NULL if requested device does not exist
*/
-static struct mtd_device* device_find(u8 type, u8 num)
+struct mtd_device *device_find(u8 type, u8 num)
{
struct list_head *entry;
struct mtd_device *dev_tmp;
"are sure of what you are doing!\n"
"\nReally scrub this NAND flash? <y/N>\n");
- if (getc() == 'y' && getc() == '\r') {
- opts.scrub = 1;
+ if (getc() == 'y') {
+ puts("y");
+ if (getc() == '\r')
+ opts.scrub = 1;
+ else {
+ puts("scrub aborted\n");
+ return -1;
+ }
} else {
puts("scrub aborted\n");
return -1;
#include <config.h>
#include <command.h>
+static ulong get_arg(char *s, int w)
+{
+ ulong *p;
+
+ /*
+ * if the parameter starts with a '*' then assume
+ * it is a pointer to the value we want
+ */
+
+ if (s[0] == '*') {
+ p = (ulong *)simple_strtoul(&s[1], NULL, 16);
+ switch (w) {
+ case 1: return((ulong)(*(uchar *)p));
+ case 2: return((ulong)(*(ushort *)p));
+ case 4:
+ default: return(*p);
+ }
+ } else {
+ return simple_strtoul(s, NULL, 16);
+ }
+}
+
int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong a, b;
char buf[16];
+ int w;
/* Validate arguments */
if ((argc != 5) || (strlen(argv[3]) != 1)) {
return 1;
}
- a = simple_strtoul(argv[2], NULL, 16);
- b = simple_strtoul(argv[4], NULL, 16);
+ w = cmd_get_data_size(argv[0], 4);
+
+ a = get_arg(argv[2], w);
+ b = get_arg(argv[4], w);
switch (argv[3][0]) {
case '|': sprintf(buf, "%lx", (a | b)); break;
U_BOOT_CMD(
setexpr, 5, 0, do_setexpr,
"set environment variable as the result of eval expression",
- "name value1 <op> value2\n"
+ "[.b, .w, .l] name value1 <op> value2\n"
" - set environment variable 'name' to the result of the evaluated\n"
- " express specified by <op>. <op> can be &, |, ^, +, -, *, /, %"
+ " express specified by <op>. <op> can be &, |, ^, +, -, *, /, %\n"
+ " size argument is only meaningful if value1 and/or value2 are memory addresses"
);
{
int i, err, reserved_pebs;
int found = 0, vol_id = 0;
- struct ubi_volume *vol;
+ struct ubi_volume *vol = NULL;
for (i = 0; i < ubi->vtbl_slots; i++) {
vol = ubi->volumes[i];
dev = simple_strtoul(boot_device, &ep, 16);
stor_dev = usb_stor_get_dev(dev);
- if (stor_dev->type == DEV_TYPE_UNKNOWN) {
+ if (stor_dev == NULL || stor_dev->type == DEV_TYPE_UNKNOWN) {
printf("\n** Device %d not available\n", dev);
return 1;
}
if (strncmp(argv[1], "part", 4) == 0) {
int devno, ok = 0;
if (argc == 2) {
- for (devno = 0; devno < USB_MAX_STOR_DEV; ++devno) {
+ for (devno = 0; ; ++devno) {
stor_dev = usb_stor_get_dev(devno);
+ if (stor_dev == NULL)
+ break;
if (stor_dev->type != DEV_TYPE_UNKNOWN) {
ok++;
if (devno)
printf("\n");
- printf("print_part of %x\n", devno);
+ debug("print_part of %x\n", devno);
print_part(stor_dev);
}
}
} else {
devno = simple_strtoul(argv[2], NULL, 16);
stor_dev = usb_stor_get_dev(devno);
- if (stor_dev->type != DEV_TYPE_UNKNOWN) {
+ if (stor_dev != NULL &&
+ stor_dev->type != DEV_TYPE_UNKNOWN) {
ok++;
- printf("print_part of %x\n", devno);
+ debug("print_part of %x\n", devno);
print_part(stor_dev);
}
}
if (argc == 3) {
int dev = (int)simple_strtoul(argv[2], NULL, 10);
printf("\nUSB device %d: ", dev);
- if (dev >= USB_MAX_STOR_DEV) {
+ stor_dev = usb_stor_get_dev(dev);
+ if (stor_dev == NULL) {
printf("unknown device\n");
return 1;
}
printf("\n Device %d: ", dev);
- stor_dev = usb_stor_get_dev(dev);
dev_print(stor_dev);
if (stor_dev->type == DEV_TYPE_UNKNOWN)
return 1;
ulong new = old + increment;
if ((new < mem_malloc_start) || (new > mem_malloc_end))
- return NULL;
+ return (void *)MORECORE_FAILURE;
mem_malloc_brk = new;
return -1;
}
#endif
+
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+
+struct reg_cell {
+ unsigned int r0;
+ unsigned int r1;
+};
+
+int fdt_del_subnodes(const void *blob, int parent_offset)
+{
+ int off, ndepth;
+ int ret;
+
+ for (ndepth = 0, off = fdt_next_node(blob, parent_offset, &ndepth);
+ (off >= 0) && (ndepth > 0);
+ off = fdt_next_node(blob, off, &ndepth)) {
+ if (ndepth == 1) {
+ debug("delete %s: offset: %x\n",
+ fdt_get_name(blob, off, 0), off);
+ ret = fdt_del_node((void *)blob, off);
+ if (ret < 0) {
+ printf("Can't delete node: %s\n",
+ fdt_strerror(ret));
+ return ret;
+ } else {
+ ndepth = 0;
+ off = parent_offset;
+ }
+ }
+ }
+ return 0;
+}
+
+int fdt_increase_size(void *fdt, int add_len)
+{
+ int newlen;
+
+ newlen = fdt_totalsize(fdt) + add_len;
+
+ /* Open in place with a new len */
+ return fdt_open_into(fdt, fdt, newlen);
+}
+
+int fdt_del_partitions(void *blob, int parent_offset)
+{
+ const void *prop;
+ int ndepth = 0;
+ int off;
+ int ret;
+
+ off = fdt_next_node(blob, parent_offset, &ndepth);
+ if (off > 0 && ndepth == 1) {
+ prop = fdt_getprop(blob, off, "label", NULL);
+ if (prop == NULL) {
+ /*
+ * Could not find label property, nand {}; node?
+ * Check subnode, delete partitions there if any.
+ */
+ return fdt_del_partitions(blob, off);
+ } else {
+ ret = fdt_del_subnodes(blob, parent_offset);
+ if (ret < 0) {
+ printf("Can't remove subnodes: %s\n",
+ fdt_strerror(ret));
+ return ret;
+ }
+ }
+ }
+ return 0;
+}
+
+int fdt_node_set_part_info(void *blob, int parent_offset,
+ struct mtd_device *dev)
+{
+ struct list_head *pentry;
+ struct part_info *part;
+ struct reg_cell cell;
+ int off, ndepth = 0;
+ int part_num, ret;
+ char buf[64];
+
+ ret = fdt_del_partitions(blob, parent_offset);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * Check if it is nand {}; subnode, adjust
+ * the offset in this case
+ */
+ off = fdt_next_node(blob, parent_offset, &ndepth);
+ if (off > 0 && ndepth == 1)
+ parent_offset = off;
+
+ part_num = 0;
+ list_for_each_prev(pentry, &dev->parts) {
+ int newoff;
+
+ part = list_entry(pentry, struct part_info, link);
+
+ debug("%2d: %-20s0x%08x\t0x%08x\t%d\n",
+ part_num, part->name, part->size,
+ part->offset, part->mask_flags);
+
+ sprintf(buf, "partition@%x", part->offset);
+add_sub:
+ ret = fdt_add_subnode(blob, parent_offset, buf);
+ if (ret == -FDT_ERR_NOSPACE) {
+ ret = fdt_increase_size(blob, 512);
+ if (!ret)
+ goto add_sub;
+ else
+ goto err_size;
+ } else if (ret < 0) {
+ printf("Can't add partition node: %s\n",
+ fdt_strerror(ret));
+ return ret;
+ }
+ newoff = ret;
+
+ /* Check MTD_WRITEABLE_CMD flag */
+ if (part->mask_flags & 1) {
+add_ro:
+ ret = fdt_setprop(blob, newoff, "read_only", NULL, 0);
+ if (ret == -FDT_ERR_NOSPACE) {
+ ret = fdt_increase_size(blob, 512);
+ if (!ret)
+ goto add_ro;
+ else
+ goto err_size;
+ } else if (ret < 0)
+ goto err_prop;
+ }
+
+ cell.r0 = cpu_to_fdt32(part->offset);
+ cell.r1 = cpu_to_fdt32(part->size);
+add_reg:
+ ret = fdt_setprop(blob, newoff, "reg", &cell, sizeof(cell));
+ if (ret == -FDT_ERR_NOSPACE) {
+ ret = fdt_increase_size(blob, 512);
+ if (!ret)
+ goto add_reg;
+ else
+ goto err_size;
+ } else if (ret < 0)
+ goto err_prop;
+
+add_label:
+ ret = fdt_setprop_string(blob, newoff, "label", part->name);
+ if (ret == -FDT_ERR_NOSPACE) {
+ ret = fdt_increase_size(blob, 512);
+ if (!ret)
+ goto add_label;
+ else
+ goto err_size;
+ } else if (ret < 0)
+ goto err_prop;
+
+ part_num++;
+ }
+ return 0;
+err_size:
+ printf("Can't increase blob size: %s\n", fdt_strerror(ret));
+ return ret;
+err_prop:
+ printf("Can't add property: %s\n", fdt_strerror(ret));
+ return ret;
+}
+
+/*
+ * Update partitions in nor/nand nodes using info from
+ * mtdparts environment variable. The nodes to update are
+ * specified by node_info structure which contains mtd device
+ * type and compatible string: E. g. the board code in
+ * ft_board_setup() could use:
+ *
+ * struct node_info nodes[] = {
+ * { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
+ * { "cfi-flash", MTD_DEV_TYPE_NOR, },
+ * };
+ *
+ * fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ */
+void fdt_fixup_mtdparts(void *blob, void *node_info, int node_info_size)
+{
+ struct node_info *ni = node_info;
+ struct mtd_device *dev;
+ char *parts;
+ int i, idx;
+ int noff;
+
+ parts = getenv("mtdparts");
+ if (!parts)
+ return;
+
+ if (mtdparts_init() != 0)
+ return;
+
+ for (i = 0; i < node_info_size; i++) {
+ idx = 0;
+ noff = fdt_node_offset_by_compatible(blob, -1, ni[i].compat);
+ while (noff != -FDT_ERR_NOTFOUND) {
+ debug("%s: %s, mtd dev type %d\n",
+ fdt_get_name(blob, noff, 0),
+ ni[i].compat, ni[i].type);
+ dev = device_find(ni[i].type, idx++);
+ if (dev) {
+ if (fdt_node_set_part_info(blob, noff, dev))
+ return; /* return on error */
+ }
+
+ /* Jump to next flash node */
+ noff = fdt_node_offset_by_compatible(blob, noff,
+ ni[i].compat);
+ }
+ }
+}
+#endif
+
+void fdt_del_node_and_alias(void *blob, const char *alias)
+{
+ int off = fdt_path_offset(blob, alias);
+
+ if (off < 0)
+ return;
+
+ fdt_del_node(blob, off);
+
+ off = fdt_path_offset(blob, "/aliases");
+ fdt_delprop(blob, off, alias);
+}
/************************************************************************/
#ifdef CONFIG_LCD_LOGO
# include <bmp_logo.h> /* Get logo data, width and height */
-# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET)
+# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET) && (LCD_BPP != LCD_COLOR16)
# error Default Color Map overlaps with Logo Color Map
# endif
#endif
for (row=0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) {
uchar *s = str;
- uchar *d = dest;
int i;
+#if LCD_BPP == LCD_COLOR16
+ ushort *d = (ushort *)dest;
+#else
+ uchar *d = dest;
+#endif
#if LCD_BPP == LCD_MONOCHROME
uchar rest = *d & -(1 << (8-off));
bits <<= 1;
}
#elif LCD_BPP == LCD_COLOR16
- for (c=0; c<16; ++c) {
+ for (c=0; c<8; ++c) {
*d++ = (bits & 0x80) ?
lcd_color_fg : lcd_color_bg;
bits <<= 1;
cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]);
#elif defined(CONFIG_ATMEL_LCD)
cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0));
+#else
+ /*
+ * default case: generic system with no cmap (most likely 16bpp)
+ * We set cmap to the source palette, so no change is done.
+ * This avoids even more ifdef in the next stanza
+ */
+ cmap = bmp_logo_palette;
#endif
WATCHDOG_RESET();
}
}
else { /* true color mode */
+ u16 col16;
fb16 = (ushort *)(lcd_base + y * lcd_line_length + x);
for (i=0; i<BMP_LOGO_HEIGHT; ++i) {
for (j=0; j<BMP_LOGO_WIDTH; j++) {
- fb16[j] = bmp_logo_palette[(bmap[j])];
+ col16 = bmp_logo_palette[(bmap[j]-16)];
+ fb16[j] =
+ ((col16 & 0x000F) << 1) |
+ ((col16 & 0x00F0) << 3) |
+ ((col16 & 0x0F00) << 4);
}
bmap += BMP_LOGO_WIDTH;
fb16 += panel_info.vl_col;
#undef DEBUG_PARSER
-char console_buffer[CONFIG_SYS_CBSIZE]; /* console I/O buffer */
+char console_buffer[CONFIG_SYS_CBSIZE + 1]; /* console I/O buffer */
static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen);
static char erase_seq[] = "\b \b"; /* erase sequence */
#define CTL_CH(c) ((c) - 'a' + 1)
-#define MAX_CMDBUF_SIZE 256
+#define MAX_CMDBUF_SIZE CONFIG_SYS_CBSIZE
#define CTL_BACKSPACE ('\b')
#define DEL ((char)255)
unsigned hist_num = 0;
char* hist_list[HIST_MAX];
-char hist_lines[HIST_MAX][HIST_SIZE];
+char hist_lines[HIST_MAX][HIST_SIZE + 1]; /* Save room for NULL */
#define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1)
while (!tstc()) { /* while no incoming data */
if (retry_time >= 0 && get_ticks() > endtime)
return (-2); /* timed out */
+ WATCHDOG_RESET();
}
#endif
while (!tstc()) { /* while no incoming data */
if (retry_time >= 0 && get_ticks() > endtime)
return (-2); /* timed out */
+ WATCHDOG_RESET();
}
#endif
WATCHDOG_RESET(); /* Trigger watchdog, if needed */
while (!tstc()) {
extern void show_activity(int arg);
show_activity(0);
+ WATCHDOG_RESET();
}
#endif
c = getc();
block_dev_desc_t *usb_stor_get_dev(int index)
{
- return (index < USB_MAX_STOR_DEV) ? &usb_dev_desc[index] : NULL;
+ return (index < usb_max_devs) ? &usb_dev_desc[index] : NULL;
}
* get info and fill it in
*/
if (usb_stor_get_info(dev, &usb_stor[usb_max_devs],
- &usb_dev_desc[usb_max_devs]))
+ &usb_dev_desc[usb_max_devs]) == 1)
usb_max_devs++;
}
/* if storage device */
USB_STOR_PRINTF("inquiry returns %d\n", i);
if (i == 0)
break;
- } while (retry--);
+ } while (--retry);
if (!retry) {
printf("error in inquiry\n");
# Load generated board configuration
sinclude $(OBJTREE)/include/autoconf.mk
-ifdef ARCH
-sinclude $(TOPDIR)/lib_$(ARCH)/config.mk # include architecture dependend rules
-endif
-ifdef CPU
-sinclude $(TOPDIR)/cpu/$(CPU)/config.mk # include CPU specific rules
+# Some architecture config.mk files need to know what CPUDIR is set to,
+# so calculate CPUDIR before including ARCH/SOC/CPU config.mk files.
+# Check if arch/$ARCH/cpu/$CPU exists, otherwise assume arch/$ARCH/cpu contains
+# CPU-specific code.
+CPUDIR=arch/$(ARCH)/cpu/$(CPU)
+ifneq ($(SRCTREE)/$(CPUDIR),$(wildcard $(SRCTREE)/$(CPUDIR)))
+CPUDIR=arch/$(ARCH)/cpu
endif
+
+sinclude $(TOPDIR)/arch/$(ARCH)/config.mk # include architecture dependend rules
+sinclude $(TOPDIR)/$(CPUDIR)/config.mk # include CPU specific rules
+
ifdef SOC
-sinclude $(TOPDIR)/cpu/$(CPU)/$(SOC)/config.mk # include SoC specific rules
+sinclude $(TOPDIR)/$(CPUDIR)/$(SOC)/config.mk # include SoC specific rules
endif
ifdef VENDOR
BOARDDIR = $(VENDOR)/$(BOARD)
#########################################################################
# Allow boards to use custom optimize flags on a per dir/file basis
-BCURDIR := $(notdir $(CURDIR))
+BCURDIR = $(subst $(SRCTREE)/,,$(CURDIR:$(obj)%=%))
$(obj)%.s: %.S
- $(CPP) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $<
+ $(CPP) $(AFLAGS) $(AFLAGS_$(BCURDIR)/$(@F)) $(AFLAGS_$(BCURDIR)) \
+ -o $@ $<
$(obj)%.o: %.S
- $(CC) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $< -c
+ $(CC) $(AFLAGS) $(AFLAGS_$(BCURDIR)/$(@F)) $(AFLAGS_$(BCURDIR)) \
+ -o $@ $< -c
$(obj)%.o: %.c
- $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c
+ $(CC) $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
+ -o $@ $< -c
$(obj)%.i: %.c
- $(CPP) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c
+ $(CPP) $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
+ -o $@ $< -c
$(obj)%.s: %.c
- $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c -S
+ $(CC) $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
+ -o $@ $< -c -S
#########################################################################
+++ /dev/null
-/*
- * Copyright (C) 2001, Software Center, Motorola China.
- *
- * This file contains microcode for the FEC controller of the MGT5100 CPU.
- */
-
-#include <config.h>
-
-#if defined(CONFIG_MGT5100)
-
-/* sas/sccg, gas target */
-.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */
-.section smartdmaTaskTable,"aw",@progbits /* Task tables */
-.globl taskTable
-taskTable:
-.globl scEthernetRecv_Entry
-scEthernetRecv_Entry: /* Task 0 */
-.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */
-.long scEthernetRecv_TDT - taskTable + 0x000000a4
-.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */
-.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */
-.long 0x00000000
-.long 0x00000000
-.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */
-.long 0xf0000000
-.globl scEthernetXmit_Entry
-scEthernetXmit_Entry: /* Task 1 */
-.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */
-.long scEthernetXmit_TDT - taskTable + 0x000000d0
-.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */
-.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */
-.long 0x00000000
-.long 0x00000000
-.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */
-.long 0xf0000000
-
-
-.globl scEthernetRecv_TDT
-scEthernetRecv_TDT: /* Task 0 Descriptor Table */
-.long 0xc4c50000 /* 0000: LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */
-.long 0x84c5e000 /* 0004: LCD: idx1 = var9 + var11; ; idx1 += inc0 */
-.long 0x10001f08 /* 0008: DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long 0x10000380 /* 000C: DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
-.long 0x00000f88 /* 0010: DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */
-.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
-.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
-.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long 0x010c504c /* 0020: DRD2B1: var4 = EU1(); EU1(var1,var12) */
-.long 0x82180349 /* 0024: LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */
-.long 0x81c68004 /* 0028: LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */
-.long 0x70000000 /* 002C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long 0x018c504e /* 0030: DRD2B1: var6 = EU1(); EU1(var1,var14) */
-.long 0x70000000 /* 0034: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long 0x020c504f /* 0038: DRD2B1: var8 = EU1(); EU1(var1,var15) */
-.long 0x00000b88 /* 003C: DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */
-.long 0x8000d184 /* 0040: LCDEXT: idx1 = 0xf0003184; ; */
-.long 0xc6990452 /* 0044: LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */
-.long 0x81486010 /* 0048: LCD: idx3 = var2 + var16; ; idx3 += inc2 */
-.long 0x006acf88 /* 004C: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */
-.long 0x8000d184 /* 0050: LCDEXT: idx1 = 0xf0003184; ; */
-.long 0x86810492 /* 0054: LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */
-.long 0x006acf88 /* 0058: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */
-.long 0x8000d184 /* 005C: LCDEXT: idx1 = 0xf0003184; ; */
-.long 0x868184d2 /* 0060: LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */
-.long 0x000acf88 /* 0064: DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */
-.long 0xc318839b /* 0068: LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */
-.long 0x80190000 /* 006C: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
-.long 0x04008468 /* 0070: DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */
-.long 0xc4038358 /* 0074: LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */
-.long 0x81c50000 /* 0078: LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */
-.long 0x1000cb18 /* 007C: DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
-.long 0x00000f18 /* 0080: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
-.long 0xc4188364 /* 0084: LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */
-.long 0x83990000 /* 0088: LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */
-.long 0x10000c00 /* 008C: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
-.long 0x0000c800 /* 0090: DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */
-.long 0x81988000 /* 0094: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
-.long 0x10000788 /* 0098: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long 0x60000000 /* 009C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long 0x080c504c /* 00A0: DRD2B1: idx0 = EU1(); EU1(var1,var12) */
-.long 0x000001f8 /* 00A4(:0): NOP */
-
-
-.globl scEthernetXmit_TDT
-scEthernetXmit_TDT: /* Task 1 Descriptor Table */
-.long 0x80014800 /* 0000: LCDEXT: idx0 = 0xf0004800; ; */
-.long 0x85c60004 /* 0004: LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */
-.long 0x10002308 /* 0008: DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long 0x10000f88 /* 000C: DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long 0x00000380 /* 0010: DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */
-.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
-.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
-.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long 0x024c504d /* 0020: DRD2B1: var9 = EU1(); EU1(var1,var13) */
-.long 0x84980309 /* 0024: LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */
-.long 0xc0004003 /* 0028: LCDEXT: idx1 = 0x00000003; ; */
-.long 0x81c60004 /* 002C: LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */
-.long 0x70000000 /* 0030: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long 0x010c504e /* 0034: DRD2B1: var4 = EU1(); EU1(var1,var14) */
-.long 0x70000000 /* 0038: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long 0x014c504f /* 003C: DRD2B1: var5 = EU1(); EU1(var1,var15) */
-.long 0x70000000 /* 0040: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long 0x028c5050 /* 0044: DRD2B1: var10 = EU1(); EU1(var1,var16) */
-.long 0x70000000 /* 0048: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long 0x018c5051 /* 004C: DRD2B1: var6 = EU1(); EU1(var1,var17) */
-.long 0x10000b90 /* 0050: DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */
-.long 0x60000000 /* 0054: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long 0x01cc50a1 /* 0058: DRD2B1: var7 = EU1(); EU1(var2,idx1) */
-.long 0xc2988312 /* 005C: LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */
-.long 0x83490000 /* 0060: LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */
-.long 0x00001b10 /* 0064: DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */
-.long 0x8000d1a4 /* 0068: LCDEXT: idx1 = 0xf00031a4; ; */
-.long 0x8301031c /* 006C: LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */
-.long 0x008ac798 /* 0070: DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */
-.long 0x8000d1a4 /* 0074: LCDEXT: idx1 = 0xf00031a4; ; */
-.long 0xc1430000 /* 0078: LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */
-.long 0x82998312 /* 007C: LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */
-.long 0x088ac790 /* 0080: DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */
-.long 0x81988000 /* 0084: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
-.long 0x60000100 /* 0088: DRD2A: EU0=0 EU1=1 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long 0x0c4c5c4d /* 008C: DRD2B1: *idx1 = EU1(); EU1(*idx1,var13) */
-.long 0xc21883ad /* 0090: LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */
-.long 0x80190000 /* 0094: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
-.long 0x04008460 /* 0098: DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */
-.long 0xc4052305 /* 009C: LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */
-.long 0x81c98000 /* 00A0: LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */
-.long 0x1000c718 /* 00A4: DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
-.long 0x00000f18 /* 00A8: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
-.long 0xc4188000 /* 00AC: LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */
-.long 0x85190312 /* 00B0: LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */
-.long 0x10000c00 /* 00B4: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
-.long 0x1000c400 /* 00B8: DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */
-.long 0x00008860 /* 00BC: DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */
-.long 0x81988000 /* 00C0: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
-.long 0x10000788 /* 00C4: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long 0x60000000 /* 00C8: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long 0x080c504d /* 00CC: DRD2B1: idx0 = EU1(); EU1(var1,var13) */
-.long 0x000001f8 /* 00D0(:0): NOP */
-
-.align 8
-
-.globl scEthernetRecv_VarTab
-scEthernetRecv_VarTab: /* Task 0 Variable Table */
-.long 0x00000000 /* var[0] */
-.long 0x00000000 /* var[1] */
-.long 0x00000000 /* var[2] */
-.long 0x00000000 /* var[3] */
-.long 0x00000000 /* var[4] */
-.long 0x00000000 /* var[5] */
-.long 0x00000000 /* var[6] */
-.long 0x00000000 /* var[7] */
-.long 0x00000000 /* var[8] */
-.long 0xf0004800 /* var[9] */
-.long 0x00000008 /* var[10] */
-.long 0x0000000c /* var[11] */
-.long 0x80000000 /* var[12] */
-.long 0x00000000 /* var[13] */
-.long 0x10000000 /* var[14] */
-.long 0x20000000 /* var[15] */
-.long 0x000005e4 /* var[16] */
-.long 0x0000000e /* var[17] */
-.long 0x000005e0 /* var[18] */
-.long 0x00000004 /* var[19] */
-.long 0x00000000 /* var[20] */
-.long 0x00000000 /* var[21] */
-.long 0x00000000 /* var[22] */
-.long 0x00000000 /* var[23] */
-.long 0x00000000 /* inc[0] */
-.long 0x60000000 /* inc[1] */
-.long 0x20000001 /* inc[2] */
-.long 0x80000000 /* inc[3] */
-.long 0x40000000 /* inc[4] */
-.long 0x00000000 /* inc[5] */
-.long 0x00000000 /* inc[6] */
-.long 0x00000000 /* inc[7] */
-
-.align 8
-
-.globl scEthernetXmit_VarTab
-scEthernetXmit_VarTab: /* Task 1 Variable Table */
-.long 0x00000000 /* var[0] */
-.long 0x00000000 /* var[1] */
-.long 0x00000000 /* var[2] */
-.long 0x00000000 /* var[3] */
-.long 0x00000000 /* var[4] */
-.long 0x00000000 /* var[5] */
-.long 0x00000000 /* var[6] */
-.long 0x00000000 /* var[7] */
-.long 0x00000000 /* var[8] */
-.long 0x00000000 /* var[9] */
-.long 0x00000000 /* var[10] */
-.long 0xf0004800 /* var[11] */
-.long 0x00000000 /* var[12] */
-.long 0x80000000 /* var[13] */
-.long 0x10000000 /* var[14] */
-.long 0x08000000 /* var[15] */
-.long 0x20000000 /* var[16] */
-.long 0x0000ffff /* var[17] */
-.long 0xffffffff /* var[18] */
-.long 0x00000008 /* var[19] */
-.long 0x00000000 /* var[20] */
-.long 0x00000000 /* var[21] */
-.long 0x00000000 /* var[22] */
-.long 0x00000000 /* var[23] */
-.long 0x00000000 /* inc[0] */
-.long 0x60000000 /* inc[1] */
-.long 0x40000000 /* inc[2] */
-.long 0x4000ffff /* inc[3] */
-.long 0xe0000001 /* inc[4] */
-.long 0x80000000 /* inc[5] */
-.long 0x00000000 /* inc[6] */
-.long 0x00000000 /* inc[7] */
-
-.align 8
-
-.globl scEthernetRecv_FDT
-scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x05800000 /* and(), EU# 1 */
-.long 0x05400000 /* andn(), EU# 1 */
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-
-.align 8
-
-.globl scEthernetXmit_FDT
-scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x05800000 /* and(), EU# 1 */
-.long 0x05400000 /* andn(), EU# 1 */
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-.long 0x00000000
-
-
-.align 8
-.globl scEthernetRecv_CSave
-scEthernetRecv_CSave: /* Task 0 context save space */
-.space 256, 0x0
-
-
-.align 8
-.globl scEthernetXmit_CSave
-scEthernetXmit_CSave: /* Task 1 context save space */
-.space 256, 0x0
-
-#endif /* CONFIG_MGT5100 */
However, to avoid duplicating code through all processor files, a generic core
for ARM Integrator CMs has been added
- cpu/arm_intcm
+ arch/arm/cpu/arm_intcm
Otherwise. for example, the standard CM reset via the CM control register would
need placing in each CM processor file......
[By Steven Scholz <steven.scholz@imc-berlin.de>, 16 Aug 2004]
Since the cpu/ directory gets clobbered with peripheral driver code I
-started cleaning up cpu/arm920t.
+started cleaning up arch/arm/cpu/arm920t.
I introduced the concept of Soc (system on a chip) into the ./cpu
directory. That means that code that is cpu (i.e. core) specific
resides in
- cpu/$(CPU)/
+ $(CPUDIR)/
and code that is specific to some SoC (i.e. vendor specific
peripherals around the core) is moved into
- cpu/$(CPU)/$(SOC)/
+ $(CPUDIR)/$(SOC)/
-Thus a library/archive "cpu/$(CPU)/$(SOC)/lib$(SOC).a" will be build
+Thus a library/archive "$(CPUDIR)/$(SOC)/lib$(SOC).a" will be build
and linked. Examples will be
- cpu/arm920t/imx/
- cpu/arm920t/s3c24x0
+ arch/arm/cpu/arm920t/imx/
+ arch/arm/cpu/arm920t/s3c24x0
One can select an SoC by passing the name of it to ./mkconfig just
like
blue_LED_on
blue_LED_off
-These are weakly defined in lib_arm/board.c to noops. Where applicable, define
+These are weakly defined in arch/arm/lib/board.c to noops. Where applicable, define
these functions in the board specific source.
TBD : Describe older board dependent macros similar to what is done for
added console settings from environment
- common/devices.c added ISA keyboard init
- common/main.c corrected the read of bootdelay
-- cpu/ppc4xx/405gp_pci.c excluded file from PIP405
-- cpu/ppc4xx/i2c.c added 16bit read write I2C support
+- arch/ppc/cpu/ppc4xx/405gp_pci.c excluded file from PIP405
+- arch/ppc/cpu/ppc4xx/i2c.c added 16bit read write I2C support
added page write
-- cpu/ppc4xx/speed.c added get_PCI_freq
-- cpu/ppc4xx/start.S added CONFIG_IDENT_STRING
+- arch/ppc/cpu/ppc4xx/speed.c added get_PCI_freq
+- arch/ppc/cpu/ppc4xx/start.S added CONFIG_IDENT_STRING
- disk/Makefile added part_iso for CD support
- disk/part.c changed to work with block device description
added ISO CD support
"U_BOOT_VERSION __TIME__ DATE___ " String, to allows to identify intermidiate
and custom versions.
Changed files:
-- cpu/ppc4xx/start.s
+- arch/ppc/cpu/ppc4xx/start.s
Firmware Image:
---------------
Correct PCI Frequency for PPC405:
---------------------------------
-Added function (in cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU.
+Added function (in arch/ppc/cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU.
The PCI Frequency will now be set correct in the board description in common/board.c.
(was set to the busfreq before).
Changed files:
-- cpu/ppc4xx/speed.c
+- arch/ppc/cpu/ppc4xx/speed.c
- common/board.c
I2C Stuff:
Added 16bit read/write support for I2C (PPC405), and page write to
I2C EEPROM if defined CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE.
Changed files:
-- cpu/ppc4xx/i2c.c
+- arch/ppc/cpu/ppc4xx/i2c.c
- common/cmd_i2c.c
Environment / Console:
reconfiguration of the physical interface chip.
The test routines for the SCC ethernet tests will be located in
-cpu/mpc8xx/scc.c.
+arch/ppc/cpu/mpc8xx/scc.c.
2.2.3.2. UART tests (SMC/SCC)
test will be executed manually.
The test routine for the SMC/SCC UART tests will be located in
-cpu/mpc8xx/serial.c.
+arch/ppc/cpu/mpc8xx/serial.c.
2.2.3.3. USB test
board/RPXLITE/RPXLITE.c /* DRAM-related routines */
board/RPXLITE/flash.c /* flash-related routines */
board/RPXLITE/config.mk /* set text base address */
- cpu/mpc8xx/serial.c /* board specific register setting */
+ arch/ppc/cpu/mpc8xx/serial.c /* board specific register setting */
include/config_RPXLITE.h /* board specific registers */
See 'reg_config.txt' for register values in detail.
MAKEALL - TQM8260 entry added
Makefile - TQM8260_config entry added
-cpu/mpc8260/Makefile - soft_i2c.o module added
-cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious
+arch/ppc/cpu/mpc8260/Makefile - soft_i2c.o module added
+arch/ppc/cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious
bug fixed (fcr -> scr)
-cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added
+arch/ppc/cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added
include/flash.h - added definitions for the AM29LV640D Flash chip
board/tqm8260/flash.c - flash driver (for AM29LV640D)
board/tqm8260/ppcboot.lds - linker script
board/tqm8260/tqm8260.c - ioport and memory initialization
-cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver
+arch/ppc/cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver
include/config_TQM8260.h - main configuration file
- include/asm-ppc/global_data.h added global variables - inp_clk, pci_clk,
vco_clk, pev_clk, flb_clk, and bExtUart
-- lib_ppc/board.c added CONFIG_MPC8220 support
+- arch/ppc/lib/board.c added CONFIG_MPC8220 support
- net/eth.c added FEC support for MPC8220
- board/alaska/config.mk config make
- board/alaska/u-boot.lds Linker description
-- cpu/mpc8220/dma.h multi-channel dma header file
-- cpu/mpc8220/dramSetup.h dram setup header file
-- cpu/mpc8220/fec.h MPC8220 FEC header file
-- cpu/mpc8220/cpu.c cpu specific code
-- cpu/mpc8220/cpu_init.c Flexbus ChipSelect and Mux pins setup
-- cpu/mpc8220/dramSetup.c MPC8220 DDR SDRAM setup
-- cpu/mpc8220/fec.c MPC8220 FEC driver
-- cpu/mpc8220/i2c.c MPC8220 I2C driver
-- cpu/mpc8220/interrupts.c interrupt support (not enable)
-- cpu/mpc8220/loadtask.c load dma
-- cpu/mpc8220/speed.c system, pci, flexbus, pev, and cpu clock
-- cpu/mpc8220/traps.c exception
-- cpu/mpc8220/uart.c MPC8220 UART driver
-- cpu/mpc8220/Makefile Makefile
-- cpu/mpc8220/config.mk config make
-- cpu/mpc8220/fec_dma_task.S MPC8220 FEC multi-channel dma program
-- cpu/mpc8220/io.S io functions
-- cpu/mpc8220/start.S start up
+- arch/ppc/cpu/mpc8220/dma.h multi-channel dma header file
+- arch/ppc/cpu/mpc8220/dramSetup.h dram setup header file
+- arch/ppc/cpu/mpc8220/fec.h MPC8220 FEC header file
+- arch/ppc/cpu/mpc8220/cpu.c cpu specific code
+- arch/ppc/cpu/mpc8220/cpu_init.c Flexbus ChipSelect and Mux pins setup
+- arch/ppc/cpu/mpc8220/dramSetup.c MPC8220 DDR SDRAM setup
+- arch/ppc/cpu/mpc8220/fec.c MPC8220 FEC driver
+- arch/ppc/cpu/mpc8220/i2c.c MPC8220 I2C driver
+- arch/ppc/cpu/mpc8220/interrupts.c interrupt support (not enable)
+- arch/ppc/cpu/mpc8220/loadtask.c load dma
+- arch/ppc/cpu/mpc8220/speed.c system, pci, flexbus, pev, and cpu clock
+- arch/ppc/cpu/mpc8220/traps.c exception
+- arch/ppc/cpu/mpc8220/uart.c MPC8220 UART driver
+- arch/ppc/cpu/mpc8220/Makefile Makefile
+- arch/ppc/cpu/mpc8220/config.mk config make
+- arch/ppc/cpu/mpc8220/fec_dma_task.S MPC8220 FEC multi-channel dma program
+- arch/ppc/cpu/mpc8220/io.S io functions
+- arch/ppc/cpu/mpc8220/start.S start up
- include/mpc8220.h
./common/board.c
Added call to initialize debugger on startup.
-./cpu/ppc4xx/Makefile
+./arch/ppc/cpu/ppc4xx/Makefile
Added bedbug_405.c to the Makefile.
-./cpu/ppc4xx/start.S
+./arch/ppc/cpu/ppc4xx/start.S
Added code to handle the debug exception (0x2000) on the 405.
Also added code to handle critical exceptions since the debug
is treated as critical on the 405.
-./cpu/ppc4xx/traps.c
+./arch/ppc/cpu/ppc4xx/traps.c
Added more detailed output for the program exception to tell
if it is an illegal instruction, privileged instruction or
a trap. Also added debug trap handler.
hardware breakpoints and stepping through code. These
routines are common to all PowerPC processors.
-./cpu/ppc4xx/bedbug_405.c
+./arch/ppc/cpu/ppc4xx/bedbug_405.c
AMCC PPC405 specific debugger routines.
common/cmd_bedbug.c
Added call to initialize 860 debugger.
- cpu/mpc8xx/Makefile
+ arch/ppc/cpu/mpc8xx/Makefile
Added new file "bedbug_860.c" to the makefile
- cpu/mpc8xx/start.S
+ arch/ppc/cpu/mpc8xx/start.S
Added handler for InstructionBreakpoint (0xfd00)
- cpu/mpc8xx/traps.c
+ arch/ppc/cpu/mpc8xx/traps.c
Added new routine DebugException()
New Files:
- cpu/mpc8xx/bedbug_860.c
+ arch/ppc/cpu/mpc8xx/bedbug_860.c
CPU-specific routines for 860 debug registers.
purpose of passing this information to an OS kernel we are about
to boot
+Correct flow of setting up the MAC address (summarized):
+
+1. Read from hardware in initialize() function
+2. Read from environment in net/eth.c after initialize()
+3. Give priority to the value in the environment if a conflict
+4. Program hardware in the device's init() function.
+
+If somebody wants to subvert the design philosophy, this can be done
+in the board-specific board_eth_init() function by calling eth_init()
+after all the NICs have been registered.
+
-------
Usage
-------
- board/freescale/m52277evb/config.mk config make
- board/freescale/m52277evb/u-boot.lds Linker description
-- cpu/mcf5227x/cpu.c cpu specific code
-- cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
-- cpu/mcf5227x/interrupts.c cpu specific interrupt support
-- cpu/mcf5227x/speed.c system, flexbus, and cpu clock
-- cpu/mcf5227x/Makefile Makefile
-- cpu/mcf5227x/config.mk config make
-- cpu/mcf5227x/start.S start up assembly code
+- arch/m68k/cpu/mcf5227x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
+- arch/m68k/cpu/mcf5227x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf5227x/speed.c system, flexbus, and cpu clock
+- arch/m68k/cpu/mcf5227x/Makefile Makefile
+- arch/m68k/cpu/mcf5227x/config.mk config make
+- arch/m68k/cpu/mcf5227x/start.S start up assembly code
- doc/README.m52277evb This readme file
- include/configs/M52277EVB.h Board specific configuration file
-- lib_m68k/board.c board init function
-- lib_m68k/cache.c
-- lib_m68k/interrupts Coldfire common interrupt functions
-- lib_m68k/m68k_linux.c
-- lib_m68k/time.c Timer functions (Dma timer and PIT)
-- lib_m68k/traps.c Exception init code
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c Exception init code
1 MCF52277 specific Options/Settings
====================================
- board/freescale/m53017evb/config.mk config make
- board/freescale/m53017evb/u-boot.lds Linker description
-- cpu/mcf532x/cpu.c cpu specific code
-- cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
-- cpu/mcf532x/interrupts.c cpu specific interrupt support
-- cpu/mcf532x/speed.c system, flexbus, and cpu clock
-- cpu/mcf532x/Makefile Makefile
-- cpu/mcf532x/config.mk config make
-- cpu/mcf532x/start.S start up assembly code
+- arch/m68k/cpu/mcf532x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
+- arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf532x/speed.c system, flexbus, and cpu clock
+- arch/m68k/cpu/mcf532x/Makefile Makefile
+- arch/m68k/cpu/mcf532x/config.mk config make
+- arch/m68k/cpu/mcf532x/start.S start up assembly code
- doc/README.m53017evb This readme file
- include/configs/M53017EVB.h Board specific configuration file
-- lib_m68k/board.c board init function
-- lib_m68k/cache.c
-- lib_m68k/interrupts Coldfire common interrupt functions
-- lib_m68k/m68k_linux.c
-- lib_m68k/time.c Timer functions (Dma timer and PIT)
-- lib_m68k/traps.c Exception init code
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c Exception init code
1 MCF5301x specific Options/Settings
====================================
- board/freescale/m5373evb/config.mk config make
- board/freescale/m5373evb/u-boot.lds Linker description
-- cpu/mcf532x/cpu.c cpu specific code
-- cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
-- cpu/mcf532x/interrupts.c cpu specific interrupt support
-- cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock
-- cpu/mcf532x/Makefile Makefile
-- cpu/mcf532x/config.mk config make
-- cpu/mcf532x/start.S start up assembly code
+- arch/m68k/cpu/mcf532x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
+- arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf532x/Makefile Makefile
+- arch/m68k/cpu/mcf532x/config.mk config make
+- arch/m68k/cpu/mcf532x/start.S start up assembly code
- doc/README.m5373evb This readme file
- include/configs/M5373EVB.h Board specific configuration file
-- lib_m68k/board.c board init function
-- lib_m68k/cache.c
-- lib_m68k/interrupts Coldfire common interrupt functions
-- lib_m68k/m68k_linux.c
-- lib_m68k/time.c Timer functions (Dma timer and PIT)
-- lib_m68k/traps.c Exception init code
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c Exception init code
1 MCF5373 specific Options/Settings
====================================
- common/cmd_bdinfo.c Clock frequencies output
- common/cmd_mii.c mii support
-- cpu/mcf5445x/cpu.c cpu specific code
-- cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
-- cpu/mcf5445x/interrupts.c cpu specific interrupt support
-- cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock
-- cpu/mcf5445x/Makefile Makefile
-- cpu/mcf5445x/config.mk config make
-- cpu/mcf5445x/start.S start up assembly code
+- arch/m68k/cpu/mcf5445x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
+- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf5445x/Makefile Makefile
+- arch/m68k/cpu/mcf5445x/config.mk config make
+- arch/m68k/cpu/mcf5445x/start.S start up assembly code
- doc/README.m54455evb This readme file
- include/configs/M54455EVB.h Board specific configuration file
-- lib_m68k/board.c board init function
-- lib_m68k/cache.c
-- lib_m68k/interrupts Coldfire common interrupt functions
-- lib_m68k/m68k_linux.c
-- lib_m68k/time.c Timer functions (Dma timer and PIT)
-- lib_m68k/traps.c Exception init code
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c Exception init code
- rtc/mcfrtc.c Realtime clock Driver
- board/freescale/m547xevb/config.mk config make
- board/freescale/m547xevb/u-boot.lds Linker description
-- cpu/mcf547x_8x/cpu.c cpu specific code
-- cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
-- cpu/mcf547x_8x/interrupts.c cpu specific interrupt support
-- cpu/mcf547x_8x/slicetimer.c Timer support
-- cpu/mcf547x_8x/speed.c system, pci, flexbus, and cpu clock
-- cpu/mcf547x_8x/Makefile Makefile
-- cpu/mcf547x_8x/config.mk config make
-- cpu/mcf547x_8x/start.S start up assembly code
+- arch/m68k/cpu/mcf547x_8x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
+- arch/m68k/cpu/mcf547x_8x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf547x_8x/slicetimer.c Timer support
+- arch/m68k/cpu/mcf547x_8x/speed.c system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf547x_8x/Makefile Makefile
+- arch/m68k/cpu/mcf547x_8x/config.mk config make
+- arch/m68k/cpu/mcf547x_8x/start.S start up assembly code
- doc/README.m5475evb This readme file
- include/configs/M5475EVB.h Board specific configuration file
-- lib_m68k/board.c board init function
-- lib_m68k/cache.c
-- lib_m68k/interrupts Coldfire common interrupt functions
-- lib_m68k/m68k_linux.c
-- lib_m68k/traps.c Exception init code
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/traps.c Exception init code
1 MCF547x specific Options/Settings
====================================
2.1 Motorola Coldfire MCF5272
-----------------------------
-CPU specific code is located in: cpu/mcf52x2
+CPU specific code is located in: arch/m68k/cpu/mcf52x2
2.1 Motorola Coldfire MCF5282
-----------------------------
-CPU specific code is located in: cpu/mcf52x2
+CPU specific code is located in: arch/m68k/cpu/mcf52x2
The MCF5282 Port no longer needs a preloader and can place in external or
internal FLASH.
+++ /dev/null
-Xilinx ML300 platform
-=====================
-
-0. Introduction
----------------
-
-The Xilinx ML300 board is based on the Virtex-II Pro FPGA with
-integrated AMCC PowerPC 405 core. The board is normally booted from
-System ACE CF. U-Boot is then run out of main memory.
-
-An FPGA is a configurable and thus very flexible device. To
-accommodate for this flexibility this port of U-Boot includes the
-required means to regenerate the drivers and configuration files if
-you decide to change the hardware design. The required steps are
-described below.
-
-
-1. Requirements
----------------
-
-To compile and run U-Boot on the Xilinx ML300 platform you need the
-following items.
-
-- A Xilinx ML300 platform (see http://www.xilinx.com/ml300)
-- EDK and ISE development tools (shipping with ML300)
-- Parallel4 cable (shipping with ML300)
-- The EDK reference design for ML300. You can get this as design #6 from
- http://www.xilinx.com/ise/embedded/edk_examples.htm
-- A BOOTP/TFTP server
-
-
-2. Quick Start
---------------
-
-To compile and run U-Boot on ML300 follow the steps below. Make sure
-to consult the documentation for U-Boot, EDK, and the EDK reference
-design for ML300 if you have any questions.
-
-1. Implement the EDK reference design for ML300. You can use any of
- the project files, for example from a xygwin shell:
- $ xps -nw system_linux.xmp
- XPS% run init_bram
-2. Configure and compile U-Boot. Change into the root directory of
- U-Boot and run:
- $ export CROSS_COMPILE=powerpc-eabi-
- $ make ml300_config
- $ make
-3. Set up the ML300, connect the Parallel4 and the serial cable. Start
- a terminal on your host computer and set the communication
- parameters to 9600,8N1,no handshake.
-4. Set up the BOOTP/TFTP server on your host machine. U-Boot is
- preconfigured to use a fixed HW MAC address of 00:0A:35:00:22:01.
-5. Download the bitstream to the ML300.
-6. Use XMD to download and run U-Boot on the ML300:
- $ xmd
- XMD% ppcconnect
- XMD% dow u-boot
- XMD% run
-
-You can now make an ACE file out of bitstream and U-Boot:
- $ xmd genace.tcl -jprog -board ml300 -hw \
- implementation/download.bit -elf u-boot -ace top.ace
-
-Put the ACE file onto the MicroDrive, for example into xilinx/myace,
-and reboot ML300.
-
-
-3. Generating a Custom BSP for U-Boot
--------------------------------------
-
-If you decide to change the EDK reference design for ML300 or if you
-build a new design from scratch either with the Base System Builder in
-XPS or all by hand you most likely will change the base addresses for
-the Uart and the Ethernet peripheral. If you do so you will have two
-options:
-
-1. Edit boards/xilinx/ml300/xparameters.h to reflect the changes you
- made to your hardware.
-2. Use the MLD technology provided by Xilinx Platform Studio to make
- the changes automatically. To do so go to the root directory of the
- EDK reference design for ML300. Copy the Linux project file and the
- Linux software configuration file:
- $ cp system_linux.xmp system_uboot.xmp
- $ cp system_linux.mss system_uboot.mss
-
- Edit system_uboot.xmp and and have it point to system_uboot.mss for
- the software configuration.
-
- Then, copy the sw_services directory in
- boards/xilinx/ml300/sw_services to the root directory of the EDK
- reference design for ML300.
- $ cp -R <uboot dir>/boards/xilinx/ml300/sw_services <edk dir>
-
- Modify system_uboot.mss. Look for the Linux library definition
- and change it to generate a BSP for U-Boot. An example, might look
- like this:
-
- BEGIN LIBRARY
- PARAMETER LIBRARY_NAME = uboot
- PARAMETER LIBRARY_VER = 1.00.a
- PARAMETER CONNECTED_PERIPHS = (opb_uart16550_0,opb_ethernet_0)
- PARAMETER TARGET_DIR = <uboot dir>
- END
-
- Now, you are ready to generate the Xilinx ML300 BSP for U-Boot:
- $ xps -nw system_uboot.xmp
- XPS% run libs
-
- If all goes well the new configuration has been copied into the
- right places within the U-Boot source tree. Recompile U-Boot and
- run it on the ML300.
-
-
-4. ToDo
--------
-
-- Add support for all other peripherals on ML300.
-- Read the MAC address out of the IIC EEPROM.
-- Store the bootargs in the IIC EEPROM.
-
-
-5. References
--------------
-
-ML300: http://www.xilinx.com/ml300
-EDK: http://www.xilinx.com/edk
-ISE: http://www.xilinx.com/ise
-Reference Design: http://www.xilinx.com/ise/embedded/edk_examples.htm
Files:
-cpu/arm720t/serial_netarm.c .. serial I/O for the cpu
+arch/arm/cpu/arm720t/serial_netarm.c .. serial I/O for the cpu
board/modnet50/lowlevel_init.S .. memory setup for ModNET50
board/modnet50/flash.c .. flash routines
u-boot-0.2.0/common/cmd_boot.c
u-boot-0.2.0/common/cmd_reginfo.c
u-boot-0.2.0/common/environment.c
-u-boot-0.2.0/cpu/mpc5xx/*
+u-boot-0.2.0/arch/ppc/cpu/mpc5xx/*
u-boot-0.2.0/include/cmd_reginfo.h
u-boot-0.2.0/include/common.h
u-boot-0.2.0/include/ppc_asm.tmpl
u-boot-0.2.0/include/status_led.h
u-boot-0.2.0/include/asm-ppc/u-boot.h
u-boot-0.2.0/include/asm-ppc/5xx_immap.h
-u-boot-0.2.0/lib_ppc/board.c
-u-boot-0.2.0/lib_ppc/cache.c
-u-boot-0.2.0/lib_ppc/time.c
+u-boot-0.2.0/arch/ppc/lib/board.c
+u-boot-0.2.0/arch/ppc/lib/cache.c
+u-boot-0.2.0/arch/ppc/lib/time.c
u-boot-0.2.0/Makefile
u-boot-0.2.0/CREDITS
u-boot-0.2.0/doc/README.mpc5xx
--- /dev/null
+Matrix Vision mvSMR
+-------------------
+
+1. Board Description
+
+ The mvSMR is a 75x130mm single image processing board used
+ in automation. Power Supply is 24VDC.
+
+2 System Components
+
+2.1 CPU
+ Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
+ 64MB DDR-I @ 133MHz.
+ 8 MByte Nor Flash on local bus.
+ 2 serial ports. Console running on ttyS0 @ 115200 8N1.
+
+2.2 PCI
+ PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core.
+
+2.3 FPGA
+ Xilinx Spartan-3 XC3S200 with PCI DMA engine.
+ Connects to Matrix Vision specific CCD/CMOS sensor interface.
+
+2.4 I2C
+ EEPROM @ 0xA0 for vendor specifics.
+ image sensor interface (slave adresses depend on sensor)
+
+3 Flash layout.
+
+ reset vector is 0x00000100, i.e. "LOWBOOT".
+
+ FF800000 u-boot
+ FF806000 u-boot script image
+ FF808000 u-boot environment
+ FF840000 FPGA raw bit file
+ FF880000 root FS
+ FFF00000 kernel
+
+4 Booting
+
+ On startup the bootscript @ FF806000 is executed. This script can be
+ exchanged easily. Default boot mode is "boot from flash", i.e. system
+ works stand-alone.
+
+ This behaviour depends on some environment variables :
+
+ "netboot" : yes ->try dhcp/bootp and boot from network.
+ A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
+ DHCP server configuration, e.g. to provide different images to
+ different devices.
+
+ During netboot the system tries to get 3 image files:
+ 1. Kernel - name + data is given during BOOTP.
+ 2. Initrd - name is stored in "initrd_name"
+ Fallback files are the flash versions.
following commands, then close the console window:
(gdb) directory common
- (gdb) directory cpu/nios
- (gdb) directory lib_nios
+ (gdb) directory arch/nios/cpu
+ (gdb) directory arch/nios/lib
(gdb) directory board/altera/dk1c20
Note that the last command is for the DK1C20 board only. If you
* setup the BIOS data area and BIOS equipment word to reflect machine config.
* Make reset work (from Linux and from the boot prompt)
* DMA, FDC, RTC, KBC initialization
-* split of part of cpu/i386/interrupt.c to cpu/i385/entry.c?
+* split of part of arch/i386/cpu/interrupt.c to cpu/i385/entry.c?
* re-entry of protected mode from real mode, should be added to realmode_switch.S
(and used by INT 10h and INT 16h handlers for console I/O during early
linux boot...)
-* missing functions in lib_i386 and cpu/i386
+* missing functions in arch/i386/lib and arch/i386/cpu
* speaker beep interface
arch = "ppc";
os = "linux";
compression = "gzip";
+ load = <00000000>;
+ entry = <00000000>;
hash@1 {
algo = "sha1";
};
arch = "ppc";
os = "linux";
compression = "gzip";
+ load = <00000000>;
+ entry = <00000000>;
hash@1 {
algo = "crc32";
};
****************************************************************************/
void *PCI_mapBIOSImage(pci_dev_t pcidev)
{
- u32 BIOSImagePhys;
+ u32 BIOSImageBus;
int BIOSImageBAR;
u8 *BIOSImage;
specific programming for different cards to solve this problem.
*/
- if ((BIOSImagePhys = PCI_findBIOSAddr(pcidev, &BIOSImageBAR)) == 0) {
+ BIOSImageBus = PCI_findBIOSAddr(pcidev, &BIOSImageBAR);
+ if (BIOSImageBus == 0) {
printf("Find bios addr error\n");
return NULL;
}
- BIOSImage = (u8 *) BIOSImagePhys;
+ BIOSImage = pci_bus_to_virt(pcidev, BIOSImageBus,
+ PCI_REGION_MEM, 0, MAP_NOCACHE);
/*Change the PCI BAR registers to map it onto the bus.*/
pci_write_config_dword(pcidev, BIOSImageBAR, 0);
- pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImagePhys | 0x1);
+ pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1);
udelay(1);
BE_init(0, 65536, VGAInfo, 0);
/*Post all the display controller BIOS'es*/
- PCI_postController(pcidev, VGAInfo);
+ if (!PCI_postController(pcidev, VGAInfo))
+ return false;
/*Cleanup and exit the emulator if requested. If the BIOS emulator
is needed after booting the card, we will not call BE_exit and
} while ((*fn->init) (cookie));
/* Load the data */
- while (bytecount < bsize) {
-
- /* Xilinx detects an error if INIT goes low (active)
- while DONE is low (inactive) */
- if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
- puts ("** CRC error during FPGA load.\n");
- return (FPGA_FAIL);
- }
- val = data [bytecount ++];
- i = 8;
- do {
- /* Deassert the clock */
- (*fn->clk) (FALSE, TRUE, cookie);
- CONFIG_FPGA_DELAY ();
- /* Write data */
- (*fn->wr) ((val & 0x80), TRUE, cookie);
- CONFIG_FPGA_DELAY ();
- /* Assert the clock */
- (*fn->clk) (TRUE, TRUE, cookie);
- CONFIG_FPGA_DELAY ();
- val <<= 1;
- i --;
- } while (i > 0);
+ if(*fn->bwr)
+ (*fn->bwr) (data, bsize, TRUE, cookie);
+ else {
+ while (bytecount < bsize) {
+
+ /* Xilinx detects an error if INIT goes low (active)
+ while DONE is low (inactive) */
+ if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
+ puts ("** CRC error during FPGA load.\n");
+ return (FPGA_FAIL);
+ }
+ val = data [bytecount ++];
+ i = 8;
+ do {
+ /* Deassert the clock */
+ (*fn->clk) (FALSE, TRUE, cookie);
+ CONFIG_FPGA_DELAY ();
+ /* Write data */
+ (*fn->wr) ((val & 0x80), TRUE, cookie);
+ CONFIG_FPGA_DELAY ();
+ /* Assert the clock */
+ (*fn->clk) (TRUE, TRUE, cookie);
+ CONFIG_FPGA_DELAY ();
+ val <<= 1;
+ i --;
+ } while (i > 0);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- if (bytecount % (bsize / 40) == 0)
- putc ('.'); /* let them know we are alive */
+ if (bytecount % (bsize / 40) == 0)
+ putc ('.'); /* let them know we are alive */
#endif
+ }
}
CONFIG_FPGA_DELAY ();
COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
+COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o
COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
#include <ppc4xx.h>
#include <4xx_i2c.h>
#include <i2c.h>
-#include <asm-ppc/io.h>
+#include <asm/io.h>
#ifdef CONFIG_HARD_I2C
void i2c_init(int speed, int slaveaddr)
{
- struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
+ struct ppc4xx_i2c *i2c;
int val, divisor;
int bus;
for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) {
I2C_SET_BUS(bus);
+ /* Set i2c pointer after calling I2C_SET_BUS() */
+ i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
+
/* Handle possible failed I2C state */
/* FIXME: put this into i2c_init_board()? */
_i2c_bus_reset();
#define PSC_BASE MPC5XXX_PSC2
#elif CONFIG_PS2SERIAL == 3
#define PSC_BASE MPC5XXX_PSC3
-#elif defined(CONFIG_MGT5100)
-#error CONFIG_PS2SERIAL must be in 1, 2 or 3
#elif CONFIG_PS2SERIAL == 4
#define PSC_BASE MPC5XXX_PSC4
#elif CONFIG_PS2SERIAL == 5
psc->command = PSC_SEL_MODE_REG_1;
/* select clock sources */
-#if defined(CONFIG_MGT5100)
- psc->psc_clock_select = 0xdd00;
- baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32;
-#elif defined(CONFIG_MPC5200)
psc->psc_clock_select = 0;
baseclk = (gd->ipb_clk + 16) / 32;
-#endif
/* switch to UART mode */
psc->sicr = 0;
/* configure parity, bit length and so on */
-#if defined(CONFIG_MGT5100)
- psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE;
-#elif defined(CONFIG_MPC5200)
psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
-#endif
psc->mode = PSC_MODE_ONE_STOP;
/* set up UART divisor */
/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#define FSL_HW_NUM_LAWS 10
#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \
defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
+ defined(CONFIG_P1012) || defined(CONFIG_P1021) || \
+ defined(CONFIG_P1013) || defined(CONFIG_P1022) || \
defined(CONFIG_P2010) || defined(CONFIG_P2020)
#define FSL_HW_NUM_LAWS 12
#elif defined(CONFIG_PPC_P4080)
/*
- * Copyright 2007, Freescale Semiconductor, Inc
+ * Copyright 2007,2010 Freescale Semiconductor, Inc
* Andy Fleming
*
* Based vaguely on the pxa mmc code:
if (wml_value > 0x10)
wml_value = 0x10;
- wml_value = 0x100000 | wml_value;
-
+ esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
esdhc_write32(®s->dsaddr, (u32)data->dest);
} else {
if (wml_value > 0x80)
printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
return TIMEOUT;
}
- wml_value = wml_value << 16 | 0x10;
+
+ esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
+ wml_value << 16);
esdhc_write32(®s->dsaddr, (u32)data->src);
}
- esdhc_write32(®s->wml, wml_value);
-
esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
/* Calculate the timeout period for data transactions */
clk = (pre_div << 8) | (div << 4);
- /* On imx the clock must be stopped before changing frequency */
- if (cfg->clk_enable)
- esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
+ esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
udelay(10000);
- clk = SYSCTL_PEREN;
- /* On imx systems the clock must be explicitely enabled */
- if (cfg->clk_enable)
- clk |= SYSCTL_CKEN;
+ clk = SYSCTL_PEREN | SYSCTL_CKEN;
esdhc_setbits32(®s->sysctl, clk);
}
return ret;
}
+static void esdhc_reset(struct fsl_esdhc *regs)
+{
+ unsigned long timeout = 100; /* wait max 100 ms */
+
+ /* reset the controller */
+ esdhc_write32(®s->sysctl, SYSCTL_RSTA);
+
+ /* hardware clears the bit when it is done */
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
+ udelay(1000);
+ if (!timeout)
+ printf("MMC/SD: Reset never completed.\n");
+}
+
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
{
struct fsl_esdhc *regs;
sprintf(mmc->name, "FSL_ESDHC");
regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ /* First reset the eSDHC controller */
+ esdhc_reset(regs);
+
mmc->priv = cfg;
mmc->send_cmd = esdhc_send_cmd;
mmc->set_ios = esdhc_set_ios;
ulong start;
#if CONFIG_SYS_HZ != 1000
- tout *= CONFIG_SYS_HZ/1000;
+ if ((ulong)CONFIG_SYS_HZ > 100000)
+ tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */
+ else
+ tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
#endif
/* Wait for command completion */
+ reset_timer();
start = get_timer (0);
while (flash_is_busy (info, sector)) {
if (get_timer (start) > tout) {
return retcode;
}
+static int use_flash_status_poll(flash_info_t *info)
+{
+#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
+ if (info->vendor == CFI_CMDSET_AMD_EXTENDED ||
+ info->vendor == CFI_CMDSET_AMD_STANDARD)
+ return 1;
+#endif
+ return 0;
+}
+
+static int flash_status_poll(flash_info_t *info, void *src, void *dst,
+ ulong tout, char *prompt)
+{
+#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
+ ulong start;
+ int ready;
+
+#if CONFIG_SYS_HZ != 1000
+ if ((ulong)CONFIG_SYS_HZ > 100000)
+ tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */
+ else
+ tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
+#endif
+
+ /* Wait for command completion */
+ reset_timer();
+ start = get_timer(0);
+ while (1) {
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ ready = flash_read8(dst) == flash_read8(src);
+ break;
+ case FLASH_CFI_16BIT:
+ ready = flash_read16(dst) == flash_read16(src);
+ break;
+ case FLASH_CFI_32BIT:
+ ready = flash_read32(dst) == flash_read32(src);
+ break;
+ case FLASH_CFI_64BIT:
+ ready = flash_read64(dst) == flash_read64(src);
+ break;
+ default:
+ ready = 0;
+ break;
+ }
+ if (ready)
+ break;
+ if (get_timer(start) > tout) {
+ printf("Flash %s timeout at address %lx data %lx\n",
+ prompt, (ulong)dst, (ulong)flash_read8(dst));
+ return ERR_TIMOUT;
+ }
+ udelay(1); /* also triggers watchdog */
+ }
+#endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */
+ return ERR_OK;
+}
+
/*-----------------------------------------------------------------------
*/
static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
if (!sect_found)
sect = find_sector (info, dest);
- return flash_full_status_check (info, sect, info->write_tout, "write");
+ if (use_flash_status_poll(info))
+ return flash_status_poll(info, &cword, dstaddr,
+ info->write_tout, "write");
+ else
+ return flash_full_status_check(info, sect,
+ info->write_tout, "write");
}
#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
}
flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
- retcode = flash_full_status_check (info, sector,
- info->buffer_write_tout,
- "buffer write");
+ if (use_flash_status_poll(info))
+ retcode = flash_status_poll(info, src - (1 << shift),
+ dst - (1 << shift),
+ info->buffer_write_tout,
+ "buffer write");
+ else
+ retcode = flash_full_status_check(info, sector,
+ info->buffer_write_tout,
+ "buffer write");
break;
default:
int rcode = 0;
int prot;
flash_sect_t sect;
+ int st;
if (info->flash_id != FLASH_MAN_CFI) {
puts ("Can't erase unknown flash type - aborted\n");
break;
}
- if (flash_full_status_check
- (info, sect, info->erase_blk_tout, "erase")) {
+ if (use_flash_status_poll(info)) {
+ cfiword_t cword = (cfiword_t)0xffffffffffffffffULL;
+ void *dest;
+ dest = flash_map(info, sect, 0);
+ st = flash_status_poll(info, &cword, dest,
+ info->erase_blk_tout, "erase");
+ flash_unmap(info, sect, 0, dest);
+ } else
+ st = flash_full_status_check(info, sect,
+ info->erase_blk_tout,
+ "erase");
+ if (st)
rcode = 1;
- } else if (flash_verbose)
+ else if (flash_verbose)
putc ('.');
}
}
#include <nand.h>
+#ifdef CONFIG_ATMEL_NAND_HWECC
+
+/* Register access macros */
+#define ecc_readl(add, reg) \
+ readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
+#define ecc_writel(add, reg, value) \
+ writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
+
+#include "atmel_nand_ecc.h" /* Hardware ECC registers */
+
+/* oob layout for large page size
+ * bad block info is on bytes 0 and 1
+ * the bytes have to be consecutives to avoid
+ * several NAND_CMD_RNDOUT during read
+ */
+static struct nand_ecclayout atmel_oobinfo_large = {
+ .eccbytes = 4,
+ .eccpos = {60, 61, 62, 63},
+ .oobfree = {
+ {2, 58}
+ },
+};
+
+/* oob layout for small page size
+ * bad block info is on bytes 4 and 5
+ * the bytes have to be consecutives to avoid
+ * several NAND_CMD_RNDOUT during read
+ */
+static struct nand_ecclayout atmel_oobinfo_small = {
+ .eccbytes = 4,
+ .eccpos = {0, 1, 2, 3},
+ .oobfree = {
+ {6, 10}
+ },
+};
+
+/*
+ * Calculate HW ECC
+ *
+ * function called after a write
+ *
+ * mtd: MTD block structure
+ * dat: raw data (unused)
+ * ecc_code: buffer for ECC
+ */
+static int atmel_nand_calculate(struct mtd_info *mtd,
+ const u_char *dat, unsigned char *ecc_code)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ unsigned int ecc_value;
+
+ /* get the first 2 ECC bytes */
+ ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
+
+ ecc_code[0] = ecc_value & 0xFF;
+ ecc_code[1] = (ecc_value >> 8) & 0xFF;
+
+ /* get the last 2 ECC bytes */
+ ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
+
+ ecc_code[2] = ecc_value & 0xFF;
+ ecc_code[3] = (ecc_value >> 8) & 0xFF;
+
+ return 0;
+}
+
+/*
+ * HW ECC read page function
+ *
+ * mtd: mtd info structure
+ * chip: nand chip info structure
+ * buf: buffer to store read data
+ */
+static int atmel_nand_read_page(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf, int page)
+{
+ int eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ uint32_t *eccpos = chip->ecc.layout->eccpos;
+ uint8_t *p = buf;
+ uint8_t *oob = chip->oob_poi;
+ uint8_t *ecc_pos;
+ int stat;
+
+ /* read the page */
+ chip->read_buf(mtd, p, eccsize);
+
+ /* move to ECC position if needed */
+ if (eccpos[0] != 0) {
+ /* This only works on large pages
+ * because the ECC controller waits for
+ * NAND_CMD_RNDOUTSTART after the
+ * NAND_CMD_RNDOUT.
+ * anyway, for small pages, the eccpos[0] == 0
+ */
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
+ mtd->writesize + eccpos[0], -1);
+ }
+
+ /* the ECC controller needs to read the ECC just after the data */
+ ecc_pos = oob + eccpos[0];
+ chip->read_buf(mtd, ecc_pos, eccbytes);
+
+ /* check if there's an error */
+ stat = chip->ecc.correct(mtd, p, oob, NULL);
+
+ if (stat < 0)
+ mtd->ecc_stats.failed++;
+ else
+ mtd->ecc_stats.corrected += stat;
+
+ /* get back to oob start (end of page) */
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
+
+ /* read the oob */
+ chip->read_buf(mtd, oob, mtd->oobsize);
+
+ return 0;
+}
+
+/*
+ * HW ECC Correction
+ *
+ * function called after a read
+ *
+ * mtd: MTD block structure
+ * dat: raw data read from the chip
+ * read_ecc: ECC from the chip (unused)
+ * isnull: unused
+ *
+ * Detect and correct a 1 bit error for a page
+ */
+static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
+ u_char *read_ecc, u_char *isnull)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ unsigned int ecc_status, ecc_parity, ecc_mode;
+ unsigned int ecc_word, ecc_bit;
+
+ /* get the status from the Status Register */
+ ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
+
+ /* if there's no error */
+ if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
+ return 0;
+
+ /* get error bit offset (4 bits) */
+ ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
+ /* get word address (12 bits) */
+ ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
+ ecc_word >>= 4;
+
+ /* if there are multiple errors */
+ if (ecc_status & ATMEL_ECC_MULERR) {
+ /* check if it is a freshly erased block
+ * (filled with 0xff) */
+ if ((ecc_bit == ATMEL_ECC_BITADDR)
+ && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
+ /* the block has just been erased, return OK */
+ return 0;
+ }
+ /* it doesn't seems to be a freshly
+ * erased block.
+ * We can't correct so many errors */
+ printk(KERN_WARNING "atmel_nand : multiple errors detected."
+ " Unable to correct.\n");
+ return -EIO;
+ }
+
+ /* if there's a single bit error : we can correct it */
+ if (ecc_status & ATMEL_ECC_ECCERR) {
+ /* there's nothing much to do here.
+ * the bit error is on the ECC itself.
+ */
+ printk(KERN_WARNING "atmel_nand : one bit error on ECC code."
+ " Nothing to correct\n");
+ return 0;
+ }
+
+ printk(KERN_WARNING "atmel_nand : one bit error on data."
+ " (word offset in the page :"
+ " 0x%x bit offset : 0x%x)\n",
+ ecc_word, ecc_bit);
+ /* correct the error */
+ if (nand_chip->options & NAND_BUSWIDTH_16) {
+ /* 16 bits words */
+ ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
+ } else {
+ /* 8 bits words */
+ dat[ecc_word] ^= (1 << ecc_bit);
+ }
+ printk(KERN_WARNING "atmel_nand : error corrected\n");
+ return 1;
+}
+
+/*
+ * Enable HW ECC : unused on most chips
+ */
+static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
+{
+}
+#endif
+
static void at91_nand_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
{
int board_nand_init(struct nand_chip *nand)
{
+#ifdef CONFIG_ATMEL_NAND_HWECC
+ static int chip_nr = 0;
+ struct mtd_info *mtd;
+#endif
+
nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CONFIG_SYS_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
nand->chip_delay = 20;
+#ifdef CONFIG_ATMEL_NAND_HWECC
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.calculate = atmel_nand_calculate;
+ nand->ecc.correct = atmel_nand_correct;
+ nand->ecc.hwctl = atmel_nand_hwctl;
+ nand->ecc.read_page = atmel_nand_read_page;
+ nand->ecc.bytes = 4;
+#endif
+
+#ifdef CONFIG_ATMEL_NAND_HWECC
+ mtd = &nand_info[chip_nr++];
+ mtd->priv = nand;
+
+ /* Detect NAND chips */
+ if (nand_scan_ident(mtd, 1)) {
+ printk(KERN_WARNING "NAND Flash not found !\n");
+ return -ENXIO;
+ }
+
+ if (nand->ecc.mode == NAND_ECC_HW) {
+ /* ECC is calculated for the whole page (1 step) */
+ nand->ecc.size = mtd->writesize;
+
+ /* set ECC page size and oob layout */
+ switch (mtd->writesize) {
+ case 512:
+ nand->ecc.layout = &atmel_oobinfo_small;
+ ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_528);
+ break;
+ case 1024:
+ nand->ecc.layout = &atmel_oobinfo_large;
+ ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_1056);
+ break;
+ case 2048:
+ nand->ecc.layout = &atmel_oobinfo_large;
+ ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_2112);
+ break;
+ case 4096:
+ nand->ecc.layout = &atmel_oobinfo_large;
+ ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_4224);
+ break;
+ default:
+ /* page size not handled by HW ECC */
+ /* switching back to soft ECC */
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->ecc.calculate = NULL;
+ nand->ecc.correct = NULL;
+ nand->ecc.hwctl = NULL;
+ nand->ecc.read_page = NULL;
+ nand->ecc.postpad = 0;
+ nand->ecc.prepad = 0;
+ nand->ecc.bytes = 0;
+ break;
+ }
+ }
+#endif
+
return 0;
}
--- /dev/null
+/*
+ * Error Corrected Code Controller (ECC) - System peripherals regsters.
+ * Based on AT91SAM9260 datasheet revision B.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef ATMEL_NAND_ECC_H
+#define ATMEL_NAND_ECC_H
+
+#define ATMEL_ECC_CR 0x00 /* Control register */
+#define ATMEL_ECC_RST (1 << 0) /* Reset parity */
+
+#define ATMEL_ECC_MR 0x04 /* Mode register */
+#define ATMEL_ECC_PAGESIZE (3 << 0) /* Page Size */
+#define ATMEL_ECC_PAGESIZE_528 (0)
+#define ATMEL_ECC_PAGESIZE_1056 (1)
+#define ATMEL_ECC_PAGESIZE_2112 (2)
+#define ATMEL_ECC_PAGESIZE_4224 (3)
+
+#define ATMEL_ECC_SR 0x08 /* Status register */
+#define ATMEL_ECC_RECERR (1 << 0) /* Recoverable Error */
+#define ATMEL_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
+#define ATMEL_ECC_MULERR (1 << 2) /* Multiple Errors */
+
+#define ATMEL_ECC_PR 0x0c /* Parity register */
+#define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */
+#define ATMEL_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
+
+#define ATMEL_ECC_NPR 0x10 /* NParity register */
+#define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */
+
+#endif
#define ECC_STATE_ERR_CORR_COMP_P 0x2
#define ECC_STATE_ERR_CORR_COMP_N 0x3
-static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
/*
* Exploit the little endianness of the ARM to do multi-byte transfers
* per device read. This can perform over twice as quickly as individual
/* copy aligned data */
while (len >= 4) {
- *(u32 *)buf = readl(nand);
+ *(u32 *)buf = __raw_readl(nand);
buf += 4;
len -= 4;
}
/* copy aligned data */
while (len >= 4) {
- writel(*(u32 *)buf, nand);
+ __raw_writel(*(u32 *)buf, nand);
buf += 4;
len -= 4;
}
}
}
-static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
- if ( ctrl & NAND_CLE )
+ if (ctrl & NAND_CLE)
IO_ADDR_W |= MASK_CLE;
- if ( ctrl & NAND_ALE )
+ if (ctrl & NAND_ALE)
IO_ADDR_W |= MASK_ALE;
this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
}
{
u_int32_t val;
- (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2]));
+ (void)__raw_readl(&(davinci_emif_regs->nandfecc[
+ CONFIG_SYS_NAND_CS - 2]));
- val = readl(&emif_regs->NANDFCR);
+ val = __raw_readl(&davinci_emif_regs->nandfcr);
val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
- writel(val, &emif_regs->NANDFCR);
+ __raw_writel(val, &davinci_emif_regs->nandfcr);
}
static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
{
u_int32_t ecc = 0;
- ecc = readl(&(emif_regs->NANDFECC[region - 1]));
+ ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));
- return(ecc);
+ return ecc;
}
-static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
+static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+ u_char *ecc_code)
{
u_int32_t tmp;
const int region = 1;
return 0;
}
-static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
+static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
+ u_char *read_ecc, u_char *calc_ecc)
{
struct nand_chip *this = mtd->priv;
u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
return -1;
}
}
- return(0);
+ return 0;
}
#endif /* CONFIG_SYS_NAND_HW_ECC */
* Start a new ECC calculation for reading or writing 512 bytes
* of data.
*/
- val = readl(&emif_regs->NANDFCR);
+ val = __raw_readl(&davinci_emif_regs->nandfcr);
val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_4BIT_ECC_START;
- writel(val, &emif_regs->NANDFCR);
+ __raw_writel(val, &davinci_emif_regs->nandfcr);
break;
case NAND_ECC_READSYN:
- val = emif_regs->NAND4BITECC1;
+ val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
break;
default:
break;
static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
{
- ecc[0] = emif_regs->NAND4BITECC1 & NAND_4BITECC_MASK;
- ecc[1] = emif_regs->NAND4BITECC2 & NAND_4BITECC_MASK;
- ecc[2] = emif_regs->NAND4BITECC3 & NAND_4BITECC_MASK;
- ecc[3] = emif_regs->NAND4BITECC4 & NAND_4BITECC_MASK;
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
+ NAND_4BITECC_MASK;
+ }
return 0;
}
*/
/*Take 2 bits from 8th byte and 8 bits from 9th byte */
- writel(((ecc16[4]) >> 6) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
+ __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
+ &davinci_emif_regs->nand4biteccload);
/* Take 4 bits from 7th byte and 6 bits from 8th byte */
- writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
- &emif_regs->NAND4BITECCLOAD);
+ __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
+ &davinci_emif_regs->nand4biteccload);
/* Take 6 bits from 6th byte and 4 bits from 7th byte */
- writel((ecc16[3] >> 2) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
+ __raw_writel((ecc16[3] >> 2) & 0x3FF,
+ &davinci_emif_regs->nand4biteccload);
/* Take 8 bits from 5th byte and 2 bits from 6th byte */
- writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
- &emif_regs->NAND4BITECCLOAD);
+ __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
+ &davinci_emif_regs->nand4biteccload);
/*Take 2 bits from 3rd byte and 8 bits from 4th byte */
- writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
- &emif_regs->NAND4BITECCLOAD);
+ __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
+ &davinci_emif_regs->nand4biteccload);
/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
- writel(((ecc16[1]) >> 4) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
+ __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
+ &davinci_emif_regs->nand4biteccload);
/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
- writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
- &emif_regs->NAND4BITECCLOAD);
+ __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
+ &davinci_emif_regs->nand4biteccload);
/* Take 10 bits from 0th and 1st bytes */
- writel((ecc16[0]) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
+ __raw_writel((ecc16[0]) & 0x3FF,
+ &davinci_emif_regs->nand4biteccload);
/*
* Perform a dummy read to the EMIF Revision Code and Status register.
* writing the ECC values in previous step.
*/
- val = emif_regs->NANDFSR;
+ val = __raw_readl(&davinci_emif_regs->nandfsr);
/*
* Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
* Clear any previous address calculation by doing a dummy read of an
* error address register.
*/
- val = emif_regs->NANDERRADD1;
+ val = __raw_readl(&davinci_emif_regs->nanderradd1);
/*
* Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
* register to 1.
*/
- emif_regs->NANDFCR |= 1 << 13;
+ __raw_writel(1 << 13, &davinci_emif_regs->nandfcr);
/*
* Wait for the corr_state field (bits 8 to 11)in the
*/
i = NAND_TIMEOUT;
do {
- val = emif_regs->NANDFSR;
+ val = __raw_readl(&davinci_emif_regs->nandfsr);
val &= 0xc00;
i--;
} while ((i > 0) && val);
- iserror = emif_regs->NANDFSR;
+ iserror = __raw_readl(&davinci_emif_regs->nandfsr);
iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
iserror = iserror >> 8;
*/
if (iserror == ECC_STATE_NO_ERR) {
- val = emif_regs->NANDERRVAL1;
+ val = __raw_readl(&davinci_emif_regs->nanderrval1);
return 0;
} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
- val = emif_regs->NANDERRVAL1;
+ val = __raw_readl(&davinci_emif_regs->nanderrval1);
return -1;
}
- numerrors = ((emif_regs->NANDFSR >> 16) & 0x3) + 1;
+ numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
+ & 0x3) + 1;
/* Read the error address, error value and correct */
for (i = 0; i < numerrors; i++) {
if (i > 1) {
erroraddress =
- ((emif_regs->NANDERRADD2 >>
+ ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
(16 * (i & 1))) & 0x3FF);
erroraddress = ((512 + 7) - erroraddress);
errorvalue =
- ((emif_regs->NANDERRVAL2 >>
+ ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
(16 * (i & 1))) & 0xFF);
} else {
erroraddress =
- ((emif_regs->NANDERRADD1 >>
+ ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
(16 * (i & 1))) & 0x3FF);
erroraddress = ((512 + 7) - erroraddress);
errorvalue =
- ((emif_regs->NANDERRVAL1 >>
+ ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
(16 * (i & 1))) & 0xFF);
}
/* xor the corrupt data with error value */
static int nand_davinci_dev_ready(struct mtd_info *mtd)
{
- return emif_regs->NANDFSR & 0x1;
+ return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
}
static void nand_flash_init(void)
* *
*------------------------------------------------------------------*/
acfg1 = 0
- | (0 << 31 ) /* selectStrobe */
- | (0 << 30 ) /* extWait */
- | (1 << 26 ) /* writeSetup 10 ns */
- | (3 << 20 ) /* writeStrobe 40 ns */
- | (1 << 17 ) /* writeHold 10 ns */
- | (1 << 13 ) /* readSetup 10 ns */
- | (5 << 7 ) /* readStrobe 60 ns */
- | (1 << 4 ) /* readHold 10 ns */
- | (3 << 2 ) /* turnAround ?? ns */
- | (0 << 0 ) /* asyncSize 8-bit bus */
+ | (0 << 31) /* selectStrobe */
+ | (0 << 30) /* extWait */
+ | (1 << 26) /* writeSetup 10 ns */
+ | (3 << 20) /* writeStrobe 40 ns */
+ | (1 << 17) /* writeHold 10 ns */
+ | (1 << 13) /* readSetup 10 ns */
+ | (5 << 7) /* readStrobe 60 ns */
+ | (1 << 4) /* readHold 10 ns */
+ | (3 << 2) /* turnAround ?? ns */
+ | (0 << 0) /* asyncSize 8-bit bus */
;
- emif_regs->AB1CR = acfg1; /* CS2 */
+ __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
- emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */
+ /* NAND flash on CS2 */
+ __raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
#endif
}
slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000,
CONFIG_DEFAULT_SPI_MODE);
+ if(!slave)
+ return 0;
+
spi_claim_bus(slave);
/* command */
slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000,
CONFIG_DEFAULT_SPI_MODE);
+ if (!slave)
+ return 0;
+
spi_claim_bus(slave);
buf[0] = SPI_EEPROM_WREN;
if (fec_get_hwaddr(edev, ethaddr) == 0) {
printf("got MAC address from EEPROM: %pM\n", ethaddr);
memcpy(edev->enetaddr, ethaddr, 6);
- fec_set_hwaddr(edev);
}
return 0;
*/
fec->eth->xmit_fsm = 0x03000000;
-#if defined(CONFIG_MPC5200)
/*
- * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
+ * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't
* work w/ the current receive task.
*/
sdma->PtdCntrl |= 0x00000001;
-#endif
/*
* Set priority of different initiators
/********************************************************************/
static void mpc5xxx_fec_halt(struct eth_device *dev)
{
-#if defined(CONFIG_MPC5200)
struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
-#endif
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
int counter = 0xffff;
SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
-#if defined(CONFIG_MPC5200)
/*
- * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
+ * Turn on COMM bus prefetch in the MPC5200 BestComm after we're
* done. It doesn't work w/ the current receive task.
*/
sdma->PtdCntrl &= ~0x00000001;
-#endif
/*
* Disable the Ethernet Controller
/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
struct pci_controller *hose)
{
int off = fdt_path_offset(blob, pci_alias);
+ u32 bus_range[2];
- if (off >= 0) {
- u32 bus_range[2];
+ if (off < 0)
+ return;
+ /* We assume a cfg_addr not being set means we didn't setup the controller */
+ if ((hose == NULL) || (hose->cfg_addr == NULL)) {
+ fdt_del_node_and_alias(blob, pci_alias);
+ } else {
bus_range[0] = 0;
bus_range[1] = hose->last_busno - hose->first_busno;
fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
* (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*
- * u-boot/cpu/sh4/pci-sh4.c
+ * u-boot/arch/sh/cpu/sh4/pci-sh4.c
*
* See file CREDITS for list of people who contributed to this
* project.
/*--------------------------------------------------------------------+
* Fixed PHY (PHY-less) support for Ethernet Ports.
*
- * Copied from cpu/ppc4xx/4xx_enet.c
+ * Copied from arch/ppc/cpu/ppc4xx/4xx_enet.c
*--------------------------------------------------------------------*/
/*
LIB := $(obj)libserial.a
+COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o
+COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
COBJS-$(CONFIG_AT91RM9200_USART) += at91rm9200_usart.o
COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o
COBJS-$(CONFIG_MCFUART) += mcfuart.o
COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o
+COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
COBJS-$(CONFIG_SYS_NS16550) += ns16550.o
COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o
COBJS-$(CONFIG_S3C64XX) += s3c64xx.o
--- /dev/null
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <nios2-io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*------------------------------------------------------------------
+ * JTAG acts as the serial port
+ *-----------------------------------------------------------------*/
+static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE;
+
+void serial_setbrg( void ){ return; }
+int serial_init( void ) { return(0);}
+
+void serial_putc (char c)
+{
+ while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0)
+ WATCHDOG_RESET ();
+ writel ((unsigned char)c, &jtag->data);
+}
+
+void serial_puts (const char *s)
+{
+ while (*s != 0)
+ serial_putc (*s++);
+}
+
+int serial_tstc (void)
+{
+ return ( readl (&jtag->control) & NIOS_JTAG_RRDY);
+}
+
+int serial_getc (void)
+{
+ int c;
+ unsigned val;
+
+ while (1) {
+ WATCHDOG_RESET ();
+ val = readl (&jtag->data);
+ if (val & NIOS_JTAG_RVALID)
+ break;
+ }
+ c = val & 0x0ff;
+ return (c);
+}
--- /dev/null
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <nios2-io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*------------------------------------------------------------------
+ * UART the serial port
+ *-----------------------------------------------------------------*/
+
+static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE;
+
+#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
+
+/* Everything's already setup for fixed-baud PTF
+ * assignment
+ */
+void serial_setbrg (void){ return; }
+int serial_init (void) { return (0);}
+
+#else
+
+void serial_setbrg (void)
+{
+ unsigned div;
+
+ div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
+ writel (div, &uart->divisor);
+ return;
+}
+
+int serial_init (void)
+{
+ serial_setbrg ();
+ return (0);
+}
+
+#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
+
+/*-----------------------------------------------------------------------
+ * UART CONSOLE
+ *---------------------------------------------------------------------*/
+void serial_putc (char c)
+{
+ if (c == '\n')
+ serial_putc ('\r');
+ while ((readl (&uart->status) & NIOS_UART_TRDY) == 0)
+ WATCHDOG_RESET ();
+ writel ((unsigned char)c, &uart->txdata);
+}
+
+void serial_puts (const char *s)
+{
+ while (*s != 0) {
+ serial_putc (*s++);
+ }
+}
+
+int serial_tstc (void)
+{
+ return (readl (&uart->status) & NIOS_UART_RRDY);
+}
+
+int serial_getc (void)
+{
+ while (serial_tstc () == 0)
+ WATCHDOG_RESET ();
+ return (readl (&uart->rxdata) & 0x00ff );
+}
DECLARE_GLOBAL_DATA_PTR;
-extern void uart_port_conf(void);
+extern void uart_port_conf(int port);
int serial_init(void)
{
uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
- uart_port_conf();
+ uart_port_conf(CONFIG_SYS_UART_PORT);
/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
uart->ucr = UART_UCR_RESET_RX;
/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * YANU Support:
* Copyright 2010, Renato Andreola <renato.andreola@imagos.it>
*
* See file CREDITS for list of people who contributed to this
* MA 02111-1307 USA
*/
-
#include <common.h>
#include <watchdog.h>
#include <asm/io.h>
-#include <nios2-io.h>
#include <nios2-yanu.h>
DECLARE_GLOBAL_DATA_PTR;
-/*------------------------------------------------------------------
- * JTAG acts as the serial port
- *-----------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
-
-static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE;
-
-void serial_setbrg( void ){ return; }
-int serial_init( void ) { return(0);}
-
-void serial_putc (char c)
-{
- unsigned val;
-
- while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0)
- WATCHDOG_RESET ();
- writel (&jtag->data, (unsigned char)c);
-}
-
-void serial_puts (const char *s)
-{
- while (*s != 0)
- serial_putc (*s++);
-}
-
-int serial_tstc (void)
-{
- return ( readl (&jtag->control) & NIOS_JTAG_RRDY);
-}
-
-int serial_getc (void)
-{
- int c;
- unsigned val;
-
- while (1) {
- WATCHDOG_RESET ();
- val = readl (&jtag->data);
- if (val & NIOS_JTAG_RVALID)
- break;
- }
- c = val & 0x0ff;
- return (c);
-}
-
-#elif defined(CONFIG_CONSOLE_YANU)
/*-----------------------------------------------------------------*/
/* YANU Imagos serial port */
/*-----------------------------------------------------------------*/
((unsigned)CONFIG_SYS_CLK_FREQ >> k);
baud = best_m + best_n * YANU_BAUDE;
- writel(&uart->baud, baud);
+ writel(baud, &uart->baud);
return;
}
((unsigned)CONFIG_SYS_CLK_FREQ >> k);
baud = best_m + best_n * YANU_BAUDE;
- writel(&uart->baud, baud);
+ writel(baud, &uart->baud);
return;
}
YANU_ACTION_RPE |
YANU_ACTION_RFE | YANU_ACTION_RFIFO_CLEAR | YANU_ACTION_TFIFO_CLEAR;
- writel(&uart->action, action);
+ writel(action, &uart->action);
/* control register cleanup */
/* no interrupts enabled */
control |= YANU_CONTROL_RDYDLY * YANU_RXFIFO_DLY;
control |= YANU_CONTROL_TXTHR * YANU_TXFIFO_THR;
- writel(&uart->control, control);
+ writel(control, &uart->control);
/* to set baud rate */
serial_setbrg();
WATCHDOG_RESET ();
}
- writel(&uart->data, (unsigned char)c);
+ writel((unsigned char)c, &uart->data);
}
void serial_puts (const char *s)
WATCHDOG_RESET ();
/* first we pull the char */
- writel(&uart->action, YANU_ACTION_RFIFO_PULL);
+ writel(YANU_ACTION_RFIFO_PULL, &uart->action);
return(readl(&uart->data) & YANU_DATA_CHAR_MASK);
}
-
-#else /*CONFIG_CONSOLE_YANU*/
-
-/*------------------------------------------------------------------
- * UART the serial port
- *-----------------------------------------------------------------*/
-
-static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE;
-
-#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
-
-/* Everything's already setup for fixed-baud PTF
- * assignment
- */
-void serial_setbrg (void){ return; }
-int serial_init (void) { return (0);}
-
-#else
-
-void serial_setbrg (void)
-{
- unsigned div;
-
- div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
- writel (&uart->divisor,div);
- return;
-}
-
-int serial_init (void)
-{
- serial_setbrg ();
- return (0);
-}
-
-#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
-
-
-/*-----------------------------------------------------------------------
- * UART CONSOLE
- *---------------------------------------------------------------------*/
-void serial_putc (char c)
-{
- if (c == '\n')
- serial_putc ('\r');
- while ((readl (&uart->status) & NIOS_UART_TRDY) == 0)
- WATCHDOG_RESET ();
- writel (&uart->txdata,(unsigned char)c);
-}
-
-void serial_puts (const char *s)
-{
- while (*s != 0) {
- serial_putc (*s++);
- }
-}
-
-int serial_tstc (void)
-{
- return (readl (&uart->status) & NIOS_UART_RRDY);
-}
-
-int serial_getc (void)
-{
- while (serial_tstc () == 0)
- WATCHDOG_RESET ();
- return (readl (&uart->rxdata) & 0x00ff );
-}
-
-#endif /* CONFIG_JTAG_CONSOLE */
/*
* Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
- * With help from the common/soft_spi and cpu/mpc8260 drivers
+ * With help from the common/soft_spi and arch/ppc/cpu/mpc8260 drivers
*
* See file CREDITS for list of people who contributed to this
* project.
{
0x12, /* bLength */
1, /* bDescriptorType: UDESC_DEVICE */
- 0x0002, /* bcdUSB: v2.0 */
+ cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
9, /* bDeviceClass: UDCLASS_HUB */
0, /* bDeviceSubClass: UDSUBCLASS_HUB */
1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
64, /* bMaxPacketSize: 64 bytes */
0x0000, /* idVendor */
0x0000, /* idProduct */
- 0x0001, /* bcdDevice */
+ cpu_to_le16(0x0100), /* bcdDevice */
1, /* iManufacturer */
2, /* iProduct */
0, /* iSerialNumber */
uint32_t reg;
uint32_t *status_reg;
- if (le16_to_cpu(req->index) >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
+ if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
printf("The request port(%d) is not configured\n",
le16_to_cpu(req->index) - 1);
return -1;
tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
if (reg & EHCI_PS_OCA)
tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
- if (reg & EHCI_PS_PR &&
- (portreset & (1 << le16_to_cpu(req->index)))) {
- int ret;
- /* force reset to complete */
- reg = reg & ~(EHCI_PS_PR | EHCI_PS_CLEAR);
- ehci_writel(status_reg, reg);
- ret = handshake(status_reg, EHCI_PS_PR, 0, 2 * 1000);
- if (!ret)
- tmpbuf[0] |= USB_PORT_STAT_RESET;
- else
- printf("port(%d) reset error\n",
- le16_to_cpu(req->index) - 1);
- }
+ if (reg & EHCI_PS_PR)
+ tmpbuf[0] |= USB_PORT_STAT_RESET;
if (reg & EHCI_PS_PP)
tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
ehci_writel(status_reg, reg);
break;
} else {
+ int ret;
+
reg |= EHCI_PS_PR;
reg &= ~EHCI_PS_PE;
ehci_writel(status_reg, reg);
wait_ms(50);
/* terminate the reset */
ehci_writel(status_reg, reg & ~EHCI_PS_PR);
- wait_ms(2);
- portreset |= 1 << le16_to_cpu(req->index);
+ /*
+ * A host controller must terminate the reset
+ * and stabilize the state of the port within
+ * 2 milliseconds
+ */
+ ret = handshake(status_reg, EHCI_PS_PR, 0,
+ 2 * 1000);
+ if (!ret)
+ portreset |=
+ 1 << le16_to_cpu(req->index);
+ else
+ printf("port(%d) reset error\n",
+ le16_to_cpu(req->index) - 1);
}
break;
default:
#ifdef CONFIG_PCI_EHCI_DEVICE
static struct pci_device_id ehci_pci_ids[] = {
/* Please add supported PCI EHCI controller ids here */
+ {0x1033, 0x00E0},
{0, 0}
};
#endif
*
* [[GNU/GPL disclaimer]]
*
- * and in part from AU1x00 OHCI HCD driver "u-boot/cpu/mips/au1x00_usb_ohci.c"
+ * and in part from AU1x00 OHCI HCD driver "u-boot/arch/mips/cpu/au1x00_usb_ohci.c"
* (original copyright message follows):
*
* URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-#ifndef CONFIG_AT91_LEGACY
-#define CONFIG_AT91_LEGACY
-#warning Please update to use C structur SoC access !
-#endif
-
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
#include <asm/arch/at91_pmc.h>
int usb_cpu_init(void)
{
+ at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE;
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
defined(CONFIG_AT91SAM9261)
/* Enable PLLB */
- at91_sys_write(AT91_CKGR_PLLBR, get_pllb_init());
- while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
+ writel(get_pllb_init(), &pmc->pllbr);
+ while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
;
#endif
/* Enable USB host clock. */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP);
+ writel(1 << AT91_ID_UHP, &pmc->pcer);
#ifdef CONFIG_AT91SAM9261
- at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP | AT91_PMC_HCK0);
+ writel(AT91_PMC_UHP | AT91_PMC_HCK0, &pmc->scer);
#else
- at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP);
+ writel(AT91_PMC_UHP, &pmc->scer);
#endif
return 0;
int usb_cpu_stop(void)
{
+ at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE;
+
/* Disable USB host clock. */
- at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP);
+ writel(1 << AT91_ID_UHP, &pmc->pcdr);
#ifdef CONFIG_AT91SAM9261
- at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_HCK0);
+ writel(AT91_PMC_UHP | AT91_PMC_HCK0, &pmc->scdr);
#else
- at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP);
+ writel(AT91_PMC_UHP, &pmc->scdr);
#endif
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20)
/* Disable PLLB */
- at91_sys_write(AT91_CKGR_PLLBR, 0);
- while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != 0)
+ writel(0, &pmc->pllbr);
+ while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0)
;
#endif
* ToDo: identify these cases
*/
- DPRINT("radeonfb: Found %ldk of %s %d bits wide videoram\n",
+ DPRINT("radeonfb: Found %dk of %s %d bits wide videoram\n",
rinfo->video_ram / 1024,
rinfo->vram_ddr ? "DDR" : "SDRAM",
rinfo->vram_width);
rinfo->pdev.device = did;
rinfo->family = get_radeon_id_family(rinfo->pdev.device);
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
- &rinfo->fb_base_phys);
+ &rinfo->fb_base_bus);
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2,
- &rinfo->mmio_base_phys);
- rinfo->fb_base_phys &= 0xfffff000;
- rinfo->mmio_base_phys &= ~0x04;
-
- rinfo->mmio_base = (void *)rinfo->mmio_base_phys;
- DPRINT("rinfo->mmio_base = 0x%x\n",rinfo->mmio_base);
+ &rinfo->mmio_base_bus);
+ rinfo->fb_base_bus &= 0xfffff000;
+ rinfo->mmio_base_bus &= ~0x04;
+
+ rinfo->mmio_base = pci_bus_to_virt(pdev, rinfo->mmio_base_bus,
+ PCI_REGION_MEM, 0, MAP_NOCACHE);
+ DPRINT("rinfo->mmio_base = 0x%p bus=0x%x\n",
+ rinfo->mmio_base, rinfo->mmio_base_bus);
rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base);
/* PostBIOS with x86 emulater */
- BootVideoCardBIOS(pdev, NULL, 0);
+ if (!BootVideoCardBIOS(pdev, NULL, 0))
+ return -1;
/*
* Check for errata
rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM,
rinfo->video_ram);
- rinfo->fb_base = (void *)rinfo->fb_base_phys;
-
- DPRINT("Radeon: framebuffer base phy address 0x%08x," \
- "MMIO base phy address 0x%08x," \
- "framebuffer local base 0x%08x.\n ",
- rinfo->fb_base_phys, rinfo->mmio_base_phys,
- rinfo->fb_local_base);
-
+ rinfo->fb_base = pci_bus_to_virt(pdev, rinfo->fb_base_bus,
+ PCI_REGION_MEM, 0, MAP_NOCACHE);
+ DPRINT("Radeon: framebuffer base address 0x%08x, "
+ "bus address 0x%08x\n"
+ "MMIO base address 0x%08x, bus address 0x%08x, "
+ "framebuffer local base 0x%08x.\n ",
+ (u32)rinfo->fb_base, rinfo->fb_base_bus,
+ (u32)rinfo->mmio_base, rinfo->mmio_base_bus,
+ rinfo->fb_local_base);
return 0;
}
return -1;
}
pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
- pGD->pciBase = rinfo->fb_base_phys;
- pGD->frameAdrs = rinfo->fb_base_phys;
+ pGD->pciBase = (unsigned int)rinfo->fb_base;
+ pGD->frameAdrs = (unsigned int)rinfo->fb_base;
pGD->memSize = 64 * 1024 * 1024;
/* Cursor Start Address */
- pGD->dprBase =
- (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + rinfo->fb_base_phys;
+ pGD->dprBase = (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) +
+ (unsigned int)rinfo->fb_base;
if ((pGD->dprBase & 0x0fff) != 0) {
/* allign it */
pGD->dprBase &= 0xfffff000;
}
DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
PATTERN_ADR);
- pGD->vprBase = rinfo->fb_base_phys; /* Dummy */
- pGD->cprBase = rinfo->fb_base_phys; /* Dummy */
+ pGD->vprBase = (unsigned int)rinfo->fb_base; /* Dummy */
+ pGD->cprBase = (unsigned int)rinfo->fb_base; /* Dummy */
/* set up Hardware */
/* Clear video memory (only visible screen area) */
struct pci_device_id pdev;
u16 family;
- u32 fb_base_phys;
- u32 mmio_base_phys;
+ u32 fb_base_bus;
+ u32 mmio_base_bus;
void *mmio_base;
void *fb_base;
}
#endif
+/*
+ * RLE8 bitmap support
+ */
+
+#ifdef CONFIG_VIDEO_BMP_RLE8
+/* Pre-calculated color table entry */
+struct palette {
+ union {
+ unsigned short w; /* word */
+ unsigned int dw; /* double word */
+ } ce; /* color entry */
+};
+
+/*
+ * Helper to draw encoded/unencoded run.
+ */
+static void draw_bitmap (uchar **fb, uchar *bm, struct palette *p,
+ int cnt, int enc)
+{
+ ulong addr = (ulong)*fb;
+ int *off;
+ int enc_off = 1;
+ int i;
+
+ /*
+ * Setup offset of the color index in the bitmap.
+ * Color index of encoded run is at offset 1.
+ */
+ off = enc ? &enc_off : &i;
+
+ switch (VIDEO_DATA_FORMAT) {
+ case GDF__8BIT_INDEX:
+ for (i = 0; i < cnt; i++)
+ *(unsigned char *)addr++ = bm[*off];
+ break;
+ case GDF_15BIT_555RGB:
+ case GDF_16BIT_565RGB:
+ /* differences handled while pre-calculating palette */
+ for (i = 0; i < cnt; i++) {
+ *(unsigned short *)addr = p[bm[*off]].ce.w;
+ addr += 2;
+ }
+ break;
+ case GDF_32BIT_X888RGB:
+ for (i = 0; i < cnt; i++) {
+ *(unsigned long *)addr = p[bm[*off]].ce.dw;
+ addr += 4;
+ }
+ break;
+ }
+ *fb = (uchar *)addr; /* return modified address */
+}
+
+static int display_rle8_bitmap (bmp_image_t *img, int xoff, int yoff,
+ int width, int height)
+{
+ unsigned char *bm;
+ unsigned char *fbp;
+ unsigned int cnt, runlen;
+ int decode = 1;
+ int x, y, bpp, i, ncolors;
+ struct palette p[256];
+ bmp_color_table_entry_t cte;
+ int green_shift, red_off;
+
+ x = 0;
+ y = __le32_to_cpu(img->header.height) - 1;
+ ncolors = __le32_to_cpu(img->header.colors_used);
+ bpp = VIDEO_PIXEL_SIZE;
+ fbp = (unsigned char *)((unsigned int)video_fb_address +
+ (((y + yoff) * VIDEO_COLS) + xoff) * bpp);
+
+ bm = (uchar *)img + __le32_to_cpu(img->header.data_offset);
+
+ /* pre-calculate and setup palette */
+ switch (VIDEO_DATA_FORMAT) {
+ case GDF__8BIT_INDEX:
+ for (i = 0; i < ncolors; i++) {
+ cte = img->color_table[i];
+ video_set_lut (i, cte.red, cte.green, cte.blue);
+ }
+ break;
+ case GDF_15BIT_555RGB:
+ case GDF_16BIT_565RGB:
+ if (VIDEO_DATA_FORMAT == GDF_15BIT_555RGB) {
+ green_shift = 3;
+ red_off = 10;
+ } else {
+ green_shift = 2;
+ red_off = 11;
+ }
+ for (i = 0; i < ncolors; i++) {
+ cte = img->color_table[i];
+ p[i].ce.w = SWAP16((unsigned short)
+ (((cte.red >> 3) << red_off) |
+ ((cte.green >> green_shift) << 5) |
+ cte.blue >> 3));
+ }
+ break;
+ case GDF_32BIT_X888RGB:
+ for (i = 0; i < ncolors; i++) {
+ cte = img->color_table[i];
+ p[i].ce.dw = SWAP32((cte.red << 16) | (cte.green << 8) |
+ cte.blue);
+ }
+ break;
+ default:
+ printf("RLE Bitmap unsupported in video mode 0x%x\n",
+ VIDEO_DATA_FORMAT);
+ return -1;
+ }
+
+ while (decode) {
+ switch (bm[0]) {
+ case 0:
+ switch (bm[1]) {
+ case 0:
+ /* scan line end marker */
+ bm += 2;
+ x = 0;
+ y--;
+ fbp = (unsigned char *)
+ ((unsigned int)video_fb_address +
+ (((y + yoff) * VIDEO_COLS) +
+ xoff) * bpp);
+ continue;
+ case 1:
+ /* end of bitmap data marker */
+ decode = 0;
+ break;
+ case 2:
+ /* run offset marker */
+ x += bm[2];
+ y -= bm[3];
+ fbp = (unsigned char *)
+ ((unsigned int)video_fb_address +
+ (((y + yoff) * VIDEO_COLS) +
+ x + xoff) * bpp);
+ bm += 4;
+ break;
+ default:
+ /* unencoded run */
+ cnt = bm[1];
+ runlen = cnt;
+ bm += 2;
+ if (y < height) {
+ if (x >= width) {
+ x += runlen;
+ goto next_run;
+ }
+ if (x + runlen > width)
+ cnt = width - x;
+
+ draw_bitmap (&fbp, bm, p, cnt, 0);
+ x += runlen;
+ }
+next_run:
+ bm += runlen;
+ if (runlen & 1)
+ bm++; /* 0 padding if length is odd */
+ }
+ break;
+ default:
+ /* encoded run */
+ if (y < height) { /* only draw into visible area */
+ cnt = bm[0];
+ runlen = cnt;
+ if (x >= width) {
+ x += runlen;
+ bm += 2;
+ continue;
+ }
+ if (x + runlen > width)
+ cnt = width - x;
+
+ draw_bitmap (&fbp, bm, p, cnt, 1);
+ x += runlen;
+ }
+ bm += 2;
+ break;
+ }
+ }
+ return 0;
+}
+#endif
+
/*
* Display the BMP file located at address bmp_image.
- * Only uncompressed
*/
int video_display_bitmap (ulong bmp_image, int x, int y)
{
debug ("Display-bmp: %d x %d with %d colors\n",
width, height, colors);
- if (compression != BMP_BI_RGB) {
+ if (compression != BMP_BI_RGB
+#ifdef CONFIG_VIDEO_BMP_RLE8
+ && compression != BMP_BI_RLE8
+#endif
+ ) {
printf ("Error: compression type %ld not supported\n",
compression);
#ifdef CONFIG_VIDEO_BMP_GZIP
((y + height - 1) * VIDEO_COLS * VIDEO_PIXEL_SIZE) +
x * VIDEO_PIXEL_SIZE);
+#ifdef CONFIG_VIDEO_BMP_RLE8
+ if (compression == BMP_BI_RLE8) {
+ return display_rle8_bitmap(bmp,
+ x, y, width, height);
+ }
+#endif
+
/* We handle only 8bpp or 24 bpp bitmap */
switch (le16_to_cpu (bmp->header.bit_count)) {
case 8:
static int at91_wdt_settimeout(unsigned int timeout)
{
unsigned int reg;
- unsigned int mr;
+ at91_wdt_t *wd = (at91_wdt_t *) AT91_WDT_BASE;
/* Check if disabled */
- mr = at91_sys_read(AT91_WDT_MR);
- if (mr & AT91_WDT_WDDIS) {
+ if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) {
printf("sorry, watchdog is disabled\n");
return -1;
}
* Since WDV is a 12-bit counter, the maximum period is
* 4096 / 256 = 16 seconds.
*/
- reg = AT91_WDT_WDRSTEN /* causes watchdog reset */
- /* | AT91_WDT_WDRPROC causes processor reset only */
- | AT91_WDT_WDDBGHLT /* disabled in debug mode */
- | AT91_WDT_WDD /* restart at any time */
- | (timeout & AT91_WDT_WDV); /* timer value */
- at91_sys_write(AT91_WDT_MR, reg);
+
+ reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */
+ | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */
+ | AT91_WDT_MR_WDD(0xfff) /* restart at any time */
+ | AT91_WDT_MR_WDV(timeout); /* timer value */
+
+ writel(reg, &wd->mr);
return 0;
}
void hw_watchdog_reset(void)
{
- at91_sys_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
+ at91_wdt_t *wd = (at91_wdt_t *) AT91_WDT_BASE;
+ writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr);
}
void hw_watchdog_init(void)
COBJ_FILES-$(CONFIG_API) += libgenwrap.o
# Source files which exist outside the examples/api directory
-EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/crc32.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/ctype.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/div64.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/string.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/time.o
-EXT_COBJ_FILES-$(CONFIG_API) += lib_generic/vsprintf.o
+EXT_COBJ_FILES-$(CONFIG_API) += lib/crc32.o
+EXT_COBJ_FILES-$(CONFIG_API) += lib/ctype.o
+EXT_COBJ_FILES-$(CONFIG_API) += lib/div64.o
+EXT_COBJ_FILES-$(CONFIG_API) += lib/string.o
+EXT_COBJ_FILES-$(CONFIG_API) += lib/time.o
+EXT_COBJ_FILES-$(CONFIG_API) += lib/vsprintf.o
ifeq ($(ARCH),ppc)
-EXT_SOBJ_FILES-$(CONFIG_API) += lib_ppc/ppcstring.o
+EXT_SOBJ_FILES-$(CONFIG_API) += arch/ppc/lib/ppcstring.o
endif
# Create a list of source files so their dependencies can be auto-generated
$(OBJCOPY) -O binary $@ $(OUTPUT).bin 2>/dev/null
# Rule to build generic library C files
-$(obj)%.o: $(SRCTREE)/lib_generic/%.c
+$(obj)%.o: $(SRCTREE)/lib/%.c
$(CC) -g $(CFLAGS) -c -o $@ $<
# Rule to build architecture-specific library assembly files
-$(obj)%.o: $(SRCTREE)/lib_$(ARCH)/%.S
+$(obj)%.o: $(SRCTREE)/arch/$(ARCH)/lib/%.S
$(CC) -g $(CFLAGS) -c -o $@ $<
#########################################################################
*
*
* This is is a set of wrappers/stubs that allow to use certain routines from
- * U-Boot's lib_generic in the standalone app. This way way we can re-use
+ * U-Boot's lib in the standalone app. This way way we can re-use
* existing code e.g. operations on strings and similar.
*
*/
/* The dpalloc function used and implemented in this file was derieved
- * from PPCBoot/U-Boot file "cpu/mpc8260/commproc.c".
+ * from PPCBoot/U-Boot file "arch/ppc/cpu/mpc8260/commproc.c".
*/
/* Author: Arun Dharankar <ADharankar@ATTBI.Com>
{
struct mtdids *id = current_part->dev->id;
+ switch(id->type) {
#if defined(CONFIG_CMD_FLASH)
- if (id->type == MTD_DEV_TYPE_NOR) {
+ case MTD_DEV_TYPE_NOR:
return get_fl_mem_nor(off, size, ext_buf);
- }
+ break;
#endif
-
#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
- if (id->type == MTD_DEV_TYPE_NAND)
+ case MTD_DEV_TYPE_NAND:
return get_fl_mem_nand(off, size, ext_buf);
+ break;
#endif
-
#if defined(CONFIG_CMD_ONENAND)
- if (id->type == MTD_DEV_TYPE_ONENAND)
+ case MTD_DEV_TYPE_ONENAND:
return get_fl_mem_onenand(off, size, ext_buf);
+ break;
#endif
-
- printf("get_fl_mem: unknown device type, using raw offset!\n");
+ default:
+ printf("get_fl_mem: unknown device type, " \
+ "using raw offset!\n");
+ }
return (void*)off;
}
{
struct mtdids *id = current_part->dev->id;
+ switch(id->type) {
#if defined(CONFIG_CMD_FLASH)
- if (id->type == MTD_DEV_TYPE_NOR)
+ case MTD_DEV_TYPE_NOR:
return get_node_mem_nor(off, ext_buf);
+ break;
#endif
-
#if defined(CONFIG_JFFS2_NAND) && \
defined(CONFIG_CMD_NAND)
- if (id->type == MTD_DEV_TYPE_NAND)
+ case MTD_DEV_TYPE_NAND:
return get_node_mem_nand(off, ext_buf);
+ break;
#endif
-
#if defined(CONFIG_CMD_ONENAND)
- if (id->type == MTD_DEV_TYPE_ONENAND)
+ case MTD_DEV_TYPE_ONENAND:
return get_node_mem_onenand(off, ext_buf);
+ break;
#endif
-
- printf("get_node_mem: unknown device type, using raw offset!\n");
+ default:
+ printf("get_fl_mem: unknown device type, " \
+ "using raw offset!\n");
+ }
return (void*)off;
}
+++ /dev/null
-/*
- * U-boot - ptrace.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _BLACKFIN_PTRACE_H
-#define _BLACKFIN_PTRACE_H
-
-#define NEW_PT_REGS
-
-/*
- * GCC defines register number like this:
- * -----------------------------
- * 0 - 7 are data registers R0-R7
- * 8 - 15 are address registers P0-P7
- * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
- * 32 - 33 A registers A0 & A1
- * 34 - status register
- *
- * We follows above, except:
- * 32-33 --- Low 32-bit of A0&1
- * 34-35 --- High 8-bit of A0&1
- */
-
-#if defined(NEW_PT_REGS)
-
-#define PT_IPEND 0
-#define PT_SYSCFG (PT_IPEND+4)
-#define PT_SEQSTAT (PT_SYSCFG+4)
-#define PT_RETE (PT_SEQSTAT+4)
-#define PT_RETN (PT_RETE+4)
-#define PT_RETX (PT_RETN+4)
-#define PT_RETI (PT_RETX+4)
-#define PT_PC PT_RETI
-#define PT_RETS (PT_RETI+4)
-#define PT_RESERVED (PT_RETS+4)
-#define PT_ASTAT (PT_RESERVED+4)
-#define PT_LB1 (PT_ASTAT+4)
-#define PT_LB0 (PT_LB1+4)
-#define PT_LT1 (PT_LB0+4)
-#define PT_LT0 (PT_LT1+4)
-#define PT_LC1 (PT_LT0+4)
-#define PT_LC0 (PT_LC1+4)
-#define PT_A1W (PT_LC0+4)
-#define PT_A1X (PT_A1W+4)
-#define PT_A0W (PT_A1X+4)
-#define PT_A0X (PT_A0W+4)
-#define PT_B3 (PT_A0X+4)
-#define PT_B2 (PT_B3+4)
-#define PT_B1 (PT_B2+4)
-#define PT_B0 (PT_B1+4)
-#define PT_L3 (PT_B0+4)
-#define PT_L2 (PT_L3+4)
-#define PT_L1 (PT_L2+4)
-#define PT_L0 (PT_L1+4)
-#define PT_M3 (PT_L0+4)
-#define PT_M2 (PT_M3+4)
-#define PT_M1 (PT_M2+4)
-#define PT_M0 (PT_M1+4)
-#define PT_I3 (PT_M0+4)
-#define PT_I2 (PT_I3+4)
-#define PT_I1 (PT_I2+4)
-#define PT_I0 (PT_I1+4)
-#define PT_USP (PT_I0+4)
-#define PT_FP (PT_USP+4)
-#define PT_P5 (PT_FP+4)
-#define PT_P4 (PT_P5+4)
-#define PT_P3 (PT_P4+4)
-#define PT_P2 (PT_P3+4)
-#define PT_P1 (PT_P2+4)
-#define PT_P0 (PT_P1+4)
-#define PT_R7 (PT_P0+4)
-#define PT_R6 (PT_R7+4)
-#define PT_R5 (PT_R6+4)
-#define PT_R4 (PT_R5+4)
-#define PT_R3 (PT_R4+4)
-#define PT_R2 (PT_R3+4)
-#define PT_R1 (PT_R2+4)
-#define PT_R0 (PT_R1+4)
-#define PT_ORIG_R0 (PT_R0+4)
-#define PT_SR PT_SEQSTAT
-
-#else
-/*
- * Here utilize blackfin : dpregs = [pregs + imm16s4]
- * [pregs + imm16s4] = dpregs
- * to access defferent saved reg in stack
- */
-#define PT_R3 0
-#define PT_R4 4
-#define PT_R2 8
-#define PT_R1 12
-#define PT_P5 16
-#define PT_P4 20
-#define PT_P3 24
-#define PT_P2 28
-#define PT_P1 32
-#define PT_P0 36
-#define PT_R7 40
-#define PT_R6 44
-#define PT_R5 48
-#define PT_PC 52
-#define PT_SEQSTAT 56 /* so-called SR reg */
-#define PT_SR PT_SEQSTAT
-#define PT_ASTAT 60
-#define PT_RETS 64
-#define PT_A1w 68
-#define PT_A0w 72
-#define PT_A1x 76
-#define PT_A0x 80
-#define PT_ORIG_R0 84
-#define PT_R0 88
-#define PT_USP 92
-#define PT_FP 96
-#define PT_SP 100
-
-/* Added by HuTao, May26 2003 3:18PM */
-#define PT_IPEND 100
-
-/* Add SYSCFG register for single stepping support */
-#define PT_SYSCFG 104
-
-#endif
-
-#ifndef __ASSEMBLY__
-
-#if defined(NEW_PT_REGS)
-/* this struct defines the way the registers are stored on the
- * stack during a system call.
- */
-struct pt_regs {
- long ipend;
- long syscfg;
- long seqstat;
- long rete;
- long retn;
- long retx;
- long pc;
- long rets;
- long reserved;
- long astat;
- long lb1;
- long lb0;
- long lt1;
- long lt0;
- long lc1;
- long lc0;
- long a1w;
- long a1x;
- long a0w;
- long a0x;
- long b3;
- long b2;
- long b1;
- long b0;
- long l3;
- long l2;
- long l1;
- long l0;
- long m3;
- long m2;
- long m1;
- long m0;
- long i3;
- long i2;
- long i1;
- long i0;
- long usp;
- long fp;
- long p5;
- long p4;
- long p3;
- long p2;
- long p1;
- long p0;
- long r7;
- long r6;
- long r5;
- long r4;
- long r3;
- long r2;
- long r1;
- long r0;
- long orig_r0;
-};
-
-#else
-/* now we don't know what regs the system call will use */
-struct pt_regs {
- long r3;
- long r4;
- long r2;
- long r1;
- long p5;
- long p4;
- long p3;
- long p2;
- long p1;
- long p0;
- long r7;
- long r6;
- long r5;
- unsigned long pc;
- unsigned long seqstat;
- unsigned long astat;
- unsigned long rets;
- long a1w;
- long a0w;
- long a1x;
- long a0x;
- long orig_r0;
- long r0;
- long usp;
- long fp;
-/*
- * Added for supervisor/user mode switch.
- *
- * HuTao May26 03 3:23PM
- */
- long ipend;
- long syscfg;
-};
-
-#endif
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13 /* ptrace signal */
-
-#ifdef __KERNEL__
-
-#ifndef PS_S
-#define PS_S (0x0c00)
-
-/* Bit 11:10 of SEQSTAT defines user/supervisor/debug mode
- * 00: user
- * 01: supervisor
- * 1x: debug
- */
-
-#define PS_M (0x1000) /* I am not sure why this is required here Akbar */
-#endif
-
-#define user_mode(regs) (!((regs)->seqstat & PS_S))
-#define instruction_pointer(regs) ((regs)->pc)
-extern void show_regs(struct pt_regs *);
-
-#endif
-#endif
-#endif
+++ /dev/null
-/*
- * U-boot - traps.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * linux/include/asm/traps.h
- * Copyright (C) 1993 Hamish Macdonald
- * Lineo, Inc Jul 2001 Tony Kou
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- */
-
-#ifndef _BLACKFIN_TRAPS_H
-#define _BLACKFIN_TRAPS_H
-
-#ifndef __ASSEMBLY__
-typedef void (*e_vector) (void);
-extern e_vector vectors[];
-#endif
-
-#define VEC_SYS (0)
-#define VEC_EXCPT01 (1)
-#define VEC_EXCPT02 (2)
-#define VEC_EXCPT03 (3)
-#define VEC_EXCPT04 (4)
-#define VEC_EXCPT05 (5)
-#define VEC_EXCPT06 (6)
-#define VEC_EXCPT07 (7)
-#define VEC_EXCPT08 (8)
-#define VEC_EXCPT09 (9)
-#define VEC_EXCPT10 (10)
-#define VEC_EXCPT11 (11)
-#define VEC_EXCPT12 (12)
-#define VEC_EXCPT13 (13)
-#define VEC_EXCPT14 (14)
-#define VEC_EXCPT15 (15)
-#define VEC_STEP (16)
-#define VEC_OVFLOW (17)
-#define VEC_UNDEF_I (33)
-#define VEC_ILGAL_I (34)
-#define VEC_CPLB_VL (35)
-#define VEC_MISALI_D (36)
-#define VEC_UNCOV (37)
-#define VEC_CPLB_M (38)
-#define VEC_CPLB_MHIT (39)
-#define VEC_WATCH (40)
-#define VEC_ISTRU_VL (41)
-#define VEC_MISALI_I (42)
-#define VEC_CPLB_I_VL (43)
-#define VEC_CPLB_I_M (44)
-#define VEC_CPLB_I_MHIT (45)
-#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
-
-#define VECOFF(vec) ((vec)<<2)
-
-#ifndef __ASSEMBLY__
-
-/* Status register bits */
-#define PS_T (0x8000)
-#define PS_S (0x0c00) /* Supervisor mode = 0b01 */
-#define PS_D (0x0c00) /* Debug mode = 0b1x */
-#define PS_M (0x1000)
-#define PS_C (0x0001)
-
-#endif
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_NIOS2_BITOPS_H_
-#define __ASM_NIOS2_BITOPS_H_
-
-
-extern void set_bit(int nr, volatile void * a);
-extern void clear_bit(int nr, volatile void * a);
-extern int test_and_clear_bit(int nr, volatile void * a);
-extern void change_bit(unsigned long nr, volatile void *addr);
-extern int test_and_set_bit(int nr, volatile void * a);
-extern int test_and_change_bit(int nr, volatile void * addr);
-extern int test_bit(int nr, volatile void * a);
-extern int ffs(int i);
-#define PLATFORM_FFS
-
-#endif /* __ASM_NIOS2_BITOPS_H */
void init_cmd_timeout(void);
void reset_cmd_timeout(void);
-/* lib_$(ARCH)/board.c */
+/* arch/$(ARCH)/lib/board.c */
void board_init_f (ulong) __attribute__ ((noreturn));
void board_init_r (gd_t *, ulong) __attribute__ ((noreturn));
int checkboard (void);
/* $(CPU)/.../video.c */
ulong video_setmem (ulong);
-/* lib_$(ARCH)/cache.c */
+/* arch/$(ARCH)/lib/cache.c */
void flush_cache (unsigned long, unsigned long);
void flush_dcache_range(unsigned long start, unsigned long stop);
void invalidate_dcache_range(unsigned long start, unsigned long stop);
-/* lib_$(ARCH)/ticks.S */
+/* arch/$(ARCH)/lib/ticks.S */
unsigned long long get_ticks(void);
void wait_ticks (unsigned long);
-/* lib_$(ARCH)/time.c */
+/* arch/$(ARCH)/lib/time.c */
void __udelay (unsigned long);
ulong usec2ticks (unsigned long usec);
ulong ticks2usec (unsigned long ticks);
int init_timebase (void);
-/* lib_generic/gunzip.c */
+/* lib/gunzip.c */
int gunzip(void *, int, unsigned char *, unsigned long *);
int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp,
int stoponerr, int offset);
-/* lib_generic/net_utils.c */
+/* lib/net_utils.c */
#include <net.h>
static inline IPaddr_t getenv_IPaddr (char *var)
{
return (string_to_ip(getenv(var)));
}
-/* lib_generic/time.c */
+/* lib/time.c */
void udelay (unsigned long);
-/* lib_generic/vsprintf.c */
+/* lib/vsprintf.c */
ulong simple_strtoul(const char *cp,char **endp,unsigned int base);
unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base);
long simple_strtol(const char *cp,char **endp,unsigned int base);
__attribute__ ((format (__printf__, 2, 3)));
int vsprintf(char *buf, const char *fmt, va_list args);
-/* lib_generic/strmhz.c */
+/* lib/strmhz.c */
char * strmhz(char *buf, long hz);
-/* lib_generic/crc32.c */
+/* lib/crc32.c */
#include <u-boot/crc.h>
/* common/console.c */
#define CONFIG_CMD_AMBAPP /* AMBA Plug & Play Bus print utility */
#define CONFIG_CMD_ASKENV /* ask for env variable */
+#define CONFIG_CMD_AT91_SPIMUX /* AT91 MMC/SPI Mux Support */
#define CONFIG_CMD_BDI /* bdinfo */
#define CONFIG_CMD_BEDBUG /* Include BedBug Debugger */
#define CONFIG_CMD_BMP /* BMP support */
#define CONFIG_CMD_EDITENV /* editenv */
#define CONFIG_CMD_EEPROM /* EEPROM read/write support */
#define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */
-#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_FDC /* Floppy Disk Support */
#define CONFIG_CMD_LOADS /* loads */
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
#define CONFIG_CMD_MFSL /* FSL support for Microblaze */
+#define CONFIG_CMD_MG_DISK /* mGine m(g)flash IO node support */
#define CONFIG_CMD_MII /* MII support */
#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_REGINFO /* Register dump */
#define CONFIG_CMD_REISER /* Reiserfs support */
#define CONFIG_CMD_RUN /* run command in env variable */
+#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_SAVES /* save S record dump */
#define CONFIG_CMD_SCSI /* SCSI Support */
#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
#define CONFIG_CMD_SOURCE /* "source" command support */
#define CONFIG_CMD_SPI /* SPI utility */
#define CONFIG_CMD_TERMINAL /* built-in Serial Terminal */
+#define CONFIG_CMD_UBI /* UBI Support */
+#define CONFIG_CMD_UBIFS /* UBIFS Support */
#define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */
#define CONFIG_CMD_UNZIP /* unzip from memory to memory */
#define CONFIG_CMD_USB /* USB Support */
#define CONFIG_CMD_VFD /* VFD support (TRAB) */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
-#define CONFIG_CMD_AT91_SPIMUX /* AT91 MMC/SPI Mux Support */
-#define CONFIG_CMD_MG_DISK /* mGine m(g)flash IO node support */
#endif /* _CONFIG_CMD_ALL_H */
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
*/
/*
- Linux TAGs (see lib_arm/armlinux.c)
+ Linux TAGs (see arch/arm/lib/armlinux.c)
*/
#define CONFIG_CMDLINE_TAG
#undef CONFIG_SETUP_MEMORY_TAGS
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
-# define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-# define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-# define CONFIG_SYS_HID0_INIT 0
-# define CONFIG_SYS_HID0_FINAL 0
-#endif
+#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL HID0_ICE
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
* I2C EEPROM (CAT24WC08) for environment
*/
#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC08) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC32) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC08) for environment
*/
#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_ETHADDR 00:40:a6:80:14:5
*/
#define CONFIG_HARD_I2C 1 /* hardware support for i2c */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SDRAM_BANK0 1
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC08) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_I2C_MULTI_BUS 1
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
+ CF_CACR_CEIB | CF_CACR_DBWE | \
+ CF_CACR_EUSP)
+
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART 1 /* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
*----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ 1000 /* Always 1000 */
#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+ (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
/*------------------------------------------------------------------------
* STATUS LED -- Provides a simple blinking led. For Nios2 each board
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART 1 /* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
*----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ 1000 /* Always 1000 */
#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+ (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
/*------------------------------------------------------------------------
* STATUS LED -- Provides a simple blinking led. For Nios2 each board
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART 1 /* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
*----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ 1000 /* Always 1000 */
#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec) */
+#define CONFIG_SYS_NIOS_TMRCNT \
+ (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
/*------------------------------------------------------------------------
* STATUS LED -- Provides a simple blinking led. For Nios2 each board
#endif /* total size of a X1240 is 2048 bytes */
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#if 0 /* test-only */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#else
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
*/
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
#define CONFIG_ICECUBE 1 /* ... on IceCube board */
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
-#else
-#define CONFIG_MII 1
-#endif
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_BOOTCOMMAND "run flash_self"
-#if defined(CONFIG_MPC5200)
/*
* IPB Bus clocking configuration.
*/
#else
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
-#endif /* CONFIG_MPC5200 */
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#if defined(CONFIG_LITE5200B)
#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C hardware support */
#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x43711630
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
#define CONFIG_SYS_SDRAM_CTRL 0xE1002000
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+ CF_CACR_DISD | CF_CACR_INVI | \
+ CF_CACR_CEIB | CF_CACR_DCM | \
+ CF_CACR_EUSP)
+
/* Chipselect bank definitions */
/*
* CS0 - NOR Flash
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+ CF_CACR_DISD | CF_CACR_INVI | \
+ CF_CACR_CEIB | CF_CACR_DCM | \
+ CF_CACR_EUSP)
+
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
+ CF_CACR_CEIB | CF_CACR_DCM | \
+ CF_CACR_EUSP)
+
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
* Command line configuration.
*/
#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_NET
#define CONFIG_SYS_PROMPT "=> "
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
+ CF_ADDRMASK(2) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
+ CF_CACR_DBWE)
+
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
*/
#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_EXT2
# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
# undef CONFIG_DM9000_DEBUG
-# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
-# define CONFIG_IPADDR 10.82.121.249
-# define CONFIG_NETMASK 255.255.252.0
-# define CONFIG_SERVERIP 10.82.120.80
-# define CONFIG_GATEWAYIP 10.82.123.254
# define CONFIG_OVERWRITE_ETHADDR_ONCE
# define CONFIG_EXTRA_ENV_SETTINGS \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
- "prog=prot off 0 2ffff;" \
- "era 0 2ffff;" \
- "cp.b ${loadaddr} 0 ${filesize};" \
+ "prog=prot off 0xff800000 0xff82ffff;" \
+ "era 0xff800000 0xff82ffff;" \
+ "cp.b ${loadaddr} 0xff800000 ${filesize};" \
"save\0" \
""
#endif
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
+ CF_ADDRMASK(8) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
+ CF_CACR_DBWE)
+
/* Port configuration */
#define CONFIG_SYS_FECI2C 0xF0
* Command line configuration.
*/
#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_NET
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
+ CF_ADDRMASK(2) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
+ CF_CACR_DBWE)
+
/* Port configuration */
#define CONFIG_SYS_FECI2C 0xF0
*/
#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+ CF_CACR_DISD | CF_CACR_INVI | \
+ CF_CACR_CEIB | CF_CACR_DCM | \
+ CF_CACR_EUSP)
+
/* Chip Select 0 : Boot Flash */
#define CONFIG_SYS_CS0_BASE 0xFFE00000
#define CONFIG_SYS_CS0_MASK 0x001F0001
*/
#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+ CF_CACR_DISD | CF_CACR_INVI | \
+ CF_CACR_CEIB | CF_CACR_DCM | \
+ CF_CACR_EUSP)
+
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
/* Available command configuration */
#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
-#ifdef CONFIG_MCFFEC
-#define CONFIG_ETHADDR 00:06:3b:01:41:55
-#define CONFIG_ETH1ADDR 00:0e:0c:bc:e5:60
-#endif
-
#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_RETRY_COUNT 5
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* FEC_ENET */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "uboot=u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${uboot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off ffe00000 ffe3ffff;" \
+ "era ffe00000 ffe3ffff;" \
+ "cp.b ${loadaddr} ffe00000 ${filesize};"\
+ "save\0" \
+ ""
+
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK 150000000
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+ CF_CACR_DISD | CF_CACR_INVI | \
+ CF_CACR_CEIB | CF_CACR_DCM | \
+ CF_CACR_EUSP)
+
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
* Command line configuration.
*/
#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
+ CF_CACR_CEIB | CF_CACR_DBWE | \
+ CF_CACR_EUSP)
+
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
+# define CONFIG_SYS_TX_ETH_BUFFER 8
+# define CONFIG_SYS_FEC_BUF_USE_SRAM
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_HAS_ETH1
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_END 0x20000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x21
+#define CONFIG_SYS_INIT_RAM_CTRL 0x221
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x43711630
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
-#define CONFIG_SYS_SDRAM_CTRL 0xE1002000
+#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
#define CONFIG_SYS_SDRAM_EMOD 0x80010000
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
+ CF_CACR_DCM_P)
+
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
+ CF_CACR_DCM_P)
+
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
+ CF_CACR_DCM_P)
+
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
+ CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
+ CF_CACR_DEC | CF_CACR_DDCM_P | \
+ CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
+ CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
+ CF_CACR_DEC | CF_CACR_DDCM_P | \
+ CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
+ CF_CACR_IDCM)
+#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
+ CF_CACR_IEC | CF_CACR_ICINVA)
+#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
+ CF_CACR_DEC | CF_CACR_DDCM_P | \
+ CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
+ CF_CACR_IDCM)
+#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
+ CF_CACR_IEC | CF_CACR_ICINVA)
+#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
+ CF_CACR_DEC | CF_CACR_DDCM_P | \
+ CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C hardware support */
#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
***************************************************************/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/
+#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
* BAT0 2G Cacheable, non-guarded
* 0x0000_0000 2G DDR
*/
-#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
+#define CONFIG_SYS_DBAT0L (BATL_PP_RW)
+#define CONFIG_SYS_IBAT0L (BATL_PP_RW)
/*
* BAT1 1G Cache-inhibited, guarded
* BAT0 DDR
*/
#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
+#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
/*
* BAT1 LBC (PIXIS/CF)
--- /dev/null
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2010
+ * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <version.h>
+
+#define CONFIG_MPC5xxx 1
+#define CONFIG_MPC5200 1
+
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
+
+#define BOOTFLAG_COLD 0x01
+#define BOOTFLAG_WARM 0x02
+
+#define CONFIG_MISC_INIT_R 1
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT 5
+#endif
+
+#define CONFIG_PSC_CONSOLE 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200,\
+ 230400}
+
+#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+#undef CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
+
+#define CONFIG_PCI_MEM_BUS 0x40000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x50000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x01000000
+
+#define CONFIG_SYS_XLB_PIPELINING 1
+#define CONFIG_HIGH_BATS 1
+
+#define MV_CI mvSMR
+#define MV_VCI mvSMR
+#define MV_FPGA_DATA 0xff840000
+#define MV_FPGA_SIZE 0x1ff88
+#define MV_KERNEL_ADDR 0xfff00000
+#define MV_SCRIPT_ADDR 0xff806000
+#define MV_INITRD_ADDR 0xff880000
+#define MV_INITRD_LENGTH 0x00240000
+#define MV_SCRATCH_ADDR 0xffcc0000
+#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define MV_KERNEL_ADDR_RAM 0x00100000
+#define MV_INITRD_ADDR_RAM 0x00400000
+
+/*
+ * Supported commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_RANDOM_DELAY
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_VENDOREX
+
+/*
+ * Autoboot
+ */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR "abcdefg"
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTCOMMAND "source ${script_addr}"
+#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \
+ " allocate=6M"
+
+#define XMK_STR(x) #x
+#define MK_STR(x) XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console_nr=0\0" \
+ "console=no\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0" \
+ "fpga=0\0" \
+ "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
+ "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
+ "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
+ "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
+ "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
+ "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
+ "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
+ "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
+ "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
+ "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
+ "mv_version=" U_BOOT_VERSION "\0" \
+ "dhcp_client_id=" MK_STR(MV_CI) "\0" \
+ "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
+ "netretry=no\0" \
+ "use_static_ipaddr=no\0" \
+ "static_ipaddr=192.168.0.101\0" \
+ "static_netmask=255.255.255.0\0" \
+ "static_gateway=0.0.0.0\0" \
+ "initrd_name=uInitrd.mvsmr-rfs\0" \
+ "zcip=yes\0" \
+ "netboot=no\0" \
+ ""
+
+#undef XMK_STR
+#undef MK_STR
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
+
+/*
+ * Flash configuration
+ */
+#undef CONFIG_FLASH_16BIT
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
+#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+
+#define CONFIG_SYS_LOWBOOT
+#define CONFIG_SYS_FLASH_BASE TEXT_BASE
+#define CONFIG_SYS_FLASH_SIZE 0x00800000
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_HAS_UID
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#define CONFIG_ENV_OFFSET 0x8000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x2000
+
+/* used by linker script to wrap code around */
+#define CONFIG_SCRIPT_OFFSET 0x6000
+#define CONFIG_SCRIPT_SECT_SIZE 0x2000
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR 0xF0000000
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT 1
+#endif
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+#define CONFIG_SYS_MALLOC_LEN (512 << 10)
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_MODULE 1
+#define CONFIG_SYS_I2C_SPEED 86000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_NET_RETRY_COUNT 5
+
+#define CONFIG_MPC5xxx_FEC
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR 0x00
+#define CONFIG_NETDEV eth0
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#undef CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024
+#else
+#define CONFIG_SYS_CBSIZE 256
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x00800000
+#define CONFIG_SYS_MEMTEST_END 0x02f00000
+
+#define CONFIG_SYS_HZ 1000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x02000000
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 0x00200000
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG 0x00050044
+
+#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
+#define CONFIG_SYS_HID0_FINAL HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG 0x00047800
+#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_CS_BURST 0x000000f0
+#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
+
+#define CONFIG_SYS_RESET_ADDRESS 0x00000100
+
+#undef FPGA_DEBUG
+#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA CONFIG_SYS_XILINX_SPARTAN2
+#define CONFIG_FPGA_XILINX 1
+#define CONFIG_FPGA_SPARTAN2 1
+#define CONFIG_FPGA_COUNT 1
+
+#endif
* I2C EEPROM (CAT24WC08) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC08) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
+#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
+
+#ifdef CONFIG_FSL_NGPIXIS
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
#ifdef CONFIG_PHYS_64BIT
#define PIXIS_BASE_PHYS 0xfffdf0000ull
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
-#define PIXIS_ID 0x0 /* Board ID at offset 0 */
-#define PIXIS_VER 0x1 /* Board version at offset 1 */
-#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
-#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
-#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
-#define PIXIS_PWR 0x5 /* PIXIS Power status register */
-#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
-#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
-#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
-#define PIXIS_VCTL 0x10 /* VELA Control Register */
-#define PIXIS_VSTAT 0x11 /* VELA Status Register */
-#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
-#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
-#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
-#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
-#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
-#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
-#define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */
-#define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */
-#define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */
-#define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */
-#define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */
-#define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */
-
-#define PIXIS_VWATCH 0x24 /* Watchdog Register */
-#define PIXIS_LED 0x25 /* LED Register */
-
-#define PIXIS_SW(x) 0x20 + (x - 1) * 2
-#define PIXIS_EN(x) 0x21 + (x - 1) * 2
-#define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */
-#define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */
-
-/* old pixis referenced names */
-#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
-#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
-#define PIXIS_VSPEED2_TSEC1SER 0x8
-#define PIXIS_VSPEED2_TSEC2SER 0x4
-#define PIXIS_VSPEED2_TSEC3SER 0x2
-#define PIXIS_VSPEED2_TSEC4SER 0x1
-#define PIXIS_VCFGEN1_TSEC1SER 0x20
-#define PIXIS_VCFGEN1_TSEC2SER 0x20
-#define PIXIS_VCFGEN1_TSEC3SER 0x20
-#define PIXIS_VCFGEN1_TSEC4SER 0x20
-#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
- | PIXIS_VSPEED2_TSEC2SER \
- | PIXIS_VSPEED2_TSEC3SER \
- | PIXIS_VSPEED2_TSEC4SER)
-#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
- | PIXIS_VCFGEN1_TSEC2SER \
- | PIXIS_VCFGEN1_TSEC3SER \
- | PIXIS_VCFGEN1_TSEC4SER)
+#define PIXIS_LBMAP_SWITCH 7
+#define PIXIS_LBMAP_MASK 0xf0
+#define PIXIS_LBMAP_SHIFT 4
+#define PIXIS_LBMAP_ALTBANK 0x20
+#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART 1 /* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */
#else
#define CONFIG_SYS_NIOS_CONSOLE 0x009208a0 /* UART base addr */
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
*----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ 1000 /* Always 1000 */
#define CONFIG_SYS_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+ (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
/*
* The Atmel EEPROM uses 16Bit addressing.
***************************************************************/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART 1 /* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
*----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ 1000 /* Always 1000 */
#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period */
+#define CONFIG_SYS_NIOS_TMRCNT \
+ (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
/*------------------------------------------------------------------------
* STATUS LED -- Provides a simple blinking led. For Nios2 each board
* I2C EEPROM (24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#undef CONFIG_NS8382X
-#endif
/* Partitions */
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
-#if defined(CONFIG_MPC5200)
#define CONFIG_CMD_PCI
-#endif
/*
#define CONFIG_BOOTCOMMAND "run flash_self"
-#if defined(CONFIG_MPC5200)
/*
* IPB Bus clocking configuration.
*/
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#endif
/*
* I2C configuration
*/
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#if defined(CONFIG_BOOT_ROM)
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (24W16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
+ CF_CACR_DBWE)
+
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
*/
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_SPLASH_SCREEN
-#ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
-#else /* MGT5100 */
-
-#define CONFIG_MII 1
-
-#endif
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
*/
#include <config_cmd_default.h>
-#if defined(CONFIG_MPC5200)
- #define CONFIG_CMD_PCI
-#endif
+#define CONFIG_CMD_PCI
#define CONFIG_CMD_BMP
#define CONFIG_CMD_EEPROM
#define CONFIG_BOOTCOMMAND "run flash_self"
-#if defined(CONFIG_MPC5200)
/*
* IPB Bus clocking configuration.
*/
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#endif
/*
* I2C configuration
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
-
-#if defined (CONFIG_MGT5100)
-# define CONFIG_BOARD_EARLY_INIT_R /* switch from CS_BOOT to CS0 */
-#endif
#if CONFIG_TOTAL5200_REV==1
# define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC08) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (ATMEL 24C04N)
*/
#define CONFIG_HARD_I2C 1 /* Hardware assisted I2C */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* I2C
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7f
#define CONFIG_I2C_MULTI_BUS
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
#undef CONFIG_WATCHDOG /* watchdog disabled */
* I2C
*/
#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*
/*
* Backward compatible definitions,
- * so we do not have to change cpu/mpc512x/fixed_sdram.c
+ * so we do not have to change arch/ppc/cpu/mpc512x/fixed_sdram.c
*/
#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
--- /dev/null
+/*
+ * Configuration settings for the Sentec Cobra Board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * configuration for ASTRO "Urmel" board.
+ * Originating from Cobra5272 configuration, messed up by
+ * Wolfgang Wegner <w.wegner@astro-kom.de>
+ * Please do not bother the original author with bug reports
+ * concerning this file.
+ */
+
+#ifndef _CONFIG_ASTRO_MCF5373L_H
+#define _CONFIG_ASTRO_MCF5373L_H
+
+/*
+ * set the card type to actually compile for; either of
+ * the possibilities listed below has to be used!
+ */
+#define CONFIG_ASTRO_V532 1
+
+#if CONFIG_ASTRO_V532
+#define ASTRO_ID 0xF8
+#elif CONFIG_ASTRO_V512
+#define ASTRO_ID 0xFA
+#elif CONFIG_ASTRO_TWIN7S2
+#define ASTRO_ID 0xF9
+#elif CONFIG_ASTRO_V912
+#define ASTRO_ID 0xFC
+#elif CONFIG_ASTRO_COFDMDUOS2
+#define ASTRO_ID 0xFB
+#else
+#error No card type defined!
+#endif
+
+/*
+ * Define processor
+ * possible values for Urmel board: only Coldfire M5373 processor supported
+ * (please do not change)
+ */
+
+/* it seems not clear yet which processor defines we should use */
+#define CONFIG_MCF537x /* define processor family */
+#define CONFIG_MCF532x /* define processor family */
+#define CONFIG_M5373 /* define processor type */
+#define CONFIG_ASTRO5373L /* define board type */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+/*
+ * CONFIG_MK_RAM defines if u-boot is loaded via BDM (or started from
+ * a different bootloader that has already performed RAM setup) or
+ * started directly from flash, which is the regular case for production
+ * boards.
+ */
+#ifdef CONFIG_MK_RAM
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_TEXT_BASE 0x40020000
+#define ENABLE_JFFS 0
+#else
+#define CONFIG_TEXT_BASE 0x00000000
+#define ENABLE_JFFS 1
+#endif
+
+/* Define which commmands should be available at u-boot command prompt */
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_XIMG
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#if ENABLE_JFFS
+#define CONFIG_CMD_JFFS2
+#endif
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SPEED 80000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x58000
+#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
+
+/*
+ * Defines processor clock - important for correct timings concerning serial
+ * interface etc.
+ * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
+ */
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_CLK 80000000
+#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3)
+#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
+
+#define CONFIG_SYS_CORE_SRAM_SIZE 0x8000
+#define CONFIG_SYS_CORE_SRAM 0x80000000
+
+#define CONFIG_SYS_UNIFY_CACHE
+
+/*
+ * Define baudrate for UART1 (console output, tftp, ...)
+ * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
+ * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected
+ * in u-boot command interface
+ */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT (2)
+#define CONFIG_SYS_UART2_ALT3_GPIO
+
+/*
+ * Watchdog configuration; Watchdog is disabled for running from RAM
+ * and set to highest possible value else. Beware there is no check
+ * in the watchdog code to validate the timeout value set here!
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */
+#endif
+
+/*
+ * Configuration for environment
+ * Environment is located in the last sector of the flash
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_ENV_OFFSET 0x1FF8000
+#define CONFIG_ENV_SECT_SIZE 0x8000
+#define CONFIG_ENV_IS_IN_FLASH 1
+#else
+/*
+ * environment in RAM - This is used to use a single PC-based application
+ * to load an image, load U-Boot, load an environment and then start U-Boot
+ * to execute the commands from the environment. Feedback is done via setting
+ * and reading memory locations.
+ */
+#define CONFIG_ENV_ADDR 0x40060000
+#define CONFIG_ENV_SECT_SIZE 0x8000
+#define CONFIG_ENV_IS_IN_FLASH 1
+#endif
+
+/* here we put our FPGA configuration... */
+#define CONFIG_MISC_INIT_R 1
+
+/* Define user parameters that have to be customized most likely */
+
+/* AUTOBOOT settings - booting images automatically by u-boot after power on */
+
+/*
+ * used for autoboot, delay in seconds u-boot will wait before starting
+ * defined (auto-)boot command, setting to -1 disables delay, setting to
+ * 0 will too prevent access to u-boot command interface: u-boot then has
+ * to be reflashed
+ * beware - watchdog is not serviced during autoboot delay time!
+ */
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_BOOTDELAY 1
+#else
+#define CONFIG_BOOTDELAY 1
+#endif
+
+/*
+ * The following settings will be contained in the environment block ; if you
+ * want to use a neutral environment all those settings can be manually set in
+ * u-boot: 'set' command
+ */
+
+#define _QUOTEME(x) #x
+#define QUOTEME(x) _QUOTEME(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loaderversion=11\0" \
+ "card_id="QUOTEME(ASTRO_ID)"\0" \
+ "alterafile=0\0" \
+ "xilinxfile=0\0" \
+ "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\
+ "fpga load 0 0x41000000 $filesize\0" \
+ "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\
+ "fpga load 1 0x41000000 $filesize\0" \
+ "env_default=1\0" \
+ "env_check=if test $env_default -eq 1;"\
+ " then setenv env_default 0;saveenv;fi\0"
+
+/*
+ * "update" is a non-standard command that has to be supplied
+ * by external update.c; This is not included in mainline because
+ * it needs non-blocking CFI routines.
+ */
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */
+#else
+#if CONFIG_ASTRO_V532
+#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\
+ "run xilinxload&&run alteraload&&bootm 0x80000;"\
+ "update;reset"
+#else
+#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\
+ "run xilinxload&&bootm 0x80000;update;reset"
+#endif
+#endif
+
+/* default bootargs that are considered during boot */
+#define CONFIG_BOOTARGS " console=ttyS2,115200 rootfstype=romfs"\
+ " loaderversion=$loaderversion"
+
+#define CONFIG_SYS_PROMPT "URMEL > "
+
+/* default RAM address for user programs */
+#define CONFIG_SYS_LOAD_ADDR 0x20000
+
+#define CONFIG_SYS_LONGHELP
+
+#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024
+#else
+#define CONFIG_SYS_CBSIZE 256
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_WAIT 1000
+
+/* End of user parameters to be customized */
+
+/* Defines memory range for test */
+
+#define CONFIG_SYS_MEMTEST_START 0x40020000
+#define CONFIG_SYS_MEMTEST_END 0x41ffffff
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/* Base register address */
+
+#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */
+
+/* System Conf. Reg. & System Protection Reg. */
+
+#define CONFIG_SYS_SCR 0x0003;
+#define CONFIG_SYS_SPR 0xffff;
+
+/*
+ * Definitions for initial stack pointer and data area (in internal SRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
+#define CONFIG_SYS_INIT_RAM_END 0x8000
+#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+
+/*
+ * Chipselect bank definitions
+ *
+ * CS0 - Flash 32MB (first 16MB)
+ * CS1 - Flash 32MB (second half)
+ * CS2 - FPGA
+ * CS3 - FPGA
+ * CS4 - unused
+ * CS5 - unused
+ */
+#define CONFIG_SYS_CS0_BASE 0
+#define CONFIG_SYS_CS0_MASK 0x00ff0001
+#define CONFIG_SYS_CS0_CTRL 0x00001fc0
+
+#define CONFIG_SYS_CS1_BASE 0x01000000
+#define CONFIG_SYS_CS1_MASK 0x00ff0001
+#define CONFIG_SYS_CS1_CTRL 0x00001fc0
+
+#define CONFIG_SYS_CS2_BASE 0x20000000
+#define CONFIG_SYS_CS2_MASK 0x00ff0001
+#define CONFIG_SYS_CS2_CTRL 0x0000fec0
+
+#define CONFIG_SYS_CS3_BASE 0x21000000
+#define CONFIG_SYS_CS3_MASK 0x00ff0001
+#define CONFIG_SYS_CS3_CTRL 0x0000fec0
+
+#define CONFIG_SYS_FLASH_BASE 0x00000000
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_BASE CONFIG_TEXT_BASE
+#else
+/* This is mainly used during relocation in start.S */
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+
+#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
+/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN (128 << 10)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
+ (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/* FLASH organization */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 259
+#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
+
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_SIZE 0x2000000
+#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_CFI_NONBLOCK 1
+
+#if ENABLE_JFFS
+/* JFFS Partition offset set */
+#define CONFIG_SYS_JFFS2_FIRST_BANK 0
+#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40
+#endif
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE 16
+
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
+ CF_CACR_DCM_P)
+
+#endif /* _CONFIG_ASTRO_MCF5373L_H */
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- cpu/blackfin/traps.o (.text .text.*); \
- cpu/blackfin/interrupt.o (.text .text.*); \
- cpu/blackfin/serial.o (.text .text.*); \
+ arch/blackfin/cpu/traps.o (.text .text.*); \
+ arch/blackfin/cpu/interrupt.o (.text .text.*); \
+ arch/blackfin/cpu/serial.o (.text .text.*); \
common/dlmalloc.o (.text .text.*); \
- lib_generic/crc32.o (.text .text.*); \
+ lib/crc32.o (.text .text.*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text .text.*);
#endif
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- cpu/blackfin/traps.o (.text .text.*); \
- cpu/blackfin/interrupt.o (.text .text.*); \
- cpu/blackfin/serial.o (.text .text.*); \
+ arch/blackfin/cpu/traps.o (.text .text.*); \
+ arch/blackfin/cpu/interrupt.o (.text .text.*); \
+ arch/blackfin/cpu/serial.o (.text .text.*); \
common/dlmalloc.o (.text .text.*); \
- lib_generic/crc32.o (.text .text.*); \
+ lib/crc32.o (.text .text.*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text .text.*);
#endif
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- cpu/blackfin/traps.o (.text .text.*); \
- cpu/blackfin/interrupt.o (.text .text.*); \
- cpu/blackfin/serial.o (.text .text.*); \
+ arch/blackfin/cpu/traps.o (.text .text.*); \
+ arch/blackfin/cpu/interrupt.o (.text .text.*); \
+ arch/blackfin/cpu/serial.o (.text .text.*); \
common/dlmalloc.o (.text .text.*); \
- lib_generic/crc32.o (.text .text.*); \
+ lib/crc32.o (.text .text.*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text .text.*);
#endif
#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
#endif
+/* These are for board tests */
+#if 0
+#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100"
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT \
+ "autoboot in %d seconds: press space to stop\n", bootdelay
+#define CONFIG_AUTOBOOT_STOP_STR " "
+#endif
+
/*
* Pull in common ADI header for remaining command/environment setup
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- cpu/blackfin/traps.o (.text .text.*); \
- cpu/blackfin/interrupt.o (.text .text.*); \
- cpu/blackfin/serial.o (.text .text.*); \
+ arch/blackfin/cpu/traps.o (.text .text.*); \
+ arch/blackfin/cpu/interrupt.o (.text .text.*); \
+ arch/blackfin/cpu/serial.o (.text .text.*); \
common/dlmalloc.o (.text .text.*); \
- lib_generic/crc32.o (.text .text.*); \
+ lib/crc32.o (.text .text.*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text .text.*);
#endif
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- cpu/blackfin/traps.o (.text .text.*); \
- cpu/blackfin/interrupt.o (.text .text.*); \
- cpu/blackfin/serial.o (.text .text.*); \
+ arch/blackfin/cpu/traps.o (.text .text.*); \
+ arch/blackfin/cpu/interrupt.o (.text .text.*); \
+ arch/blackfin/cpu/serial.o (.text .text.*); \
common/dlmalloc.o (.text .text.*); \
- lib_generic/crc32.o (.text .text.*); \
- lib_generic/zlib.o (.text .text.*); \
+ lib/crc32.o (.text .text.*); \
+ lib/zlib.o (.text .text.*); \
board/bf561-ezkit/bf561-ezkit.o (.text .text.*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text .text.*);
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- cpu/blackfin/traps.o (.text .text.*); \
- cpu/blackfin/interrupt.o (.text .text.*); \
- cpu/blackfin/serial.o (.text .text.*); \
+ arch/blackfin/cpu/traps.o (.text .text.*); \
+ arch/blackfin/cpu/interrupt.o (.text .text.*); \
+ arch/blackfin/cpu/serial.o (.text .text.*); \
common/dlmalloc.o (.text .text.*); \
- lib_generic/crc32.o (.text .text.*); \
+ lib/crc32.o (.text .text.*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text .text.*);
#endif
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- cpu/blackfin/traps.o (.text .text.*); \
- cpu/blackfin/interrupt.o (.text .text.*); \
- cpu/blackfin/serial.o (.text .text.*); \
+ arch/blackfin/cpu/traps.o (.text .text.*); \
+ arch/blackfin/cpu/interrupt.o (.text .text.*); \
+ arch/blackfin/cpu/serial.o (.text .text.*); \
common/dlmalloc.o (.text .text.*); \
- lib_generic/crc32.o (.text .text.*); \
+ lib/crc32.o (.text .text.*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text .text.*);
#endif
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-/* The next 2 lines are for use with DEV-BF5xx */
#define CONFIG_NET_MULTI
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x28000300
-/* The next 3 lines are for use with EXT-BF5xx-USB-ETH2 */
-/* #define CONFIG_DRIVER_SMC911X 1 */
-/* #define CONFIG_DRIVER_SMC911X_BASE 0x24080000 /! AMS1 */
-/* #define CONFIG_DRIVER_SMC911X_32_BIT 1 */
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_BASE 0x24008000 /* AMS1 */
+#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME cm-bf561
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:cf */
#define CONFIG_ENV_OFFSET 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
/*
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+ CF_CACR_DISD | CF_CACR_INVI | \
+ CF_CACR_CEIB | CF_CACR_DCM | \
+ CF_CACR_EUSP)
+
/*-----------------------------------------------------------------------
* Memory bank definitions
*
#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
#define CONFIG_NS8382X 1
#endif
-#endif
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
-#if defined(CONFIG_MPC5200)
-
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfd010000
#define CONFIG_SYS_NVRAM_SIZE 32*1024
* IPB Bus clocking configuration.
*/
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#endif
/*
* I2C configuration
*/
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
*
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
*
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
#define CONFIG_SYS_FLASH_BASE 0xfe000000
/*
- * The flash size is autoconfigured, but cpu/mpc5xxx/cpu_init.c needs this
+ * The flash size is autoconfigured, but arch/ppc/cpu/mpc5xxx/cpu_init.c needs this
* variable defined
*/
#define CONFIG_SYS_FLASH_SIZE 0x02000000
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- cpu/blackfin/traps.o (.text .text.*); \
- cpu/blackfin/interrupt.o (.text .text.*); \
- cpu/blackfin/serial.o (.text .text.*); \
+ arch/blackfin/cpu/traps.o (.text .text.*); \
+ arch/blackfin/cpu/interrupt.o (.text .text.*); \
+ arch/blackfin/cpu/serial.o (.text .text.*); \
common/dlmalloc.o (.text .text.*); \
- lib_generic/crc32.o (.text .text.*); \
- lib_generic/zlib.o (.text .text.*); \
+ lib/crc32.o (.text .text.*); \
+ lib/zlib.o (.text .text.*); \
board/ibf-dsp561/ibf-dsp561.o (.text .text.*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text .text.*);
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+ CF_CACR_DISD | CF_CACR_INVI | \
+ CF_CACR_CEIB | CF_CACR_DCM | \
+ CF_CACR_EUSP)
+
/* Port configuration */
#define CONFIG_SYS_FECI2C 0xF0
--- /dev/null
+/*
+ * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
+ *
+ * based on:
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMX27LITE_COMMON_CONFIG_H
+#define __IMX27LITE_COMMON_CONFIG_H
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_MX27
+#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Lowlevel configuration
+ */
+#define SDRAM_ESDCFG_REGISTER_VAL(cas) \
+ (ESDCFG_TRC(10) | \
+ ESDCFG_TRCD(3) | \
+ ESDCFG_TCAS(cas) | \
+ ESDCFG_TRRD(1) | \
+ ESDCFG_TRAS(5) | \
+ ESDCFG_TWR | \
+ ESDCFG_TMRD(2) | \
+ ESDCFG_TRP(2) | \
+ ESDCFG_TXP(3))
+
+#define SDRAM_ESDCTL_REGISTER_VAL \
+ (ESDCTL_PRCT(0) | \
+ ESDCTL_BL | \
+ ESDCTL_PWDT(0) | \
+ ESDCTL_SREFR(3) | \
+ ESDCTL_DSIZ_32 | \
+ ESDCTL_COL10 | \
+ ESDCTL_ROW13 | \
+ ESDCTL_SDE)
+
+#define SDRAM_ALL_VAL 0xf00
+
+#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */
+#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000
+
+#define MPCTL0_VAL 0x1ef15d5
+
+#define SPCTL0_VAL 0x043a1c09
+
+#define CSCR_VAL 0x33f08107
+
+#define PCDR0_VAL 0x120470c3
+#define PCDR1_VAL 0x03030303
+#define PCCR0_VAL 0xffffffff
+#define PCCR1_VAL 0xfffffffc
+
+#define AIPI1_PSR0_VAL 0x20040304
+#define AIPI1_PSR1_VAL 0xdffbfcfb
+#define AIPI2_PSR0_VAL 0x07ffc200
+#define AIPI2_PSR1_VAL 0xffffffff
+
+/*
+ * Memory Info
+ */
+/* malloc() len */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024)
+/* reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+/* memtest start address */
+#define CONFIG_SYS_MEMTEST_START 0xA0000000
+#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
+#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX27_UART1
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Flash & Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
+/* CS2 Base address */
+#define PHYS_FLASH_1 0xc0000000
+/* Flash Base for U-Boot */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \
+ CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR 0x1f
+#define CONFIG_MII
+#define CONFIG_NET_MULTI
+
+/*
+ * MTD
+ */
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_DEVICE
+
+/*
+ * NAND
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0xd8000000
+#define CONFIG_JFFS2_NAND
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXC_MMC
+#define CONFIG_DOS_PARTITION
+
+/*
+ * MTD partitions
+ */
+#define CONFIG_CMD_MTDPARTS
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+/* Print buffer sz */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY 5
+
+#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addmisc=setenv bootargs ${bootargs}\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "kernel_addr_r=a0800000\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "rootpath=/opt/eldk-4.2-arm/arm\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm\0" \
+ "bootcmd=run net_nfs\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};cp.b ${fileaddr} " \
+ xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ "upd=run load update\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+
+#endif /* __IMX27LITE_COMMON_CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
+/* include common defines/options for all imx27lite related boards */
+#include "imx27lite-common.h"
/*
* SoC Configuration
*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
-#define CONFIG_MX27
#define CONFIG_IMX27LITE
-#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
-#define CONFIG_SYS_HZ 1000
-
-#define CONFIG_DISPLAY_CPUINFO
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-/*
- * Lowlevel configuration
- */
-#define SDRAM_ESDCFG_REGISTER_VAL(cas) \
- (ESDCFG_TRC(10) | \
- ESDCFG_TRCD(3) | \
- ESDCFG_TCAS(cas) | \
- ESDCFG_TRRD(1) | \
- ESDCFG_TRAS(5) | \
- ESDCFG_TWR | \
- ESDCFG_TMRD(2) | \
- ESDCFG_TRP(2) | \
- ESDCFG_TXP(3))
-
-#define SDRAM_ESDCTL_REGISTER_VAL \
- (ESDCTL_PRCT(0) | \
- ESDCTL_BL | \
- ESDCTL_PWDT(0) | \
- ESDCTL_SREFR(3) | \
- ESDCTL_DSIZ_32 | \
- ESDCTL_COL10 | \
- ESDCTL_ROW13 | \
- ESDCTL_SDE)
-
-#define SDRAM_ALL_VAL 0xf00
-
-#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */
-#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000
-
-#define MPCTL0_VAL 0x1ef15d5
-
-#define SPCTL0_VAL 0x043a1c09
-
-#define CSCR_VAL 0x33f08107
-
-#define PCDR0_VAL 0x120470c3
-#define PCDR1_VAL 0x03030303
-#define PCCR0_VAL 0xffffffff
-#define PCCR1_VAL 0xfffffffc
-
-#define AIPI1_PSR0_VAL 0x20040304
-#define AIPI1_PSR1_VAL 0xdffbfcfb
-#define AIPI2_PSR0_VAL 0x07ffc200
-#define AIPI2_PSR1_VAL 0xffffffff
-
-/*
- * Memory Info
- */
-/* malloc() len */
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024)
-/* reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE 128
-/* memtest start address */
-#define CONFIG_SYS_MEMTEST_START 0xA0000000
-#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
-#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
-
-/*
- * Serial Driver info
- */
-#define CONFIG_MXC_UART
-#define CONFIG_SYS_MX27_UART1
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_HOSTNAME imx27
+#define CONFIG_BOARDNAME "LogicPD imx27lite\n"
/*
* Flash & Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-/* Use buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-/* Use hardware sector protection */
-#define CONFIG_SYS_FLASH_PROTECTION 1
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */
-/* end of flash */
#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000)
-/* CS2 Base address */
-#define PHYS_FLASH_1 0xc0000000
-/* Flash Base for U-Boot */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-/* Flash size 2MB */
#define PHYS_FLASH_SIZE 0x200000
-#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \
- CONFIG_SYS_FLASH_SECT_SZ)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
#define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*
- * Ethernet
- */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_MXC_PHYADDR 0x1f
-#define CONFIG_MII
-#define CONFIG_NET_MULTI
-
-/*
- * MTD
- */
-#define CONFIG_FLASH_CFI_MTD
-#define CONFIG_MTD_DEVICE
-
-/*
- * NAND
- */
-#define CONFIG_NAND_MXC
-#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0xd8000000
-#define CONFIG_JFFS2_NAND
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/*
* SD/MMC
*/
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MXC_MMC
#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
-#define CONFIG_DOS_PARTITION
/*
* MTD partitions
*/
-#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0"
#define MTDPARTS_DEFAULT \
"mtdparts=" \
"22m(rootfs)," \
"-(userfs)"
-/*
- * U-Boot general configuration
- */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-/* Print buffer sz */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-
-/*
- * U-Boot commands
- */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-
-#define CONFIG_BOOTDELAY 5
-
-#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define xstr(s) str(s)
-#define str(s) #s
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=ttymxc0,${baudrate}\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addmisc=setenv bootargs ${bootargs}\0" \
- "u-boot=imx27/u-boot.bin\0" \
- "kernel_addr_r=a0800000\0" \
- "hostname=imx27\0" \
- "bootfile=imx27/uImage\0" \
- "rootpath=/opt/eldk-4.2-arm/arm\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm\0" \
- "bootcmd=run net_nfs\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
- " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
- " +${filesize};cp.b ${fileaddr} " \
- xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
- "upd=run load update\0" \
-
#endif /* __CONFIG_H */
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
--- /dev/null
+/*
+ * U-boot - Configuration file for IP04 board (having BF532 processor)
+ *
+ * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com
+ *
+ * Copyright (c) 2005-2010 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __CONFIG_IP04_H__
+#define __CONFIG_IP04_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf532-0.5
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 10000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 40
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 3
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 10
+#define CONFIG_MEM_SIZE 64
+
+#define CONFIG_EBIU_SDRRC_VAL 0x408
+#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
+#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HOSTNAME IP04
+
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_NO_SROM
+#define CONFIG_DM9000_BASE 0x20100000
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_SYS_NO_FLASH /* we have only NAND */
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_WINBOND
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_PREBOOT "echo starting from spi flash"
+#define CONFIG_ENV_OFFSET 0x30000
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+
+
+/*
+ * NAND Settings
+ */
+#define CONFIG_NAND_PLAT
+#define CONFIG_SYS_NAND_BASE 0x20000000
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
+#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
+#define BFIN_NAND_READY PF10
+#define BFIN_NAND_WRITE(addr, cmd) \
+ do { \
+ bfin_write8(addr, cmd); \
+ SSYNC(); \
+ } while (0)
+
+#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
+#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
+#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY)
+#define NAND_PLAT_INIT() \
+ do { \
+ bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \
+ bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \
+ bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \
+ bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \
+ } while (0)
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_MISC_INIT_R /* needed for MAC address */
+#define CONFIG_UART_CONSOLE 0
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+/* Enable this if bootretry required; currently it's disabled */
+#define CONFIG_BOOT_RETRY_TIME -1
+#define CONFIG_BOOTCOMMAND "run nandboot"
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_440SPE 1 /* Specifc SPe support */
+#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
* SDRAM Controller DDR autocalibration values and takes a lot longer
* to run than Method_B.
* (See the Method_A and Method_B algorithm discription in the file:
- * cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
+ * arch/ppc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
* Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
*
* DDR Autocalibration Method_B is the default.
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* taken from the orignal Linkstation boot code
*
* Most of the low level configuration setttings are normally used
- * in cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
+ * in arch/ppc/cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
* Low level initialisation is done in board/linkstation/early_init.S
* The values below are included for reference purpose only
*/
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
--- /dev/null
+/*
+ * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
+ *
+ * based on:
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* include common defines/options for all imx27lite related boards */
+#include "imx27lite-common.h"
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MAGNESIUM
+#define CONFIG_HOSTNAME magnesium
+#define CONFIG_BOARDNAME "Projectiondesign magnesium\n"
+
+/*
+ * Flash & Environment
+ */
+#define CONFIG_SYS_FLASH_SECT_SZ 0x8000 /* 64KB sect size */
+#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x40000)
+#define PHYS_FLASH_SIZE 0x800000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* Env sector Size */
+
+/*
+ * NAND
+ */
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_MXC_MCI_REGS_BASE 0x10013000
+
+/*
+ * MTD partitions
+ */
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=" \
+ "physmap-flash.0:" \
+ "256k(U-Boot)," \
+ "7680k(user)," \
+ "128k(env1)," \
+ "128k(env2);" \
+ "mxc_nand.0:" \
+ "128k(IPL-SPL)," \
+ "4m(kernel)," \
+ "22m(rootfs)," \
+ "-(userfs)"
+
+#endif /* __CONFIG_H */
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#endif
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
-
#define CONFIG_MII
#if 0 /* test-only !!! */
#define CONFIG_NET_MULTI 1
#define CONFIG_NS8382X 1
#endif
-#else /* MPC5100 */
-
-#endif
-
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
-#if defined(CONFIG_MPC5200)
/*
* IPB Bus clocking configuration.
*/
#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
-#endif
/*
* I2C configuration
*/
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
+++ /dev/null
-/*
- * ML300.h: ML300 specific config options
- *
- * http://www.xilinx.com/ml300
- *
- * Derived from : ML2.h
- *
- * Author: Xilinx, Inc.
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- *
- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
- * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
- * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
- * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
- * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR
- * OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
- * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
- * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
- * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
- * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
- * FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * Xilinx products are not intended for use in life support appliances,
- * devices, or systems. Use in such applications is expressly prohibited.
- *
- *
- * (c) Copyright 2002 Xilinx Inc.
- * All rights reserved.
- *
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* #define DEBUG */
-/* #define ET_DEBUG 1 */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_XILINX_405 1
-#define CONFIG_XILINX_ML300 1 /* ...on a Xilinx ML300 board */
-
-#define CONFIG_SYSTEMACE 1
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_SYS_SYSTEMACE_BASE XPAR_OPB_SYSACE_0_BASEADDR
-#define CONFIG_SYS_SYSTEMACE_WIDTH XPAR_XSYSACE_MEM_WIDTH
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* environment is in EEPROM */
-
-/* following are used only if env is in EEPROM */
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR XPAR_PERSISTENT_0_IIC_0_EEPROMADDR
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_ENV_OFFSET XPAR_PERSISTENT_0_IIC_0_BASEADDR
-#define CONFIG_MISC_INIT_R 1 /* used to call out convert_env() */
-#define CONFIG_ENV_OVERWRITE 1 /* allow users to update ethaddr and serial# */
-#endif
-
-#include "../board/xilinx/ml300/xparameters.h"
-
-#define CONFIG_SYS_NO_FLASH 1 /* no flash */
-#define CONFIG_ENV_SIZE XPAR_PERSISTENT_0_IIC_0_HIGHADDR - XPAR_PERSISTENT_0_IIC_0_BASEADDR + 1
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-
-#define CONFIG_BOOTARGS "console=ttyS0,9600 ip=off " \
- "root=/dev/xsysace/disc0/part3 rw"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_NET
-
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_IMLS
-
-
-/* #define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ */
-/* 300000000 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_DUART_CHAN 0
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550 1
-#define CONFIG_SYS_INIT_CHAN1 1
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_BASE 0x04000000
-#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#endif /* __CONFIG_H */
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+#define CONFIG_SYS_DDR_CLKSEL 0
+#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
+
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
* I2C
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_BOOTCOMMAND "run flash_self"
-#if defined(CONFIG_MPC5200)
/*
* IPB Bus clocking configuration.
*/
*/
#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
-#endif
/*
* I2C configuration
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \
at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \
}
+#define I2C_SOFT_DECLARATIONS
/* Configure data pin as output */
#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTB, 4, 0)
/* Configure data pin as input */
* Command line configuration.
*/
#include <config_cmd_default.h>
-#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#endif
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#endif
-#endif
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
-#ifdef CONFIG_MPC5200
#define CONFIG_CMD_PCI
-#endif
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
-#if defined(CONFIG_MPC5200)
/*
* IPB Bus clocking configuration.
*/
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#endif
/*
* I2C configuration
*/
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_AT91_LEGACY
-
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
/* clocks */
/* CKGR_MOR - enable main osc. */
#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
+ (AT91_PMC_MOR_MOSCEN | \
(255 << 8)) /* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
+ (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
+ AT91_PMC_PLLXR_OUT(3) | \
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
+ (AT91_PMC_MCKR_CSS_SLOW | \
+ AT91_PMC_MCKR_PRES_1 | \
+ AT91_PMC_MCKR_MDIV_2 | \
+ AT91_PMC_MCKR_PLLADIV_1)
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
+ (AT91_PMC_MCKR_CSS_PLLA | \
+ AT91_PMC_MCKR_PRES_1 | \
+ AT91_PMC_MCKR_MDIV_2 | \
+ AT91_PMC_MCKR_PLLADIV_1)
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
#define CONFIG_SYS_MATRIX_EBICSA_VAL \
- (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC)
+ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
/* SDRAM */
/* SDRAMC_MR Mode register */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
- AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
+ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
+ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
- AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
+ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
- AT91_SMC_DBW_16 | \
- AT91_SMC_TDFMODE | \
- AT91_SMC_TDF_(6))
+ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
+ AT91_SMC_MODE_DBW_16 | \
+ AT91_SMC_MODE_TDF | \
+ AT91_SMC_MODE_TDF_CYCLE(6))
/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
- AT91_RSTC_PROCRST | \
- AT91_RSTC_RSTTYP_WAKEUP | \
- AT91_RSTC_RSTTYP_WATCHDOG)
+ AT91_RSTC_CR_PROCRST | \
+ AT91_RSTC_MR_ERSTL(1) | \
+ AT91_RSTC_MR_ERSTL(2))
/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
- AT91_WDT_WDV | \
- AT91_WDT_WDDIS | \
- AT91_WDT_WDD)
+ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
+ AT91_WDT_MR_WDV(0xfff) | \
+ AT91_WDT_MR_WDDIS | \
+ AT91_WDT_MR_WDD(0xfff))
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
/* LED */
#define CONFIG_AT91_LED
-#define CONFIG_RED_LED AT91_PIN_PC12
-#define CONFIG_GREEN_LED AT91_PIN_PC13
-#define CONFIG_YELLOW_LED AT91_PIN_PC15
+#define CONFIG_RED_LED AT91_PIO_PORTC, 12
+#define CONFIG_GREEN_LED AT91_PIO_PORTC, 13
+#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 15
#define CONFIG_BOOTDELAY 3
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 16
/* NOR flash */
#define CONFIG_SYS_FLASH_CFI 1
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory (OCM) for temperary stack until sdram is tested */
-/* see ./cpu/ppc4xx/start.S */
+/* see ./arch/ppc/cpu/ppc4xx/start.S */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
* Taken from PPCBoot board/icecube/icecube.h
*/
-/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
+/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
#define CONFIG_SYS_EBC_PB0AP 0x04002480
/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
*
* Taken in part from PPCBoot board/icecube/icecube.h
*/
-/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
+/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
#define CONFIG_SYS_GPIO0_OSRH 0x55555550
#define CONFIG_SYS_GPIO0_OSRL 0x00000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
*/
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define I2C_INIT
#define I2C_ACTIVE 0
* - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR
* - Stackpointer will be located to
* (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF)
- * in cpu/ppc4xx/start.S
+ * in arch/ppc/cpu/ppc4xx/start.S
*/
#undef CONFIG_SYS_INIT_DCACHE_CS
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/* ################################################################################### */
-/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */
+/* These defines will be used in arch/ppc/cpu/ppc4xx/cpu_init.c to setup external chip selects */
/* They are currently undefined cause they are initiaized in board/solidcard3/init.S */
/* This chip select accesses the boot device */
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
/*
* Various low-level settings
*/
-#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-#endif
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- cpu/blackfin/traps.o (.text .text.*); \
- cpu/blackfin/interrupt.o (.text .text.*); \
- cpu/blackfin/serial.o (.text .text.*); \
+ arch/blackfin/cpu/traps.o (.text .text.*); \
+ arch/blackfin/cpu/interrupt.o (.text .text.*); \
+ arch/blackfin/cpu/serial.o (.text .text.*); \
common/dlmalloc.o (.text .text.*); \
- lib_generic/crc32.o (.text .text.*); \
+ lib/crc32.o (.text .text.*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text .text.*);
#endif
#define CONFIG_BOOTCOMMAND "run net_nfs"
-#if defined(CONFIG_MPC5200)
/*
* IPB Bus clocking configuration.
*/
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#endif
/*
* I2C configuration
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_440SPE 1 /* Specifc SPe support */
+#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define EXTCLK_33_33 33333333
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size);
+void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
+void fdt_del_node_and_alias(void *blob, const char *alias);
+
#endif /* ifdef CONFIG_OF_LIBFDT */
#endif /* ifndef __FDT_SUPPORT_H */
* FSL SD/MMC Defines
*-------------------------------------------------------------------
*
- * Copyright 2007-2008, Freescale Semiconductor, Inc
+ * Copyright 2007-2008,2010 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
#define SYSCTL_PEREN 0x00000004
#define SYSCTL_HCKEN 0x00000002
#define SYSCTL_IPGEN 0x00000001
+#define SYSCTL_RSTA 0x01000000
#define IRQSTAT 0x0002e030
#define IRQSTAT_DMAE (0x10000000)
#define WML 0x2e044
#define WML_WRITE 0x00010000
+#define WML_RD_WML_MASK 0xff
+#define WML_WR_WML_MASK 0xff0000
#define BLKATTR 0x2e004
#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
struct fsl_esdhc_cfg {
u32 esdhc_base;
u32 no_snoop;
- u32 clk_enable;
};
/* Select the correct accessors depending on endianess */
struct _mux_device *next;
} I2C_MUX_DEVICE;
-int i2c_mux_add_device(I2C_MUX_DEVICE *dev);
-
I2C_MUX_DEVICE *i2c_mux_search_device(int id);
I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);
int i2x_mux_select_mux(int bus);
extern int mtdparts_init(void);
extern int find_dev_and_part(const char *id, struct mtd_device **dev,
u8 *part_num, struct part_info **part);
+extern struct mtd_device *device_find(u8 type, u8 num);
#endif /* load_kernel_h */
#endif /* __PPC__ */
#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\
- defined (__microblaze__)
+ defined (__microblaze__) || defined (__nios2__)
struct stat {
unsigned short st_dev;
#ifndef __LZMADEC_H__FAKE__
#define __LZMADEC_H__FAKE__
-#include "../../lib_generic/lzma/LzmaDec.h"
+#include "../../lib/lzma/LzmaDec.h"
#endif
#ifndef __LZMATOOLS_H__FAKE__
#define __LZMATOOLS_H__FAKE__
-#include "../../lib_generic/lzma/LzmaTools.h"
+#include "../../lib/lzma/LzmaTools.h"
#endif
*/
#define Byte LZByte
-#include "../../lib_generic/lzma/Types.h"
+#include "../../lib/lzma/Types.h"
#endif
/*
* include/asm-ppc/mpc5xxx.h
*
- * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
+ * Prototypes, etc. for the Motorola MPC5xxx
* embedded cpu chips
*
* 2003 (c) MontaVista, Software, Inc.
#include <asm/types.h>
/* Processor name */
-#if defined(CONFIG_MPC5200)
#define CPU_ID_STR "MPC5200"
-#elif defined(CONFIG_MGT5100)
-#define CPU_ID_STR "MGT5100"
-#endif
/* Exception offsets (PowerPC standard) */
#define EXC_OFF_SYS_RESET 0x0100
#define _START_OFFSET EXC_OFF_SYS_RESET
/* useful macros for manipulating CSx_START/STOP */
-#if defined(CONFIG_MGT5100)
-#define START_REG(start) ((start) >> 15)
-#define STOP_REG(start, size) (((start) + (size) - 1) >> 15)
-#elif defined(CONFIG_MPC5200)
#define START_REG(start) ((start) >> 16)
#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
-#endif
/* Internal memory map */
#define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050)
#define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054)
-#if defined(CONFIG_MGT5100)
-#define MPC5XXX_SDRAM_START (CONFIG_SYS_MBAR + 0x0034)
-#define MPC5XXX_SDRAM_STOP (CONFIG_SYS_MBAR + 0x0038)
-#define MPC5XXX_PCI1_START (CONFIG_SYS_MBAR + 0x003c)
-#define MPC5XXX_PCI1_STOP (CONFIG_SYS_MBAR + 0x0040)
-#define MPC5XXX_PCI2_START (CONFIG_SYS_MBAR + 0x0044)
-#define MPC5XXX_PCI2_STOP (CONFIG_SYS_MBAR + 0x0048)
-#elif defined(CONFIG_MPC5200)
#define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058)
#define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c)
#define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060)
#define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064)
#define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034)
#define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038)
-#endif
#define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100)
#define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200)
#define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200)
#define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00)
-#if defined(CONFIG_MGT5100)
-#define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000)
-#define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2400)
-#define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2800)
-#elif defined(CONFIG_MPC5200)
#define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000)
#define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200)
#define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400)
#define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600)
#define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800)
#define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00)
-#endif
#define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000)
#define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00)
#define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00)
#define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40)
-#if defined(CONFIG_MGT5100)
-#define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x4000)
-#define MPC5XXX_SRAM_SIZE (8*1024)
-#elif defined(CONFIG_MPC5200)
#define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000)
#define MPC5XXX_SRAM_SIZE (16*1024)
-#endif
/* SDRAM Controller */
#define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000)
#define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004)
#define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008)
#define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c)
-#if defined(CONFIG_MGT5100)
-#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010)
-#endif
#define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090)
/* Clock Distribution Module */
#define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG
#define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018)
#define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c)
-#if defined(CONFIG_MPC5200)
#define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020)
#define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024)
#define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028)
#define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c)
-#endif
-#if defined(CONFIG_MPC5200)
/* XLB Arbiter registers */
#define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40)
#define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64)
#define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68)
-#endif
/* GPIO registers */
#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
-#if defined(CONFIG_MGT5100)
-#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
-#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
-#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
-#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
-#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
-#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
-#elif defined(CONFIG_MPC5200)
#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
-#endif
/* Interrupt Controller registers */
#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
volatile u32 cs4_stop;
volatile u32 cs5_start; /* 0x002c */
volatile u32 cs5_stop;
-#if defined(CONFIG_MGT5100)
- volatile u32 sdram_start; /* 0x0034 */
- volatile u32 sdram_stop; /* 0x0038 */
- volatile u32 pci1_start; /* 0x003c */
- volatile u32 pci1_stop; /* 0x0040 */
- volatile u32 pci2_start; /* 0x0044 */
- volatile u32 pci2_stop; /* 0x0048 */
-#elif defined(CONFIG_MPC5200)
volatile u32 sdram0; /* 0x0034 */
volatile u32 sdram1; /* 0x0038 */
volatile u32 dummy1[4]; /* 0x003c */
-#endif
volatile u32 boot_start; /* 0x004c */
volatile u32 boot_stop;
-#if defined(CONFIG_MGT5100)
- volatile u32 addecr; /* 0x0054 */
-#elif defined(CONFIG_MPC5200)
volatile u32 ipbi_ws_ctrl; /* 0x0054 */
-#endif
-#if defined(CONFIG_MPC5200)
volatile u32 cs6_start; /* 0x0058 */
volatile u32 cs6_stop;
volatile u32 cs7_start; /* 0x0060 */
volatile u32 cs7_stop;
-#endif
};
/* Clock distribution module */
volatile u32 ctrl;
volatile u32 config1;
volatile u32 config2;
-#if defined(CONFIG_MGT5100)
- volatile u32 xlbsel;
- volatile u32 dummy[31];
-#else
volatile u32 dummy[32];
-#endif
volatile u32 sdelay;
};
volatile u32 cs5_cfg;
volatile u32 cs_ctrl;
volatile u32 cs_status;
-#if defined(CONFIG_MPC5200)
volatile u32 cs6_cfg;
volatile u32 cs7_cfg;
volatile u32 cs_burst;
volatile u32 cs_deadcycle;
-#endif
};
return l2cr_val;
}
+void setup_ddr_bat(phys_addr_t dram_size);
+
#endif /* _ASMLANGUAGE */
#endif /* __MPC86xx_H__ */
--- /dev/null
+#ifndef _NODE_INFO
+#define _NODE_INFO
+
+/*
+ * Info we use to search for a flash node in DTB.
+ */
+struct node_info {
+ const char *compat; /* compatible string */
+ int type; /* mtd flash type */
+};
+#endif
#define POST_FAIL_SAVE 0x80
+#define POST_BEFORE 1
+#define POST_AFTER 0
+#define POST_PASSED 1
+#define POST_FAILED 0
+
#ifndef __ASSEMBLY__
struct post_test {
#define CPR0_SPCID 0x0120
#define CPR0_ICFG 0x0140
+/* 440EPX boot strap options */
+#define BOOT_STRAP_OPTION_A 0x00000000
+#define BOOT_STRAP_OPTION_B 0x00000001
+#define BOOT_STRAP_OPTION_D 0x00000003
+#define BOOT_STRAP_OPTION_E 0x00000004
+
/* 440gx sdr register definations */
#define SDR0_SDSTP0 0x0020 /* */
#define SDR0_SDSTP1 0x0021 /* */
Xilinx_done_fn done;
Xilinx_wr_fn wr;
Xilinx_post_fn post;
+ Xilinx_bwr_fn bwr; /* block write function */
} Xilinx_Spartan3_Slave_Serial_fns;
/* Device Image Sizes
#ifndef _UBOOT_CRC_H
#define _UBOOT_CRC_H
-/* lib_generic/crc32.c */
+/* lib/crc32.c */
uint32_t crc32 (uint32_t, const unsigned char *, uint);
uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint);
uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint);
typedef int (*Xilinx_abort_fn)( int cookie );
typedef int (*Xilinx_pre_fn)( int cookie );
typedef int (*Xilinx_post_fn)( int cookie );
+typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie );
#endif /* _XILINX_H_ */
mkdir -p ${OBJTREE}/include2
cd ${OBJTREE}/include2
rm -f asm
- ln -s ${SRCTREE}/include/asm-$2 asm
- LNPREFIX="../../include2/asm/"
+ ln -s ${SRCTREE}/arch/$2/include/asm asm
+ LNPREFIX=${SRCTREE}/arch/$2/include/asm/
cd ../include
- rm -rf asm-$2
rm -f asm
- mkdir asm-$2
- ln -s asm-$2 asm
+ ln -s ${SRCTREE}/arch/$2/include/asm asm
else
cd ./include
rm -f asm
- ln -s asm-$2 asm
+ ln -s ../arch/$2/include/asm asm
fi
-rm -f asm-$2/arch
+rm -f asm/arch
if [ -z "$6" -o "$6" = "NULL" ] ; then
- ln -s ${LNPREFIX}arch-$3 asm-$2/arch
+ ln -s ${LNPREFIX}arch-$3 asm/arch
else
- ln -s ${LNPREFIX}arch-$6 asm-$2/arch
+ ln -s ${LNPREFIX}arch-$6 asm/arch
fi
if [ "$2" = "arm" ] ; then
- rm -f asm-$2/proc
- ln -s ${LNPREFIX}proc-armv asm-$2/proc
+ rm -f asm/proc
+ ln -s ${LNPREFIX}proc-armv asm/proc
fi
#
# from cpu directory
$(obj)cache.S:
@rm -f $(obj)cache.S
- ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/cache.S $(obj)cache.S
$(obj)gpio.c:
@rm -f $(obj)gpio.c
- ln -s $(SRCTREE)/cpu/ppc4xx/gpio.c $(obj)gpio.c
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/gpio.c $(obj)gpio.c
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)memory.c:
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)init.S:
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)init.S:
# from cpu directory
$(obj)44x_spd_ddr2.c: $(obj)ecc.h
@rm -f $(obj)44x_spd_ddr2.c
- ln -s $(SRCTREE)/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c
$(obj)cache.S:
@rm -f $(obj)cache.S
- ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/cache.S $(obj)cache.S
$(obj)ecc.h:
@rm -f $(obj)ecc.h
- ln -s $(SRCTREE)/cpu/ppc4xx/ecc.h $(obj)ecc.h
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/ecc.h $(obj)ecc.h
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
# from nand_spl directory
$(obj)nand_boot.c:
# from cpu directory
$(obj)denali_data_eye.c:
@rm -f $(obj)denali_data_eye.c
- ln -s $(SRCTREE)/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)init.S:
# create symbolic links for common files
$(obj)start.S:
- ln -sf $(SRCTREE)/cpu/mpc83xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/start.S $(obj)start.S
$(obj)nand_boot_fsl_elbc.c:
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
$(obj)nand_init.c:
- ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
$(obj)cache.c:
- ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c
$(obj)time.c:
- ln -sf $(SRCTREE)/lib_ppc/time.c $(obj)time.c
+ ln -sf $(SRCTREE)/arch/ppc/lib/time.c $(obj)time.c
$(obj)ticks.S:
- ln -sf $(SRCTREE)/lib_ppc/ticks.S $(obj)ticks.S
+ ln -sf $(SRCTREE)/arch/ppc/lib/ticks.S $(obj)ticks.S
#########################################################################
# create symbolic links for common files
$(obj)start.S:
- ln -sf $(SRCTREE)/cpu/mpc83xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/start.S $(obj)start.S
$(obj)nand_boot_fsl_elbc.c:
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
$(obj)nand_init.c:
- ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
$(obj)cache.c:
- ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c
$(obj)time.c:
- ln -sf $(SRCTREE)/lib_ppc/time.c $(obj)time.c
+ ln -sf $(SRCTREE)/arch/ppc/lib/time.c $(obj)time.c
$(obj)ticks.S:
- ln -sf $(SRCTREE)/lib_ppc/ticks.S $(obj)ticks.S
+ ln -sf $(SRCTREE)/arch/ppc/lib/ticks.S $(obj)ticks.S
#########################################################################
include $(TOPDIR)/config.mk
-LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds
+LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
$(obj)cache.c:
@rm -f $(obj)cache.c
- ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c
$(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
$(obj)cpu_init_nand.c:
@rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
$(obj)fixed_ivor.S:
@rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
$(obj)start.S: $(obj)fixed_ivor.S
@rm -f $(obj)start.S
- ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/start.S $(obj)start.S
$(obj)tlb.c:
@rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/tlb.c $(obj)tlb.c
$(obj)tlb_table.c:
@rm -f $(obj)tlb_table.c
include $(TOPDIR)/config.mk
-LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds
+LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
$(obj)cache.c:
@rm -f $(obj)cache.c
- ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c
$(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
$(obj)cpu_init_nand.c:
@rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
$(obj)fixed_ivor.S:
@rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
$(obj)start.S: $(obj)fixed_ivor.S
@rm -f $(obj)start.S
- ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/start.S $(obj)start.S
$(obj)tlb.c:
@rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/tlb.c $(obj)tlb.c
$(obj)tlb_table.c:
@rm -f $(obj)tlb_table.c
*/
#include <common.h>
#include <mpc85xx.h>
-#include <asm-ppc/io.h>
+#include <asm/io.h>
#include <ns16550.h>
#include <nand.h>
#include <asm/mmu.h>
COBJS = nand_boot_fsl_nfc.o
SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
-SRCS += $(SRCTREE)/cpu/arm1136/start.S
+SRCS += $(SRCTREE)/arch/arm/cpu/arm1136/start.S
SRCS += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
#########################################################################
-$(obj)%.o: $(SRCTREE)/cpu/arm1136/%.S
+$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm1136/%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(SRCTREE)/board/freescale/mx31pdk/%.S
include $(TOPDIR)/config.mk
-LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds
+LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
$(obj)cache.c:
@rm -f $(obj)cache.c
- ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c
$(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
$(obj)cpu_init_nand.c:
@rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
$(obj)fixed_ivor.S:
@rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
$(obj)start.S: $(obj)fixed_ivor.S
@rm -f $(obj)start.S
- ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/start.S $(obj)start.S
$(obj)tlb.c:
@rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/tlb.c $(obj)tlb.c
$(obj)tlb_table.c:
@rm -f $(obj)tlb_table.c
*/
#include <common.h>
#include <mpc85xx.h>
-#include <asm-ppc/io.h>
+#include <asm/io.h>
#include <ns16550.h>
#include <nand.h>
#include <asm/mmu.h>
COBJS = nand_boot_fsl_nfc.o
SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
-SRCS += $(SRCTREE)/cpu/arm926ejs/start.S
+SRCS += $(SRCTREE)/arch/arm/cpu/arm926ejs/start.S
SRCS += $(SRCTREE)/board/karo/tx25/lowlevel_init.S
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
#########################################################################
-$(obj)%.o: $(SRCTREE)/cpu/arm926ejs/%.S
+$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm926ejs/%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(SRCTREE)/board/karo/tx25/%.S
# from cpu directory
$(obj)start.S:
@rm -f $@
- @ln -s $(TOPDIR)/cpu/arm1176/start.S $@
+ @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/start.S $@
# from SoC directory
$(obj)cpu_init.S:
@rm -f $@
- @ln -s $(TOPDIR)/cpu/arm1176/s3c64xx/cpu_init.S $@
+ @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S $@
# from board directory
$(obj)lowlevel_init.S:
$(obj)start.S:
@rm -f $@
- ln -s $(SRCTREE)/cpu/mpc83xx/start.S $@
+ ln -s $(SRCTREE)/arch/ppc/cpu/mpc83xx/start.S $@
$(obj)nand_boot_fsl_elbc.c:
@rm -f $@
$(obj)nand_init.c:
@rm -f $@
- ln -s $(SRCTREE)/cpu/mpc83xx/nand_init.c $@
+ ln -s $(SRCTREE)/arch/ppc/cpu/mpc83xx/nand_init.c $@
$(obj)cache.c:
@rm -f $@
- ln -s $(SRCTREE)/lib_ppc/cache.c $@
+ ln -s $(SRCTREE)/arch/ppc/lib/cache.c $@
$(obj)time.c:
@rm -f $@
- ln -s $(SRCTREE)/lib_ppc/time.c $@
+ ln -s $(SRCTREE)/arch/ppc/lib/time.c $@
$(obj)ticks.S:
@rm -f $@
- ln -s $(SRCTREE)/lib_ppc/ticks.S $@
+ ln -s $(SRCTREE)/arch/ppc/lib/ticks.S $@
#########################################################################
#include <common.h>
#include <nand.h>
#ifdef CONFIG_MX31
-#include <asm-arm/arch/mx31-regs.h>
+#include <asm/arch/mx31-regs.h>
#else
-#include <asm-arm/arch/imx-regs.h>
+#include <asm/arch/imx-regs.h>
#endif
#include <asm/io.h>
#include <fsl_nfc.h>
# from cpu directory
$(obj)start.S:
@rm -f $@
- ln -s $(SRCTREE)/cpu/$(CPU)/start.S $@
+ ln -s $(SRCTREE)/$(CPUDIR)/start.S $@
# from onenand_ipl directory
$(obj)onenand_ipl.h:
/* Additional Special-Purpose Registers.
* The values must match the initialization
- * values from cpu/ppc4xx/start.S
+ * values from arch/ppc/cpu/ppc4xx/start.S
*/
{0x30, "PID", 0x00000000, 0x00000000},
{0x3a, "CSRR0", 0x00000000, 0x00000000},
}
}
+void __show_post_progress (unsigned int test_num, int before, int result)
+{
+}
+void show_post_progress (unsigned int, int, int)
+ __attribute__((weak, alias("__show_post_progress")));
+
static int post_run_single (struct post_test *test,
int test_flags, int flags, unsigned int i)
{
if (test_flags & POST_PREREL)
post_log_mark_start ( test->testid );
else
- post_log ("POST %s ", test->cmd);
+ post_log ("POST %s ", test->cmd);
}
+ show_post_progress(i, POST_BEFORE, POST_FAILED);
+
if (test_flags & POST_PREREL) {
- if ((*test->test) (flags) == 0)
+ if ((*test->test) (flags) == 0) {
post_log_mark_succ ( test->testid );
+ show_post_progress(i, POST_AFTER, POST_PASSED);
+ }
else {
+ show_post_progress(i, POST_AFTER, POST_FAILED);
if (test_flags & POST_CRITICAL)
gd->flags |= GD_FLG_POSTFAIL;
if (test_flags & POST_STOP)
if ((*test->test) (flags) != 0) {
post_log ("FAILED\n");
show_boot_progress (-32);
+ show_post_progress(i, POST_AFTER, POST_FAILED);
if (test_flags & POST_CRITICAL)
gd->flags |= GD_FLG_POSTFAIL;
if (test_flags & POST_STOP)
}
else
post_log ("PASSED\n");
+ show_post_progress(i, POST_AFTER, POST_PASSED);
}
if ((test_flags & POST_REBOOT) && !(flags & POST_MANUAL)) {
# Source files which exist outside the tools directory
EXT_OBJ_FILES-y += common/env_embedded.o
EXT_OBJ_FILES-y += common/image.o
-EXT_OBJ_FILES-y += lib_generic/crc32.o
-EXT_OBJ_FILES-y += lib_generic/md5.o
-EXT_OBJ_FILES-y += lib_generic/sha1.o
+EXT_OBJ_FILES-y += lib/crc32.o
+EXT_OBJ_FILES-y += lib/md5.o
+EXT_OBJ_FILES-y += lib/sha1.o
# Source files located in the tools directory
OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
# now $(obj) is defined
HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
HOSTSRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c))
-HOSTSRCS += $(addprefix $(SRCTREE)/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c))
+HOSTSRCS += $(addprefix $(SRCTREE)/lib/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c))
BINS := $(addprefix $(obj),$(sort $(BIN_FILES-y)))
LIBFDT_OBJS := $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y))
HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \
-idirafter $(OBJTREE)/include2 \
-idirafter $(OBJTREE)/include \
- -I $(SRCTREE)/libfdt \
+ -I $(SRCTREE)/lib/libfdt \
-I $(SRCTREE)/tools \
-DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC \
-D__KERNEL_STRICT_NAMES
$(obj)%.o: $(SRCTREE)/common/%.c
$(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-$(obj)%.o: $(SRCTREE)/lib_generic/%.c
+$(obj)%.o: $(SRCTREE)/lib/%.c
$(HOSTCC) -g $(HOSTCFLAGS) -c -o $@ $<
-$(obj)%.o: $(SRCTREE)/libfdt/%.c
+$(obj)%.o: $(SRCTREE)/lib/libfdt/%.c
$(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
subdirs:
rm -f $(obj)fw_printenv $(obj)crc32.c
$(obj)crc32.c:
- ln -s $(src)../../lib_generic/crc32.c $(obj)crc32.c
+ ln -s $(src)../../lib/crc32.c $(obj)crc32.c
#########################################################################
BIN_FILES-y += imls
# Source files which exist outside the tools/imls directory
-EXT_OBJ_FILES-y += lib_generic/crc32.o
-EXT_OBJ_FILES-y += lib_generic/md5.o
-EXT_OBJ_FILES-y += lib_generic/sha1.o
+EXT_OBJ_FILES-y += lib/crc32.o
+EXT_OBJ_FILES-y += lib/md5.o
+EXT_OBJ_FILES-y += lib/sha1.o
EXT_OBJ_FILES-y += common/image.o
# Source files located in the tools/imls directory
# now $(obj) is defined
SRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
SRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c))
-SRCS += $(addprefix $(SRCTREE)/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c))
+SRCS += $(addprefix $(SRCTREE)/lib/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c))
BINS := $(addprefix $(obj),$(sort $(BIN_FILES-y)))
LIBFDT_OBJS := $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y))
HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \
-idirafter $(OBJTREE)/include2 \
-idirafter $(OBJTREE)/include \
- -I $(SRCTREE)/libfdt \
+ -I $(SRCTREE)/lib/libfdt \
-I $(SRCTREE)/tools \
-DUSE_HOSTCC -D__KERNEL_STRICT_NAMES
$(obj)%.o: $(SRCTREE)/common/%.c
$(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
-$(obj)%.o: $(SRCTREE)/lib_generic/%.c
+$(obj)%.o: $(SRCTREE)/lib/%.c
$(CC) -g $(HOSTCFLAGS) -c -o $@ $<
-$(obj)%.o: $(SRCTREE)/libfdt/%.c
+$(obj)%.o: $(SRCTREE)/lib/libfdt/%.c
$(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
clean:
.type = IH_TYPE_KERNEL,
.comp = IH_COMP_GZIP,
.dtc = MKIMAGE_DEFAULT_DTC_OPTIONS,
+ .imagename = "",
};
/*
{
int ifd = -1;
struct stat sbuf;
- unsigned char *ptr;
+ char *ptr;
int retval = 0;
struct image_type_params *tparams = NULL;
case 'a':
if (--argc <= 0)
usage ();
- params.addr = strtoul (*++argv,
- (char **)&ptr, 16);
+ params.addr = strtoul (*++argv, &ptr, 16);
if (*ptr) {
fprintf (stderr,
"%s: invalid load address %s\n",
case 'e':
if (--argc <= 0)
usage ();
- params.ep = strtoul (*++argv,
- (char **)&ptr, 16);
+ params.ep = strtoul (*++argv, &ptr, 16);
if (*ptr) {
fprintf (stderr,
"%s: invalid entry point %s\n",
projects / karo-tx-uboot.git / commitdiff