arch/x86/kernel/cpu/perf_event_intel_ds.c

   1 #include <linux/bitops.h>
   2 #include <linux/types.h>
   3 #include <linux/slab.h>
   4
   5 #include <asm/perf_event.h>
   6 #include <asm/insn.h>
   7
   8 #include "perf_event.h"
   9
  10 /* The size of a BTS record in bytes: */
  11 #define BTS_RECORD_SIZE         24
  12
  13 #define BTS_BUFFER_SIZE         (PAGE_SIZE << 4)
  14 #define PEBS_BUFFER_SIZE        (PAGE_SIZE << 4)
  15 #define PEBS_FIXUP_SIZE         PAGE_SIZE
  16
  17 /*
  18  * pebs_record_32 for p4 and core not supported
  19
  20 struct pebs_record_32 {
  21         u32 flags, ip;
  22         u32 ax, bc, cx, dx;
  23         u32 si, di, bp, sp;
  24 };
  25
  26  */
  27
  28 union intel_x86_pebs_dse {
  29         u64 val;
  30         struct {
  31                 unsigned int ld_dse:4;
  32                 unsigned int ld_stlb_miss:1;
  33                 unsigned int ld_locked:1;
  34                 unsigned int ld_reserved:26;
  35         };
  36         struct {
  37                 unsigned int st_l1d_hit:1;
  38                 unsigned int st_reserved1:3;
  39                 unsigned int st_stlb_miss:1;
  40                 unsigned int st_locked:1;
  41                 unsigned int st_reserved2:26;
  42         };
  43 };
  44
  45
  46 /*
  47  * Map PEBS Load Latency Data Source encodings to generic
  48  * memory data source information
  49  */
  50 #define P(a, b) PERF_MEM_S(a, b)
  51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
  52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
  53
  54 static const u64 pebs_data_source[] = {
  55         P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
  56         OP_LH | P(LVL, L1)  | P(SNOOP, NONE),   /* 0x01: L1 local */
  57         OP_LH | P(LVL, LFB) | P(SNOOP, NONE),   /* 0x02: LFB hit */
  58         OP_LH | P(LVL, L2)  | P(SNOOP, NONE),   /* 0x03: L2 hit */
  59         OP_LH | P(LVL, L3)  | P(SNOOP, NONE),   /* 0x04: L3 hit */
  60         OP_LH | P(LVL, L3)  | P(SNOOP, MISS),   /* 0x05: L3 hit, snoop miss */
  61         OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x06: L3 hit, snoop hit */
  62         OP_LH | P(LVL, L3)  | P(SNOOP, HITM),   /* 0x07: L3 hit, snoop hitm */
  63         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
  64         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
  65         OP_LH | P(LVL, LOC_RAM)  | P(SNOOP, HIT),  /* 0x0a: L3 miss, shared */
  66         OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
  67         OP_LH | P(LVL, LOC_RAM)  | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
  68         OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
  69         OP_LH | P(LVL, IO)  | P(SNOOP, NONE), /* 0x0e: I/O */
  70         OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
  71 };
  72
  73 static u64 precise_store_data(u64 status)
  74 {
  75         union intel_x86_pebs_dse dse;
  76         u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
  77
  78         dse.val = status;
  79
  80         /*
  81          * bit 4: TLB access
  82          * 1 = stored missed 2nd level TLB
  83          *
  84          * so it either hit the walker or the OS
  85          * otherwise hit 2nd level TLB
  86          */
  87         if (dse.st_stlb_miss)
  88                 val |= P(TLB, MISS);
  89         else
  90                 val |= P(TLB, HIT);
  91
  92         /*
  93          * bit 0: hit L1 data cache
  94          * if not set, then all we know is that
  95          * it missed L1D
  96          */
  97         if (dse.st_l1d_hit)
  98                 val |= P(LVL, HIT);
  99         else
 100                 val |= P(LVL, MISS);
 101
 102         /*
 103          * bit 5: Locked prefix
 104          */
 105         if (dse.st_locked)
 106                 val |= P(LOCK, LOCKED);
 107
 108         return val;
 109 }
 110
 111 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
 112 {
 113         union perf_mem_data_src dse;
 114
 115         dse.val = PERF_MEM_NA;
 116
 117         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
 118                 dse.mem_op = PERF_MEM_OP_STORE;
 119         else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
 120                 dse.mem_op = PERF_MEM_OP_LOAD;
 121
 122         /*
 123          * L1 info only valid for following events:
 124          *
 125          * MEM_UOPS_RETIRED.STLB_MISS_STORES
 126          * MEM_UOPS_RETIRED.LOCK_STORES
 127          * MEM_UOPS_RETIRED.SPLIT_STORES
 128          * MEM_UOPS_RETIRED.ALL_STORES
 129          */
 130         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
 131                 if (status & 1)
 132                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
 133                 else
 134                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
 135         }
 136         return dse.val;
 137 }
 138
 139 static u64 load_latency_data(u64 status)
 140 {
 141         union intel_x86_pebs_dse dse;
 142         u64 val;
 143         int model = boot_cpu_data.x86_model;
 144         int fam = boot_cpu_data.x86;
 145
 146         dse.val = status;
 147
 148         /*
 149          * use the mapping table for bit 0-3
 150          */
 151         val = pebs_data_source[dse.ld_dse];
 152
 153         /*
 154          * Nehalem models do not support TLB, Lock infos
 155          */
 156         if (fam == 0x6 && (model == 26 || model == 30
 157             || model == 31 || model == 46)) {
 158                 val |= P(TLB, NA) | P(LOCK, NA);
 159                 return val;
 160         }
 161         /*
 162          * bit 4: TLB access
 163          * 0 = did not miss 2nd level TLB
 164          * 1 = missed 2nd level TLB
 165          */
 166         if (dse.ld_stlb_miss)
 167                 val |= P(TLB, MISS) | P(TLB, L2);
 168         else
 169                 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
 170
 171         /*
 172          * bit 5: locked prefix
 173          */
 174         if (dse.ld_locked)
 175                 val |= P(LOCK, LOCKED);
 176
 177         return val;
 178 }
 179
 180 struct pebs_record_core {
 181         u64 flags, ip;
 182         u64 ax, bx, cx, dx;
 183         u64 si, di, bp, sp;
 184         u64 r8,  r9,  r10, r11;
 185         u64 r12, r13, r14, r15;
 186 };
 187
 188 struct pebs_record_nhm {
 189         u64 flags, ip;
 190         u64 ax, bx, cx, dx;
 191         u64 si, di, bp, sp;
 192         u64 r8,  r9,  r10, r11;
 193         u64 r12, r13, r14, r15;
 194         u64 status, dla, dse, lat;
 195 };
 196
 197 /*
 198  * Same as pebs_record_nhm, with two additional fields.
 199  */
 200 struct pebs_record_hsw {
 201         u64 flags, ip;
 202         u64 ax, bx, cx, dx;
 203         u64 si, di, bp, sp;
 204         u64 r8,  r9,  r10, r11;
 205         u64 r12, r13, r14, r15;
 206         u64 status, dla, dse, lat;
 207         u64 real_ip, tsx_tuning;
 208 };
 209
 210 union hsw_tsx_tuning {
 211         struct {
 212                 u32 cycles_last_block     : 32,
 213                     hle_abort             : 1,
 214                     rtm_abort             : 1,
 215                     instruction_abort     : 1,
 216                     non_instruction_abort : 1,
 217                     retry                 : 1,
 218                     data_conflict         : 1,
 219                     capacity_writes       : 1,
 220                     capacity_reads        : 1;
 221         };
 222         u64         value;
 223 };
 224
 225 #define PEBS_HSW_TSX_FLAGS      0xff00000000ULL
 226
 227 /* Same as HSW, plus TSC */
 228
 229 struct pebs_record_skl {
 230         u64 flags, ip;
 231         u64 ax, bx, cx, dx;
 232         u64 si, di, bp, sp;
 233         u64 r8,  r9,  r10, r11;
 234         u64 r12, r13, r14, r15;
 235         u64 status, dla, dse, lat;
 236         u64 real_ip, tsx_tuning;
 237         u64 tsc;
 238 };
 239
 240 void init_debug_store_on_cpu(int cpu)
 241 {
 242         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 243
 244         if (!ds)
 245                 return;
 246
 247         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 248                      (u32)((u64)(unsigned long)ds),
 249                      (u32)((u64)(unsigned long)ds >> 32));
 250 }
 251
 252 void fini_debug_store_on_cpu(int cpu)
 253 {
 254         if (!per_cpu(cpu_hw_events, cpu).ds)
 255                 return;
 256
 257         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 258 }
 259
 260 static DEFINE_PER_CPU(void *, insn_buffer);
 261
 262 static int alloc_pebs_buffer(int cpu)
 263 {
 264         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 265         int node = cpu_to_node(cpu);
 266         int max;
 267         void *buffer, *ibuffer;
 268
 269         if (!x86_pmu.pebs)
 270                 return 0;
 271
 272         buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
 273         if (unlikely(!buffer))
 274                 return -ENOMEM;
 275
 276         /*
 277          * HSW+ already provides us the eventing ip; no need to allocate this
 278          * buffer then.
 279          */
 280         if (x86_pmu.intel_cap.pebs_format < 2) {
 281                 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
 282                 if (!ibuffer) {
 283                         kfree(buffer);
 284                         return -ENOMEM;
 285                 }
 286                 per_cpu(insn_buffer, cpu) = ibuffer;
 287         }
 288
 289         max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
 290
 291         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
 292         ds->pebs_index = ds->pebs_buffer_base;
 293         ds->pebs_absolute_maximum = ds->pebs_buffer_base +
 294                 max * x86_pmu.pebs_record_size;
 295
 296         return 0;
 297 }
 298
 299 static void release_pebs_buffer(int cpu)
 300 {
 301         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 302
 303         if (!ds || !x86_pmu.pebs)
 304                 return;
 305
 306         kfree(per_cpu(insn_buffer, cpu));
 307         per_cpu(insn_buffer, cpu) = NULL;
 308
 309         kfree((void *)(unsigned long)ds->pebs_buffer_base);
 310         ds->pebs_buffer_base = 0;
 311 }
 312
 313 static int alloc_bts_buffer(int cpu)
 314 {
 315         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 316         int node = cpu_to_node(cpu);
 317         int max, thresh;
 318         void *buffer;
 319
 320         if (!x86_pmu.bts)
 321                 return 0;
 322
 323         buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
 324         if (unlikely(!buffer)) {
 325                 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
 326                 return -ENOMEM;
 327         }
 328
 329         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 330         thresh = max / 16;
 331
 332         ds->bts_buffer_base = (u64)(unsigned long)buffer;
 333         ds->bts_index = ds->bts_buffer_base;
 334         ds->bts_absolute_maximum = ds->bts_buffer_base +
 335                 max * BTS_RECORD_SIZE;
 336         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 337                 thresh * BTS_RECORD_SIZE;
 338
 339         return 0;
 340 }
 341
 342 static void release_bts_buffer(int cpu)
 343 {
 344         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 345
 346         if (!ds || !x86_pmu.bts)
 347                 return;
 348
 349         kfree((void *)(unsigned long)ds->bts_buffer_base);
 350         ds->bts_buffer_base = 0;
 351 }
 352
 353 static int alloc_ds_buffer(int cpu)
 354 {
 355         int node = cpu_to_node(cpu);
 356         struct debug_store *ds;
 357
 358         ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
 359         if (unlikely(!ds))
 360                 return -ENOMEM;
 361
 362         per_cpu(cpu_hw_events, cpu).ds = ds;
 363
 364         return 0;
 365 }
 366
 367 static void release_ds_buffer(int cpu)
 368 {
 369         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 370
 371         if (!ds)
 372                 return;
 373
 374         per_cpu(cpu_hw_events, cpu).ds = NULL;
 375         kfree(ds);
 376 }
 377
 378 void release_ds_buffers(void)
 379 {
 380         int cpu;
 381
 382         if (!x86_pmu.bts && !x86_pmu.pebs)
 383                 return;
 384
 385         get_online_cpus();
 386         for_each_online_cpu(cpu)
 387                 fini_debug_store_on_cpu(cpu);
 388
 389         for_each_possible_cpu(cpu) {
 390                 release_pebs_buffer(cpu);
 391                 release_bts_buffer(cpu);
 392                 release_ds_buffer(cpu);
 393         }
 394         put_online_cpus();
 395 }
 396
 397 void reserve_ds_buffers(void)
 398 {
 399         int bts_err = 0, pebs_err = 0;
 400         int cpu;
 401
 402         x86_pmu.bts_active = 0;
 403         x86_pmu.pebs_active = 0;
 404
 405         if (!x86_pmu.bts && !x86_pmu.pebs)
 406                 return;
 407
 408         if (!x86_pmu.bts)
 409                 bts_err = 1;
 410
 411         if (!x86_pmu.pebs)
 412                 pebs_err = 1;
 413
 414         get_online_cpus();
 415
 416         for_each_possible_cpu(cpu) {
 417                 if (alloc_ds_buffer(cpu)) {
 418                         bts_err = 1;
 419                         pebs_err = 1;
 420                 }
 421
 422                 if (!bts_err && alloc_bts_buffer(cpu))
 423                         bts_err = 1;
 424
 425                 if (!pebs_err && alloc_pebs_buffer(cpu))
 426                         pebs_err = 1;
 427
 428                 if (bts_err && pebs_err)
 429                         break;
 430         }
 431
 432         if (bts_err) {
 433                 for_each_possible_cpu(cpu)
 434                         release_bts_buffer(cpu);
 435         }
 436
 437         if (pebs_err) {
 438                 for_each_possible_cpu(cpu)
 439                         release_pebs_buffer(cpu);
 440         }
 441
 442         if (bts_err && pebs_err) {
 443                 for_each_possible_cpu(cpu)
 444                         release_ds_buffer(cpu);
 445         } else {
 446                 if (x86_pmu.bts && !bts_err)
 447                         x86_pmu.bts_active = 1;
 448
 449                 if (x86_pmu.pebs && !pebs_err)
 450                         x86_pmu.pebs_active = 1;
 451
 452                 for_each_online_cpu(cpu)
 453                         init_debug_store_on_cpu(cpu);
 454         }
 455
 456         put_online_cpus();
 457 }
 458
 459 /*
 460  * BTS
 461  */
 462
 463 struct event_constraint bts_constraint =
 464         EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
 465
 466 void intel_pmu_enable_bts(u64 config)
 467 {
 468         unsigned long debugctlmsr;
 469
 470         debugctlmsr = get_debugctlmsr();
 471
 472         debugctlmsr |= DEBUGCTLMSR_TR;
 473         debugctlmsr |= DEBUGCTLMSR_BTS;
 474         if (config & ARCH_PERFMON_EVENTSEL_INT)
 475                 debugctlmsr |= DEBUGCTLMSR_BTINT;
 476
 477         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 478                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
 479
 480         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 481                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
 482
 483         update_debugctlmsr(debugctlmsr);
 484 }
 485
 486 void intel_pmu_disable_bts(void)
 487 {
 488         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 489         unsigned long debugctlmsr;
 490
 491         if (!cpuc->ds)
 492                 return;
 493
 494         debugctlmsr = get_debugctlmsr();
 495
 496         debugctlmsr &=
 497                 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
 498                   DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
 499
 500         update_debugctlmsr(debugctlmsr);
 501 }
 502
 503 int intel_pmu_drain_bts_buffer(void)
 504 {
 505         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 506         struct debug_store *ds = cpuc->ds;
 507         struct bts_record {
 508                 u64     from;
 509                 u64     to;
 510                 u64     flags;
 511         };
 512         struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 513         struct bts_record *at, *top;
 514         struct perf_output_handle handle;
 515         struct perf_event_header header;
 516         struct perf_sample_data data;
 517         struct pt_regs regs;
 518
 519         if (!event)
 520                 return 0;
 521
 522         if (!x86_pmu.bts_active)
 523                 return 0;
 524
 525         at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 526         top = (struct bts_record *)(unsigned long)ds->bts_index;
 527
 528         if (top <= at)
 529                 return 0;
 530
 531         memset(&regs, 0, sizeof(regs));
 532
 533         ds->bts_index = ds->bts_buffer_base;
 534
 535         perf_sample_data_init(&data, 0, event->hw.last_period);
 536
 537         /*
 538          * Prepare a generic sample, i.e. fill in the invariant fields.
 539          * We will overwrite the from and to address before we output
 540          * the sample.
 541          */
 542         perf_prepare_sample(&header, &data, event, &regs);
 543
 544         if (perf_output_begin(&handle, event, header.size * (top - at)))
 545                 return 1;
 546
 547         for (; at < top; at++) {
 548                 data.ip         = at->from;
 549                 data.addr       = at->to;
 550
 551                 perf_output_sample(&handle, &header, &data, event);
 552         }
 553
 554         perf_output_end(&handle);
 555
 556         /* There's new data available. */
 557         event->hw.interrupts++;
 558         event->pending_kill = POLL_IN;
 559         return 1;
 560 }
 561
 562 static inline void intel_pmu_drain_pebs_buffer(void)
 563 {
 564         struct pt_regs regs;
 565
 566         x86_pmu.drain_pebs(&regs);
 567 }
 568
 569 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
 570 {
 571         if (!sched_in)
 572                 intel_pmu_drain_pebs_buffer();
 573 }
 574
 575 /*
 576  * PEBS
 577  */
 578 struct event_constraint intel_core2_pebs_event_constraints[] = {
 579         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 580         INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 581         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 582         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 583         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 584         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 585         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
 586         EVENT_CONSTRAINT_END
 587 };
 588
 589 struct event_constraint intel_atom_pebs_event_constraints[] = {
 590         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 591         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
 592         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 593         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 594         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
 595         EVENT_CONSTRAINT_END
 596 };
 597
 598 struct event_constraint intel_slm_pebs_event_constraints[] = {
 599         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 600         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
 601         /* Allow all events as PEBS with no flags */
 602         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 603         EVENT_CONSTRAINT_END
 604 };
 605
 606 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
 607         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 608         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 609         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 610         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
 611         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 612         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 613         INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
 614         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 615         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 616         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 617         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 618         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 619         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
 620         EVENT_CONSTRAINT_END
 621 };
 622
 623 struct event_constraint intel_westmere_pebs_event_constraints[] = {
 624         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 625         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 626         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 627         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
 628         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 629         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 630         INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 631         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 632         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 633         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 634         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 635         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 636         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
 637         EVENT_CONSTRAINT_END
 638 };
 639
 640 struct event_constraint intel_snb_pebs_event_constraints[] = {
 641         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 642         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 643         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 644         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 645         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 646         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 647         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 648         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 649         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 650         /* Allow all events as PEBS with no flags */
 651         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 652         EVENT_CONSTRAINT_END
 653 };
 654
 655 struct event_constraint intel_ivb_pebs_event_constraints[] = {
 656         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 657         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 658         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 659         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 660         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 661         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 662         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 663         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 664         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 665         /* Allow all events as PEBS with no flags */
 666         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 667         EVENT_CONSTRAINT_END
 668 };
 669
 670 struct event_constraint intel_hsw_pebs_event_constraints[] = {
 671         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 672         INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
 673         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 674         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 675         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 676         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 677         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 678         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 679         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 680         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 681         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
 682         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 683         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 684         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
 685         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
 686         /* Allow all events as PEBS with no flags */
 687         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 688         EVENT_CONSTRAINT_END
 689 };
 690
 691 struct event_constraint intel_skl_pebs_event_constraints[] = {
 692         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2),      /* INST_RETIRED.PREC_DIST */
 693         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 694         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 695         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 696         INTEL_PLD_CONSTRAINT(0x1cd, 0xf),                     /* MEM_TRANS_RETIRED.* */
 697         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
 698         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
 699         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
 700         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
 701         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
 702         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
 703         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
 704         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
 705         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_RETIRED.* */
 706         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_L3_HIT_RETIRED.* */
 707         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_L3_MISS_RETIRED.* */
 708         /* Allow all events as PEBS with no flags */
 709         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 710         EVENT_CONSTRAINT_END
 711 };
 712
 713 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
 714 {
 715         struct event_constraint *c;
 716
 717         if (!event->attr.precise_ip)
 718                 return NULL;
 719
 720         if (x86_pmu.pebs_constraints) {
 721                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 722                         if ((event->hw.config & c->cmask) == c->code) {
 723                                 event->hw.flags |= c->flags;
 724                                 return c;
 725                         }
 726                 }
 727         }
 728
 729         return &emptyconstraint;
 730 }
 731
 732 static inline bool pebs_is_enabled(struct cpu_hw_events *cpuc)
 733 {
 734         return (cpuc->pebs_enabled & ((1ULL << MAX_PEBS_EVENTS) - 1));
 735 }
 736
 737 void intel_pmu_pebs_enable(struct perf_event *event)
 738 {
 739         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 740         struct hw_perf_event *hwc = &event->hw;
 741         struct debug_store *ds = cpuc->ds;
 742         bool first_pebs;
 743         u64 threshold;
 744
 745         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 746
 747         first_pebs = !pebs_is_enabled(cpuc);
 748         cpuc->pebs_enabled |= 1ULL << hwc->idx;
 749
 750         if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
 751                 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
 752         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
 753                 cpuc->pebs_enabled |= 1ULL << 63;
 754
 755         /*
 756          * When the event is constrained enough we can use a larger
 757          * threshold and run the event with less frequent PMI.
 758          */
 759         if (hwc->flags & PERF_X86_EVENT_FREERUNNING) {
 760                 threshold = ds->pebs_absolute_maximum -
 761                         x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
 762
 763                 if (first_pebs)
 764                         perf_sched_cb_inc(event->ctx->pmu);
 765         } else {
 766                 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
 767
 768                 /*
 769                  * If not all events can use larger buffer,
 770                  * roll back to threshold = 1
 771                  */
 772                 if (!first_pebs &&
 773                     (ds->pebs_interrupt_threshold > threshold))
 774                         perf_sched_cb_dec(event->ctx->pmu);
 775         }
 776
 777         /* Use auto-reload if possible to save a MSR write in the PMI */
 778         if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
 779                 ds->pebs_event_reset[hwc->idx] =
 780                         (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
 781         }
 782
 783         if (first_pebs || ds->pebs_interrupt_threshold > threshold)
 784                 ds->pebs_interrupt_threshold = threshold;
 785 }
 786
 787 void intel_pmu_pebs_disable(struct perf_event *event)
 788 {
 789         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 790         struct hw_perf_event *hwc = &event->hw;
 791         struct debug_store *ds = cpuc->ds;
 792         bool large_pebs = ds->pebs_interrupt_threshold >
 793                 ds->pebs_buffer_base + x86_pmu.pebs_record_size;
 794
 795         if (large_pebs)
 796                 intel_pmu_drain_pebs_buffer();
 797
 798         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
 799
 800         if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
 801                 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
 802         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
 803                 cpuc->pebs_enabled &= ~(1ULL << 63);
 804
 805         if (large_pebs && !pebs_is_enabled(cpuc))
 806                 perf_sched_cb_dec(event->ctx->pmu);
 807
 808         if (cpuc->enabled)
 809                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 810
 811         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
 812 }
 813
 814 void intel_pmu_pebs_enable_all(void)
 815 {
 816         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 817
 818         if (cpuc->pebs_enabled)
 819                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 820 }
 821
 822 void intel_pmu_pebs_disable_all(void)
 823 {
 824         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 825
 826         if (cpuc->pebs_enabled)
 827                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 828 }
 829
 830 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
 831 {
 832         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 833         unsigned long from = cpuc->lbr_entries[0].from;
 834         unsigned long old_to, to = cpuc->lbr_entries[0].to;
 835         unsigned long ip = regs->ip;
 836         int is_64bit = 0;
 837         void *kaddr;
 838         int size;
 839
 840         /*
 841          * We don't need to fixup if the PEBS assist is fault like
 842          */
 843         if (!x86_pmu.intel_cap.pebs_trap)
 844                 return 1;
 845
 846         /*
 847          * No LBR entry, no basic block, no rewinding
 848          */
 849         if (!cpuc->lbr_stack.nr || !from || !to)
 850                 return 0;
 851
 852         /*
 853          * Basic blocks should never cross user/kernel boundaries
 854          */
 855         if (kernel_ip(ip) != kernel_ip(to))
 856                 return 0;
 857
 858         /*
 859          * unsigned math, either ip is before the start (impossible) or
 860          * the basic block is larger than 1 page (sanity)
 861          */
 862         if ((ip - to) > PEBS_FIXUP_SIZE)
 863                 return 0;
 864
 865         /*
 866          * We sampled a branch insn, rewind using the LBR stack
 867          */
 868         if (ip == to) {
 869                 set_linear_ip(regs, from);
 870                 return 1;
 871         }
 872
 873         size = ip - to;
 874         if (!kernel_ip(ip)) {
 875                 int bytes;
 876                 u8 *buf = this_cpu_read(insn_buffer);
 877
 878                 /* 'size' must fit our buffer, see above */
 879                 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
 880                 if (bytes != 0)
 881                         return 0;
 882
 883                 kaddr = buf;
 884         } else {
 885                 kaddr = (void *)to;
 886         }
 887
 888         do {
 889                 struct insn insn;
 890
 891                 old_to = to;
 892
 893 #ifdef CONFIG_X86_64
 894                 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
 895 #endif
 896                 insn_init(&insn, kaddr, size, is_64bit);
 897                 insn_get_length(&insn);
 898                 /*
 899                  * Make sure there was not a problem decoding the
 900                  * instruction and getting the length.  This is
 901                  * doubly important because we have an infinite
 902                  * loop if insn.length=0.
 903                  */
 904                 if (!insn.length)
 905                         break;
 906
 907                 to += insn.length;
 908                 kaddr += insn.length;
 909                 size -= insn.length;
 910         } while (to < ip);
 911
 912         if (to == ip) {
 913                 set_linear_ip(regs, old_to);
 914                 return 1;
 915         }
 916
 917         /*
 918          * Even though we decoded the basic block, the instruction stream
 919          * never matched the given IP, either the TO or the IP got corrupted.
 920          */
 921         return 0;
 922 }
 923
 924 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
 925 {
 926         if (pebs->tsx_tuning) {
 927                 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
 928                 return tsx.cycles_last_block;
 929         }
 930         return 0;
 931 }
 932
 933 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
 934 {
 935         u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
 936
 937         /* For RTM XABORTs also log the abort code from AX */
 938         if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
 939                 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
 940         return txn;
 941 }
 942
 943 static void setup_pebs_sample_data(struct perf_event *event,
 944                                    struct pt_regs *iregs, void *__pebs,
 945                                    struct perf_sample_data *data,
 946                                    struct pt_regs *regs)
 947 {
 948 #define PERF_X86_EVENT_PEBS_HSW_PREC \
 949                 (PERF_X86_EVENT_PEBS_ST_HSW | \
 950                  PERF_X86_EVENT_PEBS_LD_HSW | \
 951                  PERF_X86_EVENT_PEBS_NA_HSW)
 952         /*
 953          * We cast to the biggest pebs_record but are careful not to
 954          * unconditionally access the 'extra' entries.
 955          */
 956         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 957         struct pebs_record_skl *pebs = __pebs;
 958         u64 sample_type;
 959         int fll, fst, dsrc;
 960         int fl = event->hw.flags;
 961
 962         if (pebs == NULL)
 963                 return;
 964
 965         sample_type = event->attr.sample_type;
 966         dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
 967
 968         fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
 969         fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
 970
 971         perf_sample_data_init(data, 0, event->hw.last_period);
 972
 973         data->period = event->hw.last_period;
 974
 975         /*
 976          * Use latency for weight (only avail with PEBS-LL)
 977          */
 978         if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
 979                 data->weight = pebs->lat;
 980
 981         /*
 982          * data.data_src encodes the data source
 983          */
 984         if (dsrc) {
 985                 u64 val = PERF_MEM_NA;
 986                 if (fll)
 987                         val = load_latency_data(pebs->dse);
 988                 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
 989                         val = precise_datala_hsw(event, pebs->dse);
 990                 else if (fst)
 991                         val = precise_store_data(pebs->dse);
 992                 data->data_src.val = val;
 993         }
 994
 995         /*
 996          * We use the interrupt regs as a base because the PEBS record
 997          * does not contain a full regs set, specifically it seems to
 998          * lack segment descriptors, which get used by things like
 999          * user_mode().
1000          *
1001          * In the simple case fix up only the IP and BP,SP regs, for
1002          * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
1003          * A possible PERF_SAMPLE_REGS will have to transfer all regs.
1004          */
1005         *regs = *iregs;
1006         regs->flags = pebs->flags;
1007         set_linear_ip(regs, pebs->ip);
1008         regs->bp = pebs->bp;
1009         regs->sp = pebs->sp;
1010
1011         if (sample_type & PERF_SAMPLE_REGS_INTR) {
1012                 regs->ax = pebs->ax;
1013                 regs->bx = pebs->bx;
1014                 regs->cx = pebs->cx;
1015                 regs->dx = pebs->dx;
1016                 regs->si = pebs->si;
1017                 regs->di = pebs->di;
1018                 regs->bp = pebs->bp;
1019                 regs->sp = pebs->sp;
1020
1021                 regs->flags = pebs->flags;
1022 #ifndef CONFIG_X86_32
1023                 regs->r8 = pebs->r8;
1024                 regs->r9 = pebs->r9;
1025                 regs->r10 = pebs->r10;
1026                 regs->r11 = pebs->r11;
1027                 regs->r12 = pebs->r12;
1028                 regs->r13 = pebs->r13;
1029                 regs->r14 = pebs->r14;
1030                 regs->r15 = pebs->r15;
1031 #endif
1032         }
1033
1034         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
1035                 regs->ip = pebs->real_ip;
1036                 regs->flags |= PERF_EFLAGS_EXACT;
1037         } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
1038                 regs->flags |= PERF_EFLAGS_EXACT;
1039         else
1040                 regs->flags &= ~PERF_EFLAGS_EXACT;
1041
1042         if ((sample_type & PERF_SAMPLE_ADDR) &&
1043             x86_pmu.intel_cap.pebs_format >= 1)
1044                 data->addr = pebs->dla;
1045
1046         if (x86_pmu.intel_cap.pebs_format >= 2) {
1047                 /* Only set the TSX weight when no memory weight. */
1048                 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1049                         data->weight = intel_hsw_weight(pebs);
1050
1051                 if (sample_type & PERF_SAMPLE_TRANSACTION)
1052                         data->txn = intel_hsw_transaction(pebs);
1053         }
1054
1055         /*
1056          * v3 supplies an accurate time stamp, so we use that
1057          * for the time stamp.
1058          *
1059          * We can only do this for the default trace clock.
1060          */
1061         if (x86_pmu.intel_cap.pebs_format >= 3 &&
1062                 event->attr.use_clockid == 0)
1063                 data->time = native_sched_clock_from_tsc(pebs->tsc);
1064
1065         if (has_branch_stack(event))
1066                 data->br_stack = &cpuc->lbr_stack;
1067 }
1068
1069 static inline void *
1070 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1071 {
1072         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1073         void *at;
1074         u64 pebs_status;
1075
1076         if (base == NULL)
1077                 return NULL;
1078
1079         for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1080                 struct pebs_record_nhm *p = at;
1081
1082                 if (test_bit(bit, (unsigned long *)&p->status)) {
1083                         /* PEBS v3 has accurate status bits */
1084                         if (x86_pmu.intel_cap.pebs_format >= 3)
1085                                 return at;
1086
1087                         if (p->status == (1 << bit))
1088                                 return at;
1089
1090                         /* clear non-PEBS bit and re-check */
1091                         pebs_status = p->status & cpuc->pebs_enabled;
1092                         pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
1093                         if (pebs_status == (1 << bit))
1094                                 return at;
1095                 }
1096         }
1097         return NULL;
1098 }
1099
1100 static void __intel_pmu_pebs_event(struct perf_event *event,
1101                                    struct pt_regs *iregs,
1102                                    void *base, void *top,
1103                                    int bit, int count)
1104 {
1105         struct perf_sample_data data;
1106         struct pt_regs regs;
1107         void *at = get_next_pebs_record_by_bit(base, top, bit);
1108
1109         if (!intel_pmu_save_and_restart(event) &&
1110             !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1111                 return;
1112
1113         while (count > 1) {
1114                 setup_pebs_sample_data(event, iregs, at, &data, &regs);
1115                 perf_event_output(event, &data, &regs);
1116                 at += x86_pmu.pebs_record_size;
1117                 at = get_next_pebs_record_by_bit(at, top, bit);
1118                 count--;
1119         }
1120
1121         setup_pebs_sample_data(event, iregs, at, &data, &regs);
1122
1123         /*
1124          * All but the last records are processed.
1125          * The last one is left to be able to call the overflow handler.
1126          */
1127         if (perf_event_overflow(event, &data, &regs)) {
1128                 x86_pmu_stop(event, 0);
1129                 return;
1130         }
1131
1132 }
1133
1134 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1135 {
1136         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1137         struct debug_store *ds = cpuc->ds;
1138         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1139         struct pebs_record_core *at, *top;
1140         int n;
1141
1142         if (!x86_pmu.pebs_active)
1143                 return;
1144
1145         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1146         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1147
1148         /*
1149          * Whatever else happens, drain the thing
1150          */
1151         ds->pebs_index = ds->pebs_buffer_base;
1152
1153         if (!test_bit(0, cpuc->active_mask))
1154                 return;
1155
1156         WARN_ON_ONCE(!event);
1157
1158         if (!event->attr.precise_ip)
1159                 return;
1160
1161         n = (top - at) / x86_pmu.pebs_record_size;
1162         if (n <= 0)
1163                 return;
1164
1165         __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1166 }
1167
1168 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1169 {
1170         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1171         struct debug_store *ds = cpuc->ds;
1172         struct perf_event *event;
1173         void *base, *at, *top;
1174         short counts[MAX_PEBS_EVENTS] = {};
1175         short error[MAX_PEBS_EVENTS] = {};
1176         int bit, i;
1177
1178         if (!x86_pmu.pebs_active)
1179                 return;
1180
1181         base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1182         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1183
1184         ds->pebs_index = ds->pebs_buffer_base;
1185
1186         if (unlikely(base >= top))
1187                 return;
1188
1189         for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1190                 struct pebs_record_nhm *p = at;
1191                 u64 pebs_status;
1192
1193                 /* PEBS v3 has accurate status bits */
1194                 if (x86_pmu.intel_cap.pebs_format >= 3) {
1195                         for_each_set_bit(bit, (unsigned long *)&p->status,
1196                                          MAX_PEBS_EVENTS)
1197                                 counts[bit]++;
1198
1199                         continue;
1200                 }
1201
1202                 pebs_status = p->status & cpuc->pebs_enabled;
1203                 pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
1204
1205                 bit = find_first_bit((unsigned long *)&pebs_status,
1206                                         x86_pmu.max_pebs_events);
1207                 if (WARN(bit >= x86_pmu.max_pebs_events,
1208                          "PEBS record without PEBS event! status=%Lx pebs_enabled=%Lx active_mask=%Lx",
1209                          (unsigned long long)p->status, (unsigned long long)cpuc->pebs_enabled,
1210                          *(unsigned long long *)cpuc->active_mask))
1211                         continue;
1212
1213                 /*
1214                  * The PEBS hardware does not deal well with the situation
1215                  * when events happen near to each other and multiple bits
1216                  * are set. But it should happen rarely.
1217                  *
1218                  * If these events include one PEBS and multiple non-PEBS
1219                  * events, it doesn't impact PEBS record. The record will
1220                  * be handled normally. (slow path)
1221                  *
1222                  * If these events include two or more PEBS events, the
1223                  * records for the events can be collapsed into a single
1224                  * one, and it's not possible to reconstruct all events
1225                  * that caused the PEBS record. It's called collision.
1226                  * If collision happened, the record will be dropped.
1227                  */
1228                 if (p->status != (1ULL << bit)) {
1229                         for_each_set_bit(i, (unsigned long *)&pebs_status,
1230                                          x86_pmu.max_pebs_events)
1231                                 error[i]++;
1232                         continue;
1233                 }
1234
1235                 counts[bit]++;
1236         }
1237
1238         for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1239                 if ((counts[bit] == 0) && (error[bit] == 0))
1240                         continue;
1241
1242                 event = cpuc->events[bit];
1243                 WARN_ON_ONCE(!event);
1244                 WARN_ON_ONCE(!event->attr.precise_ip);
1245
1246                 /* log dropped samples number */
1247                 if (error[bit])
1248                         perf_log_lost_samples(event, error[bit]);
1249
1250                 if (counts[bit]) {
1251                         __intel_pmu_pebs_event(event, iregs, base,
1252                                                top, bit, counts[bit]);
1253                 }
1254         }
1255 }
1256
1257 /*
1258  * BTS, PEBS probe and setup
1259  */
1260
1261 void __init intel_ds_init(void)
1262 {
1263         /*
1264          * No support for 32bit formats
1265          */
1266         if (!boot_cpu_has(X86_FEATURE_DTES64))
1267                 return;
1268
1269         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
1270         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1271         if (x86_pmu.pebs) {
1272                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
1273                 int format = x86_pmu.intel_cap.pebs_format;
1274
1275                 switch (format) {
1276                 case 0:
1277                         printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1278                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1279                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1280                         break;
1281
1282                 case 1:
1283                         printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1284                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1285                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1286                         break;
1287
1288                 case 2:
1289                         pr_cont("PEBS fmt2%c, ", pebs_type);
1290                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1291                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1292                         break;
1293
1294                 case 3:
1295                         pr_cont("PEBS fmt3%c, ", pebs_type);
1296                         x86_pmu.pebs_record_size =
1297                                                 sizeof(struct pebs_record_skl);
1298                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1299                         x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
1300                         break;
1301
1302                 default:
1303                         printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1304                         x86_pmu.pebs = 0;
1305                 }
1306         }
1307 }
1308
1309 void perf_restore_debug_store(void)
1310 {
1311         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1312
1313         if (!x86_pmu.bts && !x86_pmu.pebs)
1314                 return;
1315
1316         wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1317 }