drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static inline u32 /* units of 100MHz */
 102 intel_fdi_link_freq(struct drm_device *dev)
 103 {
 104         if (IS_GEN5(dev)) {
 105                 struct drm_i915_private *dev_priv = dev->dev_private;
 106                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 107         } else
 108                 return 27;
 109 }
 110
 111 static const intel_limit_t intel_limits_i8xx_dvo = {
 112         .dot = { .min = 25000, .max = 350000 },
 113         .vco = { .min = 930000, .max = 1400000 },
 114         .n = { .min = 3, .max = 16 },
 115         .m = { .min = 96, .max = 140 },
 116         .m1 = { .min = 18, .max = 26 },
 117         .m2 = { .min = 6, .max = 16 },
 118         .p = { .min = 4, .max = 128 },
 119         .p1 = { .min = 2, .max = 33 },
 120         .p2 = { .dot_limit = 165000,
 121                 .p2_slow = 4, .p2_fast = 2 },
 122         .find_pll = intel_find_best_PLL,
 123 };
 124
 125 static const intel_limit_t intel_limits_i8xx_lvds = {
 126         .dot = { .min = 25000, .max = 350000 },
 127         .vco = { .min = 930000, .max = 1400000 },
 128         .n = { .min = 3, .max = 16 },
 129         .m = { .min = 96, .max = 140 },
 130         .m1 = { .min = 18, .max = 26 },
 131         .m2 = { .min = 6, .max = 16 },
 132         .p = { .min = 4, .max = 128 },
 133         .p1 = { .min = 1, .max = 6 },
 134         .p2 = { .dot_limit = 165000,
 135                 .p2_slow = 14, .p2_fast = 7 },
 136         .find_pll = intel_find_best_PLL,
 137 };
 138
 139 static const intel_limit_t intel_limits_i9xx_sdvo = {
 140         .dot = { .min = 20000, .max = 400000 },
 141         .vco = { .min = 1400000, .max = 2800000 },
 142         .n = { .min = 1, .max = 6 },
 143         .m = { .min = 70, .max = 120 },
 144         .m1 = { .min = 10, .max = 22 },
 145         .m2 = { .min = 5, .max = 9 },
 146         .p = { .min = 5, .max = 80 },
 147         .p1 = { .min = 1, .max = 8 },
 148         .p2 = { .dot_limit = 200000,
 149                 .p2_slow = 10, .p2_fast = 5 },
 150         .find_pll = intel_find_best_PLL,
 151 };
 152
 153 static const intel_limit_t intel_limits_i9xx_lvds = {
 154         .dot = { .min = 20000, .max = 400000 },
 155         .vco = { .min = 1400000, .max = 2800000 },
 156         .n = { .min = 1, .max = 6 },
 157         .m = { .min = 70, .max = 120 },
 158         .m1 = { .min = 10, .max = 22 },
 159         .m2 = { .min = 5, .max = 9 },
 160         .p = { .min = 7, .max = 98 },
 161         .p1 = { .min = 1, .max = 8 },
 162         .p2 = { .dot_limit = 112000,
 163                 .p2_slow = 14, .p2_fast = 7 },
 164         .find_pll = intel_find_best_PLL,
 165 };
 166
 167
 168 static const intel_limit_t intel_limits_g4x_sdvo = {
 169         .dot = { .min = 25000, .max = 270000 },
 170         .vco = { .min = 1750000, .max = 3500000},
 171         .n = { .min = 1, .max = 4 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 10, .max = 30 },
 176         .p1 = { .min = 1, .max = 3},
 177         .p2 = { .dot_limit = 270000,
 178                 .p2_slow = 10,
 179                 .p2_fast = 10
 180         },
 181         .find_pll = intel_g4x_find_best_PLL,
 182 };
 183
 184 static const intel_limit_t intel_limits_g4x_hdmi = {
 185         .dot = { .min = 22000, .max = 400000 },
 186         .vco = { .min = 1750000, .max = 3500000},
 187         .n = { .min = 1, .max = 4 },
 188         .m = { .min = 104, .max = 138 },
 189         .m1 = { .min = 16, .max = 23 },
 190         .m2 = { .min = 5, .max = 11 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8},
 193         .p2 = { .dot_limit = 165000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195         .find_pll = intel_g4x_find_best_PLL,
 196 };
 197
 198 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 199         .dot = { .min = 20000, .max = 115000 },
 200         .vco = { .min = 1750000, .max = 3500000 },
 201         .n = { .min = 1, .max = 3 },
 202         .m = { .min = 104, .max = 138 },
 203         .m1 = { .min = 17, .max = 23 },
 204         .m2 = { .min = 5, .max = 11 },
 205         .p = { .min = 28, .max = 112 },
 206         .p1 = { .min = 2, .max = 8 },
 207         .p2 = { .dot_limit = 0,
 208                 .p2_slow = 14, .p2_fast = 14
 209         },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 214         .dot = { .min = 80000, .max = 224000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 14, .max = 42 },
 221         .p1 = { .min = 2, .max = 6 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 7, .p2_fast = 7
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_display_port = {
 229         .dot = { .min = 161670, .max = 227000 },
 230         .vco = { .min = 1750000, .max = 3500000},
 231         .n = { .min = 1, .max = 2 },
 232         .m = { .min = 97, .max = 108 },
 233         .m1 = { .min = 0x10, .max = 0x12 },
 234         .m2 = { .min = 0x05, .max = 0x06 },
 235         .p = { .min = 10, .max = 20 },
 236         .p1 = { .min = 1, .max = 2},
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 10, .p2_fast = 10 },
 239         .find_pll = intel_find_pll_g4x_dp,
 240 };
 241
 242 static const intel_limit_t intel_limits_pineview_sdvo = {
 243         .dot = { .min = 20000, .max = 400000},
 244         .vco = { .min = 1700000, .max = 3500000 },
 245         /* Pineview's Ncounter is a ring counter */
 246         .n = { .min = 3, .max = 6 },
 247         .m = { .min = 2, .max = 256 },
 248         /* Pineview only has one combined m divider, which we treat as m2. */
 249         .m1 = { .min = 0, .max = 0 },
 250         .m2 = { .min = 0, .max = 254 },
 251         .p = { .min = 5, .max = 80 },
 252         .p1 = { .min = 1, .max = 8 },
 253         .p2 = { .dot_limit = 200000,
 254                 .p2_slow = 10, .p2_fast = 5 },
 255         .find_pll = intel_find_best_PLL,
 256 };
 257
 258 static const intel_limit_t intel_limits_pineview_lvds = {
 259         .dot = { .min = 20000, .max = 400000 },
 260         .vco = { .min = 1700000, .max = 3500000 },
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         .m1 = { .min = 0, .max = 0 },
 264         .m2 = { .min = 0, .max = 254 },
 265         .p = { .min = 7, .max = 112 },
 266         .p1 = { .min = 1, .max = 8 },
 267         .p2 = { .dot_limit = 112000,
 268                 .p2_slow = 14, .p2_fast = 14 },
 269         .find_pll = intel_find_best_PLL,
 270 };
 271
 272 /* Ironlake / Sandybridge
 273  *
 274  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 275  * the range value for them is (actual_value - 2).
 276  */
 277 static const intel_limit_t intel_limits_ironlake_dac = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 1760000, .max = 3510000 },
 280         .n = { .min = 1, .max = 5 },
 281         .m = { .min = 79, .max = 127 },
 282         .m1 = { .min = 12, .max = 22 },
 283         .m2 = { .min = 5, .max = 9 },
 284         .p = { .min = 5, .max = 80 },
 285         .p1 = { .min = 1, .max = 8 },
 286         .p2 = { .dot_limit = 225000,
 287                 .p2_slow = 10, .p2_fast = 5 },
 288         .find_pll = intel_g4x_find_best_PLL,
 289 };
 290
 291 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 292         .dot = { .min = 25000, .max = 350000 },
 293         .vco = { .min = 1760000, .max = 3510000 },
 294         .n = { .min = 1, .max = 3 },
 295         .m = { .min = 79, .max = 118 },
 296         .m1 = { .min = 12, .max = 22 },
 297         .m2 = { .min = 5, .max = 9 },
 298         .p = { .min = 28, .max = 112 },
 299         .p1 = { .min = 2, .max = 8 },
 300         .p2 = { .dot_limit = 225000,
 301                 .p2_slow = 14, .p2_fast = 14 },
 302         .find_pll = intel_g4x_find_best_PLL,
 303 };
 304
 305 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 306         .dot = { .min = 25000, .max = 350000 },
 307         .vco = { .min = 1760000, .max = 3510000 },
 308         .n = { .min = 1, .max = 3 },
 309         .m = { .min = 79, .max = 127 },
 310         .m1 = { .min = 12, .max = 22 },
 311         .m2 = { .min = 5, .max = 9 },
 312         .p = { .min = 14, .max = 56 },
 313         .p1 = { .min = 2, .max = 8 },
 314         .p2 = { .dot_limit = 225000,
 315                 .p2_slow = 7, .p2_fast = 7 },
 316         .find_pll = intel_g4x_find_best_PLL,
 317 };
 318
 319 /* LVDS 100mhz refclk limits. */
 320 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 2 },
 324         .m = { .min = 79, .max = 126 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 14, .p2_fast = 14 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 335         .dot = { .min = 25000, .max = 350000 },
 336         .vco = { .min = 1760000, .max = 3510000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 79, .max = 126 },
 339         .m1 = { .min = 12, .max = 22 },
 340         .m2 = { .min = 5, .max = 9 },
 341         .p = { .min = 14, .max = 42 },
 342         .p1 = { .min = 2, .max = 6 },
 343         .p2 = { .dot_limit = 225000,
 344                 .p2_slow = 7, .p2_fast = 7 },
 345         .find_pll = intel_g4x_find_best_PLL,
 346 };
 347
 348 static const intel_limit_t intel_limits_ironlake_display_port = {
 349         .dot = { .min = 25000, .max = 350000 },
 350         .vco = { .min = 1760000, .max = 3510000},
 351         .n = { .min = 1, .max = 2 },
 352         .m = { .min = 81, .max = 90 },
 353         .m1 = { .min = 12, .max = 22 },
 354         .m2 = { .min = 5, .max = 9 },
 355         .p = { .min = 10, .max = 20 },
 356         .p1 = { .min = 1, .max = 2},
 357         .p2 = { .dot_limit = 0,
 358                 .p2_slow = 10, .p2_fast = 10 },
 359         .find_pll = intel_find_pll_ironlake_dp,
 360 };
 361
 362 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 363 {
 364         unsigned long flags;
 365         u32 val = 0;
 366
 367         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 368         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 369                 DRM_ERROR("DPIO idle wait timed out\n");
 370                 goto out_unlock;
 371         }
 372
 373         I915_WRITE(DPIO_REG, reg);
 374         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 375                    DPIO_BYTE);
 376         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 377                 DRM_ERROR("DPIO read wait timed out\n");
 378                 goto out_unlock;
 379         }
 380         val = I915_READ(DPIO_DATA);
 381
 382 out_unlock:
 383         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 384         return val;
 385 }
 386
 387 static void vlv_init_dpio(struct drm_device *dev)
 388 {
 389         struct drm_i915_private *dev_priv = dev->dev_private;
 390
 391         /* Reset the DPIO config */
 392         I915_WRITE(DPIO_CTL, 0);
 393         POSTING_READ(DPIO_CTL);
 394         I915_WRITE(DPIO_CTL, 1);
 395         POSTING_READ(DPIO_CTL);
 396 }
 397
 398 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 399 {
 400         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 401         return 1;
 402 }
 403
 404 static const struct dmi_system_id intel_dual_link_lvds[] = {
 405         {
 406                 .callback = intel_dual_link_lvds_callback,
 407                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 408                 .matches = {
 409                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 410                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 411                 },
 412         },
 413         { }     /* terminating entry */
 414 };
 415
 416 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 417                               unsigned int reg)
 418 {
 419         unsigned int val;
 420
 421         /* use the module option value if specified */
 422         if (i915_lvds_channel_mode > 0)
 423                 return i915_lvds_channel_mode == 2;
 424
 425         if (dmi_check_system(intel_dual_link_lvds))
 426                 return true;
 427
 428         if (dev_priv->lvds_val)
 429                 val = dev_priv->lvds_val;
 430         else {
 431                 /* BIOS should set the proper LVDS register value at boot, but
 432                  * in reality, it doesn't set the value when the lid is closed;
 433                  * we need to check "the value to be set" in VBT when LVDS
 434                  * register is uninitialized.
 435                  */
 436                 val = I915_READ(reg);
 437                 if (!(val & ~LVDS_DETECTED))
 438                         val = dev_priv->bios_lvds_val;
 439                 dev_priv->lvds_val = val;
 440         }
 441         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 442 }
 443
 444 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 445                                                 int refclk)
 446 {
 447         struct drm_device *dev = crtc->dev;
 448         struct drm_i915_private *dev_priv = dev->dev_private;
 449         const intel_limit_t *limit;
 450
 451         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 452                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 453                         /* LVDS dual channel */
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_dual_lvds;
 458                 } else {
 459                         if (refclk == 100000)
 460                                 limit = &intel_limits_ironlake_single_lvds_100m;
 461                         else
 462                                 limit = &intel_limits_ironlake_single_lvds;
 463                 }
 464         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 465                         HAS_eDP)
 466                 limit = &intel_limits_ironlake_display_port;
 467         else
 468                 limit = &intel_limits_ironlake_dac;
 469
 470         return limit;
 471 }
 472
 473 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 474 {
 475         struct drm_device *dev = crtc->dev;
 476         struct drm_i915_private *dev_priv = dev->dev_private;
 477         const intel_limit_t *limit;
 478
 479         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 480                 if (is_dual_link_lvds(dev_priv, LVDS))
 481                         /* LVDS with dual channel */
 482                         limit = &intel_limits_g4x_dual_channel_lvds;
 483                 else
 484                         /* LVDS with dual channel */
 485                         limit = &intel_limits_g4x_single_channel_lvds;
 486         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 487                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 488                 limit = &intel_limits_g4x_hdmi;
 489         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 490                 limit = &intel_limits_g4x_sdvo;
 491         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 492                 limit = &intel_limits_g4x_display_port;
 493         } else /* The option is for other outputs */
 494                 limit = &intel_limits_i9xx_sdvo;
 495
 496         return limit;
 497 }
 498
 499 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 500 {
 501         struct drm_device *dev = crtc->dev;
 502         const intel_limit_t *limit;
 503
 504         if (HAS_PCH_SPLIT(dev))
 505                 limit = intel_ironlake_limit(crtc, refclk);
 506         else if (IS_G4X(dev)) {
 507                 limit = intel_g4x_limit(crtc);
 508         } else if (IS_PINEVIEW(dev)) {
 509                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 510                         limit = &intel_limits_pineview_lvds;
 511                 else
 512                         limit = &intel_limits_pineview_sdvo;
 513         } else if (!IS_GEN2(dev)) {
 514                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 515                         limit = &intel_limits_i9xx_lvds;
 516                 else
 517                         limit = &intel_limits_i9xx_sdvo;
 518         } else {
 519                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 520                         limit = &intel_limits_i8xx_lvds;
 521                 else
 522                         limit = &intel_limits_i8xx_dvo;
 523         }
 524         return limit;
 525 }
 526
 527 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 528 static void pineview_clock(int refclk, intel_clock_t *clock)
 529 {
 530         clock->m = clock->m2 + 2;
 531         clock->p = clock->p1 * clock->p2;
 532         clock->vco = refclk * clock->m / clock->n;
 533         clock->dot = clock->vco / clock->p;
 534 }
 535
 536 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 537 {
 538         if (IS_PINEVIEW(dev)) {
 539                 pineview_clock(refclk, clock);
 540                 return;
 541         }
 542         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 543         clock->p = clock->p1 * clock->p2;
 544         clock->vco = refclk * clock->m / (clock->n + 2);
 545         clock->dot = clock->vco / clock->p;
 546 }
 547
 548 /**
 549  * Returns whether any output on the specified pipe is of the specified type
 550  */
 551 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 552 {
 553         struct drm_device *dev = crtc->dev;
 554         struct drm_mode_config *mode_config = &dev->mode_config;
 555         struct intel_encoder *encoder;
 556
 557         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 558                 if (encoder->base.crtc == crtc && encoder->type == type)
 559                         return true;
 560
 561         return false;
 562 }
 563
 564 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 565 /**
 566  * Returns whether the given set of divisors are valid for a given refclk with
 567  * the given connectors.
 568  */
 569
 570 static bool intel_PLL_is_valid(struct drm_device *dev,
 571                                const intel_limit_t *limit,
 572                                const intel_clock_t *clock)
 573 {
 574         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 575                 INTELPllInvalid("p1 out of range\n");
 576         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 577                 INTELPllInvalid("p out of range\n");
 578         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 579                 INTELPllInvalid("m2 out of range\n");
 580         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 581                 INTELPllInvalid("m1 out of range\n");
 582         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 583                 INTELPllInvalid("m1 <= m2\n");
 584         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 585                 INTELPllInvalid("m out of range\n");
 586         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 587                 INTELPllInvalid("n out of range\n");
 588         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 589                 INTELPllInvalid("vco out of range\n");
 590         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 591          * connector, etc., rather than just a single range.
 592          */
 593         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 594                 INTELPllInvalid("dot out of range\n");
 595
 596         return true;
 597 }
 598
 599 static bool
 600 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 601                     int target, int refclk, intel_clock_t *match_clock,
 602                     intel_clock_t *best_clock)
 603
 604 {
 605         struct drm_device *dev = crtc->dev;
 606         struct drm_i915_private *dev_priv = dev->dev_private;
 607         intel_clock_t clock;
 608         int err = target;
 609
 610         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 611             (I915_READ(LVDS)) != 0) {
 612                 /*
 613                  * For LVDS, if the panel is on, just rely on its current
 614                  * settings for dual-channel.  We haven't figured out how to
 615                  * reliably set up different single/dual channel state, if we
 616                  * even can.
 617                  */
 618                 if (is_dual_link_lvds(dev_priv, LVDS))
 619                         clock.p2 = limit->p2.p2_fast;
 620                 else
 621                         clock.p2 = limit->p2.p2_slow;
 622         } else {
 623                 if (target < limit->p2.dot_limit)
 624                         clock.p2 = limit->p2.p2_slow;
 625                 else
 626                         clock.p2 = limit->p2.p2_fast;
 627         }
 628
 629         memset(best_clock, 0, sizeof(*best_clock));
 630
 631         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 632              clock.m1++) {
 633                 for (clock.m2 = limit->m2.min;
 634                      clock.m2 <= limit->m2.max; clock.m2++) {
 635                         /* m1 is always 0 in Pineview */
 636                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 637                                 break;
 638                         for (clock.n = limit->n.min;
 639                              clock.n <= limit->n.max; clock.n++) {
 640                                 for (clock.p1 = limit->p1.min;
 641                                         clock.p1 <= limit->p1.max; clock.p1++) {
 642                                         int this_err;
 643
 644                                         intel_clock(dev, refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648                                         if (match_clock &&
 649                                             clock.p != match_clock->p)
 650                                                 continue;
 651
 652                                         this_err = abs(clock.dot - target);
 653                                         if (this_err < err) {
 654                                                 *best_clock = clock;
 655                                                 err = this_err;
 656                                         }
 657                                 }
 658                         }
 659                 }
 660         }
 661
 662         return (err != target);
 663 }
 664
 665 static bool
 666 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 667                         int target, int refclk, intel_clock_t *match_clock,
 668                         intel_clock_t *best_clock)
 669 {
 670         struct drm_device *dev = crtc->dev;
 671         struct drm_i915_private *dev_priv = dev->dev_private;
 672         intel_clock_t clock;
 673         int max_n;
 674         bool found;
 675         /* approximately equals target * 0.00585 */
 676         int err_most = (target >> 8) + (target >> 9);
 677         found = false;
 678
 679         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 680                 int lvds_reg;
 681
 682                 if (HAS_PCH_SPLIT(dev))
 683                         lvds_reg = PCH_LVDS;
 684                 else
 685                         lvds_reg = LVDS;
 686                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 687                     LVDS_CLKB_POWER_UP)
 688                         clock.p2 = limit->p2.p2_fast;
 689                 else
 690                         clock.p2 = limit->p2.p2_slow;
 691         } else {
 692                 if (target < limit->p2.dot_limit)
 693                         clock.p2 = limit->p2.p2_slow;
 694                 else
 695                         clock.p2 = limit->p2.p2_fast;
 696         }
 697
 698         memset(best_clock, 0, sizeof(*best_clock));
 699         max_n = limit->n.max;
 700         /* based on hardware requirement, prefer smaller n to precision */
 701         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 702                 /* based on hardware requirement, prefere larger m1,m2 */
 703                 for (clock.m1 = limit->m1.max;
 704                      clock.m1 >= limit->m1.min; clock.m1--) {
 705                         for (clock.m2 = limit->m2.max;
 706                              clock.m2 >= limit->m2.min; clock.m2--) {
 707                                 for (clock.p1 = limit->p1.max;
 708                                      clock.p1 >= limit->p1.min; clock.p1--) {
 709                                         int this_err;
 710
 711                                         intel_clock(dev, refclk, &clock);
 712                                         if (!intel_PLL_is_valid(dev, limit,
 713                                                                 &clock))
 714                                                 continue;
 715                                         if (match_clock &&
 716                                             clock.p != match_clock->p)
 717                                                 continue;
 718
 719                                         this_err = abs(clock.dot - target);
 720                                         if (this_err < err_most) {
 721                                                 *best_clock = clock;
 722                                                 err_most = this_err;
 723                                                 max_n = clock.n;
 724                                                 found = true;
 725                                         }
 726                                 }
 727                         }
 728                 }
 729         }
 730         return found;
 731 }
 732
 733 static bool
 734 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 735                            int target, int refclk, intel_clock_t *match_clock,
 736                            intel_clock_t *best_clock)
 737 {
 738         struct drm_device *dev = crtc->dev;
 739         intel_clock_t clock;
 740
 741         if (target < 200000) {
 742                 clock.n = 1;
 743                 clock.p1 = 2;
 744                 clock.p2 = 10;
 745                 clock.m1 = 12;
 746                 clock.m2 = 9;
 747         } else {
 748                 clock.n = 2;
 749                 clock.p1 = 1;
 750                 clock.p2 = 10;
 751                 clock.m1 = 14;
 752                 clock.m2 = 8;
 753         }
 754         intel_clock(dev, refclk, &clock);
 755         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 756         return true;
 757 }
 758
 759 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 760 static bool
 761 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 762                       int target, int refclk, intel_clock_t *match_clock,
 763                       intel_clock_t *best_clock)
 764 {
 765         intel_clock_t clock;
 766         if (target < 200000) {
 767                 clock.p1 = 2;
 768                 clock.p2 = 10;
 769                 clock.n = 2;
 770                 clock.m1 = 23;
 771                 clock.m2 = 8;
 772         } else {
 773                 clock.p1 = 1;
 774                 clock.p2 = 10;
 775                 clock.n = 1;
 776                 clock.m1 = 14;
 777                 clock.m2 = 2;
 778         }
 779         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 780         clock.p = (clock.p1 * clock.p2);
 781         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 782         clock.vco = 0;
 783         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 784         return true;
 785 }
 786
 787 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 788 {
 789         struct drm_i915_private *dev_priv = dev->dev_private;
 790         u32 frame, frame_reg = PIPEFRAME(pipe);
 791
 792         frame = I915_READ(frame_reg);
 793
 794         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 795                 DRM_DEBUG_KMS("vblank wait timed out\n");
 796 }
 797
 798 /**
 799  * intel_wait_for_vblank - wait for vblank on a given pipe
 800  * @dev: drm device
 801  * @pipe: pipe to wait for
 802  *
 803  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 804  * mode setting code.
 805  */
 806 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 807 {
 808         struct drm_i915_private *dev_priv = dev->dev_private;
 809         int pipestat_reg = PIPESTAT(pipe);
 810
 811         if (INTEL_INFO(dev)->gen >= 5) {
 812                 ironlake_wait_for_vblank(dev, pipe);
 813                 return;
 814         }
 815
 816         /* Clear existing vblank status. Note this will clear any other
 817          * sticky status fields as well.
 818          *
 819          * This races with i915_driver_irq_handler() with the result
 820          * that either function could miss a vblank event.  Here it is not
 821          * fatal, as we will either wait upon the next vblank interrupt or
 822          * timeout.  Generally speaking intel_wait_for_vblank() is only
 823          * called during modeset at which time the GPU should be idle and
 824          * should *not* be performing page flips and thus not waiting on
 825          * vblanks...
 826          * Currently, the result of us stealing a vblank from the irq
 827          * handler is that a single frame will be skipped during swapbuffers.
 828          */
 829         I915_WRITE(pipestat_reg,
 830                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 831
 832         /* Wait for vblank interrupt bit to set */
 833         if (wait_for(I915_READ(pipestat_reg) &
 834                      PIPE_VBLANK_INTERRUPT_STATUS,
 835                      50))
 836                 DRM_DEBUG_KMS("vblank wait timed out\n");
 837 }
 838
 839 /*
 840  * intel_wait_for_pipe_off - wait for pipe to turn off
 841  * @dev: drm device
 842  * @pipe: pipe to wait for
 843  *
 844  * After disabling a pipe, we can't wait for vblank in the usual way,
 845  * spinning on the vblank interrupt status bit, since we won't actually
 846  * see an interrupt when the pipe is disabled.
 847  *
 848  * On Gen4 and above:
 849  *   wait for the pipe register state bit to turn off
 850  *
 851  * Otherwise:
 852  *   wait for the display line value to settle (it usually
 853  *   ends up stopping at the start of the next frame).
 854  *
 855  */
 856 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 857 {
 858         struct drm_i915_private *dev_priv = dev->dev_private;
 859
 860         if (INTEL_INFO(dev)->gen >= 4) {
 861                 int reg = PIPECONF(pipe);
 862
 863                 /* Wait for the Pipe State to go off */
 864                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 865                              100))
 866                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 867         } else {
 868                 u32 last_line, line_mask;
 869                 int reg = PIPEDSL(pipe);
 870                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 871
 872                 if (IS_GEN2(dev))
 873                         line_mask = DSL_LINEMASK_GEN2;
 874                 else
 875                         line_mask = DSL_LINEMASK_GEN3;
 876
 877                 /* Wait for the display line to settle */
 878                 do {
 879                         last_line = I915_READ(reg) & line_mask;
 880                         mdelay(5);
 881                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 882                          time_after(timeout, jiffies));
 883                 if (time_after(jiffies, timeout))
 884                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 885         }
 886 }
 887
 888 static const char *state_string(bool enabled)
 889 {
 890         return enabled ? "on" : "off";
 891 }
 892
 893 /* Only for pre-ILK configs */
 894 static void assert_pll(struct drm_i915_private *dev_priv,
 895                        enum pipe pipe, bool state)
 896 {
 897         int reg;
 898         u32 val;
 899         bool cur_state;
 900
 901         reg = DPLL(pipe);
 902         val = I915_READ(reg);
 903         cur_state = !!(val & DPLL_VCO_ENABLE);
 904         WARN(cur_state != state,
 905              "PLL state assertion failure (expected %s, current %s)\n",
 906              state_string(state), state_string(cur_state));
 907 }
 908 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 909 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 910
 911 /* For ILK+ */
 912 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 913                            struct intel_pch_pll *pll,
 914                            struct intel_crtc *crtc,
 915                            bool state)
 916 {
 917         u32 val;
 918         bool cur_state;
 919
 920         if (HAS_PCH_LPT(dev_priv->dev)) {
 921                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 922                 return;
 923         }
 924
 925         if (WARN (!pll,
 926                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
 927                 return;
 928
 929         val = I915_READ(pll->pll_reg);
 930         cur_state = !!(val & DPLL_VCO_ENABLE);
 931         WARN(cur_state != state,
 932              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
 933              pll->pll_reg, state_string(state), state_string(cur_state), val);
 934
 935         /* Make sure the selected PLL is correctly attached to the transcoder */
 936         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
 937                 u32 pch_dpll;
 938
 939                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 940                 cur_state = pll->pll_reg == _PCH_DPLL_B;
 941                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 942                           "PLL[%d] not attached to this transcoder %d: %08x\n",
 943                           cur_state, crtc->pipe, pch_dpll)) {
 944                         cur_state = !!(val >> (4*crtc->pipe + 3));
 945                         WARN(cur_state != state,
 946                              "PLL[%d] not %s on this transcoder %d: %08x\n",
 947                              pll->pll_reg == _PCH_DPLL_B,
 948                              state_string(state),
 949                              crtc->pipe,
 950                              val);
 951                 }
 952         }
 953 }
 954 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
 955 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
 956
 957 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 958                           enum pipe pipe, bool state)
 959 {
 960         int reg;
 961         u32 val;
 962         bool cur_state;
 963
 964         if (IS_HASWELL(dev_priv->dev)) {
 965                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
 966                 reg = DDI_FUNC_CTL(pipe);
 967                 val = I915_READ(reg);
 968                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
 969         } else {
 970                 reg = FDI_TX_CTL(pipe);
 971                 val = I915_READ(reg);
 972                 cur_state = !!(val & FDI_TX_ENABLE);
 973         }
 974         WARN(cur_state != state,
 975              "FDI TX state assertion failure (expected %s, current %s)\n",
 976              state_string(state), state_string(cur_state));
 977 }
 978 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 979 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 980
 981 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 982                           enum pipe pipe, bool state)
 983 {
 984         int reg;
 985         u32 val;
 986         bool cur_state;
 987
 988         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
 989                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
 990                         return;
 991         } else {
 992                 reg = FDI_RX_CTL(pipe);
 993                 val = I915_READ(reg);
 994                 cur_state = !!(val & FDI_RX_ENABLE);
 995         }
 996         WARN(cur_state != state,
 997              "FDI RX state assertion failure (expected %s, current %s)\n",
 998              state_string(state), state_string(cur_state));
 999 }
1000 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1001 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1002
1003 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1004                                       enum pipe pipe)
1005 {
1006         int reg;
1007         u32 val;
1008
1009         /* ILK FDI PLL is always enabled */
1010         if (dev_priv->info->gen == 5)
1011                 return;
1012
1013         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1014         if (IS_HASWELL(dev_priv->dev))
1015                 return;
1016
1017         reg = FDI_TX_CTL(pipe);
1018         val = I915_READ(reg);
1019         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1020 }
1021
1022 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1023                                       enum pipe pipe)
1024 {
1025         int reg;
1026         u32 val;
1027
1028         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1029                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1030                 return;
1031         }
1032         reg = FDI_RX_CTL(pipe);
1033         val = I915_READ(reg);
1034         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1035 }
1036
1037 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1038                                   enum pipe pipe)
1039 {
1040         int pp_reg, lvds_reg;
1041         u32 val;
1042         enum pipe panel_pipe = PIPE_A;
1043         bool locked = true;
1044
1045         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1046                 pp_reg = PCH_PP_CONTROL;
1047                 lvds_reg = PCH_LVDS;
1048         } else {
1049                 pp_reg = PP_CONTROL;
1050                 lvds_reg = LVDS;
1051         }
1052
1053         val = I915_READ(pp_reg);
1054         if (!(val & PANEL_POWER_ON) ||
1055             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1056                 locked = false;
1057
1058         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1059                 panel_pipe = PIPE_B;
1060
1061         WARN(panel_pipe == pipe && locked,
1062              "panel assertion failure, pipe %c regs locked\n",
1063              pipe_name(pipe));
1064 }
1065
1066 void assert_pipe(struct drm_i915_private *dev_priv,
1067                  enum pipe pipe, bool state)
1068 {
1069         int reg;
1070         u32 val;
1071         bool cur_state;
1072
1073         /* if we need the pipe A quirk it must be always on */
1074         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1075                 state = true;
1076
1077         reg = PIPECONF(pipe);
1078         val = I915_READ(reg);
1079         cur_state = !!(val & PIPECONF_ENABLE);
1080         WARN(cur_state != state,
1081              "pipe %c assertion failure (expected %s, current %s)\n",
1082              pipe_name(pipe), state_string(state), state_string(cur_state));
1083 }
1084
1085 static void assert_plane(struct drm_i915_private *dev_priv,
1086                          enum plane plane, bool state)
1087 {
1088         int reg;
1089         u32 val;
1090         bool cur_state;
1091
1092         reg = DSPCNTR(plane);
1093         val = I915_READ(reg);
1094         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1095         WARN(cur_state != state,
1096              "plane %c assertion failure (expected %s, current %s)\n",
1097              plane_name(plane), state_string(state), state_string(cur_state));
1098 }
1099
1100 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1101 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1102
1103 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1104                                    enum pipe pipe)
1105 {
1106         int reg, i;
1107         u32 val;
1108         int cur_pipe;
1109
1110         /* Planes are fixed to pipes on ILK+ */
1111         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1112                 reg = DSPCNTR(pipe);
1113                 val = I915_READ(reg);
1114                 WARN((val & DISPLAY_PLANE_ENABLE),
1115                      "plane %c assertion failure, should be disabled but not\n",
1116                      plane_name(pipe));
1117                 return;
1118         }
1119
1120         /* Need to check both planes against the pipe */
1121         for (i = 0; i < 2; i++) {
1122                 reg = DSPCNTR(i);
1123                 val = I915_READ(reg);
1124                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1125                         DISPPLANE_SEL_PIPE_SHIFT;
1126                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1127                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1128                      plane_name(i), pipe_name(pipe));
1129         }
1130 }
1131
1132 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1133 {
1134         u32 val;
1135         bool enabled;
1136
1137         if (HAS_PCH_LPT(dev_priv->dev)) {
1138                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1139                 return;
1140         }
1141
1142         val = I915_READ(PCH_DREF_CONTROL);
1143         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1144                             DREF_SUPERSPREAD_SOURCE_MASK));
1145         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1146 }
1147
1148 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1149                                        enum pipe pipe)
1150 {
1151         int reg;
1152         u32 val;
1153         bool enabled;
1154
1155         reg = TRANSCONF(pipe);
1156         val = I915_READ(reg);
1157         enabled = !!(val & TRANS_ENABLE);
1158         WARN(enabled,
1159              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1160              pipe_name(pipe));
1161 }
1162
1163 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1164                             enum pipe pipe, u32 port_sel, u32 val)
1165 {
1166         if ((val & DP_PORT_EN) == 0)
1167                 return false;
1168
1169         if (HAS_PCH_CPT(dev_priv->dev)) {
1170                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1171                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1172                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1173                         return false;
1174         } else {
1175                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1176                         return false;
1177         }
1178         return true;
1179 }
1180
1181 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1182                               enum pipe pipe, u32 val)
1183 {
1184         if ((val & PORT_ENABLE) == 0)
1185                 return false;
1186
1187         if (HAS_PCH_CPT(dev_priv->dev)) {
1188                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1189                         return false;
1190         } else {
1191                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1192                         return false;
1193         }
1194         return true;
1195 }
1196
1197 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1198                               enum pipe pipe, u32 val)
1199 {
1200         if ((val & LVDS_PORT_EN) == 0)
1201                 return false;
1202
1203         if (HAS_PCH_CPT(dev_priv->dev)) {
1204                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1205                         return false;
1206         } else {
1207                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1208                         return false;
1209         }
1210         return true;
1211 }
1212
1213 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1214                               enum pipe pipe, u32 val)
1215 {
1216         if ((val & ADPA_DAC_ENABLE) == 0)
1217                 return false;
1218         if (HAS_PCH_CPT(dev_priv->dev)) {
1219                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1220                         return false;
1221         } else {
1222                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1223                         return false;
1224         }
1225         return true;
1226 }
1227
1228 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1229                                    enum pipe pipe, int reg, u32 port_sel)
1230 {
1231         u32 val = I915_READ(reg);
1232         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1233              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1234              reg, pipe_name(pipe));
1235 }
1236
1237 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1238                                      enum pipe pipe, int reg)
1239 {
1240         u32 val = I915_READ(reg);
1241         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1242              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1243              reg, pipe_name(pipe));
1244 }
1245
1246 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1247                                       enum pipe pipe)
1248 {
1249         int reg;
1250         u32 val;
1251
1252         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1253         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1254         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1255
1256         reg = PCH_ADPA;
1257         val = I915_READ(reg);
1258         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1259              "PCH VGA enabled on transcoder %c, should be disabled\n",
1260              pipe_name(pipe));
1261
1262         reg = PCH_LVDS;
1263         val = I915_READ(reg);
1264         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1265              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1266              pipe_name(pipe));
1267
1268         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1269         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1270         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1271 }
1272
1273 /**
1274  * intel_enable_pll - enable a PLL
1275  * @dev_priv: i915 private structure
1276  * @pipe: pipe PLL to enable
1277  *
1278  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1279  * make sure the PLL reg is writable first though, since the panel write
1280  * protect mechanism may be enabled.
1281  *
1282  * Note!  This is for pre-ILK only.
1283  */
1284 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1285 {
1286         int reg;
1287         u32 val;
1288
1289         /* No really, not for ILK+ */
1290         BUG_ON(dev_priv->info->gen >= 5);
1291
1292         /* PLL is protected by panel, make sure we can write it */
1293         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1294                 assert_panel_unlocked(dev_priv, pipe);
1295
1296         reg = DPLL(pipe);
1297         val = I915_READ(reg);
1298         val |= DPLL_VCO_ENABLE;
1299
1300         /* We do this three times for luck */
1301         I915_WRITE(reg, val);
1302         POSTING_READ(reg);
1303         udelay(150); /* wait for warmup */
1304         I915_WRITE(reg, val);
1305         POSTING_READ(reg);
1306         udelay(150); /* wait for warmup */
1307         I915_WRITE(reg, val);
1308         POSTING_READ(reg);
1309         udelay(150); /* wait for warmup */
1310 }
1311
1312 /**
1313  * intel_disable_pll - disable a PLL
1314  * @dev_priv: i915 private structure
1315  * @pipe: pipe PLL to disable
1316  *
1317  * Disable the PLL for @pipe, making sure the pipe is off first.
1318  *
1319  * Note!  This is for pre-ILK only.
1320  */
1321 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1322 {
1323         int reg;
1324         u32 val;
1325
1326         /* Don't disable pipe A or pipe A PLLs if needed */
1327         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1328                 return;
1329
1330         /* Make sure the pipe isn't still relying on us */
1331         assert_pipe_disabled(dev_priv, pipe);
1332
1333         reg = DPLL(pipe);
1334         val = I915_READ(reg);
1335         val &= ~DPLL_VCO_ENABLE;
1336         I915_WRITE(reg, val);
1337         POSTING_READ(reg);
1338 }
1339
1340 /* SBI access */
1341 static void
1342 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1343 {
1344         unsigned long flags;
1345
1346         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1347         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1348                                 100)) {
1349                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1350                 goto out_unlock;
1351         }
1352
1353         I915_WRITE(SBI_ADDR,
1354                         (reg << 16));
1355         I915_WRITE(SBI_DATA,
1356                         value);
1357         I915_WRITE(SBI_CTL_STAT,
1358                         SBI_BUSY |
1359                         SBI_CTL_OP_CRWR);
1360
1361         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1362                                 100)) {
1363                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1364                 goto out_unlock;
1365         }
1366
1367 out_unlock:
1368         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1369 }
1370
1371 static u32
1372 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1373 {
1374         unsigned long flags;
1375         u32 value;
1376
1377         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1378         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1379                                 100)) {
1380                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1381                 goto out_unlock;
1382         }
1383
1384         I915_WRITE(SBI_ADDR,
1385                         (reg << 16));
1386         I915_WRITE(SBI_CTL_STAT,
1387                         SBI_BUSY |
1388                         SBI_CTL_OP_CRRD);
1389
1390         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1391                                 100)) {
1392                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1393                 goto out_unlock;
1394         }
1395
1396         value = I915_READ(SBI_DATA);
1397
1398 out_unlock:
1399         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1400         return value;
1401 }
1402
1403 /**
1404  * intel_enable_pch_pll - enable PCH PLL
1405  * @dev_priv: i915 private structure
1406  * @pipe: pipe PLL to enable
1407  *
1408  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1409  * drives the transcoder clock.
1410  */
1411 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1412 {
1413         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1414         struct intel_pch_pll *pll;
1415         int reg;
1416         u32 val;
1417
1418         /* PCH PLLs only available on ILK, SNB and IVB */
1419         BUG_ON(dev_priv->info->gen < 5);
1420         pll = intel_crtc->pch_pll;
1421         if (pll == NULL)
1422                 return;
1423
1424         if (WARN_ON(pll->refcount == 0))
1425                 return;
1426
1427         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1428                       pll->pll_reg, pll->active, pll->on,
1429                       intel_crtc->base.base.id);
1430
1431         /* PCH refclock must be enabled first */
1432         assert_pch_refclk_enabled(dev_priv);
1433
1434         if (pll->active++ && pll->on) {
1435                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1436                 return;
1437         }
1438
1439         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1440
1441         reg = pll->pll_reg;
1442         val = I915_READ(reg);
1443         val |= DPLL_VCO_ENABLE;
1444         I915_WRITE(reg, val);
1445         POSTING_READ(reg);
1446         udelay(200);
1447
1448         pll->on = true;
1449 }
1450
1451 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1452 {
1453         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1454         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1455         int reg;
1456         u32 val;
1457
1458         /* PCH only available on ILK+ */
1459         BUG_ON(dev_priv->info->gen < 5);
1460         if (pll == NULL)
1461                return;
1462
1463         if (WARN_ON(pll->refcount == 0))
1464                 return;
1465
1466         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1467                       pll->pll_reg, pll->active, pll->on,
1468                       intel_crtc->base.base.id);
1469
1470         if (WARN_ON(pll->active == 0)) {
1471                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1472                 return;
1473         }
1474
1475         if (--pll->active) {
1476                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1477                 return;
1478         }
1479
1480         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1481
1482         /* Make sure transcoder isn't still depending on us */
1483         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1484
1485         reg = pll->pll_reg;
1486         val = I915_READ(reg);
1487         val &= ~DPLL_VCO_ENABLE;
1488         I915_WRITE(reg, val);
1489         POSTING_READ(reg);
1490         udelay(200);
1491
1492         pll->on = false;
1493 }
1494
1495 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1496                                     enum pipe pipe)
1497 {
1498         int reg;
1499         u32 val, pipeconf_val;
1500         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1501
1502         /* PCH only available on ILK+ */
1503         BUG_ON(dev_priv->info->gen < 5);
1504
1505         /* Make sure PCH DPLL is enabled */
1506         assert_pch_pll_enabled(dev_priv,
1507                                to_intel_crtc(crtc)->pch_pll,
1508                                to_intel_crtc(crtc));
1509
1510         /* FDI must be feeding us bits for PCH ports */
1511         assert_fdi_tx_enabled(dev_priv, pipe);
1512         assert_fdi_rx_enabled(dev_priv, pipe);
1513
1514         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1515                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1516                 return;
1517         }
1518         reg = TRANSCONF(pipe);
1519         val = I915_READ(reg);
1520         pipeconf_val = I915_READ(PIPECONF(pipe));
1521
1522         if (HAS_PCH_IBX(dev_priv->dev)) {
1523                 /*
1524                  * make the BPC in transcoder be consistent with
1525                  * that in pipeconf reg.
1526                  */
1527                 val &= ~PIPE_BPC_MASK;
1528                 val |= pipeconf_val & PIPE_BPC_MASK;
1529         }
1530
1531         val &= ~TRANS_INTERLACE_MASK;
1532         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1533                 if (HAS_PCH_IBX(dev_priv->dev) &&
1534                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1535                         val |= TRANS_LEGACY_INTERLACED_ILK;
1536                 else
1537                         val |= TRANS_INTERLACED;
1538         else
1539                 val |= TRANS_PROGRESSIVE;
1540
1541         I915_WRITE(reg, val | TRANS_ENABLE);
1542         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1543                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1544 }
1545
1546 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1547                                      enum pipe pipe)
1548 {
1549         int reg;
1550         u32 val;
1551
1552         /* FDI relies on the transcoder */
1553         assert_fdi_tx_disabled(dev_priv, pipe);
1554         assert_fdi_rx_disabled(dev_priv, pipe);
1555
1556         /* Ports must be off as well */
1557         assert_pch_ports_disabled(dev_priv, pipe);
1558
1559         reg = TRANSCONF(pipe);
1560         val = I915_READ(reg);
1561         val &= ~TRANS_ENABLE;
1562         I915_WRITE(reg, val);
1563         /* wait for PCH transcoder off, transcoder state */
1564         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1565                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1566 }
1567
1568 /**
1569  * intel_enable_pipe - enable a pipe, asserting requirements
1570  * @dev_priv: i915 private structure
1571  * @pipe: pipe to enable
1572  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1573  *
1574  * Enable @pipe, making sure that various hardware specific requirements
1575  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1576  *
1577  * @pipe should be %PIPE_A or %PIPE_B.
1578  *
1579  * Will wait until the pipe is actually running (i.e. first vblank) before
1580  * returning.
1581  */
1582 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1583                               bool pch_port)
1584 {
1585         int reg;
1586         u32 val;
1587
1588         /*
1589          * A pipe without a PLL won't actually be able to drive bits from
1590          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1591          * need the check.
1592          */
1593         if (!HAS_PCH_SPLIT(dev_priv->dev))
1594                 assert_pll_enabled(dev_priv, pipe);
1595         else {
1596                 if (pch_port) {
1597                         /* if driving the PCH, we need FDI enabled */
1598                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1599                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1600                 }
1601                 /* FIXME: assert CPU port conditions for SNB+ */
1602         }
1603
1604         reg = PIPECONF(pipe);
1605         val = I915_READ(reg);
1606         if (val & PIPECONF_ENABLE)
1607                 return;
1608
1609         I915_WRITE(reg, val | PIPECONF_ENABLE);
1610         intel_wait_for_vblank(dev_priv->dev, pipe);
1611 }
1612
1613 /**
1614  * intel_disable_pipe - disable a pipe, asserting requirements
1615  * @dev_priv: i915 private structure
1616  * @pipe: pipe to disable
1617  *
1618  * Disable @pipe, making sure that various hardware specific requirements
1619  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1620  *
1621  * @pipe should be %PIPE_A or %PIPE_B.
1622  *
1623  * Will wait until the pipe has shut down before returning.
1624  */
1625 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1626                                enum pipe pipe)
1627 {
1628         int reg;
1629         u32 val;
1630
1631         /*
1632          * Make sure planes won't keep trying to pump pixels to us,
1633          * or we might hang the display.
1634          */
1635         assert_planes_disabled(dev_priv, pipe);
1636
1637         /* Don't disable pipe A or pipe A PLLs if needed */
1638         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1639                 return;
1640
1641         reg = PIPECONF(pipe);
1642         val = I915_READ(reg);
1643         if ((val & PIPECONF_ENABLE) == 0)
1644                 return;
1645
1646         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1647         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1648 }
1649
1650 /*
1651  * Plane regs are double buffered, going from enabled->disabled needs a
1652  * trigger in order to latch.  The display address reg provides this.
1653  */
1654 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1655                                       enum plane plane)
1656 {
1657         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1658         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1659 }
1660
1661 /**
1662  * intel_enable_plane - enable a display plane on a given pipe
1663  * @dev_priv: i915 private structure
1664  * @plane: plane to enable
1665  * @pipe: pipe being fed
1666  *
1667  * Enable @plane on @pipe, making sure that @pipe is running first.
1668  */
1669 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1670                                enum plane plane, enum pipe pipe)
1671 {
1672         int reg;
1673         u32 val;
1674
1675         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1676         assert_pipe_enabled(dev_priv, pipe);
1677
1678         reg = DSPCNTR(plane);
1679         val = I915_READ(reg);
1680         if (val & DISPLAY_PLANE_ENABLE)
1681                 return;
1682
1683         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1684         intel_flush_display_plane(dev_priv, plane);
1685         intel_wait_for_vblank(dev_priv->dev, pipe);
1686 }
1687
1688 /**
1689  * intel_disable_plane - disable a display plane
1690  * @dev_priv: i915 private structure
1691  * @plane: plane to disable
1692  * @pipe: pipe consuming the data
1693  *
1694  * Disable @plane; should be an independent operation.
1695  */
1696 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1697                                 enum plane plane, enum pipe pipe)
1698 {
1699         int reg;
1700         u32 val;
1701
1702         reg = DSPCNTR(plane);
1703         val = I915_READ(reg);
1704         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1705                 return;
1706
1707         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1708         intel_flush_display_plane(dev_priv, plane);
1709         intel_wait_for_vblank(dev_priv->dev, pipe);
1710 }
1711
1712 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1713                            enum pipe pipe, int reg, u32 port_sel)
1714 {
1715         u32 val = I915_READ(reg);
1716         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1717                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1718                 I915_WRITE(reg, val & ~DP_PORT_EN);
1719         }
1720 }
1721
1722 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1723                              enum pipe pipe, int reg)
1724 {
1725         u32 val = I915_READ(reg);
1726         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1727                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1728                               reg, pipe);
1729                 I915_WRITE(reg, val & ~PORT_ENABLE);
1730         }
1731 }
1732
1733 /* Disable any ports connected to this transcoder */
1734 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1735                                     enum pipe pipe)
1736 {
1737         u32 reg, val;
1738
1739         val = I915_READ(PCH_PP_CONTROL);
1740         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1741
1742         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1743         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1744         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1745
1746         reg = PCH_ADPA;
1747         val = I915_READ(reg);
1748         if (adpa_pipe_enabled(dev_priv, val, pipe))
1749                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1750
1751         reg = PCH_LVDS;
1752         val = I915_READ(reg);
1753         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1754                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1755                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1756                 POSTING_READ(reg);
1757                 udelay(100);
1758         }
1759
1760         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1761         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1762         disable_pch_hdmi(dev_priv, pipe, HDMID);
1763 }
1764
1765 int
1766 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1767                            struct drm_i915_gem_object *obj,
1768                            struct intel_ring_buffer *pipelined)
1769 {
1770         struct drm_i915_private *dev_priv = dev->dev_private;
1771         u32 alignment;
1772         int ret;
1773
1774         switch (obj->tiling_mode) {
1775         case I915_TILING_NONE:
1776                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1777                         alignment = 128 * 1024;
1778                 else if (INTEL_INFO(dev)->gen >= 4)
1779                         alignment = 4 * 1024;
1780                 else
1781                         alignment = 64 * 1024;
1782                 break;
1783         case I915_TILING_X:
1784                 /* pin() will align the object as required by fence */
1785                 alignment = 0;
1786                 break;
1787         case I915_TILING_Y:
1788                 /* FIXME: Is this true? */
1789                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1790                 return -EINVAL;
1791         default:
1792                 BUG();
1793         }
1794
1795         dev_priv->mm.interruptible = false;
1796         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1797         if (ret)
1798                 goto err_interruptible;
1799
1800         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1801          * fence, whereas 965+ only requires a fence if using
1802          * framebuffer compression.  For simplicity, we always install
1803          * a fence as the cost is not that onerous.
1804          */
1805         ret = i915_gem_object_get_fence(obj);
1806         if (ret)
1807                 goto err_unpin;
1808
1809         i915_gem_object_pin_fence(obj);
1810
1811         dev_priv->mm.interruptible = true;
1812         return 0;
1813
1814 err_unpin:
1815         i915_gem_object_unpin(obj);
1816 err_interruptible:
1817         dev_priv->mm.interruptible = true;
1818         return ret;
1819 }
1820
1821 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1822 {
1823         i915_gem_object_unpin_fence(obj);
1824         i915_gem_object_unpin(obj);
1825 }
1826
1827 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1828                              int x, int y)
1829 {
1830         struct drm_device *dev = crtc->dev;
1831         struct drm_i915_private *dev_priv = dev->dev_private;
1832         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1833         struct intel_framebuffer *intel_fb;
1834         struct drm_i915_gem_object *obj;
1835         int plane = intel_crtc->plane;
1836         unsigned long Start, Offset;
1837         u32 dspcntr;
1838         u32 reg;
1839
1840         switch (plane) {
1841         case 0:
1842         case 1:
1843                 break;
1844         default:
1845                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1846                 return -EINVAL;
1847         }
1848
1849         intel_fb = to_intel_framebuffer(fb);
1850         obj = intel_fb->obj;
1851
1852         reg = DSPCNTR(plane);
1853         dspcntr = I915_READ(reg);
1854         /* Mask out pixel format bits in case we change it */
1855         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1856         switch (fb->bits_per_pixel) {
1857         case 8:
1858                 dspcntr |= DISPPLANE_8BPP;
1859                 break;
1860         case 16:
1861                 if (fb->depth == 15)
1862                         dspcntr |= DISPPLANE_15_16BPP;
1863                 else
1864                         dspcntr |= DISPPLANE_16BPP;
1865                 break;
1866         case 24:
1867         case 32:
1868                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1869                 break;
1870         default:
1871                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1872                 return -EINVAL;
1873         }
1874         if (INTEL_INFO(dev)->gen >= 4) {
1875                 if (obj->tiling_mode != I915_TILING_NONE)
1876                         dspcntr |= DISPPLANE_TILED;
1877                 else
1878                         dspcntr &= ~DISPPLANE_TILED;
1879         }
1880
1881         I915_WRITE(reg, dspcntr);
1882
1883         Start = obj->gtt_offset;
1884         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1885
1886         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1887                       Start, Offset, x, y, fb->pitches[0]);
1888         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1889         if (INTEL_INFO(dev)->gen >= 4) {
1890                 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1891                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1892                 I915_WRITE(DSPADDR(plane), Offset);
1893         } else
1894                 I915_WRITE(DSPADDR(plane), Start + Offset);
1895         POSTING_READ(reg);
1896
1897         return 0;
1898 }
1899
1900 static int ironlake_update_plane(struct drm_crtc *crtc,
1901                                  struct drm_framebuffer *fb, int x, int y)
1902 {
1903         struct drm_device *dev = crtc->dev;
1904         struct drm_i915_private *dev_priv = dev->dev_private;
1905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1906         struct intel_framebuffer *intel_fb;
1907         struct drm_i915_gem_object *obj;
1908         int plane = intel_crtc->plane;
1909         unsigned long Start, Offset;
1910         u32 dspcntr;
1911         u32 reg;
1912
1913         switch (plane) {
1914         case 0:
1915         case 1:
1916         case 2:
1917                 break;
1918         default:
1919                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1920                 return -EINVAL;
1921         }
1922
1923         intel_fb = to_intel_framebuffer(fb);
1924         obj = intel_fb->obj;
1925
1926         reg = DSPCNTR(plane);
1927         dspcntr = I915_READ(reg);
1928         /* Mask out pixel format bits in case we change it */
1929         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1930         switch (fb->bits_per_pixel) {
1931         case 8:
1932                 dspcntr |= DISPPLANE_8BPP;
1933                 break;
1934         case 16:
1935                 if (fb->depth != 16)
1936                         return -EINVAL;
1937
1938                 dspcntr |= DISPPLANE_16BPP;
1939                 break;
1940         case 24:
1941         case 32:
1942                 if (fb->depth == 24)
1943                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1944                 else if (fb->depth == 30)
1945                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1946                 else
1947                         return -EINVAL;
1948                 break;
1949         default:
1950                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1951                 return -EINVAL;
1952         }
1953
1954         if (obj->tiling_mode != I915_TILING_NONE)
1955                 dspcntr |= DISPPLANE_TILED;
1956         else
1957                 dspcntr &= ~DISPPLANE_TILED;
1958
1959         /* must disable */
1960         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1961
1962         I915_WRITE(reg, dspcntr);
1963
1964         Start = obj->gtt_offset;
1965         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1966
1967         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1968                       Start, Offset, x, y, fb->pitches[0]);
1969         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1970         I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1971         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1972         I915_WRITE(DSPADDR(plane), Offset);
1973         POSTING_READ(reg);
1974
1975         return 0;
1976 }
1977
1978 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1979 static int
1980 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1981                            int x, int y, enum mode_set_atomic state)
1982 {
1983         struct drm_device *dev = crtc->dev;
1984         struct drm_i915_private *dev_priv = dev->dev_private;
1985
1986         if (dev_priv->display.disable_fbc)
1987                 dev_priv->display.disable_fbc(dev);
1988         intel_increase_pllclock(crtc);
1989
1990         return dev_priv->display.update_plane(crtc, fb, x, y);
1991 }
1992
1993 static int
1994 intel_finish_fb(struct drm_framebuffer *old_fb)
1995 {
1996         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1997         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1998         bool was_interruptible = dev_priv->mm.interruptible;
1999         int ret;
2000
2001         wait_event(dev_priv->pending_flip_queue,
2002                    atomic_read(&dev_priv->mm.wedged) ||
2003                    atomic_read(&obj->pending_flip) == 0);
2004
2005         /* Big Hammer, we also need to ensure that any pending
2006          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2007          * current scanout is retired before unpinning the old
2008          * framebuffer.
2009          *
2010          * This should only fail upon a hung GPU, in which case we
2011          * can safely continue.
2012          */
2013         dev_priv->mm.interruptible = false;
2014         ret = i915_gem_object_finish_gpu(obj);
2015         dev_priv->mm.interruptible = was_interruptible;
2016
2017         return ret;
2018 }
2019
2020 static int
2021 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2022                     struct drm_framebuffer *old_fb)
2023 {
2024         struct drm_device *dev = crtc->dev;
2025         struct drm_i915_private *dev_priv = dev->dev_private;
2026         struct drm_i915_master_private *master_priv;
2027         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2028         int ret;
2029
2030         /* no fb bound */
2031         if (!crtc->fb) {
2032                 DRM_ERROR("No FB bound\n");
2033                 return 0;
2034         }
2035
2036         if(intel_crtc->plane > dev_priv->num_pipe) {
2037                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2038                                 intel_crtc->plane,
2039                                 dev_priv->num_pipe);
2040                 return -EINVAL;
2041         }
2042
2043         mutex_lock(&dev->struct_mutex);
2044         ret = intel_pin_and_fence_fb_obj(dev,
2045                                          to_intel_framebuffer(crtc->fb)->obj,
2046                                          NULL);
2047         if (ret != 0) {
2048                 mutex_unlock(&dev->struct_mutex);
2049                 DRM_ERROR("pin & fence failed\n");
2050                 return ret;
2051         }
2052
2053         if (old_fb)
2054                 intel_finish_fb(old_fb);
2055
2056         ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2057         if (ret) {
2058                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2059                 mutex_unlock(&dev->struct_mutex);
2060                 DRM_ERROR("failed to update base address\n");
2061                 return ret;
2062         }
2063
2064         if (old_fb) {
2065                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2066                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2067         }
2068
2069         intel_update_fbc(dev);
2070         mutex_unlock(&dev->struct_mutex);
2071
2072         if (!dev->primary->master)
2073                 return 0;
2074
2075         master_priv = dev->primary->master->driver_priv;
2076         if (!master_priv->sarea_priv)
2077                 return 0;
2078
2079         if (intel_crtc->pipe) {
2080                 master_priv->sarea_priv->pipeB_x = x;
2081                 master_priv->sarea_priv->pipeB_y = y;
2082         } else {
2083                 master_priv->sarea_priv->pipeA_x = x;
2084                 master_priv->sarea_priv->pipeA_y = y;
2085         }
2086
2087         return 0;
2088 }
2089
2090 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2091 {
2092         struct drm_device *dev = crtc->dev;
2093         struct drm_i915_private *dev_priv = dev->dev_private;
2094         u32 dpa_ctl;
2095
2096         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2097         dpa_ctl = I915_READ(DP_A);
2098         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2099
2100         if (clock < 200000) {
2101                 u32 temp;
2102                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2103                 /* workaround for 160Mhz:
2104                    1) program 0x4600c bits 15:0 = 0x8124
2105                    2) program 0x46010 bit 0 = 1
2106                    3) program 0x46034 bit 24 = 1
2107                    4) program 0x64000 bit 14 = 1
2108                    */
2109                 temp = I915_READ(0x4600c);
2110                 temp &= 0xffff0000;
2111                 I915_WRITE(0x4600c, temp | 0x8124);
2112
2113                 temp = I915_READ(0x46010);
2114                 I915_WRITE(0x46010, temp | 1);
2115
2116                 temp = I915_READ(0x46034);
2117                 I915_WRITE(0x46034, temp | (1 << 24));
2118         } else {
2119                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2120         }
2121         I915_WRITE(DP_A, dpa_ctl);
2122
2123         POSTING_READ(DP_A);
2124         udelay(500);
2125 }
2126
2127 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2128 {
2129         struct drm_device *dev = crtc->dev;
2130         struct drm_i915_private *dev_priv = dev->dev_private;
2131         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132         int pipe = intel_crtc->pipe;
2133         u32 reg, temp;
2134
2135         /* enable normal train */
2136         reg = FDI_TX_CTL(pipe);
2137         temp = I915_READ(reg);
2138         if (IS_IVYBRIDGE(dev)) {
2139                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2140                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2141         } else {
2142                 temp &= ~FDI_LINK_TRAIN_NONE;
2143                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2144         }
2145         I915_WRITE(reg, temp);
2146
2147         reg = FDI_RX_CTL(pipe);
2148         temp = I915_READ(reg);
2149         if (HAS_PCH_CPT(dev)) {
2150                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2151                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2152         } else {
2153                 temp &= ~FDI_LINK_TRAIN_NONE;
2154                 temp |= FDI_LINK_TRAIN_NONE;
2155         }
2156         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2157
2158         /* wait one idle pattern time */
2159         POSTING_READ(reg);
2160         udelay(1000);
2161
2162         /* IVB wants error correction enabled */
2163         if (IS_IVYBRIDGE(dev))
2164                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2165                            FDI_FE_ERRC_ENABLE);
2166 }
2167
2168 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2169 {
2170         struct drm_i915_private *dev_priv = dev->dev_private;
2171         u32 flags = I915_READ(SOUTH_CHICKEN1);
2172
2173         flags |= FDI_PHASE_SYNC_OVR(pipe);
2174         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2175         flags |= FDI_PHASE_SYNC_EN(pipe);
2176         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2177         POSTING_READ(SOUTH_CHICKEN1);
2178 }
2179
2180 /* The FDI link training functions for ILK/Ibexpeak. */
2181 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2182 {
2183         struct drm_device *dev = crtc->dev;
2184         struct drm_i915_private *dev_priv = dev->dev_private;
2185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2186         int pipe = intel_crtc->pipe;
2187         int plane = intel_crtc->plane;
2188         u32 reg, temp, tries;
2189
2190         /* FDI needs bits from pipe & plane first */
2191         assert_pipe_enabled(dev_priv, pipe);
2192         assert_plane_enabled(dev_priv, plane);
2193
2194         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2195            for train result */
2196         reg = FDI_RX_IMR(pipe);
2197         temp = I915_READ(reg);
2198         temp &= ~FDI_RX_SYMBOL_LOCK;
2199         temp &= ~FDI_RX_BIT_LOCK;
2200         I915_WRITE(reg, temp);
2201         I915_READ(reg);
2202         udelay(150);
2203
2204         /* enable CPU FDI TX and PCH FDI RX */
2205         reg = FDI_TX_CTL(pipe);
2206         temp = I915_READ(reg);
2207         temp &= ~(7 << 19);
2208         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2209         temp &= ~FDI_LINK_TRAIN_NONE;
2210         temp |= FDI_LINK_TRAIN_PATTERN_1;
2211         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2212
2213         reg = FDI_RX_CTL(pipe);
2214         temp = I915_READ(reg);
2215         temp &= ~FDI_LINK_TRAIN_NONE;
2216         temp |= FDI_LINK_TRAIN_PATTERN_1;
2217         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2218
2219         POSTING_READ(reg);
2220         udelay(150);
2221
2222         /* Ironlake workaround, enable clock pointer after FDI enable*/
2223         if (HAS_PCH_IBX(dev)) {
2224                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2225                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2226                            FDI_RX_PHASE_SYNC_POINTER_EN);
2227         }
2228
2229         reg = FDI_RX_IIR(pipe);
2230         for (tries = 0; tries < 5; tries++) {
2231                 temp = I915_READ(reg);
2232                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2233
2234                 if ((temp & FDI_RX_BIT_LOCK)) {
2235                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2236                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2237                         break;
2238                 }
2239         }
2240         if (tries == 5)
2241                 DRM_ERROR("FDI train 1 fail!\n");
2242
2243         /* Train 2 */
2244         reg = FDI_TX_CTL(pipe);
2245         temp = I915_READ(reg);
2246         temp &= ~FDI_LINK_TRAIN_NONE;
2247         temp |= FDI_LINK_TRAIN_PATTERN_2;
2248         I915_WRITE(reg, temp);
2249
2250         reg = FDI_RX_CTL(pipe);
2251         temp = I915_READ(reg);
2252         temp &= ~FDI_LINK_TRAIN_NONE;
2253         temp |= FDI_LINK_TRAIN_PATTERN_2;
2254         I915_WRITE(reg, temp);
2255
2256         POSTING_READ(reg);
2257         udelay(150);
2258
2259         reg = FDI_RX_IIR(pipe);
2260         for (tries = 0; tries < 5; tries++) {
2261                 temp = I915_READ(reg);
2262                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2263
2264                 if (temp & FDI_RX_SYMBOL_LOCK) {
2265                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2266                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2267                         break;
2268                 }
2269         }
2270         if (tries == 5)
2271                 DRM_ERROR("FDI train 2 fail!\n");
2272
2273         DRM_DEBUG_KMS("FDI train done\n");
2274
2275 }
2276
2277 static const int snb_b_fdi_train_param[] = {
2278         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2279         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2280         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2281         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2282 };
2283
2284 /* The FDI link training functions for SNB/Cougarpoint. */
2285 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2286 {
2287         struct drm_device *dev = crtc->dev;
2288         struct drm_i915_private *dev_priv = dev->dev_private;
2289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2290         int pipe = intel_crtc->pipe;
2291         u32 reg, temp, i, retry;
2292
2293         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2294            for train result */
2295         reg = FDI_RX_IMR(pipe);
2296         temp = I915_READ(reg);
2297         temp &= ~FDI_RX_SYMBOL_LOCK;
2298         temp &= ~FDI_RX_BIT_LOCK;
2299         I915_WRITE(reg, temp);
2300
2301         POSTING_READ(reg);
2302         udelay(150);
2303
2304         /* enable CPU FDI TX and PCH FDI RX */
2305         reg = FDI_TX_CTL(pipe);
2306         temp = I915_READ(reg);
2307         temp &= ~(7 << 19);
2308         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2309         temp &= ~FDI_LINK_TRAIN_NONE;
2310         temp |= FDI_LINK_TRAIN_PATTERN_1;
2311         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2312         /* SNB-B */
2313         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2314         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2315
2316         reg = FDI_RX_CTL(pipe);
2317         temp = I915_READ(reg);
2318         if (HAS_PCH_CPT(dev)) {
2319                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2320                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2321         } else {
2322                 temp &= ~FDI_LINK_TRAIN_NONE;
2323                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2324         }
2325         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2326
2327         POSTING_READ(reg);
2328         udelay(150);
2329
2330         if (HAS_PCH_CPT(dev))
2331                 cpt_phase_pointer_enable(dev, pipe);
2332
2333         for (i = 0; i < 4; i++) {
2334                 reg = FDI_TX_CTL(pipe);
2335                 temp = I915_READ(reg);
2336                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2337                 temp |= snb_b_fdi_train_param[i];
2338                 I915_WRITE(reg, temp);
2339
2340                 POSTING_READ(reg);
2341                 udelay(500);
2342
2343                 for (retry = 0; retry < 5; retry++) {
2344                         reg = FDI_RX_IIR(pipe);
2345                         temp = I915_READ(reg);
2346                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2347                         if (temp & FDI_RX_BIT_LOCK) {
2348                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2349                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2350                                 break;
2351                         }
2352                         udelay(50);
2353                 }
2354                 if (retry < 5)
2355                         break;
2356         }
2357         if (i == 4)
2358                 DRM_ERROR("FDI train 1 fail!\n");
2359
2360         /* Train 2 */
2361         reg = FDI_TX_CTL(pipe);
2362         temp = I915_READ(reg);
2363         temp &= ~FDI_LINK_TRAIN_NONE;
2364         temp |= FDI_LINK_TRAIN_PATTERN_2;
2365         if (IS_GEN6(dev)) {
2366                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2367                 /* SNB-B */
2368                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2369         }
2370         I915_WRITE(reg, temp);
2371
2372         reg = FDI_RX_CTL(pipe);
2373         temp = I915_READ(reg);
2374         if (HAS_PCH_CPT(dev)) {
2375                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2376                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2377         } else {
2378                 temp &= ~FDI_LINK_TRAIN_NONE;
2379                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2380         }
2381         I915_WRITE(reg, temp);
2382
2383         POSTING_READ(reg);
2384         udelay(150);
2385
2386         for (i = 0; i < 4; i++) {
2387                 reg = FDI_TX_CTL(pipe);
2388                 temp = I915_READ(reg);
2389                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2390                 temp |= snb_b_fdi_train_param[i];
2391                 I915_WRITE(reg, temp);
2392
2393                 POSTING_READ(reg);
2394                 udelay(500);
2395
2396                 for (retry = 0; retry < 5; retry++) {
2397                         reg = FDI_RX_IIR(pipe);
2398                         temp = I915_READ(reg);
2399                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2400                         if (temp & FDI_RX_SYMBOL_LOCK) {
2401                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2402                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2403                                 break;
2404                         }
2405                         udelay(50);
2406                 }
2407                 if (retry < 5)
2408                         break;
2409         }
2410         if (i == 4)
2411                 DRM_ERROR("FDI train 2 fail!\n");
2412
2413         DRM_DEBUG_KMS("FDI train done.\n");
2414 }
2415
2416 /* Manual link training for Ivy Bridge A0 parts */
2417 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2418 {
2419         struct drm_device *dev = crtc->dev;
2420         struct drm_i915_private *dev_priv = dev->dev_private;
2421         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2422         int pipe = intel_crtc->pipe;
2423         u32 reg, temp, i;
2424
2425         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2426            for train result */
2427         reg = FDI_RX_IMR(pipe);
2428         temp = I915_READ(reg);
2429         temp &= ~FDI_RX_SYMBOL_LOCK;
2430         temp &= ~FDI_RX_BIT_LOCK;
2431         I915_WRITE(reg, temp);
2432
2433         POSTING_READ(reg);
2434         udelay(150);
2435
2436         /* enable CPU FDI TX and PCH FDI RX */
2437         reg = FDI_TX_CTL(pipe);
2438         temp = I915_READ(reg);
2439         temp &= ~(7 << 19);
2440         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2441         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2442         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2443         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2444         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2445         temp |= FDI_COMPOSITE_SYNC;
2446         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2447
2448         reg = FDI_RX_CTL(pipe);
2449         temp = I915_READ(reg);
2450         temp &= ~FDI_LINK_TRAIN_AUTO;
2451         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2452         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2453         temp |= FDI_COMPOSITE_SYNC;
2454         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2455
2456         POSTING_READ(reg);
2457         udelay(150);
2458
2459         if (HAS_PCH_CPT(dev))
2460                 cpt_phase_pointer_enable(dev, pipe);
2461
2462         for (i = 0; i < 4; i++) {
2463                 reg = FDI_TX_CTL(pipe);
2464                 temp = I915_READ(reg);
2465                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2466                 temp |= snb_b_fdi_train_param[i];
2467                 I915_WRITE(reg, temp);
2468
2469                 POSTING_READ(reg);
2470                 udelay(500);
2471
2472                 reg = FDI_RX_IIR(pipe);
2473                 temp = I915_READ(reg);
2474                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2475
2476                 if (temp & FDI_RX_BIT_LOCK ||
2477                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2478                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2479                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2480                         break;
2481                 }
2482         }
2483         if (i == 4)
2484                 DRM_ERROR("FDI train 1 fail!\n");
2485
2486         /* Train 2 */
2487         reg = FDI_TX_CTL(pipe);
2488         temp = I915_READ(reg);
2489         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2490         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2491         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2492         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2493         I915_WRITE(reg, temp);
2494
2495         reg = FDI_RX_CTL(pipe);
2496         temp = I915_READ(reg);
2497         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2498         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2499         I915_WRITE(reg, temp);
2500
2501         POSTING_READ(reg);
2502         udelay(150);
2503
2504         for (i = 0; i < 4; i++) {
2505                 reg = FDI_TX_CTL(pipe);
2506                 temp = I915_READ(reg);
2507                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2508                 temp |= snb_b_fdi_train_param[i];
2509                 I915_WRITE(reg, temp);
2510
2511                 POSTING_READ(reg);
2512                 udelay(500);
2513
2514                 reg = FDI_RX_IIR(pipe);
2515                 temp = I915_READ(reg);
2516                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2517
2518                 if (temp & FDI_RX_SYMBOL_LOCK) {
2519                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2520                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2521                         break;
2522                 }
2523         }
2524         if (i == 4)
2525                 DRM_ERROR("FDI train 2 fail!\n");
2526
2527         DRM_DEBUG_KMS("FDI train done.\n");
2528 }
2529
2530 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2531 {
2532         struct drm_device *dev = crtc->dev;
2533         struct drm_i915_private *dev_priv = dev->dev_private;
2534         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2535         int pipe = intel_crtc->pipe;
2536         u32 reg, temp;
2537
2538         /* Write the TU size bits so error detection works */
2539         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2540                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2541
2542         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2543         reg = FDI_RX_CTL(pipe);
2544         temp = I915_READ(reg);
2545         temp &= ~((0x7 << 19) | (0x7 << 16));
2546         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2547         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2548         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2549
2550         POSTING_READ(reg);
2551         udelay(200);
2552
2553         /* Switch from Rawclk to PCDclk */
2554         temp = I915_READ(reg);
2555         I915_WRITE(reg, temp | FDI_PCDCLK);
2556
2557         POSTING_READ(reg);
2558         udelay(200);
2559
2560         /* On Haswell, the PLL configuration for ports and pipes is handled
2561          * separately, as part of DDI setup */
2562         if (!IS_HASWELL(dev)) {
2563                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2564                 reg = FDI_TX_CTL(pipe);
2565                 temp = I915_READ(reg);
2566                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2567                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2568
2569                         POSTING_READ(reg);
2570                         udelay(100);
2571                 }
2572         }
2573 }
2574
2575 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2576 {
2577         struct drm_i915_private *dev_priv = dev->dev_private;
2578         u32 flags = I915_READ(SOUTH_CHICKEN1);
2579
2580         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2581         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2582         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2583         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2584         POSTING_READ(SOUTH_CHICKEN1);
2585 }
2586 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2587 {
2588         struct drm_device *dev = crtc->dev;
2589         struct drm_i915_private *dev_priv = dev->dev_private;
2590         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2591         int pipe = intel_crtc->pipe;
2592         u32 reg, temp;
2593
2594         /* disable CPU FDI tx and PCH FDI rx */
2595         reg = FDI_TX_CTL(pipe);
2596         temp = I915_READ(reg);
2597         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2598         POSTING_READ(reg);
2599
2600         reg = FDI_RX_CTL(pipe);
2601         temp = I915_READ(reg);
2602         temp &= ~(0x7 << 16);
2603         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2604         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2605
2606         POSTING_READ(reg);
2607         udelay(100);
2608
2609         /* Ironlake workaround, disable clock pointer after downing FDI */
2610         if (HAS_PCH_IBX(dev)) {
2611                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2612                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2613                            I915_READ(FDI_RX_CHICKEN(pipe) &
2614                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2615         } else if (HAS_PCH_CPT(dev)) {
2616                 cpt_phase_pointer_disable(dev, pipe);
2617         }
2618
2619         /* still set train pattern 1 */
2620         reg = FDI_TX_CTL(pipe);
2621         temp = I915_READ(reg);
2622         temp &= ~FDI_LINK_TRAIN_NONE;
2623         temp |= FDI_LINK_TRAIN_PATTERN_1;
2624         I915_WRITE(reg, temp);
2625
2626         reg = FDI_RX_CTL(pipe);
2627         temp = I915_READ(reg);
2628         if (HAS_PCH_CPT(dev)) {
2629                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2630                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2631         } else {
2632                 temp &= ~FDI_LINK_TRAIN_NONE;
2633                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2634         }
2635         /* BPC in FDI rx is consistent with that in PIPECONF */
2636         temp &= ~(0x07 << 16);
2637         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2638         I915_WRITE(reg, temp);
2639
2640         POSTING_READ(reg);
2641         udelay(100);
2642 }
2643
2644 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2645 {
2646         struct drm_device *dev = crtc->dev;
2647
2648         if (crtc->fb == NULL)
2649                 return;
2650
2651         mutex_lock(&dev->struct_mutex);
2652         intel_finish_fb(crtc->fb);
2653         mutex_unlock(&dev->struct_mutex);
2654 }
2655
2656 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2657 {
2658         struct drm_device *dev = crtc->dev;
2659         struct drm_mode_config *mode_config = &dev->mode_config;
2660         struct intel_encoder *encoder;
2661
2662         /*
2663          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2664          * must be driven by its own crtc; no sharing is possible.
2665          */
2666         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2667                 if (encoder->base.crtc != crtc)
2668                         continue;
2669
2670                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2671                  * CPU handles all others */
2672                 if (IS_HASWELL(dev)) {
2673                         /* It is still unclear how this will work on PPT, so throw up a warning */
2674                         WARN_ON(!HAS_PCH_LPT(dev));
2675
2676                         if (encoder->type == DRM_MODE_ENCODER_DAC) {
2677                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2678                                 return true;
2679                         } else {
2680                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2681                                                 encoder->type);
2682                                 return false;
2683                         }
2684                 }
2685
2686                 switch (encoder->type) {
2687                 case INTEL_OUTPUT_EDP:
2688                         if (!intel_encoder_is_pch_edp(&encoder->base))
2689                                 return false;
2690                         continue;
2691                 }
2692         }
2693
2694         return true;
2695 }
2696
2697 /* Program iCLKIP clock to the desired frequency */
2698 static void lpt_program_iclkip(struct drm_crtc *crtc)
2699 {
2700         struct drm_device *dev = crtc->dev;
2701         struct drm_i915_private *dev_priv = dev->dev_private;
2702         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2703         u32 temp;
2704
2705         /* It is necessary to ungate the pixclk gate prior to programming
2706          * the divisors, and gate it back when it is done.
2707          */
2708         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2709
2710         /* Disable SSCCTL */
2711         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2712                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2713                                         SBI_SSCCTL_DISABLE);
2714
2715         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2716         if (crtc->mode.clock == 20000) {
2717                 auxdiv = 1;
2718                 divsel = 0x41;
2719                 phaseinc = 0x20;
2720         } else {
2721                 /* The iCLK virtual clock root frequency is in MHz,
2722                  * but the crtc->mode.clock in in KHz. To get the divisors,
2723                  * it is necessary to divide one by another, so we
2724                  * convert the virtual clock precision to KHz here for higher
2725                  * precision.
2726                  */
2727                 u32 iclk_virtual_root_freq = 172800 * 1000;
2728                 u32 iclk_pi_range = 64;
2729                 u32 desired_divisor, msb_divisor_value, pi_value;
2730
2731                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2732                 msb_divisor_value = desired_divisor / iclk_pi_range;
2733                 pi_value = desired_divisor % iclk_pi_range;
2734
2735                 auxdiv = 0;
2736                 divsel = msb_divisor_value - 2;
2737                 phaseinc = pi_value;
2738         }
2739
2740         /* This should not happen with any sane values */
2741         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2742                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2743         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2744                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2745
2746         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2747                         crtc->mode.clock,
2748                         auxdiv,
2749                         divsel,
2750                         phasedir,
2751                         phaseinc);
2752
2753         /* Program SSCDIVINTPHASE6 */
2754         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2755         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2756         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2757         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2758         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2759         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2760         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2761
2762         intel_sbi_write(dev_priv,
2763                         SBI_SSCDIVINTPHASE6,
2764                         temp);
2765
2766         /* Program SSCAUXDIV */
2767         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2768         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2769         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2770         intel_sbi_write(dev_priv,
2771                         SBI_SSCAUXDIV6,
2772                         temp);
2773
2774
2775         /* Enable modulator and associated divider */
2776         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2777         temp &= ~SBI_SSCCTL_DISABLE;
2778         intel_sbi_write(dev_priv,
2779                         SBI_SSCCTL6,
2780                         temp);
2781
2782         /* Wait for initialization time */
2783         udelay(24);
2784
2785         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2786 }
2787
2788 /*
2789  * Enable PCH resources required for PCH ports:
2790  *   - PCH PLLs
2791  *   - FDI training & RX/TX
2792  *   - update transcoder timings
2793  *   - DP transcoding bits
2794  *   - transcoder
2795  */
2796 static void ironlake_pch_enable(struct drm_crtc *crtc)
2797 {
2798         struct drm_device *dev = crtc->dev;
2799         struct drm_i915_private *dev_priv = dev->dev_private;
2800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801         int pipe = intel_crtc->pipe;
2802         u32 reg, temp;
2803
2804         assert_transcoder_disabled(dev_priv, pipe);
2805
2806         /* For PCH output, training FDI link */
2807         dev_priv->display.fdi_link_train(crtc);
2808
2809         intel_enable_pch_pll(intel_crtc);
2810
2811         if (HAS_PCH_LPT(dev)) {
2812                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2813                 lpt_program_iclkip(crtc);
2814         } else if (HAS_PCH_CPT(dev)) {
2815                 u32 sel;
2816
2817                 temp = I915_READ(PCH_DPLL_SEL);
2818                 switch (pipe) {
2819                 default:
2820                 case 0:
2821                         temp |= TRANSA_DPLL_ENABLE;
2822                         sel = TRANSA_DPLLB_SEL;
2823                         break;
2824                 case 1:
2825                         temp |= TRANSB_DPLL_ENABLE;
2826                         sel = TRANSB_DPLLB_SEL;
2827                         break;
2828                 case 2:
2829                         temp |= TRANSC_DPLL_ENABLE;
2830                         sel = TRANSC_DPLLB_SEL;
2831                         break;
2832                 }
2833                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2834                         temp |= sel;
2835                 else
2836                         temp &= ~sel;
2837                 I915_WRITE(PCH_DPLL_SEL, temp);
2838         }
2839
2840         /* set transcoder timing, panel must allow it */
2841         assert_panel_unlocked(dev_priv, pipe);
2842         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2843         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2844         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2845
2846         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2847         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2848         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2849         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
2850
2851         if (!IS_HASWELL(dev))
2852                 intel_fdi_normal_train(crtc);
2853
2854         /* For PCH DP, enable TRANS_DP_CTL */
2855         if (HAS_PCH_CPT(dev) &&
2856             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2857              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2858                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2859                 reg = TRANS_DP_CTL(pipe);
2860                 temp = I915_READ(reg);
2861                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2862                           TRANS_DP_SYNC_MASK |
2863                           TRANS_DP_BPC_MASK);
2864                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2865                          TRANS_DP_ENH_FRAMING);
2866                 temp |= bpc << 9; /* same format but at 11:9 */
2867
2868                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2869                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2870                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2871                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2872
2873                 switch (intel_trans_dp_port_sel(crtc)) {
2874                 case PCH_DP_B:
2875                         temp |= TRANS_DP_PORT_SEL_B;
2876                         break;
2877                 case PCH_DP_C:
2878                         temp |= TRANS_DP_PORT_SEL_C;
2879                         break;
2880                 case PCH_DP_D:
2881                         temp |= TRANS_DP_PORT_SEL_D;
2882                         break;
2883                 default:
2884                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2885                         temp |= TRANS_DP_PORT_SEL_B;
2886                         break;
2887                 }
2888
2889                 I915_WRITE(reg, temp);
2890         }
2891
2892         intel_enable_transcoder(dev_priv, pipe);
2893 }
2894
2895 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2896 {
2897         struct intel_pch_pll *pll = intel_crtc->pch_pll;
2898
2899         if (pll == NULL)
2900                 return;
2901
2902         if (pll->refcount == 0) {
2903                 WARN(1, "bad PCH PLL refcount\n");
2904                 return;
2905         }
2906
2907         --pll->refcount;
2908         intel_crtc->pch_pll = NULL;
2909 }
2910
2911 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2912 {
2913         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2914         struct intel_pch_pll *pll;
2915         int i;
2916
2917         pll = intel_crtc->pch_pll;
2918         if (pll) {
2919                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2920                               intel_crtc->base.base.id, pll->pll_reg);
2921                 goto prepare;
2922         }
2923
2924         if (HAS_PCH_IBX(dev_priv->dev)) {
2925                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
2926                 i = intel_crtc->pipe;
2927                 pll = &dev_priv->pch_plls[i];
2928
2929                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
2930                               intel_crtc->base.base.id, pll->pll_reg);
2931
2932                 goto found;
2933         }
2934
2935         for (i = 0; i < dev_priv->num_pch_pll; i++) {
2936                 pll = &dev_priv->pch_plls[i];
2937
2938                 /* Only want to check enabled timings first */
2939                 if (pll->refcount == 0)
2940                         continue;
2941
2942                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2943                     fp == I915_READ(pll->fp0_reg)) {
2944                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2945                                       intel_crtc->base.base.id,
2946                                       pll->pll_reg, pll->refcount, pll->active);
2947
2948                         goto found;
2949                 }
2950         }
2951
2952         /* Ok no matching timings, maybe there's a free one? */
2953         for (i = 0; i < dev_priv->num_pch_pll; i++) {
2954                 pll = &dev_priv->pch_plls[i];
2955                 if (pll->refcount == 0) {
2956                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2957                                       intel_crtc->base.base.id, pll->pll_reg);
2958                         goto found;
2959                 }
2960         }
2961
2962         return NULL;
2963
2964 found:
2965         intel_crtc->pch_pll = pll;
2966         pll->refcount++;
2967         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2968 prepare: /* separate function? */
2969         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2970
2971         /* Wait for the clocks to stabilize before rewriting the regs */
2972         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2973         POSTING_READ(pll->pll_reg);
2974         udelay(150);
2975
2976         I915_WRITE(pll->fp0_reg, fp);
2977         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2978         pll->on = false;
2979         return pll;
2980 }
2981
2982 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2983 {
2984         struct drm_i915_private *dev_priv = dev->dev_private;
2985         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2986         u32 temp;
2987
2988         temp = I915_READ(dslreg);
2989         udelay(500);
2990         if (wait_for(I915_READ(dslreg) != temp, 5)) {
2991                 /* Without this, mode sets may fail silently on FDI */
2992                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2993                 udelay(250);
2994                 I915_WRITE(tc2reg, 0);
2995                 if (wait_for(I915_READ(dslreg) != temp, 5))
2996                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2997         }
2998 }
2999
3000 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3001 {
3002         struct drm_device *dev = crtc->dev;
3003         struct drm_i915_private *dev_priv = dev->dev_private;
3004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3005         int pipe = intel_crtc->pipe;
3006         int plane = intel_crtc->plane;
3007         u32 temp;
3008         bool is_pch_port;
3009
3010         if (intel_crtc->active)
3011                 return;
3012
3013         intel_crtc->active = true;
3014         intel_update_watermarks(dev);
3015
3016         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3017                 temp = I915_READ(PCH_LVDS);
3018                 if ((temp & LVDS_PORT_EN) == 0)
3019                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3020         }
3021
3022         is_pch_port = intel_crtc_driving_pch(crtc);
3023
3024         if (is_pch_port)
3025                 ironlake_fdi_pll_enable(crtc);
3026         else
3027                 ironlake_fdi_disable(crtc);
3028
3029         /* Enable panel fitting for LVDS */
3030         if (dev_priv->pch_pf_size &&
3031             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3032                 /* Force use of hard-coded filter coefficients
3033                  * as some pre-programmed values are broken,
3034                  * e.g. x201.
3035                  */
3036                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3037                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3038                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3039         }
3040
3041         /*
3042          * On ILK+ LUT must be loaded before the pipe is running but with
3043          * clocks enabled
3044          */
3045         intel_crtc_load_lut(crtc);
3046
3047         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3048         intel_enable_plane(dev_priv, plane, pipe);
3049
3050         if (is_pch_port)
3051                 ironlake_pch_enable(crtc);
3052
3053         mutex_lock(&dev->struct_mutex);
3054         intel_update_fbc(dev);
3055         mutex_unlock(&dev->struct_mutex);
3056
3057         intel_crtc_update_cursor(crtc, true);
3058 }
3059
3060 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3061 {
3062         struct drm_device *dev = crtc->dev;
3063         struct drm_i915_private *dev_priv = dev->dev_private;
3064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3065         int pipe = intel_crtc->pipe;
3066         int plane = intel_crtc->plane;
3067         u32 reg, temp;
3068
3069         if (!intel_crtc->active)
3070                 return;
3071
3072         intel_crtc_wait_for_pending_flips(crtc);
3073         drm_vblank_off(dev, pipe);
3074         intel_crtc_update_cursor(crtc, false);
3075
3076         intel_disable_plane(dev_priv, plane, pipe);
3077
3078         if (dev_priv->cfb_plane == plane)
3079                 intel_disable_fbc(dev);
3080
3081         intel_disable_pipe(dev_priv, pipe);
3082
3083         /* Disable PF */
3084         I915_WRITE(PF_CTL(pipe), 0);
3085         I915_WRITE(PF_WIN_SZ(pipe), 0);
3086
3087         ironlake_fdi_disable(crtc);
3088
3089         /* This is a horrible layering violation; we should be doing this in
3090          * the connector/encoder ->prepare instead, but we don't always have
3091          * enough information there about the config to know whether it will
3092          * actually be necessary or just cause undesired flicker.
3093          */
3094         intel_disable_pch_ports(dev_priv, pipe);
3095
3096         intel_disable_transcoder(dev_priv, pipe);
3097
3098         if (HAS_PCH_CPT(dev)) {
3099                 /* disable TRANS_DP_CTL */
3100                 reg = TRANS_DP_CTL(pipe);
3101                 temp = I915_READ(reg);
3102                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3103                 temp |= TRANS_DP_PORT_SEL_NONE;
3104                 I915_WRITE(reg, temp);
3105
3106                 /* disable DPLL_SEL */
3107                 temp = I915_READ(PCH_DPLL_SEL);
3108                 switch (pipe) {
3109                 case 0:
3110                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3111                         break;
3112                 case 1:
3113                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3114                         break;
3115                 case 2:
3116                         /* C shares PLL A or B */
3117                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3118                         break;
3119                 default:
3120                         BUG(); /* wtf */
3121                 }
3122                 I915_WRITE(PCH_DPLL_SEL, temp);
3123         }
3124
3125         /* disable PCH DPLL */
3126         intel_disable_pch_pll(intel_crtc);
3127
3128         /* Switch from PCDclk to Rawclk */
3129         reg = FDI_RX_CTL(pipe);
3130         temp = I915_READ(reg);
3131         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3132
3133         /* Disable CPU FDI TX PLL */
3134         reg = FDI_TX_CTL(pipe);
3135         temp = I915_READ(reg);
3136         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3137
3138         POSTING_READ(reg);
3139         udelay(100);
3140
3141         reg = FDI_RX_CTL(pipe);
3142         temp = I915_READ(reg);
3143         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3144
3145         /* Wait for the clocks to turn off. */
3146         POSTING_READ(reg);
3147         udelay(100);
3148
3149         intel_crtc->active = false;
3150         intel_update_watermarks(dev);
3151
3152         mutex_lock(&dev->struct_mutex);
3153         intel_update_fbc(dev);
3154         mutex_unlock(&dev->struct_mutex);
3155 }
3156
3157 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3158 {
3159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3160         int pipe = intel_crtc->pipe;
3161         int plane = intel_crtc->plane;
3162
3163         /* XXX: When our outputs are all unaware of DPMS modes other than off
3164          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3165          */
3166         switch (mode) {
3167         case DRM_MODE_DPMS_ON:
3168         case DRM_MODE_DPMS_STANDBY:
3169         case DRM_MODE_DPMS_SUSPEND:
3170                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3171                 ironlake_crtc_enable(crtc);
3172                 break;
3173
3174         case DRM_MODE_DPMS_OFF:
3175                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3176                 ironlake_crtc_disable(crtc);
3177                 break;
3178         }
3179 }
3180
3181 static void ironlake_crtc_off(struct drm_crtc *crtc)
3182 {
3183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3184         intel_put_pch_pll(intel_crtc);
3185 }
3186
3187 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3188 {
3189         if (!enable && intel_crtc->overlay) {
3190                 struct drm_device *dev = intel_crtc->base.dev;
3191                 struct drm_i915_private *dev_priv = dev->dev_private;
3192
3193                 mutex_lock(&dev->struct_mutex);
3194                 dev_priv->mm.interruptible = false;
3195                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3196                 dev_priv->mm.interruptible = true;
3197                 mutex_unlock(&dev->struct_mutex);
3198         }
3199
3200         /* Let userspace switch the overlay on again. In most cases userspace
3201          * has to recompute where to put it anyway.
3202          */
3203 }
3204
3205 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3206 {
3207         struct drm_device *dev = crtc->dev;
3208         struct drm_i915_private *dev_priv = dev->dev_private;
3209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3210         int pipe = intel_crtc->pipe;
3211         int plane = intel_crtc->plane;
3212
3213         if (intel_crtc->active)
3214                 return;
3215
3216         intel_crtc->active = true;
3217         intel_update_watermarks(dev);
3218
3219         intel_enable_pll(dev_priv, pipe);
3220         intel_enable_pipe(dev_priv, pipe, false);
3221         intel_enable_plane(dev_priv, plane, pipe);
3222
3223         intel_crtc_load_lut(crtc);
3224         intel_update_fbc(dev);
3225
3226         /* Give the overlay scaler a chance to enable if it's on this pipe */
3227         intel_crtc_dpms_overlay(intel_crtc, true);
3228         intel_crtc_update_cursor(crtc, true);
3229 }
3230
3231 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3232 {
3233         struct drm_device *dev = crtc->dev;
3234         struct drm_i915_private *dev_priv = dev->dev_private;
3235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3236         int pipe = intel_crtc->pipe;
3237         int plane = intel_crtc->plane;
3238
3239         if (!intel_crtc->active)
3240                 return;
3241
3242         /* Give the overlay scaler a chance to disable if it's on this pipe */
3243         intel_crtc_wait_for_pending_flips(crtc);
3244         drm_vblank_off(dev, pipe);
3245         intel_crtc_dpms_overlay(intel_crtc, false);
3246         intel_crtc_update_cursor(crtc, false);
3247
3248         if (dev_priv->cfb_plane == plane)
3249                 intel_disable_fbc(dev);
3250
3251         intel_disable_plane(dev_priv, plane, pipe);
3252         intel_disable_pipe(dev_priv, pipe);
3253         intel_disable_pll(dev_priv, pipe);
3254
3255         intel_crtc->active = false;
3256         intel_update_fbc(dev);
3257         intel_update_watermarks(dev);
3258 }
3259
3260 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3261 {
3262         /* XXX: When our outputs are all unaware of DPMS modes other than off
3263          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3264          */
3265         switch (mode) {
3266         case DRM_MODE_DPMS_ON:
3267         case DRM_MODE_DPMS_STANDBY:
3268         case DRM_MODE_DPMS_SUSPEND:
3269                 i9xx_crtc_enable(crtc);
3270                 break;
3271         case DRM_MODE_DPMS_OFF:
3272                 i9xx_crtc_disable(crtc);
3273                 break;
3274         }
3275 }
3276
3277 static void i9xx_crtc_off(struct drm_crtc *crtc)
3278 {
3279 }
3280
3281 /**
3282  * Sets the power management mode of the pipe and plane.
3283  */
3284 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3285 {
3286         struct drm_device *dev = crtc->dev;
3287         struct drm_i915_private *dev_priv = dev->dev_private;
3288         struct drm_i915_master_private *master_priv;
3289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3290         int pipe = intel_crtc->pipe;
3291         bool enabled;
3292
3293         if (intel_crtc->dpms_mode == mode)
3294                 return;
3295
3296         intel_crtc->dpms_mode = mode;
3297
3298         dev_priv->display.dpms(crtc, mode);
3299
3300         if (!dev->primary->master)
3301                 return;
3302
3303         master_priv = dev->primary->master->driver_priv;
3304         if (!master_priv->sarea_priv)
3305                 return;
3306
3307         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3308
3309         switch (pipe) {
3310         case 0:
3311                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3312                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3313                 break;
3314         case 1:
3315                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3316                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3317                 break;
3318         default:
3319                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3320                 break;
3321         }
3322 }
3323
3324 static void intel_crtc_disable(struct drm_crtc *crtc)
3325 {
3326         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3327         struct drm_device *dev = crtc->dev;
3328         struct drm_i915_private *dev_priv = dev->dev_private;
3329
3330         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3331         dev_priv->display.off(crtc);
3332
3333         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3334         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3335
3336         if (crtc->fb) {
3337                 mutex_lock(&dev->struct_mutex);
3338                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3339                 mutex_unlock(&dev->struct_mutex);
3340         }
3341 }
3342
3343 /* Prepare for a mode set.
3344  *
3345  * Note we could be a lot smarter here.  We need to figure out which outputs
3346  * will be enabled, which disabled (in short, how the config will changes)
3347  * and perform the minimum necessary steps to accomplish that, e.g. updating
3348  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3349  * panel fitting is in the proper state, etc.
3350  */
3351 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3352 {
3353         i9xx_crtc_disable(crtc);
3354 }
3355
3356 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3357 {
3358         i9xx_crtc_enable(crtc);
3359 }
3360
3361 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3362 {
3363         ironlake_crtc_disable(crtc);
3364 }
3365
3366 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3367 {
3368         ironlake_crtc_enable(crtc);
3369 }
3370
3371 void intel_encoder_prepare(struct drm_encoder *encoder)
3372 {
3373         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3374         /* lvds has its own version of prepare see intel_lvds_prepare */
3375         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3376 }
3377
3378 void intel_encoder_commit(struct drm_encoder *encoder)
3379 {
3380         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3381         struct drm_device *dev = encoder->dev;
3382         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3383
3384         /* lvds has its own version of commit see intel_lvds_commit */
3385         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3386
3387         if (HAS_PCH_CPT(dev))
3388                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3389 }
3390
3391 void intel_encoder_destroy(struct drm_encoder *encoder)
3392 {
3393         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3394
3395         drm_encoder_cleanup(encoder);
3396         kfree(intel_encoder);
3397 }
3398
3399 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3400                                   struct drm_display_mode *mode,
3401                                   struct drm_display_mode *adjusted_mode)
3402 {
3403         struct drm_device *dev = crtc->dev;
3404
3405         if (HAS_PCH_SPLIT(dev)) {
3406                 /* FDI link clock is fixed at 2.7G */
3407                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3408                         return false;
3409         }
3410
3411         /* All interlaced capable intel hw wants timings in frames. Note though
3412          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3413          * timings, so we need to be careful not to clobber these.*/
3414         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3415                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3416
3417         return true;
3418 }
3419
3420 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3421 {
3422         return 400000; /* FIXME */
3423 }
3424
3425 static int i945_get_display_clock_speed(struct drm_device *dev)
3426 {
3427         return 400000;
3428 }
3429
3430 static int i915_get_display_clock_speed(struct drm_device *dev)
3431 {
3432         return 333000;
3433 }
3434
3435 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3436 {
3437         return 200000;
3438 }
3439
3440 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3441 {
3442         u16 gcfgc = 0;
3443
3444         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3445
3446         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3447                 return 133000;
3448         else {
3449                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3450                 case GC_DISPLAY_CLOCK_333_MHZ:
3451                         return 333000;
3452                 default:
3453                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3454                         return 190000;
3455                 }
3456         }
3457 }
3458
3459 static int i865_get_display_clock_speed(struct drm_device *dev)
3460 {
3461         return 266000;
3462 }
3463
3464 static int i855_get_display_clock_speed(struct drm_device *dev)
3465 {
3466         u16 hpllcc = 0;
3467         /* Assume that the hardware is in the high speed state.  This
3468          * should be the default.
3469          */
3470         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3471         case GC_CLOCK_133_200:
3472         case GC_CLOCK_100_200:
3473                 return 200000;
3474         case GC_CLOCK_166_250:
3475                 return 250000;
3476         case GC_CLOCK_100_133:
3477                 return 133000;
3478         }
3479
3480         /* Shouldn't happen */
3481         return 0;
3482 }
3483
3484 static int i830_get_display_clock_speed(struct drm_device *dev)
3485 {
3486         return 133000;
3487 }
3488
3489 struct fdi_m_n {
3490         u32        tu;
3491         u32        gmch_m;
3492         u32        gmch_n;
3493         u32        link_m;
3494         u32        link_n;
3495 };
3496
3497 static void
3498 fdi_reduce_ratio(u32 *num, u32 *den)
3499 {
3500         while (*num > 0xffffff || *den > 0xffffff) {
3501                 *num >>= 1;
3502                 *den >>= 1;
3503         }
3504 }
3505
3506 static void
3507 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3508                      int link_clock, struct fdi_m_n *m_n)
3509 {
3510         m_n->tu = 64; /* default size */
3511
3512         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3513         m_n->gmch_m = bits_per_pixel * pixel_clock;
3514         m_n->gmch_n = link_clock * nlanes * 8;
3515         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3516
3517         m_n->link_m = pixel_clock;
3518         m_n->link_n = link_clock;
3519         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3520 }
3521
3522 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3523 {
3524         if (i915_panel_use_ssc >= 0)
3525                 return i915_panel_use_ssc != 0;
3526         return dev_priv->lvds_use_ssc
3527                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3528 }
3529
3530 /**
3531  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3532  * @crtc: CRTC structure
3533  * @mode: requested mode
3534  *
3535  * A pipe may be connected to one or more outputs.  Based on the depth of the
3536  * attached framebuffer, choose a good color depth to use on the pipe.
3537  *
3538  * If possible, match the pipe depth to the fb depth.  In some cases, this
3539  * isn't ideal, because the connected output supports a lesser or restricted
3540  * set of depths.  Resolve that here:
3541  *    LVDS typically supports only 6bpc, so clamp down in that case
3542  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3543  *    Displays may support a restricted set as well, check EDID and clamp as
3544  *      appropriate.
3545  *    DP may want to dither down to 6bpc to fit larger modes
3546  *
3547  * RETURNS:
3548  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3549  * true if they don't match).
3550  */
3551 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3552                                          unsigned int *pipe_bpp,
3553                                          struct drm_display_mode *mode)
3554 {
3555         struct drm_device *dev = crtc->dev;
3556         struct drm_i915_private *dev_priv = dev->dev_private;
3557         struct drm_encoder *encoder;
3558         struct drm_connector *connector;
3559         unsigned int display_bpc = UINT_MAX, bpc;
3560
3561         /* Walk the encoders & connectors on this crtc, get min bpc */
3562         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3563                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3564
3565                 if (encoder->crtc != crtc)
3566                         continue;
3567
3568                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3569                         unsigned int lvds_bpc;
3570
3571                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3572                             LVDS_A3_POWER_UP)
3573                                 lvds_bpc = 8;
3574                         else
3575                                 lvds_bpc = 6;
3576
3577                         if (lvds_bpc < display_bpc) {
3578                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3579                                 display_bpc = lvds_bpc;
3580                         }
3581                         continue;
3582                 }
3583
3584                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3585                         /* Use VBT settings if we have an eDP panel */
3586                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3587
3588                         if (edp_bpc < display_bpc) {
3589                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3590                                 display_bpc = edp_bpc;
3591                         }
3592                         continue;
3593                 }
3594
3595                 /* Not one of the known troublemakers, check the EDID */
3596                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3597                                     head) {
3598                         if (connector->encoder != encoder)
3599                                 continue;
3600
3601                         /* Don't use an invalid EDID bpc value */
3602                         if (connector->display_info.bpc &&
3603                             connector->display_info.bpc < display_bpc) {
3604                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3605                                 display_bpc = connector->display_info.bpc;
3606                         }
3607                 }
3608
3609                 /*
3610                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3611                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3612                  */
3613                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3614                         if (display_bpc > 8 && display_bpc < 12) {
3615                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3616                                 display_bpc = 12;
3617                         } else {
3618                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3619                                 display_bpc = 8;
3620                         }
3621                 }
3622         }
3623
3624         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3625                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3626                 display_bpc = 6;
3627         }
3628
3629         /*
3630          * We could just drive the pipe at the highest bpc all the time and
3631          * enable dithering as needed, but that costs bandwidth.  So choose
3632          * the minimum value that expresses the full color range of the fb but
3633          * also stays within the max display bpc discovered above.
3634          */
3635
3636         switch (crtc->fb->depth) {
3637         case 8:
3638                 bpc = 8; /* since we go through a colormap */
3639                 break;
3640         case 15:
3641         case 16:
3642                 bpc = 6; /* min is 18bpp */
3643                 break;
3644         case 24:
3645                 bpc = 8;
3646                 break;
3647         case 30:
3648                 bpc = 10;
3649                 break;
3650         case 48:
3651                 bpc = 12;
3652                 break;
3653         default:
3654                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3655                 bpc = min((unsigned int)8, display_bpc);
3656                 break;
3657         }
3658
3659         display_bpc = min(display_bpc, bpc);
3660
3661         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3662                       bpc, display_bpc);
3663
3664         *pipe_bpp = display_bpc * 3;
3665
3666         return display_bpc != bpc;
3667 }
3668
3669 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3670 {
3671         struct drm_device *dev = crtc->dev;
3672         struct drm_i915_private *dev_priv = dev->dev_private;
3673         int refclk;
3674
3675         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3676             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3677                 refclk = dev_priv->lvds_ssc_freq * 1000;
3678                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3679                               refclk / 1000);
3680         } else if (!IS_GEN2(dev)) {
3681                 refclk = 96000;
3682         } else {
3683                 refclk = 48000;
3684         }
3685
3686         return refclk;
3687 }
3688
3689 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3690                                       intel_clock_t *clock)
3691 {
3692         /* SDVO TV has fixed PLL values depend on its clock range,
3693            this mirrors vbios setting. */
3694         if (adjusted_mode->clock >= 100000
3695             && adjusted_mode->clock < 140500) {
3696                 clock->p1 = 2;
3697                 clock->p2 = 10;
3698                 clock->n = 3;
3699                 clock->m1 = 16;
3700                 clock->m2 = 8;
3701         } else if (adjusted_mode->clock >= 140500
3702                    && adjusted_mode->clock <= 200000) {
3703                 clock->p1 = 1;
3704                 clock->p2 = 10;
3705                 clock->n = 6;
3706                 clock->m1 = 12;
3707                 clock->m2 = 8;
3708         }
3709 }
3710
3711 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3712                                      intel_clock_t *clock,
3713                                      intel_clock_t *reduced_clock)
3714 {
3715         struct drm_device *dev = crtc->dev;
3716         struct drm_i915_private *dev_priv = dev->dev_private;
3717         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3718         int pipe = intel_crtc->pipe;
3719         u32 fp, fp2 = 0;
3720
3721         if (IS_PINEVIEW(dev)) {
3722                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3723                 if (reduced_clock)
3724                         fp2 = (1 << reduced_clock->n) << 16 |
3725                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3726         } else {
3727                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3728                 if (reduced_clock)
3729                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3730                                 reduced_clock->m2;
3731         }
3732
3733         I915_WRITE(FP0(pipe), fp);
3734
3735         intel_crtc->lowfreq_avail = false;
3736         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3737             reduced_clock && i915_powersave) {
3738                 I915_WRITE(FP1(pipe), fp2);
3739                 intel_crtc->lowfreq_avail = true;
3740         } else {
3741                 I915_WRITE(FP1(pipe), fp);
3742         }
3743 }
3744
3745 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3746                               struct drm_display_mode *adjusted_mode)
3747 {
3748         struct drm_device *dev = crtc->dev;
3749         struct drm_i915_private *dev_priv = dev->dev_private;
3750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3751         int pipe = intel_crtc->pipe;
3752         u32 temp;
3753
3754         temp = I915_READ(LVDS);
3755         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3756         if (pipe == 1) {
3757                 temp |= LVDS_PIPEB_SELECT;
3758         } else {
3759                 temp &= ~LVDS_PIPEB_SELECT;
3760         }
3761         /* set the corresponsding LVDS_BORDER bit */
3762         temp |= dev_priv->lvds_border_bits;
3763         /* Set the B0-B3 data pairs corresponding to whether we're going to
3764          * set the DPLLs for dual-channel mode or not.
3765          */
3766         if (clock->p2 == 7)
3767                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3768         else
3769                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3770
3771         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3772          * appropriately here, but we need to look more thoroughly into how
3773          * panels behave in the two modes.
3774          */
3775         /* set the dithering flag on LVDS as needed */
3776         if (INTEL_INFO(dev)->gen >= 4) {
3777                 if (dev_priv->lvds_dither)
3778                         temp |= LVDS_ENABLE_DITHER;
3779                 else
3780                         temp &= ~LVDS_ENABLE_DITHER;
3781         }
3782         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3783         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3784                 temp |= LVDS_HSYNC_POLARITY;
3785         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3786                 temp |= LVDS_VSYNC_POLARITY;
3787         I915_WRITE(LVDS, temp);
3788 }
3789
3790 static void i9xx_update_pll(struct drm_crtc *crtc,
3791                             struct drm_display_mode *mode,
3792                             struct drm_display_mode *adjusted_mode,
3793                             intel_clock_t *clock, intel_clock_t *reduced_clock,
3794                             int num_connectors)
3795 {
3796         struct drm_device *dev = crtc->dev;
3797         struct drm_i915_private *dev_priv = dev->dev_private;
3798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3799         int pipe = intel_crtc->pipe;
3800         u32 dpll;
3801         bool is_sdvo;
3802
3803         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3804                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3805
3806         dpll = DPLL_VGA_MODE_DIS;
3807
3808         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3809                 dpll |= DPLLB_MODE_LVDS;
3810         else
3811                 dpll |= DPLLB_MODE_DAC_SERIAL;
3812         if (is_sdvo) {
3813                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3814                 if (pixel_multiplier > 1) {
3815                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3816                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3817                 }
3818                 dpll |= DPLL_DVO_HIGH_SPEED;
3819         }
3820         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3821                 dpll |= DPLL_DVO_HIGH_SPEED;
3822
3823         /* compute bitmask from p1 value */
3824         if (IS_PINEVIEW(dev))
3825                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3826         else {
3827                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3828                 if (IS_G4X(dev) && reduced_clock)
3829                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3830         }
3831         switch (clock->p2) {
3832         case 5:
3833                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3834                 break;
3835         case 7:
3836                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3837                 break;
3838         case 10:
3839                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3840                 break;
3841         case 14:
3842                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3843                 break;
3844         }
3845         if (INTEL_INFO(dev)->gen >= 4)
3846                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3847
3848         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3849                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3850         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3851                 /* XXX: just matching BIOS for now */
3852                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3853                 dpll |= 3;
3854         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3855                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3856                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3857         else
3858                 dpll |= PLL_REF_INPUT_DREFCLK;
3859
3860         dpll |= DPLL_VCO_ENABLE;
3861         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3862         POSTING_READ(DPLL(pipe));
3863         udelay(150);
3864
3865         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3866          * This is an exception to the general rule that mode_set doesn't turn
3867          * things on.
3868          */
3869         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3870                 intel_update_lvds(crtc, clock, adjusted_mode);
3871
3872         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3873                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3874
3875         I915_WRITE(DPLL(pipe), dpll);
3876
3877         /* Wait for the clocks to stabilize. */
3878         POSTING_READ(DPLL(pipe));
3879         udelay(150);
3880
3881         if (INTEL_INFO(dev)->gen >= 4) {
3882                 u32 temp = 0;
3883                 if (is_sdvo) {
3884                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3885                         if (temp > 1)
3886                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3887                         else
3888                                 temp = 0;
3889                 }
3890                 I915_WRITE(DPLL_MD(pipe), temp);
3891         } else {
3892                 /* The pixel multiplier can only be updated once the
3893                  * DPLL is enabled and the clocks are stable.
3894                  *
3895                  * So write it again.
3896                  */
3897                 I915_WRITE(DPLL(pipe), dpll);
3898         }
3899 }
3900
3901 static void i8xx_update_pll(struct drm_crtc *crtc,
3902                             struct drm_display_mode *adjusted_mode,
3903                             intel_clock_t *clock,
3904                             int num_connectors)
3905 {
3906         struct drm_device *dev = crtc->dev;
3907         struct drm_i915_private *dev_priv = dev->dev_private;
3908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3909         int pipe = intel_crtc->pipe;
3910         u32 dpll;
3911
3912         dpll = DPLL_VGA_MODE_DIS;
3913
3914         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3915                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3916         } else {
3917                 if (clock->p1 == 2)
3918                         dpll |= PLL_P1_DIVIDE_BY_TWO;
3919                 else
3920                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3921                 if (clock->p2 == 4)
3922                         dpll |= PLL_P2_DIVIDE_BY_4;
3923         }
3924
3925         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3926                 /* XXX: just matching BIOS for now */
3927                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3928                 dpll |= 3;
3929         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3930                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3931                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3932         else
3933                 dpll |= PLL_REF_INPUT_DREFCLK;
3934
3935         dpll |= DPLL_VCO_ENABLE;
3936         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3937         POSTING_READ(DPLL(pipe));
3938         udelay(150);
3939
3940         I915_WRITE(DPLL(pipe), dpll);
3941
3942         /* Wait for the clocks to stabilize. */
3943         POSTING_READ(DPLL(pipe));
3944         udelay(150);
3945
3946         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3947          * This is an exception to the general rule that mode_set doesn't turn
3948          * things on.
3949          */
3950         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3951                 intel_update_lvds(crtc, clock, adjusted_mode);
3952
3953         /* The pixel multiplier can only be updated once the
3954          * DPLL is enabled and the clocks are stable.
3955          *
3956          * So write it again.
3957          */
3958         I915_WRITE(DPLL(pipe), dpll);
3959 }
3960
3961 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3962                               struct drm_display_mode *mode,
3963                               struct drm_display_mode *adjusted_mode,
3964                               int x, int y,
3965                               struct drm_framebuffer *old_fb)
3966 {
3967         struct drm_device *dev = crtc->dev;
3968         struct drm_i915_private *dev_priv = dev->dev_private;
3969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3970         int pipe = intel_crtc->pipe;
3971         int plane = intel_crtc->plane;
3972         int refclk, num_connectors = 0;
3973         intel_clock_t clock, reduced_clock;
3974         u32 dspcntr, pipeconf, vsyncshift;
3975         bool ok, has_reduced_clock = false, is_sdvo = false;
3976         bool is_lvds = false, is_tv = false, is_dp = false;
3977         struct drm_mode_config *mode_config = &dev->mode_config;
3978         struct intel_encoder *encoder;
3979         const intel_limit_t *limit;
3980         int ret;
3981
3982         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3983                 if (encoder->base.crtc != crtc)
3984                         continue;
3985
3986                 switch (encoder->type) {
3987                 case INTEL_OUTPUT_LVDS:
3988                         is_lvds = true;
3989                         break;
3990                 case INTEL_OUTPUT_SDVO:
3991                 case INTEL_OUTPUT_HDMI:
3992                         is_sdvo = true;
3993                         if (encoder->needs_tv_clock)
3994                                 is_tv = true;
3995                         break;
3996                 case INTEL_OUTPUT_TVOUT:
3997                         is_tv = true;
3998                         break;
3999                 case INTEL_OUTPUT_DISPLAYPORT:
4000                         is_dp = true;
4001                         break;
4002                 }
4003
4004                 num_connectors++;
4005         }
4006
4007         refclk = i9xx_get_refclk(crtc, num_connectors);
4008
4009         /*
4010          * Returns a set of divisors for the desired target clock with the given
4011          * refclk, or FALSE.  The returned values represent the clock equation:
4012          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4013          */
4014         limit = intel_limit(crtc, refclk);
4015         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4016                              &clock);
4017         if (!ok) {
4018                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4019                 return -EINVAL;
4020         }
4021
4022         /* Ensure that the cursor is valid for the new mode before changing... */
4023         intel_crtc_update_cursor(crtc, true);
4024
4025         if (is_lvds && dev_priv->lvds_downclock_avail) {
4026                 /*
4027                  * Ensure we match the reduced clock's P to the target clock.
4028                  * If the clocks don't match, we can't switch the display clock
4029                  * by using the FP0/FP1. In such case we will disable the LVDS
4030                  * downclock feature.
4031                 */
4032                 has_reduced_clock = limit->find_pll(limit, crtc,
4033                                                     dev_priv->lvds_downclock,
4034                                                     refclk,
4035                                                     &clock,
4036                                                     &reduced_clock);
4037         }
4038
4039         if (is_sdvo && is_tv)
4040                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4041
4042         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4043                                  &reduced_clock : NULL);
4044
4045         if (IS_GEN2(dev))
4046                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4047         else
4048                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4049                                 has_reduced_clock ? &reduced_clock : NULL,
4050                                 num_connectors);
4051
4052         /* setup pipeconf */
4053         pipeconf = I915_READ(PIPECONF(pipe));
4054
4055         /* Set up the display plane register */
4056         dspcntr = DISPPLANE_GAMMA_ENABLE;
4057
4058         if (pipe == 0)
4059                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4060         else
4061                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4062
4063         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4064                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4065                  * core speed.
4066                  *
4067                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4068                  * pipe == 0 check?
4069                  */
4070                 if (mode->clock >
4071                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4072                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4073                 else
4074                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4075         }
4076
4077         /* default to 8bpc */
4078         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4079         if (is_dp) {
4080                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4081                         pipeconf |= PIPECONF_BPP_6 |
4082                                     PIPECONF_DITHER_EN |
4083                                     PIPECONF_DITHER_TYPE_SP;
4084                 }
4085         }
4086
4087         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4088         drm_mode_debug_printmodeline(mode);
4089
4090         if (HAS_PIPE_CXSR(dev)) {
4091                 if (intel_crtc->lowfreq_avail) {
4092                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4093                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4094                 } else {
4095                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4096                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4097                 }
4098         }
4099
4100         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4101         if (!IS_GEN2(dev) &&
4102             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4103                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4104                 /* the chip adds 2 halflines automatically */
4105                 adjusted_mode->crtc_vtotal -= 1;
4106                 adjusted_mode->crtc_vblank_end -= 1;
4107                 vsyncshift = adjusted_mode->crtc_hsync_start
4108                              - adjusted_mode->crtc_htotal/2;
4109         } else {
4110                 pipeconf |= PIPECONF_PROGRESSIVE;
4111                 vsyncshift = 0;
4112         }
4113
4114         if (!IS_GEN3(dev))
4115                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4116
4117         I915_WRITE(HTOTAL(pipe),
4118                    (adjusted_mode->crtc_hdisplay - 1) |
4119                    ((adjusted_mode->crtc_htotal - 1) << 16));
4120         I915_WRITE(HBLANK(pipe),
4121                    (adjusted_mode->crtc_hblank_start - 1) |
4122                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4123         I915_WRITE(HSYNC(pipe),
4124                    (adjusted_mode->crtc_hsync_start - 1) |
4125                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4126
4127         I915_WRITE(VTOTAL(pipe),
4128                    (adjusted_mode->crtc_vdisplay - 1) |
4129                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4130         I915_WRITE(VBLANK(pipe),
4131                    (adjusted_mode->crtc_vblank_start - 1) |
4132                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4133         I915_WRITE(VSYNC(pipe),
4134                    (adjusted_mode->crtc_vsync_start - 1) |
4135                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4136
4137         /* pipesrc and dspsize control the size that is scaled from,
4138          * which should always be the user's requested size.
4139          */
4140         I915_WRITE(DSPSIZE(plane),
4141                    ((mode->vdisplay - 1) << 16) |
4142                    (mode->hdisplay - 1));
4143         I915_WRITE(DSPPOS(plane), 0);
4144         I915_WRITE(PIPESRC(pipe),
4145                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4146
4147         I915_WRITE(PIPECONF(pipe), pipeconf);
4148         POSTING_READ(PIPECONF(pipe));
4149         intel_enable_pipe(dev_priv, pipe, false);
4150
4151         intel_wait_for_vblank(dev, pipe);
4152
4153         I915_WRITE(DSPCNTR(plane), dspcntr);
4154         POSTING_READ(DSPCNTR(plane));
4155
4156         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4157
4158         intel_update_watermarks(dev);
4159
4160         return ret;
4161 }
4162
4163 /*
4164  * Initialize reference clocks when the driver loads
4165  */
4166 void ironlake_init_pch_refclk(struct drm_device *dev)
4167 {
4168         struct drm_i915_private *dev_priv = dev->dev_private;
4169         struct drm_mode_config *mode_config = &dev->mode_config;
4170         struct intel_encoder *encoder;
4171         u32 temp;
4172         bool has_lvds = false;
4173         bool has_cpu_edp = false;
4174         bool has_pch_edp = false;
4175         bool has_panel = false;
4176         bool has_ck505 = false;
4177         bool can_ssc = false;
4178
4179         /* We need to take the global config into account */
4180         list_for_each_entry(encoder, &mode_config->encoder_list,
4181                             base.head) {
4182                 switch (encoder->type) {
4183                 case INTEL_OUTPUT_LVDS:
4184                         has_panel = true;
4185                         has_lvds = true;
4186                         break;
4187                 case INTEL_OUTPUT_EDP:
4188                         has_panel = true;
4189                         if (intel_encoder_is_pch_edp(&encoder->base))
4190                                 has_pch_edp = true;
4191                         else
4192                                 has_cpu_edp = true;
4193                         break;
4194                 }
4195         }
4196
4197         if (HAS_PCH_IBX(dev)) {
4198                 has_ck505 = dev_priv->display_clock_mode;
4199                 can_ssc = has_ck505;
4200         } else {
4201                 has_ck505 = false;
4202                 can_ssc = true;
4203         }
4204
4205         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4206                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4207                       has_ck505);
4208
4209         /* Ironlake: try to setup display ref clock before DPLL
4210          * enabling. This is only under driver's control after
4211          * PCH B stepping, previous chipset stepping should be
4212          * ignoring this setting.
4213          */
4214         temp = I915_READ(PCH_DREF_CONTROL);
4215         /* Always enable nonspread source */
4216         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4217
4218         if (has_ck505)
4219                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4220         else
4221                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4222
4223         if (has_panel) {
4224                 temp &= ~DREF_SSC_SOURCE_MASK;
4225                 temp |= DREF_SSC_SOURCE_ENABLE;
4226
4227                 /* SSC must be turned on before enabling the CPU output  */
4228                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4229                         DRM_DEBUG_KMS("Using SSC on panel\n");
4230                         temp |= DREF_SSC1_ENABLE;
4231                 } else
4232                         temp &= ~DREF_SSC1_ENABLE;
4233
4234                 /* Get SSC going before enabling the outputs */
4235                 I915_WRITE(PCH_DREF_CONTROL, temp);
4236                 POSTING_READ(PCH_DREF_CONTROL);
4237                 udelay(200);
4238
4239                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4240
4241                 /* Enable CPU source on CPU attached eDP */
4242                 if (has_cpu_edp) {
4243                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4244                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4245                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4246                         }
4247                         else
4248                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4249                 } else
4250                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4251
4252                 I915_WRITE(PCH_DREF_CONTROL, temp);
4253                 POSTING_READ(PCH_DREF_CONTROL);
4254                 udelay(200);
4255         } else {
4256                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4257
4258                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4259
4260                 /* Turn off CPU output */
4261                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4262
4263                 I915_WRITE(PCH_DREF_CONTROL, temp);
4264                 POSTING_READ(PCH_DREF_CONTROL);
4265                 udelay(200);
4266
4267                 /* Turn off the SSC source */
4268                 temp &= ~DREF_SSC_SOURCE_MASK;
4269                 temp |= DREF_SSC_SOURCE_DISABLE;
4270
4271                 /* Turn off SSC1 */
4272                 temp &= ~ DREF_SSC1_ENABLE;
4273
4274                 I915_WRITE(PCH_DREF_CONTROL, temp);
4275                 POSTING_READ(PCH_DREF_CONTROL);
4276                 udelay(200);
4277         }
4278 }
4279
4280 static int ironlake_get_refclk(struct drm_crtc *crtc)
4281 {
4282         struct drm_device *dev = crtc->dev;
4283         struct drm_i915_private *dev_priv = dev->dev_private;
4284         struct intel_encoder *encoder;
4285         struct drm_mode_config *mode_config = &dev->mode_config;
4286         struct intel_encoder *edp_encoder = NULL;
4287         int num_connectors = 0;
4288         bool is_lvds = false;
4289
4290         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4291                 if (encoder->base.crtc != crtc)
4292                         continue;
4293
4294                 switch (encoder->type) {
4295                 case INTEL_OUTPUT_LVDS:
4296                         is_lvds = true;
4297                         break;
4298                 case INTEL_OUTPUT_EDP:
4299                         edp_encoder = encoder;
4300                         break;
4301                 }
4302                 num_connectors++;
4303         }
4304
4305         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4306                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4307                               dev_priv->lvds_ssc_freq);
4308                 return dev_priv->lvds_ssc_freq * 1000;
4309         }
4310
4311         return 120000;
4312 }
4313
4314 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4315                                   struct drm_display_mode *mode,
4316                                   struct drm_display_mode *adjusted_mode,
4317                                   int x, int y,
4318                                   struct drm_framebuffer *old_fb)
4319 {
4320         struct drm_device *dev = crtc->dev;
4321         struct drm_i915_private *dev_priv = dev->dev_private;
4322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4323         int pipe = intel_crtc->pipe;
4324         int plane = intel_crtc->plane;
4325         int refclk, num_connectors = 0;
4326         intel_clock_t clock, reduced_clock;
4327         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4328         bool ok, has_reduced_clock = false, is_sdvo = false;
4329         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4330         struct drm_mode_config *mode_config = &dev->mode_config;
4331         struct intel_encoder *encoder, *edp_encoder = NULL;
4332         const intel_limit_t *limit;
4333         int ret;
4334         struct fdi_m_n m_n = {0};
4335         u32 temp;
4336         int target_clock, pixel_multiplier, lane, link_bw, factor;
4337         unsigned int pipe_bpp;
4338         bool dither;
4339         bool is_cpu_edp = false, is_pch_edp = false;
4340
4341         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4342                 if (encoder->base.crtc != crtc)
4343                         continue;
4344
4345                 switch (encoder->type) {
4346                 case INTEL_OUTPUT_LVDS:
4347                         is_lvds = true;
4348                         break;
4349                 case INTEL_OUTPUT_SDVO:
4350                 case INTEL_OUTPUT_HDMI:
4351                         is_sdvo = true;
4352                         if (encoder->needs_tv_clock)
4353                                 is_tv = true;
4354                         break;
4355                 case INTEL_OUTPUT_TVOUT:
4356                         is_tv = true;
4357                         break;
4358                 case INTEL_OUTPUT_ANALOG:
4359                         is_crt = true;
4360                         break;
4361                 case INTEL_OUTPUT_DISPLAYPORT:
4362                         is_dp = true;
4363                         break;
4364                 case INTEL_OUTPUT_EDP:
4365                         is_dp = true;
4366                         if (intel_encoder_is_pch_edp(&encoder->base))
4367                                 is_pch_edp = true;
4368                         else
4369                                 is_cpu_edp = true;
4370                         edp_encoder = encoder;
4371                         break;
4372                 }
4373
4374                 num_connectors++;
4375         }
4376
4377         refclk = ironlake_get_refclk(crtc);
4378
4379         /*
4380          * Returns a set of divisors for the desired target clock with the given
4381          * refclk, or FALSE.  The returned values represent the clock equation:
4382          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4383          */
4384         limit = intel_limit(crtc, refclk);
4385         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4386                              &clock);
4387         if (!ok) {
4388                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4389                 return -EINVAL;
4390         }
4391
4392         /* Ensure that the cursor is valid for the new mode before changing... */
4393         intel_crtc_update_cursor(crtc, true);
4394
4395         if (is_lvds && dev_priv->lvds_downclock_avail) {
4396                 /*
4397                  * Ensure we match the reduced clock's P to the target clock.
4398                  * If the clocks don't match, we can't switch the display clock
4399                  * by using the FP0/FP1. In such case we will disable the LVDS
4400                  * downclock feature.
4401                 */
4402                 has_reduced_clock = limit->find_pll(limit, crtc,
4403                                                     dev_priv->lvds_downclock,
4404                                                     refclk,
4405                                                     &clock,
4406                                                     &reduced_clock);
4407         }
4408
4409         if (is_sdvo && is_tv)
4410                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4411
4412
4413         /* FDI link */
4414         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4415         lane = 0;
4416         /* CPU eDP doesn't require FDI link, so just set DP M/N
4417            according to current link config */
4418         if (is_cpu_edp) {
4419                 target_clock = mode->clock;
4420                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4421         } else {
4422                 /* [e]DP over FDI requires target mode clock
4423                    instead of link clock */
4424                 if (is_dp)
4425                         target_clock = mode->clock;
4426                 else
4427                         target_clock = adjusted_mode->clock;
4428
4429                 /* FDI is a binary signal running at ~2.7GHz, encoding
4430                  * each output octet as 10 bits. The actual frequency
4431                  * is stored as a divider into a 100MHz clock, and the
4432                  * mode pixel clock is stored in units of 1KHz.
4433                  * Hence the bw of each lane in terms of the mode signal
4434                  * is:
4435                  */
4436                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4437         }
4438
4439         /* determine panel color depth */
4440         temp = I915_READ(PIPECONF(pipe));
4441         temp &= ~PIPE_BPC_MASK;
4442         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4443         switch (pipe_bpp) {
4444         case 18:
4445                 temp |= PIPE_6BPC;
4446                 break;
4447         case 24:
4448                 temp |= PIPE_8BPC;
4449                 break;
4450         case 30:
4451                 temp |= PIPE_10BPC;
4452                 break;
4453         case 36:
4454                 temp |= PIPE_12BPC;
4455                 break;
4456         default:
4457                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4458                         pipe_bpp);
4459                 temp |= PIPE_8BPC;
4460                 pipe_bpp = 24;
4461                 break;
4462         }
4463
4464         intel_crtc->bpp = pipe_bpp;
4465         I915_WRITE(PIPECONF(pipe), temp);
4466
4467         if (!lane) {
4468                 /*
4469                  * Account for spread spectrum to avoid
4470                  * oversubscribing the link. Max center spread
4471                  * is 2.5%; use 5% for safety's sake.
4472                  */
4473                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4474                 lane = bps / (link_bw * 8) + 1;
4475         }
4476
4477         intel_crtc->fdi_lanes = lane;
4478
4479         if (pixel_multiplier > 1)
4480                 link_bw *= pixel_multiplier;
4481         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4482                              &m_n);
4483
4484         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4485         if (has_reduced_clock)
4486                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4487                         reduced_clock.m2;
4488
4489         /* Enable autotuning of the PLL clock (if permissible) */
4490         factor = 21;
4491         if (is_lvds) {
4492                 if ((intel_panel_use_ssc(dev_priv) &&
4493                      dev_priv->lvds_ssc_freq == 100) ||
4494                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4495                         factor = 25;
4496         } else if (is_sdvo && is_tv)
4497                 factor = 20;
4498
4499         if (clock.m < factor * clock.n)
4500                 fp |= FP_CB_TUNE;
4501
4502         dpll = 0;
4503
4504         if (is_lvds)
4505                 dpll |= DPLLB_MODE_LVDS;
4506         else
4507                 dpll |= DPLLB_MODE_DAC_SERIAL;
4508         if (is_sdvo) {
4509                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4510                 if (pixel_multiplier > 1) {
4511                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4512                 }
4513                 dpll |= DPLL_DVO_HIGH_SPEED;
4514         }
4515         if (is_dp && !is_cpu_edp)
4516                 dpll |= DPLL_DVO_HIGH_SPEED;
4517
4518         /* compute bitmask from p1 value */
4519         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4520         /* also FPA1 */
4521         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4522
4523         switch (clock.p2) {
4524         case 5:
4525                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4526                 break;
4527         case 7:
4528                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4529                 break;
4530         case 10:
4531                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4532                 break;
4533         case 14:
4534                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4535                 break;
4536         }
4537
4538         if (is_sdvo && is_tv)
4539                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4540         else if (is_tv)
4541                 /* XXX: just matching BIOS for now */
4542                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4543                 dpll |= 3;
4544         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4545                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4546         else
4547                 dpll |= PLL_REF_INPUT_DREFCLK;
4548
4549         /* setup pipeconf */
4550         pipeconf = I915_READ(PIPECONF(pipe));
4551
4552         /* Set up the display plane register */
4553         dspcntr = DISPPLANE_GAMMA_ENABLE;
4554
4555         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4556         drm_mode_debug_printmodeline(mode);
4557
4558         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4559          * pre-Haswell/LPT generation */
4560         if (HAS_PCH_LPT(dev)) {
4561                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4562                                 pipe);
4563         } else if (!is_cpu_edp) {
4564                 struct intel_pch_pll *pll;
4565
4566                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4567                 if (pll == NULL) {
4568                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4569                                          pipe);
4570                         return -EINVAL;
4571                 }
4572         } else
4573                 intel_put_pch_pll(intel_crtc);
4574
4575         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4576          * This is an exception to the general rule that mode_set doesn't turn
4577          * things on.
4578          */
4579         if (is_lvds) {
4580                 temp = I915_READ(PCH_LVDS);
4581                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4582                 if (HAS_PCH_CPT(dev)) {
4583                         temp &= ~PORT_TRANS_SEL_MASK;
4584                         temp |= PORT_TRANS_SEL_CPT(pipe);
4585                 } else {
4586                         if (pipe == 1)
4587                                 temp |= LVDS_PIPEB_SELECT;
4588                         else
4589                                 temp &= ~LVDS_PIPEB_SELECT;
4590                 }
4591
4592                 /* set the corresponsding LVDS_BORDER bit */
4593                 temp |= dev_priv->lvds_border_bits;
4594                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4595                  * set the DPLLs for dual-channel mode or not.
4596                  */
4597                 if (clock.p2 == 7)
4598                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4599                 else
4600                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4601
4602                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4603                  * appropriately here, but we need to look more thoroughly into how
4604                  * panels behave in the two modes.
4605                  */
4606                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4607                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4608                         temp |= LVDS_HSYNC_POLARITY;
4609                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4610                         temp |= LVDS_VSYNC_POLARITY;
4611                 I915_WRITE(PCH_LVDS, temp);
4612         }
4613
4614         pipeconf &= ~PIPECONF_DITHER_EN;
4615         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4616         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4617                 pipeconf |= PIPECONF_DITHER_EN;
4618                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4619         }
4620         if (is_dp && !is_cpu_edp) {
4621                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4622         } else {
4623                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4624                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4625                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4626                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4627                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4628         }
4629
4630         if (intel_crtc->pch_pll) {
4631                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4632
4633                 /* Wait for the clocks to stabilize. */
4634                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4635                 udelay(150);
4636
4637                 /* The pixel multiplier can only be updated once the
4638                  * DPLL is enabled and the clocks are stable.
4639                  *
4640                  * So write it again.
4641                  */
4642                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4643         }
4644
4645         intel_crtc->lowfreq_avail = false;
4646         if (intel_crtc->pch_pll) {
4647                 if (is_lvds && has_reduced_clock && i915_powersave) {
4648                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4649                         intel_crtc->lowfreq_avail = true;
4650                 } else {
4651                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4652                 }
4653         }
4654
4655         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4656         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4657                 pipeconf |= PIPECONF_INTERLACED_ILK;
4658                 /* the chip adds 2 halflines automatically */
4659                 adjusted_mode->crtc_vtotal -= 1;
4660                 adjusted_mode->crtc_vblank_end -= 1;
4661                 I915_WRITE(VSYNCSHIFT(pipe),
4662                            adjusted_mode->crtc_hsync_start
4663                            - adjusted_mode->crtc_htotal/2);
4664         } else {
4665                 pipeconf |= PIPECONF_PROGRESSIVE;
4666                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4667         }
4668
4669         I915_WRITE(HTOTAL(pipe),
4670                    (adjusted_mode->crtc_hdisplay - 1) |
4671                    ((adjusted_mode->crtc_htotal - 1) << 16));
4672         I915_WRITE(HBLANK(pipe),
4673                    (adjusted_mode->crtc_hblank_start - 1) |
4674                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4675         I915_WRITE(HSYNC(pipe),
4676                    (adjusted_mode->crtc_hsync_start - 1) |
4677                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4678
4679         I915_WRITE(VTOTAL(pipe),
4680                    (adjusted_mode->crtc_vdisplay - 1) |
4681                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4682         I915_WRITE(VBLANK(pipe),
4683                    (adjusted_mode->crtc_vblank_start - 1) |
4684                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4685         I915_WRITE(VSYNC(pipe),
4686                    (adjusted_mode->crtc_vsync_start - 1) |
4687                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4688
4689         /* pipesrc controls the size that is scaled from, which should
4690          * always be the user's requested size.
4691          */
4692         I915_WRITE(PIPESRC(pipe),
4693                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4694
4695         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4696         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4697         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4698         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4699
4700         if (is_cpu_edp)
4701                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4702
4703         I915_WRITE(PIPECONF(pipe), pipeconf);
4704         POSTING_READ(PIPECONF(pipe));
4705
4706         intel_wait_for_vblank(dev, pipe);
4707
4708         I915_WRITE(DSPCNTR(plane), dspcntr);
4709         POSTING_READ(DSPCNTR(plane));
4710
4711         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4712
4713         intel_update_watermarks(dev);
4714
4715         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4716
4717         return ret;
4718 }
4719
4720 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4721                                struct drm_display_mode *mode,
4722                                struct drm_display_mode *adjusted_mode,
4723                                int x, int y,
4724                                struct drm_framebuffer *old_fb)
4725 {
4726         struct drm_device *dev = crtc->dev;
4727         struct drm_i915_private *dev_priv = dev->dev_private;
4728         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4729         int pipe = intel_crtc->pipe;
4730         int ret;
4731
4732         drm_vblank_pre_modeset(dev, pipe);
4733
4734         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4735                                               x, y, old_fb);
4736         drm_vblank_post_modeset(dev, pipe);
4737
4738         if (ret)
4739                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4740         else
4741                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4742
4743         return ret;
4744 }
4745
4746 static bool intel_eld_uptodate(struct drm_connector *connector,
4747                                int reg_eldv, uint32_t bits_eldv,
4748                                int reg_elda, uint32_t bits_elda,
4749                                int reg_edid)
4750 {
4751         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4752         uint8_t *eld = connector->eld;
4753         uint32_t i;
4754
4755         i = I915_READ(reg_eldv);
4756         i &= bits_eldv;
4757
4758         if (!eld[0])
4759                 return !i;
4760
4761         if (!i)
4762                 return false;
4763
4764         i = I915_READ(reg_elda);
4765         i &= ~bits_elda;
4766         I915_WRITE(reg_elda, i);
4767
4768         for (i = 0; i < eld[2]; i++)
4769                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4770                         return false;
4771
4772         return true;
4773 }
4774
4775 static void g4x_write_eld(struct drm_connector *connector,
4776                           struct drm_crtc *crtc)
4777 {
4778         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4779         uint8_t *eld = connector->eld;
4780         uint32_t eldv;
4781         uint32_t len;
4782         uint32_t i;
4783
4784         i = I915_READ(G4X_AUD_VID_DID);
4785
4786         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4787                 eldv = G4X_ELDV_DEVCL_DEVBLC;
4788         else
4789                 eldv = G4X_ELDV_DEVCTG;
4790
4791         if (intel_eld_uptodate(connector,
4792                                G4X_AUD_CNTL_ST, eldv,
4793                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4794                                G4X_HDMIW_HDMIEDID))
4795                 return;
4796
4797         i = I915_READ(G4X_AUD_CNTL_ST);
4798         i &= ~(eldv | G4X_ELD_ADDR);
4799         len = (i >> 9) & 0x1f;          /* ELD buffer size */
4800         I915_WRITE(G4X_AUD_CNTL_ST, i);
4801
4802         if (!eld[0])
4803                 return;
4804
4805         len = min_t(uint8_t, eld[2], len);
4806         DRM_DEBUG_DRIVER("ELD size %d\n", len);
4807         for (i = 0; i < len; i++)
4808                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4809
4810         i = I915_READ(G4X_AUD_CNTL_ST);
4811         i |= eldv;
4812         I915_WRITE(G4X_AUD_CNTL_ST, i);
4813 }
4814
4815 static void ironlake_write_eld(struct drm_connector *connector,
4816                                      struct drm_crtc *crtc)
4817 {
4818         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4819         uint8_t *eld = connector->eld;
4820         uint32_t eldv;
4821         uint32_t i;
4822         int len;
4823         int hdmiw_hdmiedid;
4824         int aud_config;
4825         int aud_cntl_st;
4826         int aud_cntrl_st2;
4827
4828         if (HAS_PCH_IBX(connector->dev)) {
4829                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4830                 aud_config = IBX_AUD_CONFIG_A;
4831                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4832                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4833         } else {
4834                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4835                 aud_config = CPT_AUD_CONFIG_A;
4836                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4837                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4838         }
4839
4840         i = to_intel_crtc(crtc)->pipe;
4841         hdmiw_hdmiedid += i * 0x100;
4842         aud_cntl_st += i * 0x100;
4843         aud_config += i * 0x100;
4844
4845         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4846
4847         i = I915_READ(aud_cntl_st);
4848         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
4849         if (!i) {
4850                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4851                 /* operate blindly on all ports */
4852                 eldv = IBX_ELD_VALIDB;
4853                 eldv |= IBX_ELD_VALIDB << 4;
4854                 eldv |= IBX_ELD_VALIDB << 8;
4855         } else {
4856                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
4857                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4858         }
4859
4860         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4861                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4862                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
4863                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4864         } else
4865                 I915_WRITE(aud_config, 0);
4866
4867         if (intel_eld_uptodate(connector,
4868                                aud_cntrl_st2, eldv,
4869                                aud_cntl_st, IBX_ELD_ADDRESS,
4870                                hdmiw_hdmiedid))
4871                 return;
4872
4873         i = I915_READ(aud_cntrl_st2);
4874         i &= ~eldv;
4875         I915_WRITE(aud_cntrl_st2, i);
4876
4877         if (!eld[0])
4878                 return;
4879
4880         i = I915_READ(aud_cntl_st);
4881         i &= ~IBX_ELD_ADDRESS;
4882         I915_WRITE(aud_cntl_st, i);
4883
4884         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
4885         DRM_DEBUG_DRIVER("ELD size %d\n", len);
4886         for (i = 0; i < len; i++)
4887                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4888
4889         i = I915_READ(aud_cntrl_st2);
4890         i |= eldv;
4891         I915_WRITE(aud_cntrl_st2, i);
4892 }
4893
4894 void intel_write_eld(struct drm_encoder *encoder,
4895                      struct drm_display_mode *mode)
4896 {
4897         struct drm_crtc *crtc = encoder->crtc;
4898         struct drm_connector *connector;
4899         struct drm_device *dev = encoder->dev;
4900         struct drm_i915_private *dev_priv = dev->dev_private;
4901
4902         connector = drm_select_eld(encoder, mode);
4903         if (!connector)
4904                 return;
4905
4906         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4907                          connector->base.id,
4908                          drm_get_connector_name(connector),
4909                          connector->encoder->base.id,
4910                          drm_get_encoder_name(connector->encoder));
4911
4912         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4913
4914         if (dev_priv->display.write_eld)
4915                 dev_priv->display.write_eld(connector, crtc);
4916 }
4917
4918 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4919 void intel_crtc_load_lut(struct drm_crtc *crtc)
4920 {
4921         struct drm_device *dev = crtc->dev;
4922         struct drm_i915_private *dev_priv = dev->dev_private;
4923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4924         int palreg = PALETTE(intel_crtc->pipe);
4925         int i;
4926
4927         /* The clocks have to be on to load the palette. */
4928         if (!crtc->enabled || !intel_crtc->active)
4929                 return;
4930
4931         /* use legacy palette for Ironlake */
4932         if (HAS_PCH_SPLIT(dev))
4933                 palreg = LGC_PALETTE(intel_crtc->pipe);
4934
4935         for (i = 0; i < 256; i++) {
4936                 I915_WRITE(palreg + 4 * i,
4937                            (intel_crtc->lut_r[i] << 16) |
4938                            (intel_crtc->lut_g[i] << 8) |
4939                            intel_crtc->lut_b[i]);
4940         }
4941 }
4942
4943 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4944 {
4945         struct drm_device *dev = crtc->dev;
4946         struct drm_i915_private *dev_priv = dev->dev_private;
4947         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4948         bool visible = base != 0;
4949         u32 cntl;
4950
4951         if (intel_crtc->cursor_visible == visible)
4952                 return;
4953
4954         cntl = I915_READ(_CURACNTR);
4955         if (visible) {
4956                 /* On these chipsets we can only modify the base whilst
4957                  * the cursor is disabled.
4958                  */
4959                 I915_WRITE(_CURABASE, base);
4960
4961                 cntl &= ~(CURSOR_FORMAT_MASK);
4962                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4963                 cntl |= CURSOR_ENABLE |
4964                         CURSOR_GAMMA_ENABLE |
4965                         CURSOR_FORMAT_ARGB;
4966         } else
4967                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4968         I915_WRITE(_CURACNTR, cntl);
4969
4970         intel_crtc->cursor_visible = visible;
4971 }
4972
4973 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4974 {
4975         struct drm_device *dev = crtc->dev;
4976         struct drm_i915_private *dev_priv = dev->dev_private;
4977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4978         int pipe = intel_crtc->pipe;
4979         bool visible = base != 0;
4980
4981         if (intel_crtc->cursor_visible != visible) {
4982                 uint32_t cntl = I915_READ(CURCNTR(pipe));
4983                 if (base) {
4984                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4985                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4986                         cntl |= pipe << 28; /* Connect to correct pipe */
4987                 } else {
4988                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4989                         cntl |= CURSOR_MODE_DISABLE;
4990                 }
4991                 I915_WRITE(CURCNTR(pipe), cntl);
4992
4993                 intel_crtc->cursor_visible = visible;
4994         }
4995         /* and commit changes on next vblank */
4996         I915_WRITE(CURBASE(pipe), base);
4997 }
4998
4999 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5000 {
5001         struct drm_device *dev = crtc->dev;
5002         struct drm_i915_private *dev_priv = dev->dev_private;
5003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5004         int pipe = intel_crtc->pipe;
5005         bool visible = base != 0;
5006
5007         if (intel_crtc->cursor_visible != visible) {
5008                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5009                 if (base) {
5010                         cntl &= ~CURSOR_MODE;
5011                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5012                 } else {
5013                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5014                         cntl |= CURSOR_MODE_DISABLE;
5015                 }
5016                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5017
5018                 intel_crtc->cursor_visible = visible;
5019         }
5020         /* and commit changes on next vblank */
5021         I915_WRITE(CURBASE_IVB(pipe), base);
5022 }
5023
5024 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5025 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5026                                      bool on)
5027 {
5028         struct drm_device *dev = crtc->dev;
5029         struct drm_i915_private *dev_priv = dev->dev_private;
5030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5031         int pipe = intel_crtc->pipe;
5032         int x = intel_crtc->cursor_x;
5033         int y = intel_crtc->cursor_y;
5034         u32 base, pos;
5035         bool visible;
5036
5037         pos = 0;
5038
5039         if (on && crtc->enabled && crtc->fb) {
5040                 base = intel_crtc->cursor_addr;
5041                 if (x > (int) crtc->fb->width)
5042                         base = 0;
5043
5044                 if (y > (int) crtc->fb->height)
5045                         base = 0;
5046         } else
5047                 base = 0;
5048
5049         if (x < 0) {
5050                 if (x + intel_crtc->cursor_width < 0)
5051                         base = 0;
5052
5053                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5054                 x = -x;
5055         }
5056         pos |= x << CURSOR_X_SHIFT;
5057
5058         if (y < 0) {
5059                 if (y + intel_crtc->cursor_height < 0)
5060                         base = 0;
5061
5062                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5063                 y = -y;
5064         }
5065         pos |= y << CURSOR_Y_SHIFT;
5066
5067         visible = base != 0;
5068         if (!visible && !intel_crtc->cursor_visible)
5069                 return;
5070
5071         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5072                 I915_WRITE(CURPOS_IVB(pipe), pos);
5073                 ivb_update_cursor(crtc, base);
5074         } else {
5075                 I915_WRITE(CURPOS(pipe), pos);
5076                 if (IS_845G(dev) || IS_I865G(dev))
5077                         i845_update_cursor(crtc, base);
5078                 else
5079                         i9xx_update_cursor(crtc, base);
5080         }
5081 }
5082
5083 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5084                                  struct drm_file *file,
5085                                  uint32_t handle,
5086                                  uint32_t width, uint32_t height)
5087 {
5088         struct drm_device *dev = crtc->dev;
5089         struct drm_i915_private *dev_priv = dev->dev_private;
5090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5091         struct drm_i915_gem_object *obj;
5092         uint32_t addr;
5093         int ret;
5094
5095         DRM_DEBUG_KMS("\n");
5096
5097         /* if we want to turn off the cursor ignore width and height */
5098         if (!handle) {
5099                 DRM_DEBUG_KMS("cursor off\n");
5100                 addr = 0;
5101                 obj = NULL;
5102                 mutex_lock(&dev->struct_mutex);
5103                 goto finish;
5104         }
5105
5106         /* Currently we only support 64x64 cursors */
5107         if (width != 64 || height != 64) {
5108                 DRM_ERROR("we currently only support 64x64 cursors\n");
5109                 return -EINVAL;
5110         }
5111
5112         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5113         if (&obj->base == NULL)
5114                 return -ENOENT;
5115
5116         if (obj->base.size < width * height * 4) {
5117                 DRM_ERROR("buffer is to small\n");
5118                 ret = -ENOMEM;
5119                 goto fail;
5120         }
5121
5122         /* we only need to pin inside GTT if cursor is non-phy */
5123         mutex_lock(&dev->struct_mutex);
5124         if (!dev_priv->info->cursor_needs_physical) {
5125                 if (obj->tiling_mode) {
5126                         DRM_ERROR("cursor cannot be tiled\n");
5127                         ret = -EINVAL;
5128                         goto fail_locked;
5129                 }
5130
5131                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5132                 if (ret) {
5133                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5134                         goto fail_locked;
5135                 }
5136
5137                 ret = i915_gem_object_put_fence(obj);
5138                 if (ret) {
5139                         DRM_ERROR("failed to release fence for cursor");
5140                         goto fail_unpin;
5141                 }
5142
5143                 addr = obj->gtt_offset;
5144         } else {
5145                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5146                 ret = i915_gem_attach_phys_object(dev, obj,
5147                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5148                                                   align);
5149                 if (ret) {
5150                         DRM_ERROR("failed to attach phys object\n");
5151                         goto fail_locked;
5152                 }
5153                 addr = obj->phys_obj->handle->busaddr;
5154         }
5155
5156         if (IS_GEN2(dev))
5157                 I915_WRITE(CURSIZE, (height << 12) | width);
5158
5159  finish:
5160         if (intel_crtc->cursor_bo) {
5161                 if (dev_priv->info->cursor_needs_physical) {
5162                         if (intel_crtc->cursor_bo != obj)
5163                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5164                 } else
5165                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5166                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5167         }
5168
5169         mutex_unlock(&dev->struct_mutex);
5170
5171         intel_crtc->cursor_addr = addr;
5172         intel_crtc->cursor_bo = obj;
5173         intel_crtc->cursor_width = width;
5174         intel_crtc->cursor_height = height;
5175
5176         intel_crtc_update_cursor(crtc, true);
5177
5178         return 0;
5179 fail_unpin:
5180         i915_gem_object_unpin(obj);
5181 fail_locked:
5182         mutex_unlock(&dev->struct_mutex);
5183 fail:
5184         drm_gem_object_unreference_unlocked(&obj->base);
5185         return ret;
5186 }
5187
5188 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5189 {
5190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5191
5192         intel_crtc->cursor_x = x;
5193         intel_crtc->cursor_y = y;
5194
5195         intel_crtc_update_cursor(crtc, true);
5196
5197         return 0;
5198 }
5199
5200 /** Sets the color ramps on behalf of RandR */
5201 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5202                                  u16 blue, int regno)
5203 {
5204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5205
5206         intel_crtc->lut_r[regno] = red >> 8;
5207         intel_crtc->lut_g[regno] = green >> 8;
5208         intel_crtc->lut_b[regno] = blue >> 8;
5209 }
5210
5211 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5212                              u16 *blue, int regno)
5213 {
5214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5215
5216         *red = intel_crtc->lut_r[regno] << 8;
5217         *green = intel_crtc->lut_g[regno] << 8;
5218         *blue = intel_crtc->lut_b[regno] << 8;
5219 }
5220
5221 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5222                                  u16 *blue, uint32_t start, uint32_t size)
5223 {
5224         int end = (start + size > 256) ? 256 : start + size, i;
5225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5226
5227         for (i = start; i < end; i++) {
5228                 intel_crtc->lut_r[i] = red[i] >> 8;
5229                 intel_crtc->lut_g[i] = green[i] >> 8;
5230                 intel_crtc->lut_b[i] = blue[i] >> 8;
5231         }
5232
5233         intel_crtc_load_lut(crtc);
5234 }
5235
5236 /**
5237  * Get a pipe with a simple mode set on it for doing load-based monitor
5238  * detection.
5239  *
5240  * It will be up to the load-detect code to adjust the pipe as appropriate for
5241  * its requirements.  The pipe will be connected to no other encoders.
5242  *
5243  * Currently this code will only succeed if there is a pipe with no encoders
5244  * configured for it.  In the future, it could choose to temporarily disable
5245  * some outputs to free up a pipe for its use.
5246  *
5247  * \return crtc, or NULL if no pipes are available.
5248  */
5249
5250 /* VESA 640x480x72Hz mode to set on the pipe */
5251 static struct drm_display_mode load_detect_mode = {
5252         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5253                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5254 };
5255
5256 static struct drm_framebuffer *
5257 intel_framebuffer_create(struct drm_device *dev,
5258                          struct drm_mode_fb_cmd2 *mode_cmd,
5259                          struct drm_i915_gem_object *obj)
5260 {
5261         struct intel_framebuffer *intel_fb;
5262         int ret;
5263
5264         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5265         if (!intel_fb) {
5266                 drm_gem_object_unreference_unlocked(&obj->base);
5267                 return ERR_PTR(-ENOMEM);
5268         }
5269
5270         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5271         if (ret) {
5272                 drm_gem_object_unreference_unlocked(&obj->base);
5273                 kfree(intel_fb);
5274                 return ERR_PTR(ret);
5275         }
5276
5277         return &intel_fb->base;
5278 }
5279
5280 static u32
5281 intel_framebuffer_pitch_for_width(int width, int bpp)
5282 {
5283         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5284         return ALIGN(pitch, 64);
5285 }
5286
5287 static u32
5288 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5289 {
5290         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5291         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5292 }
5293
5294 static struct drm_framebuffer *
5295 intel_framebuffer_create_for_mode(struct drm_device *dev,
5296                                   struct drm_display_mode *mode,
5297                                   int depth, int bpp)
5298 {
5299         struct drm_i915_gem_object *obj;
5300         struct drm_mode_fb_cmd2 mode_cmd;
5301
5302         obj = i915_gem_alloc_object(dev,
5303                                     intel_framebuffer_size_for_mode(mode, bpp));
5304         if (obj == NULL)
5305                 return ERR_PTR(-ENOMEM);
5306
5307         mode_cmd.width = mode->hdisplay;
5308         mode_cmd.height = mode->vdisplay;
5309         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5310                                                                 bpp);
5311         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5312
5313         return intel_framebuffer_create(dev, &mode_cmd, obj);
5314 }
5315
5316 static struct drm_framebuffer *
5317 mode_fits_in_fbdev(struct drm_device *dev,
5318                    struct drm_display_mode *mode)
5319 {
5320         struct drm_i915_private *dev_priv = dev->dev_private;
5321         struct drm_i915_gem_object *obj;
5322         struct drm_framebuffer *fb;
5323
5324         if (dev_priv->fbdev == NULL)
5325                 return NULL;
5326
5327         obj = dev_priv->fbdev->ifb.obj;
5328         if (obj == NULL)
5329                 return NULL;
5330
5331         fb = &dev_priv->fbdev->ifb.base;
5332         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5333                                                                fb->bits_per_pixel))
5334                 return NULL;
5335
5336         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5337                 return NULL;
5338
5339         return fb;
5340 }
5341
5342 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5343                                 struct drm_connector *connector,
5344                                 struct drm_display_mode *mode,
5345                                 struct intel_load_detect_pipe *old)
5346 {
5347         struct intel_crtc *intel_crtc;
5348         struct drm_crtc *possible_crtc;
5349         struct drm_encoder *encoder = &intel_encoder->base;
5350         struct drm_crtc *crtc = NULL;
5351         struct drm_device *dev = encoder->dev;
5352         struct drm_framebuffer *old_fb;
5353         int i = -1;
5354
5355         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5356                       connector->base.id, drm_get_connector_name(connector),
5357                       encoder->base.id, drm_get_encoder_name(encoder));
5358
5359         /*
5360          * Algorithm gets a little messy:
5361          *
5362          *   - if the connector already has an assigned crtc, use it (but make
5363          *     sure it's on first)
5364          *
5365          *   - try to find the first unused crtc that can drive this connector,
5366          *     and use that if we find one
5367          */
5368
5369         /* See if we already have a CRTC for this connector */
5370         if (encoder->crtc) {
5371                 crtc = encoder->crtc;
5372
5373                 intel_crtc = to_intel_crtc(crtc);
5374                 old->dpms_mode = intel_crtc->dpms_mode;
5375                 old->load_detect_temp = false;
5376
5377                 /* Make sure the crtc and connector are running */
5378                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5379                         struct drm_encoder_helper_funcs *encoder_funcs;
5380                         struct drm_crtc_helper_funcs *crtc_funcs;
5381
5382                         crtc_funcs = crtc->helper_private;
5383                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5384
5385                         encoder_funcs = encoder->helper_private;
5386                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5387                 }
5388
5389                 return true;
5390         }
5391
5392         /* Find an unused one (if possible) */
5393         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5394                 i++;
5395                 if (!(encoder->possible_crtcs & (1 << i)))
5396                         continue;
5397                 if (!possible_crtc->enabled) {
5398                         crtc = possible_crtc;
5399                         break;
5400                 }
5401         }
5402
5403         /*
5404          * If we didn't find an unused CRTC, don't use any.
5405          */
5406         if (!crtc) {
5407                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5408                 return false;
5409         }
5410
5411         encoder->crtc = crtc;
5412         connector->encoder = encoder;
5413
5414         intel_crtc = to_intel_crtc(crtc);
5415         old->dpms_mode = intel_crtc->dpms_mode;
5416         old->load_detect_temp = true;
5417         old->release_fb = NULL;
5418
5419         if (!mode)
5420                 mode = &load_detect_mode;
5421
5422         old_fb = crtc->fb;
5423
5424         /* We need a framebuffer large enough to accommodate all accesses
5425          * that the plane may generate whilst we perform load detection.
5426          * We can not rely on the fbcon either being present (we get called
5427          * during its initialisation to detect all boot displays, or it may
5428          * not even exist) or that it is large enough to satisfy the
5429          * requested mode.
5430          */
5431         crtc->fb = mode_fits_in_fbdev(dev, mode);
5432         if (crtc->fb == NULL) {
5433                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5434                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5435                 old->release_fb = crtc->fb;
5436         } else
5437                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5438         if (IS_ERR(crtc->fb)) {
5439                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5440                 crtc->fb = old_fb;
5441                 return false;
5442         }
5443
5444         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5445                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5446                 if (old->release_fb)
5447                         old->release_fb->funcs->destroy(old->release_fb);
5448                 crtc->fb = old_fb;
5449                 return false;
5450         }
5451
5452         /* let the connector get through one full cycle before testing */
5453         intel_wait_for_vblank(dev, intel_crtc->pipe);
5454
5455         return true;
5456 }
5457
5458 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5459                                     struct drm_connector *connector,
5460                                     struct intel_load_detect_pipe *old)
5461 {
5462         struct drm_encoder *encoder = &intel_encoder->base;
5463         struct drm_device *dev = encoder->dev;
5464         struct drm_crtc *crtc = encoder->crtc;
5465         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5466         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5467
5468         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5469                       connector->base.id, drm_get_connector_name(connector),
5470                       encoder->base.id, drm_get_encoder_name(encoder));
5471
5472         if (old->load_detect_temp) {
5473                 connector->encoder = NULL;
5474                 drm_helper_disable_unused_functions(dev);
5475
5476                 if (old->release_fb)
5477                         old->release_fb->funcs->destroy(old->release_fb);
5478
5479                 return;
5480         }
5481
5482         /* Switch crtc and encoder back off if necessary */
5483         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5484                 encoder_funcs->dpms(encoder, old->dpms_mode);
5485                 crtc_funcs->dpms(crtc, old->dpms_mode);
5486         }
5487 }
5488
5489 /* Returns the clock of the currently programmed mode of the given pipe. */
5490 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5491 {
5492         struct drm_i915_private *dev_priv = dev->dev_private;
5493         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5494         int pipe = intel_crtc->pipe;
5495         u32 dpll = I915_READ(DPLL(pipe));
5496         u32 fp;
5497         intel_clock_t clock;
5498
5499         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5500                 fp = I915_READ(FP0(pipe));
5501         else
5502                 fp = I915_READ(FP1(pipe));
5503
5504         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5505         if (IS_PINEVIEW(dev)) {
5506                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5507                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5508         } else {
5509                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5510                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5511         }
5512
5513         if (!IS_GEN2(dev)) {
5514                 if (IS_PINEVIEW(dev))
5515                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5516                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5517                 else
5518                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5519                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5520
5521                 switch (dpll & DPLL_MODE_MASK) {
5522                 case DPLLB_MODE_DAC_SERIAL:
5523                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5524                                 5 : 10;
5525                         break;
5526                 case DPLLB_MODE_LVDS:
5527                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5528                                 7 : 14;
5529                         break;
5530                 default:
5531                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5532                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5533                         return 0;
5534                 }
5535
5536                 /* XXX: Handle the 100Mhz refclk */
5537                 intel_clock(dev, 96000, &clock);
5538         } else {
5539                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5540
5541                 if (is_lvds) {
5542                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5543                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5544                         clock.p2 = 14;
5545
5546                         if ((dpll & PLL_REF_INPUT_MASK) ==
5547                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5548                                 /* XXX: might not be 66MHz */
5549                                 intel_clock(dev, 66000, &clock);
5550                         } else
5551                                 intel_clock(dev, 48000, &clock);
5552                 } else {
5553                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5554                                 clock.p1 = 2;
5555                         else {
5556                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5557                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5558                         }
5559                         if (dpll & PLL_P2_DIVIDE_BY_4)
5560                                 clock.p2 = 4;
5561                         else
5562                                 clock.p2 = 2;
5563
5564                         intel_clock(dev, 48000, &clock);
5565                 }
5566         }
5567
5568         /* XXX: It would be nice to validate the clocks, but we can't reuse
5569          * i830PllIsValid() because it relies on the xf86_config connector
5570          * configuration being accurate, which it isn't necessarily.
5571          */
5572
5573         return clock.dot;
5574 }
5575
5576 /** Returns the currently programmed mode of the given pipe. */
5577 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5578                                              struct drm_crtc *crtc)
5579 {
5580         struct drm_i915_private *dev_priv = dev->dev_private;
5581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5582         int pipe = intel_crtc->pipe;
5583         struct drm_display_mode *mode;
5584         int htot = I915_READ(HTOTAL(pipe));
5585         int hsync = I915_READ(HSYNC(pipe));
5586         int vtot = I915_READ(VTOTAL(pipe));
5587         int vsync = I915_READ(VSYNC(pipe));
5588
5589         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5590         if (!mode)
5591                 return NULL;
5592
5593         mode->clock = intel_crtc_clock_get(dev, crtc);
5594         mode->hdisplay = (htot & 0xffff) + 1;
5595         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5596         mode->hsync_start = (hsync & 0xffff) + 1;
5597         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5598         mode->vdisplay = (vtot & 0xffff) + 1;
5599         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5600         mode->vsync_start = (vsync & 0xffff) + 1;
5601         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5602
5603         drm_mode_set_name(mode);
5604
5605         return mode;
5606 }
5607
5608 #define GPU_IDLE_TIMEOUT 500 /* ms */
5609
5610 /* When this timer fires, we've been idle for awhile */
5611 static void intel_gpu_idle_timer(unsigned long arg)
5612 {
5613         struct drm_device *dev = (struct drm_device *)arg;
5614         drm_i915_private_t *dev_priv = dev->dev_private;
5615
5616         if (!list_empty(&dev_priv->mm.active_list)) {
5617                 /* Still processing requests, so just re-arm the timer. */
5618                 mod_timer(&dev_priv->idle_timer, jiffies +
5619                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5620                 return;
5621         }
5622
5623         dev_priv->busy = false;
5624         queue_work(dev_priv->wq, &dev_priv->idle_work);
5625 }
5626
5627 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5628
5629 static void intel_crtc_idle_timer(unsigned long arg)
5630 {
5631         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5632         struct drm_crtc *crtc = &intel_crtc->base;
5633         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5634         struct intel_framebuffer *intel_fb;
5635
5636         intel_fb = to_intel_framebuffer(crtc->fb);
5637         if (intel_fb && intel_fb->obj->active) {
5638                 /* The framebuffer is still being accessed by the GPU. */
5639                 mod_timer(&intel_crtc->idle_timer, jiffies +
5640                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5641                 return;
5642         }
5643
5644         intel_crtc->busy = false;
5645         queue_work(dev_priv->wq, &dev_priv->idle_work);
5646 }
5647
5648 static void intel_increase_pllclock(struct drm_crtc *crtc)
5649 {
5650         struct drm_device *dev = crtc->dev;
5651         drm_i915_private_t *dev_priv = dev->dev_private;
5652         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5653         int pipe = intel_crtc->pipe;
5654         int dpll_reg = DPLL(pipe);
5655         int dpll;
5656
5657         if (HAS_PCH_SPLIT(dev))
5658                 return;
5659
5660         if (!dev_priv->lvds_downclock_avail)
5661                 return;
5662
5663         dpll = I915_READ(dpll_reg);
5664         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5665                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5666
5667                 assert_panel_unlocked(dev_priv, pipe);
5668
5669                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5670                 I915_WRITE(dpll_reg, dpll);
5671                 intel_wait_for_vblank(dev, pipe);
5672
5673                 dpll = I915_READ(dpll_reg);
5674                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5675                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5676         }
5677
5678         /* Schedule downclock */
5679         mod_timer(&intel_crtc->idle_timer, jiffies +
5680                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5681 }
5682
5683 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5684 {
5685         struct drm_device *dev = crtc->dev;
5686         drm_i915_private_t *dev_priv = dev->dev_private;
5687         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5688
5689         if (HAS_PCH_SPLIT(dev))
5690                 return;
5691
5692         if (!dev_priv->lvds_downclock_avail)
5693                 return;
5694
5695         /*
5696          * Since this is called by a timer, we should never get here in
5697          * the manual case.
5698          */
5699         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5700                 int pipe = intel_crtc->pipe;
5701                 int dpll_reg = DPLL(pipe);
5702                 int dpll;
5703
5704                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5705
5706                 assert_panel_unlocked(dev_priv, pipe);
5707
5708                 dpll = I915_READ(dpll_reg);
5709                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5710                 I915_WRITE(dpll_reg, dpll);
5711                 intel_wait_for_vblank(dev, pipe);
5712                 dpll = I915_READ(dpll_reg);
5713                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5714                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5715         }
5716
5717 }
5718
5719 /**
5720  * intel_idle_update - adjust clocks for idleness
5721  * @work: work struct
5722  *
5723  * Either the GPU or display (or both) went idle.  Check the busy status
5724  * here and adjust the CRTC and GPU clocks as necessary.
5725  */
5726 static void intel_idle_update(struct work_struct *work)
5727 {
5728         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5729                                                     idle_work);
5730         struct drm_device *dev = dev_priv->dev;
5731         struct drm_crtc *crtc;
5732         struct intel_crtc *intel_crtc;
5733
5734         if (!i915_powersave)
5735                 return;
5736
5737         mutex_lock(&dev->struct_mutex);
5738
5739         i915_update_gfx_val(dev_priv);
5740
5741         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5742                 /* Skip inactive CRTCs */
5743                 if (!crtc->fb)
5744                         continue;
5745
5746                 intel_crtc = to_intel_crtc(crtc);
5747                 if (!intel_crtc->busy)
5748                         intel_decrease_pllclock(crtc);
5749         }
5750
5751
5752         mutex_unlock(&dev->struct_mutex);
5753 }
5754
5755 /**
5756  * intel_mark_busy - mark the GPU and possibly the display busy
5757  * @dev: drm device
5758  * @obj: object we're operating on
5759  *
5760  * Callers can use this function to indicate that the GPU is busy processing
5761  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5762  * buffer), we'll also mark the display as busy, so we know to increase its
5763  * clock frequency.
5764  */
5765 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5766 {
5767         drm_i915_private_t *dev_priv = dev->dev_private;
5768         struct drm_crtc *crtc = NULL;
5769         struct intel_framebuffer *intel_fb;
5770         struct intel_crtc *intel_crtc;
5771
5772         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5773                 return;
5774
5775         if (!dev_priv->busy) {
5776                 intel_sanitize_pm(dev);
5777                 dev_priv->busy = true;
5778         } else
5779                 mod_timer(&dev_priv->idle_timer, jiffies +
5780                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5781
5782         if (obj == NULL)
5783                 return;
5784
5785         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5786                 if (!crtc->fb)
5787                         continue;
5788
5789                 intel_crtc = to_intel_crtc(crtc);
5790                 intel_fb = to_intel_framebuffer(crtc->fb);
5791                 if (intel_fb->obj == obj) {
5792                         if (!intel_crtc->busy) {
5793                                 /* Non-busy -> busy, upclock */
5794                                 intel_increase_pllclock(crtc);
5795                                 intel_crtc->busy = true;
5796                         } else {
5797                                 /* Busy -> busy, put off timer */
5798                                 mod_timer(&intel_crtc->idle_timer, jiffies +
5799                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5800                         }
5801                 }
5802         }
5803 }
5804
5805 static void intel_crtc_destroy(struct drm_crtc *crtc)
5806 {
5807         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5808         struct drm_device *dev = crtc->dev;
5809         struct intel_unpin_work *work;
5810         unsigned long flags;
5811
5812         spin_lock_irqsave(&dev->event_lock, flags);
5813         work = intel_crtc->unpin_work;
5814         intel_crtc->unpin_work = NULL;
5815         spin_unlock_irqrestore(&dev->event_lock, flags);
5816
5817         if (work) {
5818                 cancel_work_sync(&work->work);
5819                 kfree(work);
5820         }
5821
5822         drm_crtc_cleanup(crtc);
5823
5824         kfree(intel_crtc);
5825 }
5826
5827 static void intel_unpin_work_fn(struct work_struct *__work)
5828 {
5829         struct intel_unpin_work *work =
5830                 container_of(__work, struct intel_unpin_work, work);
5831
5832         mutex_lock(&work->dev->struct_mutex);
5833         intel_unpin_fb_obj(work->old_fb_obj);
5834         drm_gem_object_unreference(&work->pending_flip_obj->base);
5835         drm_gem_object_unreference(&work->old_fb_obj->base);
5836
5837         intel_update_fbc(work->dev);
5838         mutex_unlock(&work->dev->struct_mutex);
5839         kfree(work);
5840 }
5841
5842 static void do_intel_finish_page_flip(struct drm_device *dev,
5843                                       struct drm_crtc *crtc)
5844 {
5845         drm_i915_private_t *dev_priv = dev->dev_private;
5846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5847         struct intel_unpin_work *work;
5848         struct drm_i915_gem_object *obj;
5849         struct drm_pending_vblank_event *e;
5850         struct timeval tnow, tvbl;
5851         unsigned long flags;
5852
5853         /* Ignore early vblank irqs */
5854         if (intel_crtc == NULL)
5855                 return;
5856
5857         do_gettimeofday(&tnow);
5858
5859         spin_lock_irqsave(&dev->event_lock, flags);
5860         work = intel_crtc->unpin_work;
5861         if (work == NULL || !work->pending) {
5862                 spin_unlock_irqrestore(&dev->event_lock, flags);
5863                 return;
5864         }
5865
5866         intel_crtc->unpin_work = NULL;
5867
5868         if (work->event) {
5869                 e = work->event;
5870                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5871
5872                 /* Called before vblank count and timestamps have
5873                  * been updated for the vblank interval of flip
5874                  * completion? Need to increment vblank count and
5875                  * add one videorefresh duration to returned timestamp
5876                  * to account for this. We assume this happened if we
5877                  * get called over 0.9 frame durations after the last
5878                  * timestamped vblank.
5879                  *
5880                  * This calculation can not be used with vrefresh rates
5881                  * below 5Hz (10Hz to be on the safe side) without
5882                  * promoting to 64 integers.
5883                  */
5884                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5885                     9 * crtc->framedur_ns) {
5886                         e->event.sequence++;
5887                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5888                                              crtc->framedur_ns);
5889                 }
5890
5891                 e->event.tv_sec = tvbl.tv_sec;
5892                 e->event.tv_usec = tvbl.tv_usec;
5893
5894                 list_add_tail(&e->base.link,
5895                               &e->base.file_priv->event_list);
5896                 wake_up_interruptible(&e->base.file_priv->event_wait);
5897         }
5898
5899         drm_vblank_put(dev, intel_crtc->pipe);
5900
5901         spin_unlock_irqrestore(&dev->event_lock, flags);
5902
5903         obj = work->old_fb_obj;
5904
5905         atomic_clear_mask(1 << intel_crtc->plane,
5906                           &obj->pending_flip.counter);
5907         if (atomic_read(&obj->pending_flip) == 0)
5908                 wake_up(&dev_priv->pending_flip_queue);
5909
5910         schedule_work(&work->work);
5911
5912         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5913 }
5914
5915 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5916 {
5917         drm_i915_private_t *dev_priv = dev->dev_private;
5918         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5919
5920         do_intel_finish_page_flip(dev, crtc);
5921 }
5922
5923 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5924 {
5925         drm_i915_private_t *dev_priv = dev->dev_private;
5926         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5927
5928         do_intel_finish_page_flip(dev, crtc);
5929 }
5930
5931 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5932 {
5933         drm_i915_private_t *dev_priv = dev->dev_private;
5934         struct intel_crtc *intel_crtc =
5935                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5936         unsigned long flags;
5937
5938         spin_lock_irqsave(&dev->event_lock, flags);
5939         if (intel_crtc->unpin_work) {
5940                 if ((++intel_crtc->unpin_work->pending) > 1)
5941                         DRM_ERROR("Prepared flip multiple times\n");
5942         } else {
5943                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5944         }
5945         spin_unlock_irqrestore(&dev->event_lock, flags);
5946 }
5947
5948 static int intel_gen2_queue_flip(struct drm_device *dev,
5949                                  struct drm_crtc *crtc,
5950                                  struct drm_framebuffer *fb,
5951                                  struct drm_i915_gem_object *obj)
5952 {
5953         struct drm_i915_private *dev_priv = dev->dev_private;
5954         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5955         unsigned long offset;
5956         u32 flip_mask;
5957         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5958         int ret;
5959
5960         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5961         if (ret)
5962                 goto err;
5963
5964         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5965         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5966
5967         ret = intel_ring_begin(ring, 6);
5968         if (ret)
5969                 goto err_unpin;
5970
5971         /* Can't queue multiple flips, so wait for the previous
5972          * one to finish before executing the next.
5973          */
5974         if (intel_crtc->plane)
5975                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5976         else
5977                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5978         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5979         intel_ring_emit(ring, MI_NOOP);
5980         intel_ring_emit(ring, MI_DISPLAY_FLIP |
5981                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5982         intel_ring_emit(ring, fb->pitches[0]);
5983         intel_ring_emit(ring, obj->gtt_offset + offset);
5984         intel_ring_emit(ring, 0); /* aux display base address, unused */
5985         intel_ring_advance(ring);
5986         return 0;
5987
5988 err_unpin:
5989         intel_unpin_fb_obj(obj);
5990 err:
5991         return ret;
5992 }
5993
5994 static int intel_gen3_queue_flip(struct drm_device *dev,
5995                                  struct drm_crtc *crtc,
5996                                  struct drm_framebuffer *fb,
5997                                  struct drm_i915_gem_object *obj)
5998 {
5999         struct drm_i915_private *dev_priv = dev->dev_private;
6000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6001         unsigned long offset;
6002         u32 flip_mask;
6003         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6004         int ret;
6005
6006         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6007         if (ret)
6008                 goto err;
6009
6010         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6011         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
6012
6013         ret = intel_ring_begin(ring, 6);
6014         if (ret)
6015                 goto err_unpin;
6016
6017         if (intel_crtc->plane)
6018                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6019         else
6020                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6021         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6022         intel_ring_emit(ring, MI_NOOP);
6023         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6024                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6025         intel_ring_emit(ring, fb->pitches[0]);
6026         intel_ring_emit(ring, obj->gtt_offset + offset);
6027         intel_ring_emit(ring, MI_NOOP);
6028
6029         intel_ring_advance(ring);
6030         return 0;
6031
6032 err_unpin:
6033         intel_unpin_fb_obj(obj);
6034 err:
6035         return ret;
6036 }
6037
6038 static int intel_gen4_queue_flip(struct drm_device *dev,
6039                                  struct drm_crtc *crtc,
6040                                  struct drm_framebuffer *fb,
6041                                  struct drm_i915_gem_object *obj)
6042 {
6043         struct drm_i915_private *dev_priv = dev->dev_private;
6044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6045         uint32_t pf, pipesrc;
6046         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6047         int ret;
6048
6049         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6050         if (ret)
6051                 goto err;
6052
6053         ret = intel_ring_begin(ring, 4);
6054         if (ret)
6055                 goto err_unpin;
6056
6057         /* i965+ uses the linear or tiled offsets from the
6058          * Display Registers (which do not change across a page-flip)
6059          * so we need only reprogram the base address.
6060          */
6061         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6062                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6063         intel_ring_emit(ring, fb->pitches[0]);
6064         intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
6065
6066         /* XXX Enabling the panel-fitter across page-flip is so far
6067          * untested on non-native modes, so ignore it for now.
6068          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6069          */
6070         pf = 0;
6071         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6072         intel_ring_emit(ring, pf | pipesrc);
6073         intel_ring_advance(ring);
6074         return 0;
6075
6076 err_unpin:
6077         intel_unpin_fb_obj(obj);
6078 err:
6079         return ret;
6080 }
6081
6082 static int intel_gen6_queue_flip(struct drm_device *dev,
6083                                  struct drm_crtc *crtc,
6084                                  struct drm_framebuffer *fb,
6085                                  struct drm_i915_gem_object *obj)
6086 {
6087         struct drm_i915_private *dev_priv = dev->dev_private;
6088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6089         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6090         uint32_t pf, pipesrc;
6091         int ret;
6092
6093         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6094         if (ret)
6095                 goto err;
6096
6097         ret = intel_ring_begin(ring, 4);
6098         if (ret)
6099                 goto err_unpin;
6100
6101         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6102                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6103         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6104         intel_ring_emit(ring, obj->gtt_offset);
6105
6106         /* Contrary to the suggestions in the documentation,
6107          * "Enable Panel Fitter" does not seem to be required when page
6108          * flipping with a non-native mode, and worse causes a normal
6109          * modeset to fail.
6110          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6111          */
6112         pf = 0;
6113         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6114         intel_ring_emit(ring, pf | pipesrc);
6115         intel_ring_advance(ring);
6116         return 0;
6117
6118 err_unpin:
6119         intel_unpin_fb_obj(obj);
6120 err:
6121         return ret;
6122 }
6123
6124 /*
6125  * On gen7 we currently use the blit ring because (in early silicon at least)
6126  * the render ring doesn't give us interrpts for page flip completion, which
6127  * means clients will hang after the first flip is queued.  Fortunately the
6128  * blit ring generates interrupts properly, so use it instead.
6129  */
6130 static int intel_gen7_queue_flip(struct drm_device *dev,
6131                                  struct drm_crtc *crtc,
6132                                  struct drm_framebuffer *fb,
6133                                  struct drm_i915_gem_object *obj)
6134 {
6135         struct drm_i915_private *dev_priv = dev->dev_private;
6136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6137         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6138         int ret;
6139
6140         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6141         if (ret)
6142                 goto err;
6143
6144         ret = intel_ring_begin(ring, 4);
6145         if (ret)
6146                 goto err_unpin;
6147
6148         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6149         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6150         intel_ring_emit(ring, (obj->gtt_offset));
6151         intel_ring_emit(ring, (MI_NOOP));
6152         intel_ring_advance(ring);
6153         return 0;
6154
6155 err_unpin:
6156         intel_unpin_fb_obj(obj);
6157 err:
6158         return ret;
6159 }
6160
6161 static int intel_default_queue_flip(struct drm_device *dev,
6162                                     struct drm_crtc *crtc,
6163                                     struct drm_framebuffer *fb,
6164                                     struct drm_i915_gem_object *obj)
6165 {
6166         return -ENODEV;
6167 }
6168
6169 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6170                                 struct drm_framebuffer *fb,
6171                                 struct drm_pending_vblank_event *event)
6172 {
6173         struct drm_device *dev = crtc->dev;
6174         struct drm_i915_private *dev_priv = dev->dev_private;
6175         struct intel_framebuffer *intel_fb;
6176         struct drm_i915_gem_object *obj;
6177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6178         struct intel_unpin_work *work;
6179         unsigned long flags;
6180         int ret;
6181
6182         work = kzalloc(sizeof *work, GFP_KERNEL);
6183         if (work == NULL)
6184                 return -ENOMEM;
6185
6186         work->event = event;
6187         work->dev = crtc->dev;
6188         intel_fb = to_intel_framebuffer(crtc->fb);
6189         work->old_fb_obj = intel_fb->obj;
6190         INIT_WORK(&work->work, intel_unpin_work_fn);
6191
6192         ret = drm_vblank_get(dev, intel_crtc->pipe);
6193         if (ret)
6194                 goto free_work;
6195
6196         /* We borrow the event spin lock for protecting unpin_work */
6197         spin_lock_irqsave(&dev->event_lock, flags);
6198         if (intel_crtc->unpin_work) {
6199                 spin_unlock_irqrestore(&dev->event_lock, flags);
6200                 kfree(work);
6201                 drm_vblank_put(dev, intel_crtc->pipe);
6202
6203                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6204                 return -EBUSY;
6205         }
6206         intel_crtc->unpin_work = work;
6207         spin_unlock_irqrestore(&dev->event_lock, flags);
6208
6209         intel_fb = to_intel_framebuffer(fb);
6210         obj = intel_fb->obj;
6211
6212         mutex_lock(&dev->struct_mutex);
6213
6214         /* Reference the objects for the scheduled work. */
6215         drm_gem_object_reference(&work->old_fb_obj->base);
6216         drm_gem_object_reference(&obj->base);
6217
6218         crtc->fb = fb;
6219
6220         work->pending_flip_obj = obj;
6221
6222         work->enable_stall_check = true;
6223
6224         /* Block clients from rendering to the new back buffer until
6225          * the flip occurs and the object is no longer visible.
6226          */
6227         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6228
6229         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6230         if (ret)
6231                 goto cleanup_pending;
6232
6233         intel_disable_fbc(dev);
6234         intel_mark_busy(dev, obj);
6235         mutex_unlock(&dev->struct_mutex);
6236
6237         trace_i915_flip_request(intel_crtc->plane, obj);
6238
6239         return 0;
6240
6241 cleanup_pending:
6242         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6243         drm_gem_object_unreference(&work->old_fb_obj->base);
6244         drm_gem_object_unreference(&obj->base);
6245         mutex_unlock(&dev->struct_mutex);
6246
6247         spin_lock_irqsave(&dev->event_lock, flags);
6248         intel_crtc->unpin_work = NULL;
6249         spin_unlock_irqrestore(&dev->event_lock, flags);
6250
6251         drm_vblank_put(dev, intel_crtc->pipe);
6252 free_work:
6253         kfree(work);
6254
6255         return ret;
6256 }
6257
6258 static void intel_sanitize_modesetting(struct drm_device *dev,
6259                                        int pipe, int plane)
6260 {
6261         struct drm_i915_private *dev_priv = dev->dev_private;
6262         u32 reg, val;
6263         int i;
6264
6265         /* Clear any frame start delays used for debugging left by the BIOS */
6266         for_each_pipe(i) {
6267                 reg = PIPECONF(i);
6268                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6269         }
6270
6271         if (HAS_PCH_SPLIT(dev))
6272                 return;
6273
6274         /* Who knows what state these registers were left in by the BIOS or
6275          * grub?
6276          *
6277          * If we leave the registers in a conflicting state (e.g. with the
6278          * display plane reading from the other pipe than the one we intend
6279          * to use) then when we attempt to teardown the active mode, we will
6280          * not disable the pipes and planes in the correct order -- leaving
6281          * a plane reading from a disabled pipe and possibly leading to
6282          * undefined behaviour.
6283          */
6284
6285         reg = DSPCNTR(plane);
6286         val = I915_READ(reg);
6287
6288         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6289                 return;
6290         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6291                 return;
6292
6293         /* This display plane is active and attached to the other CPU pipe. */
6294         pipe = !pipe;
6295
6296         /* Disable the plane and wait for it to stop reading from the pipe. */
6297         intel_disable_plane(dev_priv, plane, pipe);
6298         intel_disable_pipe(dev_priv, pipe);
6299 }
6300
6301 static void intel_crtc_reset(struct drm_crtc *crtc)
6302 {
6303         struct drm_device *dev = crtc->dev;
6304         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6305
6306         /* Reset flags back to the 'unknown' status so that they
6307          * will be correctly set on the initial modeset.
6308          */
6309         intel_crtc->dpms_mode = -1;
6310
6311         /* We need to fix up any BIOS configuration that conflicts with
6312          * our expectations.
6313          */
6314         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6315 }
6316
6317 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6318         .dpms = intel_crtc_dpms,
6319         .mode_fixup = intel_crtc_mode_fixup,
6320         .mode_set = intel_crtc_mode_set,
6321         .mode_set_base = intel_pipe_set_base,
6322         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6323         .load_lut = intel_crtc_load_lut,
6324         .disable = intel_crtc_disable,
6325 };
6326
6327 static const struct drm_crtc_funcs intel_crtc_funcs = {
6328         .reset = intel_crtc_reset,
6329         .cursor_set = intel_crtc_cursor_set,
6330         .cursor_move = intel_crtc_cursor_move,
6331         .gamma_set = intel_crtc_gamma_set,
6332         .set_config = drm_crtc_helper_set_config,
6333         .destroy = intel_crtc_destroy,
6334         .page_flip = intel_crtc_page_flip,
6335 };
6336
6337 static void intel_pch_pll_init(struct drm_device *dev)
6338 {
6339         drm_i915_private_t *dev_priv = dev->dev_private;
6340         int i;
6341
6342         if (dev_priv->num_pch_pll == 0) {
6343                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6344                 return;
6345         }
6346
6347         for (i = 0; i < dev_priv->num_pch_pll; i++) {
6348                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6349                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6350                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6351         }
6352 }
6353
6354 static void intel_crtc_init(struct drm_device *dev, int pipe)
6355 {
6356         drm_i915_private_t *dev_priv = dev->dev_private;
6357         struct intel_crtc *intel_crtc;
6358         int i;
6359
6360         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6361         if (intel_crtc == NULL)
6362                 return;
6363
6364         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6365
6366         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6367         for (i = 0; i < 256; i++) {
6368                 intel_crtc->lut_r[i] = i;
6369                 intel_crtc->lut_g[i] = i;
6370                 intel_crtc->lut_b[i] = i;
6371         }
6372
6373         /* Swap pipes & planes for FBC on pre-965 */
6374         intel_crtc->pipe = pipe;
6375         intel_crtc->plane = pipe;
6376         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6377                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6378                 intel_crtc->plane = !pipe;
6379         }
6380
6381         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6382                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6383         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6384         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6385
6386         intel_crtc_reset(&intel_crtc->base);
6387         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6388         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6389
6390         if (HAS_PCH_SPLIT(dev)) {
6391                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6392                 intel_helper_funcs.commit = ironlake_crtc_commit;
6393         } else {
6394                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6395                 intel_helper_funcs.commit = i9xx_crtc_commit;
6396         }
6397
6398         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6399
6400         intel_crtc->busy = false;
6401
6402         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6403                     (unsigned long)intel_crtc);
6404 }
6405
6406 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6407                                 struct drm_file *file)
6408 {
6409         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6410         struct drm_mode_object *drmmode_obj;
6411         struct intel_crtc *crtc;
6412
6413         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6414                 return -ENODEV;
6415
6416         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6417                         DRM_MODE_OBJECT_CRTC);
6418
6419         if (!drmmode_obj) {
6420                 DRM_ERROR("no such CRTC id\n");
6421                 return -EINVAL;
6422         }
6423
6424         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6425         pipe_from_crtc_id->pipe = crtc->pipe;
6426
6427         return 0;
6428 }
6429
6430 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6431 {
6432         struct intel_encoder *encoder;
6433         int index_mask = 0;
6434         int entry = 0;
6435
6436         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6437                 if (type_mask & encoder->clone_mask)
6438                         index_mask |= (1 << entry);
6439                 entry++;
6440         }
6441
6442         return index_mask;
6443 }
6444
6445 static bool has_edp_a(struct drm_device *dev)
6446 {
6447         struct drm_i915_private *dev_priv = dev->dev_private;
6448
6449         if (!IS_MOBILE(dev))
6450                 return false;
6451
6452         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6453                 return false;
6454
6455         if (IS_GEN5(dev) &&
6456             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6457                 return false;
6458
6459         return true;
6460 }
6461
6462 static void intel_setup_outputs(struct drm_device *dev)
6463 {
6464         struct drm_i915_private *dev_priv = dev->dev_private;
6465         struct intel_encoder *encoder;
6466         bool dpd_is_edp = false;
6467         bool has_lvds;
6468
6469         has_lvds = intel_lvds_init(dev);
6470         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6471                 /* disable the panel fitter on everything but LVDS */
6472                 I915_WRITE(PFIT_CONTROL, 0);
6473         }
6474
6475         if (HAS_PCH_SPLIT(dev)) {
6476                 dpd_is_edp = intel_dpd_is_edp(dev);
6477
6478                 if (has_edp_a(dev))
6479                         intel_dp_init(dev, DP_A);
6480
6481                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6482                         intel_dp_init(dev, PCH_DP_D);
6483         }
6484
6485         intel_crt_init(dev);
6486
6487         if (IS_HASWELL(dev)) {
6488                 int found;
6489
6490                 /* Haswell uses DDI functions to detect digital outputs */
6491                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6492                 /* DDI A only supports eDP */
6493                 if (found)
6494                         intel_ddi_init(dev, PORT_A);
6495
6496                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6497                  * register */
6498                 found = I915_READ(SFUSE_STRAP);
6499
6500                 if (found & SFUSE_STRAP_DDIB_DETECTED)
6501                         intel_ddi_init(dev, PORT_B);
6502                 if (found & SFUSE_STRAP_DDIC_DETECTED)
6503                         intel_ddi_init(dev, PORT_C);
6504                 if (found & SFUSE_STRAP_DDID_DETECTED)
6505                         intel_ddi_init(dev, PORT_D);
6506         } else if (HAS_PCH_SPLIT(dev)) {
6507                 int found;
6508
6509                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6510                         /* PCH SDVOB multiplex with HDMIB */
6511                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
6512                         if (!found)
6513                                 intel_hdmi_init(dev, HDMIB);
6514                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6515                                 intel_dp_init(dev, PCH_DP_B);
6516                 }
6517
6518                 if (I915_READ(HDMIC) & PORT_DETECTED)
6519                         intel_hdmi_init(dev, HDMIC);
6520
6521                 if (I915_READ(HDMID) & PORT_DETECTED)
6522                         intel_hdmi_init(dev, HDMID);
6523
6524                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6525                         intel_dp_init(dev, PCH_DP_C);
6526
6527                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6528                         intel_dp_init(dev, PCH_DP_D);
6529
6530         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6531                 bool found = false;
6532
6533                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6534                         DRM_DEBUG_KMS("probing SDVOB\n");
6535                         found = intel_sdvo_init(dev, SDVOB, true);
6536                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6537                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6538                                 intel_hdmi_init(dev, SDVOB);
6539                         }
6540
6541                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6542                                 DRM_DEBUG_KMS("probing DP_B\n");
6543                                 intel_dp_init(dev, DP_B);
6544                         }
6545                 }
6546
6547                 /* Before G4X SDVOC doesn't have its own detect register */
6548
6549                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6550                         DRM_DEBUG_KMS("probing SDVOC\n");
6551                         found = intel_sdvo_init(dev, SDVOC, false);
6552                 }
6553
6554                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6555
6556                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6557                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6558                                 intel_hdmi_init(dev, SDVOC);
6559                         }
6560                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6561                                 DRM_DEBUG_KMS("probing DP_C\n");
6562                                 intel_dp_init(dev, DP_C);
6563                         }
6564                 }
6565
6566                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6567                     (I915_READ(DP_D) & DP_DETECTED)) {
6568                         DRM_DEBUG_KMS("probing DP_D\n");
6569                         intel_dp_init(dev, DP_D);
6570                 }
6571         } else if (IS_GEN2(dev))
6572                 intel_dvo_init(dev);
6573
6574         if (SUPPORTS_TV(dev))
6575                 intel_tv_init(dev);
6576
6577         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6578                 encoder->base.possible_crtcs = encoder->crtc_mask;
6579                 encoder->base.possible_clones =
6580                         intel_encoder_clones(dev, encoder->clone_mask);
6581         }
6582
6583         /* disable all the possible outputs/crtcs before entering KMS mode */
6584         drm_helper_disable_unused_functions(dev);
6585
6586         if (HAS_PCH_SPLIT(dev))
6587                 ironlake_init_pch_refclk(dev);
6588 }
6589
6590 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6591 {
6592         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6593
6594         drm_framebuffer_cleanup(fb);
6595         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6596
6597         kfree(intel_fb);
6598 }
6599
6600 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6601                                                 struct drm_file *file,
6602                                                 unsigned int *handle)
6603 {
6604         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6605         struct drm_i915_gem_object *obj = intel_fb->obj;
6606
6607         return drm_gem_handle_create(file, &obj->base, handle);
6608 }
6609
6610 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6611         .destroy = intel_user_framebuffer_destroy,
6612         .create_handle = intel_user_framebuffer_create_handle,
6613 };
6614
6615 int intel_framebuffer_init(struct drm_device *dev,
6616                            struct intel_framebuffer *intel_fb,
6617                            struct drm_mode_fb_cmd2 *mode_cmd,
6618                            struct drm_i915_gem_object *obj)
6619 {
6620         int ret;
6621
6622         if (obj->tiling_mode == I915_TILING_Y)
6623                 return -EINVAL;
6624
6625         if (mode_cmd->pitches[0] & 63)
6626                 return -EINVAL;
6627
6628         switch (mode_cmd->pixel_format) {
6629         case DRM_FORMAT_RGB332:
6630         case DRM_FORMAT_RGB565:
6631         case DRM_FORMAT_XRGB8888:
6632         case DRM_FORMAT_XBGR8888:
6633         case DRM_FORMAT_ARGB8888:
6634         case DRM_FORMAT_XRGB2101010:
6635         case DRM_FORMAT_ARGB2101010:
6636                 /* RGB formats are common across chipsets */
6637                 break;
6638         case DRM_FORMAT_YUYV:
6639         case DRM_FORMAT_UYVY:
6640         case DRM_FORMAT_YVYU:
6641         case DRM_FORMAT_VYUY:
6642                 break;
6643         default:
6644                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6645                                 mode_cmd->pixel_format);
6646                 return -EINVAL;
6647         }
6648
6649         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6650         if (ret) {
6651                 DRM_ERROR("framebuffer init failed %d\n", ret);
6652                 return ret;
6653         }
6654
6655         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6656         intel_fb->obj = obj;
6657         return 0;
6658 }
6659
6660 static struct drm_framebuffer *
6661 intel_user_framebuffer_create(struct drm_device *dev,
6662                               struct drm_file *filp,
6663                               struct drm_mode_fb_cmd2 *mode_cmd)
6664 {
6665         struct drm_i915_gem_object *obj;
6666
6667         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6668                                                 mode_cmd->handles[0]));
6669         if (&obj->base == NULL)
6670                 return ERR_PTR(-ENOENT);
6671
6672         return intel_framebuffer_create(dev, mode_cmd, obj);
6673 }
6674
6675 static const struct drm_mode_config_funcs intel_mode_funcs = {
6676         .fb_create = intel_user_framebuffer_create,
6677         .output_poll_changed = intel_fb_output_poll_changed,
6678 };
6679
6680 /* Set up chip specific display functions */
6681 static void intel_init_display(struct drm_device *dev)
6682 {
6683         struct drm_i915_private *dev_priv = dev->dev_private;
6684
6685         /* We always want a DPMS function */
6686         if (HAS_PCH_SPLIT(dev)) {
6687                 dev_priv->display.dpms = ironlake_crtc_dpms;
6688                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6689                 dev_priv->display.off = ironlake_crtc_off;
6690                 dev_priv->display.update_plane = ironlake_update_plane;
6691         } else {
6692                 dev_priv->display.dpms = i9xx_crtc_dpms;
6693                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6694                 dev_priv->display.off = i9xx_crtc_off;
6695                 dev_priv->display.update_plane = i9xx_update_plane;
6696         }
6697
6698         /* Returns the core display clock speed */
6699         if (IS_VALLEYVIEW(dev))
6700                 dev_priv->display.get_display_clock_speed =
6701                         valleyview_get_display_clock_speed;
6702         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6703                 dev_priv->display.get_display_clock_speed =
6704                         i945_get_display_clock_speed;
6705         else if (IS_I915G(dev))
6706                 dev_priv->display.get_display_clock_speed =
6707                         i915_get_display_clock_speed;
6708         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6709                 dev_priv->display.get_display_clock_speed =
6710                         i9xx_misc_get_display_clock_speed;
6711         else if (IS_I915GM(dev))
6712                 dev_priv->display.get_display_clock_speed =
6713                         i915gm_get_display_clock_speed;
6714         else if (IS_I865G(dev))
6715                 dev_priv->display.get_display_clock_speed =
6716                         i865_get_display_clock_speed;
6717         else if (IS_I85X(dev))
6718                 dev_priv->display.get_display_clock_speed =
6719                         i855_get_display_clock_speed;
6720         else /* 852, 830 */
6721                 dev_priv->display.get_display_clock_speed =
6722                         i830_get_display_clock_speed;
6723
6724         if (HAS_PCH_SPLIT(dev)) {
6725                 if (IS_GEN5(dev)) {
6726                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6727                         dev_priv->display.write_eld = ironlake_write_eld;
6728                 } else if (IS_GEN6(dev)) {
6729                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6730                         dev_priv->display.write_eld = ironlake_write_eld;
6731                 } else if (IS_IVYBRIDGE(dev)) {
6732                         /* FIXME: detect B0+ stepping and use auto training */
6733                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6734                         dev_priv->display.write_eld = ironlake_write_eld;
6735                 } else if (IS_HASWELL(dev)) {
6736                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
6737                         dev_priv->display.write_eld = ironlake_write_eld;
6738                 } else
6739                         dev_priv->display.update_wm = NULL;
6740         } else if (IS_VALLEYVIEW(dev)) {
6741                 dev_priv->display.force_wake_get = vlv_force_wake_get;
6742                 dev_priv->display.force_wake_put = vlv_force_wake_put;
6743         } else if (IS_G4X(dev)) {
6744                 dev_priv->display.write_eld = g4x_write_eld;
6745         }
6746
6747         /* Default just returns -ENODEV to indicate unsupported */
6748         dev_priv->display.queue_flip = intel_default_queue_flip;
6749
6750         switch (INTEL_INFO(dev)->gen) {
6751         case 2:
6752                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6753                 break;
6754
6755         case 3:
6756                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6757                 break;
6758
6759         case 4:
6760         case 5:
6761                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6762                 break;
6763
6764         case 6:
6765                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6766                 break;
6767         case 7:
6768                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6769                 break;
6770         }
6771 }
6772
6773 /*
6774  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6775  * resume, or other times.  This quirk makes sure that's the case for
6776  * affected systems.
6777  */
6778 static void quirk_pipea_force(struct drm_device *dev)
6779 {
6780         struct drm_i915_private *dev_priv = dev->dev_private;
6781
6782         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6783         DRM_INFO("applying pipe a force quirk\n");
6784 }
6785
6786 /*
6787  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6788  */
6789 static void quirk_ssc_force_disable(struct drm_device *dev)
6790 {
6791         struct drm_i915_private *dev_priv = dev->dev_private;
6792         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6793         DRM_INFO("applying lvds SSC disable quirk\n");
6794 }
6795
6796 /*
6797  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6798  * brightness value
6799  */
6800 static void quirk_invert_brightness(struct drm_device *dev)
6801 {
6802         struct drm_i915_private *dev_priv = dev->dev_private;
6803         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6804         DRM_INFO("applying inverted panel brightness quirk\n");
6805 }
6806
6807 struct intel_quirk {
6808         int device;
6809         int subsystem_vendor;
6810         int subsystem_device;
6811         void (*hook)(struct drm_device *dev);
6812 };
6813
6814 static struct intel_quirk intel_quirks[] = {
6815         /* HP Mini needs pipe A force quirk (LP: #322104) */
6816         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6817
6818         /* Thinkpad R31 needs pipe A force quirk */
6819         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6820         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6821         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6822
6823         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6824         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6825         /* ThinkPad X40 needs pipe A force quirk */
6826
6827         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6828         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6829
6830         /* 855 & before need to leave pipe A & dpll A up */
6831         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6832         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6833
6834         /* Lenovo U160 cannot use SSC on LVDS */
6835         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6836
6837         /* Sony Vaio Y cannot use SSC on LVDS */
6838         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6839
6840         /* Acer Aspire 5734Z must invert backlight brightness */
6841         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6842 };
6843
6844 static void intel_init_quirks(struct drm_device *dev)
6845 {
6846         struct pci_dev *d = dev->pdev;
6847         int i;
6848
6849         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6850                 struct intel_quirk *q = &intel_quirks[i];
6851
6852                 if (d->device == q->device &&
6853                     (d->subsystem_vendor == q->subsystem_vendor ||
6854                      q->subsystem_vendor == PCI_ANY_ID) &&
6855                     (d->subsystem_device == q->subsystem_device ||
6856                      q->subsystem_device == PCI_ANY_ID))
6857                         q->hook(dev);
6858         }
6859 }
6860
6861 /* Disable the VGA plane that we never use */
6862 static void i915_disable_vga(struct drm_device *dev)
6863 {
6864         struct drm_i915_private *dev_priv = dev->dev_private;
6865         u8 sr1;
6866         u32 vga_reg;
6867
6868         if (HAS_PCH_SPLIT(dev))
6869                 vga_reg = CPU_VGACNTRL;
6870         else
6871                 vga_reg = VGACNTRL;
6872
6873         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6874         outb(SR01, VGA_SR_INDEX);
6875         sr1 = inb(VGA_SR_DATA);
6876         outb(sr1 | 1<<5, VGA_SR_DATA);
6877         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6878         udelay(300);
6879
6880         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6881         POSTING_READ(vga_reg);
6882 }
6883
6884 static void ivb_pch_pwm_override(struct drm_device *dev)
6885 {
6886         struct drm_i915_private *dev_priv = dev->dev_private;
6887
6888         /*
6889          * IVB has CPU eDP backlight regs too, set things up to let the
6890          * PCH regs control the backlight
6891          */
6892         I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6893         I915_WRITE(BLC_PWM_CPU_CTL, 0);
6894         I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6895 }
6896
6897 void intel_modeset_init_hw(struct drm_device *dev)
6898 {
6899         struct drm_i915_private *dev_priv = dev->dev_private;
6900
6901         intel_init_clock_gating(dev);
6902
6903         if (IS_IRONLAKE_M(dev)) {
6904                 ironlake_enable_drps(dev);
6905                 ironlake_enable_rc6(dev);
6906                 intel_init_emon(dev);
6907         }
6908
6909         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6910                 gen6_enable_rps(dev_priv);
6911                 gen6_update_ring_freq(dev_priv);
6912         }
6913
6914         if (IS_IVYBRIDGE(dev))
6915                 ivb_pch_pwm_override(dev);
6916 }
6917
6918 void intel_modeset_init(struct drm_device *dev)
6919 {
6920         struct drm_i915_private *dev_priv = dev->dev_private;
6921         int i, ret;
6922
6923         drm_mode_config_init(dev);
6924
6925         dev->mode_config.min_width = 0;
6926         dev->mode_config.min_height = 0;
6927
6928         dev->mode_config.preferred_depth = 24;
6929         dev->mode_config.prefer_shadow = 1;
6930
6931         dev->mode_config.funcs = &intel_mode_funcs;
6932
6933         intel_init_quirks(dev);
6934
6935         intel_init_pm(dev);
6936
6937         intel_prepare_ddi(dev);
6938
6939         intel_init_display(dev);
6940
6941         if (IS_GEN2(dev)) {
6942                 dev->mode_config.max_width = 2048;
6943                 dev->mode_config.max_height = 2048;
6944         } else if (IS_GEN3(dev)) {
6945                 dev->mode_config.max_width = 4096;
6946                 dev->mode_config.max_height = 4096;
6947         } else {
6948                 dev->mode_config.max_width = 8192;
6949                 dev->mode_config.max_height = 8192;
6950         }
6951         dev->mode_config.fb_base = dev->agp->base;
6952
6953         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6954                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6955
6956         for (i = 0; i < dev_priv->num_pipe; i++) {
6957                 intel_crtc_init(dev, i);
6958                 ret = intel_plane_init(dev, i);
6959                 if (ret)
6960                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6961         }
6962
6963         intel_pch_pll_init(dev);
6964
6965         /* Just disable it once at startup */
6966         i915_disable_vga(dev);
6967         intel_setup_outputs(dev);
6968
6969         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6970         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6971                     (unsigned long)dev);
6972 }
6973
6974 void intel_modeset_gem_init(struct drm_device *dev)
6975 {
6976         intel_modeset_init_hw(dev);
6977
6978         intel_setup_overlay(dev);
6979 }
6980
6981 void intel_modeset_cleanup(struct drm_device *dev)
6982 {
6983         struct drm_i915_private *dev_priv = dev->dev_private;
6984         struct drm_crtc *crtc;
6985         struct intel_crtc *intel_crtc;
6986
6987         drm_kms_helper_poll_fini(dev);
6988         mutex_lock(&dev->struct_mutex);
6989
6990         intel_unregister_dsm_handler();
6991
6992
6993         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6994                 /* Skip inactive CRTCs */
6995                 if (!crtc->fb)
6996                         continue;
6997
6998                 intel_crtc = to_intel_crtc(crtc);
6999                 intel_increase_pllclock(crtc);
7000         }
7001
7002         intel_disable_fbc(dev);
7003
7004         if (IS_IRONLAKE_M(dev))
7005                 ironlake_disable_drps(dev);
7006         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
7007                 gen6_disable_rps(dev);
7008
7009         if (IS_IRONLAKE_M(dev))
7010                 ironlake_disable_rc6(dev);
7011
7012         if (IS_VALLEYVIEW(dev))
7013                 vlv_init_dpio(dev);
7014
7015         mutex_unlock(&dev->struct_mutex);
7016
7017         /* Disable the irq before mode object teardown, for the irq might
7018          * enqueue unpin/hotplug work. */
7019         drm_irq_uninstall(dev);
7020         cancel_work_sync(&dev_priv->hotplug_work);
7021         cancel_work_sync(&dev_priv->rps_work);
7022
7023         /* flush any delayed tasks or pending work */
7024         flush_scheduled_work();
7025
7026         /* Shut off idle work before the crtcs get freed. */
7027         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7028                 intel_crtc = to_intel_crtc(crtc);
7029                 del_timer_sync(&intel_crtc->idle_timer);
7030         }
7031         del_timer_sync(&dev_priv->idle_timer);
7032         cancel_work_sync(&dev_priv->idle_work);
7033
7034         drm_mode_config_cleanup(dev);
7035 }
7036
7037 /*
7038  * Return which encoder is currently attached for connector.
7039  */
7040 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7041 {
7042         return &intel_attached_encoder(connector)->base;
7043 }
7044
7045 void intel_connector_attach_encoder(struct intel_connector *connector,
7046                                     struct intel_encoder *encoder)
7047 {
7048         connector->encoder = encoder;
7049         drm_mode_connector_attach_encoder(&connector->base,
7050                                           &encoder->base);
7051 }
7052
7053 /*
7054  * set vga decode state - true == enable VGA decode
7055  */
7056 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7057 {
7058         struct drm_i915_private *dev_priv = dev->dev_private;
7059         u16 gmch_ctrl;
7060
7061         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7062         if (state)
7063                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7064         else
7065                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7066         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7067         return 0;
7068 }
7069
7070 #ifdef CONFIG_DEBUG_FS
7071 #include <linux/seq_file.h>
7072
7073 struct intel_display_error_state {
7074         struct intel_cursor_error_state {
7075                 u32 control;
7076                 u32 position;
7077                 u32 base;
7078                 u32 size;
7079         } cursor[2];
7080
7081         struct intel_pipe_error_state {
7082                 u32 conf;
7083                 u32 source;
7084
7085                 u32 htotal;
7086                 u32 hblank;
7087                 u32 hsync;
7088                 u32 vtotal;
7089                 u32 vblank;
7090                 u32 vsync;
7091         } pipe[2];
7092
7093         struct intel_plane_error_state {
7094                 u32 control;
7095                 u32 stride;
7096                 u32 size;
7097                 u32 pos;
7098                 u32 addr;
7099                 u32 surface;
7100                 u32 tile_offset;
7101         } plane[2];
7102 };
7103
7104 struct intel_display_error_state *
7105 intel_display_capture_error_state(struct drm_device *dev)
7106 {
7107         drm_i915_private_t *dev_priv = dev->dev_private;
7108         struct intel_display_error_state *error;
7109         int i;
7110
7111         error = kmalloc(sizeof(*error), GFP_ATOMIC);
7112         if (error == NULL)
7113                 return NULL;
7114
7115         for (i = 0; i < 2; i++) {
7116                 error->cursor[i].control = I915_READ(CURCNTR(i));
7117                 error->cursor[i].position = I915_READ(CURPOS(i));
7118                 error->cursor[i].base = I915_READ(CURBASE(i));
7119
7120                 error->plane[i].control = I915_READ(DSPCNTR(i));
7121                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7122                 error->plane[i].size = I915_READ(DSPSIZE(i));
7123                 error->plane[i].pos = I915_READ(DSPPOS(i));
7124                 error->plane[i].addr = I915_READ(DSPADDR(i));
7125                 if (INTEL_INFO(dev)->gen >= 4) {
7126                         error->plane[i].surface = I915_READ(DSPSURF(i));
7127                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7128                 }
7129
7130                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7131                 error->pipe[i].source = I915_READ(PIPESRC(i));
7132                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7133                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7134                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7135                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7136                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7137                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7138         }
7139
7140         return error;
7141 }
7142
7143 void
7144 intel_display_print_error_state(struct seq_file *m,
7145                                 struct drm_device *dev,
7146                                 struct intel_display_error_state *error)
7147 {
7148         int i;
7149
7150         for (i = 0; i < 2; i++) {
7151                 seq_printf(m, "Pipe [%d]:\n", i);
7152                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7153                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7154                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7155                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7156                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7157                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7158                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7159                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7160
7161                 seq_printf(m, "Plane [%d]:\n", i);
7162                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7163                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7164                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7165                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
7166                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7167                 if (INTEL_INFO(dev)->gen >= 4) {
7168                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7169                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7170                 }
7171
7172                 seq_printf(m, "Cursor [%d]:\n", i);
7173                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7174                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
7175                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7176         }
7177 }
7178 #endif