drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62         /**
  63          * find_pll() - Find the best values for the PLL
  64          * @limit: limits for the PLL
  65          * @crtc: current CRTC
  66          * @target: target frequency in kHz
  67          * @refclk: reference clock frequency in kHz
  68          * @match_clock: if provided, @best_clock P divider must
  69          *               match the P divider from @match_clock
  70          *               used for LVDS downclocking
  71          * @best_clock: best PLL values found
  72          *
  73          * Returns true on success, false on failure.
  74          */
  75         bool (*find_pll)(const intel_limit_t *limit,
  76                          struct drm_crtc *crtc,
  77                          int target, int refclk,
  78                          intel_clock_t *match_clock,
  79                          intel_clock_t *best_clock);
  80 };
  81
  82 /* FDI */
  83 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  84
  85 int
  86 intel_pch_rawclk(struct drm_device *dev)
  87 {
  88         struct drm_i915_private *dev_priv = dev->dev_private;
  89
  90         WARN_ON(!HAS_PCH_SPLIT(dev));
  91
  92         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  93 }
  94
  95 static bool
  96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                     int target, int refclk, intel_clock_t *match_clock,
  98                     intel_clock_t *best_clock);
  99 static bool
 100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 101                         int target, int refclk, intel_clock_t *match_clock,
 102                         intel_clock_t *best_clock);
 103
 104 static bool
 105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 106                         int target, int refclk, intel_clock_t *match_clock,
 107                         intel_clock_t *best_clock);
 108
 109 static inline u32 /* units of 100MHz */
 110 intel_fdi_link_freq(struct drm_device *dev)
 111 {
 112         if (IS_GEN5(dev)) {
 113                 struct drm_i915_private *dev_priv = dev->dev_private;
 114                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 115         } else
 116                 return 27;
 117 }
 118
 119 static const intel_limit_t intel_limits_i8xx_dvo = {
 120         .dot = { .min = 25000, .max = 350000 },
 121         .vco = { .min = 930000, .max = 1400000 },
 122         .n = { .min = 3, .max = 16 },
 123         .m = { .min = 96, .max = 140 },
 124         .m1 = { .min = 18, .max = 26 },
 125         .m2 = { .min = 6, .max = 16 },
 126         .p = { .min = 4, .max = 128 },
 127         .p1 = { .min = 2, .max = 33 },
 128         .p2 = { .dot_limit = 165000,
 129                 .p2_slow = 4, .p2_fast = 2 },
 130         .find_pll = intel_find_best_PLL,
 131 };
 132
 133 static const intel_limit_t intel_limits_i8xx_lvds = {
 134         .dot = { .min = 25000, .max = 350000 },
 135         .vco = { .min = 930000, .max = 1400000 },
 136         .n = { .min = 3, .max = 16 },
 137         .m = { .min = 96, .max = 140 },
 138         .m1 = { .min = 18, .max = 26 },
 139         .m2 = { .min = 6, .max = 16 },
 140         .p = { .min = 4, .max = 128 },
 141         .p1 = { .min = 1, .max = 6 },
 142         .p2 = { .dot_limit = 165000,
 143                 .p2_slow = 14, .p2_fast = 7 },
 144         .find_pll = intel_find_best_PLL,
 145 };
 146
 147 static const intel_limit_t intel_limits_i9xx_sdvo = {
 148         .dot = { .min = 20000, .max = 400000 },
 149         .vco = { .min = 1400000, .max = 2800000 },
 150         .n = { .min = 1, .max = 6 },
 151         .m = { .min = 70, .max = 120 },
 152         .m1 = { .min = 8, .max = 18 },
 153         .m2 = { .min = 3, .max = 7 },
 154         .p = { .min = 5, .max = 80 },
 155         .p1 = { .min = 1, .max = 8 },
 156         .p2 = { .dot_limit = 200000,
 157                 .p2_slow = 10, .p2_fast = 5 },
 158         .find_pll = intel_find_best_PLL,
 159 };
 160
 161 static const intel_limit_t intel_limits_i9xx_lvds = {
 162         .dot = { .min = 20000, .max = 400000 },
 163         .vco = { .min = 1400000, .max = 2800000 },
 164         .n = { .min = 1, .max = 6 },
 165         .m = { .min = 70, .max = 120 },
 166         .m1 = { .min = 8, .max = 18 },
 167         .m2 = { .min = 3, .max = 7 },
 168         .p = { .min = 7, .max = 98 },
 169         .p1 = { .min = 1, .max = 8 },
 170         .p2 = { .dot_limit = 112000,
 171                 .p2_slow = 14, .p2_fast = 7 },
 172         .find_pll = intel_find_best_PLL,
 173 };
 174
 175
 176 static const intel_limit_t intel_limits_g4x_sdvo = {
 177         .dot = { .min = 25000, .max = 270000 },
 178         .vco = { .min = 1750000, .max = 3500000},
 179         .n = { .min = 1, .max = 4 },
 180         .m = { .min = 104, .max = 138 },
 181         .m1 = { .min = 17, .max = 23 },
 182         .m2 = { .min = 5, .max = 11 },
 183         .p = { .min = 10, .max = 30 },
 184         .p1 = { .min = 1, .max = 3},
 185         .p2 = { .dot_limit = 270000,
 186                 .p2_slow = 10,
 187                 .p2_fast = 10
 188         },
 189         .find_pll = intel_g4x_find_best_PLL,
 190 };
 191
 192 static const intel_limit_t intel_limits_g4x_hdmi = {
 193         .dot = { .min = 22000, .max = 400000 },
 194         .vco = { .min = 1750000, .max = 3500000},
 195         .n = { .min = 1, .max = 4 },
 196         .m = { .min = 104, .max = 138 },
 197         .m1 = { .min = 16, .max = 23 },
 198         .m2 = { .min = 5, .max = 11 },
 199         .p = { .min = 5, .max = 80 },
 200         .p1 = { .min = 1, .max = 8},
 201         .p2 = { .dot_limit = 165000,
 202                 .p2_slow = 10, .p2_fast = 5 },
 203         .find_pll = intel_g4x_find_best_PLL,
 204 };
 205
 206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 207         .dot = { .min = 20000, .max = 115000 },
 208         .vco = { .min = 1750000, .max = 3500000 },
 209         .n = { .min = 1, .max = 3 },
 210         .m = { .min = 104, .max = 138 },
 211         .m1 = { .min = 17, .max = 23 },
 212         .m2 = { .min = 5, .max = 11 },
 213         .p = { .min = 28, .max = 112 },
 214         .p1 = { .min = 2, .max = 8 },
 215         .p2 = { .dot_limit = 0,
 216                 .p2_slow = 14, .p2_fast = 14
 217         },
 218         .find_pll = intel_g4x_find_best_PLL,
 219 };
 220
 221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 222         .dot = { .min = 80000, .max = 224000 },
 223         .vco = { .min = 1750000, .max = 3500000 },
 224         .n = { .min = 1, .max = 3 },
 225         .m = { .min = 104, .max = 138 },
 226         .m1 = { .min = 17, .max = 23 },
 227         .m2 = { .min = 5, .max = 11 },
 228         .p = { .min = 14, .max = 42 },
 229         .p1 = { .min = 2, .max = 6 },
 230         .p2 = { .dot_limit = 0,
 231                 .p2_slow = 7, .p2_fast = 7
 232         },
 233         .find_pll = intel_g4x_find_best_PLL,
 234 };
 235
 236 static const intel_limit_t intel_limits_pineview_sdvo = {
 237         .dot = { .min = 20000, .max = 400000},
 238         .vco = { .min = 1700000, .max = 3500000 },
 239         /* Pineview's Ncounter is a ring counter */
 240         .n = { .min = 3, .max = 6 },
 241         .m = { .min = 2, .max = 256 },
 242         /* Pineview only has one combined m divider, which we treat as m2. */
 243         .m1 = { .min = 0, .max = 0 },
 244         .m2 = { .min = 0, .max = 254 },
 245         .p = { .min = 5, .max = 80 },
 246         .p1 = { .min = 1, .max = 8 },
 247         .p2 = { .dot_limit = 200000,
 248                 .p2_slow = 10, .p2_fast = 5 },
 249         .find_pll = intel_find_best_PLL,
 250 };
 251
 252 static const intel_limit_t intel_limits_pineview_lvds = {
 253         .dot = { .min = 20000, .max = 400000 },
 254         .vco = { .min = 1700000, .max = 3500000 },
 255         .n = { .min = 3, .max = 6 },
 256         .m = { .min = 2, .max = 256 },
 257         .m1 = { .min = 0, .max = 0 },
 258         .m2 = { .min = 0, .max = 254 },
 259         .p = { .min = 7, .max = 112 },
 260         .p1 = { .min = 1, .max = 8 },
 261         .p2 = { .dot_limit = 112000,
 262                 .p2_slow = 14, .p2_fast = 14 },
 263         .find_pll = intel_find_best_PLL,
 264 };
 265
 266 /* Ironlake / Sandybridge
 267  *
 268  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 269  * the range value for them is (actual_value - 2).
 270  */
 271 static const intel_limit_t intel_limits_ironlake_dac = {
 272         .dot = { .min = 25000, .max = 350000 },
 273         .vco = { .min = 1760000, .max = 3510000 },
 274         .n = { .min = 1, .max = 5 },
 275         .m = { .min = 79, .max = 127 },
 276         .m1 = { .min = 12, .max = 22 },
 277         .m2 = { .min = 5, .max = 9 },
 278         .p = { .min = 5, .max = 80 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 225000,
 281                 .p2_slow = 10, .p2_fast = 5 },
 282         .find_pll = intel_g4x_find_best_PLL,
 283 };
 284
 285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 286         .dot = { .min = 25000, .max = 350000 },
 287         .vco = { .min = 1760000, .max = 3510000 },
 288         .n = { .min = 1, .max = 3 },
 289         .m = { .min = 79, .max = 118 },
 290         .m1 = { .min = 12, .max = 22 },
 291         .m2 = { .min = 5, .max = 9 },
 292         .p = { .min = 28, .max = 112 },
 293         .p1 = { .min = 2, .max = 8 },
 294         .p2 = { .dot_limit = 225000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296         .find_pll = intel_g4x_find_best_PLL,
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 127 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 56 },
 307         .p1 = { .min = 2, .max = 8 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310         .find_pll = intel_g4x_find_best_PLL,
 311 };
 312
 313 /* LVDS 100mhz refclk limits. */
 314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 315         .dot = { .min = 25000, .max = 350000 },
 316         .vco = { .min = 1760000, .max = 3510000 },
 317         .n = { .min = 1, .max = 2 },
 318         .m = { .min = 79, .max = 126 },
 319         .m1 = { .min = 12, .max = 22 },
 320         .m2 = { .min = 5, .max = 9 },
 321         .p = { .min = 28, .max = 112 },
 322         .p1 = { .min = 2, .max = 8 },
 323         .p2 = { .dot_limit = 225000,
 324                 .p2_slow = 14, .p2_fast = 14 },
 325         .find_pll = intel_g4x_find_best_PLL,
 326 };
 327
 328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 329         .dot = { .min = 25000, .max = 350000 },
 330         .vco = { .min = 1760000, .max = 3510000 },
 331         .n = { .min = 1, .max = 3 },
 332         .m = { .min = 79, .max = 126 },
 333         .m1 = { .min = 12, .max = 22 },
 334         .m2 = { .min = 5, .max = 9 },
 335         .p = { .min = 14, .max = 42 },
 336         .p1 = { .min = 2, .max = 6 },
 337         .p2 = { .dot_limit = 225000,
 338                 .p2_slow = 7, .p2_fast = 7 },
 339         .find_pll = intel_g4x_find_best_PLL,
 340 };
 341
 342 static const intel_limit_t intel_limits_vlv_dac = {
 343         .dot = { .min = 25000, .max = 270000 },
 344         .vco = { .min = 4000000, .max = 6000000 },
 345         .n = { .min = 1, .max = 7 },
 346         .m = { .min = 22, .max = 450 }, /* guess */
 347         .m1 = { .min = 2, .max = 3 },
 348         .m2 = { .min = 11, .max = 156 },
 349         .p = { .min = 10, .max = 30 },
 350         .p1 = { .min = 1, .max = 3 },
 351         .p2 = { .dot_limit = 270000,
 352                 .p2_slow = 2, .p2_fast = 20 },
 353         .find_pll = intel_vlv_find_best_pll,
 354 };
 355
 356 static const intel_limit_t intel_limits_vlv_hdmi = {
 357         .dot = { .min = 25000, .max = 270000 },
 358         .vco = { .min = 4000000, .max = 6000000 },
 359         .n = { .min = 1, .max = 7 },
 360         .m = { .min = 60, .max = 300 }, /* guess */
 361         .m1 = { .min = 2, .max = 3 },
 362         .m2 = { .min = 11, .max = 156 },
 363         .p = { .min = 10, .max = 30 },
 364         .p1 = { .min = 2, .max = 3 },
 365         .p2 = { .dot_limit = 270000,
 366                 .p2_slow = 2, .p2_fast = 20 },
 367         .find_pll = intel_vlv_find_best_pll,
 368 };
 369
 370 static const intel_limit_t intel_limits_vlv_dp = {
 371         .dot = { .min = 25000, .max = 270000 },
 372         .vco = { .min = 4000000, .max = 6000000 },
 373         .n = { .min = 1, .max = 7 },
 374         .m = { .min = 22, .max = 450 },
 375         .m1 = { .min = 2, .max = 3 },
 376         .m2 = { .min = 11, .max = 156 },
 377         .p = { .min = 10, .max = 30 },
 378         .p1 = { .min = 1, .max = 3 },
 379         .p2 = { .dot_limit = 270000,
 380                 .p2_slow = 2, .p2_fast = 20 },
 381         .find_pll = intel_vlv_find_best_pll,
 382 };
 383
 384 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 385                                                 int refclk)
 386 {
 387         struct drm_device *dev = crtc->dev;
 388         const intel_limit_t *limit;
 389
 390         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 391                 if (intel_is_dual_link_lvds(dev)) {
 392                         if (refclk == 100000)
 393                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 394                         else
 395                                 limit = &intel_limits_ironlake_dual_lvds;
 396                 } else {
 397                         if (refclk == 100000)
 398                                 limit = &intel_limits_ironlake_single_lvds_100m;
 399                         else
 400                                 limit = &intel_limits_ironlake_single_lvds;
 401                 }
 402         } else
 403                 limit = &intel_limits_ironlake_dac;
 404
 405         return limit;
 406 }
 407
 408 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 409 {
 410         struct drm_device *dev = crtc->dev;
 411         const intel_limit_t *limit;
 412
 413         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 414                 if (intel_is_dual_link_lvds(dev))
 415                         limit = &intel_limits_g4x_dual_channel_lvds;
 416                 else
 417                         limit = &intel_limits_g4x_single_channel_lvds;
 418         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 419                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 420                 limit = &intel_limits_g4x_hdmi;
 421         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 422                 limit = &intel_limits_g4x_sdvo;
 423         } else /* The option is for other outputs */
 424                 limit = &intel_limits_i9xx_sdvo;
 425
 426         return limit;
 427 }
 428
 429 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 430 {
 431         struct drm_device *dev = crtc->dev;
 432         const intel_limit_t *limit;
 433
 434         if (HAS_PCH_SPLIT(dev))
 435                 limit = intel_ironlake_limit(crtc, refclk);
 436         else if (IS_G4X(dev)) {
 437                 limit = intel_g4x_limit(crtc);
 438         } else if (IS_PINEVIEW(dev)) {
 439                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 440                         limit = &intel_limits_pineview_lvds;
 441                 else
 442                         limit = &intel_limits_pineview_sdvo;
 443         } else if (IS_VALLEYVIEW(dev)) {
 444                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 445                         limit = &intel_limits_vlv_dac;
 446                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 447                         limit = &intel_limits_vlv_hdmi;
 448                 else
 449                         limit = &intel_limits_vlv_dp;
 450         } else if (!IS_GEN2(dev)) {
 451                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 452                         limit = &intel_limits_i9xx_lvds;
 453                 else
 454                         limit = &intel_limits_i9xx_sdvo;
 455         } else {
 456                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 457                         limit = &intel_limits_i8xx_lvds;
 458                 else
 459                         limit = &intel_limits_i8xx_dvo;
 460         }
 461         return limit;
 462 }
 463
 464 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 465 static void pineview_clock(int refclk, intel_clock_t *clock)
 466 {
 467         clock->m = clock->m2 + 2;
 468         clock->p = clock->p1 * clock->p2;
 469         clock->vco = refclk * clock->m / clock->n;
 470         clock->dot = clock->vco / clock->p;
 471 }
 472
 473 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 474 {
 475         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 476 }
 477
 478 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 479 {
 480         if (IS_PINEVIEW(dev)) {
 481                 pineview_clock(refclk, clock);
 482                 return;
 483         }
 484         clock->m = i9xx_dpll_compute_m(clock);
 485         clock->p = clock->p1 * clock->p2;
 486         clock->vco = refclk * clock->m / (clock->n + 2);
 487         clock->dot = clock->vco / clock->p;
 488 }
 489
 490 /**
 491  * Returns whether any output on the specified pipe is of the specified type
 492  */
 493 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 494 {
 495         struct drm_device *dev = crtc->dev;
 496         struct intel_encoder *encoder;
 497
 498         for_each_encoder_on_crtc(dev, crtc, encoder)
 499                 if (encoder->type == type)
 500                         return true;
 501
 502         return false;
 503 }
 504
 505 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 506 /**
 507  * Returns whether the given set of divisors are valid for a given refclk with
 508  * the given connectors.
 509  */
 510
 511 static bool intel_PLL_is_valid(struct drm_device *dev,
 512                                const intel_limit_t *limit,
 513                                const intel_clock_t *clock)
 514 {
 515         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 516                 INTELPllInvalid("p1 out of range\n");
 517         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 518                 INTELPllInvalid("p out of range\n");
 519         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 520                 INTELPllInvalid("m2 out of range\n");
 521         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 522                 INTELPllInvalid("m1 out of range\n");
 523         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 524                 INTELPllInvalid("m1 <= m2\n");
 525         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 526                 INTELPllInvalid("m out of range\n");
 527         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 528                 INTELPllInvalid("n out of range\n");
 529         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 530                 INTELPllInvalid("vco out of range\n");
 531         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 532          * connector, etc., rather than just a single range.
 533          */
 534         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 535                 INTELPllInvalid("dot out of range\n");
 536
 537         return true;
 538 }
 539
 540 static bool
 541 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 542                     int target, int refclk, intel_clock_t *match_clock,
 543                     intel_clock_t *best_clock)
 544
 545 {
 546         struct drm_device *dev = crtc->dev;
 547         intel_clock_t clock;
 548         int err = target;
 549
 550         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 551                 /*
 552                  * For LVDS just rely on its current settings for dual-channel.
 553                  * We haven't figured out how to reliably set up different
 554                  * single/dual channel state, if we even can.
 555                  */
 556                 if (intel_is_dual_link_lvds(dev))
 557                         clock.p2 = limit->p2.p2_fast;
 558                 else
 559                         clock.p2 = limit->p2.p2_slow;
 560         } else {
 561                 if (target < limit->p2.dot_limit)
 562                         clock.p2 = limit->p2.p2_slow;
 563                 else
 564                         clock.p2 = limit->p2.p2_fast;
 565         }
 566
 567         memset(best_clock, 0, sizeof(*best_clock));
 568
 569         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 570              clock.m1++) {
 571                 for (clock.m2 = limit->m2.min;
 572                      clock.m2 <= limit->m2.max; clock.m2++) {
 573                         /* m1 is always 0 in Pineview */
 574                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 575                                 break;
 576                         for (clock.n = limit->n.min;
 577                              clock.n <= limit->n.max; clock.n++) {
 578                                 for (clock.p1 = limit->p1.min;
 579                                         clock.p1 <= limit->p1.max; clock.p1++) {
 580                                         int this_err;
 581
 582                                         intel_clock(dev, refclk, &clock);
 583                                         if (!intel_PLL_is_valid(dev, limit,
 584                                                                 &clock))
 585                                                 continue;
 586                                         if (match_clock &&
 587                                             clock.p != match_clock->p)
 588                                                 continue;
 589
 590                                         this_err = abs(clock.dot - target);
 591                                         if (this_err < err) {
 592                                                 *best_clock = clock;
 593                                                 err = this_err;
 594                                         }
 595                                 }
 596                         }
 597                 }
 598         }
 599
 600         return (err != target);
 601 }
 602
 603 static bool
 604 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 605                         int target, int refclk, intel_clock_t *match_clock,
 606                         intel_clock_t *best_clock)
 607 {
 608         struct drm_device *dev = crtc->dev;
 609         intel_clock_t clock;
 610         int max_n;
 611         bool found;
 612         /* approximately equals target * 0.00585 */
 613         int err_most = (target >> 8) + (target >> 9);
 614         found = false;
 615
 616         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 617                 if (intel_is_dual_link_lvds(dev))
 618                         clock.p2 = limit->p2.p2_fast;
 619                 else
 620                         clock.p2 = limit->p2.p2_slow;
 621         } else {
 622                 if (target < limit->p2.dot_limit)
 623                         clock.p2 = limit->p2.p2_slow;
 624                 else
 625                         clock.p2 = limit->p2.p2_fast;
 626         }
 627
 628         memset(best_clock, 0, sizeof(*best_clock));
 629         max_n = limit->n.max;
 630         /* based on hardware requirement, prefer smaller n to precision */
 631         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 632                 /* based on hardware requirement, prefere larger m1,m2 */
 633                 for (clock.m1 = limit->m1.max;
 634                      clock.m1 >= limit->m1.min; clock.m1--) {
 635                         for (clock.m2 = limit->m2.max;
 636                              clock.m2 >= limit->m2.min; clock.m2--) {
 637                                 for (clock.p1 = limit->p1.max;
 638                                      clock.p1 >= limit->p1.min; clock.p1--) {
 639                                         int this_err;
 640
 641                                         intel_clock(dev, refclk, &clock);
 642                                         if (!intel_PLL_is_valid(dev, limit,
 643                                                                 &clock))
 644                                                 continue;
 645
 646                                         this_err = abs(clock.dot - target);
 647                                         if (this_err < err_most) {
 648                                                 *best_clock = clock;
 649                                                 err_most = this_err;
 650                                                 max_n = clock.n;
 651                                                 found = true;
 652                                         }
 653                                 }
 654                         }
 655                 }
 656         }
 657         return found;
 658 }
 659
 660 static bool
 661 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 662                         int target, int refclk, intel_clock_t *match_clock,
 663                         intel_clock_t *best_clock)
 664 {
 665         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 666         u32 m, n, fastclk;
 667         u32 updrate, minupdate, fracbits, p;
 668         unsigned long bestppm, ppm, absppm;
 669         int dotclk, flag;
 670
 671         flag = 0;
 672         dotclk = target * 1000;
 673         bestppm = 1000000;
 674         ppm = absppm = 0;
 675         fastclk = dotclk / (2*100);
 676         updrate = 0;
 677         minupdate = 19200;
 678         fracbits = 1;
 679         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 680         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 681
 682         /* based on hardware requirement, prefer smaller n to precision */
 683         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 684                 updrate = refclk / n;
 685                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 686                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 687                                 if (p2 > 10)
 688                                         p2 = p2 - 1;
 689                                 p = p1 * p2;
 690                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 691                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 692                                         m2 = (((2*(fastclk * p * n / m1 )) +
 693                                                refclk) / (2*refclk));
 694                                         m = m1 * m2;
 695                                         vco = updrate * m;
 696                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 697                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 698                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 699                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 700                                                         bestppm = 0;
 701                                                         flag = 1;
 702                                                 }
 703                                                 if (absppm < bestppm - 10) {
 704                                                         bestppm = absppm;
 705                                                         flag = 1;
 706                                                 }
 707                                                 if (flag) {
 708                                                         bestn = n;
 709                                                         bestm1 = m1;
 710                                                         bestm2 = m2;
 711                                                         bestp1 = p1;
 712                                                         bestp2 = p2;
 713                                                         flag = 0;
 714                                                 }
 715                                         }
 716                                 }
 717                         }
 718                 }
 719         }
 720         best_clock->n = bestn;
 721         best_clock->m1 = bestm1;
 722         best_clock->m2 = bestm2;
 723         best_clock->p1 = bestp1;
 724         best_clock->p2 = bestp2;
 725
 726         return true;
 727 }
 728
 729 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 730                                              enum pipe pipe)
 731 {
 732         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 734
 735         return intel_crtc->config.cpu_transcoder;
 736 }
 737
 738 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 739 {
 740         struct drm_i915_private *dev_priv = dev->dev_private;
 741         u32 frame, frame_reg = PIPEFRAME(pipe);
 742
 743         frame = I915_READ(frame_reg);
 744
 745         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 746                 DRM_DEBUG_KMS("vblank wait timed out\n");
 747 }
 748
 749 /**
 750  * intel_wait_for_vblank - wait for vblank on a given pipe
 751  * @dev: drm device
 752  * @pipe: pipe to wait for
 753  *
 754  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 755  * mode setting code.
 756  */
 757 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 758 {
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         int pipestat_reg = PIPESTAT(pipe);
 761
 762         if (INTEL_INFO(dev)->gen >= 5) {
 763                 ironlake_wait_for_vblank(dev, pipe);
 764                 return;
 765         }
 766
 767         /* Clear existing vblank status. Note this will clear any other
 768          * sticky status fields as well.
 769          *
 770          * This races with i915_driver_irq_handler() with the result
 771          * that either function could miss a vblank event.  Here it is not
 772          * fatal, as we will either wait upon the next vblank interrupt or
 773          * timeout.  Generally speaking intel_wait_for_vblank() is only
 774          * called during modeset at which time the GPU should be idle and
 775          * should *not* be performing page flips and thus not waiting on
 776          * vblanks...
 777          * Currently, the result of us stealing a vblank from the irq
 778          * handler is that a single frame will be skipped during swapbuffers.
 779          */
 780         I915_WRITE(pipestat_reg,
 781                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 782
 783         /* Wait for vblank interrupt bit to set */
 784         if (wait_for(I915_READ(pipestat_reg) &
 785                      PIPE_VBLANK_INTERRUPT_STATUS,
 786                      50))
 787                 DRM_DEBUG_KMS("vblank wait timed out\n");
 788 }
 789
 790 /*
 791  * intel_wait_for_pipe_off - wait for pipe to turn off
 792  * @dev: drm device
 793  * @pipe: pipe to wait for
 794  *
 795  * After disabling a pipe, we can't wait for vblank in the usual way,
 796  * spinning on the vblank interrupt status bit, since we won't actually
 797  * see an interrupt when the pipe is disabled.
 798  *
 799  * On Gen4 and above:
 800  *   wait for the pipe register state bit to turn off
 801  *
 802  * Otherwise:
 803  *   wait for the display line value to settle (it usually
 804  *   ends up stopping at the start of the next frame).
 805  *
 806  */
 807 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 808 {
 809         struct drm_i915_private *dev_priv = dev->dev_private;
 810         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 811                                                                       pipe);
 812
 813         if (INTEL_INFO(dev)->gen >= 4) {
 814                 int reg = PIPECONF(cpu_transcoder);
 815
 816                 /* Wait for the Pipe State to go off */
 817                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 818                              100))
 819                         WARN(1, "pipe_off wait timed out\n");
 820         } else {
 821                 u32 last_line, line_mask;
 822                 int reg = PIPEDSL(pipe);
 823                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 824
 825                 if (IS_GEN2(dev))
 826                         line_mask = DSL_LINEMASK_GEN2;
 827                 else
 828                         line_mask = DSL_LINEMASK_GEN3;
 829
 830                 /* Wait for the display line to settle */
 831                 do {
 832                         last_line = I915_READ(reg) & line_mask;
 833                         mdelay(5);
 834                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 835                          time_after(timeout, jiffies));
 836                 if (time_after(jiffies, timeout))
 837                         WARN(1, "pipe_off wait timed out\n");
 838         }
 839 }
 840
 841 /*
 842  * ibx_digital_port_connected - is the specified port connected?
 843  * @dev_priv: i915 private structure
 844  * @port: the port to test
 845  *
 846  * Returns true if @port is connected, false otherwise.
 847  */
 848 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 849                                 struct intel_digital_port *port)
 850 {
 851         u32 bit;
 852
 853         if (HAS_PCH_IBX(dev_priv->dev)) {
 854                 switch(port->port) {
 855                 case PORT_B:
 856                         bit = SDE_PORTB_HOTPLUG;
 857                         break;
 858                 case PORT_C:
 859                         bit = SDE_PORTC_HOTPLUG;
 860                         break;
 861                 case PORT_D:
 862                         bit = SDE_PORTD_HOTPLUG;
 863                         break;
 864                 default:
 865                         return true;
 866                 }
 867         } else {
 868                 switch(port->port) {
 869                 case PORT_B:
 870                         bit = SDE_PORTB_HOTPLUG_CPT;
 871                         break;
 872                 case PORT_C:
 873                         bit = SDE_PORTC_HOTPLUG_CPT;
 874                         break;
 875                 case PORT_D:
 876                         bit = SDE_PORTD_HOTPLUG_CPT;
 877                         break;
 878                 default:
 879                         return true;
 880                 }
 881         }
 882
 883         return I915_READ(SDEISR) & bit;
 884 }
 885
 886 static const char *state_string(bool enabled)
 887 {
 888         return enabled ? "on" : "off";
 889 }
 890
 891 /* Only for pre-ILK configs */
 892 static void assert_pll(struct drm_i915_private *dev_priv,
 893                        enum pipe pipe, bool state)
 894 {
 895         int reg;
 896         u32 val;
 897         bool cur_state;
 898
 899         reg = DPLL(pipe);
 900         val = I915_READ(reg);
 901         cur_state = !!(val & DPLL_VCO_ENABLE);
 902         WARN(cur_state != state,
 903              "PLL state assertion failure (expected %s, current %s)\n",
 904              state_string(state), state_string(cur_state));
 905 }
 906 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 907 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 908
 909 /* For ILK+ */
 910 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 911                            struct intel_pch_pll *pll,
 912                            struct intel_crtc *crtc,
 913                            bool state)
 914 {
 915         u32 val;
 916         bool cur_state;
 917
 918         if (HAS_PCH_LPT(dev_priv->dev)) {
 919                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 920                 return;
 921         }
 922
 923         if (WARN (!pll,
 924                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
 925                 return;
 926
 927         val = I915_READ(pll->pll_reg);
 928         cur_state = !!(val & DPLL_VCO_ENABLE);
 929         WARN(cur_state != state,
 930              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
 931              pll->pll_reg, state_string(state), state_string(cur_state), val);
 932
 933         /* Make sure the selected PLL is correctly attached to the transcoder */
 934         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
 935                 u32 pch_dpll;
 936
 937                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 938                 cur_state = pll->pll_reg == _PCH_DPLL_B;
 939                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 940                           "PLL[%d] not attached to this transcoder %c: %08x\n",
 941                           cur_state, pipe_name(crtc->pipe), pch_dpll)) {
 942                         cur_state = !!(val >> (4*crtc->pipe + 3));
 943                         WARN(cur_state != state,
 944                              "PLL[%d] not %s on this transcoder %c: %08x\n",
 945                              pll->pll_reg == _PCH_DPLL_B,
 946                              state_string(state),
 947                              pipe_name(crtc->pipe),
 948                              val);
 949                 }
 950         }
 951 }
 952 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
 953 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
 954
 955 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 956                           enum pipe pipe, bool state)
 957 {
 958         int reg;
 959         u32 val;
 960         bool cur_state;
 961         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 962                                                                       pipe);
 963
 964         if (HAS_DDI(dev_priv->dev)) {
 965                 /* DDI does not have a specific FDI_TX register */
 966                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 967                 val = I915_READ(reg);
 968                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 969         } else {
 970                 reg = FDI_TX_CTL(pipe);
 971                 val = I915_READ(reg);
 972                 cur_state = !!(val & FDI_TX_ENABLE);
 973         }
 974         WARN(cur_state != state,
 975              "FDI TX state assertion failure (expected %s, current %s)\n",
 976              state_string(state), state_string(cur_state));
 977 }
 978 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 979 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 980
 981 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 982                           enum pipe pipe, bool state)
 983 {
 984         int reg;
 985         u32 val;
 986         bool cur_state;
 987
 988         reg = FDI_RX_CTL(pipe);
 989         val = I915_READ(reg);
 990         cur_state = !!(val & FDI_RX_ENABLE);
 991         WARN(cur_state != state,
 992              "FDI RX state assertion failure (expected %s, current %s)\n",
 993              state_string(state), state_string(cur_state));
 994 }
 995 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 996 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 997
 998 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 999                                       enum pipe pipe)
1000 {
1001         int reg;
1002         u32 val;
1003
1004         /* ILK FDI PLL is always enabled */
1005         if (dev_priv->info->gen == 5)
1006                 return;
1007
1008         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1009         if (HAS_DDI(dev_priv->dev))
1010                 return;
1011
1012         reg = FDI_TX_CTL(pipe);
1013         val = I915_READ(reg);
1014         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1015 }
1016
1017 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1018                                       enum pipe pipe)
1019 {
1020         int reg;
1021         u32 val;
1022
1023         reg = FDI_RX_CTL(pipe);
1024         val = I915_READ(reg);
1025         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1026 }
1027
1028 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1029                                   enum pipe pipe)
1030 {
1031         int pp_reg, lvds_reg;
1032         u32 val;
1033         enum pipe panel_pipe = PIPE_A;
1034         bool locked = true;
1035
1036         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1037                 pp_reg = PCH_PP_CONTROL;
1038                 lvds_reg = PCH_LVDS;
1039         } else {
1040                 pp_reg = PP_CONTROL;
1041                 lvds_reg = LVDS;
1042         }
1043
1044         val = I915_READ(pp_reg);
1045         if (!(val & PANEL_POWER_ON) ||
1046             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1047                 locked = false;
1048
1049         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1050                 panel_pipe = PIPE_B;
1051
1052         WARN(panel_pipe == pipe && locked,
1053              "panel assertion failure, pipe %c regs locked\n",
1054              pipe_name(pipe));
1055 }
1056
1057 void assert_pipe(struct drm_i915_private *dev_priv,
1058                  enum pipe pipe, bool state)
1059 {
1060         int reg;
1061         u32 val;
1062         bool cur_state;
1063         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1064                                                                       pipe);
1065
1066         /* if we need the pipe A quirk it must be always on */
1067         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1068                 state = true;
1069
1070         if (!intel_display_power_enabled(dev_priv->dev,
1071                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1072                 cur_state = false;
1073         } else {
1074                 reg = PIPECONF(cpu_transcoder);
1075                 val = I915_READ(reg);
1076                 cur_state = !!(val & PIPECONF_ENABLE);
1077         }
1078
1079         WARN(cur_state != state,
1080              "pipe %c assertion failure (expected %s, current %s)\n",
1081              pipe_name(pipe), state_string(state), state_string(cur_state));
1082 }
1083
1084 static void assert_plane(struct drm_i915_private *dev_priv,
1085                          enum plane plane, bool state)
1086 {
1087         int reg;
1088         u32 val;
1089         bool cur_state;
1090
1091         reg = DSPCNTR(plane);
1092         val = I915_READ(reg);
1093         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1094         WARN(cur_state != state,
1095              "plane %c assertion failure (expected %s, current %s)\n",
1096              plane_name(plane), state_string(state), state_string(cur_state));
1097 }
1098
1099 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1100 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1101
1102 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1103                                    enum pipe pipe)
1104 {
1105         int reg, i;
1106         u32 val;
1107         int cur_pipe;
1108
1109         /* Planes are fixed to pipes on ILK+ */
1110         if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1111                 reg = DSPCNTR(pipe);
1112                 val = I915_READ(reg);
1113                 WARN((val & DISPLAY_PLANE_ENABLE),
1114                      "plane %c assertion failure, should be disabled but not\n",
1115                      plane_name(pipe));
1116                 return;
1117         }
1118
1119         /* Need to check both planes against the pipe */
1120         for (i = 0; i < 2; i++) {
1121                 reg = DSPCNTR(i);
1122                 val = I915_READ(reg);
1123                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1124                         DISPPLANE_SEL_PIPE_SHIFT;
1125                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1126                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1127                      plane_name(i), pipe_name(pipe));
1128         }
1129 }
1130
1131 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1132                                     enum pipe pipe)
1133 {
1134         int reg, i;
1135         u32 val;
1136
1137         if (!IS_VALLEYVIEW(dev_priv->dev))
1138                 return;
1139
1140         /* Need to check both planes against the pipe */
1141         for (i = 0; i < dev_priv->num_plane; i++) {
1142                 reg = SPCNTR(pipe, i);
1143                 val = I915_READ(reg);
1144                 WARN((val & SP_ENABLE),
1145                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1146                      sprite_name(pipe, i), pipe_name(pipe));
1147         }
1148 }
1149
1150 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1151 {
1152         u32 val;
1153         bool enabled;
1154
1155         if (HAS_PCH_LPT(dev_priv->dev)) {
1156                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1157                 return;
1158         }
1159
1160         val = I915_READ(PCH_DREF_CONTROL);
1161         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1162                             DREF_SUPERSPREAD_SOURCE_MASK));
1163         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1164 }
1165
1166 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1167                                            enum pipe pipe)
1168 {
1169         int reg;
1170         u32 val;
1171         bool enabled;
1172
1173         reg = PCH_TRANSCONF(pipe);
1174         val = I915_READ(reg);
1175         enabled = !!(val & TRANS_ENABLE);
1176         WARN(enabled,
1177              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1178              pipe_name(pipe));
1179 }
1180
1181 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1182                             enum pipe pipe, u32 port_sel, u32 val)
1183 {
1184         if ((val & DP_PORT_EN) == 0)
1185                 return false;
1186
1187         if (HAS_PCH_CPT(dev_priv->dev)) {
1188                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1189                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1190                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1191                         return false;
1192         } else {
1193                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1194                         return false;
1195         }
1196         return true;
1197 }
1198
1199 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1200                               enum pipe pipe, u32 val)
1201 {
1202         if ((val & SDVO_ENABLE) == 0)
1203                 return false;
1204
1205         if (HAS_PCH_CPT(dev_priv->dev)) {
1206                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1207                         return false;
1208         } else {
1209                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1210                         return false;
1211         }
1212         return true;
1213 }
1214
1215 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1216                               enum pipe pipe, u32 val)
1217 {
1218         if ((val & LVDS_PORT_EN) == 0)
1219                 return false;
1220
1221         if (HAS_PCH_CPT(dev_priv->dev)) {
1222                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1223                         return false;
1224         } else {
1225                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1226                         return false;
1227         }
1228         return true;
1229 }
1230
1231 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1232                               enum pipe pipe, u32 val)
1233 {
1234         if ((val & ADPA_DAC_ENABLE) == 0)
1235                 return false;
1236         if (HAS_PCH_CPT(dev_priv->dev)) {
1237                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1238                         return false;
1239         } else {
1240                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1241                         return false;
1242         }
1243         return true;
1244 }
1245
1246 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1247                                    enum pipe pipe, int reg, u32 port_sel)
1248 {
1249         u32 val = I915_READ(reg);
1250         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1251              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1252              reg, pipe_name(pipe));
1253
1254         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1255              && (val & DP_PIPEB_SELECT),
1256              "IBX PCH dp port still using transcoder B\n");
1257 }
1258
1259 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1260                                      enum pipe pipe, int reg)
1261 {
1262         u32 val = I915_READ(reg);
1263         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1264              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1265              reg, pipe_name(pipe));
1266
1267         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1268              && (val & SDVO_PIPE_B_SELECT),
1269              "IBX PCH hdmi port still using transcoder B\n");
1270 }
1271
1272 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1273                                       enum pipe pipe)
1274 {
1275         int reg;
1276         u32 val;
1277
1278         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1279         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1280         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1281
1282         reg = PCH_ADPA;
1283         val = I915_READ(reg);
1284         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1285              "PCH VGA enabled on transcoder %c, should be disabled\n",
1286              pipe_name(pipe));
1287
1288         reg = PCH_LVDS;
1289         val = I915_READ(reg);
1290         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1291              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1292              pipe_name(pipe));
1293
1294         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1295         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1296         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1297 }
1298
1299 /**
1300  * intel_enable_pll - enable a PLL
1301  * @dev_priv: i915 private structure
1302  * @pipe: pipe PLL to enable
1303  *
1304  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1305  * make sure the PLL reg is writable first though, since the panel write
1306  * protect mechanism may be enabled.
1307  *
1308  * Note!  This is for pre-ILK only.
1309  *
1310  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1311  */
1312 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1313 {
1314         int reg;
1315         u32 val;
1316
1317         assert_pipe_disabled(dev_priv, pipe);
1318
1319         /* No really, not for ILK+ */
1320         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1321
1322         /* PLL is protected by panel, make sure we can write it */
1323         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1324                 assert_panel_unlocked(dev_priv, pipe);
1325
1326         reg = DPLL(pipe);
1327         val = I915_READ(reg);
1328         val |= DPLL_VCO_ENABLE;
1329
1330         /* We do this three times for luck */
1331         I915_WRITE(reg, val);
1332         POSTING_READ(reg);
1333         udelay(150); /* wait for warmup */
1334         I915_WRITE(reg, val);
1335         POSTING_READ(reg);
1336         udelay(150); /* wait for warmup */
1337         I915_WRITE(reg, val);
1338         POSTING_READ(reg);
1339         udelay(150); /* wait for warmup */
1340 }
1341
1342 /**
1343  * intel_disable_pll - disable a PLL
1344  * @dev_priv: i915 private structure
1345  * @pipe: pipe PLL to disable
1346  *
1347  * Disable the PLL for @pipe, making sure the pipe is off first.
1348  *
1349  * Note!  This is for pre-ILK only.
1350  */
1351 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1352 {
1353         int reg;
1354         u32 val;
1355
1356         /* Don't disable pipe A or pipe A PLLs if needed */
1357         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1358                 return;
1359
1360         /* Make sure the pipe isn't still relying on us */
1361         assert_pipe_disabled(dev_priv, pipe);
1362
1363         reg = DPLL(pipe);
1364         val = I915_READ(reg);
1365         val &= ~DPLL_VCO_ENABLE;
1366         I915_WRITE(reg, val);
1367         POSTING_READ(reg);
1368 }
1369
1370 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1371 {
1372         u32 port_mask;
1373
1374         if (!port)
1375                 port_mask = DPLL_PORTB_READY_MASK;
1376         else
1377                 port_mask = DPLL_PORTC_READY_MASK;
1378
1379         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1380                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1381                      'B' + port, I915_READ(DPLL(0)));
1382 }
1383
1384 /**
1385  * ironlake_enable_pch_pll - enable PCH PLL
1386  * @dev_priv: i915 private structure
1387  * @pipe: pipe PLL to enable
1388  *
1389  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1390  * drives the transcoder clock.
1391  */
1392 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1393 {
1394         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1395         struct intel_pch_pll *pll;
1396         int reg;
1397         u32 val;
1398
1399         /* PCH PLLs only available on ILK, SNB and IVB */
1400         BUG_ON(dev_priv->info->gen < 5);
1401         pll = intel_crtc->pch_pll;
1402         if (pll == NULL)
1403                 return;
1404
1405         if (WARN_ON(pll->refcount == 0))
1406                 return;
1407
1408         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1409                       pll->pll_reg, pll->active, pll->on,
1410                       intel_crtc->base.base.id);
1411
1412         /* PCH refclock must be enabled first */
1413         assert_pch_refclk_enabled(dev_priv);
1414
1415         if (pll->active++ && pll->on) {
1416                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1417                 return;
1418         }
1419
1420         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1421
1422         reg = pll->pll_reg;
1423         val = I915_READ(reg);
1424         val |= DPLL_VCO_ENABLE;
1425         I915_WRITE(reg, val);
1426         POSTING_READ(reg);
1427         udelay(200);
1428
1429         pll->on = true;
1430 }
1431
1432 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1433 {
1434         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1435         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1436         int reg;
1437         u32 val;
1438
1439         /* PCH only available on ILK+ */
1440         BUG_ON(dev_priv->info->gen < 5);
1441         if (pll == NULL)
1442                return;
1443
1444         if (WARN_ON(pll->refcount == 0))
1445                 return;
1446
1447         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1448                       pll->pll_reg, pll->active, pll->on,
1449                       intel_crtc->base.base.id);
1450
1451         if (WARN_ON(pll->active == 0)) {
1452                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1453                 return;
1454         }
1455
1456         if (--pll->active) {
1457                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1458                 return;
1459         }
1460
1461         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1462
1463         /* Make sure transcoder isn't still depending on us */
1464         assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1465
1466         reg = pll->pll_reg;
1467         val = I915_READ(reg);
1468         val &= ~DPLL_VCO_ENABLE;
1469         I915_WRITE(reg, val);
1470         POSTING_READ(reg);
1471         udelay(200);
1472
1473         pll->on = false;
1474 }
1475
1476 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1477                                            enum pipe pipe)
1478 {
1479         struct drm_device *dev = dev_priv->dev;
1480         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1481         uint32_t reg, val, pipeconf_val;
1482
1483         /* PCH only available on ILK+ */
1484         BUG_ON(dev_priv->info->gen < 5);
1485
1486         /* Make sure PCH DPLL is enabled */
1487         assert_pch_pll_enabled(dev_priv,
1488                                to_intel_crtc(crtc)->pch_pll,
1489                                to_intel_crtc(crtc));
1490
1491         /* FDI must be feeding us bits for PCH ports */
1492         assert_fdi_tx_enabled(dev_priv, pipe);
1493         assert_fdi_rx_enabled(dev_priv, pipe);
1494
1495         if (HAS_PCH_CPT(dev)) {
1496                 /* Workaround: Set the timing override bit before enabling the
1497                  * pch transcoder. */
1498                 reg = TRANS_CHICKEN2(pipe);
1499                 val = I915_READ(reg);
1500                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1501                 I915_WRITE(reg, val);
1502         }
1503
1504         reg = PCH_TRANSCONF(pipe);
1505         val = I915_READ(reg);
1506         pipeconf_val = I915_READ(PIPECONF(pipe));
1507
1508         if (HAS_PCH_IBX(dev_priv->dev)) {
1509                 /*
1510                  * make the BPC in transcoder be consistent with
1511                  * that in pipeconf reg.
1512                  */
1513                 val &= ~PIPECONF_BPC_MASK;
1514                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1515         }
1516
1517         val &= ~TRANS_INTERLACE_MASK;
1518         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1519                 if (HAS_PCH_IBX(dev_priv->dev) &&
1520                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1521                         val |= TRANS_LEGACY_INTERLACED_ILK;
1522                 else
1523                         val |= TRANS_INTERLACED;
1524         else
1525                 val |= TRANS_PROGRESSIVE;
1526
1527         I915_WRITE(reg, val | TRANS_ENABLE);
1528         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1529                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1530 }
1531
1532 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1533                                       enum transcoder cpu_transcoder)
1534 {
1535         u32 val, pipeconf_val;
1536
1537         /* PCH only available on ILK+ */
1538         BUG_ON(dev_priv->info->gen < 5);
1539
1540         /* FDI must be feeding us bits for PCH ports */
1541         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1542         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1543
1544         /* Workaround: set timing override bit. */
1545         val = I915_READ(_TRANSA_CHICKEN2);
1546         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1547         I915_WRITE(_TRANSA_CHICKEN2, val);
1548
1549         val = TRANS_ENABLE;
1550         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1551
1552         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1553             PIPECONF_INTERLACED_ILK)
1554                 val |= TRANS_INTERLACED;
1555         else
1556                 val |= TRANS_PROGRESSIVE;
1557
1558         I915_WRITE(LPT_TRANSCONF, val);
1559         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1560                 DRM_ERROR("Failed to enable PCH transcoder\n");
1561 }
1562
1563 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1564                                             enum pipe pipe)
1565 {
1566         struct drm_device *dev = dev_priv->dev;
1567         uint32_t reg, val;
1568
1569         /* FDI relies on the transcoder */
1570         assert_fdi_tx_disabled(dev_priv, pipe);
1571         assert_fdi_rx_disabled(dev_priv, pipe);
1572
1573         /* Ports must be off as well */
1574         assert_pch_ports_disabled(dev_priv, pipe);
1575
1576         reg = PCH_TRANSCONF(pipe);
1577         val = I915_READ(reg);
1578         val &= ~TRANS_ENABLE;
1579         I915_WRITE(reg, val);
1580         /* wait for PCH transcoder off, transcoder state */
1581         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1582                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1583
1584         if (!HAS_PCH_IBX(dev)) {
1585                 /* Workaround: Clear the timing override chicken bit again. */
1586                 reg = TRANS_CHICKEN2(pipe);
1587                 val = I915_READ(reg);
1588                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1589                 I915_WRITE(reg, val);
1590         }
1591 }
1592
1593 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1594 {
1595         u32 val;
1596
1597         val = I915_READ(LPT_TRANSCONF);
1598         val &= ~TRANS_ENABLE;
1599         I915_WRITE(LPT_TRANSCONF, val);
1600         /* wait for PCH transcoder off, transcoder state */
1601         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1602                 DRM_ERROR("Failed to disable PCH transcoder\n");
1603
1604         /* Workaround: clear timing override bit. */
1605         val = I915_READ(_TRANSA_CHICKEN2);
1606         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1607         I915_WRITE(_TRANSA_CHICKEN2, val);
1608 }
1609
1610 /**
1611  * intel_enable_pipe - enable a pipe, asserting requirements
1612  * @dev_priv: i915 private structure
1613  * @pipe: pipe to enable
1614  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1615  *
1616  * Enable @pipe, making sure that various hardware specific requirements
1617  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1618  *
1619  * @pipe should be %PIPE_A or %PIPE_B.
1620  *
1621  * Will wait until the pipe is actually running (i.e. first vblank) before
1622  * returning.
1623  */
1624 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1625                               bool pch_port)
1626 {
1627         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1628                                                                       pipe);
1629         enum pipe pch_transcoder;
1630         int reg;
1631         u32 val;
1632
1633         assert_planes_disabled(dev_priv, pipe);
1634         assert_sprites_disabled(dev_priv, pipe);
1635
1636         if (HAS_PCH_LPT(dev_priv->dev))
1637                 pch_transcoder = TRANSCODER_A;
1638         else
1639                 pch_transcoder = pipe;
1640
1641         /*
1642          * A pipe without a PLL won't actually be able to drive bits from
1643          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1644          * need the check.
1645          */
1646         if (!HAS_PCH_SPLIT(dev_priv->dev))
1647                 assert_pll_enabled(dev_priv, pipe);
1648         else {
1649                 if (pch_port) {
1650                         /* if driving the PCH, we need FDI enabled */
1651                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1652                         assert_fdi_tx_pll_enabled(dev_priv,
1653                                                   (enum pipe) cpu_transcoder);
1654                 }
1655                 /* FIXME: assert CPU port conditions for SNB+ */
1656         }
1657
1658         reg = PIPECONF(cpu_transcoder);
1659         val = I915_READ(reg);
1660         if (val & PIPECONF_ENABLE)
1661                 return;
1662
1663         I915_WRITE(reg, val | PIPECONF_ENABLE);
1664         intel_wait_for_vblank(dev_priv->dev, pipe);
1665 }
1666
1667 /**
1668  * intel_disable_pipe - disable a pipe, asserting requirements
1669  * @dev_priv: i915 private structure
1670  * @pipe: pipe to disable
1671  *
1672  * Disable @pipe, making sure that various hardware specific requirements
1673  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1674  *
1675  * @pipe should be %PIPE_A or %PIPE_B.
1676  *
1677  * Will wait until the pipe has shut down before returning.
1678  */
1679 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1680                                enum pipe pipe)
1681 {
1682         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1683                                                                       pipe);
1684         int reg;
1685         u32 val;
1686
1687         /*
1688          * Make sure planes won't keep trying to pump pixels to us,
1689          * or we might hang the display.
1690          */
1691         assert_planes_disabled(dev_priv, pipe);
1692         assert_sprites_disabled(dev_priv, pipe);
1693
1694         /* Don't disable pipe A or pipe A PLLs if needed */
1695         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1696                 return;
1697
1698         reg = PIPECONF(cpu_transcoder);
1699         val = I915_READ(reg);
1700         if ((val & PIPECONF_ENABLE) == 0)
1701                 return;
1702
1703         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1704         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1705 }
1706
1707 /*
1708  * Plane regs are double buffered, going from enabled->disabled needs a
1709  * trigger in order to latch.  The display address reg provides this.
1710  */
1711 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1712                                       enum plane plane)
1713 {
1714         if (dev_priv->info->gen >= 4)
1715                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1716         else
1717                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1718 }
1719
1720 /**
1721  * intel_enable_plane - enable a display plane on a given pipe
1722  * @dev_priv: i915 private structure
1723  * @plane: plane to enable
1724  * @pipe: pipe being fed
1725  *
1726  * Enable @plane on @pipe, making sure that @pipe is running first.
1727  */
1728 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1729                                enum plane plane, enum pipe pipe)
1730 {
1731         int reg;
1732         u32 val;
1733
1734         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1735         assert_pipe_enabled(dev_priv, pipe);
1736
1737         reg = DSPCNTR(plane);
1738         val = I915_READ(reg);
1739         if (val & DISPLAY_PLANE_ENABLE)
1740                 return;
1741
1742         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1743         intel_flush_display_plane(dev_priv, plane);
1744         intel_wait_for_vblank(dev_priv->dev, pipe);
1745 }
1746
1747 /**
1748  * intel_disable_plane - disable a display plane
1749  * @dev_priv: i915 private structure
1750  * @plane: plane to disable
1751  * @pipe: pipe consuming the data
1752  *
1753  * Disable @plane; should be an independent operation.
1754  */
1755 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1756                                 enum plane plane, enum pipe pipe)
1757 {
1758         int reg;
1759         u32 val;
1760
1761         reg = DSPCNTR(plane);
1762         val = I915_READ(reg);
1763         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1764                 return;
1765
1766         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1767         intel_flush_display_plane(dev_priv, plane);
1768         intel_wait_for_vblank(dev_priv->dev, pipe);
1769 }
1770
1771 static bool need_vtd_wa(struct drm_device *dev)
1772 {
1773 #ifdef CONFIG_INTEL_IOMMU
1774         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1775                 return true;
1776 #endif
1777         return false;
1778 }
1779
1780 int
1781 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1782                            struct drm_i915_gem_object *obj,
1783                            struct intel_ring_buffer *pipelined)
1784 {
1785         struct drm_i915_private *dev_priv = dev->dev_private;
1786         u32 alignment;
1787         int ret;
1788
1789         switch (obj->tiling_mode) {
1790         case I915_TILING_NONE:
1791                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1792                         alignment = 128 * 1024;
1793                 else if (INTEL_INFO(dev)->gen >= 4)
1794                         alignment = 4 * 1024;
1795                 else
1796                         alignment = 64 * 1024;
1797                 break;
1798         case I915_TILING_X:
1799                 /* pin() will align the object as required by fence */
1800                 alignment = 0;
1801                 break;
1802         case I915_TILING_Y:
1803                 /* Despite that we check this in framebuffer_init userspace can
1804                  * screw us over and change the tiling after the fact. Only
1805                  * pinned buffers can't change their tiling. */
1806                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1807                 return -EINVAL;
1808         default:
1809                 BUG();
1810         }
1811
1812         /* Note that the w/a also requires 64 PTE of padding following the
1813          * bo. We currently fill all unused PTE with the shadow page and so
1814          * we should always have valid PTE following the scanout preventing
1815          * the VT-d warning.
1816          */
1817         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1818                 alignment = 256 * 1024;
1819
1820         dev_priv->mm.interruptible = false;
1821         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1822         if (ret)
1823                 goto err_interruptible;
1824
1825         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1826          * fence, whereas 965+ only requires a fence if using
1827          * framebuffer compression.  For simplicity, we always install
1828          * a fence as the cost is not that onerous.
1829          */
1830         ret = i915_gem_object_get_fence(obj);
1831         if (ret)
1832                 goto err_unpin;
1833
1834         i915_gem_object_pin_fence(obj);
1835
1836         dev_priv->mm.interruptible = true;
1837         return 0;
1838
1839 err_unpin:
1840         i915_gem_object_unpin(obj);
1841 err_interruptible:
1842         dev_priv->mm.interruptible = true;
1843         return ret;
1844 }
1845
1846 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1847 {
1848         i915_gem_object_unpin_fence(obj);
1849         i915_gem_object_unpin(obj);
1850 }
1851
1852 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1853  * is assumed to be a power-of-two. */
1854 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1855                                              unsigned int tiling_mode,
1856                                              unsigned int cpp,
1857                                              unsigned int pitch)
1858 {
1859         if (tiling_mode != I915_TILING_NONE) {
1860                 unsigned int tile_rows, tiles;
1861
1862                 tile_rows = *y / 8;
1863                 *y %= 8;
1864
1865                 tiles = *x / (512/cpp);
1866                 *x %= 512/cpp;
1867
1868                 return tile_rows * pitch * 8 + tiles * 4096;
1869         } else {
1870                 unsigned int offset;
1871
1872                 offset = *y * pitch + *x * cpp;
1873                 *y = 0;
1874                 *x = (offset & 4095) / cpp;
1875                 return offset & -4096;
1876         }
1877 }
1878
1879 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1880                              int x, int y)
1881 {
1882         struct drm_device *dev = crtc->dev;
1883         struct drm_i915_private *dev_priv = dev->dev_private;
1884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1885         struct intel_framebuffer *intel_fb;
1886         struct drm_i915_gem_object *obj;
1887         int plane = intel_crtc->plane;
1888         unsigned long linear_offset;
1889         u32 dspcntr;
1890         u32 reg;
1891
1892         switch (plane) {
1893         case 0:
1894         case 1:
1895                 break;
1896         default:
1897                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1898                 return -EINVAL;
1899         }
1900
1901         intel_fb = to_intel_framebuffer(fb);
1902         obj = intel_fb->obj;
1903
1904         reg = DSPCNTR(plane);
1905         dspcntr = I915_READ(reg);
1906         /* Mask out pixel format bits in case we change it */
1907         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1908         switch (fb->pixel_format) {
1909         case DRM_FORMAT_C8:
1910                 dspcntr |= DISPPLANE_8BPP;
1911                 break;
1912         case DRM_FORMAT_XRGB1555:
1913         case DRM_FORMAT_ARGB1555:
1914                 dspcntr |= DISPPLANE_BGRX555;
1915                 break;
1916         case DRM_FORMAT_RGB565:
1917                 dspcntr |= DISPPLANE_BGRX565;
1918                 break;
1919         case DRM_FORMAT_XRGB8888:
1920         case DRM_FORMAT_ARGB8888:
1921                 dspcntr |= DISPPLANE_BGRX888;
1922                 break;
1923         case DRM_FORMAT_XBGR8888:
1924         case DRM_FORMAT_ABGR8888:
1925                 dspcntr |= DISPPLANE_RGBX888;
1926                 break;
1927         case DRM_FORMAT_XRGB2101010:
1928         case DRM_FORMAT_ARGB2101010:
1929                 dspcntr |= DISPPLANE_BGRX101010;
1930                 break;
1931         case DRM_FORMAT_XBGR2101010:
1932         case DRM_FORMAT_ABGR2101010:
1933                 dspcntr |= DISPPLANE_RGBX101010;
1934                 break;
1935         default:
1936                 BUG();
1937         }
1938
1939         if (INTEL_INFO(dev)->gen >= 4) {
1940                 if (obj->tiling_mode != I915_TILING_NONE)
1941                         dspcntr |= DISPPLANE_TILED;
1942                 else
1943                         dspcntr &= ~DISPPLANE_TILED;
1944         }
1945
1946         I915_WRITE(reg, dspcntr);
1947
1948         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1949
1950         if (INTEL_INFO(dev)->gen >= 4) {
1951                 intel_crtc->dspaddr_offset =
1952                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1953                                                        fb->bits_per_pixel / 8,
1954                                                        fb->pitches[0]);
1955                 linear_offset -= intel_crtc->dspaddr_offset;
1956         } else {
1957                 intel_crtc->dspaddr_offset = linear_offset;
1958         }
1959
1960         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1961                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1962         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1963         if (INTEL_INFO(dev)->gen >= 4) {
1964                 I915_MODIFY_DISPBASE(DSPSURF(plane),
1965                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
1966                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1967                 I915_WRITE(DSPLINOFF(plane), linear_offset);
1968         } else
1969                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1970         POSTING_READ(reg);
1971
1972         return 0;
1973 }
1974
1975 static int ironlake_update_plane(struct drm_crtc *crtc,
1976                                  struct drm_framebuffer *fb, int x, int y)
1977 {
1978         struct drm_device *dev = crtc->dev;
1979         struct drm_i915_private *dev_priv = dev->dev_private;
1980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1981         struct intel_framebuffer *intel_fb;
1982         struct drm_i915_gem_object *obj;
1983         int plane = intel_crtc->plane;
1984         unsigned long linear_offset;
1985         u32 dspcntr;
1986         u32 reg;
1987
1988         switch (plane) {
1989         case 0:
1990         case 1:
1991         case 2:
1992                 break;
1993         default:
1994                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1995                 return -EINVAL;
1996         }
1997
1998         intel_fb = to_intel_framebuffer(fb);
1999         obj = intel_fb->obj;
2000
2001         reg = DSPCNTR(plane);
2002         dspcntr = I915_READ(reg);
2003         /* Mask out pixel format bits in case we change it */
2004         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2005         switch (fb->pixel_format) {
2006         case DRM_FORMAT_C8:
2007                 dspcntr |= DISPPLANE_8BPP;
2008                 break;
2009         case DRM_FORMAT_RGB565:
2010                 dspcntr |= DISPPLANE_BGRX565;
2011                 break;
2012         case DRM_FORMAT_XRGB8888:
2013         case DRM_FORMAT_ARGB8888:
2014                 dspcntr |= DISPPLANE_BGRX888;
2015                 break;
2016         case DRM_FORMAT_XBGR8888:
2017         case DRM_FORMAT_ABGR8888:
2018                 dspcntr |= DISPPLANE_RGBX888;
2019                 break;
2020         case DRM_FORMAT_XRGB2101010:
2021         case DRM_FORMAT_ARGB2101010:
2022                 dspcntr |= DISPPLANE_BGRX101010;
2023                 break;
2024         case DRM_FORMAT_XBGR2101010:
2025         case DRM_FORMAT_ABGR2101010:
2026                 dspcntr |= DISPPLANE_RGBX101010;
2027                 break;
2028         default:
2029                 BUG();
2030         }
2031
2032         if (obj->tiling_mode != I915_TILING_NONE)
2033                 dspcntr |= DISPPLANE_TILED;
2034         else
2035                 dspcntr &= ~DISPPLANE_TILED;
2036
2037         /* must disable */
2038         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2039
2040         I915_WRITE(reg, dspcntr);
2041
2042         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2043         intel_crtc->dspaddr_offset =
2044                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2045                                                fb->bits_per_pixel / 8,
2046                                                fb->pitches[0]);
2047         linear_offset -= intel_crtc->dspaddr_offset;
2048
2049         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2050                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2051         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2052         I915_MODIFY_DISPBASE(DSPSURF(plane),
2053                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2054         if (IS_HASWELL(dev)) {
2055                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2056         } else {
2057                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2058                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2059         }
2060         POSTING_READ(reg);
2061
2062         return 0;
2063 }
2064
2065 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2066 static int
2067 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2068                            int x, int y, enum mode_set_atomic state)
2069 {
2070         struct drm_device *dev = crtc->dev;
2071         struct drm_i915_private *dev_priv = dev->dev_private;
2072
2073         if (dev_priv->display.disable_fbc)
2074                 dev_priv->display.disable_fbc(dev);
2075         intel_increase_pllclock(crtc);
2076
2077         return dev_priv->display.update_plane(crtc, fb, x, y);
2078 }
2079
2080 void intel_display_handle_reset(struct drm_device *dev)
2081 {
2082         struct drm_i915_private *dev_priv = dev->dev_private;
2083         struct drm_crtc *crtc;
2084
2085         /*
2086          * Flips in the rings have been nuked by the reset,
2087          * so complete all pending flips so that user space
2088          * will get its events and not get stuck.
2089          *
2090          * Also update the base address of all primary
2091          * planes to the the last fb to make sure we're
2092          * showing the correct fb after a reset.
2093          *
2094          * Need to make two loops over the crtcs so that we
2095          * don't try to grab a crtc mutex before the
2096          * pending_flip_queue really got woken up.
2097          */
2098
2099         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2100                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2101                 enum plane plane = intel_crtc->plane;
2102
2103                 intel_prepare_page_flip(dev, plane);
2104                 intel_finish_page_flip_plane(dev, plane);
2105         }
2106
2107         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2108                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2109
2110                 mutex_lock(&crtc->mutex);
2111                 if (intel_crtc->active)
2112                         dev_priv->display.update_plane(crtc, crtc->fb,
2113                                                        crtc->x, crtc->y);
2114                 mutex_unlock(&crtc->mutex);
2115         }
2116 }
2117
2118 static int
2119 intel_finish_fb(struct drm_framebuffer *old_fb)
2120 {
2121         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2122         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2123         bool was_interruptible = dev_priv->mm.interruptible;
2124         int ret;
2125
2126         /* Big Hammer, we also need to ensure that any pending
2127          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2128          * current scanout is retired before unpinning the old
2129          * framebuffer.
2130          *
2131          * This should only fail upon a hung GPU, in which case we
2132          * can safely continue.
2133          */
2134         dev_priv->mm.interruptible = false;
2135         ret = i915_gem_object_finish_gpu(obj);
2136         dev_priv->mm.interruptible = was_interruptible;
2137
2138         return ret;
2139 }
2140
2141 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2142 {
2143         struct drm_device *dev = crtc->dev;
2144         struct drm_i915_master_private *master_priv;
2145         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2146
2147         if (!dev->primary->master)
2148                 return;
2149
2150         master_priv = dev->primary->master->driver_priv;
2151         if (!master_priv->sarea_priv)
2152                 return;
2153
2154         switch (intel_crtc->pipe) {
2155         case 0:
2156                 master_priv->sarea_priv->pipeA_x = x;
2157                 master_priv->sarea_priv->pipeA_y = y;
2158                 break;
2159         case 1:
2160                 master_priv->sarea_priv->pipeB_x = x;
2161                 master_priv->sarea_priv->pipeB_y = y;
2162                 break;
2163         default:
2164                 break;
2165         }
2166 }
2167
2168 static int
2169 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2170                     struct drm_framebuffer *fb)
2171 {
2172         struct drm_device *dev = crtc->dev;
2173         struct drm_i915_private *dev_priv = dev->dev_private;
2174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2175         struct drm_framebuffer *old_fb;
2176         int ret;
2177
2178         /* no fb bound */
2179         if (!fb) {
2180                 DRM_ERROR("No FB bound\n");
2181                 return 0;
2182         }
2183
2184         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2185                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2186                           plane_name(intel_crtc->plane),
2187                           INTEL_INFO(dev)->num_pipes);
2188                 return -EINVAL;
2189         }
2190
2191         mutex_lock(&dev->struct_mutex);
2192         ret = intel_pin_and_fence_fb_obj(dev,
2193                                          to_intel_framebuffer(fb)->obj,
2194                                          NULL);
2195         if (ret != 0) {
2196                 mutex_unlock(&dev->struct_mutex);
2197                 DRM_ERROR("pin & fence failed\n");
2198                 return ret;
2199         }
2200
2201         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2202         if (ret) {
2203                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2204                 mutex_unlock(&dev->struct_mutex);
2205                 DRM_ERROR("failed to update base address\n");
2206                 return ret;
2207         }
2208
2209         old_fb = crtc->fb;
2210         crtc->fb = fb;
2211         crtc->x = x;
2212         crtc->y = y;
2213
2214         if (old_fb) {
2215                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2216                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2217         }
2218
2219         intel_update_fbc(dev);
2220         mutex_unlock(&dev->struct_mutex);
2221
2222         intel_crtc_update_sarea_pos(crtc, x, y);
2223
2224         return 0;
2225 }
2226
2227 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2228 {
2229         struct drm_device *dev = crtc->dev;
2230         struct drm_i915_private *dev_priv = dev->dev_private;
2231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2232         int pipe = intel_crtc->pipe;
2233         u32 reg, temp;
2234
2235         /* enable normal train */
2236         reg = FDI_TX_CTL(pipe);
2237         temp = I915_READ(reg);
2238         if (IS_IVYBRIDGE(dev)) {
2239                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2240                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2241         } else {
2242                 temp &= ~FDI_LINK_TRAIN_NONE;
2243                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2244         }
2245         I915_WRITE(reg, temp);
2246
2247         reg = FDI_RX_CTL(pipe);
2248         temp = I915_READ(reg);
2249         if (HAS_PCH_CPT(dev)) {
2250                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2251                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2252         } else {
2253                 temp &= ~FDI_LINK_TRAIN_NONE;
2254                 temp |= FDI_LINK_TRAIN_NONE;
2255         }
2256         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2257
2258         /* wait one idle pattern time */
2259         POSTING_READ(reg);
2260         udelay(1000);
2261
2262         /* IVB wants error correction enabled */
2263         if (IS_IVYBRIDGE(dev))
2264                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2265                            FDI_FE_ERRC_ENABLE);
2266 }
2267
2268 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2269 {
2270         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2271 }
2272
2273 static void ivb_modeset_global_resources(struct drm_device *dev)
2274 {
2275         struct drm_i915_private *dev_priv = dev->dev_private;
2276         struct intel_crtc *pipe_B_crtc =
2277                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2278         struct intel_crtc *pipe_C_crtc =
2279                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2280         uint32_t temp;
2281
2282         /*
2283          * When everything is off disable fdi C so that we could enable fdi B
2284          * with all lanes. Note that we don't care about enabled pipes without
2285          * an enabled pch encoder.
2286          */
2287         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2288             !pipe_has_enabled_pch(pipe_C_crtc)) {
2289                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2290                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2291
2292                 temp = I915_READ(SOUTH_CHICKEN1);
2293                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2294                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2295                 I915_WRITE(SOUTH_CHICKEN1, temp);
2296         }
2297 }
2298
2299 /* The FDI link training functions for ILK/Ibexpeak. */
2300 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2301 {
2302         struct drm_device *dev = crtc->dev;
2303         struct drm_i915_private *dev_priv = dev->dev_private;
2304         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2305         int pipe = intel_crtc->pipe;
2306         int plane = intel_crtc->plane;
2307         u32 reg, temp, tries;
2308
2309         /* FDI needs bits from pipe & plane first */
2310         assert_pipe_enabled(dev_priv, pipe);
2311         assert_plane_enabled(dev_priv, plane);
2312
2313         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2314            for train result */
2315         reg = FDI_RX_IMR(pipe);
2316         temp = I915_READ(reg);
2317         temp &= ~FDI_RX_SYMBOL_LOCK;
2318         temp &= ~FDI_RX_BIT_LOCK;
2319         I915_WRITE(reg, temp);
2320         I915_READ(reg);
2321         udelay(150);
2322
2323         /* enable CPU FDI TX and PCH FDI RX */
2324         reg = FDI_TX_CTL(pipe);
2325         temp = I915_READ(reg);
2326         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2327         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2328         temp &= ~FDI_LINK_TRAIN_NONE;
2329         temp |= FDI_LINK_TRAIN_PATTERN_1;
2330         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2331
2332         reg = FDI_RX_CTL(pipe);
2333         temp = I915_READ(reg);
2334         temp &= ~FDI_LINK_TRAIN_NONE;
2335         temp |= FDI_LINK_TRAIN_PATTERN_1;
2336         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2337
2338         POSTING_READ(reg);
2339         udelay(150);
2340
2341         /* Ironlake workaround, enable clock pointer after FDI enable*/
2342         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2343         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2344                    FDI_RX_PHASE_SYNC_POINTER_EN);
2345
2346         reg = FDI_RX_IIR(pipe);
2347         for (tries = 0; tries < 5; tries++) {
2348                 temp = I915_READ(reg);
2349                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2350
2351                 if ((temp & FDI_RX_BIT_LOCK)) {
2352                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2353                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2354                         break;
2355                 }
2356         }
2357         if (tries == 5)
2358                 DRM_ERROR("FDI train 1 fail!\n");
2359
2360         /* Train 2 */
2361         reg = FDI_TX_CTL(pipe);
2362         temp = I915_READ(reg);
2363         temp &= ~FDI_LINK_TRAIN_NONE;
2364         temp |= FDI_LINK_TRAIN_PATTERN_2;
2365         I915_WRITE(reg, temp);
2366
2367         reg = FDI_RX_CTL(pipe);
2368         temp = I915_READ(reg);
2369         temp &= ~FDI_LINK_TRAIN_NONE;
2370         temp |= FDI_LINK_TRAIN_PATTERN_2;
2371         I915_WRITE(reg, temp);
2372
2373         POSTING_READ(reg);
2374         udelay(150);
2375
2376         reg = FDI_RX_IIR(pipe);
2377         for (tries = 0; tries < 5; tries++) {
2378                 temp = I915_READ(reg);
2379                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2380
2381                 if (temp & FDI_RX_SYMBOL_LOCK) {
2382                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2383                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2384                         break;
2385                 }
2386         }
2387         if (tries == 5)
2388                 DRM_ERROR("FDI train 2 fail!\n");
2389
2390         DRM_DEBUG_KMS("FDI train done\n");
2391
2392 }
2393
2394 static const int snb_b_fdi_train_param[] = {
2395         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2396         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2397         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2398         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2399 };
2400
2401 /* The FDI link training functions for SNB/Cougarpoint. */
2402 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2403 {
2404         struct drm_device *dev = crtc->dev;
2405         struct drm_i915_private *dev_priv = dev->dev_private;
2406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2407         int pipe = intel_crtc->pipe;
2408         u32 reg, temp, i, retry;
2409
2410         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2411            for train result */
2412         reg = FDI_RX_IMR(pipe);
2413         temp = I915_READ(reg);
2414         temp &= ~FDI_RX_SYMBOL_LOCK;
2415         temp &= ~FDI_RX_BIT_LOCK;
2416         I915_WRITE(reg, temp);
2417
2418         POSTING_READ(reg);
2419         udelay(150);
2420
2421         /* enable CPU FDI TX and PCH FDI RX */
2422         reg = FDI_TX_CTL(pipe);
2423         temp = I915_READ(reg);
2424         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2425         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2426         temp &= ~FDI_LINK_TRAIN_NONE;
2427         temp |= FDI_LINK_TRAIN_PATTERN_1;
2428         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2429         /* SNB-B */
2430         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2431         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2432
2433         I915_WRITE(FDI_RX_MISC(pipe),
2434                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2435
2436         reg = FDI_RX_CTL(pipe);
2437         temp = I915_READ(reg);
2438         if (HAS_PCH_CPT(dev)) {
2439                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2440                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2441         } else {
2442                 temp &= ~FDI_LINK_TRAIN_NONE;
2443                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2444         }
2445         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2446
2447         POSTING_READ(reg);
2448         udelay(150);
2449
2450         for (i = 0; i < 4; i++) {
2451                 reg = FDI_TX_CTL(pipe);
2452                 temp = I915_READ(reg);
2453                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2454                 temp |= snb_b_fdi_train_param[i];
2455                 I915_WRITE(reg, temp);
2456
2457                 POSTING_READ(reg);
2458                 udelay(500);
2459
2460                 for (retry = 0; retry < 5; retry++) {
2461                         reg = FDI_RX_IIR(pipe);
2462                         temp = I915_READ(reg);
2463                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2464                         if (temp & FDI_RX_BIT_LOCK) {
2465                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2466                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2467                                 break;
2468                         }
2469                         udelay(50);
2470                 }
2471                 if (retry < 5)
2472                         break;
2473         }
2474         if (i == 4)
2475                 DRM_ERROR("FDI train 1 fail!\n");
2476
2477         /* Train 2 */
2478         reg = FDI_TX_CTL(pipe);
2479         temp = I915_READ(reg);
2480         temp &= ~FDI_LINK_TRAIN_NONE;
2481         temp |= FDI_LINK_TRAIN_PATTERN_2;
2482         if (IS_GEN6(dev)) {
2483                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2484                 /* SNB-B */
2485                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2486         }
2487         I915_WRITE(reg, temp);
2488
2489         reg = FDI_RX_CTL(pipe);
2490         temp = I915_READ(reg);
2491         if (HAS_PCH_CPT(dev)) {
2492                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2493                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2494         } else {
2495                 temp &= ~FDI_LINK_TRAIN_NONE;
2496                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2497         }
2498         I915_WRITE(reg, temp);
2499
2500         POSTING_READ(reg);
2501         udelay(150);
2502
2503         for (i = 0; i < 4; i++) {
2504                 reg = FDI_TX_CTL(pipe);
2505                 temp = I915_READ(reg);
2506                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2507                 temp |= snb_b_fdi_train_param[i];
2508                 I915_WRITE(reg, temp);
2509
2510                 POSTING_READ(reg);
2511                 udelay(500);
2512
2513                 for (retry = 0; retry < 5; retry++) {
2514                         reg = FDI_RX_IIR(pipe);
2515                         temp = I915_READ(reg);
2516                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2517                         if (temp & FDI_RX_SYMBOL_LOCK) {
2518                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2519                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2520                                 break;
2521                         }
2522                         udelay(50);
2523                 }
2524                 if (retry < 5)
2525                         break;
2526         }
2527         if (i == 4)
2528                 DRM_ERROR("FDI train 2 fail!\n");
2529
2530         DRM_DEBUG_KMS("FDI train done.\n");
2531 }
2532
2533 /* Manual link training for Ivy Bridge A0 parts */
2534 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2535 {
2536         struct drm_device *dev = crtc->dev;
2537         struct drm_i915_private *dev_priv = dev->dev_private;
2538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2539         int pipe = intel_crtc->pipe;
2540         u32 reg, temp, i;
2541
2542         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2543            for train result */
2544         reg = FDI_RX_IMR(pipe);
2545         temp = I915_READ(reg);
2546         temp &= ~FDI_RX_SYMBOL_LOCK;
2547         temp &= ~FDI_RX_BIT_LOCK;
2548         I915_WRITE(reg, temp);
2549
2550         POSTING_READ(reg);
2551         udelay(150);
2552
2553         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2554                       I915_READ(FDI_RX_IIR(pipe)));
2555
2556         /* enable CPU FDI TX and PCH FDI RX */
2557         reg = FDI_TX_CTL(pipe);
2558         temp = I915_READ(reg);
2559         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2560         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2561         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2562         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2563         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2564         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2565         temp |= FDI_COMPOSITE_SYNC;
2566         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2567
2568         I915_WRITE(FDI_RX_MISC(pipe),
2569                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2570
2571         reg = FDI_RX_CTL(pipe);
2572         temp = I915_READ(reg);
2573         temp &= ~FDI_LINK_TRAIN_AUTO;
2574         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2575         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2576         temp |= FDI_COMPOSITE_SYNC;
2577         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2578
2579         POSTING_READ(reg);
2580         udelay(150);
2581
2582         for (i = 0; i < 4; i++) {
2583                 reg = FDI_TX_CTL(pipe);
2584                 temp = I915_READ(reg);
2585                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586                 temp |= snb_b_fdi_train_param[i];
2587                 I915_WRITE(reg, temp);
2588
2589                 POSTING_READ(reg);
2590                 udelay(500);
2591
2592                 reg = FDI_RX_IIR(pipe);
2593                 temp = I915_READ(reg);
2594                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2595
2596                 if (temp & FDI_RX_BIT_LOCK ||
2597                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2598                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2599                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2600                         break;
2601                 }
2602         }
2603         if (i == 4)
2604                 DRM_ERROR("FDI train 1 fail!\n");
2605
2606         /* Train 2 */
2607         reg = FDI_TX_CTL(pipe);
2608         temp = I915_READ(reg);
2609         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2610         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2611         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2612         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2613         I915_WRITE(reg, temp);
2614
2615         reg = FDI_RX_CTL(pipe);
2616         temp = I915_READ(reg);
2617         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2618         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2619         I915_WRITE(reg, temp);
2620
2621         POSTING_READ(reg);
2622         udelay(150);
2623
2624         for (i = 0; i < 4; i++) {
2625                 reg = FDI_TX_CTL(pipe);
2626                 temp = I915_READ(reg);
2627                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2628                 temp |= snb_b_fdi_train_param[i];
2629                 I915_WRITE(reg, temp);
2630
2631                 POSTING_READ(reg);
2632                 udelay(500);
2633
2634                 reg = FDI_RX_IIR(pipe);
2635                 temp = I915_READ(reg);
2636                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2637
2638                 if (temp & FDI_RX_SYMBOL_LOCK) {
2639                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2640                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2641                         break;
2642                 }
2643         }
2644         if (i == 4)
2645                 DRM_ERROR("FDI train 2 fail!\n");
2646
2647         DRM_DEBUG_KMS("FDI train done.\n");
2648 }
2649
2650 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2651 {
2652         struct drm_device *dev = intel_crtc->base.dev;
2653         struct drm_i915_private *dev_priv = dev->dev_private;
2654         int pipe = intel_crtc->pipe;
2655         u32 reg, temp;
2656
2657
2658         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2659         reg = FDI_RX_CTL(pipe);
2660         temp = I915_READ(reg);
2661         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2662         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2663         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2664         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2665
2666         POSTING_READ(reg);
2667         udelay(200);
2668
2669         /* Switch from Rawclk to PCDclk */
2670         temp = I915_READ(reg);
2671         I915_WRITE(reg, temp | FDI_PCDCLK);
2672
2673         POSTING_READ(reg);
2674         udelay(200);
2675
2676         /* Enable CPU FDI TX PLL, always on for Ironlake */
2677         reg = FDI_TX_CTL(pipe);
2678         temp = I915_READ(reg);
2679         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2680                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2681
2682                 POSTING_READ(reg);
2683                 udelay(100);
2684         }
2685 }
2686
2687 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2688 {
2689         struct drm_device *dev = intel_crtc->base.dev;
2690         struct drm_i915_private *dev_priv = dev->dev_private;
2691         int pipe = intel_crtc->pipe;
2692         u32 reg, temp;
2693
2694         /* Switch from PCDclk to Rawclk */
2695         reg = FDI_RX_CTL(pipe);
2696         temp = I915_READ(reg);
2697         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2698
2699         /* Disable CPU FDI TX PLL */
2700         reg = FDI_TX_CTL(pipe);
2701         temp = I915_READ(reg);
2702         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2703
2704         POSTING_READ(reg);
2705         udelay(100);
2706
2707         reg = FDI_RX_CTL(pipe);
2708         temp = I915_READ(reg);
2709         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2710
2711         /* Wait for the clocks to turn off. */
2712         POSTING_READ(reg);
2713         udelay(100);
2714 }
2715
2716 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2717 {
2718         struct drm_device *dev = crtc->dev;
2719         struct drm_i915_private *dev_priv = dev->dev_private;
2720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2721         int pipe = intel_crtc->pipe;
2722         u32 reg, temp;
2723
2724         /* disable CPU FDI tx and PCH FDI rx */
2725         reg = FDI_TX_CTL(pipe);
2726         temp = I915_READ(reg);
2727         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2728         POSTING_READ(reg);
2729
2730         reg = FDI_RX_CTL(pipe);
2731         temp = I915_READ(reg);
2732         temp &= ~(0x7 << 16);
2733         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2734         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2735
2736         POSTING_READ(reg);
2737         udelay(100);
2738
2739         /* Ironlake workaround, disable clock pointer after downing FDI */
2740         if (HAS_PCH_IBX(dev)) {
2741                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2742         }
2743
2744         /* still set train pattern 1 */
2745         reg = FDI_TX_CTL(pipe);
2746         temp = I915_READ(reg);
2747         temp &= ~FDI_LINK_TRAIN_NONE;
2748         temp |= FDI_LINK_TRAIN_PATTERN_1;
2749         I915_WRITE(reg, temp);
2750
2751         reg = FDI_RX_CTL(pipe);
2752         temp = I915_READ(reg);
2753         if (HAS_PCH_CPT(dev)) {
2754                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2755                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2756         } else {
2757                 temp &= ~FDI_LINK_TRAIN_NONE;
2758                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2759         }
2760         /* BPC in FDI rx is consistent with that in PIPECONF */
2761         temp &= ~(0x07 << 16);
2762         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2763         I915_WRITE(reg, temp);
2764
2765         POSTING_READ(reg);
2766         udelay(100);
2767 }
2768
2769 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2770 {
2771         struct drm_device *dev = crtc->dev;
2772         struct drm_i915_private *dev_priv = dev->dev_private;
2773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2774         unsigned long flags;
2775         bool pending;
2776
2777         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2778             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2779                 return false;
2780
2781         spin_lock_irqsave(&dev->event_lock, flags);
2782         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2783         spin_unlock_irqrestore(&dev->event_lock, flags);
2784
2785         return pending;
2786 }
2787
2788 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2789 {
2790         struct drm_device *dev = crtc->dev;
2791         struct drm_i915_private *dev_priv = dev->dev_private;
2792
2793         if (crtc->fb == NULL)
2794                 return;
2795
2796         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2797
2798         wait_event(dev_priv->pending_flip_queue,
2799                    !intel_crtc_has_pending_flip(crtc));
2800
2801         mutex_lock(&dev->struct_mutex);
2802         intel_finish_fb(crtc->fb);
2803         mutex_unlock(&dev->struct_mutex);
2804 }
2805
2806 /* Program iCLKIP clock to the desired frequency */
2807 static void lpt_program_iclkip(struct drm_crtc *crtc)
2808 {
2809         struct drm_device *dev = crtc->dev;
2810         struct drm_i915_private *dev_priv = dev->dev_private;
2811         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2812         u32 temp;
2813
2814         mutex_lock(&dev_priv->dpio_lock);
2815
2816         /* It is necessary to ungate the pixclk gate prior to programming
2817          * the divisors, and gate it back when it is done.
2818          */
2819         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2820
2821         /* Disable SSCCTL */
2822         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2823                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2824                                 SBI_SSCCTL_DISABLE,
2825                         SBI_ICLK);
2826
2827         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2828         if (crtc->mode.clock == 20000) {
2829                 auxdiv = 1;
2830                 divsel = 0x41;
2831                 phaseinc = 0x20;
2832         } else {
2833                 /* The iCLK virtual clock root frequency is in MHz,
2834                  * but the crtc->mode.clock in in KHz. To get the divisors,
2835                  * it is necessary to divide one by another, so we
2836                  * convert the virtual clock precision to KHz here for higher
2837                  * precision.
2838                  */
2839                 u32 iclk_virtual_root_freq = 172800 * 1000;
2840                 u32 iclk_pi_range = 64;
2841                 u32 desired_divisor, msb_divisor_value, pi_value;
2842
2843                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2844                 msb_divisor_value = desired_divisor / iclk_pi_range;
2845                 pi_value = desired_divisor % iclk_pi_range;
2846
2847                 auxdiv = 0;
2848                 divsel = msb_divisor_value - 2;
2849                 phaseinc = pi_value;
2850         }
2851
2852         /* This should not happen with any sane values */
2853         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2854                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2855         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2856                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2857
2858         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2859                         crtc->mode.clock,
2860                         auxdiv,
2861                         divsel,
2862                         phasedir,
2863                         phaseinc);
2864
2865         /* Program SSCDIVINTPHASE6 */
2866         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2867         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2868         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2869         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2870         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2871         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2872         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2873         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2874
2875         /* Program SSCAUXDIV */
2876         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2877         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2878         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2879         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2880
2881         /* Enable modulator and associated divider */
2882         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2883         temp &= ~SBI_SSCCTL_DISABLE;
2884         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2885
2886         /* Wait for initialization time */
2887         udelay(24);
2888
2889         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2890
2891         mutex_unlock(&dev_priv->dpio_lock);
2892 }
2893
2894 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2895                                                 enum pipe pch_transcoder)
2896 {
2897         struct drm_device *dev = crtc->base.dev;
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2900
2901         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2902                    I915_READ(HTOTAL(cpu_transcoder)));
2903         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2904                    I915_READ(HBLANK(cpu_transcoder)));
2905         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2906                    I915_READ(HSYNC(cpu_transcoder)));
2907
2908         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2909                    I915_READ(VTOTAL(cpu_transcoder)));
2910         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2911                    I915_READ(VBLANK(cpu_transcoder)));
2912         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2913                    I915_READ(VSYNC(cpu_transcoder)));
2914         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2915                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2916 }
2917
2918 /*
2919  * Enable PCH resources required for PCH ports:
2920  *   - PCH PLLs
2921  *   - FDI training & RX/TX
2922  *   - update transcoder timings
2923  *   - DP transcoding bits
2924  *   - transcoder
2925  */
2926 static void ironlake_pch_enable(struct drm_crtc *crtc)
2927 {
2928         struct drm_device *dev = crtc->dev;
2929         struct drm_i915_private *dev_priv = dev->dev_private;
2930         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2931         int pipe = intel_crtc->pipe;
2932         u32 reg, temp;
2933
2934         assert_pch_transcoder_disabled(dev_priv, pipe);
2935
2936         /* Write the TU size bits before fdi link training, so that error
2937          * detection works. */
2938         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2939                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2940
2941         /* For PCH output, training FDI link */
2942         dev_priv->display.fdi_link_train(crtc);
2943
2944         /* XXX: pch pll's can be enabled any time before we enable the PCH
2945          * transcoder, and we actually should do this to not upset any PCH
2946          * transcoder that already use the clock when we share it.
2947          *
2948          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2949          * unconditionally resets the pll - we need that to have the right LVDS
2950          * enable sequence. */
2951         ironlake_enable_pch_pll(intel_crtc);
2952
2953         if (HAS_PCH_CPT(dev)) {
2954                 u32 sel;
2955
2956                 temp = I915_READ(PCH_DPLL_SEL);
2957                 switch (pipe) {
2958                 default:
2959                 case 0:
2960                         temp |= TRANSA_DPLL_ENABLE;
2961                         sel = TRANSA_DPLLB_SEL;
2962                         break;
2963                 case 1:
2964                         temp |= TRANSB_DPLL_ENABLE;
2965                         sel = TRANSB_DPLLB_SEL;
2966                         break;
2967                 case 2:
2968                         temp |= TRANSC_DPLL_ENABLE;
2969                         sel = TRANSC_DPLLB_SEL;
2970                         break;
2971                 }
2972                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2973                         temp |= sel;
2974                 else
2975                         temp &= ~sel;
2976                 I915_WRITE(PCH_DPLL_SEL, temp);
2977         }
2978
2979         /* set transcoder timing, panel must allow it */
2980         assert_panel_unlocked(dev_priv, pipe);
2981         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2982
2983         intel_fdi_normal_train(crtc);
2984
2985         /* For PCH DP, enable TRANS_DP_CTL */
2986         if (HAS_PCH_CPT(dev) &&
2987             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2988              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2989                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2990                 reg = TRANS_DP_CTL(pipe);
2991                 temp = I915_READ(reg);
2992                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2993                           TRANS_DP_SYNC_MASK |
2994                           TRANS_DP_BPC_MASK);
2995                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2996                          TRANS_DP_ENH_FRAMING);
2997                 temp |= bpc << 9; /* same format but at 11:9 */
2998
2999                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3000                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3001                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3002                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3003
3004                 switch (intel_trans_dp_port_sel(crtc)) {
3005                 case PCH_DP_B:
3006                         temp |= TRANS_DP_PORT_SEL_B;
3007                         break;
3008                 case PCH_DP_C:
3009                         temp |= TRANS_DP_PORT_SEL_C;
3010                         break;
3011                 case PCH_DP_D:
3012                         temp |= TRANS_DP_PORT_SEL_D;
3013                         break;
3014                 default:
3015                         BUG();
3016                 }
3017
3018                 I915_WRITE(reg, temp);
3019         }
3020
3021         ironlake_enable_pch_transcoder(dev_priv, pipe);
3022 }
3023
3024 static void lpt_pch_enable(struct drm_crtc *crtc)
3025 {
3026         struct drm_device *dev = crtc->dev;
3027         struct drm_i915_private *dev_priv = dev->dev_private;
3028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3030
3031         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3032
3033         lpt_program_iclkip(crtc);
3034
3035         /* Set transcoder timing. */
3036         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3037
3038         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3039 }
3040
3041 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3042 {
3043         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3044
3045         if (pll == NULL)
3046                 return;
3047
3048         if (pll->refcount == 0) {
3049                 WARN(1, "bad PCH PLL refcount\n");
3050                 return;
3051         }
3052
3053         --pll->refcount;
3054         intel_crtc->pch_pll = NULL;
3055 }
3056
3057 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3058 {
3059         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3060         struct intel_pch_pll *pll;
3061         int i;
3062
3063         pll = intel_crtc->pch_pll;
3064         if (pll) {
3065                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3066                               intel_crtc->base.base.id, pll->pll_reg);
3067                 goto prepare;
3068         }
3069
3070         if (HAS_PCH_IBX(dev_priv->dev)) {
3071                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3072                 i = intel_crtc->pipe;
3073                 pll = &dev_priv->pch_plls[i];
3074
3075                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3076                               intel_crtc->base.base.id, pll->pll_reg);
3077
3078                 goto found;
3079         }
3080
3081         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3082                 pll = &dev_priv->pch_plls[i];
3083
3084                 /* Only want to check enabled timings first */
3085                 if (pll->refcount == 0)
3086                         continue;
3087
3088                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3089                     fp == I915_READ(pll->fp0_reg)) {
3090                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3091                                       intel_crtc->base.base.id,
3092                                       pll->pll_reg, pll->refcount, pll->active);
3093
3094                         goto found;
3095                 }
3096         }
3097
3098         /* Ok no matching timings, maybe there's a free one? */
3099         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3100                 pll = &dev_priv->pch_plls[i];
3101                 if (pll->refcount == 0) {
3102                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3103                                       intel_crtc->base.base.id, pll->pll_reg);
3104                         goto found;
3105                 }
3106         }
3107
3108         return NULL;
3109
3110 found:
3111         intel_crtc->pch_pll = pll;
3112         pll->refcount++;
3113         DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3114 prepare: /* separate function? */
3115         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3116
3117         /* Wait for the clocks to stabilize before rewriting the regs */
3118         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3119         POSTING_READ(pll->pll_reg);
3120         udelay(150);
3121
3122         I915_WRITE(pll->fp0_reg, fp);
3123         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3124         pll->on = false;
3125         return pll;
3126 }
3127
3128 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3129 {
3130         struct drm_i915_private *dev_priv = dev->dev_private;
3131         int dslreg = PIPEDSL(pipe);
3132         u32 temp;
3133
3134         temp = I915_READ(dslreg);
3135         udelay(500);
3136         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3137                 if (wait_for(I915_READ(dslreg) != temp, 5))
3138                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3139         }
3140 }
3141
3142 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3143 {
3144         struct drm_device *dev = crtc->base.dev;
3145         struct drm_i915_private *dev_priv = dev->dev_private;
3146         int pipe = crtc->pipe;
3147
3148         if (crtc->config.pch_pfit.size) {
3149                 /* Force use of hard-coded filter coefficients
3150                  * as some pre-programmed values are broken,
3151                  * e.g. x201.
3152                  */
3153                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3154                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3155                                                  PF_PIPE_SEL_IVB(pipe));
3156                 else
3157                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3158                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3159                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3160         }
3161 }
3162
3163 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3164 {
3165         struct drm_device *dev = crtc->dev;
3166         struct drm_i915_private *dev_priv = dev->dev_private;
3167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168         struct intel_encoder *encoder;
3169         int pipe = intel_crtc->pipe;
3170         int plane = intel_crtc->plane;
3171         u32 temp;
3172
3173         WARN_ON(!crtc->enabled);
3174
3175         if (intel_crtc->active)
3176                 return;
3177
3178         intel_crtc->active = true;
3179
3180         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3181         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3182
3183         intel_update_watermarks(dev);
3184
3185         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3186                 temp = I915_READ(PCH_LVDS);
3187                 if ((temp & LVDS_PORT_EN) == 0)
3188                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3189         }
3190
3191
3192         if (intel_crtc->config.has_pch_encoder) {
3193                 /* Note: FDI PLL enabling _must_ be done before we enable the
3194                  * cpu pipes, hence this is separate from all the other fdi/pch
3195                  * enabling. */
3196                 ironlake_fdi_pll_enable(intel_crtc);
3197         } else {
3198                 assert_fdi_tx_disabled(dev_priv, pipe);
3199                 assert_fdi_rx_disabled(dev_priv, pipe);
3200         }
3201
3202         for_each_encoder_on_crtc(dev, crtc, encoder)
3203                 if (encoder->pre_enable)
3204                         encoder->pre_enable(encoder);
3205
3206         /* Enable panel fitting for LVDS */
3207         ironlake_pfit_enable(intel_crtc);
3208
3209         /*
3210          * On ILK+ LUT must be loaded before the pipe is running but with
3211          * clocks enabled
3212          */
3213         intel_crtc_load_lut(crtc);
3214
3215         intel_enable_pipe(dev_priv, pipe,
3216                           intel_crtc->config.has_pch_encoder);
3217         intel_enable_plane(dev_priv, plane, pipe);
3218
3219         if (intel_crtc->config.has_pch_encoder)
3220                 ironlake_pch_enable(crtc);
3221
3222         mutex_lock(&dev->struct_mutex);
3223         intel_update_fbc(dev);
3224         mutex_unlock(&dev->struct_mutex);
3225
3226         intel_crtc_update_cursor(crtc, true);
3227
3228         for_each_encoder_on_crtc(dev, crtc, encoder)
3229                 encoder->enable(encoder);
3230
3231         if (HAS_PCH_CPT(dev))
3232                 cpt_verify_modeset(dev, intel_crtc->pipe);
3233
3234         /*
3235          * There seems to be a race in PCH platform hw (at least on some
3236          * outputs) where an enabled pipe still completes any pageflip right
3237          * away (as if the pipe is off) instead of waiting for vblank. As soon
3238          * as the first vblank happend, everything works as expected. Hence just
3239          * wait for one vblank before returning to avoid strange things
3240          * happening.
3241          */
3242         intel_wait_for_vblank(dev, intel_crtc->pipe);
3243 }
3244
3245 /* IPS only exists on ULT machines and is tied to pipe A. */
3246 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3247 {
3248         return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3249 }
3250
3251 static void hsw_enable_ips(struct intel_crtc *crtc)
3252 {
3253         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3254
3255         if (!crtc->config.ips_enabled)
3256                 return;
3257
3258         /* We can only enable IPS after we enable a plane and wait for a vblank.
3259          * We guarantee that the plane is enabled by calling intel_enable_ips
3260          * only after intel_enable_plane. And intel_enable_plane already waits
3261          * for a vblank, so all we need to do here is to enable the IPS bit. */
3262         assert_plane_enabled(dev_priv, crtc->plane);
3263         I915_WRITE(IPS_CTL, IPS_ENABLE);
3264 }
3265
3266 static void hsw_disable_ips(struct intel_crtc *crtc)
3267 {
3268         struct drm_device *dev = crtc->base.dev;
3269         struct drm_i915_private *dev_priv = dev->dev_private;
3270
3271         if (!crtc->config.ips_enabled)
3272                 return;
3273
3274         assert_plane_enabled(dev_priv, crtc->plane);
3275         I915_WRITE(IPS_CTL, 0);
3276
3277         /* We need to wait for a vblank before we can disable the plane. */
3278         intel_wait_for_vblank(dev, crtc->pipe);
3279 }
3280
3281 static void haswell_crtc_enable(struct drm_crtc *crtc)
3282 {
3283         struct drm_device *dev = crtc->dev;
3284         struct drm_i915_private *dev_priv = dev->dev_private;
3285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3286         struct intel_encoder *encoder;
3287         int pipe = intel_crtc->pipe;
3288         int plane = intel_crtc->plane;
3289
3290         WARN_ON(!crtc->enabled);
3291
3292         if (intel_crtc->active)
3293                 return;
3294
3295         intel_crtc->active = true;
3296
3297         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3298         if (intel_crtc->config.has_pch_encoder)
3299                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3300
3301         intel_update_watermarks(dev);
3302
3303         if (intel_crtc->config.has_pch_encoder)
3304                 dev_priv->display.fdi_link_train(crtc);
3305
3306         for_each_encoder_on_crtc(dev, crtc, encoder)
3307                 if (encoder->pre_enable)
3308                         encoder->pre_enable(encoder);
3309
3310         intel_ddi_enable_pipe_clock(intel_crtc);
3311
3312         /* Enable panel fitting for eDP */
3313         ironlake_pfit_enable(intel_crtc);
3314
3315         /*
3316          * On ILK+ LUT must be loaded before the pipe is running but with
3317          * clocks enabled
3318          */
3319         intel_crtc_load_lut(crtc);
3320
3321         intel_ddi_set_pipe_settings(crtc);
3322         intel_ddi_enable_transcoder_func(crtc);
3323
3324         intel_enable_pipe(dev_priv, pipe,
3325                           intel_crtc->config.has_pch_encoder);
3326         intel_enable_plane(dev_priv, plane, pipe);
3327
3328         hsw_enable_ips(intel_crtc);
3329
3330         if (intel_crtc->config.has_pch_encoder)
3331                 lpt_pch_enable(crtc);
3332
3333         mutex_lock(&dev->struct_mutex);
3334         intel_update_fbc(dev);
3335         mutex_unlock(&dev->struct_mutex);
3336
3337         intel_crtc_update_cursor(crtc, true);
3338
3339         for_each_encoder_on_crtc(dev, crtc, encoder)
3340                 encoder->enable(encoder);
3341
3342         /*
3343          * There seems to be a race in PCH platform hw (at least on some
3344          * outputs) where an enabled pipe still completes any pageflip right
3345          * away (as if the pipe is off) instead of waiting for vblank. As soon
3346          * as the first vblank happend, everything works as expected. Hence just
3347          * wait for one vblank before returning to avoid strange things
3348          * happening.
3349          */
3350         intel_wait_for_vblank(dev, intel_crtc->pipe);
3351 }
3352
3353 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3354 {
3355         struct drm_device *dev = crtc->base.dev;
3356         struct drm_i915_private *dev_priv = dev->dev_private;
3357         int pipe = crtc->pipe;
3358
3359         /* To avoid upsetting the power well on haswell only disable the pfit if
3360          * it's in use. The hw state code will make sure we get this right. */
3361         if (crtc->config.pch_pfit.size) {
3362                 I915_WRITE(PF_CTL(pipe), 0);
3363                 I915_WRITE(PF_WIN_POS(pipe), 0);
3364                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3365         }
3366 }
3367
3368 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3369 {
3370         struct drm_device *dev = crtc->dev;
3371         struct drm_i915_private *dev_priv = dev->dev_private;
3372         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3373         struct intel_encoder *encoder;
3374         int pipe = intel_crtc->pipe;
3375         int plane = intel_crtc->plane;
3376         u32 reg, temp;
3377
3378
3379         if (!intel_crtc->active)
3380                 return;
3381
3382         for_each_encoder_on_crtc(dev, crtc, encoder)
3383                 encoder->disable(encoder);
3384
3385         intel_crtc_wait_for_pending_flips(crtc);
3386         drm_vblank_off(dev, pipe);
3387         intel_crtc_update_cursor(crtc, false);
3388
3389         intel_disable_plane(dev_priv, plane, pipe);
3390
3391         if (dev_priv->cfb_plane == plane)
3392                 intel_disable_fbc(dev);
3393
3394         intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3395         intel_disable_pipe(dev_priv, pipe);
3396
3397         ironlake_pfit_disable(intel_crtc);
3398
3399         for_each_encoder_on_crtc(dev, crtc, encoder)
3400                 if (encoder->post_disable)
3401                         encoder->post_disable(encoder);
3402
3403         ironlake_fdi_disable(crtc);
3404
3405         ironlake_disable_pch_transcoder(dev_priv, pipe);
3406         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3407
3408         if (HAS_PCH_CPT(dev)) {
3409                 /* disable TRANS_DP_CTL */
3410                 reg = TRANS_DP_CTL(pipe);
3411                 temp = I915_READ(reg);
3412                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3413                 temp |= TRANS_DP_PORT_SEL_NONE;
3414                 I915_WRITE(reg, temp);
3415
3416                 /* disable DPLL_SEL */
3417                 temp = I915_READ(PCH_DPLL_SEL);
3418                 switch (pipe) {
3419                 case 0:
3420                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3421                         break;
3422                 case 1:
3423                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3424                         break;
3425                 case 2:
3426                         /* C shares PLL A or B */
3427                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3428                         break;
3429                 default:
3430                         BUG(); /* wtf */
3431                 }
3432                 I915_WRITE(PCH_DPLL_SEL, temp);
3433         }
3434
3435         /* disable PCH DPLL */
3436         intel_disable_pch_pll(intel_crtc);
3437
3438         ironlake_fdi_pll_disable(intel_crtc);
3439
3440         intel_crtc->active = false;
3441         intel_update_watermarks(dev);
3442
3443         mutex_lock(&dev->struct_mutex);
3444         intel_update_fbc(dev);
3445         mutex_unlock(&dev->struct_mutex);
3446 }
3447
3448 static void haswell_crtc_disable(struct drm_crtc *crtc)
3449 {
3450         struct drm_device *dev = crtc->dev;
3451         struct drm_i915_private *dev_priv = dev->dev_private;
3452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3453         struct intel_encoder *encoder;
3454         int pipe = intel_crtc->pipe;
3455         int plane = intel_crtc->plane;
3456         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3457
3458         if (!intel_crtc->active)
3459                 return;
3460
3461         for_each_encoder_on_crtc(dev, crtc, encoder)
3462                 encoder->disable(encoder);
3463
3464         intel_crtc_wait_for_pending_flips(crtc);
3465         drm_vblank_off(dev, pipe);
3466         intel_crtc_update_cursor(crtc, false);
3467
3468         /* FBC must be disabled before disabling the plane on HSW. */
3469         if (dev_priv->cfb_plane == plane)
3470                 intel_disable_fbc(dev);
3471
3472         hsw_disable_ips(intel_crtc);
3473
3474         intel_disable_plane(dev_priv, plane, pipe);
3475
3476         if (intel_crtc->config.has_pch_encoder)
3477                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3478         intel_disable_pipe(dev_priv, pipe);
3479
3480         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3481
3482         ironlake_pfit_disable(intel_crtc);
3483
3484         intel_ddi_disable_pipe_clock(intel_crtc);
3485
3486         for_each_encoder_on_crtc(dev, crtc, encoder)
3487                 if (encoder->post_disable)
3488                         encoder->post_disable(encoder);
3489
3490         if (intel_crtc->config.has_pch_encoder) {
3491                 lpt_disable_pch_transcoder(dev_priv);
3492                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3493                 intel_ddi_fdi_disable(crtc);
3494         }
3495
3496         intel_crtc->active = false;
3497         intel_update_watermarks(dev);
3498
3499         mutex_lock(&dev->struct_mutex);
3500         intel_update_fbc(dev);
3501         mutex_unlock(&dev->struct_mutex);
3502 }
3503
3504 static void ironlake_crtc_off(struct drm_crtc *crtc)
3505 {
3506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507         intel_put_pch_pll(intel_crtc);
3508 }
3509
3510 static void haswell_crtc_off(struct drm_crtc *crtc)
3511 {
3512         intel_ddi_put_crtc_pll(crtc);
3513 }
3514
3515 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3516 {
3517         if (!enable && intel_crtc->overlay) {
3518                 struct drm_device *dev = intel_crtc->base.dev;
3519                 struct drm_i915_private *dev_priv = dev->dev_private;
3520
3521                 mutex_lock(&dev->struct_mutex);
3522                 dev_priv->mm.interruptible = false;
3523                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3524                 dev_priv->mm.interruptible = true;
3525                 mutex_unlock(&dev->struct_mutex);
3526         }
3527
3528         /* Let userspace switch the overlay on again. In most cases userspace
3529          * has to recompute where to put it anyway.
3530          */
3531 }
3532
3533 /**
3534  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3535  * cursor plane briefly if not already running after enabling the display
3536  * plane.
3537  * This workaround avoids occasional blank screens when self refresh is
3538  * enabled.
3539  */
3540 static void
3541 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3542 {
3543         u32 cntl = I915_READ(CURCNTR(pipe));
3544
3545         if ((cntl & CURSOR_MODE) == 0) {
3546                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3547
3548                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3549                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3550                 intel_wait_for_vblank(dev_priv->dev, pipe);
3551                 I915_WRITE(CURCNTR(pipe), cntl);
3552                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3553                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3554         }
3555 }
3556
3557 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3558 {
3559         struct drm_device *dev = crtc->base.dev;
3560         struct drm_i915_private *dev_priv = dev->dev_private;
3561         struct intel_crtc_config *pipe_config = &crtc->config;
3562
3563         if (!crtc->config.gmch_pfit.control)
3564                 return;
3565
3566         /*
3567          * The panel fitter should only be adjusted whilst the pipe is disabled,
3568          * according to register description and PRM.
3569          */
3570         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3571         assert_pipe_disabled(dev_priv, crtc->pipe);
3572
3573         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3574         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3575
3576         /* Border color in case we don't scale up to the full screen. Black by
3577          * default, change to something else for debugging. */
3578         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3579 }
3580
3581 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3582 {
3583         struct drm_device *dev = crtc->dev;
3584         struct drm_i915_private *dev_priv = dev->dev_private;
3585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3586         struct intel_encoder *encoder;
3587         int pipe = intel_crtc->pipe;
3588         int plane = intel_crtc->plane;
3589
3590         WARN_ON(!crtc->enabled);
3591
3592         if (intel_crtc->active)
3593                 return;
3594
3595         intel_crtc->active = true;
3596         intel_update_watermarks(dev);
3597
3598         mutex_lock(&dev_priv->dpio_lock);
3599
3600         for_each_encoder_on_crtc(dev, crtc, encoder)
3601                 if (encoder->pre_pll_enable)
3602                         encoder->pre_pll_enable(encoder);
3603
3604         intel_enable_pll(dev_priv, pipe);
3605
3606         for_each_encoder_on_crtc(dev, crtc, encoder)
3607                 if (encoder->pre_enable)
3608                         encoder->pre_enable(encoder);
3609
3610         /* VLV wants encoder enabling _before_ the pipe is up. */
3611         for_each_encoder_on_crtc(dev, crtc, encoder)
3612                 encoder->enable(encoder);
3613
3614         /* Enable panel fitting for eDP */
3615         i9xx_pfit_enable(intel_crtc);
3616
3617         intel_enable_pipe(dev_priv, pipe, false);
3618         intel_enable_plane(dev_priv, plane, pipe);
3619
3620         intel_crtc_load_lut(crtc);
3621         intel_update_fbc(dev);
3622
3623         /* Give the overlay scaler a chance to enable if it's on this pipe */
3624         intel_crtc_dpms_overlay(intel_crtc, true);
3625         intel_crtc_update_cursor(crtc, true);
3626
3627         mutex_unlock(&dev_priv->dpio_lock);
3628 }
3629
3630 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3631 {
3632         struct drm_device *dev = crtc->dev;
3633         struct drm_i915_private *dev_priv = dev->dev_private;
3634         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3635         struct intel_encoder *encoder;
3636         int pipe = intel_crtc->pipe;
3637         int plane = intel_crtc->plane;
3638
3639         WARN_ON(!crtc->enabled);
3640
3641         if (intel_crtc->active)
3642                 return;
3643
3644         intel_crtc->active = true;
3645         intel_update_watermarks(dev);
3646
3647         intel_enable_pll(dev_priv, pipe);
3648
3649         for_each_encoder_on_crtc(dev, crtc, encoder)
3650                 if (encoder->pre_enable)
3651                         encoder->pre_enable(encoder);
3652
3653         /* Enable panel fitting for LVDS */
3654         i9xx_pfit_enable(intel_crtc);
3655
3656         intel_enable_pipe(dev_priv, pipe, false);
3657         intel_enable_plane(dev_priv, plane, pipe);
3658         if (IS_G4X(dev))
3659                 g4x_fixup_plane(dev_priv, pipe);
3660
3661         intel_crtc_load_lut(crtc);
3662         intel_update_fbc(dev);
3663
3664         /* Give the overlay scaler a chance to enable if it's on this pipe */
3665         intel_crtc_dpms_overlay(intel_crtc, true);
3666         intel_crtc_update_cursor(crtc, true);
3667
3668         for_each_encoder_on_crtc(dev, crtc, encoder)
3669                 encoder->enable(encoder);
3670 }
3671
3672 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3673 {
3674         struct drm_device *dev = crtc->base.dev;
3675         struct drm_i915_private *dev_priv = dev->dev_private;
3676
3677         if (!crtc->config.gmch_pfit.control)
3678                 return;
3679
3680         assert_pipe_disabled(dev_priv, crtc->pipe);
3681
3682         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3683                          I915_READ(PFIT_CONTROL));
3684         I915_WRITE(PFIT_CONTROL, 0);
3685 }
3686
3687 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3688 {
3689         struct drm_device *dev = crtc->dev;
3690         struct drm_i915_private *dev_priv = dev->dev_private;
3691         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3692         struct intel_encoder *encoder;
3693         int pipe = intel_crtc->pipe;
3694         int plane = intel_crtc->plane;
3695
3696         if (!intel_crtc->active)
3697                 return;
3698
3699         for_each_encoder_on_crtc(dev, crtc, encoder)
3700                 encoder->disable(encoder);
3701
3702         /* Give the overlay scaler a chance to disable if it's on this pipe */
3703         intel_crtc_wait_for_pending_flips(crtc);
3704         drm_vblank_off(dev, pipe);
3705         intel_crtc_dpms_overlay(intel_crtc, false);
3706         intel_crtc_update_cursor(crtc, false);
3707
3708         if (dev_priv->cfb_plane == plane)
3709                 intel_disable_fbc(dev);
3710
3711         intel_disable_plane(dev_priv, plane, pipe);
3712         intel_disable_pipe(dev_priv, pipe);
3713
3714         i9xx_pfit_disable(intel_crtc);
3715
3716         for_each_encoder_on_crtc(dev, crtc, encoder)
3717                 if (encoder->post_disable)
3718                         encoder->post_disable(encoder);
3719
3720         intel_disable_pll(dev_priv, pipe);
3721
3722         intel_crtc->active = false;
3723         intel_update_fbc(dev);
3724         intel_update_watermarks(dev);
3725 }
3726
3727 static void i9xx_crtc_off(struct drm_crtc *crtc)
3728 {
3729 }
3730
3731 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3732                                     bool enabled)
3733 {
3734         struct drm_device *dev = crtc->dev;
3735         struct drm_i915_master_private *master_priv;
3736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3737         int pipe = intel_crtc->pipe;
3738
3739         if (!dev->primary->master)
3740                 return;
3741
3742         master_priv = dev->primary->master->driver_priv;
3743         if (!master_priv->sarea_priv)
3744                 return;
3745
3746         switch (pipe) {
3747         case 0:
3748                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3749                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3750                 break;
3751         case 1:
3752                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3753                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3754                 break;
3755         default:
3756                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3757                 break;
3758         }
3759 }
3760
3761 /**
3762  * Sets the power management mode of the pipe and plane.
3763  */
3764 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3765 {
3766         struct drm_device *dev = crtc->dev;
3767         struct drm_i915_private *dev_priv = dev->dev_private;
3768         struct intel_encoder *intel_encoder;
3769         bool enable = false;
3770
3771         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3772                 enable |= intel_encoder->connectors_active;
3773
3774         if (enable)
3775                 dev_priv->display.crtc_enable(crtc);
3776         else
3777                 dev_priv->display.crtc_disable(crtc);
3778
3779         intel_crtc_update_sarea(crtc, enable);
3780 }
3781
3782 static void intel_crtc_disable(struct drm_crtc *crtc)
3783 {
3784         struct drm_device *dev = crtc->dev;
3785         struct drm_connector *connector;
3786         struct drm_i915_private *dev_priv = dev->dev_private;
3787         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3788
3789         /* crtc should still be enabled when we disable it. */
3790         WARN_ON(!crtc->enabled);
3791
3792         dev_priv->display.crtc_disable(crtc);
3793         intel_crtc->eld_vld = false;
3794         intel_crtc_update_sarea(crtc, false);
3795         dev_priv->display.off(crtc);
3796
3797         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3798         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3799
3800         if (crtc->fb) {
3801                 mutex_lock(&dev->struct_mutex);
3802                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3803                 mutex_unlock(&dev->struct_mutex);
3804                 crtc->fb = NULL;
3805         }
3806
3807         /* Update computed state. */
3808         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3809                 if (!connector->encoder || !connector->encoder->crtc)
3810                         continue;
3811
3812                 if (connector->encoder->crtc != crtc)
3813                         continue;
3814
3815                 connector->dpms = DRM_MODE_DPMS_OFF;
3816                 to_intel_encoder(connector->encoder)->connectors_active = false;
3817         }
3818 }
3819
3820 void intel_modeset_disable(struct drm_device *dev)
3821 {
3822         struct drm_crtc *crtc;
3823
3824         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3825                 if (crtc->enabled)
3826                         intel_crtc_disable(crtc);
3827         }
3828 }
3829
3830 void intel_encoder_destroy(struct drm_encoder *encoder)
3831 {
3832         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3833
3834         drm_encoder_cleanup(encoder);
3835         kfree(intel_encoder);
3836 }
3837
3838 /* Simple dpms helper for encodres with just one connector, no cloning and only
3839  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3840  * state of the entire output pipe. */
3841 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3842 {
3843         if (mode == DRM_MODE_DPMS_ON) {
3844                 encoder->connectors_active = true;
3845
3846                 intel_crtc_update_dpms(encoder->base.crtc);
3847         } else {
3848                 encoder->connectors_active = false;
3849
3850                 intel_crtc_update_dpms(encoder->base.crtc);
3851         }
3852 }
3853
3854 /* Cross check the actual hw state with our own modeset state tracking (and it's
3855  * internal consistency). */
3856 static void intel_connector_check_state(struct intel_connector *connector)
3857 {
3858         if (connector->get_hw_state(connector)) {
3859                 struct intel_encoder *encoder = connector->encoder;
3860                 struct drm_crtc *crtc;
3861                 bool encoder_enabled;
3862                 enum pipe pipe;
3863
3864                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3865                               connector->base.base.id,
3866                               drm_get_connector_name(&connector->base));
3867
3868                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3869                      "wrong connector dpms state\n");
3870                 WARN(connector->base.encoder != &encoder->base,
3871                      "active connector not linked to encoder\n");
3872                 WARN(!encoder->connectors_active,
3873                      "encoder->connectors_active not set\n");
3874
3875                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3876                 WARN(!encoder_enabled, "encoder not enabled\n");
3877                 if (WARN_ON(!encoder->base.crtc))
3878                         return;
3879
3880                 crtc = encoder->base.crtc;
3881
3882                 WARN(!crtc->enabled, "crtc not enabled\n");
3883                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3884                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3885                      "encoder active on the wrong pipe\n");
3886         }
3887 }
3888
3889 /* Even simpler default implementation, if there's really no special case to
3890  * consider. */
3891 void intel_connector_dpms(struct drm_connector *connector, int mode)
3892 {
3893         struct intel_encoder *encoder = intel_attached_encoder(connector);
3894
3895         /* All the simple cases only support two dpms states. */
3896         if (mode != DRM_MODE_DPMS_ON)
3897                 mode = DRM_MODE_DPMS_OFF;
3898
3899         if (mode == connector->dpms)
3900                 return;
3901
3902         connector->dpms = mode;
3903
3904         /* Only need to change hw state when actually enabled */
3905         if (encoder->base.crtc)
3906                 intel_encoder_dpms(encoder, mode);
3907         else
3908                 WARN_ON(encoder->connectors_active != false);
3909
3910         intel_modeset_check_state(connector->dev);
3911 }
3912
3913 /* Simple connector->get_hw_state implementation for encoders that support only
3914  * one connector and no cloning and hence the encoder state determines the state
3915  * of the connector. */
3916 bool intel_connector_get_hw_state(struct intel_connector *connector)
3917 {
3918         enum pipe pipe = 0;
3919         struct intel_encoder *encoder = connector->encoder;
3920
3921         return encoder->get_hw_state(encoder, &pipe);
3922 }
3923
3924 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3925                                      struct intel_crtc_config *pipe_config)
3926 {
3927         struct drm_i915_private *dev_priv = dev->dev_private;
3928         struct intel_crtc *pipe_B_crtc =
3929                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3930
3931         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3932                       pipe_name(pipe), pipe_config->fdi_lanes);
3933         if (pipe_config->fdi_lanes > 4) {
3934                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3935                               pipe_name(pipe), pipe_config->fdi_lanes);
3936                 return false;
3937         }
3938
3939         if (IS_HASWELL(dev)) {
3940                 if (pipe_config->fdi_lanes > 2) {
3941                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3942                                       pipe_config->fdi_lanes);
3943                         return false;
3944                 } else {
3945                         return true;
3946                 }
3947         }
3948
3949         if (INTEL_INFO(dev)->num_pipes == 2)
3950                 return true;
3951
3952         /* Ivybridge 3 pipe is really complicated */
3953         switch (pipe) {
3954         case PIPE_A:
3955                 return true;
3956         case PIPE_B:
3957                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3958                     pipe_config->fdi_lanes > 2) {
3959                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3960                                       pipe_name(pipe), pipe_config->fdi_lanes);
3961                         return false;
3962                 }
3963                 return true;
3964         case PIPE_C:
3965                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3966                     pipe_B_crtc->config.fdi_lanes <= 2) {
3967                         if (pipe_config->fdi_lanes > 2) {
3968                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3969                                               pipe_name(pipe), pipe_config->fdi_lanes);
3970                                 return false;
3971                         }
3972                 } else {
3973                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3974                         return false;
3975                 }
3976                 return true;
3977         default:
3978                 BUG();
3979         }
3980 }
3981
3982 #define RETRY 1
3983 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3984                                        struct intel_crtc_config *pipe_config)
3985 {
3986         struct drm_device *dev = intel_crtc->base.dev;
3987         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3988         int target_clock, lane, link_bw;
3989         bool setup_ok, needs_recompute = false;
3990
3991 retry:
3992         /* FDI is a binary signal running at ~2.7GHz, encoding
3993          * each output octet as 10 bits. The actual frequency
3994          * is stored as a divider into a 100MHz clock, and the
3995          * mode pixel clock is stored in units of 1KHz.
3996          * Hence the bw of each lane in terms of the mode signal
3997          * is:
3998          */
3999         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4000
4001         if (pipe_config->pixel_target_clock)
4002                 target_clock = pipe_config->pixel_target_clock;
4003         else
4004                 target_clock = adjusted_mode->clock;
4005
4006         lane = ironlake_get_lanes_required(target_clock, link_bw,
4007                                            pipe_config->pipe_bpp);
4008
4009         pipe_config->fdi_lanes = lane;
4010
4011         if (pipe_config->pixel_multiplier > 1)
4012                 link_bw *= pipe_config->pixel_multiplier;
4013         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4014                                link_bw, &pipe_config->fdi_m_n);
4015
4016         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4017                                             intel_crtc->pipe, pipe_config);
4018         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4019                 pipe_config->pipe_bpp -= 2*3;
4020                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4021                               pipe_config->pipe_bpp);
4022                 needs_recompute = true;
4023                 pipe_config->bw_constrained = true;
4024
4025                 goto retry;
4026         }
4027
4028         if (needs_recompute)
4029                 return RETRY;
4030
4031         return setup_ok ? 0 : -EINVAL;
4032 }
4033
4034 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4035                                    struct intel_crtc_config *pipe_config)
4036 {
4037         pipe_config->ips_enabled = i915_enable_ips &&
4038                                    hsw_crtc_supports_ips(crtc) &&
4039                                    pipe_config->pipe_bpp == 24;
4040 }
4041
4042 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4043                                      struct intel_crtc_config *pipe_config)
4044 {
4045         struct drm_device *dev = crtc->dev;
4046         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4048
4049         if (HAS_PCH_SPLIT(dev)) {
4050                 /* FDI link clock is fixed at 2.7G */
4051                 if (pipe_config->requested_mode.clock * 3
4052                     > IRONLAKE_FDI_FREQ * 4)
4053                         return -EINVAL;
4054         }
4055
4056         /* All interlaced capable intel hw wants timings in frames. Note though
4057          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4058          * timings, so we need to be careful not to clobber these.*/
4059         if (!pipe_config->timings_set)
4060                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4061
4062         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4063          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4064          */
4065         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4066                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4067                 return -EINVAL;
4068
4069         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4070                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4071         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4072                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4073                  * for lvds. */
4074                 pipe_config->pipe_bpp = 8*3;
4075         }
4076
4077         if (IS_HASWELL(dev))
4078                 hsw_compute_ips_config(intel_crtc, pipe_config);
4079
4080         if (pipe_config->has_pch_encoder)
4081                 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
4082
4083         return 0;
4084 }
4085
4086 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4087 {
4088         return 400000; /* FIXME */
4089 }
4090
4091 static int i945_get_display_clock_speed(struct drm_device *dev)
4092 {
4093         return 400000;
4094 }
4095
4096 static int i915_get_display_clock_speed(struct drm_device *dev)
4097 {
4098         return 333000;
4099 }
4100
4101 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4102 {
4103         return 200000;
4104 }
4105
4106 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4107 {
4108         u16 gcfgc = 0;
4109
4110         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4111
4112         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4113                 return 133000;
4114         else {
4115                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4116                 case GC_DISPLAY_CLOCK_333_MHZ:
4117                         return 333000;
4118                 default:
4119                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4120                         return 190000;
4121                 }
4122         }
4123 }
4124
4125 static int i865_get_display_clock_speed(struct drm_device *dev)
4126 {
4127         return 266000;
4128 }
4129
4130 static int i855_get_display_clock_speed(struct drm_device *dev)
4131 {
4132         u16 hpllcc = 0;
4133         /* Assume that the hardware is in the high speed state.  This
4134          * should be the default.
4135          */
4136         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4137         case GC_CLOCK_133_200:
4138         case GC_CLOCK_100_200:
4139                 return 200000;
4140         case GC_CLOCK_166_250:
4141                 return 250000;
4142         case GC_CLOCK_100_133:
4143                 return 133000;
4144         }
4145
4146         /* Shouldn't happen */
4147         return 0;
4148 }
4149
4150 static int i830_get_display_clock_speed(struct drm_device *dev)
4151 {
4152         return 133000;
4153 }
4154
4155 static void
4156 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4157 {
4158         while (*num > DATA_LINK_M_N_MASK ||
4159                *den > DATA_LINK_M_N_MASK) {
4160                 *num >>= 1;
4161                 *den >>= 1;
4162         }
4163 }
4164
4165 static void compute_m_n(unsigned int m, unsigned int n,
4166                         uint32_t *ret_m, uint32_t *ret_n)
4167 {
4168         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4169         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4170         intel_reduce_m_n_ratio(ret_m, ret_n);
4171 }
4172
4173 void
4174 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4175                        int pixel_clock, int link_clock,
4176                        struct intel_link_m_n *m_n)
4177 {
4178         m_n->tu = 64;
4179
4180         compute_m_n(bits_per_pixel * pixel_clock,
4181                     link_clock * nlanes * 8,
4182                     &m_n->gmch_m, &m_n->gmch_n);
4183
4184         compute_m_n(pixel_clock, link_clock,
4185                     &m_n->link_m, &m_n->link_n);
4186 }
4187
4188 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4189 {
4190         if (i915_panel_use_ssc >= 0)
4191                 return i915_panel_use_ssc != 0;
4192         return dev_priv->vbt.lvds_use_ssc
4193                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4194 }
4195
4196 static int vlv_get_refclk(struct drm_crtc *crtc)
4197 {
4198         struct drm_device *dev = crtc->dev;
4199         struct drm_i915_private *dev_priv = dev->dev_private;
4200         int refclk = 27000; /* for DP & HDMI */
4201
4202         return 100000; /* only one validated so far */
4203
4204         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4205                 refclk = 96000;
4206         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4207                 if (intel_panel_use_ssc(dev_priv))
4208                         refclk = 100000;
4209                 else
4210                         refclk = 96000;
4211         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4212                 refclk = 100000;
4213         }
4214
4215         return refclk;
4216 }
4217
4218 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4219 {
4220         struct drm_device *dev = crtc->dev;
4221         struct drm_i915_private *dev_priv = dev->dev_private;
4222         int refclk;
4223
4224         if (IS_VALLEYVIEW(dev)) {
4225                 refclk = vlv_get_refclk(crtc);
4226         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4227             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4228                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4229                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4230                               refclk / 1000);
4231         } else if (!IS_GEN2(dev)) {
4232                 refclk = 96000;
4233         } else {
4234                 refclk = 48000;
4235         }
4236
4237         return refclk;
4238 }
4239
4240 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4241 {
4242         return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4243 }
4244
4245 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4246 {
4247         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4248 }
4249
4250 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4251                                      intel_clock_t *reduced_clock)
4252 {
4253         struct drm_device *dev = crtc->base.dev;
4254         struct drm_i915_private *dev_priv = dev->dev_private;
4255         int pipe = crtc->pipe;
4256         u32 fp, fp2 = 0;
4257
4258         if (IS_PINEVIEW(dev)) {
4259                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4260                 if (reduced_clock)
4261                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4262         } else {
4263                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4264                 if (reduced_clock)
4265                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4266         }
4267
4268         I915_WRITE(FP0(pipe), fp);
4269
4270         crtc->lowfreq_avail = false;
4271         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4272             reduced_clock && i915_powersave) {
4273                 I915_WRITE(FP1(pipe), fp2);
4274                 crtc->lowfreq_avail = true;
4275         } else {
4276                 I915_WRITE(FP1(pipe), fp);
4277         }
4278 }
4279
4280 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4281 {
4282         u32 reg_val;
4283
4284         /*
4285          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4286          * and set it to a reasonable value instead.
4287          */
4288         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4289         reg_val &= 0xffffff00;
4290         reg_val |= 0x00000030;
4291         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4292
4293         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4294         reg_val &= 0x8cffffff;
4295         reg_val = 0x8c000000;
4296         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4297
4298         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4299         reg_val &= 0xffffff00;
4300         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4301
4302         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4303         reg_val &= 0x00ffffff;
4304         reg_val |= 0xb0000000;
4305         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4306 }
4307
4308 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4309                                          struct intel_link_m_n *m_n)
4310 {
4311         struct drm_device *dev = crtc->base.dev;
4312         struct drm_i915_private *dev_priv = dev->dev_private;
4313         int pipe = crtc->pipe;
4314
4315         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4316         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4317         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4318         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4319 }
4320
4321 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4322                                          struct intel_link_m_n *m_n)
4323 {
4324         struct drm_device *dev = crtc->base.dev;
4325         struct drm_i915_private *dev_priv = dev->dev_private;
4326         int pipe = crtc->pipe;
4327         enum transcoder transcoder = crtc->config.cpu_transcoder;
4328
4329         if (INTEL_INFO(dev)->gen >= 5) {
4330                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4331                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4332                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4333                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4334         } else {
4335                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4336                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4337                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4338                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4339         }
4340 }
4341
4342 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4343 {
4344         if (crtc->config.has_pch_encoder)
4345                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4346         else
4347                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4348 }
4349
4350 static void vlv_update_pll(struct intel_crtc *crtc)
4351 {
4352         struct drm_device *dev = crtc->base.dev;
4353         struct drm_i915_private *dev_priv = dev->dev_private;
4354         struct drm_display_mode *adjusted_mode =
4355                 &crtc->config.adjusted_mode;
4356         struct intel_encoder *encoder;
4357         int pipe = crtc->pipe;
4358         u32 dpll, mdiv;
4359         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4360         bool is_hdmi;
4361         u32 coreclk, reg_val, dpll_md;
4362
4363         mutex_lock(&dev_priv->dpio_lock);
4364
4365         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4366
4367         bestn = crtc->config.dpll.n;
4368         bestm1 = crtc->config.dpll.m1;
4369         bestm2 = crtc->config.dpll.m2;
4370         bestp1 = crtc->config.dpll.p1;
4371         bestp2 = crtc->config.dpll.p2;
4372
4373         /* See eDP HDMI DPIO driver vbios notes doc */
4374
4375         /* PLL B needs special handling */
4376         if (pipe)
4377                 vlv_pllb_recal_opamp(dev_priv);
4378
4379         /* Set up Tx target for periodic Rcomp update */
4380         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4381
4382         /* Disable target IRef on PLL */
4383         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4384         reg_val &= 0x00ffffff;
4385         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4386
4387         /* Disable fast lock */
4388         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4389
4390         /* Set idtafcrecal before PLL is enabled */
4391         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4392         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4393         mdiv |= ((bestn << DPIO_N_SHIFT));
4394         mdiv |= (1 << DPIO_K_SHIFT);
4395
4396         /*
4397          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4398          * but we don't support that).
4399          * Note: don't use the DAC post divider as it seems unstable.
4400          */
4401         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4402         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4403
4404         mdiv |= DPIO_ENABLE_CALIBRATION;
4405         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4406
4407         /* Set HBR and RBR LPF coefficients */
4408         if (adjusted_mode->clock == 162000 ||
4409             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4410                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4411                                  0x005f0021);
4412         else
4413                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4414                                  0x00d0000f);
4415
4416         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4417             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4418                 /* Use SSC source */
4419                 if (!pipe)
4420                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4421                                          0x0df40000);
4422                 else
4423                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4424                                          0x0df70000);
4425         } else { /* HDMI or VGA */
4426                 /* Use bend source */
4427                 if (!pipe)
4428                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4429                                          0x0df70000);
4430                 else
4431                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4432                                          0x0df40000);
4433         }
4434
4435         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4436         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4437         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4438             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4439                 coreclk |= 0x01000000;
4440         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4441
4442         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4443
4444         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4445                 if (encoder->pre_pll_enable)
4446                         encoder->pre_pll_enable(encoder);
4447
4448         /* Enable DPIO clock input */
4449         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4450                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4451         if (pipe)
4452                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4453
4454         dpll |= DPLL_VCO_ENABLE;
4455         I915_WRITE(DPLL(pipe), dpll);
4456         POSTING_READ(DPLL(pipe));
4457         udelay(150);
4458
4459         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4460                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4461
4462         dpll_md = 0;
4463         if (crtc->config.pixel_multiplier > 1) {
4464                 dpll_md = (crtc->config.pixel_multiplier - 1)
4465                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4466         }
4467         I915_WRITE(DPLL_MD(pipe), dpll_md);
4468         POSTING_READ(DPLL_MD(pipe));
4469
4470         if (crtc->config.has_dp_encoder)
4471                 intel_dp_set_m_n(crtc);
4472
4473         mutex_unlock(&dev_priv->dpio_lock);
4474 }
4475
4476 static void i9xx_update_pll(struct intel_crtc *crtc,
4477                             intel_clock_t *reduced_clock,
4478                             int num_connectors)
4479 {
4480         struct drm_device *dev = crtc->base.dev;
4481         struct drm_i915_private *dev_priv = dev->dev_private;
4482         struct intel_encoder *encoder;
4483         int pipe = crtc->pipe;
4484         u32 dpll;
4485         bool is_sdvo;
4486         struct dpll *clock = &crtc->config.dpll;
4487
4488         i9xx_update_pll_dividers(crtc, reduced_clock);
4489
4490         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4491                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4492
4493         dpll = DPLL_VGA_MODE_DIS;
4494
4495         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4496                 dpll |= DPLLB_MODE_LVDS;
4497         else
4498                 dpll |= DPLLB_MODE_DAC_SERIAL;
4499
4500         if ((crtc->config.pixel_multiplier > 1) &&
4501             (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4502                 dpll |= (crtc->config.pixel_multiplier - 1)
4503                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4504         }
4505
4506         if (is_sdvo)
4507                 dpll |= DPLL_DVO_HIGH_SPEED;
4508
4509         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4510                 dpll |= DPLL_DVO_HIGH_SPEED;
4511
4512         /* compute bitmask from p1 value */
4513         if (IS_PINEVIEW(dev))
4514                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4515         else {
4516                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4517                 if (IS_G4X(dev) && reduced_clock)
4518                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4519         }
4520         switch (clock->p2) {
4521         case 5:
4522                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4523                 break;
4524         case 7:
4525                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4526                 break;
4527         case 10:
4528                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4529                 break;
4530         case 14:
4531                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4532                 break;
4533         }
4534         if (INTEL_INFO(dev)->gen >= 4)
4535                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4536
4537         if (crtc->config.sdvo_tv_clock)
4538                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4539         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4540                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4541                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4542         else
4543                 dpll |= PLL_REF_INPUT_DREFCLK;
4544
4545         dpll |= DPLL_VCO_ENABLE;
4546         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4547         POSTING_READ(DPLL(pipe));
4548         udelay(150);
4549
4550         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4551                 if (encoder->pre_pll_enable)
4552                         encoder->pre_pll_enable(encoder);
4553
4554         if (crtc->config.has_dp_encoder)
4555                 intel_dp_set_m_n(crtc);
4556
4557         I915_WRITE(DPLL(pipe), dpll);
4558
4559         /* Wait for the clocks to stabilize. */
4560         POSTING_READ(DPLL(pipe));
4561         udelay(150);
4562
4563         if (INTEL_INFO(dev)->gen >= 4) {
4564                 u32 dpll_md = 0;
4565                 if (crtc->config.pixel_multiplier > 1) {
4566                         dpll_md = (crtc->config.pixel_multiplier - 1)
4567                                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4568                 }
4569                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4570         } else {
4571                 /* The pixel multiplier can only be updated once the
4572                  * DPLL is enabled and the clocks are stable.
4573                  *
4574                  * So write it again.
4575                  */
4576                 I915_WRITE(DPLL(pipe), dpll);
4577         }
4578 }
4579
4580 static void i8xx_update_pll(struct intel_crtc *crtc,
4581                             struct drm_display_mode *adjusted_mode,
4582                             intel_clock_t *reduced_clock,
4583                             int num_connectors)
4584 {
4585         struct drm_device *dev = crtc->base.dev;
4586         struct drm_i915_private *dev_priv = dev->dev_private;
4587         struct intel_encoder *encoder;
4588         int pipe = crtc->pipe;
4589         u32 dpll;
4590         struct dpll *clock = &crtc->config.dpll;
4591
4592         i9xx_update_pll_dividers(crtc, reduced_clock);
4593
4594         dpll = DPLL_VGA_MODE_DIS;
4595
4596         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4597                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4598         } else {
4599                 if (clock->p1 == 2)
4600                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4601                 else
4602                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4603                 if (clock->p2 == 4)
4604                         dpll |= PLL_P2_DIVIDE_BY_4;
4605         }
4606
4607         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4608                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4609                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4610         else
4611                 dpll |= PLL_REF_INPUT_DREFCLK;
4612
4613         dpll |= DPLL_VCO_ENABLE;
4614         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4615         POSTING_READ(DPLL(pipe));
4616         udelay(150);
4617
4618         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4619                 if (encoder->pre_pll_enable)
4620                         encoder->pre_pll_enable(encoder);
4621
4622         I915_WRITE(DPLL(pipe), dpll);
4623
4624         /* Wait for the clocks to stabilize. */
4625         POSTING_READ(DPLL(pipe));
4626         udelay(150);
4627
4628         /* The pixel multiplier can only be updated once the
4629          * DPLL is enabled and the clocks are stable.
4630          *
4631          * So write it again.
4632          */
4633         I915_WRITE(DPLL(pipe), dpll);
4634 }
4635
4636 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4637                                    struct drm_display_mode *mode,
4638                                    struct drm_display_mode *adjusted_mode)
4639 {
4640         struct drm_device *dev = intel_crtc->base.dev;
4641         struct drm_i915_private *dev_priv = dev->dev_private;
4642         enum pipe pipe = intel_crtc->pipe;
4643         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4644         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4645
4646         /* We need to be careful not to changed the adjusted mode, for otherwise
4647          * the hw state checker will get angry at the mismatch. */
4648         crtc_vtotal = adjusted_mode->crtc_vtotal;
4649         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4650
4651         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4652                 /* the chip adds 2 halflines automatically */
4653                 crtc_vtotal -= 1;
4654                 crtc_vblank_end -= 1;
4655                 vsyncshift = adjusted_mode->crtc_hsync_start
4656                              - adjusted_mode->crtc_htotal / 2;
4657         } else {
4658                 vsyncshift = 0;
4659         }
4660
4661         if (INTEL_INFO(dev)->gen > 3)
4662                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4663
4664         I915_WRITE(HTOTAL(cpu_transcoder),
4665                    (adjusted_mode->crtc_hdisplay - 1) |
4666                    ((adjusted_mode->crtc_htotal - 1) << 16));
4667         I915_WRITE(HBLANK(cpu_transcoder),
4668                    (adjusted_mode->crtc_hblank_start - 1) |
4669                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4670         I915_WRITE(HSYNC(cpu_transcoder),
4671                    (adjusted_mode->crtc_hsync_start - 1) |
4672                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4673
4674         I915_WRITE(VTOTAL(cpu_transcoder),
4675                    (adjusted_mode->crtc_vdisplay - 1) |
4676                    ((crtc_vtotal - 1) << 16));
4677         I915_WRITE(VBLANK(cpu_transcoder),
4678                    (adjusted_mode->crtc_vblank_start - 1) |
4679                    ((crtc_vblank_end - 1) << 16));
4680         I915_WRITE(VSYNC(cpu_transcoder),
4681                    (adjusted_mode->crtc_vsync_start - 1) |
4682                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4683
4684         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4685          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4686          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4687          * bits. */
4688         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4689             (pipe == PIPE_B || pipe == PIPE_C))
4690                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4691
4692         /* pipesrc controls the size that is scaled from, which should
4693          * always be the user's requested size.
4694          */
4695         I915_WRITE(PIPESRC(pipe),
4696                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4697 }
4698
4699 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4700                                    struct intel_crtc_config *pipe_config)
4701 {
4702         struct drm_device *dev = crtc->base.dev;
4703         struct drm_i915_private *dev_priv = dev->dev_private;
4704         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4705         uint32_t tmp;
4706
4707         tmp = I915_READ(HTOTAL(cpu_transcoder));
4708         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4709         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4710         tmp = I915_READ(HBLANK(cpu_transcoder));
4711         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4712         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4713         tmp = I915_READ(HSYNC(cpu_transcoder));
4714         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4715         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4716
4717         tmp = I915_READ(VTOTAL(cpu_transcoder));
4718         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4719         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4720         tmp = I915_READ(VBLANK(cpu_transcoder));
4721         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4722         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4723         tmp = I915_READ(VSYNC(cpu_transcoder));
4724         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4725         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4726
4727         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4728                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4729                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4730                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4731         }
4732
4733         tmp = I915_READ(PIPESRC(crtc->pipe));
4734         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4735         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4736 }
4737
4738 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4739 {
4740         struct drm_device *dev = intel_crtc->base.dev;
4741         struct drm_i915_private *dev_priv = dev->dev_private;
4742         uint32_t pipeconf;
4743
4744         pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4745
4746         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4747                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4748                  * core speed.
4749                  *
4750                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4751                  * pipe == 0 check?
4752                  */
4753                 if (intel_crtc->config.requested_mode.clock >
4754                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4755                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4756                 else
4757                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4758         }
4759
4760         /* only g4x and later have fancy bpc/dither controls */
4761         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4762                 pipeconf &= ~(PIPECONF_BPC_MASK |
4763                               PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4764
4765                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4766                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4767                         pipeconf |= PIPECONF_DITHER_EN |
4768                                     PIPECONF_DITHER_TYPE_SP;
4769
4770                 switch (intel_crtc->config.pipe_bpp) {
4771                 case 18:
4772                         pipeconf |= PIPECONF_6BPC;
4773                         break;
4774                 case 24:
4775                         pipeconf |= PIPECONF_8BPC;
4776                         break;
4777                 case 30:
4778                         pipeconf |= PIPECONF_10BPC;
4779                         break;
4780                 default:
4781                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4782                         BUG();
4783                 }
4784         }
4785
4786         if (HAS_PIPE_CXSR(dev)) {
4787                 if (intel_crtc->lowfreq_avail) {
4788                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4789                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4790                 } else {
4791                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4792                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4793                 }
4794         }
4795
4796         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4797         if (!IS_GEN2(dev) &&
4798             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4799                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4800         else
4801                 pipeconf |= PIPECONF_PROGRESSIVE;
4802
4803         if (IS_VALLEYVIEW(dev)) {
4804                 if (intel_crtc->config.limited_color_range)
4805                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4806                 else
4807                         pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4808         }
4809
4810         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4811         POSTING_READ(PIPECONF(intel_crtc->pipe));
4812 }
4813
4814 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4815                               int x, int y,
4816                               struct drm_framebuffer *fb)
4817 {
4818         struct drm_device *dev = crtc->dev;
4819         struct drm_i915_private *dev_priv = dev->dev_private;
4820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4821         struct drm_display_mode *adjusted_mode =
4822                 &intel_crtc->config.adjusted_mode;
4823         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4824         int pipe = intel_crtc->pipe;
4825         int plane = intel_crtc->plane;
4826         int refclk, num_connectors = 0;
4827         intel_clock_t clock, reduced_clock;
4828         u32 dspcntr;
4829         bool ok, has_reduced_clock = false;
4830         bool is_lvds = false;
4831         struct intel_encoder *encoder;
4832         const intel_limit_t *limit;
4833         int ret;
4834
4835         for_each_encoder_on_crtc(dev, crtc, encoder) {
4836                 switch (encoder->type) {
4837                 case INTEL_OUTPUT_LVDS:
4838                         is_lvds = true;
4839                         break;
4840                 }
4841
4842                 num_connectors++;
4843         }
4844
4845         refclk = i9xx_get_refclk(crtc, num_connectors);
4846
4847         /*
4848          * Returns a set of divisors for the desired target clock with the given
4849          * refclk, or FALSE.  The returned values represent the clock equation:
4850          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4851          */
4852         limit = intel_limit(crtc, refclk);
4853         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4854                              &clock);
4855         if (!ok) {
4856                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4857                 return -EINVAL;
4858         }
4859
4860         /* Ensure that the cursor is valid for the new mode before changing... */
4861         intel_crtc_update_cursor(crtc, true);
4862
4863         if (is_lvds && dev_priv->lvds_downclock_avail) {
4864                 /*
4865                  * Ensure we match the reduced clock's P to the target clock.
4866                  * If the clocks don't match, we can't switch the display clock
4867                  * by using the FP0/FP1. In such case we will disable the LVDS
4868                  * downclock feature.
4869                 */
4870                 has_reduced_clock = limit->find_pll(limit, crtc,
4871                                                     dev_priv->lvds_downclock,
4872                                                     refclk,
4873                                                     &clock,
4874                                                     &reduced_clock);
4875         }
4876         /* Compat-code for transition, will disappear. */
4877         if (!intel_crtc->config.clock_set) {
4878                 intel_crtc->config.dpll.n = clock.n;
4879                 intel_crtc->config.dpll.m1 = clock.m1;
4880                 intel_crtc->config.dpll.m2 = clock.m2;
4881                 intel_crtc->config.dpll.p1 = clock.p1;
4882                 intel_crtc->config.dpll.p2 = clock.p2;
4883         }
4884
4885         if (IS_GEN2(dev))
4886                 i8xx_update_pll(intel_crtc, adjusted_mode,
4887                                 has_reduced_clock ? &reduced_clock : NULL,
4888                                 num_connectors);
4889         else if (IS_VALLEYVIEW(dev))
4890                 vlv_update_pll(intel_crtc);
4891         else
4892                 i9xx_update_pll(intel_crtc,
4893                                 has_reduced_clock ? &reduced_clock : NULL,
4894                                 num_connectors);
4895
4896         /* Set up the display plane register */
4897         dspcntr = DISPPLANE_GAMMA_ENABLE;
4898
4899         if (!IS_VALLEYVIEW(dev)) {
4900                 if (pipe == 0)
4901                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4902                 else
4903                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4904         }
4905
4906         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4907
4908         /* pipesrc and dspsize control the size that is scaled from,
4909          * which should always be the user's requested size.
4910          */
4911         I915_WRITE(DSPSIZE(plane),
4912                    ((mode->vdisplay - 1) << 16) |
4913                    (mode->hdisplay - 1));
4914         I915_WRITE(DSPPOS(plane), 0);
4915
4916         i9xx_set_pipeconf(intel_crtc);
4917
4918         I915_WRITE(DSPCNTR(plane), dspcntr);
4919         POSTING_READ(DSPCNTR(plane));
4920
4921         ret = intel_pipe_set_base(crtc, x, y, fb);
4922
4923         intel_update_watermarks(dev);
4924
4925         return ret;
4926 }
4927
4928 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4929                                  struct intel_crtc_config *pipe_config)
4930 {
4931         struct drm_device *dev = crtc->base.dev;
4932         struct drm_i915_private *dev_priv = dev->dev_private;
4933         uint32_t tmp;
4934
4935         tmp = I915_READ(PFIT_CONTROL);
4936
4937         if (INTEL_INFO(dev)->gen < 4) {
4938                 if (crtc->pipe != PIPE_B)
4939                         return;
4940
4941                 /* gen2/3 store dither state in pfit control, needs to match */
4942                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4943         } else {
4944                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4945                         return;
4946         }
4947
4948         if (!(tmp & PFIT_ENABLE))
4949                 return;
4950
4951         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4952         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4953         if (INTEL_INFO(dev)->gen < 5)
4954                 pipe_config->gmch_pfit.lvds_border_bits =
4955                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4956 }
4957
4958 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4959                                  struct intel_crtc_config *pipe_config)
4960 {
4961         struct drm_device *dev = crtc->base.dev;
4962         struct drm_i915_private *dev_priv = dev->dev_private;
4963         uint32_t tmp;
4964
4965         pipe_config->cpu_transcoder = crtc->pipe;
4966
4967         tmp = I915_READ(PIPECONF(crtc->pipe));
4968         if (!(tmp & PIPECONF_ENABLE))
4969                 return false;
4970
4971         intel_get_pipe_timings(crtc, pipe_config);
4972
4973         i9xx_get_pfit_config(crtc, pipe_config);
4974
4975         return true;
4976 }
4977
4978 static void ironlake_init_pch_refclk(struct drm_device *dev)
4979 {
4980         struct drm_i915_private *dev_priv = dev->dev_private;
4981         struct drm_mode_config *mode_config = &dev->mode_config;
4982         struct intel_encoder *encoder;
4983         u32 val, final;
4984         bool has_lvds = false;
4985         bool has_cpu_edp = false;
4986         bool has_panel = false;
4987         bool has_ck505 = false;
4988         bool can_ssc = false;
4989
4990         /* We need to take the global config into account */
4991         list_for_each_entry(encoder, &mode_config->encoder_list,
4992                             base.head) {
4993                 switch (encoder->type) {
4994                 case INTEL_OUTPUT_LVDS:
4995                         has_panel = true;
4996                         has_lvds = true;
4997                         break;
4998                 case INTEL_OUTPUT_EDP:
4999                         has_panel = true;
5000                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5001                                 has_cpu_edp = true;
5002                         break;
5003                 }
5004         }
5005
5006         if (HAS_PCH_IBX(dev)) {
5007                 has_ck505 = dev_priv->vbt.display_clock_mode;
5008                 can_ssc = has_ck505;
5009         } else {
5010                 has_ck505 = false;
5011                 can_ssc = true;
5012         }
5013
5014         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5015                       has_panel, has_lvds, has_ck505);
5016
5017         /* Ironlake: try to setup display ref clock before DPLL
5018          * enabling. This is only under driver's control after
5019          * PCH B stepping, previous chipset stepping should be
5020          * ignoring this setting.
5021          */
5022         val = I915_READ(PCH_DREF_CONTROL);
5023
5024         /* As we must carefully and slowly disable/enable each source in turn,
5025          * compute the final state we want first and check if we need to
5026          * make any changes at all.
5027          */
5028         final = val;
5029         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5030         if (has_ck505)
5031                 final |= DREF_NONSPREAD_CK505_ENABLE;
5032         else
5033                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5034
5035         final &= ~DREF_SSC_SOURCE_MASK;
5036         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5037         final &= ~DREF_SSC1_ENABLE;
5038
5039         if (has_panel) {
5040                 final |= DREF_SSC_SOURCE_ENABLE;
5041
5042                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5043                         final |= DREF_SSC1_ENABLE;
5044
5045                 if (has_cpu_edp) {
5046                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5047                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5048                         else
5049                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5050                 } else
5051                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5052         } else {
5053                 final |= DREF_SSC_SOURCE_DISABLE;
5054                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5055         }
5056
5057         if (final == val)
5058                 return;
5059
5060         /* Always enable nonspread source */
5061         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5062
5063         if (has_ck505)
5064                 val |= DREF_NONSPREAD_CK505_ENABLE;
5065         else
5066                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5067
5068         if (has_panel) {
5069                 val &= ~DREF_SSC_SOURCE_MASK;
5070                 val |= DREF_SSC_SOURCE_ENABLE;
5071
5072                 /* SSC must be turned on before enabling the CPU output  */
5073                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5074                         DRM_DEBUG_KMS("Using SSC on panel\n");
5075                         val |= DREF_SSC1_ENABLE;
5076                 } else
5077                         val &= ~DREF_SSC1_ENABLE;
5078
5079                 /* Get SSC going before enabling the outputs */
5080                 I915_WRITE(PCH_DREF_CONTROL, val);
5081                 POSTING_READ(PCH_DREF_CONTROL);
5082                 udelay(200);
5083
5084                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5085
5086                 /* Enable CPU source on CPU attached eDP */
5087                 if (has_cpu_edp) {
5088                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5089                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5090                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5091                         }
5092                         else
5093                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5094                 } else
5095                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5096
5097                 I915_WRITE(PCH_DREF_CONTROL, val);
5098                 POSTING_READ(PCH_DREF_CONTROL);
5099                 udelay(200);
5100         } else {
5101                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5102
5103                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5104
5105                 /* Turn off CPU output */
5106                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5107
5108                 I915_WRITE(PCH_DREF_CONTROL, val);
5109                 POSTING_READ(PCH_DREF_CONTROL);
5110                 udelay(200);
5111
5112                 /* Turn off the SSC source */
5113                 val &= ~DREF_SSC_SOURCE_MASK;
5114                 val |= DREF_SSC_SOURCE_DISABLE;
5115
5116                 /* Turn off SSC1 */
5117                 val &= ~DREF_SSC1_ENABLE;
5118
5119                 I915_WRITE(PCH_DREF_CONTROL, val);
5120                 POSTING_READ(PCH_DREF_CONTROL);
5121                 udelay(200);
5122         }
5123
5124         BUG_ON(val != final);
5125 }
5126
5127 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5128 static void lpt_init_pch_refclk(struct drm_device *dev)
5129 {
5130         struct drm_i915_private *dev_priv = dev->dev_private;
5131         struct drm_mode_config *mode_config = &dev->mode_config;
5132         struct intel_encoder *encoder;
5133         bool has_vga = false;
5134         bool is_sdv = false;
5135         u32 tmp;
5136
5137         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5138                 switch (encoder->type) {
5139                 case INTEL_OUTPUT_ANALOG:
5140                         has_vga = true;
5141                         break;
5142                 }
5143         }
5144
5145         if (!has_vga)
5146                 return;
5147
5148         mutex_lock(&dev_priv->dpio_lock);
5149
5150         /* XXX: Rip out SDV support once Haswell ships for real. */
5151         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5152                 is_sdv = true;
5153
5154         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5155         tmp &= ~SBI_SSCCTL_DISABLE;
5156         tmp |= SBI_SSCCTL_PATHALT;
5157         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5158
5159         udelay(24);
5160
5161         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5162         tmp &= ~SBI_SSCCTL_PATHALT;
5163         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5164
5165         if (!is_sdv) {
5166                 tmp = I915_READ(SOUTH_CHICKEN2);
5167                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5168                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5169
5170                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5171                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5172                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5173
5174                 tmp = I915_READ(SOUTH_CHICKEN2);
5175                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5176                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5177
5178                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5179                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5180                                        100))
5181                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5182         }
5183
5184         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5185         tmp &= ~(0xFF << 24);
5186         tmp |= (0x12 << 24);
5187         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5188
5189         if (is_sdv) {
5190                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5191                 tmp |= 0x7FFF;
5192                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5193         }
5194
5195         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5196         tmp |= (1 << 11);
5197         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5198
5199         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5200         tmp |= (1 << 11);
5201         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5202
5203         if (is_sdv) {
5204                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5205                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5206                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5207
5208                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5209                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5210                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5211
5212                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5213                 tmp |= (0x3F << 8);
5214                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5215
5216                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5217                 tmp |= (0x3F << 8);
5218                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5219         }
5220
5221         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5222         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5223         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5224
5225         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5226         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5227         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5228
5229         if (!is_sdv) {
5230                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5231                 tmp &= ~(7 << 13);
5232                 tmp |= (5 << 13);
5233                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5234
5235                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5236                 tmp &= ~(7 << 13);
5237                 tmp |= (5 << 13);
5238                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5239         }
5240
5241         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5242         tmp &= ~0xFF;
5243         tmp |= 0x1C;
5244         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5245
5246         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5247         tmp &= ~0xFF;
5248         tmp |= 0x1C;
5249         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5250
5251         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5252         tmp &= ~(0xFF << 16);
5253         tmp |= (0x1C << 16);
5254         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5255
5256         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5257         tmp &= ~(0xFF << 16);
5258         tmp |= (0x1C << 16);
5259         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5260
5261         if (!is_sdv) {
5262                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5263                 tmp |= (1 << 27);
5264                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5265
5266                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5267                 tmp |= (1 << 27);
5268                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5269
5270                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5271                 tmp &= ~(0xF << 28);
5272                 tmp |= (4 << 28);
5273                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5274
5275                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5276                 tmp &= ~(0xF << 28);
5277                 tmp |= (4 << 28);
5278                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5279         }
5280
5281         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5282         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5283         tmp |= SBI_DBUFF0_ENABLE;
5284         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5285
5286         mutex_unlock(&dev_priv->dpio_lock);
5287 }
5288
5289 /*
5290  * Initialize reference clocks when the driver loads
5291  */
5292 void intel_init_pch_refclk(struct drm_device *dev)
5293 {
5294         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5295                 ironlake_init_pch_refclk(dev);
5296         else if (HAS_PCH_LPT(dev))
5297                 lpt_init_pch_refclk(dev);
5298 }
5299
5300 static int ironlake_get_refclk(struct drm_crtc *crtc)
5301 {
5302         struct drm_device *dev = crtc->dev;
5303         struct drm_i915_private *dev_priv = dev->dev_private;
5304         struct intel_encoder *encoder;
5305         int num_connectors = 0;
5306         bool is_lvds = false;
5307
5308         for_each_encoder_on_crtc(dev, crtc, encoder) {
5309                 switch (encoder->type) {
5310                 case INTEL_OUTPUT_LVDS:
5311                         is_lvds = true;
5312                         break;
5313                 }
5314                 num_connectors++;
5315         }
5316
5317         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5318                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5319                               dev_priv->vbt.lvds_ssc_freq);
5320                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5321         }
5322
5323         return 120000;
5324 }
5325
5326 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5327 {
5328         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5330         int pipe = intel_crtc->pipe;
5331         uint32_t val;
5332
5333         val = I915_READ(PIPECONF(pipe));
5334
5335         val &= ~PIPECONF_BPC_MASK;
5336         switch (intel_crtc->config.pipe_bpp) {
5337         case 18:
5338                 val |= PIPECONF_6BPC;
5339                 break;
5340         case 24:
5341                 val |= PIPECONF_8BPC;
5342                 break;
5343         case 30:
5344                 val |= PIPECONF_10BPC;
5345                 break;
5346         case 36:
5347                 val |= PIPECONF_12BPC;
5348                 break;
5349         default:
5350                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5351                 BUG();
5352         }
5353
5354         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5355         if (intel_crtc->config.dither)
5356                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5357
5358         val &= ~PIPECONF_INTERLACE_MASK;
5359         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5360                 val |= PIPECONF_INTERLACED_ILK;
5361         else
5362                 val |= PIPECONF_PROGRESSIVE;
5363
5364         if (intel_crtc->config.limited_color_range)
5365                 val |= PIPECONF_COLOR_RANGE_SELECT;
5366         else
5367                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5368
5369         I915_WRITE(PIPECONF(pipe), val);
5370         POSTING_READ(PIPECONF(pipe));
5371 }
5372
5373 /*
5374  * Set up the pipe CSC unit.
5375  *
5376  * Currently only full range RGB to limited range RGB conversion
5377  * is supported, but eventually this should handle various
5378  * RGB<->YCbCr scenarios as well.
5379  */
5380 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5381 {
5382         struct drm_device *dev = crtc->dev;
5383         struct drm_i915_private *dev_priv = dev->dev_private;
5384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5385         int pipe = intel_crtc->pipe;
5386         uint16_t coeff = 0x7800; /* 1.0 */
5387
5388         /*
5389          * TODO: Check what kind of values actually come out of the pipe
5390          * with these coeff/postoff values and adjust to get the best
5391          * accuracy. Perhaps we even need to take the bpc value into
5392          * consideration.
5393          */
5394
5395         if (intel_crtc->config.limited_color_range)
5396                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5397
5398         /*
5399          * GY/GU and RY/RU should be the other way around according
5400          * to BSpec, but reality doesn't agree. Just set them up in
5401          * a way that results in the correct picture.
5402          */
5403         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5404         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5405
5406         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5407         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5408
5409         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5410         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5411
5412         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5413         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5414         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5415
5416         if (INTEL_INFO(dev)->gen > 6) {
5417                 uint16_t postoff = 0;
5418
5419                 if (intel_crtc->config.limited_color_range)
5420                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5421
5422                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5423                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5424                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5425
5426                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5427         } else {
5428                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5429
5430                 if (intel_crtc->config.limited_color_range)
5431                         mode |= CSC_BLACK_SCREEN_OFFSET;
5432
5433                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5434         }
5435 }
5436
5437 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5438 {
5439         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5441         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5442         uint32_t val;
5443
5444         val = I915_READ(PIPECONF(cpu_transcoder));
5445
5446         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5447         if (intel_crtc->config.dither)
5448                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5449
5450         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5451         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5452                 val |= PIPECONF_INTERLACED_ILK;
5453         else
5454                 val |= PIPECONF_PROGRESSIVE;
5455
5456         I915_WRITE(PIPECONF(cpu_transcoder), val);
5457         POSTING_READ(PIPECONF(cpu_transcoder));
5458 }
5459
5460 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5461                                     struct drm_display_mode *adjusted_mode,
5462                                     intel_clock_t *clock,
5463                                     bool *has_reduced_clock,
5464                                     intel_clock_t *reduced_clock)
5465 {
5466         struct drm_device *dev = crtc->dev;
5467         struct drm_i915_private *dev_priv = dev->dev_private;
5468         struct intel_encoder *intel_encoder;
5469         int refclk;
5470         const intel_limit_t *limit;
5471         bool ret, is_lvds = false;
5472
5473         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5474                 switch (intel_encoder->type) {
5475                 case INTEL_OUTPUT_LVDS:
5476                         is_lvds = true;
5477                         break;
5478                 }
5479         }
5480
5481         refclk = ironlake_get_refclk(crtc);
5482
5483         /*
5484          * Returns a set of divisors for the desired target clock with the given
5485          * refclk, or FALSE.  The returned values represent the clock equation:
5486          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5487          */
5488         limit = intel_limit(crtc, refclk);
5489         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5490                               clock);
5491         if (!ret)
5492                 return false;
5493
5494         if (is_lvds && dev_priv->lvds_downclock_avail) {
5495                 /*
5496                  * Ensure we match the reduced clock's P to the target clock.
5497                  * If the clocks don't match, we can't switch the display clock
5498                  * by using the FP0/FP1. In such case we will disable the LVDS
5499                  * downclock feature.
5500                 */
5501                 *has_reduced_clock = limit->find_pll(limit, crtc,
5502                                                      dev_priv->lvds_downclock,
5503                                                      refclk,
5504                                                      clock,
5505                                                      reduced_clock);
5506         }
5507
5508         return true;
5509 }
5510
5511 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5512 {
5513         struct drm_i915_private *dev_priv = dev->dev_private;
5514         uint32_t temp;
5515
5516         temp = I915_READ(SOUTH_CHICKEN1);
5517         if (temp & FDI_BC_BIFURCATION_SELECT)
5518                 return;
5519
5520         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5521         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5522
5523         temp |= FDI_BC_BIFURCATION_SELECT;
5524         DRM_DEBUG_KMS("enabling fdi C rx\n");
5525         I915_WRITE(SOUTH_CHICKEN1, temp);
5526         POSTING_READ(SOUTH_CHICKEN1);
5527 }
5528
5529 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5530 {
5531         struct drm_device *dev = intel_crtc->base.dev;
5532         struct drm_i915_private *dev_priv = dev->dev_private;
5533
5534         switch (intel_crtc->pipe) {
5535         case PIPE_A:
5536                 break;
5537         case PIPE_B:
5538                 if (intel_crtc->config.fdi_lanes > 2)
5539                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5540                 else
5541                         cpt_enable_fdi_bc_bifurcation(dev);
5542
5543                 break;
5544         case PIPE_C:
5545                 cpt_enable_fdi_bc_bifurcation(dev);
5546
5547                 break;
5548         default:
5549                 BUG();
5550         }
5551 }
5552
5553 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5554 {
5555         /*
5556          * Account for spread spectrum to avoid
5557          * oversubscribing the link. Max center spread
5558          * is 2.5%; use 5% for safety's sake.
5559          */
5560         u32 bps = target_clock * bpp * 21 / 20;
5561         return bps / (link_bw * 8) + 1;
5562 }
5563
5564 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5565 {
5566         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5567 }
5568
5569 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5570                                       u32 *fp,
5571                                       intel_clock_t *reduced_clock, u32 *fp2)
5572 {
5573         struct drm_crtc *crtc = &intel_crtc->base;
5574         struct drm_device *dev = crtc->dev;
5575         struct drm_i915_private *dev_priv = dev->dev_private;
5576         struct intel_encoder *intel_encoder;
5577         uint32_t dpll;
5578         int factor, num_connectors = 0;
5579         bool is_lvds = false, is_sdvo = false;
5580
5581         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5582                 switch (intel_encoder->type) {
5583                 case INTEL_OUTPUT_LVDS:
5584                         is_lvds = true;
5585                         break;
5586                 case INTEL_OUTPUT_SDVO:
5587                 case INTEL_OUTPUT_HDMI:
5588                         is_sdvo = true;
5589                         break;
5590                 }
5591
5592                 num_connectors++;
5593         }
5594
5595         /* Enable autotuning of the PLL clock (if permissible) */
5596         factor = 21;
5597         if (is_lvds) {
5598                 if ((intel_panel_use_ssc(dev_priv) &&
5599                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5600                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5601                         factor = 25;
5602         } else if (intel_crtc->config.sdvo_tv_clock)
5603                 factor = 20;
5604
5605         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5606                 *fp |= FP_CB_TUNE;
5607
5608         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5609                 *fp2 |= FP_CB_TUNE;
5610
5611         dpll = 0;
5612
5613         if (is_lvds)
5614                 dpll |= DPLLB_MODE_LVDS;
5615         else
5616                 dpll |= DPLLB_MODE_DAC_SERIAL;
5617
5618         if (intel_crtc->config.pixel_multiplier > 1) {
5619                 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5620                         << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5621         }
5622
5623         if (is_sdvo)
5624                 dpll |= DPLL_DVO_HIGH_SPEED;
5625         if (intel_crtc->config.has_dp_encoder)
5626                 dpll |= DPLL_DVO_HIGH_SPEED;
5627
5628         /* compute bitmask from p1 value */
5629         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5630         /* also FPA1 */
5631         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5632
5633         switch (intel_crtc->config.dpll.p2) {
5634         case 5:
5635                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5636                 break;
5637         case 7:
5638                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5639                 break;
5640         case 10:
5641                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5642                 break;
5643         case 14:
5644                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5645                 break;
5646         }
5647
5648         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5649                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5650         else
5651                 dpll |= PLL_REF_INPUT_DREFCLK;
5652
5653         return dpll;
5654 }
5655
5656 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5657                                   int x, int y,
5658                                   struct drm_framebuffer *fb)
5659 {
5660         struct drm_device *dev = crtc->dev;
5661         struct drm_i915_private *dev_priv = dev->dev_private;
5662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5663         struct drm_display_mode *adjusted_mode =
5664                 &intel_crtc->config.adjusted_mode;
5665         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5666         int pipe = intel_crtc->pipe;
5667         int plane = intel_crtc->plane;
5668         int num_connectors = 0;
5669         intel_clock_t clock, reduced_clock;
5670         u32 dpll = 0, fp = 0, fp2 = 0;
5671         bool ok, has_reduced_clock = false;
5672         bool is_lvds = false;
5673         struct intel_encoder *encoder;
5674         int ret;
5675
5676         for_each_encoder_on_crtc(dev, crtc, encoder) {
5677                 switch (encoder->type) {
5678                 case INTEL_OUTPUT_LVDS:
5679                         is_lvds = true;
5680                         break;
5681                 }
5682
5683                 num_connectors++;
5684         }
5685
5686         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5687              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5688
5689         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5690                                      &has_reduced_clock, &reduced_clock);
5691         if (!ok) {
5692                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5693                 return -EINVAL;
5694         }
5695         /* Compat-code for transition, will disappear. */
5696         if (!intel_crtc->config.clock_set) {
5697                 intel_crtc->config.dpll.n = clock.n;
5698                 intel_crtc->config.dpll.m1 = clock.m1;
5699                 intel_crtc->config.dpll.m2 = clock.m2;
5700                 intel_crtc->config.dpll.p1 = clock.p1;
5701                 intel_crtc->config.dpll.p2 = clock.p2;
5702         }
5703
5704         /* Ensure that the cursor is valid for the new mode before changing... */
5705         intel_crtc_update_cursor(crtc, true);
5706
5707         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5708         if (intel_crtc->config.has_pch_encoder) {
5709                 struct intel_pch_pll *pll;
5710
5711                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5712                 if (has_reduced_clock)
5713                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5714
5715                 dpll = ironlake_compute_dpll(intel_crtc,
5716                                              &fp, &reduced_clock,
5717                                              has_reduced_clock ? &fp2 : NULL);
5718
5719                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5720                 if (pll == NULL) {
5721                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5722                                          pipe_name(pipe));
5723                         return -EINVAL;
5724                 }
5725         } else
5726                 intel_put_pch_pll(intel_crtc);
5727
5728         if (intel_crtc->config.has_dp_encoder)
5729                 intel_dp_set_m_n(intel_crtc);
5730
5731         for_each_encoder_on_crtc(dev, crtc, encoder)
5732                 if (encoder->pre_pll_enable)
5733                         encoder->pre_pll_enable(encoder);
5734
5735         if (intel_crtc->pch_pll) {
5736                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5737
5738                 /* Wait for the clocks to stabilize. */
5739                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5740                 udelay(150);
5741
5742                 /* The pixel multiplier can only be updated once the
5743                  * DPLL is enabled and the clocks are stable.
5744                  *
5745                  * So write it again.
5746                  */
5747                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5748         }
5749
5750         intel_crtc->lowfreq_avail = false;
5751         if (intel_crtc->pch_pll) {
5752                 if (is_lvds && has_reduced_clock && i915_powersave) {
5753                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5754                         intel_crtc->lowfreq_avail = true;
5755                 } else {
5756                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5757                 }
5758         }
5759
5760         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5761
5762         if (intel_crtc->config.has_pch_encoder) {
5763                 intel_cpu_transcoder_set_m_n(intel_crtc,
5764                                              &intel_crtc->config.fdi_m_n);
5765         }
5766
5767         if (IS_IVYBRIDGE(dev))
5768                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5769
5770         ironlake_set_pipeconf(crtc);
5771
5772         /* Set up the display plane register */
5773         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5774         POSTING_READ(DSPCNTR(plane));
5775
5776         ret = intel_pipe_set_base(crtc, x, y, fb);
5777
5778         intel_update_watermarks(dev);
5779
5780         return ret;
5781 }
5782
5783 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5784                                         struct intel_crtc_config *pipe_config)
5785 {
5786         struct drm_device *dev = crtc->base.dev;
5787         struct drm_i915_private *dev_priv = dev->dev_private;
5788         enum transcoder transcoder = pipe_config->cpu_transcoder;
5789
5790         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5791         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5792         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5793                                         & ~TU_SIZE_MASK;
5794         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5795         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5796                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5797 }
5798
5799 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5800                                      struct intel_crtc_config *pipe_config)
5801 {
5802         struct drm_device *dev = crtc->base.dev;
5803         struct drm_i915_private *dev_priv = dev->dev_private;
5804         uint32_t tmp;
5805
5806         tmp = I915_READ(PF_CTL(crtc->pipe));
5807
5808         if (tmp & PF_ENABLE) {
5809                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5810                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5811         }
5812 }
5813
5814 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5815                                      struct intel_crtc_config *pipe_config)
5816 {
5817         struct drm_device *dev = crtc->base.dev;
5818         struct drm_i915_private *dev_priv = dev->dev_private;
5819         uint32_t tmp;
5820
5821         pipe_config->cpu_transcoder = crtc->pipe;
5822
5823         tmp = I915_READ(PIPECONF(crtc->pipe));
5824         if (!(tmp & PIPECONF_ENABLE))
5825                 return false;
5826
5827         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5828                 pipe_config->has_pch_encoder = true;
5829
5830                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5831                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5832                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5833
5834                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5835         }
5836
5837         intel_get_pipe_timings(crtc, pipe_config);
5838
5839         ironlake_get_pfit_config(crtc, pipe_config);
5840
5841         return true;
5842 }
5843
5844 static void haswell_modeset_global_resources(struct drm_device *dev)
5845 {
5846         bool enable = false;
5847         struct intel_crtc *crtc;
5848
5849         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5850                 if (!crtc->base.enabled)
5851                         continue;
5852
5853                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5854                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5855                         enable = true;
5856         }
5857
5858         intel_set_power_well(dev, enable);
5859 }
5860
5861 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5862                                  int x, int y,
5863                                  struct drm_framebuffer *fb)
5864 {
5865         struct drm_device *dev = crtc->dev;
5866         struct drm_i915_private *dev_priv = dev->dev_private;
5867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5868         struct drm_display_mode *adjusted_mode =
5869                 &intel_crtc->config.adjusted_mode;
5870         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5871         int pipe = intel_crtc->pipe;
5872         int plane = intel_crtc->plane;
5873         int num_connectors = 0;
5874         bool is_cpu_edp = false;
5875         struct intel_encoder *encoder;
5876         int ret;
5877
5878         for_each_encoder_on_crtc(dev, crtc, encoder) {
5879                 switch (encoder->type) {
5880                 case INTEL_OUTPUT_EDP:
5881                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5882                                 is_cpu_edp = true;
5883                         break;
5884                 }
5885
5886                 num_connectors++;
5887         }
5888
5889         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5890              num_connectors, pipe_name(pipe));
5891
5892         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5893                 return -EINVAL;
5894
5895         /* Ensure that the cursor is valid for the new mode before changing... */
5896         intel_crtc_update_cursor(crtc, true);
5897
5898         if (intel_crtc->config.has_dp_encoder)
5899                 intel_dp_set_m_n(intel_crtc);
5900
5901         intel_crtc->lowfreq_avail = false;
5902
5903         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5904
5905         if (intel_crtc->config.has_pch_encoder) {
5906                 intel_cpu_transcoder_set_m_n(intel_crtc,
5907                                              &intel_crtc->config.fdi_m_n);
5908         }
5909
5910         haswell_set_pipeconf(crtc);
5911
5912         intel_set_pipe_csc(crtc);
5913
5914         /* Set up the display plane register */
5915         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5916         POSTING_READ(DSPCNTR(plane));
5917
5918         ret = intel_pipe_set_base(crtc, x, y, fb);
5919
5920         intel_update_watermarks(dev);
5921
5922         return ret;
5923 }
5924
5925 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5926                                     struct intel_crtc_config *pipe_config)
5927 {
5928         struct drm_device *dev = crtc->base.dev;
5929         struct drm_i915_private *dev_priv = dev->dev_private;
5930         enum intel_display_power_domain pfit_domain;
5931         uint32_t tmp;
5932
5933         pipe_config->cpu_transcoder = crtc->pipe;
5934         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5935         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5936                 enum pipe trans_edp_pipe;
5937                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5938                 default:
5939                         WARN(1, "unknown pipe linked to edp transcoder\n");
5940                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5941                 case TRANS_DDI_EDP_INPUT_A_ON:
5942                         trans_edp_pipe = PIPE_A;
5943                         break;
5944                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5945                         trans_edp_pipe = PIPE_B;
5946                         break;
5947                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5948                         trans_edp_pipe = PIPE_C;
5949                         break;
5950                 }
5951
5952                 if (trans_edp_pipe == crtc->pipe)
5953                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5954         }
5955
5956         if (!intel_display_power_enabled(dev,
5957                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5958                 return false;
5959
5960         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5961         if (!(tmp & PIPECONF_ENABLE))
5962                 return false;
5963
5964         /*
5965          * Haswell has only FDI/PCH transcoder A. It is which is connected to
5966          * DDI E. So just check whether this pipe is wired to DDI E and whether
5967          * the PCH transcoder is on.
5968          */
5969         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5970         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5971             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5972                 pipe_config->has_pch_encoder = true;
5973
5974                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5975                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5976                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5977
5978                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5979         }
5980
5981         intel_get_pipe_timings(crtc, pipe_config);
5982
5983         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5984         if (intel_display_power_enabled(dev, pfit_domain))
5985                 ironlake_get_pfit_config(crtc, pipe_config);
5986
5987         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5988                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
5989
5990         return true;
5991 }
5992
5993 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5994                                int x, int y,
5995                                struct drm_framebuffer *fb)
5996 {
5997         struct drm_device *dev = crtc->dev;
5998         struct drm_i915_private *dev_priv = dev->dev_private;
5999         struct drm_encoder_helper_funcs *encoder_funcs;
6000         struct intel_encoder *encoder;
6001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6002         struct drm_display_mode *adjusted_mode =
6003                 &intel_crtc->config.adjusted_mode;
6004         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6005         int pipe = intel_crtc->pipe;
6006         int ret;
6007
6008         drm_vblank_pre_modeset(dev, pipe);
6009
6010         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6011
6012         drm_vblank_post_modeset(dev, pipe);
6013
6014         if (ret != 0)
6015                 return ret;
6016
6017         for_each_encoder_on_crtc(dev, crtc, encoder) {
6018                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6019                         encoder->base.base.id,
6020                         drm_get_encoder_name(&encoder->base),
6021                         mode->base.id, mode->name);
6022                 if (encoder->mode_set) {
6023                         encoder->mode_set(encoder);
6024                 } else {
6025                         encoder_funcs = encoder->base.helper_private;
6026                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6027                 }
6028         }
6029
6030         return 0;
6031 }
6032
6033 static bool intel_eld_uptodate(struct drm_connector *connector,
6034                                int reg_eldv, uint32_t bits_eldv,
6035                                int reg_elda, uint32_t bits_elda,
6036                                int reg_edid)
6037 {
6038         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6039         uint8_t *eld = connector->eld;
6040         uint32_t i;
6041
6042         i = I915_READ(reg_eldv);
6043         i &= bits_eldv;
6044
6045         if (!eld[0])
6046                 return !i;
6047
6048         if (!i)
6049                 return false;
6050
6051         i = I915_READ(reg_elda);
6052         i &= ~bits_elda;
6053         I915_WRITE(reg_elda, i);
6054
6055         for (i = 0; i < eld[2]; i++)
6056                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6057                         return false;
6058
6059         return true;
6060 }
6061
6062 static void g4x_write_eld(struct drm_connector *connector,
6063                           struct drm_crtc *crtc)
6064 {
6065         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6066         uint8_t *eld = connector->eld;
6067         uint32_t eldv;
6068         uint32_t len;
6069         uint32_t i;
6070
6071         i = I915_READ(G4X_AUD_VID_DID);
6072
6073         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6074                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6075         else
6076                 eldv = G4X_ELDV_DEVCTG;
6077
6078         if (intel_eld_uptodate(connector,
6079                                G4X_AUD_CNTL_ST, eldv,
6080                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6081                                G4X_HDMIW_HDMIEDID))
6082                 return;
6083
6084         i = I915_READ(G4X_AUD_CNTL_ST);
6085         i &= ~(eldv | G4X_ELD_ADDR);
6086         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6087         I915_WRITE(G4X_AUD_CNTL_ST, i);
6088
6089         if (!eld[0])
6090                 return;
6091
6092         len = min_t(uint8_t, eld[2], len);
6093         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6094         for (i = 0; i < len; i++)
6095                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6096
6097         i = I915_READ(G4X_AUD_CNTL_ST);
6098         i |= eldv;
6099         I915_WRITE(G4X_AUD_CNTL_ST, i);
6100 }
6101
6102 static void haswell_write_eld(struct drm_connector *connector,
6103                                      struct drm_crtc *crtc)
6104 {
6105         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6106         uint8_t *eld = connector->eld;
6107         struct drm_device *dev = crtc->dev;
6108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6109         uint32_t eldv;
6110         uint32_t i;
6111         int len;
6112         int pipe = to_intel_crtc(crtc)->pipe;
6113         int tmp;
6114
6115         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6116         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6117         int aud_config = HSW_AUD_CFG(pipe);
6118         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6119
6120
6121         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6122
6123         /* Audio output enable */
6124         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6125         tmp = I915_READ(aud_cntrl_st2);
6126         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6127         I915_WRITE(aud_cntrl_st2, tmp);
6128
6129         /* Wait for 1 vertical blank */
6130         intel_wait_for_vblank(dev, pipe);
6131
6132         /* Set ELD valid state */
6133         tmp = I915_READ(aud_cntrl_st2);
6134         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6135         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6136         I915_WRITE(aud_cntrl_st2, tmp);
6137         tmp = I915_READ(aud_cntrl_st2);
6138         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6139
6140         /* Enable HDMI mode */
6141         tmp = I915_READ(aud_config);
6142         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6143         /* clear N_programing_enable and N_value_index */
6144         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6145         I915_WRITE(aud_config, tmp);
6146
6147         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6148
6149         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6150         intel_crtc->eld_vld = true;
6151
6152         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6153                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6154                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6155                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6156         } else
6157                 I915_WRITE(aud_config, 0);
6158
6159         if (intel_eld_uptodate(connector,
6160                                aud_cntrl_st2, eldv,
6161                                aud_cntl_st, IBX_ELD_ADDRESS,
6162                                hdmiw_hdmiedid))
6163                 return;
6164
6165         i = I915_READ(aud_cntrl_st2);
6166         i &= ~eldv;
6167         I915_WRITE(aud_cntrl_st2, i);
6168
6169         if (!eld[0])
6170                 return;
6171
6172         i = I915_READ(aud_cntl_st);
6173         i &= ~IBX_ELD_ADDRESS;
6174         I915_WRITE(aud_cntl_st, i);
6175         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6176         DRM_DEBUG_DRIVER("port num:%d\n", i);
6177
6178         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6179         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6180         for (i = 0; i < len; i++)
6181                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6182
6183         i = I915_READ(aud_cntrl_st2);
6184         i |= eldv;
6185         I915_WRITE(aud_cntrl_st2, i);
6186
6187 }
6188
6189 static void ironlake_write_eld(struct drm_connector *connector,
6190                                      struct drm_crtc *crtc)
6191 {
6192         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6193         uint8_t *eld = connector->eld;
6194         uint32_t eldv;
6195         uint32_t i;
6196         int len;
6197         int hdmiw_hdmiedid;
6198         int aud_config;
6199         int aud_cntl_st;
6200         int aud_cntrl_st2;
6201         int pipe = to_intel_crtc(crtc)->pipe;
6202
6203         if (HAS_PCH_IBX(connector->dev)) {
6204                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6205                 aud_config = IBX_AUD_CFG(pipe);
6206                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6207                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6208         } else {
6209                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6210                 aud_config = CPT_AUD_CFG(pipe);
6211                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6212                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6213         }
6214
6215         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6216
6217         i = I915_READ(aud_cntl_st);
6218         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6219         if (!i) {
6220                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6221                 /* operate blindly on all ports */
6222                 eldv = IBX_ELD_VALIDB;
6223                 eldv |= IBX_ELD_VALIDB << 4;
6224                 eldv |= IBX_ELD_VALIDB << 8;
6225         } else {
6226                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6227                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6228         }
6229
6230         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6231                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6232                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6233                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6234         } else
6235                 I915_WRITE(aud_config, 0);
6236
6237         if (intel_eld_uptodate(connector,
6238                                aud_cntrl_st2, eldv,
6239                                aud_cntl_st, IBX_ELD_ADDRESS,
6240                                hdmiw_hdmiedid))
6241                 return;
6242
6243         i = I915_READ(aud_cntrl_st2);
6244         i &= ~eldv;
6245         I915_WRITE(aud_cntrl_st2, i);
6246
6247         if (!eld[0])
6248                 return;
6249
6250         i = I915_READ(aud_cntl_st);
6251         i &= ~IBX_ELD_ADDRESS;
6252         I915_WRITE(aud_cntl_st, i);
6253
6254         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6255         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6256         for (i = 0; i < len; i++)
6257                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6258
6259         i = I915_READ(aud_cntrl_st2);
6260         i |= eldv;
6261         I915_WRITE(aud_cntrl_st2, i);
6262 }
6263
6264 void intel_write_eld(struct drm_encoder *encoder,
6265                      struct drm_display_mode *mode)
6266 {
6267         struct drm_crtc *crtc = encoder->crtc;
6268         struct drm_connector *connector;
6269         struct drm_device *dev = encoder->dev;
6270         struct drm_i915_private *dev_priv = dev->dev_private;
6271
6272         connector = drm_select_eld(encoder, mode);
6273         if (!connector)
6274                 return;
6275
6276         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6277                          connector->base.id,
6278                          drm_get_connector_name(connector),
6279                          connector->encoder->base.id,
6280                          drm_get_encoder_name(connector->encoder));
6281
6282         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6283
6284         if (dev_priv->display.write_eld)
6285                 dev_priv->display.write_eld(connector, crtc);
6286 }
6287
6288 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6289 void intel_crtc_load_lut(struct drm_crtc *crtc)
6290 {
6291         struct drm_device *dev = crtc->dev;
6292         struct drm_i915_private *dev_priv = dev->dev_private;
6293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6294         enum pipe pipe = intel_crtc->pipe;
6295         int palreg = PALETTE(pipe);
6296         int i;
6297         bool reenable_ips = false;
6298
6299         /* The clocks have to be on to load the palette. */
6300         if (!crtc->enabled || !intel_crtc->active)
6301                 return;
6302
6303         /* use legacy palette for Ironlake */
6304         if (HAS_PCH_SPLIT(dev))
6305                 palreg = LGC_PALETTE(pipe);
6306
6307         /* Workaround : Do not read or write the pipe palette/gamma data while
6308          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6309          */
6310         if (intel_crtc->config.ips_enabled &&
6311             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6312              GAMMA_MODE_MODE_SPLIT)) {
6313                 hsw_disable_ips(intel_crtc);
6314                 reenable_ips = true;
6315         }
6316
6317         for (i = 0; i < 256; i++) {
6318                 I915_WRITE(palreg + 4 * i,
6319                            (intel_crtc->lut_r[i] << 16) |
6320                            (intel_crtc->lut_g[i] << 8) |
6321                            intel_crtc->lut_b[i]);
6322         }
6323
6324         if (reenable_ips)
6325                 hsw_enable_ips(intel_crtc);
6326 }
6327
6328 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6329 {
6330         struct drm_device *dev = crtc->dev;
6331         struct drm_i915_private *dev_priv = dev->dev_private;
6332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6333         bool visible = base != 0;
6334         u32 cntl;
6335
6336         if (intel_crtc->cursor_visible == visible)
6337                 return;
6338
6339         cntl = I915_READ(_CURACNTR);
6340         if (visible) {
6341                 /* On these chipsets we can only modify the base whilst
6342                  * the cursor is disabled.
6343                  */
6344                 I915_WRITE(_CURABASE, base);
6345
6346                 cntl &= ~(CURSOR_FORMAT_MASK);
6347                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6348                 cntl |= CURSOR_ENABLE |
6349                         CURSOR_GAMMA_ENABLE |
6350                         CURSOR_FORMAT_ARGB;
6351         } else
6352                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6353         I915_WRITE(_CURACNTR, cntl);
6354
6355         intel_crtc->cursor_visible = visible;
6356 }
6357
6358 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6359 {
6360         struct drm_device *dev = crtc->dev;
6361         struct drm_i915_private *dev_priv = dev->dev_private;
6362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6363         int pipe = intel_crtc->pipe;
6364         bool visible = base != 0;
6365
6366         if (intel_crtc->cursor_visible != visible) {
6367                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6368                 if (base) {
6369                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6370                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6371                         cntl |= pipe << 28; /* Connect to correct pipe */
6372                 } else {
6373                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6374                         cntl |= CURSOR_MODE_DISABLE;
6375                 }
6376                 I915_WRITE(CURCNTR(pipe), cntl);
6377
6378                 intel_crtc->cursor_visible = visible;
6379         }
6380         /* and commit changes on next vblank */
6381         I915_WRITE(CURBASE(pipe), base);
6382 }
6383
6384 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6385 {
6386         struct drm_device *dev = crtc->dev;
6387         struct drm_i915_private *dev_priv = dev->dev_private;
6388         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6389         int pipe = intel_crtc->pipe;
6390         bool visible = base != 0;
6391
6392         if (intel_crtc->cursor_visible != visible) {
6393                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6394                 if (base) {
6395                         cntl &= ~CURSOR_MODE;
6396                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6397                 } else {
6398                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6399                         cntl |= CURSOR_MODE_DISABLE;
6400                 }
6401                 if (IS_HASWELL(dev))
6402                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6403                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6404
6405                 intel_crtc->cursor_visible = visible;
6406         }
6407         /* and commit changes on next vblank */
6408         I915_WRITE(CURBASE_IVB(pipe), base);
6409 }
6410
6411 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6412 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6413                                      bool on)
6414 {
6415         struct drm_device *dev = crtc->dev;
6416         struct drm_i915_private *dev_priv = dev->dev_private;
6417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6418         int pipe = intel_crtc->pipe;
6419         int x = intel_crtc->cursor_x;
6420         int y = intel_crtc->cursor_y;
6421         u32 base, pos;
6422         bool visible;
6423
6424         pos = 0;
6425
6426         if (on && crtc->enabled && crtc->fb) {
6427                 base = intel_crtc->cursor_addr;
6428                 if (x > (int) crtc->fb->width)
6429                         base = 0;
6430
6431                 if (y > (int) crtc->fb->height)
6432                         base = 0;
6433         } else
6434                 base = 0;
6435
6436         if (x < 0) {
6437                 if (x + intel_crtc->cursor_width < 0)
6438                         base = 0;
6439
6440                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6441                 x = -x;
6442         }
6443         pos |= x << CURSOR_X_SHIFT;
6444
6445         if (y < 0) {
6446                 if (y + intel_crtc->cursor_height < 0)
6447                         base = 0;
6448
6449                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6450                 y = -y;
6451         }
6452         pos |= y << CURSOR_Y_SHIFT;
6453
6454         visible = base != 0;
6455         if (!visible && !intel_crtc->cursor_visible)
6456                 return;
6457
6458         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6459                 I915_WRITE(CURPOS_IVB(pipe), pos);
6460                 ivb_update_cursor(crtc, base);
6461         } else {
6462                 I915_WRITE(CURPOS(pipe), pos);
6463                 if (IS_845G(dev) || IS_I865G(dev))
6464                         i845_update_cursor(crtc, base);
6465                 else
6466                         i9xx_update_cursor(crtc, base);
6467         }
6468 }
6469
6470 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6471                                  struct drm_file *file,
6472                                  uint32_t handle,
6473                                  uint32_t width, uint32_t height)
6474 {
6475         struct drm_device *dev = crtc->dev;
6476         struct drm_i915_private *dev_priv = dev->dev_private;
6477         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6478         struct drm_i915_gem_object *obj;
6479         uint32_t addr;
6480         int ret;
6481
6482         /* if we want to turn off the cursor ignore width and height */
6483         if (!handle) {
6484                 DRM_DEBUG_KMS("cursor off\n");
6485                 addr = 0;
6486                 obj = NULL;
6487                 mutex_lock(&dev->struct_mutex);
6488                 goto finish;
6489         }
6490
6491         /* Currently we only support 64x64 cursors */
6492         if (width != 64 || height != 64) {
6493                 DRM_ERROR("we currently only support 64x64 cursors\n");
6494                 return -EINVAL;
6495         }
6496
6497         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6498         if (&obj->base == NULL)
6499                 return -ENOENT;
6500
6501         if (obj->base.size < width * height * 4) {
6502                 DRM_ERROR("buffer is to small\n");
6503                 ret = -ENOMEM;
6504                 goto fail;
6505         }
6506
6507         /* we only need to pin inside GTT if cursor is non-phy */
6508         mutex_lock(&dev->struct_mutex);
6509         if (!dev_priv->info->cursor_needs_physical) {
6510                 unsigned alignment;
6511
6512                 if (obj->tiling_mode) {
6513                         DRM_ERROR("cursor cannot be tiled\n");
6514                         ret = -EINVAL;
6515                         goto fail_locked;
6516                 }
6517
6518                 /* Note that the w/a also requires 2 PTE of padding following
6519                  * the bo. We currently fill all unused PTE with the shadow
6520                  * page and so we should always have valid PTE following the
6521                  * cursor preventing the VT-d warning.
6522                  */
6523                 alignment = 0;
6524                 if (need_vtd_wa(dev))
6525                         alignment = 64*1024;
6526
6527                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6528                 if (ret) {
6529                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6530                         goto fail_locked;
6531                 }
6532
6533                 ret = i915_gem_object_put_fence(obj);
6534                 if (ret) {
6535                         DRM_ERROR("failed to release fence for cursor");
6536                         goto fail_unpin;
6537                 }
6538
6539                 addr = obj->gtt_offset;
6540         } else {
6541                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6542                 ret = i915_gem_attach_phys_object(dev, obj,
6543                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6544                                                   align);
6545                 if (ret) {
6546                         DRM_ERROR("failed to attach phys object\n");
6547                         goto fail_locked;
6548                 }
6549                 addr = obj->phys_obj->handle->busaddr;
6550         }
6551
6552         if (IS_GEN2(dev))
6553                 I915_WRITE(CURSIZE, (height << 12) | width);
6554
6555  finish:
6556         if (intel_crtc->cursor_bo) {
6557                 if (dev_priv->info->cursor_needs_physical) {
6558                         if (intel_crtc->cursor_bo != obj)
6559                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6560                 } else
6561                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6562                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6563         }
6564
6565         mutex_unlock(&dev->struct_mutex);
6566
6567         intel_crtc->cursor_addr = addr;
6568         intel_crtc->cursor_bo = obj;
6569         intel_crtc->cursor_width = width;
6570         intel_crtc->cursor_height = height;
6571
6572         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6573
6574         return 0;
6575 fail_unpin:
6576         i915_gem_object_unpin(obj);
6577 fail_locked:
6578         mutex_unlock(&dev->struct_mutex);
6579 fail:
6580         drm_gem_object_unreference_unlocked(&obj->base);
6581         return ret;
6582 }
6583
6584 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6585 {
6586         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6587
6588         intel_crtc->cursor_x = x;
6589         intel_crtc->cursor_y = y;
6590
6591         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6592
6593         return 0;
6594 }
6595
6596 /** Sets the color ramps on behalf of RandR */
6597 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6598                                  u16 blue, int regno)
6599 {
6600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6601
6602         intel_crtc->lut_r[regno] = red >> 8;
6603         intel_crtc->lut_g[regno] = green >> 8;
6604         intel_crtc->lut_b[regno] = blue >> 8;
6605 }
6606
6607 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6608                              u16 *blue, int regno)
6609 {
6610         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6611
6612         *red = intel_crtc->lut_r[regno] << 8;
6613         *green = intel_crtc->lut_g[regno] << 8;
6614         *blue = intel_crtc->lut_b[regno] << 8;
6615 }
6616
6617 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6618                                  u16 *blue, uint32_t start, uint32_t size)
6619 {
6620         int end = (start + size > 256) ? 256 : start + size, i;
6621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6622
6623         for (i = start; i < end; i++) {
6624                 intel_crtc->lut_r[i] = red[i] >> 8;
6625                 intel_crtc->lut_g[i] = green[i] >> 8;
6626                 intel_crtc->lut_b[i] = blue[i] >> 8;
6627         }
6628
6629         intel_crtc_load_lut(crtc);
6630 }
6631
6632 /* VESA 640x480x72Hz mode to set on the pipe */
6633 static struct drm_display_mode load_detect_mode = {
6634         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6635                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6636 };
6637
6638 static struct drm_framebuffer *
6639 intel_framebuffer_create(struct drm_device *dev,
6640                          struct drm_mode_fb_cmd2 *mode_cmd,
6641                          struct drm_i915_gem_object *obj)
6642 {
6643         struct intel_framebuffer *intel_fb;
6644         int ret;
6645
6646         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6647         if (!intel_fb) {
6648                 drm_gem_object_unreference_unlocked(&obj->base);
6649                 return ERR_PTR(-ENOMEM);
6650         }
6651
6652         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6653         if (ret) {
6654                 drm_gem_object_unreference_unlocked(&obj->base);
6655                 kfree(intel_fb);
6656                 return ERR_PTR(ret);
6657         }
6658
6659         return &intel_fb->base;
6660 }
6661
6662 static u32
6663 intel_framebuffer_pitch_for_width(int width, int bpp)
6664 {
6665         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6666         return ALIGN(pitch, 64);
6667 }
6668
6669 static u32
6670 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6671 {
6672         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6673         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6674 }
6675
6676 static struct drm_framebuffer *
6677 intel_framebuffer_create_for_mode(struct drm_device *dev,
6678                                   struct drm_display_mode *mode,
6679                                   int depth, int bpp)
6680 {
6681         struct drm_i915_gem_object *obj;
6682         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6683
6684         obj = i915_gem_alloc_object(dev,
6685                                     intel_framebuffer_size_for_mode(mode, bpp));
6686         if (obj == NULL)
6687                 return ERR_PTR(-ENOMEM);
6688
6689         mode_cmd.width = mode->hdisplay;
6690         mode_cmd.height = mode->vdisplay;
6691         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6692                                                                 bpp);
6693         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6694
6695         return intel_framebuffer_create(dev, &mode_cmd, obj);
6696 }
6697
6698 static struct drm_framebuffer *
6699 mode_fits_in_fbdev(struct drm_device *dev,
6700                    struct drm_display_mode *mode)
6701 {
6702         struct drm_i915_private *dev_priv = dev->dev_private;
6703         struct drm_i915_gem_object *obj;
6704         struct drm_framebuffer *fb;
6705
6706         if (dev_priv->fbdev == NULL)
6707                 return NULL;
6708
6709         obj = dev_priv->fbdev->ifb.obj;
6710         if (obj == NULL)
6711                 return NULL;
6712
6713         fb = &dev_priv->fbdev->ifb.base;
6714         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6715                                                                fb->bits_per_pixel))
6716                 return NULL;
6717
6718         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6719                 return NULL;
6720
6721         return fb;
6722 }
6723
6724 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6725                                 struct drm_display_mode *mode,
6726                                 struct intel_load_detect_pipe *old)
6727 {
6728         struct intel_crtc *intel_crtc;
6729         struct intel_encoder *intel_encoder =
6730                 intel_attached_encoder(connector);
6731         struct drm_crtc *possible_crtc;
6732         struct drm_encoder *encoder = &intel_encoder->base;
6733         struct drm_crtc *crtc = NULL;
6734         struct drm_device *dev = encoder->dev;
6735         struct drm_framebuffer *fb;
6736         int i = -1;
6737
6738         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6739                       connector->base.id, drm_get_connector_name(connector),
6740                       encoder->base.id, drm_get_encoder_name(encoder));
6741
6742         /*
6743          * Algorithm gets a little messy:
6744          *
6745          *   - if the connector already has an assigned crtc, use it (but make
6746          *     sure it's on first)
6747          *
6748          *   - try to find the first unused crtc that can drive this connector,
6749          *     and use that if we find one
6750          */
6751
6752         /* See if we already have a CRTC for this connector */
6753         if (encoder->crtc) {
6754                 crtc = encoder->crtc;
6755
6756                 mutex_lock(&crtc->mutex);
6757
6758                 old->dpms_mode = connector->dpms;
6759                 old->load_detect_temp = false;
6760
6761                 /* Make sure the crtc and connector are running */
6762                 if (connector->dpms != DRM_MODE_DPMS_ON)
6763                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6764
6765                 return true;
6766         }
6767
6768         /* Find an unused one (if possible) */
6769         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6770                 i++;
6771                 if (!(encoder->possible_crtcs & (1 << i)))
6772                         continue;
6773                 if (!possible_crtc->enabled) {
6774                         crtc = possible_crtc;
6775                         break;
6776                 }
6777         }
6778
6779         /*
6780          * If we didn't find an unused CRTC, don't use any.
6781          */
6782         if (!crtc) {
6783                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6784                 return false;
6785         }
6786
6787         mutex_lock(&crtc->mutex);
6788         intel_encoder->new_crtc = to_intel_crtc(crtc);
6789         to_intel_connector(connector)->new_encoder = intel_encoder;
6790
6791         intel_crtc = to_intel_crtc(crtc);
6792         old->dpms_mode = connector->dpms;
6793         old->load_detect_temp = true;
6794         old->release_fb = NULL;
6795
6796         if (!mode)
6797                 mode = &load_detect_mode;
6798
6799         /* We need a framebuffer large enough to accommodate all accesses
6800          * that the plane may generate whilst we perform load detection.
6801          * We can not rely on the fbcon either being present (we get called
6802          * during its initialisation to detect all boot displays, or it may
6803          * not even exist) or that it is large enough to satisfy the
6804          * requested mode.
6805          */
6806         fb = mode_fits_in_fbdev(dev, mode);
6807         if (fb == NULL) {
6808                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6809                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6810                 old->release_fb = fb;
6811         } else
6812                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6813         if (IS_ERR(fb)) {
6814                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6815                 mutex_unlock(&crtc->mutex);
6816                 return false;
6817         }
6818
6819         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6820                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6821                 if (old->release_fb)
6822                         old->release_fb->funcs->destroy(old->release_fb);
6823                 mutex_unlock(&crtc->mutex);
6824                 return false;
6825         }
6826
6827         /* let the connector get through one full cycle before testing */
6828         intel_wait_for_vblank(dev, intel_crtc->pipe);
6829         return true;
6830 }
6831
6832 void intel_release_load_detect_pipe(struct drm_connector *connector,
6833                                     struct intel_load_detect_pipe *old)
6834 {
6835         struct intel_encoder *intel_encoder =
6836                 intel_attached_encoder(connector);
6837         struct drm_encoder *encoder = &intel_encoder->base;
6838         struct drm_crtc *crtc = encoder->crtc;
6839
6840         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6841                       connector->base.id, drm_get_connector_name(connector),
6842                       encoder->base.id, drm_get_encoder_name(encoder));
6843
6844         if (old->load_detect_temp) {
6845                 to_intel_connector(connector)->new_encoder = NULL;
6846                 intel_encoder->new_crtc = NULL;
6847                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6848
6849                 if (old->release_fb) {
6850                         drm_framebuffer_unregister_private(old->release_fb);
6851                         drm_framebuffer_unreference(old->release_fb);
6852                 }
6853
6854                 mutex_unlock(&crtc->mutex);
6855                 return;
6856         }
6857
6858         /* Switch crtc and encoder back off if necessary */
6859         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6860                 connector->funcs->dpms(connector, old->dpms_mode);
6861
6862         mutex_unlock(&crtc->mutex);
6863 }
6864
6865 /* Returns the clock of the currently programmed mode of the given pipe. */
6866 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6867 {
6868         struct drm_i915_private *dev_priv = dev->dev_private;
6869         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6870         int pipe = intel_crtc->pipe;
6871         u32 dpll = I915_READ(DPLL(pipe));
6872         u32 fp;
6873         intel_clock_t clock;
6874
6875         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6876                 fp = I915_READ(FP0(pipe));
6877         else
6878                 fp = I915_READ(FP1(pipe));
6879
6880         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6881         if (IS_PINEVIEW(dev)) {
6882                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6883                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6884         } else {
6885                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6886                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6887         }
6888
6889         if (!IS_GEN2(dev)) {
6890                 if (IS_PINEVIEW(dev))
6891                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6892                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6893                 else
6894                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6895                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6896
6897                 switch (dpll & DPLL_MODE_MASK) {
6898                 case DPLLB_MODE_DAC_SERIAL:
6899                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6900                                 5 : 10;
6901                         break;
6902                 case DPLLB_MODE_LVDS:
6903                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6904                                 7 : 14;
6905                         break;
6906                 default:
6907                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6908                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6909                         return 0;
6910                 }
6911
6912                 /* XXX: Handle the 100Mhz refclk */
6913                 intel_clock(dev, 96000, &clock);
6914         } else {
6915                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6916
6917                 if (is_lvds) {
6918                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6919                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6920                         clock.p2 = 14;
6921
6922                         if ((dpll & PLL_REF_INPUT_MASK) ==
6923                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6924                                 /* XXX: might not be 66MHz */
6925                                 intel_clock(dev, 66000, &clock);
6926                         } else
6927                                 intel_clock(dev, 48000, &clock);
6928                 } else {
6929                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6930                                 clock.p1 = 2;
6931                         else {
6932                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6933                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6934                         }
6935                         if (dpll & PLL_P2_DIVIDE_BY_4)
6936                                 clock.p2 = 4;
6937                         else
6938                                 clock.p2 = 2;
6939
6940                         intel_clock(dev, 48000, &clock);
6941                 }
6942         }
6943
6944         /* XXX: It would be nice to validate the clocks, but we can't reuse
6945          * i830PllIsValid() because it relies on the xf86_config connector
6946          * configuration being accurate, which it isn't necessarily.
6947          */
6948
6949         return clock.dot;
6950 }
6951
6952 /** Returns the currently programmed mode of the given pipe. */
6953 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6954                                              struct drm_crtc *crtc)
6955 {
6956         struct drm_i915_private *dev_priv = dev->dev_private;
6957         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6958         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6959         struct drm_display_mode *mode;
6960         int htot = I915_READ(HTOTAL(cpu_transcoder));
6961         int hsync = I915_READ(HSYNC(cpu_transcoder));
6962         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6963         int vsync = I915_READ(VSYNC(cpu_transcoder));
6964
6965         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6966         if (!mode)
6967                 return NULL;
6968
6969         mode->clock = intel_crtc_clock_get(dev, crtc);
6970         mode->hdisplay = (htot & 0xffff) + 1;
6971         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6972         mode->hsync_start = (hsync & 0xffff) + 1;
6973         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6974         mode->vdisplay = (vtot & 0xffff) + 1;
6975         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6976         mode->vsync_start = (vsync & 0xffff) + 1;
6977         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6978
6979         drm_mode_set_name(mode);
6980
6981         return mode;
6982 }
6983
6984 static void intel_increase_pllclock(struct drm_crtc *crtc)
6985 {
6986         struct drm_device *dev = crtc->dev;
6987         drm_i915_private_t *dev_priv = dev->dev_private;
6988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6989         int pipe = intel_crtc->pipe;
6990         int dpll_reg = DPLL(pipe);
6991         int dpll;
6992
6993         if (HAS_PCH_SPLIT(dev))
6994                 return;
6995
6996         if (!dev_priv->lvds_downclock_avail)
6997                 return;
6998
6999         dpll = I915_READ(dpll_reg);
7000         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7001                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7002
7003                 assert_panel_unlocked(dev_priv, pipe);
7004
7005                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7006                 I915_WRITE(dpll_reg, dpll);
7007                 intel_wait_for_vblank(dev, pipe);
7008
7009                 dpll = I915_READ(dpll_reg);
7010                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7011                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7012         }
7013 }
7014
7015 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7016 {
7017         struct drm_device *dev = crtc->dev;
7018         drm_i915_private_t *dev_priv = dev->dev_private;
7019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7020
7021         if (HAS_PCH_SPLIT(dev))
7022                 return;
7023
7024         if (!dev_priv->lvds_downclock_avail)
7025                 return;
7026
7027         /*
7028          * Since this is called by a timer, we should never get here in
7029          * the manual case.
7030          */
7031         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7032                 int pipe = intel_crtc->pipe;
7033                 int dpll_reg = DPLL(pipe);
7034                 int dpll;
7035
7036                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7037
7038                 assert_panel_unlocked(dev_priv, pipe);
7039
7040                 dpll = I915_READ(dpll_reg);
7041                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7042                 I915_WRITE(dpll_reg, dpll);
7043                 intel_wait_for_vblank(dev, pipe);
7044                 dpll = I915_READ(dpll_reg);
7045                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7046                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7047         }
7048
7049 }
7050
7051 void intel_mark_busy(struct drm_device *dev)
7052 {
7053         i915_update_gfx_val(dev->dev_private);
7054 }
7055
7056 void intel_mark_idle(struct drm_device *dev)
7057 {
7058         struct drm_crtc *crtc;
7059
7060         if (!i915_powersave)
7061                 return;
7062
7063         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7064                 if (!crtc->fb)
7065                         continue;
7066
7067                 intel_decrease_pllclock(crtc);
7068         }
7069 }
7070
7071 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7072 {
7073         struct drm_device *dev = obj->base.dev;
7074         struct drm_crtc *crtc;
7075
7076         if (!i915_powersave)
7077                 return;
7078
7079         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7080                 if (!crtc->fb)
7081                         continue;
7082
7083                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7084                         intel_increase_pllclock(crtc);
7085         }
7086 }
7087
7088 static void intel_crtc_destroy(struct drm_crtc *crtc)
7089 {
7090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7091         struct drm_device *dev = crtc->dev;
7092         struct intel_unpin_work *work;
7093         unsigned long flags;
7094
7095         spin_lock_irqsave(&dev->event_lock, flags);
7096         work = intel_crtc->unpin_work;
7097         intel_crtc->unpin_work = NULL;
7098         spin_unlock_irqrestore(&dev->event_lock, flags);
7099
7100         if (work) {
7101                 cancel_work_sync(&work->work);
7102                 kfree(work);
7103         }
7104
7105         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7106
7107         drm_crtc_cleanup(crtc);
7108
7109         kfree(intel_crtc);
7110 }
7111
7112 static void intel_unpin_work_fn(struct work_struct *__work)
7113 {
7114         struct intel_unpin_work *work =
7115                 container_of(__work, struct intel_unpin_work, work);
7116         struct drm_device *dev = work->crtc->dev;
7117
7118         mutex_lock(&dev->struct_mutex);
7119         intel_unpin_fb_obj(work->old_fb_obj);
7120         drm_gem_object_unreference(&work->pending_flip_obj->base);
7121         drm_gem_object_unreference(&work->old_fb_obj->base);
7122
7123         intel_update_fbc(dev);
7124         mutex_unlock(&dev->struct_mutex);
7125
7126         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7127         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7128
7129         kfree(work);
7130 }
7131
7132 static void do_intel_finish_page_flip(struct drm_device *dev,
7133                                       struct drm_crtc *crtc)
7134 {
7135         drm_i915_private_t *dev_priv = dev->dev_private;
7136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7137         struct intel_unpin_work *work;
7138         unsigned long flags;
7139
7140         /* Ignore early vblank irqs */
7141         if (intel_crtc == NULL)
7142                 return;
7143
7144         spin_lock_irqsave(&dev->event_lock, flags);
7145         work = intel_crtc->unpin_work;
7146
7147         /* Ensure we don't miss a work->pending update ... */
7148         smp_rmb();
7149
7150         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7151                 spin_unlock_irqrestore(&dev->event_lock, flags);
7152                 return;
7153         }
7154
7155         /* and that the unpin work is consistent wrt ->pending. */
7156         smp_rmb();
7157
7158         intel_crtc->unpin_work = NULL;
7159
7160         if (work->event)
7161                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7162
7163         drm_vblank_put(dev, intel_crtc->pipe);
7164
7165         spin_unlock_irqrestore(&dev->event_lock, flags);
7166
7167         wake_up_all(&dev_priv->pending_flip_queue);
7168
7169         queue_work(dev_priv->wq, &work->work);
7170
7171         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7172 }
7173
7174 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7175 {
7176         drm_i915_private_t *dev_priv = dev->dev_private;
7177         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7178
7179         do_intel_finish_page_flip(dev, crtc);
7180 }
7181
7182 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7183 {
7184         drm_i915_private_t *dev_priv = dev->dev_private;
7185         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7186
7187         do_intel_finish_page_flip(dev, crtc);
7188 }
7189
7190 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7191 {
7192         drm_i915_private_t *dev_priv = dev->dev_private;
7193         struct intel_crtc *intel_crtc =
7194                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7195         unsigned long flags;
7196
7197         /* NB: An MMIO update of the plane base pointer will also
7198          * generate a page-flip completion irq, i.e. every modeset
7199          * is also accompanied by a spurious intel_prepare_page_flip().
7200          */
7201         spin_lock_irqsave(&dev->event_lock, flags);
7202         if (intel_crtc->unpin_work)
7203                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7204         spin_unlock_irqrestore(&dev->event_lock, flags);
7205 }
7206
7207 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7208 {
7209         /* Ensure that the work item is consistent when activating it ... */
7210         smp_wmb();
7211         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7212         /* and that it is marked active as soon as the irq could fire. */
7213         smp_wmb();
7214 }
7215
7216 static int intel_gen2_queue_flip(struct drm_device *dev,
7217                                  struct drm_crtc *crtc,
7218                                  struct drm_framebuffer *fb,
7219                                  struct drm_i915_gem_object *obj)
7220 {
7221         struct drm_i915_private *dev_priv = dev->dev_private;
7222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7223         u32 flip_mask;
7224         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7225         int ret;
7226
7227         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7228         if (ret)
7229                 goto err;
7230
7231         ret = intel_ring_begin(ring, 6);
7232         if (ret)
7233                 goto err_unpin;
7234
7235         /* Can't queue multiple flips, so wait for the previous
7236          * one to finish before executing the next.
7237          */
7238         if (intel_crtc->plane)
7239                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7240         else
7241                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7242         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7243         intel_ring_emit(ring, MI_NOOP);
7244         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7245                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7246         intel_ring_emit(ring, fb->pitches[0]);
7247         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7248         intel_ring_emit(ring, 0); /* aux display base address, unused */
7249
7250         intel_mark_page_flip_active(intel_crtc);
7251         intel_ring_advance(ring);
7252         return 0;
7253
7254 err_unpin:
7255         intel_unpin_fb_obj(obj);
7256 err:
7257         return ret;
7258 }
7259
7260 static int intel_gen3_queue_flip(struct drm_device *dev,
7261                                  struct drm_crtc *crtc,
7262                                  struct drm_framebuffer *fb,
7263                                  struct drm_i915_gem_object *obj)
7264 {
7265         struct drm_i915_private *dev_priv = dev->dev_private;
7266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7267         u32 flip_mask;
7268         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7269         int ret;
7270
7271         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7272         if (ret)
7273                 goto err;
7274
7275         ret = intel_ring_begin(ring, 6);
7276         if (ret)
7277                 goto err_unpin;
7278
7279         if (intel_crtc->plane)
7280                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7281         else
7282                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7283         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7284         intel_ring_emit(ring, MI_NOOP);
7285         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7286                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7287         intel_ring_emit(ring, fb->pitches[0]);
7288         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7289         intel_ring_emit(ring, MI_NOOP);
7290
7291         intel_mark_page_flip_active(intel_crtc);
7292         intel_ring_advance(ring);
7293         return 0;
7294
7295 err_unpin:
7296         intel_unpin_fb_obj(obj);
7297 err:
7298         return ret;
7299 }
7300
7301 static int intel_gen4_queue_flip(struct drm_device *dev,
7302                                  struct drm_crtc *crtc,
7303                                  struct drm_framebuffer *fb,
7304                                  struct drm_i915_gem_object *obj)
7305 {
7306         struct drm_i915_private *dev_priv = dev->dev_private;
7307         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7308         uint32_t pf, pipesrc;
7309         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7310         int ret;
7311
7312         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7313         if (ret)
7314                 goto err;
7315
7316         ret = intel_ring_begin(ring, 4);
7317         if (ret)
7318                 goto err_unpin;
7319
7320         /* i965+ uses the linear or tiled offsets from the
7321          * Display Registers (which do not change across a page-flip)
7322          * so we need only reprogram the base address.
7323          */
7324         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7325                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7326         intel_ring_emit(ring, fb->pitches[0]);
7327         intel_ring_emit(ring,
7328                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7329                         obj->tiling_mode);
7330
7331         /* XXX Enabling the panel-fitter across page-flip is so far
7332          * untested on non-native modes, so ignore it for now.
7333          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7334          */
7335         pf = 0;
7336         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7337         intel_ring_emit(ring, pf | pipesrc);
7338
7339         intel_mark_page_flip_active(intel_crtc);
7340         intel_ring_advance(ring);
7341         return 0;
7342
7343 err_unpin:
7344         intel_unpin_fb_obj(obj);
7345 err:
7346         return ret;
7347 }
7348
7349 static int intel_gen6_queue_flip(struct drm_device *dev,
7350                                  struct drm_crtc *crtc,
7351                                  struct drm_framebuffer *fb,
7352                                  struct drm_i915_gem_object *obj)
7353 {
7354         struct drm_i915_private *dev_priv = dev->dev_private;
7355         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7356         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7357         uint32_t pf, pipesrc;
7358         int ret;
7359
7360         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7361         if (ret)
7362                 goto err;
7363
7364         ret = intel_ring_begin(ring, 4);
7365         if (ret)
7366                 goto err_unpin;
7367
7368         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7369                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7370         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7371         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7372
7373         /* Contrary to the suggestions in the documentation,
7374          * "Enable Panel Fitter" does not seem to be required when page
7375          * flipping with a non-native mode, and worse causes a normal
7376          * modeset to fail.
7377          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7378          */
7379         pf = 0;
7380         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7381         intel_ring_emit(ring, pf | pipesrc);
7382
7383         intel_mark_page_flip_active(intel_crtc);
7384         intel_ring_advance(ring);
7385         return 0;
7386
7387 err_unpin:
7388         intel_unpin_fb_obj(obj);
7389 err:
7390         return ret;
7391 }
7392
7393 /*
7394  * On gen7 we currently use the blit ring because (in early silicon at least)
7395  * the render ring doesn't give us interrpts for page flip completion, which
7396  * means clients will hang after the first flip is queued.  Fortunately the
7397  * blit ring generates interrupts properly, so use it instead.
7398  */
7399 static int intel_gen7_queue_flip(struct drm_device *dev,
7400                                  struct drm_crtc *crtc,
7401                                  struct drm_framebuffer *fb,
7402                                  struct drm_i915_gem_object *obj)
7403 {
7404         struct drm_i915_private *dev_priv = dev->dev_private;
7405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7406         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7407         uint32_t plane_bit = 0;
7408         int ret;
7409
7410         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7411         if (ret)
7412                 goto err;
7413
7414         switch(intel_crtc->plane) {
7415         case PLANE_A:
7416                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7417                 break;
7418         case PLANE_B:
7419                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7420                 break;
7421         case PLANE_C:
7422                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7423                 break;
7424         default:
7425                 WARN_ONCE(1, "unknown plane in flip command\n");
7426                 ret = -ENODEV;
7427                 goto err_unpin;
7428         }
7429
7430         ret = intel_ring_begin(ring, 4);
7431         if (ret)
7432                 goto err_unpin;
7433
7434         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7435         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7436         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7437         intel_ring_emit(ring, (MI_NOOP));
7438
7439         intel_mark_page_flip_active(intel_crtc);
7440         intel_ring_advance(ring);
7441         return 0;
7442
7443 err_unpin:
7444         intel_unpin_fb_obj(obj);
7445 err:
7446         return ret;
7447 }
7448
7449 static int intel_default_queue_flip(struct drm_device *dev,
7450                                     struct drm_crtc *crtc,
7451                                     struct drm_framebuffer *fb,
7452                                     struct drm_i915_gem_object *obj)
7453 {
7454         return -ENODEV;
7455 }
7456
7457 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7458                                 struct drm_framebuffer *fb,
7459                                 struct drm_pending_vblank_event *event)
7460 {
7461         struct drm_device *dev = crtc->dev;
7462         struct drm_i915_private *dev_priv = dev->dev_private;
7463         struct drm_framebuffer *old_fb = crtc->fb;
7464         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7466         struct intel_unpin_work *work;
7467         unsigned long flags;
7468         int ret;
7469
7470         /* Can't change pixel format via MI display flips. */
7471         if (fb->pixel_format != crtc->fb->pixel_format)
7472                 return -EINVAL;
7473
7474         /*
7475          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7476          * Note that pitch changes could also affect these register.
7477          */
7478         if (INTEL_INFO(dev)->gen > 3 &&
7479             (fb->offsets[0] != crtc->fb->offsets[0] ||
7480              fb->pitches[0] != crtc->fb->pitches[0]))
7481                 return -EINVAL;
7482
7483         work = kzalloc(sizeof *work, GFP_KERNEL);
7484         if (work == NULL)
7485                 return -ENOMEM;
7486
7487         work->event = event;
7488         work->crtc = crtc;
7489         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7490         INIT_WORK(&work->work, intel_unpin_work_fn);
7491
7492         ret = drm_vblank_get(dev, intel_crtc->pipe);
7493         if (ret)
7494                 goto free_work;
7495
7496         /* We borrow the event spin lock for protecting unpin_work */
7497         spin_lock_irqsave(&dev->event_lock, flags);
7498         if (intel_crtc->unpin_work) {
7499                 spin_unlock_irqrestore(&dev->event_lock, flags);
7500                 kfree(work);
7501                 drm_vblank_put(dev, intel_crtc->pipe);
7502
7503                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7504                 return -EBUSY;
7505         }
7506         intel_crtc->unpin_work = work;
7507         spin_unlock_irqrestore(&dev->event_lock, flags);
7508
7509         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7510                 flush_workqueue(dev_priv->wq);
7511
7512         ret = i915_mutex_lock_interruptible(dev);
7513         if (ret)
7514                 goto cleanup;
7515
7516         /* Reference the objects for the scheduled work. */
7517         drm_gem_object_reference(&work->old_fb_obj->base);
7518         drm_gem_object_reference(&obj->base);
7519
7520         crtc->fb = fb;
7521
7522         work->pending_flip_obj = obj;
7523
7524         work->enable_stall_check = true;
7525
7526         atomic_inc(&intel_crtc->unpin_work_count);
7527         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7528
7529         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7530         if (ret)
7531                 goto cleanup_pending;
7532
7533         intel_disable_fbc(dev);
7534         intel_mark_fb_busy(obj);
7535         mutex_unlock(&dev->struct_mutex);
7536
7537         trace_i915_flip_request(intel_crtc->plane, obj);
7538
7539         return 0;
7540
7541 cleanup_pending:
7542         atomic_dec(&intel_crtc->unpin_work_count);
7543         crtc->fb = old_fb;
7544         drm_gem_object_unreference(&work->old_fb_obj->base);
7545         drm_gem_object_unreference(&obj->base);
7546         mutex_unlock(&dev->struct_mutex);
7547
7548 cleanup:
7549         spin_lock_irqsave(&dev->event_lock, flags);
7550         intel_crtc->unpin_work = NULL;
7551         spin_unlock_irqrestore(&dev->event_lock, flags);
7552
7553         drm_vblank_put(dev, intel_crtc->pipe);
7554 free_work:
7555         kfree(work);
7556
7557         return ret;
7558 }
7559
7560 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7561         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7562         .load_lut = intel_crtc_load_lut,
7563 };
7564
7565 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7566 {
7567         struct intel_encoder *other_encoder;
7568         struct drm_crtc *crtc = &encoder->new_crtc->base;
7569
7570         if (WARN_ON(!crtc))
7571                 return false;
7572
7573         list_for_each_entry(other_encoder,
7574                             &crtc->dev->mode_config.encoder_list,
7575                             base.head) {
7576
7577                 if (&other_encoder->new_crtc->base != crtc ||
7578                     encoder == other_encoder)
7579                         continue;
7580                 else
7581                         return true;
7582         }
7583
7584         return false;
7585 }
7586
7587 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7588                                   struct drm_crtc *crtc)
7589 {
7590         struct drm_device *dev;
7591         struct drm_crtc *tmp;
7592         int crtc_mask = 1;
7593
7594         WARN(!crtc, "checking null crtc?\n");
7595
7596         dev = crtc->dev;
7597
7598         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7599                 if (tmp == crtc)
7600                         break;
7601                 crtc_mask <<= 1;
7602         }
7603
7604         if (encoder->possible_crtcs & crtc_mask)
7605                 return true;
7606         return false;
7607 }
7608
7609 /**
7610  * intel_modeset_update_staged_output_state
7611  *
7612  * Updates the staged output configuration state, e.g. after we've read out the
7613  * current hw state.
7614  */
7615 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7616 {
7617         struct intel_encoder *encoder;
7618         struct intel_connector *connector;
7619
7620         list_for_each_entry(connector, &dev->mode_config.connector_list,
7621                             base.head) {
7622                 connector->new_encoder =
7623                         to_intel_encoder(connector->base.encoder);
7624         }
7625
7626         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7627                             base.head) {
7628                 encoder->new_crtc =
7629                         to_intel_crtc(encoder->base.crtc);
7630         }
7631 }
7632
7633 /**
7634  * intel_modeset_commit_output_state
7635  *
7636  * This function copies the stage display pipe configuration to the real one.
7637  */
7638 static void intel_modeset_commit_output_state(struct drm_device *dev)
7639 {
7640         struct intel_encoder *encoder;
7641         struct intel_connector *connector;
7642
7643         list_for_each_entry(connector, &dev->mode_config.connector_list,
7644                             base.head) {
7645                 connector->base.encoder = &connector->new_encoder->base;
7646         }
7647
7648         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7649                             base.head) {
7650                 encoder->base.crtc = &encoder->new_crtc->base;
7651         }
7652 }
7653
7654 static int
7655 pipe_config_set_bpp(struct drm_crtc *crtc,
7656                     struct drm_framebuffer *fb,
7657                     struct intel_crtc_config *pipe_config)
7658 {
7659         struct drm_device *dev = crtc->dev;
7660         struct drm_connector *connector;
7661         int bpp;
7662
7663         switch (fb->pixel_format) {
7664         case DRM_FORMAT_C8:
7665                 bpp = 8*3; /* since we go through a colormap */
7666                 break;
7667         case DRM_FORMAT_XRGB1555:
7668         case DRM_FORMAT_ARGB1555:
7669                 /* checked in intel_framebuffer_init already */
7670                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7671                         return -EINVAL;
7672         case DRM_FORMAT_RGB565:
7673                 bpp = 6*3; /* min is 18bpp */
7674                 break;
7675         case DRM_FORMAT_XBGR8888:
7676         case DRM_FORMAT_ABGR8888:
7677                 /* checked in intel_framebuffer_init already */
7678                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7679                         return -EINVAL;
7680         case DRM_FORMAT_XRGB8888:
7681         case DRM_FORMAT_ARGB8888:
7682                 bpp = 8*3;
7683                 break;
7684         case DRM_FORMAT_XRGB2101010:
7685         case DRM_FORMAT_ARGB2101010:
7686         case DRM_FORMAT_XBGR2101010:
7687         case DRM_FORMAT_ABGR2101010:
7688                 /* checked in intel_framebuffer_init already */
7689                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7690                         return -EINVAL;
7691                 bpp = 10*3;
7692                 break;
7693         /* TODO: gen4+ supports 16 bpc floating point, too. */
7694         default:
7695                 DRM_DEBUG_KMS("unsupported depth\n");
7696                 return -EINVAL;
7697         }
7698
7699         pipe_config->pipe_bpp = bpp;
7700
7701         /* Clamp display bpp to EDID value */
7702         list_for_each_entry(connector, &dev->mode_config.connector_list,
7703                             head) {
7704                 if (connector->encoder && connector->encoder->crtc != crtc)
7705                         continue;
7706
7707                 /* Don't use an invalid EDID bpc value */
7708                 if (connector->display_info.bpc &&
7709                     connector->display_info.bpc * 3 < bpp) {
7710                         DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7711                                       bpp, connector->display_info.bpc*3);
7712                         pipe_config->pipe_bpp = connector->display_info.bpc*3;
7713                 }
7714
7715                 /* Clamp bpp to 8 on screens without EDID 1.4 */
7716                 if (connector->display_info.bpc == 0 && bpp > 24) {
7717                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7718                                       bpp);
7719                         pipe_config->pipe_bpp = 24;
7720                 }
7721         }
7722
7723         return bpp;
7724 }
7725
7726 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7727                                    struct intel_crtc_config *pipe_config,
7728                                    const char *context)
7729 {
7730         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7731                       context, pipe_name(crtc->pipe));
7732
7733         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7734         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7735                       pipe_config->pipe_bpp, pipe_config->dither);
7736         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7737                       pipe_config->has_pch_encoder,
7738                       pipe_config->fdi_lanes,
7739                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7740                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7741                       pipe_config->fdi_m_n.tu);
7742         DRM_DEBUG_KMS("requested mode:\n");
7743         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7744         DRM_DEBUG_KMS("adjusted mode:\n");
7745         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7746         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7747                       pipe_config->gmch_pfit.control,
7748                       pipe_config->gmch_pfit.pgm_ratios,
7749                       pipe_config->gmch_pfit.lvds_border_bits);
7750         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7751                       pipe_config->pch_pfit.pos,
7752                       pipe_config->pch_pfit.size);
7753         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7754 }
7755
7756 static struct intel_crtc_config *
7757 intel_modeset_pipe_config(struct drm_crtc *crtc,
7758                           struct drm_framebuffer *fb,
7759                           struct drm_display_mode *mode)
7760 {
7761         struct drm_device *dev = crtc->dev;
7762         struct drm_encoder_helper_funcs *encoder_funcs;
7763         struct intel_encoder *encoder;
7764         struct intel_crtc_config *pipe_config;
7765         int plane_bpp, ret = -EINVAL;
7766         bool retry = true;
7767
7768         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7769         if (!pipe_config)
7770                 return ERR_PTR(-ENOMEM);
7771
7772         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7773         drm_mode_copy(&pipe_config->requested_mode, mode);
7774         pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7775
7776         plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7777         if (plane_bpp < 0)
7778                 goto fail;
7779
7780 encoder_retry:
7781         /* Pass our mode to the connectors and the CRTC to give them a chance to
7782          * adjust it according to limitations or connector properties, and also
7783          * a chance to reject the mode entirely.
7784          */
7785         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7786                             base.head) {
7787
7788                 if (&encoder->new_crtc->base != crtc)
7789                         continue;
7790
7791                 if (encoder->compute_config) {
7792                         if (!(encoder->compute_config(encoder, pipe_config))) {
7793                                 DRM_DEBUG_KMS("Encoder config failure\n");
7794                                 goto fail;
7795                         }
7796
7797                         continue;
7798                 }
7799
7800                 encoder_funcs = encoder->base.helper_private;
7801                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7802                                                 &pipe_config->requested_mode,
7803                                                 &pipe_config->adjusted_mode))) {
7804                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7805                         goto fail;
7806                 }
7807         }
7808
7809         ret = intel_crtc_compute_config(crtc, pipe_config);
7810         if (ret < 0) {
7811                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7812                 goto fail;
7813         }
7814
7815         if (ret == RETRY) {
7816                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7817                         ret = -EINVAL;
7818                         goto fail;
7819                 }
7820
7821                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7822                 retry = false;
7823                 goto encoder_retry;
7824         }
7825
7826         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7827         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7828                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7829
7830         return pipe_config;
7831 fail:
7832         kfree(pipe_config);
7833         return ERR_PTR(ret);
7834 }
7835
7836 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7837  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7838 static void
7839 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7840                              unsigned *prepare_pipes, unsigned *disable_pipes)
7841 {
7842         struct intel_crtc *intel_crtc;
7843         struct drm_device *dev = crtc->dev;
7844         struct intel_encoder *encoder;
7845         struct intel_connector *connector;
7846         struct drm_crtc *tmp_crtc;
7847
7848         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7849
7850         /* Check which crtcs have changed outputs connected to them, these need
7851          * to be part of the prepare_pipes mask. We don't (yet) support global
7852          * modeset across multiple crtcs, so modeset_pipes will only have one
7853          * bit set at most. */
7854         list_for_each_entry(connector, &dev->mode_config.connector_list,
7855                             base.head) {
7856                 if (connector->base.encoder == &connector->new_encoder->base)
7857                         continue;
7858
7859                 if (connector->base.encoder) {
7860                         tmp_crtc = connector->base.encoder->crtc;
7861
7862                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7863                 }
7864
7865                 if (connector->new_encoder)
7866                         *prepare_pipes |=
7867                                 1 << connector->new_encoder->new_crtc->pipe;
7868         }
7869
7870         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7871                             base.head) {
7872                 if (encoder->base.crtc == &encoder->new_crtc->base)
7873                         continue;
7874
7875                 if (encoder->base.crtc) {
7876                         tmp_crtc = encoder->base.crtc;
7877
7878                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7879                 }
7880
7881                 if (encoder->new_crtc)
7882                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7883         }
7884
7885         /* Check for any pipes that will be fully disabled ... */
7886         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7887                             base.head) {
7888                 bool used = false;
7889
7890                 /* Don't try to disable disabled crtcs. */
7891                 if (!intel_crtc->base.enabled)
7892                         continue;
7893
7894                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7895                                     base.head) {
7896                         if (encoder->new_crtc == intel_crtc)
7897                                 used = true;
7898                 }
7899
7900                 if (!used)
7901                         *disable_pipes |= 1 << intel_crtc->pipe;
7902         }
7903
7904
7905         /* set_mode is also used to update properties on life display pipes. */
7906         intel_crtc = to_intel_crtc(crtc);
7907         if (crtc->enabled)
7908                 *prepare_pipes |= 1 << intel_crtc->pipe;
7909
7910         /*
7911          * For simplicity do a full modeset on any pipe where the output routing
7912          * changed. We could be more clever, but that would require us to be
7913          * more careful with calling the relevant encoder->mode_set functions.
7914          */
7915         if (*prepare_pipes)
7916                 *modeset_pipes = *prepare_pipes;
7917
7918         /* ... and mask these out. */
7919         *modeset_pipes &= ~(*disable_pipes);
7920         *prepare_pipes &= ~(*disable_pipes);
7921
7922         /*
7923          * HACK: We don't (yet) fully support global modesets. intel_set_config
7924          * obies this rule, but the modeset restore mode of
7925          * intel_modeset_setup_hw_state does not.
7926          */
7927         *modeset_pipes &= 1 << intel_crtc->pipe;
7928         *prepare_pipes &= 1 << intel_crtc->pipe;
7929
7930         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7931                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7932 }
7933
7934 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7935 {
7936         struct drm_encoder *encoder;
7937         struct drm_device *dev = crtc->dev;
7938
7939         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7940                 if (encoder->crtc == crtc)
7941                         return true;
7942
7943         return false;
7944 }
7945
7946 static void
7947 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7948 {
7949         struct intel_encoder *intel_encoder;
7950         struct intel_crtc *intel_crtc;
7951         struct drm_connector *connector;
7952
7953         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7954                             base.head) {
7955                 if (!intel_encoder->base.crtc)
7956                         continue;
7957
7958                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7959
7960                 if (prepare_pipes & (1 << intel_crtc->pipe))
7961                         intel_encoder->connectors_active = false;
7962         }
7963
7964         intel_modeset_commit_output_state(dev);
7965
7966         /* Update computed state. */
7967         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7968                             base.head) {
7969                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7970         }
7971
7972         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7973                 if (!connector->encoder || !connector->encoder->crtc)
7974                         continue;
7975
7976                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7977
7978                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7979                         struct drm_property *dpms_property =
7980                                 dev->mode_config.dpms_property;
7981
7982                         connector->dpms = DRM_MODE_DPMS_ON;
7983                         drm_object_property_set_value(&connector->base,
7984                                                          dpms_property,
7985                                                          DRM_MODE_DPMS_ON);
7986
7987                         intel_encoder = to_intel_encoder(connector->encoder);
7988                         intel_encoder->connectors_active = true;
7989                 }
7990         }
7991
7992 }
7993
7994 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7995         list_for_each_entry((intel_crtc), \
7996                             &(dev)->mode_config.crtc_list, \
7997                             base.head) \
7998                 if (mask & (1 <<(intel_crtc)->pipe))
7999
8000 static bool
8001 intel_pipe_config_compare(struct drm_device *dev,
8002                           struct intel_crtc_config *current_config,
8003                           struct intel_crtc_config *pipe_config)
8004 {
8005 #define PIPE_CONF_CHECK_I(name) \
8006         if (current_config->name != pipe_config->name) { \
8007                 DRM_ERROR("mismatch in " #name " " \
8008                           "(expected %i, found %i)\n", \
8009                           current_config->name, \
8010                           pipe_config->name); \
8011                 return false; \
8012         }
8013
8014 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8015         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8016                 DRM_ERROR("mismatch in " #name " " \
8017                           "(expected %i, found %i)\n", \
8018                           current_config->name & (mask), \
8019                           pipe_config->name & (mask)); \
8020                 return false; \
8021         }
8022
8023         PIPE_CONF_CHECK_I(cpu_transcoder);
8024
8025         PIPE_CONF_CHECK_I(has_pch_encoder);
8026         PIPE_CONF_CHECK_I(fdi_lanes);
8027         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8028         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8029         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8030         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8031         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8032
8033         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8034         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8035         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8036         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8037         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8038         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8039
8040         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8041         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8042         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8043         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8044         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8045         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8046
8047         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8048                               DRM_MODE_FLAG_INTERLACE);
8049
8050         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8051                               DRM_MODE_FLAG_PHSYNC);
8052         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8053                               DRM_MODE_FLAG_NHSYNC);
8054         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8055                               DRM_MODE_FLAG_PVSYNC);
8056         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8057                               DRM_MODE_FLAG_NVSYNC);
8058
8059         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8060         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8061
8062         PIPE_CONF_CHECK_I(gmch_pfit.control);
8063         /* pfit ratios are autocomputed by the hw on gen4+ */
8064         if (INTEL_INFO(dev)->gen < 4)
8065                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8066         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8067         PIPE_CONF_CHECK_I(pch_pfit.pos);
8068         PIPE_CONF_CHECK_I(pch_pfit.size);
8069
8070         PIPE_CONF_CHECK_I(ips_enabled);
8071
8072 #undef PIPE_CONF_CHECK_I
8073 #undef PIPE_CONF_CHECK_FLAGS
8074
8075         return true;
8076 }
8077
8078 void
8079 intel_modeset_check_state(struct drm_device *dev)
8080 {
8081         drm_i915_private_t *dev_priv = dev->dev_private;
8082         struct intel_crtc *crtc;
8083         struct intel_encoder *encoder;
8084         struct intel_connector *connector;
8085         struct intel_crtc_config pipe_config;
8086
8087         list_for_each_entry(connector, &dev->mode_config.connector_list,
8088                             base.head) {
8089                 /* This also checks the encoder/connector hw state with the
8090                  * ->get_hw_state callbacks. */
8091                 intel_connector_check_state(connector);
8092
8093                 WARN(&connector->new_encoder->base != connector->base.encoder,
8094                      "connector's staged encoder doesn't match current encoder\n");
8095         }
8096
8097         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8098                             base.head) {
8099                 bool enabled = false;
8100                 bool active = false;
8101                 enum pipe pipe, tracked_pipe;
8102
8103                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8104                               encoder->base.base.id,
8105                               drm_get_encoder_name(&encoder->base));
8106
8107                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8108                      "encoder's stage crtc doesn't match current crtc\n");
8109                 WARN(encoder->connectors_active && !encoder->base.crtc,
8110                      "encoder's active_connectors set, but no crtc\n");
8111
8112                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8113                                     base.head) {
8114                         if (connector->base.encoder != &encoder->base)
8115                                 continue;
8116                         enabled = true;
8117                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8118                                 active = true;
8119                 }
8120                 WARN(!!encoder->base.crtc != enabled,
8121                      "encoder's enabled state mismatch "
8122                      "(expected %i, found %i)\n",
8123                      !!encoder->base.crtc, enabled);
8124                 WARN(active && !encoder->base.crtc,
8125                      "active encoder with no crtc\n");
8126
8127                 WARN(encoder->connectors_active != active,
8128                      "encoder's computed active state doesn't match tracked active state "
8129                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8130
8131                 active = encoder->get_hw_state(encoder, &pipe);
8132                 WARN(active != encoder->connectors_active,
8133                      "encoder's hw state doesn't match sw tracking "
8134                      "(expected %i, found %i)\n",
8135                      encoder->connectors_active, active);
8136
8137                 if (!encoder->base.crtc)
8138                         continue;
8139
8140                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8141                 WARN(active && pipe != tracked_pipe,
8142                      "active encoder's pipe doesn't match"
8143                      "(expected %i, found %i)\n",
8144                      tracked_pipe, pipe);
8145
8146         }
8147
8148         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8149                             base.head) {
8150                 bool enabled = false;
8151                 bool active = false;
8152
8153                 memset(&pipe_config, 0, sizeof(pipe_config));
8154
8155                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8156                               crtc->base.base.id);
8157
8158                 WARN(crtc->active && !crtc->base.enabled,
8159                      "active crtc, but not enabled in sw tracking\n");
8160
8161                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8162                                     base.head) {
8163                         if (encoder->base.crtc != &crtc->base)
8164                                 continue;
8165                         enabled = true;
8166                         if (encoder->connectors_active)
8167                                 active = true;
8168                         if (encoder->get_config)
8169                                 encoder->get_config(encoder, &pipe_config);
8170                 }
8171                 WARN(active != crtc->active,
8172                      "crtc's computed active state doesn't match tracked active state "
8173                      "(expected %i, found %i)\n", active, crtc->active);
8174                 WARN(enabled != crtc->base.enabled,
8175                      "crtc's computed enabled state doesn't match tracked enabled state "
8176                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8177
8178                 active = dev_priv->display.get_pipe_config(crtc,
8179                                                            &pipe_config);
8180                 WARN(crtc->active != active,
8181                      "crtc active state doesn't match with hw state "
8182                      "(expected %i, found %i)\n", crtc->active, active);
8183
8184                 if (active &&
8185                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8186                         WARN(1, "pipe state doesn't match!\n");
8187                         intel_dump_pipe_config(crtc, &pipe_config,
8188                                                "[hw state]");
8189                         intel_dump_pipe_config(crtc, &crtc->config,
8190                                                "[sw state]");
8191                 }
8192         }
8193 }
8194
8195 static int __intel_set_mode(struct drm_crtc *crtc,
8196                             struct drm_display_mode *mode,
8197                             int x, int y, struct drm_framebuffer *fb)
8198 {
8199         struct drm_device *dev = crtc->dev;
8200         drm_i915_private_t *dev_priv = dev->dev_private;
8201         struct drm_display_mode *saved_mode, *saved_hwmode;
8202         struct intel_crtc_config *pipe_config = NULL;
8203         struct intel_crtc *intel_crtc;
8204         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8205         int ret = 0;
8206
8207         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8208         if (!saved_mode)
8209                 return -ENOMEM;
8210         saved_hwmode = saved_mode + 1;
8211
8212         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8213                                      &prepare_pipes, &disable_pipes);
8214
8215         *saved_hwmode = crtc->hwmode;
8216         *saved_mode = crtc->mode;
8217
8218         /* Hack: Because we don't (yet) support global modeset on multiple
8219          * crtcs, we don't keep track of the new mode for more than one crtc.
8220          * Hence simply check whether any bit is set in modeset_pipes in all the
8221          * pieces of code that are not yet converted to deal with mutliple crtcs
8222          * changing their mode at the same time. */
8223         if (modeset_pipes) {
8224                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8225                 if (IS_ERR(pipe_config)) {
8226                         ret = PTR_ERR(pipe_config);
8227                         pipe_config = NULL;
8228
8229                         goto out;
8230                 }
8231                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8232                                        "[modeset]");
8233         }
8234
8235         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8236                 intel_crtc_disable(&intel_crtc->base);
8237
8238         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8239                 if (intel_crtc->base.enabled)
8240                         dev_priv->display.crtc_disable(&intel_crtc->base);
8241         }
8242
8243         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8244          * to set it here already despite that we pass it down the callchain.
8245          */
8246         if (modeset_pipes) {
8247                 crtc->mode = *mode;
8248                 /* mode_set/enable/disable functions rely on a correct pipe
8249                  * config. */
8250                 to_intel_crtc(crtc)->config = *pipe_config;
8251         }
8252
8253         /* Only after disabling all output pipelines that will be changed can we
8254          * update the the output configuration. */
8255         intel_modeset_update_state(dev, prepare_pipes);
8256
8257         if (dev_priv->display.modeset_global_resources)
8258                 dev_priv->display.modeset_global_resources(dev);
8259
8260         /* Set up the DPLL and any encoders state that needs to adjust or depend
8261          * on the DPLL.
8262          */
8263         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8264                 ret = intel_crtc_mode_set(&intel_crtc->base,
8265                                           x, y, fb);
8266                 if (ret)
8267                         goto done;
8268         }
8269
8270         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8271         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8272                 dev_priv->display.crtc_enable(&intel_crtc->base);
8273
8274         if (modeset_pipes) {
8275                 /* Store real post-adjustment hardware mode. */
8276                 crtc->hwmode = pipe_config->adjusted_mode;
8277
8278                 /* Calculate and store various constants which
8279                  * are later needed by vblank and swap-completion
8280                  * timestamping. They are derived from true hwmode.
8281                  */
8282                 drm_calc_timestamping_constants(crtc);
8283         }
8284
8285         /* FIXME: add subpixel order */
8286 done:
8287         if (ret && crtc->enabled) {
8288                 crtc->hwmode = *saved_hwmode;
8289                 crtc->mode = *saved_mode;
8290         }
8291
8292 out:
8293         kfree(pipe_config);
8294         kfree(saved_mode);
8295         return ret;
8296 }
8297
8298 int intel_set_mode(struct drm_crtc *crtc,
8299                      struct drm_display_mode *mode,
8300                      int x, int y, struct drm_framebuffer *fb)
8301 {
8302         int ret;
8303
8304         ret = __intel_set_mode(crtc, mode, x, y, fb);
8305
8306         if (ret == 0)
8307                 intel_modeset_check_state(crtc->dev);
8308
8309         return ret;
8310 }
8311
8312 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8313 {
8314         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8315 }
8316
8317 #undef for_each_intel_crtc_masked
8318
8319 static void intel_set_config_free(struct intel_set_config *config)
8320 {
8321         if (!config)
8322                 return;
8323
8324         kfree(config->save_connector_encoders);
8325         kfree(config->save_encoder_crtcs);
8326         kfree(config);
8327 }
8328
8329 static int intel_set_config_save_state(struct drm_device *dev,
8330                                        struct intel_set_config *config)
8331 {
8332         struct drm_encoder *encoder;
8333         struct drm_connector *connector;
8334         int count;
8335
8336         config->save_encoder_crtcs =
8337                 kcalloc(dev->mode_config.num_encoder,
8338                         sizeof(struct drm_crtc *), GFP_KERNEL);
8339         if (!config->save_encoder_crtcs)
8340                 return -ENOMEM;
8341
8342         config->save_connector_encoders =
8343                 kcalloc(dev->mode_config.num_connector,
8344                         sizeof(struct drm_encoder *), GFP_KERNEL);
8345         if (!config->save_connector_encoders)
8346                 return -ENOMEM;
8347
8348         /* Copy data. Note that driver private data is not affected.
8349          * Should anything bad happen only the expected state is
8350          * restored, not the drivers personal bookkeeping.
8351          */
8352         count = 0;
8353         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8354                 config->save_encoder_crtcs[count++] = encoder->crtc;
8355         }
8356
8357         count = 0;
8358         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8359                 config->save_connector_encoders[count++] = connector->encoder;
8360         }
8361
8362         return 0;
8363 }
8364
8365 static void intel_set_config_restore_state(struct drm_device *dev,
8366                                            struct intel_set_config *config)
8367 {
8368         struct intel_encoder *encoder;
8369         struct intel_connector *connector;
8370         int count;
8371
8372         count = 0;
8373         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8374                 encoder->new_crtc =
8375                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8376         }
8377
8378         count = 0;
8379         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8380                 connector->new_encoder =
8381                         to_intel_encoder(config->save_connector_encoders[count++]);
8382         }
8383 }
8384
8385 static bool
8386 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8387                       int num_connectors)
8388 {
8389         int i;
8390
8391         for (i = 0; i < num_connectors; i++)
8392                 if (connectors[i].encoder &&
8393                     connectors[i].encoder->crtc == crtc &&
8394                     connectors[i].dpms != DRM_MODE_DPMS_ON)
8395                         return true;
8396
8397         return false;
8398 }
8399
8400 static void
8401 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8402                                       struct intel_set_config *config)
8403 {
8404
8405         /* We should be able to check here if the fb has the same properties
8406          * and then just flip_or_move it */
8407         if (set->connectors != NULL &&
8408             is_crtc_connector_off(set->crtc, *set->connectors,
8409                                   set->num_connectors)) {
8410                         config->mode_changed = true;
8411         } else if (set->crtc->fb != set->fb) {
8412                 /* If we have no fb then treat it as a full mode set */
8413                 if (set->crtc->fb == NULL) {
8414                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8415                         config->mode_changed = true;
8416                 } else if (set->fb == NULL) {
8417                         config->mode_changed = true;
8418                 } else if (set->fb->pixel_format !=
8419                            set->crtc->fb->pixel_format) {
8420                         config->mode_changed = true;
8421                 } else {
8422                         config->fb_changed = true;
8423                 }
8424         }
8425
8426         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8427                 config->fb_changed = true;
8428
8429         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8430                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8431                 drm_mode_debug_printmodeline(&set->crtc->mode);
8432                 drm_mode_debug_printmodeline(set->mode);
8433                 config->mode_changed = true;
8434         }
8435 }
8436
8437 static int
8438 intel_modeset_stage_output_state(struct drm_device *dev,
8439                                  struct drm_mode_set *set,
8440                                  struct intel_set_config *config)
8441 {
8442         struct drm_crtc *new_crtc;
8443         struct intel_connector *connector;
8444         struct intel_encoder *encoder;
8445         int count, ro;
8446
8447         /* The upper layers ensure that we either disable a crtc or have a list
8448          * of connectors. For paranoia, double-check this. */
8449         WARN_ON(!set->fb && (set->num_connectors != 0));
8450         WARN_ON(set->fb && (set->num_connectors == 0));
8451
8452         count = 0;
8453         list_for_each_entry(connector, &dev->mode_config.connector_list,
8454                             base.head) {
8455                 /* Otherwise traverse passed in connector list and get encoders
8456                  * for them. */
8457                 for (ro = 0; ro < set->num_connectors; ro++) {
8458                         if (set->connectors[ro] == &connector->base) {
8459                                 connector->new_encoder = connector->encoder;
8460                                 break;
8461                         }
8462                 }
8463
8464                 /* If we disable the crtc, disable all its connectors. Also, if
8465                  * the connector is on the changing crtc but not on the new
8466                  * connector list, disable it. */
8467                 if ((!set->fb || ro == set->num_connectors) &&
8468                     connector->base.encoder &&
8469                     connector->base.encoder->crtc == set->crtc) {
8470                         connector->new_encoder = NULL;
8471
8472                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8473                                 connector->base.base.id,
8474                                 drm_get_connector_name(&connector->base));
8475                 }
8476
8477
8478                 if (&connector->new_encoder->base != connector->base.encoder) {
8479                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8480                         config->mode_changed = true;
8481                 }
8482         }
8483         /* connector->new_encoder is now updated for all connectors. */
8484
8485         /* Update crtc of enabled connectors. */
8486         count = 0;
8487         list_for_each_entry(connector, &dev->mode_config.connector_list,
8488                             base.head) {
8489                 if (!connector->new_encoder)
8490                         continue;
8491
8492                 new_crtc = connector->new_encoder->base.crtc;
8493
8494                 for (ro = 0; ro < set->num_connectors; ro++) {
8495                         if (set->connectors[ro] == &connector->base)
8496                                 new_crtc = set->crtc;
8497                 }
8498
8499                 /* Make sure the new CRTC will work with the encoder */
8500                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8501                                            new_crtc)) {
8502                         return -EINVAL;
8503                 }
8504                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8505
8506                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8507                         connector->base.base.id,
8508                         drm_get_connector_name(&connector->base),
8509                         new_crtc->base.id);
8510         }
8511
8512         /* Check for any encoders that needs to be disabled. */
8513         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8514                             base.head) {
8515                 list_for_each_entry(connector,
8516                                     &dev->mode_config.connector_list,
8517                                     base.head) {
8518                         if (connector->new_encoder == encoder) {
8519                                 WARN_ON(!connector->new_encoder->new_crtc);
8520
8521                                 goto next_encoder;
8522                         }
8523                 }
8524                 encoder->new_crtc = NULL;
8525 next_encoder:
8526                 /* Only now check for crtc changes so we don't miss encoders
8527                  * that will be disabled. */
8528                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8529                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8530                         config->mode_changed = true;
8531                 }
8532         }
8533         /* Now we've also updated encoder->new_crtc for all encoders. */
8534
8535         return 0;
8536 }
8537
8538 static int intel_crtc_set_config(struct drm_mode_set *set)
8539 {
8540         struct drm_device *dev;
8541         struct drm_mode_set save_set;
8542         struct intel_set_config *config;
8543         int ret;
8544
8545         BUG_ON(!set);
8546         BUG_ON(!set->crtc);
8547         BUG_ON(!set->crtc->helper_private);
8548
8549         /* Enforce sane interface api - has been abused by the fb helper. */
8550         BUG_ON(!set->mode && set->fb);
8551         BUG_ON(set->fb && set->num_connectors == 0);
8552
8553         if (set->fb) {
8554                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8555                                 set->crtc->base.id, set->fb->base.id,
8556                                 (int)set->num_connectors, set->x, set->y);
8557         } else {
8558                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8559         }
8560
8561         dev = set->crtc->dev;
8562
8563         ret = -ENOMEM;
8564         config = kzalloc(sizeof(*config), GFP_KERNEL);
8565         if (!config)
8566                 goto out_config;
8567
8568         ret = intel_set_config_save_state(dev, config);
8569         if (ret)
8570                 goto out_config;
8571
8572         save_set.crtc = set->crtc;
8573         save_set.mode = &set->crtc->mode;
8574         save_set.x = set->crtc->x;
8575         save_set.y = set->crtc->y;
8576         save_set.fb = set->crtc->fb;
8577
8578         /* Compute whether we need a full modeset, only an fb base update or no
8579          * change at all. In the future we might also check whether only the
8580          * mode changed, e.g. for LVDS where we only change the panel fitter in
8581          * such cases. */
8582         intel_set_config_compute_mode_changes(set, config);
8583
8584         ret = intel_modeset_stage_output_state(dev, set, config);
8585         if (ret)
8586                 goto fail;
8587
8588         if (config->mode_changed) {
8589                 ret = intel_set_mode(set->crtc, set->mode,
8590                                      set->x, set->y, set->fb);
8591         } else if (config->fb_changed) {
8592                 intel_crtc_wait_for_pending_flips(set->crtc);
8593
8594                 ret = intel_pipe_set_base(set->crtc,
8595                                           set->x, set->y, set->fb);
8596         }
8597
8598         if (ret) {
8599                 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8600                           set->crtc->base.id, ret);
8601 fail:
8602                 intel_set_config_restore_state(dev, config);
8603
8604                 /* Try to restore the config */
8605                 if (config->mode_changed &&
8606                     intel_set_mode(save_set.crtc, save_set.mode,
8607                                    save_set.x, save_set.y, save_set.fb))
8608                         DRM_ERROR("failed to restore config after modeset failure\n");
8609         }
8610
8611 out_config:
8612         intel_set_config_free(config);
8613         return ret;
8614 }
8615
8616 static const struct drm_crtc_funcs intel_crtc_funcs = {
8617         .cursor_set = intel_crtc_cursor_set,
8618         .cursor_move = intel_crtc_cursor_move,
8619         .gamma_set = intel_crtc_gamma_set,
8620         .set_config = intel_crtc_set_config,
8621         .destroy = intel_crtc_destroy,
8622         .page_flip = intel_crtc_page_flip,
8623 };
8624
8625 static void intel_cpu_pll_init(struct drm_device *dev)
8626 {
8627         if (HAS_DDI(dev))
8628                 intel_ddi_pll_init(dev);
8629 }
8630
8631 static void intel_pch_pll_init(struct drm_device *dev)
8632 {
8633         drm_i915_private_t *dev_priv = dev->dev_private;
8634         int i;
8635
8636         if (dev_priv->num_pch_pll == 0) {
8637                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8638                 return;
8639         }
8640
8641         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8642                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8643                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8644                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8645         }
8646 }
8647
8648 static void intel_crtc_init(struct drm_device *dev, int pipe)
8649 {
8650         drm_i915_private_t *dev_priv = dev->dev_private;
8651         struct intel_crtc *intel_crtc;
8652         int i;
8653
8654         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8655         if (intel_crtc == NULL)
8656                 return;
8657
8658         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8659
8660         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8661         for (i = 0; i < 256; i++) {
8662                 intel_crtc->lut_r[i] = i;
8663                 intel_crtc->lut_g[i] = i;
8664                 intel_crtc->lut_b[i] = i;
8665         }
8666
8667         /* Swap pipes & planes for FBC on pre-965 */
8668         intel_crtc->pipe = pipe;
8669         intel_crtc->plane = pipe;
8670         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8671                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8672                 intel_crtc->plane = !pipe;
8673         }
8674
8675         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8676                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8677         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8678         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8679
8680         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8681 }
8682
8683 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8684                                 struct drm_file *file)
8685 {
8686         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8687         struct drm_mode_object *drmmode_obj;
8688         struct intel_crtc *crtc;
8689
8690         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8691                 return -ENODEV;
8692
8693         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8694                         DRM_MODE_OBJECT_CRTC);
8695
8696         if (!drmmode_obj) {
8697                 DRM_ERROR("no such CRTC id\n");
8698                 return -EINVAL;
8699         }
8700
8701         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8702         pipe_from_crtc_id->pipe = crtc->pipe;
8703
8704         return 0;
8705 }
8706
8707 static int intel_encoder_clones(struct intel_encoder *encoder)
8708 {
8709         struct drm_device *dev = encoder->base.dev;
8710         struct intel_encoder *source_encoder;
8711         int index_mask = 0;
8712         int entry = 0;
8713
8714         list_for_each_entry(source_encoder,
8715                             &dev->mode_config.encoder_list, base.head) {
8716
8717                 if (encoder == source_encoder)
8718                         index_mask |= (1 << entry);
8719
8720                 /* Intel hw has only one MUX where enocoders could be cloned. */
8721                 if (encoder->cloneable && source_encoder->cloneable)
8722                         index_mask |= (1 << entry);
8723
8724                 entry++;
8725         }
8726
8727         return index_mask;
8728 }
8729
8730 static bool has_edp_a(struct drm_device *dev)
8731 {
8732         struct drm_i915_private *dev_priv = dev->dev_private;
8733
8734         if (!IS_MOBILE(dev))
8735                 return false;
8736
8737         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8738                 return false;
8739
8740         if (IS_GEN5(dev) &&
8741             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8742                 return false;
8743
8744         return true;
8745 }
8746
8747 static void intel_setup_outputs(struct drm_device *dev)
8748 {
8749         struct drm_i915_private *dev_priv = dev->dev_private;
8750         struct intel_encoder *encoder;
8751         bool dpd_is_edp = false;
8752         bool has_lvds;
8753
8754         has_lvds = intel_lvds_init(dev);
8755         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8756                 /* disable the panel fitter on everything but LVDS */
8757                 I915_WRITE(PFIT_CONTROL, 0);
8758         }
8759
8760         if (!IS_ULT(dev))
8761                 intel_crt_init(dev);
8762
8763         if (HAS_DDI(dev)) {
8764                 int found;
8765
8766                 /* Haswell uses DDI functions to detect digital outputs */
8767                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8768                 /* DDI A only supports eDP */
8769                 if (found)
8770                         intel_ddi_init(dev, PORT_A);
8771
8772                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8773                  * register */
8774                 found = I915_READ(SFUSE_STRAP);
8775
8776                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8777                         intel_ddi_init(dev, PORT_B);
8778                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8779                         intel_ddi_init(dev, PORT_C);
8780                 if (found & SFUSE_STRAP_DDID_DETECTED)
8781                         intel_ddi_init(dev, PORT_D);
8782         } else if (HAS_PCH_SPLIT(dev)) {
8783                 int found;
8784                 dpd_is_edp = intel_dpd_is_edp(dev);
8785
8786                 if (has_edp_a(dev))
8787                         intel_dp_init(dev, DP_A, PORT_A);
8788
8789                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8790                         /* PCH SDVOB multiplex with HDMIB */
8791                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8792                         if (!found)
8793                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8794                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8795                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8796                 }
8797
8798                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8799                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8800
8801                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8802                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8803
8804                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8805                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8806
8807                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8808                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8809         } else if (IS_VALLEYVIEW(dev)) {
8810                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8811                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8812                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8813
8814                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8815                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8816                                         PORT_B);
8817                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8818                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8819                 }
8820         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8821                 bool found = false;
8822
8823                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8824                         DRM_DEBUG_KMS("probing SDVOB\n");
8825                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8826                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8827                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8828                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8829                         }
8830
8831                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
8832                                 intel_dp_init(dev, DP_B, PORT_B);
8833                 }
8834
8835                 /* Before G4X SDVOC doesn't have its own detect register */
8836
8837                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8838                         DRM_DEBUG_KMS("probing SDVOC\n");
8839                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8840                 }
8841
8842                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8843
8844                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8845                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8846                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8847                         }
8848                         if (SUPPORTS_INTEGRATED_DP(dev))
8849                                 intel_dp_init(dev, DP_C, PORT_C);
8850                 }
8851
8852                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8853                     (I915_READ(DP_D) & DP_DETECTED))
8854                         intel_dp_init(dev, DP_D, PORT_D);
8855         } else if (IS_GEN2(dev))
8856                 intel_dvo_init(dev);
8857
8858         if (SUPPORTS_TV(dev))
8859                 intel_tv_init(dev);
8860
8861         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8862                 encoder->base.possible_crtcs = encoder->crtc_mask;
8863                 encoder->base.possible_clones =
8864                         intel_encoder_clones(encoder);
8865         }
8866
8867         intel_init_pch_refclk(dev);
8868
8869         drm_helper_move_panel_connectors_to_head(dev);
8870 }
8871
8872 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8873 {
8874         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8875
8876         drm_framebuffer_cleanup(fb);
8877         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8878
8879         kfree(intel_fb);
8880 }
8881
8882 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8883                                                 struct drm_file *file,
8884                                                 unsigned int *handle)
8885 {
8886         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8887         struct drm_i915_gem_object *obj = intel_fb->obj;
8888
8889         return drm_gem_handle_create(file, &obj->base, handle);
8890 }
8891
8892 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8893         .destroy = intel_user_framebuffer_destroy,
8894         .create_handle = intel_user_framebuffer_create_handle,
8895 };
8896
8897 int intel_framebuffer_init(struct drm_device *dev,
8898                            struct intel_framebuffer *intel_fb,
8899                            struct drm_mode_fb_cmd2 *mode_cmd,
8900                            struct drm_i915_gem_object *obj)
8901 {
8902         int ret;
8903
8904         if (obj->tiling_mode == I915_TILING_Y) {
8905                 DRM_DEBUG("hardware does not support tiling Y\n");
8906                 return -EINVAL;
8907         }
8908
8909         if (mode_cmd->pitches[0] & 63) {
8910                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8911                           mode_cmd->pitches[0]);
8912                 return -EINVAL;
8913         }
8914
8915         /* FIXME <= Gen4 stride limits are bit unclear */
8916         if (mode_cmd->pitches[0] > 32768) {
8917                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8918                           mode_cmd->pitches[0]);
8919                 return -EINVAL;
8920         }
8921
8922         if (obj->tiling_mode != I915_TILING_NONE &&
8923             mode_cmd->pitches[0] != obj->stride) {
8924                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8925                           mode_cmd->pitches[0], obj->stride);
8926                 return -EINVAL;
8927         }
8928
8929         /* Reject formats not supported by any plane early. */
8930         switch (mode_cmd->pixel_format) {
8931         case DRM_FORMAT_C8:
8932         case DRM_FORMAT_RGB565:
8933         case DRM_FORMAT_XRGB8888:
8934         case DRM_FORMAT_ARGB8888:
8935                 break;
8936         case DRM_FORMAT_XRGB1555:
8937         case DRM_FORMAT_ARGB1555:
8938                 if (INTEL_INFO(dev)->gen > 3) {
8939                         DRM_DEBUG("unsupported pixel format: %s\n",
8940                                   drm_get_format_name(mode_cmd->pixel_format));
8941                         return -EINVAL;
8942                 }
8943                 break;
8944         case DRM_FORMAT_XBGR8888:
8945         case DRM_FORMAT_ABGR8888:
8946         case DRM_FORMAT_XRGB2101010:
8947         case DRM_FORMAT_ARGB2101010:
8948         case DRM_FORMAT_XBGR2101010:
8949         case DRM_FORMAT_ABGR2101010:
8950                 if (INTEL_INFO(dev)->gen < 4) {
8951                         DRM_DEBUG("unsupported pixel format: %s\n",
8952                                   drm_get_format_name(mode_cmd->pixel_format));
8953                         return -EINVAL;
8954                 }
8955                 break;
8956         case DRM_FORMAT_YUYV:
8957         case DRM_FORMAT_UYVY:
8958         case DRM_FORMAT_YVYU:
8959         case DRM_FORMAT_VYUY:
8960                 if (INTEL_INFO(dev)->gen < 5) {
8961                         DRM_DEBUG("unsupported pixel format: %s\n",
8962                                   drm_get_format_name(mode_cmd->pixel_format));
8963                         return -EINVAL;
8964                 }
8965                 break;
8966         default:
8967                 DRM_DEBUG("unsupported pixel format: %s\n",
8968                           drm_get_format_name(mode_cmd->pixel_format));
8969                 return -EINVAL;
8970         }
8971
8972         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8973         if (mode_cmd->offsets[0] != 0)
8974                 return -EINVAL;
8975
8976         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8977         intel_fb->obj = obj;
8978
8979         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8980         if (ret) {
8981                 DRM_ERROR("framebuffer init failed %d\n", ret);
8982                 return ret;
8983         }
8984
8985         return 0;
8986 }
8987
8988 static struct drm_framebuffer *
8989 intel_user_framebuffer_create(struct drm_device *dev,
8990                               struct drm_file *filp,
8991                               struct drm_mode_fb_cmd2 *mode_cmd)
8992 {
8993         struct drm_i915_gem_object *obj;
8994
8995         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8996                                                 mode_cmd->handles[0]));
8997         if (&obj->base == NULL)
8998                 return ERR_PTR(-ENOENT);
8999
9000         return intel_framebuffer_create(dev, mode_cmd, obj);
9001 }
9002
9003 static const struct drm_mode_config_funcs intel_mode_funcs = {
9004         .fb_create = intel_user_framebuffer_create,
9005         .output_poll_changed = intel_fb_output_poll_changed,
9006 };
9007
9008 /* Set up chip specific display functions */
9009 static void intel_init_display(struct drm_device *dev)
9010 {
9011         struct drm_i915_private *dev_priv = dev->dev_private;
9012
9013         if (HAS_DDI(dev)) {
9014                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9015                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9016                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9017                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9018                 dev_priv->display.off = haswell_crtc_off;
9019                 dev_priv->display.update_plane = ironlake_update_plane;
9020         } else if (HAS_PCH_SPLIT(dev)) {
9021                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9022                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9023                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9024                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9025                 dev_priv->display.off = ironlake_crtc_off;
9026                 dev_priv->display.update_plane = ironlake_update_plane;
9027         } else if (IS_VALLEYVIEW(dev)) {
9028                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9029                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9030                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9031                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9032                 dev_priv->display.off = i9xx_crtc_off;
9033                 dev_priv->display.update_plane = i9xx_update_plane;
9034         } else {
9035                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9036                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9037                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9038                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9039                 dev_priv->display.off = i9xx_crtc_off;
9040                 dev_priv->display.update_plane = i9xx_update_plane;
9041         }
9042
9043         /* Returns the core display clock speed */
9044         if (IS_VALLEYVIEW(dev))
9045                 dev_priv->display.get_display_clock_speed =
9046                         valleyview_get_display_clock_speed;
9047         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9048                 dev_priv->display.get_display_clock_speed =
9049                         i945_get_display_clock_speed;
9050         else if (IS_I915G(dev))
9051                 dev_priv->display.get_display_clock_speed =
9052                         i915_get_display_clock_speed;
9053         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9054                 dev_priv->display.get_display_clock_speed =
9055                         i9xx_misc_get_display_clock_speed;
9056         else if (IS_I915GM(dev))
9057                 dev_priv->display.get_display_clock_speed =
9058                         i915gm_get_display_clock_speed;
9059         else if (IS_I865G(dev))
9060                 dev_priv->display.get_display_clock_speed =
9061                         i865_get_display_clock_speed;
9062         else if (IS_I85X(dev))
9063                 dev_priv->display.get_display_clock_speed =
9064                         i855_get_display_clock_speed;
9065         else /* 852, 830 */
9066                 dev_priv->display.get_display_clock_speed =
9067                         i830_get_display_clock_speed;
9068
9069         if (HAS_PCH_SPLIT(dev)) {
9070                 if (IS_GEN5(dev)) {
9071                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9072                         dev_priv->display.write_eld = ironlake_write_eld;
9073                 } else if (IS_GEN6(dev)) {
9074                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9075                         dev_priv->display.write_eld = ironlake_write_eld;
9076                 } else if (IS_IVYBRIDGE(dev)) {
9077                         /* FIXME: detect B0+ stepping and use auto training */
9078                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9079                         dev_priv->display.write_eld = ironlake_write_eld;
9080                         dev_priv->display.modeset_global_resources =
9081                                 ivb_modeset_global_resources;
9082                 } else if (IS_HASWELL(dev)) {
9083                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9084                         dev_priv->display.write_eld = haswell_write_eld;
9085                         dev_priv->display.modeset_global_resources =
9086                                 haswell_modeset_global_resources;
9087                 }
9088         } else if (IS_G4X(dev)) {
9089                 dev_priv->display.write_eld = g4x_write_eld;
9090         }
9091
9092         /* Default just returns -ENODEV to indicate unsupported */
9093         dev_priv->display.queue_flip = intel_default_queue_flip;
9094
9095         switch (INTEL_INFO(dev)->gen) {
9096         case 2:
9097                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9098                 break;
9099
9100         case 3:
9101                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9102                 break;
9103
9104         case 4:
9105         case 5:
9106                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9107                 break;
9108
9109         case 6:
9110                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9111                 break;
9112         case 7:
9113                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9114                 break;
9115         }
9116 }
9117
9118 /*
9119  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9120  * resume, or other times.  This quirk makes sure that's the case for
9121  * affected systems.
9122  */
9123 static void quirk_pipea_force(struct drm_device *dev)
9124 {
9125         struct drm_i915_private *dev_priv = dev->dev_private;
9126
9127         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9128         DRM_INFO("applying pipe a force quirk\n");
9129 }
9130
9131 /*
9132  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9133  */
9134 static void quirk_ssc_force_disable(struct drm_device *dev)
9135 {
9136         struct drm_i915_private *dev_priv = dev->dev_private;
9137         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9138         DRM_INFO("applying lvds SSC disable quirk\n");
9139 }
9140
9141 /*
9142  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9143  * brightness value
9144  */
9145 static void quirk_invert_brightness(struct drm_device *dev)
9146 {
9147         struct drm_i915_private *dev_priv = dev->dev_private;
9148         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9149         DRM_INFO("applying inverted panel brightness quirk\n");
9150 }
9151
9152 struct intel_quirk {
9153         int device;
9154         int subsystem_vendor;
9155         int subsystem_device;
9156         void (*hook)(struct drm_device *dev);
9157 };
9158
9159 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9160 struct intel_dmi_quirk {
9161         void (*hook)(struct drm_device *dev);
9162         const struct dmi_system_id (*dmi_id_list)[];
9163 };
9164
9165 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9166 {
9167         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9168         return 1;
9169 }
9170
9171 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9172         {
9173                 .dmi_id_list = &(const struct dmi_system_id[]) {
9174                         {
9175                                 .callback = intel_dmi_reverse_brightness,
9176                                 .ident = "NCR Corporation",
9177                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9178                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9179                                 },
9180                         },
9181                         { }  /* terminating entry */
9182                 },
9183                 .hook = quirk_invert_brightness,
9184         },
9185 };
9186
9187 static struct intel_quirk intel_quirks[] = {
9188         /* HP Mini needs pipe A force quirk (LP: #322104) */
9189         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9190
9191         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9192         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9193
9194         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9195         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9196
9197         /* 830/845 need to leave pipe A & dpll A up */
9198         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9199         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9200
9201         /* Lenovo U160 cannot use SSC on LVDS */
9202         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9203
9204         /* Sony Vaio Y cannot use SSC on LVDS */
9205         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9206
9207         /* Acer Aspire 5734Z must invert backlight brightness */
9208         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9209
9210         /* Acer/eMachines G725 */
9211         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9212
9213         /* Acer/eMachines e725 */
9214         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9215
9216         /* Acer/Packard Bell NCL20 */
9217         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9218
9219         /* Acer Aspire 4736Z */
9220         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9221 };
9222
9223 static void intel_init_quirks(struct drm_device *dev)
9224 {
9225         struct pci_dev *d = dev->pdev;
9226         int i;
9227
9228         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9229                 struct intel_quirk *q = &intel_quirks[i];
9230
9231                 if (d->device == q->device &&
9232                     (d->subsystem_vendor == q->subsystem_vendor ||
9233                      q->subsystem_vendor == PCI_ANY_ID) &&
9234                     (d->subsystem_device == q->subsystem_device ||
9235                      q->subsystem_device == PCI_ANY_ID))
9236                         q->hook(dev);
9237         }
9238         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9239                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9240                         intel_dmi_quirks[i].hook(dev);
9241         }
9242 }
9243
9244 /* Disable the VGA plane that we never use */
9245 static void i915_disable_vga(struct drm_device *dev)
9246 {
9247         struct drm_i915_private *dev_priv = dev->dev_private;
9248         u8 sr1;
9249         u32 vga_reg = i915_vgacntrl_reg(dev);
9250
9251         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9252         outb(SR01, VGA_SR_INDEX);
9253         sr1 = inb(VGA_SR_DATA);
9254         outb(sr1 | 1<<5, VGA_SR_DATA);
9255         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9256         udelay(300);
9257
9258         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9259         POSTING_READ(vga_reg);
9260 }
9261
9262 void intel_modeset_init_hw(struct drm_device *dev)
9263 {
9264         intel_init_power_well(dev);
9265
9266         intel_prepare_ddi(dev);
9267
9268         intel_init_clock_gating(dev);
9269
9270         mutex_lock(&dev->struct_mutex);
9271         intel_enable_gt_powersave(dev);
9272         mutex_unlock(&dev->struct_mutex);
9273 }
9274
9275 void intel_modeset_suspend_hw(struct drm_device *dev)
9276 {
9277         intel_suspend_hw(dev);
9278 }
9279
9280 void intel_modeset_init(struct drm_device *dev)
9281 {
9282         struct drm_i915_private *dev_priv = dev->dev_private;
9283         int i, j, ret;
9284
9285         drm_mode_config_init(dev);
9286
9287         dev->mode_config.min_width = 0;
9288         dev->mode_config.min_height = 0;
9289
9290         dev->mode_config.preferred_depth = 24;
9291         dev->mode_config.prefer_shadow = 1;
9292
9293         dev->mode_config.funcs = &intel_mode_funcs;
9294
9295         intel_init_quirks(dev);
9296
9297         intel_init_pm(dev);
9298
9299         if (INTEL_INFO(dev)->num_pipes == 0)
9300                 return;
9301
9302         intel_init_display(dev);
9303
9304         if (IS_GEN2(dev)) {
9305                 dev->mode_config.max_width = 2048;
9306                 dev->mode_config.max_height = 2048;
9307         } else if (IS_GEN3(dev)) {
9308                 dev->mode_config.max_width = 4096;
9309                 dev->mode_config.max_height = 4096;
9310         } else {
9311                 dev->mode_config.max_width = 8192;
9312                 dev->mode_config.max_height = 8192;
9313         }
9314         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9315
9316         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9317                       INTEL_INFO(dev)->num_pipes,
9318                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9319
9320         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9321                 intel_crtc_init(dev, i);
9322                 for (j = 0; j < dev_priv->num_plane; j++) {
9323                         ret = intel_plane_init(dev, i, j);
9324                         if (ret)
9325                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9326                                               pipe_name(i), sprite_name(i, j), ret);
9327                 }
9328         }
9329
9330         intel_cpu_pll_init(dev);
9331         intel_pch_pll_init(dev);
9332
9333         /* Just disable it once at startup */
9334         i915_disable_vga(dev);
9335         intel_setup_outputs(dev);
9336
9337         /* Just in case the BIOS is doing something questionable. */
9338         intel_disable_fbc(dev);
9339 }
9340
9341 static void
9342 intel_connector_break_all_links(struct intel_connector *connector)
9343 {
9344         connector->base.dpms = DRM_MODE_DPMS_OFF;
9345         connector->base.encoder = NULL;
9346         connector->encoder->connectors_active = false;
9347         connector->encoder->base.crtc = NULL;
9348 }
9349
9350 static void intel_enable_pipe_a(struct drm_device *dev)
9351 {
9352         struct intel_connector *connector;
9353         struct drm_connector *crt = NULL;
9354         struct intel_load_detect_pipe load_detect_temp;
9355
9356         /* We can't just switch on the pipe A, we need to set things up with a
9357          * proper mode and output configuration. As a gross hack, enable pipe A
9358          * by enabling the load detect pipe once. */
9359         list_for_each_entry(connector,
9360                             &dev->mode_config.connector_list,
9361                             base.head) {
9362                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9363                         crt = &connector->base;
9364                         break;
9365                 }
9366         }
9367
9368         if (!crt)
9369                 return;
9370
9371         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9372                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9373
9374
9375 }
9376
9377 static bool
9378 intel_check_plane_mapping(struct intel_crtc *crtc)
9379 {
9380         struct drm_device *dev = crtc->base.dev;
9381         struct drm_i915_private *dev_priv = dev->dev_private;
9382         u32 reg, val;
9383
9384         if (INTEL_INFO(dev)->num_pipes == 1)
9385                 return true;
9386
9387         reg = DSPCNTR(!crtc->plane);
9388         val = I915_READ(reg);
9389
9390         if ((val & DISPLAY_PLANE_ENABLE) &&
9391             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9392                 return false;
9393
9394         return true;
9395 }
9396
9397 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9398 {
9399         struct drm_device *dev = crtc->base.dev;
9400         struct drm_i915_private *dev_priv = dev->dev_private;
9401         u32 reg;
9402
9403         /* Clear any frame start delays used for debugging left by the BIOS */
9404         reg = PIPECONF(crtc->config.cpu_transcoder);
9405         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9406
9407         /* We need to sanitize the plane -> pipe mapping first because this will
9408          * disable the crtc (and hence change the state) if it is wrong. Note
9409          * that gen4+ has a fixed plane -> pipe mapping.  */
9410         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9411                 struct intel_connector *connector;
9412                 bool plane;
9413
9414                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9415                               crtc->base.base.id);
9416
9417                 /* Pipe has the wrong plane attached and the plane is active.
9418                  * Temporarily change the plane mapping and disable everything
9419                  * ...  */
9420                 plane = crtc->plane;
9421                 crtc->plane = !plane;
9422                 dev_priv->display.crtc_disable(&crtc->base);
9423                 crtc->plane = plane;
9424
9425                 /* ... and break all links. */
9426                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9427                                     base.head) {
9428                         if (connector->encoder->base.crtc != &crtc->base)
9429                                 continue;
9430
9431                         intel_connector_break_all_links(connector);
9432                 }
9433
9434                 WARN_ON(crtc->active);
9435                 crtc->base.enabled = false;
9436         }
9437
9438         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9439             crtc->pipe == PIPE_A && !crtc->active) {
9440                 /* BIOS forgot to enable pipe A, this mostly happens after
9441                  * resume. Force-enable the pipe to fix this, the update_dpms
9442                  * call below we restore the pipe to the right state, but leave
9443                  * the required bits on. */
9444                 intel_enable_pipe_a(dev);
9445         }
9446
9447         /* Adjust the state of the output pipe according to whether we
9448          * have active connectors/encoders. */
9449         intel_crtc_update_dpms(&crtc->base);
9450
9451         if (crtc->active != crtc->base.enabled) {
9452                 struct intel_encoder *encoder;
9453
9454                 /* This can happen either due to bugs in the get_hw_state
9455                  * functions or because the pipe is force-enabled due to the
9456                  * pipe A quirk. */
9457                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9458                               crtc->base.base.id,
9459                               crtc->base.enabled ? "enabled" : "disabled",
9460                               crtc->active ? "enabled" : "disabled");
9461
9462                 crtc->base.enabled = crtc->active;
9463
9464                 /* Because we only establish the connector -> encoder ->
9465                  * crtc links if something is active, this means the
9466                  * crtc is now deactivated. Break the links. connector
9467                  * -> encoder links are only establish when things are
9468                  *  actually up, hence no need to break them. */
9469                 WARN_ON(crtc->active);
9470
9471                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9472                         WARN_ON(encoder->connectors_active);
9473                         encoder->base.crtc = NULL;
9474                 }
9475         }
9476 }
9477
9478 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9479 {
9480         struct intel_connector *connector;
9481         struct drm_device *dev = encoder->base.dev;
9482
9483         /* We need to check both for a crtc link (meaning that the
9484          * encoder is active and trying to read from a pipe) and the
9485          * pipe itself being active. */
9486         bool has_active_crtc = encoder->base.crtc &&
9487                 to_intel_crtc(encoder->base.crtc)->active;
9488
9489         if (encoder->connectors_active && !has_active_crtc) {
9490                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9491                               encoder->base.base.id,
9492                               drm_get_encoder_name(&encoder->base));
9493
9494                 /* Connector is active, but has no active pipe. This is
9495                  * fallout from our resume register restoring. Disable
9496                  * the encoder manually again. */
9497                 if (encoder->base.crtc) {
9498                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9499                                       encoder->base.base.id,
9500                                       drm_get_encoder_name(&encoder->base));
9501                         encoder->disable(encoder);
9502                 }
9503
9504                 /* Inconsistent output/port/pipe state happens presumably due to
9505                  * a bug in one of the get_hw_state functions. Or someplace else
9506                  * in our code, like the register restore mess on resume. Clamp
9507                  * things to off as a safer default. */
9508                 list_for_each_entry(connector,
9509                                     &dev->mode_config.connector_list,
9510                                     base.head) {
9511                         if (connector->encoder != encoder)
9512                                 continue;
9513
9514                         intel_connector_break_all_links(connector);
9515                 }
9516         }
9517         /* Enabled encoders without active connectors will be fixed in
9518          * the crtc fixup. */
9519 }
9520
9521 void i915_redisable_vga(struct drm_device *dev)
9522 {
9523         struct drm_i915_private *dev_priv = dev->dev_private;
9524         u32 vga_reg = i915_vgacntrl_reg(dev);
9525
9526         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9527                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9528                 i915_disable_vga(dev);
9529         }
9530 }
9531
9532 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9533  * and i915 state tracking structures. */
9534 void intel_modeset_setup_hw_state(struct drm_device *dev,
9535                                   bool force_restore)
9536 {
9537         struct drm_i915_private *dev_priv = dev->dev_private;
9538         enum pipe pipe;
9539         struct drm_plane *plane;
9540         struct intel_crtc *crtc;
9541         struct intel_encoder *encoder;
9542         struct intel_connector *connector;
9543
9544         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9545                             base.head) {
9546                 memset(&crtc->config, 0, sizeof(crtc->config));
9547
9548                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9549                                                                  &crtc->config);
9550
9551                 crtc->base.enabled = crtc->active;
9552
9553                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9554                               crtc->base.base.id,
9555                               crtc->active ? "enabled" : "disabled");
9556         }
9557
9558         if (HAS_DDI(dev))
9559                 intel_ddi_setup_hw_pll_state(dev);
9560
9561         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9562                             base.head) {
9563                 pipe = 0;
9564
9565                 if (encoder->get_hw_state(encoder, &pipe)) {
9566                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9567                         encoder->base.crtc = &crtc->base;
9568                         if (encoder->get_config)
9569                                 encoder->get_config(encoder, &crtc->config);
9570                 } else {
9571                         encoder->base.crtc = NULL;
9572                 }
9573
9574                 encoder->connectors_active = false;
9575                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9576                               encoder->base.base.id,
9577                               drm_get_encoder_name(&encoder->base),
9578                               encoder->base.crtc ? "enabled" : "disabled",
9579                               pipe);
9580         }
9581
9582         list_for_each_entry(connector, &dev->mode_config.connector_list,
9583                             base.head) {
9584                 if (connector->get_hw_state(connector)) {
9585                         connector->base.dpms = DRM_MODE_DPMS_ON;
9586                         connector->encoder->connectors_active = true;
9587                         connector->base.encoder = &connector->encoder->base;
9588                 } else {
9589                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9590                         connector->base.encoder = NULL;
9591                 }
9592                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9593                               connector->base.base.id,
9594                               drm_get_connector_name(&connector->base),
9595                               connector->base.encoder ? "enabled" : "disabled");
9596         }
9597
9598         /* HW state is read out, now we need to sanitize this mess. */
9599         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9600                             base.head) {
9601                 intel_sanitize_encoder(encoder);
9602         }
9603
9604         for_each_pipe(pipe) {
9605                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9606                 intel_sanitize_crtc(crtc);
9607                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9608         }
9609
9610         if (force_restore) {
9611                 /*
9612                  * We need to use raw interfaces for restoring state to avoid
9613                  * checking (bogus) intermediate states.
9614                  */
9615                 for_each_pipe(pipe) {
9616                         struct drm_crtc *crtc =
9617                                 dev_priv->pipe_to_crtc_mapping[pipe];
9618
9619                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9620                                          crtc->fb);
9621                 }
9622                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9623                         intel_plane_restore(plane);
9624
9625                 i915_redisable_vga(dev);
9626         } else {
9627                 intel_modeset_update_staged_output_state(dev);
9628         }
9629
9630         intel_modeset_check_state(dev);
9631
9632         drm_mode_config_reset(dev);
9633 }
9634
9635 void intel_modeset_gem_init(struct drm_device *dev)
9636 {
9637         intel_modeset_init_hw(dev);
9638
9639         intel_setup_overlay(dev);
9640
9641         intel_modeset_setup_hw_state(dev, false);
9642 }
9643
9644 void intel_modeset_cleanup(struct drm_device *dev)
9645 {
9646         struct drm_i915_private *dev_priv = dev->dev_private;
9647         struct drm_crtc *crtc;
9648         struct intel_crtc *intel_crtc;
9649
9650         /*
9651          * Interrupts and polling as the first thing to avoid creating havoc.
9652          * Too much stuff here (turning of rps, connectors, ...) would
9653          * experience fancy races otherwise.
9654          */
9655         drm_irq_uninstall(dev);
9656         cancel_work_sync(&dev_priv->hotplug_work);
9657         /*
9658          * Due to the hpd irq storm handling the hotplug work can re-arm the
9659          * poll handlers. Hence disable polling after hpd handling is shut down.
9660          */
9661         drm_kms_helper_poll_fini(dev);
9662
9663         mutex_lock(&dev->struct_mutex);
9664
9665         intel_unregister_dsm_handler();
9666
9667         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9668                 /* Skip inactive CRTCs */
9669                 if (!crtc->fb)
9670                         continue;
9671
9672                 intel_crtc = to_intel_crtc(crtc);
9673                 intel_increase_pllclock(crtc);
9674         }
9675
9676         intel_disable_fbc(dev);
9677
9678         intel_disable_gt_powersave(dev);
9679
9680         ironlake_teardown_rc6(dev);
9681
9682         mutex_unlock(&dev->struct_mutex);
9683
9684         /* flush any delayed tasks or pending work */
9685         flush_scheduled_work();
9686
9687         /* destroy backlight, if any, before the connectors */
9688         intel_panel_destroy_backlight(dev);
9689
9690         drm_mode_config_cleanup(dev);
9691
9692         intel_cleanup_overlay(dev);
9693 }
9694
9695 /*
9696  * Return which encoder is currently attached for connector.
9697  */
9698 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9699 {
9700         return &intel_attached_encoder(connector)->base;
9701 }
9702
9703 void intel_connector_attach_encoder(struct intel_connector *connector,
9704                                     struct intel_encoder *encoder)
9705 {
9706         connector->encoder = encoder;
9707         drm_mode_connector_attach_encoder(&connector->base,
9708                                           &encoder->base);
9709 }
9710
9711 /*
9712  * set vga decode state - true == enable VGA decode
9713  */
9714 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9715 {
9716         struct drm_i915_private *dev_priv = dev->dev_private;
9717         u16 gmch_ctrl;
9718
9719         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9720         if (state)
9721                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9722         else
9723                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9724         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9725         return 0;
9726 }
9727
9728 #ifdef CONFIG_DEBUG_FS
9729 #include <linux/seq_file.h>
9730
9731 struct intel_display_error_state {
9732
9733         u32 power_well_driver;
9734
9735         struct intel_cursor_error_state {
9736                 u32 control;
9737                 u32 position;
9738                 u32 base;
9739                 u32 size;
9740         } cursor[I915_MAX_PIPES];
9741
9742         struct intel_pipe_error_state {
9743                 enum transcoder cpu_transcoder;
9744                 u32 conf;
9745                 u32 source;
9746
9747                 u32 htotal;
9748                 u32 hblank;
9749                 u32 hsync;
9750                 u32 vtotal;
9751                 u32 vblank;
9752                 u32 vsync;
9753         } pipe[I915_MAX_PIPES];
9754
9755         struct intel_plane_error_state {
9756                 u32 control;
9757                 u32 stride;
9758                 u32 size;
9759                 u32 pos;
9760                 u32 addr;
9761                 u32 surface;
9762                 u32 tile_offset;
9763         } plane[I915_MAX_PIPES];
9764 };
9765
9766 struct intel_display_error_state *
9767 intel_display_capture_error_state(struct drm_device *dev)
9768 {
9769         drm_i915_private_t *dev_priv = dev->dev_private;
9770         struct intel_display_error_state *error;
9771         enum transcoder cpu_transcoder;
9772         int i;
9773
9774         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9775         if (error == NULL)
9776                 return NULL;
9777
9778         if (HAS_POWER_WELL(dev))
9779                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9780
9781         for_each_pipe(i) {
9782                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9783                 error->pipe[i].cpu_transcoder = cpu_transcoder;
9784
9785                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9786                         error->cursor[i].control = I915_READ(CURCNTR(i));
9787                         error->cursor[i].position = I915_READ(CURPOS(i));
9788                         error->cursor[i].base = I915_READ(CURBASE(i));
9789                 } else {
9790                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9791                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9792                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9793                 }
9794
9795                 error->plane[i].control = I915_READ(DSPCNTR(i));
9796                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9797                 if (INTEL_INFO(dev)->gen <= 3) {
9798                         error->plane[i].size = I915_READ(DSPSIZE(i));
9799                         error->plane[i].pos = I915_READ(DSPPOS(i));
9800                 }
9801                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9802                         error->plane[i].addr = I915_READ(DSPADDR(i));
9803                 if (INTEL_INFO(dev)->gen >= 4) {
9804                         error->plane[i].surface = I915_READ(DSPSURF(i));
9805                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9806                 }
9807
9808                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9809                 error->pipe[i].source = I915_READ(PIPESRC(i));
9810                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9811                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9812                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9813                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9814                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9815                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9816         }
9817
9818         /* In the code above we read the registers without checking if the power
9819          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9820          * prevent the next I915_WRITE from detecting it and printing an error
9821          * message. */
9822         if (HAS_POWER_WELL(dev))
9823                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9824
9825         return error;
9826 }
9827
9828 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9829
9830 void
9831 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
9832                                 struct drm_device *dev,
9833                                 struct intel_display_error_state *error)
9834 {
9835         int i;
9836
9837         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9838         if (HAS_POWER_WELL(dev))
9839                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
9840                            error->power_well_driver);
9841         for_each_pipe(i) {
9842                 err_printf(m, "Pipe [%d]:\n", i);
9843                 err_printf(m, "  CPU transcoder: %c\n",
9844                            transcoder_name(error->pipe[i].cpu_transcoder));
9845                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9846                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9847                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9848                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9849                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9850                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9851                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9852                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9853
9854                 err_printf(m, "Plane [%d]:\n", i);
9855                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9856                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9857                 if (INTEL_INFO(dev)->gen <= 3) {
9858                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9859                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
9860                 }
9861                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9862                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9863                 if (INTEL_INFO(dev)->gen >= 4) {
9864                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9865                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9866                 }
9867
9868                 err_printf(m, "Cursor [%d]:\n", i);
9869                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9870                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
9871                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9872         }
9873 }
9874 #endif