drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic_helper.h>
  41 #include <drm/drm_dp_helper.h>
  42 #include <drm/drm_crtc_helper.h>
  43 #include <drm/drm_plane_helper.h>
  44 #include <drm/drm_rect.h>
  45 #include <linux/dma_remapping.h>
  46
  47 /* Primary plane formats supported by all gen */
  48 #define COMMON_PRIMARY_FORMATS \
  49         DRM_FORMAT_C8, \
  50         DRM_FORMAT_RGB565, \
  51         DRM_FORMAT_XRGB8888, \
  52         DRM_FORMAT_ARGB8888
  53
  54 /* Primary plane formats for gen <= 3 */
  55 static const uint32_t intel_primary_formats_gen2[] = {
  56         COMMON_PRIMARY_FORMATS,
  57         DRM_FORMAT_XRGB1555,
  58         DRM_FORMAT_ARGB1555,
  59 };
  60
  61 /* Primary plane formats for gen >= 4 */
  62 static const uint32_t intel_primary_formats_gen4[] = {
  63         COMMON_PRIMARY_FORMATS, \
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_ABGR8888,
  66         DRM_FORMAT_XRGB2101010,
  67         DRM_FORMAT_ARGB2101010,
  68         DRM_FORMAT_XBGR2101010,
  69         DRM_FORMAT_ABGR2101010,
  70 };
  71
  72 /* Cursor formats */
  73 static const uint32_t intel_cursor_formats[] = {
  74         DRM_FORMAT_ARGB8888,
  75 };
  76
  77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  78
  79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  80                                 struct intel_crtc_state *pipe_config);
  81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  82                                    struct intel_crtc_state *pipe_config);
  83
  84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  85                           int x, int y, struct drm_framebuffer *old_fb);
  86 static int intel_framebuffer_init(struct drm_device *dev,
  87                                   struct intel_framebuffer *ifb,
  88                                   struct drm_mode_fb_cmd2 *mode_cmd,
  89                                   struct drm_i915_gem_object *obj);
  90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  93                                          struct intel_link_m_n *m_n,
  94                                          struct intel_link_m_n *m2_n2);
  95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  98 static void vlv_prepare_pll(struct intel_crtc *crtc,
  99                             const struct intel_crtc_state *pipe_config);
 100 static void chv_prepare_pll(struct intel_crtc *crtc,
 101                             const struct intel_crtc_state *pipe_config);
 102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 104
 105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 106 {
 107         if (!connector->mst_port)
 108                 return connector->encoder;
 109         else
 110                 return &connector->mst_port->mst_encoders[pipe]->base;
 111 }
 112
 113 typedef struct {
 114         int     min, max;
 115 } intel_range_t;
 116
 117 typedef struct {
 118         int     dot_limit;
 119         int     p2_slow, p2_fast;
 120 } intel_p2_t;
 121
 122 typedef struct intel_limit intel_limit_t;
 123 struct intel_limit {
 124         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 125         intel_p2_t          p2;
 126 };
 127
 128 int
 129 intel_pch_rawclk(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132
 133         WARN_ON(!HAS_PCH_SPLIT(dev));
 134
 135         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 136 }
 137
 138 static inline u32 /* units of 100MHz */
 139 intel_fdi_link_freq(struct drm_device *dev)
 140 {
 141         if (IS_GEN5(dev)) {
 142                 struct drm_i915_private *dev_priv = dev->dev_private;
 143                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 144         } else
 145                 return 27;
 146 }
 147
 148 static const intel_limit_t intel_limits_i8xx_dac = {
 149         .dot = { .min = 25000, .max = 350000 },
 150         .vco = { .min = 908000, .max = 1512000 },
 151         .n = { .min = 2, .max = 16 },
 152         .m = { .min = 96, .max = 140 },
 153         .m1 = { .min = 18, .max = 26 },
 154         .m2 = { .min = 6, .max = 16 },
 155         .p = { .min = 4, .max = 128 },
 156         .p1 = { .min = 2, .max = 33 },
 157         .p2 = { .dot_limit = 165000,
 158                 .p2_slow = 4, .p2_fast = 2 },
 159 };
 160
 161 static const intel_limit_t intel_limits_i8xx_dvo = {
 162         .dot = { .min = 25000, .max = 350000 },
 163         .vco = { .min = 908000, .max = 1512000 },
 164         .n = { .min = 2, .max = 16 },
 165         .m = { .min = 96, .max = 140 },
 166         .m1 = { .min = 18, .max = 26 },
 167         .m2 = { .min = 6, .max = 16 },
 168         .p = { .min = 4, .max = 128 },
 169         .p1 = { .min = 2, .max = 33 },
 170         .p2 = { .dot_limit = 165000,
 171                 .p2_slow = 4, .p2_fast = 4 },
 172 };
 173
 174 static const intel_limit_t intel_limits_i8xx_lvds = {
 175         .dot = { .min = 25000, .max = 350000 },
 176         .vco = { .min = 908000, .max = 1512000 },
 177         .n = { .min = 2, .max = 16 },
 178         .m = { .min = 96, .max = 140 },
 179         .m1 = { .min = 18, .max = 26 },
 180         .m2 = { .min = 6, .max = 16 },
 181         .p = { .min = 4, .max = 128 },
 182         .p1 = { .min = 1, .max = 6 },
 183         .p2 = { .dot_limit = 165000,
 184                 .p2_slow = 14, .p2_fast = 7 },
 185 };
 186
 187 static const intel_limit_t intel_limits_i9xx_sdvo = {
 188         .dot = { .min = 20000, .max = 400000 },
 189         .vco = { .min = 1400000, .max = 2800000 },
 190         .n = { .min = 1, .max = 6 },
 191         .m = { .min = 70, .max = 120 },
 192         .m1 = { .min = 8, .max = 18 },
 193         .m2 = { .min = 3, .max = 7 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8 },
 196         .p2 = { .dot_limit = 200000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_i9xx_lvds = {
 201         .dot = { .min = 20000, .max = 400000 },
 202         .vco = { .min = 1400000, .max = 2800000 },
 203         .n = { .min = 1, .max = 6 },
 204         .m = { .min = 70, .max = 120 },
 205         .m1 = { .min = 8, .max = 18 },
 206         .m2 = { .min = 3, .max = 7 },
 207         .p = { .min = 7, .max = 98 },
 208         .p1 = { .min = 1, .max = 8 },
 209         .p2 = { .dot_limit = 112000,
 210                 .p2_slow = 14, .p2_fast = 7 },
 211 };
 212
 213
 214 static const intel_limit_t intel_limits_g4x_sdvo = {
 215         .dot = { .min = 25000, .max = 270000 },
 216         .vco = { .min = 1750000, .max = 3500000},
 217         .n = { .min = 1, .max = 4 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 10, .max = 30 },
 222         .p1 = { .min = 1, .max = 3},
 223         .p2 = { .dot_limit = 270000,
 224                 .p2_slow = 10,
 225                 .p2_fast = 10
 226         },
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_hdmi = {
 230         .dot = { .min = 22000, .max = 400000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 4 },
 233         .m = { .min = 104, .max = 138 },
 234         .m1 = { .min = 16, .max = 23 },
 235         .m2 = { .min = 5, .max = 11 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8},
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 243         .dot = { .min = 20000, .max = 115000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 14, .p2_fast = 14
 253         },
 254 };
 255
 256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 257         .dot = { .min = 80000, .max = 224000 },
 258         .vco = { .min = 1750000, .max = 3500000 },
 259         .n = { .min = 1, .max = 3 },
 260         .m = { .min = 104, .max = 138 },
 261         .m1 = { .min = 17, .max = 23 },
 262         .m2 = { .min = 5, .max = 11 },
 263         .p = { .min = 14, .max = 42 },
 264         .p1 = { .min = 2, .max = 6 },
 265         .p2 = { .dot_limit = 0,
 266                 .p2_slow = 7, .p2_fast = 7
 267         },
 268 };
 269
 270 static const intel_limit_t intel_limits_pineview_sdvo = {
 271         .dot = { .min = 20000, .max = 400000},
 272         .vco = { .min = 1700000, .max = 3500000 },
 273         /* Pineview's Ncounter is a ring counter */
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         /* Pineview only has one combined m divider, which we treat as m2. */
 277         .m1 = { .min = 0, .max = 0 },
 278         .m2 = { .min = 0, .max = 254 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 200000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283 };
 284
 285 static const intel_limit_t intel_limits_pineview_lvds = {
 286         .dot = { .min = 20000, .max = 400000 },
 287         .vco = { .min = 1700000, .max = 3500000 },
 288         .n = { .min = 3, .max = 6 },
 289         .m = { .min = 2, .max = 256 },
 290         .m1 = { .min = 0, .max = 0 },
 291         .m2 = { .min = 0, .max = 254 },
 292         .p = { .min = 7, .max = 112 },
 293         .p1 = { .min = 1, .max = 8 },
 294         .p2 = { .dot_limit = 112000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296 };
 297
 298 /* Ironlake / Sandybridge
 299  *
 300  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 301  * the range value for them is (actual_value - 2).
 302  */
 303 static const intel_limit_t intel_limits_ironlake_dac = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 5 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 3 },
 320         .m = { .min = 79, .max = 118 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 127 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 56 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340 };
 341
 342 /* LVDS 100mhz refclk limits. */
 343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 28, .max = 112 },
 351         .p1 = { .min = 2, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 14, .p2_fast = 14 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 126 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 14, .max = 42 },
 364         .p1 = { .min = 2, .max = 6 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 7, .p2_fast = 7 },
 367 };
 368
 369 static const intel_limit_t intel_limits_vlv = {
 370          /*
 371           * These are the data rate limits (measured in fast clocks)
 372           * since those are the strictest limits we have. The fast
 373           * clock and actual rate limits are more relaxed, so checking
 374           * them would make no difference.
 375           */
 376         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m1 = { .min = 2, .max = 3 },
 380         .m2 = { .min = 11, .max = 156 },
 381         .p1 = { .min = 2, .max = 3 },
 382         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 383 };
 384
 385 static const intel_limit_t intel_limits_chv = {
 386         /*
 387          * These are the data rate limits (measured in fast clocks)
 388          * since those are the strictest limits we have.  The fast
 389          * clock and actual rate limits are more relaxed, so checking
 390          * them would make no difference.
 391          */
 392         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 393         .vco = { .min = 4860000, .max = 6700000 },
 394         .n = { .min = 1, .max = 1 },
 395         .m1 = { .min = 2, .max = 2 },
 396         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 397         .p1 = { .min = 2, .max = 4 },
 398         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 399 };
 400
 401 static void vlv_clock(int refclk, intel_clock_t *clock)
 402 {
 403         clock->m = clock->m1 * clock->m2;
 404         clock->p = clock->p1 * clock->p2;
 405         if (WARN_ON(clock->n == 0 || clock->p == 0))
 406                 return;
 407         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 408         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 409 }
 410
 411 /**
 412  * Returns whether any output on the specified pipe is of the specified type
 413  */
 414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 415 {
 416         struct drm_device *dev = crtc->base.dev;
 417         struct intel_encoder *encoder;
 418
 419         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 420                 if (encoder->type == type)
 421                         return true;
 422
 423         return false;
 424 }
 425
 426 /**
 427  * Returns whether any output on the specified pipe will have the specified
 428  * type after a staged modeset is complete, i.e., the same as
 429  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 430  * encoder->crtc.
 431  */
 432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 433 {
 434         struct drm_device *dev = crtc->base.dev;
 435         struct intel_encoder *encoder;
 436
 437         for_each_intel_encoder(dev, encoder)
 438                 if (encoder->new_crtc == crtc && encoder->type == type)
 439                         return true;
 440
 441         return false;
 442 }
 443
 444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 445                                                 int refclk)
 446 {
 447         struct drm_device *dev = crtc->base.dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev)) {
 452                         if (refclk == 100000)
 453                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 454                         else
 455                                 limit = &intel_limits_ironlake_dual_lvds;
 456                 } else {
 457                         if (refclk == 100000)
 458                                 limit = &intel_limits_ironlake_single_lvds_100m;
 459                         else
 460                                 limit = &intel_limits_ironlake_single_lvds;
 461                 }
 462         } else
 463                 limit = &intel_limits_ironlake_dac;
 464
 465         return limit;
 466 }
 467
 468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 469 {
 470         struct drm_device *dev = crtc->base.dev;
 471         const intel_limit_t *limit;
 472
 473         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 474                 if (intel_is_dual_link_lvds(dev))
 475                         limit = &intel_limits_g4x_dual_channel_lvds;
 476                 else
 477                         limit = &intel_limits_g4x_single_channel_lvds;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 479                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 480                 limit = &intel_limits_g4x_hdmi;
 481         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 482                 limit = &intel_limits_g4x_sdvo;
 483         } else /* The option is for other outputs */
 484                 limit = &intel_limits_i9xx_sdvo;
 485
 486         return limit;
 487 }
 488
 489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 490 {
 491         struct drm_device *dev = crtc->base.dev;
 492         const intel_limit_t *limit;
 493
 494         if (HAS_PCH_SPLIT(dev))
 495                 limit = intel_ironlake_limit(crtc, refclk);
 496         else if (IS_G4X(dev)) {
 497                 limit = intel_g4x_limit(crtc);
 498         } else if (IS_PINEVIEW(dev)) {
 499                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 500                         limit = &intel_limits_pineview_lvds;
 501                 else
 502                         limit = &intel_limits_pineview_sdvo;
 503         } else if (IS_CHERRYVIEW(dev)) {
 504                 limit = &intel_limits_chv;
 505         } else if (IS_VALLEYVIEW(dev)) {
 506                 limit = &intel_limits_vlv;
 507         } else if (!IS_GEN2(dev)) {
 508                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 509                         limit = &intel_limits_i9xx_lvds;
 510                 else
 511                         limit = &intel_limits_i9xx_sdvo;
 512         } else {
 513                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 514                         limit = &intel_limits_i8xx_lvds;
 515                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 516                         limit = &intel_limits_i8xx_dvo;
 517                 else
 518                         limit = &intel_limits_i8xx_dac;
 519         }
 520         return limit;
 521 }
 522
 523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 524 static void pineview_clock(int refclk, intel_clock_t *clock)
 525 {
 526         clock->m = clock->m2 + 2;
 527         clock->p = clock->p1 * clock->p2;
 528         if (WARN_ON(clock->n == 0 || clock->p == 0))
 529                 return;
 530         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 531         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 532 }
 533
 534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 535 {
 536         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 537 }
 538
 539 static void i9xx_clock(int refclk, intel_clock_t *clock)
 540 {
 541         clock->m = i9xx_dpll_compute_m(clock);
 542         clock->p = clock->p1 * clock->p2;
 543         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 544                 return;
 545         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 546         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 547 }
 548
 549 static void chv_clock(int refclk, intel_clock_t *clock)
 550 {
 551         clock->m = clock->m1 * clock->m2;
 552         clock->p = clock->p1 * clock->p2;
 553         if (WARN_ON(clock->n == 0 || clock->p == 0))
 554                 return;
 555         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 556                         clock->n << 22);
 557         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 558 }
 559
 560 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 561 /**
 562  * Returns whether the given set of divisors are valid for a given refclk with
 563  * the given connectors.
 564  */
 565
 566 static bool intel_PLL_is_valid(struct drm_device *dev,
 567                                const intel_limit_t *limit,
 568                                const intel_clock_t *clock)
 569 {
 570         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 571                 INTELPllInvalid("n out of range\n");
 572         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 573                 INTELPllInvalid("p1 out of range\n");
 574         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 575                 INTELPllInvalid("m2 out of range\n");
 576         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 577                 INTELPllInvalid("m1 out of range\n");
 578
 579         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 580                 if (clock->m1 <= clock->m2)
 581                         INTELPllInvalid("m1 <= m2\n");
 582
 583         if (!IS_VALLEYVIEW(dev)) {
 584                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 585                         INTELPllInvalid("p out of range\n");
 586                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 587                         INTELPllInvalid("m out of range\n");
 588         }
 589
 590         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 591                 INTELPllInvalid("vco out of range\n");
 592         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 593          * connector, etc., rather than just a single range.
 594          */
 595         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 596                 INTELPllInvalid("dot out of range\n");
 597
 598         return true;
 599 }
 600
 601 static bool
 602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 603                     int target, int refclk, intel_clock_t *match_clock,
 604                     intel_clock_t *best_clock)
 605 {
 606         struct drm_device *dev = crtc->base.dev;
 607         intel_clock_t clock;
 608         int err = target;
 609
 610         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 611                 /*
 612                  * For LVDS just rely on its current settings for dual-channel.
 613                  * We haven't figured out how to reliably set up different
 614                  * single/dual channel state, if we even can.
 615                  */
 616                 if (intel_is_dual_link_lvds(dev))
 617                         clock.p2 = limit->p2.p2_fast;
 618                 else
 619                         clock.p2 = limit->p2.p2_slow;
 620         } else {
 621                 if (target < limit->p2.dot_limit)
 622                         clock.p2 = limit->p2.p2_slow;
 623                 else
 624                         clock.p2 = limit->p2.p2_fast;
 625         }
 626
 627         memset(best_clock, 0, sizeof(*best_clock));
 628
 629         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 630              clock.m1++) {
 631                 for (clock.m2 = limit->m2.min;
 632                      clock.m2 <= limit->m2.max; clock.m2++) {
 633                         if (clock.m2 >= clock.m1)
 634                                 break;
 635                         for (clock.n = limit->n.min;
 636                              clock.n <= limit->n.max; clock.n++) {
 637                                 for (clock.p1 = limit->p1.min;
 638                                         clock.p1 <= limit->p1.max; clock.p1++) {
 639                                         int this_err;
 640
 641                                         i9xx_clock(refclk, &clock);
 642                                         if (!intel_PLL_is_valid(dev, limit,
 643                                                                 &clock))
 644                                                 continue;
 645                                         if (match_clock &&
 646                                             clock.p != match_clock->p)
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err) {
 651                                                 *best_clock = clock;
 652                                                 err = this_err;
 653                                         }
 654                                 }
 655                         }
 656                 }
 657         }
 658
 659         return (err != target);
 660 }
 661
 662 static bool
 663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 664                    int target, int refclk, intel_clock_t *match_clock,
 665                    intel_clock_t *best_clock)
 666 {
 667         struct drm_device *dev = crtc->base.dev;
 668         intel_clock_t clock;
 669         int err = target;
 670
 671         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 672                 /*
 673                  * For LVDS just rely on its current settings for dual-channel.
 674                  * We haven't figured out how to reliably set up different
 675                  * single/dual channel state, if we even can.
 676                  */
 677                 if (intel_is_dual_link_lvds(dev))
 678                         clock.p2 = limit->p2.p2_fast;
 679                 else
 680                         clock.p2 = limit->p2.p2_slow;
 681         } else {
 682                 if (target < limit->p2.dot_limit)
 683                         clock.p2 = limit->p2.p2_slow;
 684                 else
 685                         clock.p2 = limit->p2.p2_fast;
 686         }
 687
 688         memset(best_clock, 0, sizeof(*best_clock));
 689
 690         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 691              clock.m1++) {
 692                 for (clock.m2 = limit->m2.min;
 693                      clock.m2 <= limit->m2.max; clock.m2++) {
 694                         for (clock.n = limit->n.min;
 695                              clock.n <= limit->n.max; clock.n++) {
 696                                 for (clock.p1 = limit->p1.min;
 697                                         clock.p1 <= limit->p1.max; clock.p1++) {
 698                                         int this_err;
 699
 700                                         pineview_clock(refclk, &clock);
 701                                         if (!intel_PLL_is_valid(dev, limit,
 702                                                                 &clock))
 703                                                 continue;
 704                                         if (match_clock &&
 705                                             clock.p != match_clock->p)
 706                                                 continue;
 707
 708                                         this_err = abs(clock.dot - target);
 709                                         if (this_err < err) {
 710                                                 *best_clock = clock;
 711                                                 err = this_err;
 712                                         }
 713                                 }
 714                         }
 715                 }
 716         }
 717
 718         return (err != target);
 719 }
 720
 721 static bool
 722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 723                    int target, int refclk, intel_clock_t *match_clock,
 724                    intel_clock_t *best_clock)
 725 {
 726         struct drm_device *dev = crtc->base.dev;
 727         intel_clock_t clock;
 728         int max_n;
 729         bool found;
 730         /* approximately equals target * 0.00585 */
 731         int err_most = (target >> 8) + (target >> 9);
 732         found = false;
 733
 734         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 735                 if (intel_is_dual_link_lvds(dev))
 736                         clock.p2 = limit->p2.p2_fast;
 737                 else
 738                         clock.p2 = limit->p2.p2_slow;
 739         } else {
 740                 if (target < limit->p2.dot_limit)
 741                         clock.p2 = limit->p2.p2_slow;
 742                 else
 743                         clock.p2 = limit->p2.p2_fast;
 744         }
 745
 746         memset(best_clock, 0, sizeof(*best_clock));
 747         max_n = limit->n.max;
 748         /* based on hardware requirement, prefer smaller n to precision */
 749         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 750                 /* based on hardware requirement, prefere larger m1,m2 */
 751                 for (clock.m1 = limit->m1.max;
 752                      clock.m1 >= limit->m1.min; clock.m1--) {
 753                         for (clock.m2 = limit->m2.max;
 754                              clock.m2 >= limit->m2.min; clock.m2--) {
 755                                 for (clock.p1 = limit->p1.max;
 756                                      clock.p1 >= limit->p1.min; clock.p1--) {
 757                                         int this_err;
 758
 759                                         i9xx_clock(refclk, &clock);
 760                                         if (!intel_PLL_is_valid(dev, limit,
 761                                                                 &clock))
 762                                                 continue;
 763
 764                                         this_err = abs(clock.dot - target);
 765                                         if (this_err < err_most) {
 766                                                 *best_clock = clock;
 767                                                 err_most = this_err;
 768                                                 max_n = clock.n;
 769                                                 found = true;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775         return found;
 776 }
 777
 778 static bool
 779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 780                    int target, int refclk, intel_clock_t *match_clock,
 781                    intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->base.dev;
 784         intel_clock_t clock;
 785         unsigned int bestppm = 1000000;
 786         /* min update 19.2 MHz */
 787         int max_n = min(limit->n.max, refclk / 19200);
 788         bool found = false;
 789
 790         target *= 5; /* fast clock */
 791
 792         memset(best_clock, 0, sizeof(*best_clock));
 793
 794         /* based on hardware requirement, prefer smaller n to precision */
 795         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 796                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 797                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 798                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 799                                 clock.p = clock.p1 * clock.p2;
 800                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 801                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 802                                         unsigned int ppm, diff;
 803
 804                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 805                                                                      refclk * clock.m1);
 806
 807                                         vlv_clock(refclk, &clock);
 808
 809                                         if (!intel_PLL_is_valid(dev, limit,
 810                                                                 &clock))
 811                                                 continue;
 812
 813                                         diff = abs(clock.dot - target);
 814                                         ppm = div_u64(1000000ULL * diff, target);
 815
 816                                         if (ppm < 100 && clock.p > best_clock->p) {
 817                                                 bestppm = 0;
 818                                                 *best_clock = clock;
 819                                                 found = true;
 820                                         }
 821
 822                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 823                                                 bestppm = ppm;
 824                                                 *best_clock = clock;
 825                                                 found = true;
 826                                         }
 827                                 }
 828                         }
 829                 }
 830         }
 831
 832         return found;
 833 }
 834
 835 static bool
 836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 837                    int target, int refclk, intel_clock_t *match_clock,
 838                    intel_clock_t *best_clock)
 839 {
 840         struct drm_device *dev = crtc->base.dev;
 841         intel_clock_t clock;
 842         uint64_t m2;
 843         int found = false;
 844
 845         memset(best_clock, 0, sizeof(*best_clock));
 846
 847         /*
 848          * Based on hardware doc, the n always set to 1, and m1 always
 849          * set to 2.  If requires to support 200Mhz refclk, we need to
 850          * revisit this because n may not 1 anymore.
 851          */
 852         clock.n = 1, clock.m1 = 2;
 853         target *= 5;    /* fast clock */
 854
 855         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 856                 for (clock.p2 = limit->p2.p2_fast;
 857                                 clock.p2 >= limit->p2.p2_slow;
 858                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 859
 860                         clock.p = clock.p1 * clock.p2;
 861
 862                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 863                                         clock.n) << 22, refclk * clock.m1);
 864
 865                         if (m2 > INT_MAX/clock.m1)
 866                                 continue;
 867
 868                         clock.m2 = m2;
 869
 870                         chv_clock(refclk, &clock);
 871
 872                         if (!intel_PLL_is_valid(dev, limit, &clock))
 873                                 continue;
 874
 875                         /* based on hardware requirement, prefer bigger p
 876                          */
 877                         if (clock.p > best_clock->p) {
 878                                 *best_clock = clock;
 879                                 found = true;
 880                         }
 881                 }
 882         }
 883
 884         return found;
 885 }
 886
 887 bool intel_crtc_active(struct drm_crtc *crtc)
 888 {
 889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 890
 891         /* Be paranoid as we can arrive here with only partial
 892          * state retrieved from the hardware during setup.
 893          *
 894          * We can ditch the adjusted_mode.crtc_clock check as soon
 895          * as Haswell has gained clock readout/fastboot support.
 896          *
 897          * We can ditch the crtc->primary->fb check as soon as we can
 898          * properly reconstruct framebuffers.
 899          */
 900         return intel_crtc->active && crtc->primary->fb &&
 901                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 902 }
 903
 904 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 905                                              enum pipe pipe)
 906 {
 907         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 909
 910         return intel_crtc->config->cpu_transcoder;
 911 }
 912
 913 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 914 {
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         u32 reg = PIPEDSL(pipe);
 917         u32 line1, line2;
 918         u32 line_mask;
 919
 920         if (IS_GEN2(dev))
 921                 line_mask = DSL_LINEMASK_GEN2;
 922         else
 923                 line_mask = DSL_LINEMASK_GEN3;
 924
 925         line1 = I915_READ(reg) & line_mask;
 926         mdelay(5);
 927         line2 = I915_READ(reg) & line_mask;
 928
 929         return line1 == line2;
 930 }
 931
 932 /*
 933  * intel_wait_for_pipe_off - wait for pipe to turn off
 934  * @crtc: crtc whose pipe to wait for
 935  *
 936  * After disabling a pipe, we can't wait for vblank in the usual way,
 937  * spinning on the vblank interrupt status bit, since we won't actually
 938  * see an interrupt when the pipe is disabled.
 939  *
 940  * On Gen4 and above:
 941  *   wait for the pipe register state bit to turn off
 942  *
 943  * Otherwise:
 944  *   wait for the display line value to settle (it usually
 945  *   ends up stopping at the start of the next frame).
 946  *
 947  */
 948 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 949 {
 950         struct drm_device *dev = crtc->base.dev;
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
 953         enum pipe pipe = crtc->pipe;
 954
 955         if (INTEL_INFO(dev)->gen >= 4) {
 956                 int reg = PIPECONF(cpu_transcoder);
 957
 958                 /* Wait for the Pipe State to go off */
 959                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 960                              100))
 961                         WARN(1, "pipe_off wait timed out\n");
 962         } else {
 963                 /* Wait for the display line to settle */
 964                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 965                         WARN(1, "pipe_off wait timed out\n");
 966         }
 967 }
 968
 969 /*
 970  * ibx_digital_port_connected - is the specified port connected?
 971  * @dev_priv: i915 private structure
 972  * @port: the port to test
 973  *
 974  * Returns true if @port is connected, false otherwise.
 975  */
 976 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 977                                 struct intel_digital_port *port)
 978 {
 979         u32 bit;
 980
 981         if (HAS_PCH_IBX(dev_priv->dev)) {
 982                 switch (port->port) {
 983                 case PORT_B:
 984                         bit = SDE_PORTB_HOTPLUG;
 985                         break;
 986                 case PORT_C:
 987                         bit = SDE_PORTC_HOTPLUG;
 988                         break;
 989                 case PORT_D:
 990                         bit = SDE_PORTD_HOTPLUG;
 991                         break;
 992                 default:
 993                         return true;
 994                 }
 995         } else {
 996                 switch (port->port) {
 997                 case PORT_B:
 998                         bit = SDE_PORTB_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_C:
1001                         bit = SDE_PORTC_HOTPLUG_CPT;
1002                         break;
1003                 case PORT_D:
1004                         bit = SDE_PORTD_HOTPLUG_CPT;
1005                         break;
1006                 default:
1007                         return true;
1008                 }
1009         }
1010
1011         return I915_READ(SDEISR) & bit;
1012 }
1013
1014 static const char *state_string(bool enabled)
1015 {
1016         return enabled ? "on" : "off";
1017 }
1018
1019 /* Only for pre-ILK configs */
1020 void assert_pll(struct drm_i915_private *dev_priv,
1021                 enum pipe pipe, bool state)
1022 {
1023         int reg;
1024         u32 val;
1025         bool cur_state;
1026
1027         reg = DPLL(pipe);
1028         val = I915_READ(reg);
1029         cur_state = !!(val & DPLL_VCO_ENABLE);
1030         I915_STATE_WARN(cur_state != state,
1031              "PLL state assertion failure (expected %s, current %s)\n",
1032              state_string(state), state_string(cur_state));
1033 }
1034
1035 /* XXX: the dsi pll is shared between MIPI DSI ports */
1036 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1037 {
1038         u32 val;
1039         bool cur_state;
1040
1041         mutex_lock(&dev_priv->dpio_lock);
1042         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043         mutex_unlock(&dev_priv->dpio_lock);
1044
1045         cur_state = val & DSI_PLL_VCO_EN;
1046         I915_STATE_WARN(cur_state != state,
1047              "DSI PLL state assertion failure (expected %s, current %s)\n",
1048              state_string(state), state_string(cur_state));
1049 }
1050 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052
1053 struct intel_shared_dpll *
1054 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1055 {
1056         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1057
1058         if (crtc->config->shared_dpll < 0)
1059                 return NULL;
1060
1061         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1062 }
1063
1064 /* For ILK+ */
1065 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066                         struct intel_shared_dpll *pll,
1067                         bool state)
1068 {
1069         bool cur_state;
1070         struct intel_dpll_hw_state hw_state;
1071
1072         if (WARN (!pll,
1073                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1074                 return;
1075
1076         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1077         I915_STATE_WARN(cur_state != state,
1078              "%s assertion failure (expected %s, current %s)\n",
1079              pll->name, state_string(state), state_string(cur_state));
1080 }
1081
1082 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083                           enum pipe pipe, bool state)
1084 {
1085         int reg;
1086         u32 val;
1087         bool cur_state;
1088         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1089                                                                       pipe);
1090
1091         if (HAS_DDI(dev_priv->dev)) {
1092                 /* DDI does not have a specific FDI_TX register */
1093                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1094                 val = I915_READ(reg);
1095                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1096         } else {
1097                 reg = FDI_TX_CTL(pipe);
1098                 val = I915_READ(reg);
1099                 cur_state = !!(val & FDI_TX_ENABLE);
1100         }
1101         I915_STATE_WARN(cur_state != state,
1102              "FDI TX state assertion failure (expected %s, current %s)\n",
1103              state_string(state), state_string(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109                           enum pipe pipe, bool state)
1110 {
1111         int reg;
1112         u32 val;
1113         bool cur_state;
1114
1115         reg = FDI_RX_CTL(pipe);
1116         val = I915_READ(reg);
1117         cur_state = !!(val & FDI_RX_ENABLE);
1118         I915_STATE_WARN(cur_state != state,
1119              "FDI RX state assertion failure (expected %s, current %s)\n",
1120              state_string(state), state_string(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126                                       enum pipe pipe)
1127 {
1128         int reg;
1129         u32 val;
1130
1131         /* ILK FDI PLL is always enabled */
1132         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1133                 return;
1134
1135         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136         if (HAS_DDI(dev_priv->dev))
1137                 return;
1138
1139         reg = FDI_TX_CTL(pipe);
1140         val = I915_READ(reg);
1141         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1142 }
1143
1144 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145                        enum pipe pipe, bool state)
1146 {
1147         int reg;
1148         u32 val;
1149         bool cur_state;
1150
1151         reg = FDI_RX_CTL(pipe);
1152         val = I915_READ(reg);
1153         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1154         I915_STATE_WARN(cur_state != state,
1155              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156              state_string(state), state_string(cur_state));
1157 }
1158
1159 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1160                            enum pipe pipe)
1161 {
1162         struct drm_device *dev = dev_priv->dev;
1163         int pp_reg;
1164         u32 val;
1165         enum pipe panel_pipe = PIPE_A;
1166         bool locked = true;
1167
1168         if (WARN_ON(HAS_DDI(dev)))
1169                 return;
1170
1171         if (HAS_PCH_SPLIT(dev)) {
1172                 u32 port_sel;
1173
1174                 pp_reg = PCH_PP_CONTROL;
1175                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1176
1177                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179                         panel_pipe = PIPE_B;
1180                 /* XXX: else fix for eDP */
1181         } else if (IS_VALLEYVIEW(dev)) {
1182                 /* presumably write lock depends on pipe, not port select */
1183                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1184                 panel_pipe = pipe;
1185         } else {
1186                 pp_reg = PP_CONTROL;
1187                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188                         panel_pipe = PIPE_B;
1189         }
1190
1191         val = I915_READ(pp_reg);
1192         if (!(val & PANEL_POWER_ON) ||
1193             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1194                 locked = false;
1195
1196         I915_STATE_WARN(panel_pipe == pipe && locked,
1197              "panel assertion failure, pipe %c regs locked\n",
1198              pipe_name(pipe));
1199 }
1200
1201 static void assert_cursor(struct drm_i915_private *dev_priv,
1202                           enum pipe pipe, bool state)
1203 {
1204         struct drm_device *dev = dev_priv->dev;
1205         bool cur_state;
1206
1207         if (IS_845G(dev) || IS_I865G(dev))
1208                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1209         else
1210                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1211
1212         I915_STATE_WARN(cur_state != state,
1213              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214              pipe_name(pipe), state_string(state), state_string(cur_state));
1215 }
1216 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220                  enum pipe pipe, bool state)
1221 {
1222         int reg;
1223         u32 val;
1224         bool cur_state;
1225         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226                                                                       pipe);
1227
1228         /* if we need the pipe quirk it must be always on */
1229         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1231                 state = true;
1232
1233         if (!intel_display_power_is_enabled(dev_priv,
1234                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1235                 cur_state = false;
1236         } else {
1237                 reg = PIPECONF(cpu_transcoder);
1238                 val = I915_READ(reg);
1239                 cur_state = !!(val & PIPECONF_ENABLE);
1240         }
1241
1242         I915_STATE_WARN(cur_state != state,
1243              "pipe %c assertion failure (expected %s, current %s)\n",
1244              pipe_name(pipe), state_string(state), state_string(cur_state));
1245 }
1246
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248                          enum plane plane, bool state)
1249 {
1250         int reg;
1251         u32 val;
1252         bool cur_state;
1253
1254         reg = DSPCNTR(plane);
1255         val = I915_READ(reg);
1256         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257         I915_STATE_WARN(cur_state != state,
1258              "plane %c assertion failure (expected %s, current %s)\n",
1259              plane_name(plane), state_string(state), state_string(cur_state));
1260 }
1261
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266                                    enum pipe pipe)
1267 {
1268         struct drm_device *dev = dev_priv->dev;
1269         int reg, i;
1270         u32 val;
1271         int cur_pipe;
1272
1273         /* Primary planes are fixed to pipes on gen4+ */
1274         if (INTEL_INFO(dev)->gen >= 4) {
1275                 reg = DSPCNTR(pipe);
1276                 val = I915_READ(reg);
1277                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1278                      "plane %c assertion failure, should be disabled but not\n",
1279                      plane_name(pipe));
1280                 return;
1281         }
1282
1283         /* Need to check both planes against the pipe */
1284         for_each_pipe(dev_priv, i) {
1285                 reg = DSPCNTR(i);
1286                 val = I915_READ(reg);
1287                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288                         DISPPLANE_SEL_PIPE_SHIFT;
1289                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1290                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291                      plane_name(i), pipe_name(pipe));
1292         }
1293 }
1294
1295 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1296                                     enum pipe pipe)
1297 {
1298         struct drm_device *dev = dev_priv->dev;
1299         int reg, sprite;
1300         u32 val;
1301
1302         if (INTEL_INFO(dev)->gen >= 9) {
1303                 for_each_sprite(pipe, sprite) {
1304                         val = I915_READ(PLANE_CTL(pipe, sprite));
1305                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1306                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307                              sprite, pipe_name(pipe));
1308                 }
1309         } else if (IS_VALLEYVIEW(dev)) {
1310                 for_each_sprite(pipe, sprite) {
1311                         reg = SPCNTR(pipe, sprite);
1312                         val = I915_READ(reg);
1313                         I915_STATE_WARN(val & SP_ENABLE,
1314                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315                              sprite_name(pipe, sprite), pipe_name(pipe));
1316                 }
1317         } else if (INTEL_INFO(dev)->gen >= 7) {
1318                 reg = SPRCTL(pipe);
1319                 val = I915_READ(reg);
1320                 I915_STATE_WARN(val & SPRITE_ENABLE,
1321                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322                      plane_name(pipe), pipe_name(pipe));
1323         } else if (INTEL_INFO(dev)->gen >= 5) {
1324                 reg = DVSCNTR(pipe);
1325                 val = I915_READ(reg);
1326                 I915_STATE_WARN(val & DVS_ENABLE,
1327                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328                      plane_name(pipe), pipe_name(pipe));
1329         }
1330 }
1331
1332 static void assert_vblank_disabled(struct drm_crtc *crtc)
1333 {
1334         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1335                 drm_crtc_vblank_put(crtc);
1336 }
1337
1338 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1339 {
1340         u32 val;
1341         bool enabled;
1342
1343         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1344
1345         val = I915_READ(PCH_DREF_CONTROL);
1346         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347                             DREF_SUPERSPREAD_SOURCE_MASK));
1348         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1349 }
1350
1351 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1352                                            enum pipe pipe)
1353 {
1354         int reg;
1355         u32 val;
1356         bool enabled;
1357
1358         reg = PCH_TRANSCONF(pipe);
1359         val = I915_READ(reg);
1360         enabled = !!(val & TRANS_ENABLE);
1361         I915_STATE_WARN(enabled,
1362              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363              pipe_name(pipe));
1364 }
1365
1366 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367                             enum pipe pipe, u32 port_sel, u32 val)
1368 {
1369         if ((val & DP_PORT_EN) == 0)
1370                 return false;
1371
1372         if (HAS_PCH_CPT(dev_priv->dev)) {
1373                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376                         return false;
1377         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379                         return false;
1380         } else {
1381                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382                         return false;
1383         }
1384         return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388                               enum pipe pipe, u32 val)
1389 {
1390         if ((val & SDVO_ENABLE) == 0)
1391                 return false;
1392
1393         if (HAS_PCH_CPT(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395                         return false;
1396         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398                         return false;
1399         } else {
1400                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401                         return false;
1402         }
1403         return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407                               enum pipe pipe, u32 val)
1408 {
1409         if ((val & LVDS_PORT_EN) == 0)
1410                 return false;
1411
1412         if (HAS_PCH_CPT(dev_priv->dev)) {
1413                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414                         return false;
1415         } else {
1416                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417                         return false;
1418         }
1419         return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423                               enum pipe pipe, u32 val)
1424 {
1425         if ((val & ADPA_DAC_ENABLE) == 0)
1426                 return false;
1427         if (HAS_PCH_CPT(dev_priv->dev)) {
1428                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429                         return false;
1430         } else {
1431                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432                         return false;
1433         }
1434         return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438                                    enum pipe pipe, int reg, u32 port_sel)
1439 {
1440         u32 val = I915_READ(reg);
1441         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1442              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443              reg, pipe_name(pipe));
1444
1445         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1446              && (val & DP_PIPEB_SELECT),
1447              "IBX PCH dp port still using transcoder B\n");
1448 }
1449
1450 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451                                      enum pipe pipe, int reg)
1452 {
1453         u32 val = I915_READ(reg);
1454         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1455              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456              reg, pipe_name(pipe));
1457
1458         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1459              && (val & SDVO_PIPE_B_SELECT),
1460              "IBX PCH hdmi port still using transcoder B\n");
1461 }
1462
1463 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1464                                       enum pipe pipe)
1465 {
1466         int reg;
1467         u32 val;
1468
1469         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473         reg = PCH_ADPA;
1474         val = I915_READ(reg);
1475         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476              "PCH VGA enabled on transcoder %c, should be disabled\n",
1477              pipe_name(pipe));
1478
1479         reg = PCH_LVDS;
1480         val = I915_READ(reg);
1481         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1482              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1483              pipe_name(pipe));
1484
1485         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1488 }
1489
1490 static void intel_init_dpio(struct drm_device *dev)
1491 {
1492         struct drm_i915_private *dev_priv = dev->dev_private;
1493
1494         if (!IS_VALLEYVIEW(dev))
1495                 return;
1496
1497         /*
1498          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499          * CHV x1 PHY (DP/HDMI D)
1500          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501          */
1502         if (IS_CHERRYVIEW(dev)) {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1505         } else {
1506                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507         }
1508 }
1509
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511                            const struct intel_crtc_state *pipe_config)
1512 {
1513         struct drm_device *dev = crtc->base.dev;
1514         struct drm_i915_private *dev_priv = dev->dev_private;
1515         int reg = DPLL(crtc->pipe);
1516         u32 dpll = pipe_config->dpll_hw_state.dpll;
1517
1518         assert_pipe_disabled(dev_priv, crtc->pipe);
1519
1520         /* No really, not for ILK+ */
1521         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1522
1523         /* PLL is protected by panel, make sure we can write it */
1524         if (IS_MOBILE(dev_priv->dev))
1525                 assert_panel_unlocked(dev_priv, crtc->pipe);
1526
1527         I915_WRITE(reg, dpll);
1528         POSTING_READ(reg);
1529         udelay(150);
1530
1531         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1533
1534         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1535         POSTING_READ(DPLL_MD(crtc->pipe));
1536
1537         /* We do this three times for luck */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544         I915_WRITE(reg, dpll);
1545         POSTING_READ(reg);
1546         udelay(150); /* wait for warmup */
1547 }
1548
1549 static void chv_enable_pll(struct intel_crtc *crtc,
1550                            const struct intel_crtc_state *pipe_config)
1551 {
1552         struct drm_device *dev = crtc->base.dev;
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         int pipe = crtc->pipe;
1555         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1556         u32 tmp;
1557
1558         assert_pipe_disabled(dev_priv, crtc->pipe);
1559
1560         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1561
1562         mutex_lock(&dev_priv->dpio_lock);
1563
1564         /* Enable back the 10bit clock to display controller */
1565         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566         tmp |= DPIO_DCLKP_EN;
1567         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1568
1569         /*
1570          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1571          */
1572         udelay(1);
1573
1574         /* Enable PLL */
1575         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1576
1577         /* Check PLL is locked */
1578         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1579                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1580
1581         /* not sure when this should be written */
1582         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1583         POSTING_READ(DPLL_MD(pipe));
1584
1585         mutex_unlock(&dev_priv->dpio_lock);
1586 }
1587
1588 static int intel_num_dvo_pipes(struct drm_device *dev)
1589 {
1590         struct intel_crtc *crtc;
1591         int count = 0;
1592
1593         for_each_intel_crtc(dev, crtc)
1594                 count += crtc->active &&
1595                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1596
1597         return count;
1598 }
1599
1600 static void i9xx_enable_pll(struct intel_crtc *crtc)
1601 {
1602         struct drm_device *dev = crtc->base.dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         int reg = DPLL(crtc->pipe);
1605         u32 dpll = crtc->config->dpll_hw_state.dpll;
1606
1607         assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609         /* No really, not for ILK+ */
1610         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1611
1612         /* PLL is protected by panel, make sure we can write it */
1613         if (IS_MOBILE(dev) && !IS_I830(dev))
1614                 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616         /* Enable DVO 2x clock on both PLLs if necessary */
1617         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1618                 /*
1619                  * It appears to be important that we don't enable this
1620                  * for the current pipe before otherwise configuring the
1621                  * PLL. No idea how this should be handled if multiple
1622                  * DVO outputs are enabled simultaneosly.
1623                  */
1624                 dpll |= DPLL_DVO_2X_MODE;
1625                 I915_WRITE(DPLL(!crtc->pipe),
1626                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1627         }
1628
1629         /* Wait for the clocks to stabilize. */
1630         POSTING_READ(reg);
1631         udelay(150);
1632
1633         if (INTEL_INFO(dev)->gen >= 4) {
1634                 I915_WRITE(DPLL_MD(crtc->pipe),
1635                            crtc->config->dpll_hw_state.dpll_md);
1636         } else {
1637                 /* The pixel multiplier can only be updated once the
1638                  * DPLL is enabled and the clocks are stable.
1639                  *
1640                  * So write it again.
1641                  */
1642                 I915_WRITE(reg, dpll);
1643         }
1644
1645         /* We do this three times for luck */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652         I915_WRITE(reg, dpll);
1653         POSTING_READ(reg);
1654         udelay(150); /* wait for warmup */
1655 }
1656
1657 /**
1658  * i9xx_disable_pll - disable a PLL
1659  * @dev_priv: i915 private structure
1660  * @pipe: pipe PLL to disable
1661  *
1662  * Disable the PLL for @pipe, making sure the pipe is off first.
1663  *
1664  * Note!  This is for pre-ILK only.
1665  */
1666 static void i9xx_disable_pll(struct intel_crtc *crtc)
1667 {
1668         struct drm_device *dev = crtc->base.dev;
1669         struct drm_i915_private *dev_priv = dev->dev_private;
1670         enum pipe pipe = crtc->pipe;
1671
1672         /* Disable DVO 2x clock on both PLLs if necessary */
1673         if (IS_I830(dev) &&
1674             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1675             intel_num_dvo_pipes(dev) == 1) {
1676                 I915_WRITE(DPLL(PIPE_B),
1677                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678                 I915_WRITE(DPLL(PIPE_A),
1679                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1680         }
1681
1682         /* Don't disable pipe or pipe PLLs if needed */
1683         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1685                 return;
1686
1687         /* Make sure the pipe isn't still relying on us */
1688         assert_pipe_disabled(dev_priv, pipe);
1689
1690         I915_WRITE(DPLL(pipe), 0);
1691         POSTING_READ(DPLL(pipe));
1692 }
1693
1694 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696         u32 val = 0;
1697
1698         /* Make sure the pipe isn't still relying on us */
1699         assert_pipe_disabled(dev_priv, pipe);
1700
1701         /*
1702          * Leave integrated clock source and reference clock enabled for pipe B.
1703          * The latter is needed for VGA hotplug / manual detection.
1704          */
1705         if (pipe == PIPE_B)
1706                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707         I915_WRITE(DPLL(pipe), val);
1708         POSTING_READ(DPLL(pipe));
1709
1710 }
1711
1712 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1715         u32 val;
1716
1717         /* Make sure the pipe isn't still relying on us */
1718         assert_pipe_disabled(dev_priv, pipe);
1719
1720         /* Set PLL en = 0 */
1721         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1722         if (pipe != PIPE_A)
1723                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724         I915_WRITE(DPLL(pipe), val);
1725         POSTING_READ(DPLL(pipe));
1726
1727         mutex_lock(&dev_priv->dpio_lock);
1728
1729         /* Disable 10bit clock to display controller */
1730         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731         val &= ~DPIO_DCLKP_EN;
1732         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1733
1734         /* disable left/right clock distribution */
1735         if (pipe != PIPE_B) {
1736                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1739         } else {
1740                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1743         }
1744
1745         mutex_unlock(&dev_priv->dpio_lock);
1746 }
1747
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749                 struct intel_digital_port *dport)
1750 {
1751         u32 port_mask;
1752         int dpll_reg;
1753
1754         switch (dport->port) {
1755         case PORT_B:
1756                 port_mask = DPLL_PORTB_READY_MASK;
1757                 dpll_reg = DPLL(0);
1758                 break;
1759         case PORT_C:
1760                 port_mask = DPLL_PORTC_READY_MASK;
1761                 dpll_reg = DPLL(0);
1762                 break;
1763         case PORT_D:
1764                 port_mask = DPLL_PORTD_READY_MASK;
1765                 dpll_reg = DPIO_PHY_STATUS;
1766                 break;
1767         default:
1768                 BUG();
1769         }
1770
1771         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773                      port_name(dport->port), I915_READ(dpll_reg));
1774 }
1775
1776 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1777 {
1778         struct drm_device *dev = crtc->base.dev;
1779         struct drm_i915_private *dev_priv = dev->dev_private;
1780         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782         if (WARN_ON(pll == NULL))
1783                 return;
1784
1785         WARN_ON(!pll->config.crtc_mask);
1786         if (pll->active == 0) {
1787                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1788                 WARN_ON(pll->on);
1789                 assert_shared_dpll_disabled(dev_priv, pll);
1790
1791                 pll->mode_set(dev_priv, pll);
1792         }
1793 }
1794
1795 /**
1796  * intel_enable_shared_dpll - enable PCH PLL
1797  * @dev_priv: i915 private structure
1798  * @pipe: pipe PLL to enable
1799  *
1800  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801  * drives the transcoder clock.
1802  */
1803 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1804 {
1805         struct drm_device *dev = crtc->base.dev;
1806         struct drm_i915_private *dev_priv = dev->dev_private;
1807         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809         if (WARN_ON(pll == NULL))
1810                 return;
1811
1812         if (WARN_ON(pll->config.crtc_mask == 0))
1813                 return;
1814
1815         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816                       pll->name, pll->active, pll->on,
1817                       crtc->base.base.id);
1818
1819         if (pll->active++) {
1820                 WARN_ON(!pll->on);
1821                 assert_shared_dpll_enabled(dev_priv, pll);
1822                 return;
1823         }
1824         WARN_ON(pll->on);
1825
1826         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1827
1828         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829         pll->enable(dev_priv, pll);
1830         pll->on = true;
1831 }
1832
1833 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1834 {
1835         struct drm_device *dev = crtc->base.dev;
1836         struct drm_i915_private *dev_priv = dev->dev_private;
1837         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1838
1839         /* PCH only available on ILK+ */
1840         BUG_ON(INTEL_INFO(dev)->gen < 5);
1841         if (WARN_ON(pll == NULL))
1842                return;
1843
1844         if (WARN_ON(pll->config.crtc_mask == 0))
1845                 return;
1846
1847         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848                       pll->name, pll->active, pll->on,
1849                       crtc->base.base.id);
1850
1851         if (WARN_ON(pll->active == 0)) {
1852                 assert_shared_dpll_disabled(dev_priv, pll);
1853                 return;
1854         }
1855
1856         assert_shared_dpll_enabled(dev_priv, pll);
1857         WARN_ON(!pll->on);
1858         if (--pll->active)
1859                 return;
1860
1861         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862         pll->disable(dev_priv, pll);
1863         pll->on = false;
1864
1865         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1866 }
1867
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1869                                            enum pipe pipe)
1870 {
1871         struct drm_device *dev = dev_priv->dev;
1872         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874         uint32_t reg, val, pipeconf_val;
1875
1876         /* PCH only available on ILK+ */
1877         BUG_ON(!HAS_PCH_SPLIT(dev));
1878
1879         /* Make sure PCH DPLL is enabled */
1880         assert_shared_dpll_enabled(dev_priv,
1881                                    intel_crtc_to_shared_dpll(intel_crtc));
1882
1883         /* FDI must be feeding us bits for PCH ports */
1884         assert_fdi_tx_enabled(dev_priv, pipe);
1885         assert_fdi_rx_enabled(dev_priv, pipe);
1886
1887         if (HAS_PCH_CPT(dev)) {
1888                 /* Workaround: Set the timing override bit before enabling the
1889                  * pch transcoder. */
1890                 reg = TRANS_CHICKEN2(pipe);
1891                 val = I915_READ(reg);
1892                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893                 I915_WRITE(reg, val);
1894         }
1895
1896         reg = PCH_TRANSCONF(pipe);
1897         val = I915_READ(reg);
1898         pipeconf_val = I915_READ(PIPECONF(pipe));
1899
1900         if (HAS_PCH_IBX(dev_priv->dev)) {
1901                 /*
1902                  * make the BPC in transcoder be consistent with
1903                  * that in pipeconf reg.
1904                  */
1905                 val &= ~PIPECONF_BPC_MASK;
1906                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1907         }
1908
1909         val &= ~TRANS_INTERLACE_MASK;
1910         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911                 if (HAS_PCH_IBX(dev_priv->dev) &&
1912                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1913                         val |= TRANS_LEGACY_INTERLACED_ILK;
1914                 else
1915                         val |= TRANS_INTERLACED;
1916         else
1917                 val |= TRANS_PROGRESSIVE;
1918
1919         I915_WRITE(reg, val | TRANS_ENABLE);
1920         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1922 }
1923
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925                                       enum transcoder cpu_transcoder)
1926 {
1927         u32 val, pipeconf_val;
1928
1929         /* PCH only available on ILK+ */
1930         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1931
1932         /* FDI must be feeding us bits for PCH ports */
1933         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1935
1936         /* Workaround: set timing override bit. */
1937         val = I915_READ(_TRANSA_CHICKEN2);
1938         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939         I915_WRITE(_TRANSA_CHICKEN2, val);
1940
1941         val = TRANS_ENABLE;
1942         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1943
1944         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945             PIPECONF_INTERLACED_ILK)
1946                 val |= TRANS_INTERLACED;
1947         else
1948                 val |= TRANS_PROGRESSIVE;
1949
1950         I915_WRITE(LPT_TRANSCONF, val);
1951         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952                 DRM_ERROR("Failed to enable PCH transcoder\n");
1953 }
1954
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1956                                             enum pipe pipe)
1957 {
1958         struct drm_device *dev = dev_priv->dev;
1959         uint32_t reg, val;
1960
1961         /* FDI relies on the transcoder */
1962         assert_fdi_tx_disabled(dev_priv, pipe);
1963         assert_fdi_rx_disabled(dev_priv, pipe);
1964
1965         /* Ports must be off as well */
1966         assert_pch_ports_disabled(dev_priv, pipe);
1967
1968         reg = PCH_TRANSCONF(pipe);
1969         val = I915_READ(reg);
1970         val &= ~TRANS_ENABLE;
1971         I915_WRITE(reg, val);
1972         /* wait for PCH transcoder off, transcoder state */
1973         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1975
1976         if (!HAS_PCH_IBX(dev)) {
1977                 /* Workaround: Clear the timing override chicken bit again. */
1978                 reg = TRANS_CHICKEN2(pipe);
1979                 val = I915_READ(reg);
1980                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981                 I915_WRITE(reg, val);
1982         }
1983 }
1984
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986 {
1987         u32 val;
1988
1989         val = I915_READ(LPT_TRANSCONF);
1990         val &= ~TRANS_ENABLE;
1991         I915_WRITE(LPT_TRANSCONF, val);
1992         /* wait for PCH transcoder off, transcoder state */
1993         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994                 DRM_ERROR("Failed to disable PCH transcoder\n");
1995
1996         /* Workaround: clear timing override bit. */
1997         val = I915_READ(_TRANSA_CHICKEN2);
1998         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999         I915_WRITE(_TRANSA_CHICKEN2, val);
2000 }
2001
2002 /**
2003  * intel_enable_pipe - enable a pipe, asserting requirements
2004  * @crtc: crtc responsible for the pipe
2005  *
2006  * Enable @crtc's pipe, making sure that various hardware specific requirements
2007  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008  */
2009 static void intel_enable_pipe(struct intel_crtc *crtc)
2010 {
2011         struct drm_device *dev = crtc->base.dev;
2012         struct drm_i915_private *dev_priv = dev->dev_private;
2013         enum pipe pipe = crtc->pipe;
2014         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2015                                                                       pipe);
2016         enum pipe pch_transcoder;
2017         int reg;
2018         u32 val;
2019
2020         assert_planes_disabled(dev_priv, pipe);
2021         assert_cursor_disabled(dev_priv, pipe);
2022         assert_sprites_disabled(dev_priv, pipe);
2023
2024         if (HAS_PCH_LPT(dev_priv->dev))
2025                 pch_transcoder = TRANSCODER_A;
2026         else
2027                 pch_transcoder = pipe;
2028
2029         /*
2030          * A pipe without a PLL won't actually be able to drive bits from
2031          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2032          * need the check.
2033          */
2034         if (!HAS_PCH_SPLIT(dev_priv->dev))
2035                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2036                         assert_dsi_pll_enabled(dev_priv);
2037                 else
2038                         assert_pll_enabled(dev_priv, pipe);
2039         else {
2040                 if (crtc->config->has_pch_encoder) {
2041                         /* if driving the PCH, we need FDI enabled */
2042                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043                         assert_fdi_tx_pll_enabled(dev_priv,
2044                                                   (enum pipe) cpu_transcoder);
2045                 }
2046                 /* FIXME: assert CPU port conditions for SNB+ */
2047         }
2048
2049         reg = PIPECONF(cpu_transcoder);
2050         val = I915_READ(reg);
2051         if (val & PIPECONF_ENABLE) {
2052                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2054                 return;
2055         }
2056
2057         I915_WRITE(reg, val | PIPECONF_ENABLE);
2058         POSTING_READ(reg);
2059 }
2060
2061 /**
2062  * intel_disable_pipe - disable a pipe, asserting requirements
2063  * @crtc: crtc whose pipes is to be disabled
2064  *
2065  * Disable the pipe of @crtc, making sure that various hardware
2066  * specific requirements are met, if applicable, e.g. plane
2067  * disabled, panel fitter off, etc.
2068  *
2069  * Will wait until the pipe has shut down before returning.
2070  */
2071 static void intel_disable_pipe(struct intel_crtc *crtc)
2072 {
2073         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2074         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2075         enum pipe pipe = crtc->pipe;
2076         int reg;
2077         u32 val;
2078
2079         /*
2080          * Make sure planes won't keep trying to pump pixels to us,
2081          * or we might hang the display.
2082          */
2083         assert_planes_disabled(dev_priv, pipe);
2084         assert_cursor_disabled(dev_priv, pipe);
2085         assert_sprites_disabled(dev_priv, pipe);
2086
2087         reg = PIPECONF(cpu_transcoder);
2088         val = I915_READ(reg);
2089         if ((val & PIPECONF_ENABLE) == 0)
2090                 return;
2091
2092         /*
2093          * Double wide has implications for planes
2094          * so best keep it disabled when not needed.
2095          */
2096         if (crtc->config->double_wide)
2097                 val &= ~PIPECONF_DOUBLE_WIDE;
2098
2099         /* Don't disable pipe or pipe PLLs if needed */
2100         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2102                 val &= ~PIPECONF_ENABLE;
2103
2104         I915_WRITE(reg, val);
2105         if ((val & PIPECONF_ENABLE) == 0)
2106                 intel_wait_for_pipe_off(crtc);
2107 }
2108
2109 /*
2110  * Plane regs are double buffered, going from enabled->disabled needs a
2111  * trigger in order to latch.  The display address reg provides this.
2112  */
2113 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2114                                enum plane plane)
2115 {
2116         struct drm_device *dev = dev_priv->dev;
2117         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2118
2119         I915_WRITE(reg, I915_READ(reg));
2120         POSTING_READ(reg);
2121 }
2122
2123 /**
2124  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125  * @plane:  plane to be enabled
2126  * @crtc: crtc for the plane
2127  *
2128  * Enable @plane on @crtc, making sure that the pipe is running first.
2129  */
2130 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131                                           struct drm_crtc *crtc)
2132 {
2133         struct drm_device *dev = plane->dev;
2134         struct drm_i915_private *dev_priv = dev->dev_private;
2135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
2137         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2139
2140         if (intel_crtc->primary_enabled)
2141                 return;
2142
2143         intel_crtc->primary_enabled = true;
2144
2145         dev_priv->display.update_primary_plane(crtc, plane->fb,
2146                                                crtc->x, crtc->y);
2147
2148         /*
2149          * BDW signals flip done immediately if the plane
2150          * is disabled, even if the plane enable is already
2151          * armed to occur at the next vblank :(
2152          */
2153         if (IS_BROADWELL(dev))
2154                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155 }
2156
2157 /**
2158  * intel_disable_primary_hw_plane - disable the primary hardware plane
2159  * @plane: plane to be disabled
2160  * @crtc: crtc for the plane
2161  *
2162  * Disable @plane on @crtc, making sure that the pipe is running first.
2163  */
2164 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165                                            struct drm_crtc *crtc)
2166 {
2167         struct drm_device *dev = plane->dev;
2168         struct drm_i915_private *dev_priv = dev->dev_private;
2169         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170
2171         if (WARN_ON(!intel_crtc->active))
2172                 return;
2173
2174         if (!intel_crtc->primary_enabled)
2175                 return;
2176
2177         intel_crtc->primary_enabled = false;
2178
2179         dev_priv->display.update_primary_plane(crtc, plane->fb,
2180                                                crtc->x, crtc->y);
2181 }
2182
2183 static bool need_vtd_wa(struct drm_device *dev)
2184 {
2185 #ifdef CONFIG_INTEL_IOMMU
2186         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2187                 return true;
2188 #endif
2189         return false;
2190 }
2191
2192 int
2193 intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
2194 {
2195         int tile_height;
2196
2197         tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
2198         return ALIGN(height, tile_height);
2199 }
2200
2201 int
2202 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2203                            struct drm_framebuffer *fb,
2204                            struct intel_engine_cs *pipelined)
2205 {
2206         struct drm_device *dev = fb->dev;
2207         struct drm_i915_private *dev_priv = dev->dev_private;
2208         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2209         u32 alignment;
2210         int ret;
2211
2212         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2213
2214         switch (obj->tiling_mode) {
2215         case I915_TILING_NONE:
2216                 if (INTEL_INFO(dev)->gen >= 9)
2217                         alignment = 256 * 1024;
2218                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2219                         alignment = 128 * 1024;
2220                 else if (INTEL_INFO(dev)->gen >= 4)
2221                         alignment = 4 * 1024;
2222                 else
2223                         alignment = 64 * 1024;
2224                 break;
2225         case I915_TILING_X:
2226                 if (INTEL_INFO(dev)->gen >= 9)
2227                         alignment = 256 * 1024;
2228                 else {
2229                         /* pin() will align the object as required by fence */
2230                         alignment = 0;
2231                 }
2232                 break;
2233         case I915_TILING_Y:
2234                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2235                 return -EINVAL;
2236         default:
2237                 BUG();
2238         }
2239
2240         /* Note that the w/a also requires 64 PTE of padding following the
2241          * bo. We currently fill all unused PTE with the shadow page and so
2242          * we should always have valid PTE following the scanout preventing
2243          * the VT-d warning.
2244          */
2245         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2246                 alignment = 256 * 1024;
2247
2248         /*
2249          * Global gtt pte registers are special registers which actually forward
2250          * writes to a chunk of system memory. Which means that there is no risk
2251          * that the register values disappear as soon as we call
2252          * intel_runtime_pm_put(), so it is correct to wrap only the
2253          * pin/unpin/fence and not more.
2254          */
2255         intel_runtime_pm_get(dev_priv);
2256
2257         dev_priv->mm.interruptible = false;
2258         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2259         if (ret)
2260                 goto err_interruptible;
2261
2262         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2263          * fence, whereas 965+ only requires a fence if using
2264          * framebuffer compression.  For simplicity, we always install
2265          * a fence as the cost is not that onerous.
2266          */
2267         ret = i915_gem_object_get_fence(obj);
2268         if (ret)
2269                 goto err_unpin;
2270
2271         i915_gem_object_pin_fence(obj);
2272
2273         dev_priv->mm.interruptible = true;
2274         intel_runtime_pm_put(dev_priv);
2275         return 0;
2276
2277 err_unpin:
2278         i915_gem_object_unpin_from_display_plane(obj);
2279 err_interruptible:
2280         dev_priv->mm.interruptible = true;
2281         intel_runtime_pm_put(dev_priv);
2282         return ret;
2283 }
2284
2285 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2286 {
2287         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2288
2289         i915_gem_object_unpin_fence(obj);
2290         i915_gem_object_unpin_from_display_plane(obj);
2291 }
2292
2293 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2294  * is assumed to be a power-of-two. */
2295 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2296                                              unsigned int tiling_mode,
2297                                              unsigned int cpp,
2298                                              unsigned int pitch)
2299 {
2300         if (tiling_mode != I915_TILING_NONE) {
2301                 unsigned int tile_rows, tiles;
2302
2303                 tile_rows = *y / 8;
2304                 *y %= 8;
2305
2306                 tiles = *x / (512/cpp);
2307                 *x %= 512/cpp;
2308
2309                 return tile_rows * pitch * 8 + tiles * 4096;
2310         } else {
2311                 unsigned int offset;
2312
2313                 offset = *y * pitch + *x * cpp;
2314                 *y = 0;
2315                 *x = (offset & 4095) / cpp;
2316                 return offset & -4096;
2317         }
2318 }
2319
2320 static int i9xx_format_to_fourcc(int format)
2321 {
2322         switch (format) {
2323         case DISPPLANE_8BPP:
2324                 return DRM_FORMAT_C8;
2325         case DISPPLANE_BGRX555:
2326                 return DRM_FORMAT_XRGB1555;
2327         case DISPPLANE_BGRX565:
2328                 return DRM_FORMAT_RGB565;
2329         default:
2330         case DISPPLANE_BGRX888:
2331                 return DRM_FORMAT_XRGB8888;
2332         case DISPPLANE_RGBX888:
2333                 return DRM_FORMAT_XBGR8888;
2334         case DISPPLANE_BGRX101010:
2335                 return DRM_FORMAT_XRGB2101010;
2336         case DISPPLANE_RGBX101010:
2337                 return DRM_FORMAT_XBGR2101010;
2338         }
2339 }
2340
2341 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2342 {
2343         switch (format) {
2344         case PLANE_CTL_FORMAT_RGB_565:
2345                 return DRM_FORMAT_RGB565;
2346         default:
2347         case PLANE_CTL_FORMAT_XRGB_8888:
2348                 if (rgb_order) {
2349                         if (alpha)
2350                                 return DRM_FORMAT_ABGR8888;
2351                         else
2352                                 return DRM_FORMAT_XBGR8888;
2353                 } else {
2354                         if (alpha)
2355                                 return DRM_FORMAT_ARGB8888;
2356                         else
2357                                 return DRM_FORMAT_XRGB8888;
2358                 }
2359         case PLANE_CTL_FORMAT_XRGB_2101010:
2360                 if (rgb_order)
2361                         return DRM_FORMAT_XBGR2101010;
2362                 else
2363                         return DRM_FORMAT_XRGB2101010;
2364         }
2365 }
2366
2367 static bool
2368 intel_alloc_plane_obj(struct intel_crtc *crtc,
2369                       struct intel_initial_plane_config *plane_config)
2370 {
2371         struct drm_device *dev = crtc->base.dev;
2372         struct drm_i915_gem_object *obj = NULL;
2373         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2374         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2375         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2376                                     PAGE_SIZE);
2377
2378         size_aligned -= base_aligned;
2379
2380         if (plane_config->size == 0)
2381                 return false;
2382
2383         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2384                                                              base_aligned,
2385                                                              base_aligned,
2386                                                              size_aligned);
2387         if (!obj)
2388                 return false;
2389
2390         obj->tiling_mode = plane_config->tiling;
2391         if (obj->tiling_mode == I915_TILING_X)
2392                 obj->stride = crtc->base.primary->fb->pitches[0];
2393
2394         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2395         mode_cmd.width = crtc->base.primary->fb->width;
2396         mode_cmd.height = crtc->base.primary->fb->height;
2397         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2398
2399         mutex_lock(&dev->struct_mutex);
2400
2401         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2402                                    &mode_cmd, obj)) {
2403                 DRM_DEBUG_KMS("intel fb init failed\n");
2404                 goto out_unref_obj;
2405         }
2406
2407         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2408         mutex_unlock(&dev->struct_mutex);
2409
2410         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2411         return true;
2412
2413 out_unref_obj:
2414         drm_gem_object_unreference(&obj->base);
2415         mutex_unlock(&dev->struct_mutex);
2416         return false;
2417 }
2418
2419 static void
2420 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2421                      struct intel_initial_plane_config *plane_config)
2422 {
2423         struct drm_device *dev = intel_crtc->base.dev;
2424         struct drm_i915_private *dev_priv = dev->dev_private;
2425         struct drm_crtc *c;
2426         struct intel_crtc *i;
2427         struct drm_i915_gem_object *obj;
2428
2429         if (!intel_crtc->base.primary->fb)
2430                 return;
2431
2432         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2433                 return;
2434
2435         kfree(intel_crtc->base.primary->fb);
2436         intel_crtc->base.primary->fb = NULL;
2437
2438         /*
2439          * Failed to alloc the obj, check to see if we should share
2440          * an fb with another CRTC instead
2441          */
2442         for_each_crtc(dev, c) {
2443                 i = to_intel_crtc(c);
2444
2445                 if (c == &intel_crtc->base)
2446                         continue;
2447
2448                 if (!i->active)
2449                         continue;
2450
2451                 obj = intel_fb_obj(c->primary->fb);
2452                 if (obj == NULL)
2453                         continue;
2454
2455                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2456                         if (obj->tiling_mode != I915_TILING_NONE)
2457                                 dev_priv->preserve_bios_swizzle = true;
2458
2459                         drm_framebuffer_reference(c->primary->fb);
2460                         intel_crtc->base.primary->fb = c->primary->fb;
2461                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2462                         break;
2463                 }
2464         }
2465 }
2466
2467 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2468                                       struct drm_framebuffer *fb,
2469                                       int x, int y)
2470 {
2471         struct drm_device *dev = crtc->dev;
2472         struct drm_i915_private *dev_priv = dev->dev_private;
2473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2474         struct drm_i915_gem_object *obj;
2475         int plane = intel_crtc->plane;
2476         unsigned long linear_offset;
2477         u32 dspcntr;
2478         u32 reg = DSPCNTR(plane);
2479         int pixel_size;
2480
2481         if (!intel_crtc->primary_enabled) {
2482                 I915_WRITE(reg, 0);
2483                 if (INTEL_INFO(dev)->gen >= 4)
2484                         I915_WRITE(DSPSURF(plane), 0);
2485                 else
2486                         I915_WRITE(DSPADDR(plane), 0);
2487                 POSTING_READ(reg);
2488                 return;
2489         }
2490
2491         obj = intel_fb_obj(fb);
2492         if (WARN_ON(obj == NULL))
2493                 return;
2494
2495         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2496
2497         dspcntr = DISPPLANE_GAMMA_ENABLE;
2498
2499         dspcntr |= DISPLAY_PLANE_ENABLE;
2500
2501         if (INTEL_INFO(dev)->gen < 4) {
2502                 if (intel_crtc->pipe == PIPE_B)
2503                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2504
2505                 /* pipesrc and dspsize control the size that is scaled from,
2506                  * which should always be the user's requested size.
2507                  */
2508                 I915_WRITE(DSPSIZE(plane),
2509                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2510                            (intel_crtc->config->pipe_src_w - 1));
2511                 I915_WRITE(DSPPOS(plane), 0);
2512         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2513                 I915_WRITE(PRIMSIZE(plane),
2514                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2515                            (intel_crtc->config->pipe_src_w - 1));
2516                 I915_WRITE(PRIMPOS(plane), 0);
2517                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2518         }
2519
2520         switch (fb->pixel_format) {
2521         case DRM_FORMAT_C8:
2522                 dspcntr |= DISPPLANE_8BPP;
2523                 break;
2524         case DRM_FORMAT_XRGB1555:
2525         case DRM_FORMAT_ARGB1555:
2526                 dspcntr |= DISPPLANE_BGRX555;
2527                 break;
2528         case DRM_FORMAT_RGB565:
2529                 dspcntr |= DISPPLANE_BGRX565;
2530                 break;
2531         case DRM_FORMAT_XRGB8888:
2532         case DRM_FORMAT_ARGB8888:
2533                 dspcntr |= DISPPLANE_BGRX888;
2534                 break;
2535         case DRM_FORMAT_XBGR8888:
2536         case DRM_FORMAT_ABGR8888:
2537                 dspcntr |= DISPPLANE_RGBX888;
2538                 break;
2539         case DRM_FORMAT_XRGB2101010:
2540         case DRM_FORMAT_ARGB2101010:
2541                 dspcntr |= DISPPLANE_BGRX101010;
2542                 break;
2543         case DRM_FORMAT_XBGR2101010:
2544         case DRM_FORMAT_ABGR2101010:
2545                 dspcntr |= DISPPLANE_RGBX101010;
2546                 break;
2547         default:
2548                 BUG();
2549         }
2550
2551         if (INTEL_INFO(dev)->gen >= 4 &&
2552             obj->tiling_mode != I915_TILING_NONE)
2553                 dspcntr |= DISPPLANE_TILED;
2554
2555         if (IS_G4X(dev))
2556                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2557
2558         linear_offset = y * fb->pitches[0] + x * pixel_size;
2559
2560         if (INTEL_INFO(dev)->gen >= 4) {
2561                 intel_crtc->dspaddr_offset =
2562                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2563                                                        pixel_size,
2564                                                        fb->pitches[0]);
2565                 linear_offset -= intel_crtc->dspaddr_offset;
2566         } else {
2567                 intel_crtc->dspaddr_offset = linear_offset;
2568         }
2569
2570         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2571                 dspcntr |= DISPPLANE_ROTATE_180;
2572
2573                 x += (intel_crtc->config->pipe_src_w - 1);
2574                 y += (intel_crtc->config->pipe_src_h - 1);
2575
2576                 /* Finding the last pixel of the last line of the display
2577                 data and adding to linear_offset*/
2578                 linear_offset +=
2579                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2580                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2581         }
2582
2583         I915_WRITE(reg, dspcntr);
2584
2585         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2586                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2587                       fb->pitches[0]);
2588         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2589         if (INTEL_INFO(dev)->gen >= 4) {
2590                 I915_WRITE(DSPSURF(plane),
2591                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2592                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2593                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2594         } else
2595                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2596         POSTING_READ(reg);
2597 }
2598
2599 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2600                                           struct drm_framebuffer *fb,
2601                                           int x, int y)
2602 {
2603         struct drm_device *dev = crtc->dev;
2604         struct drm_i915_private *dev_priv = dev->dev_private;
2605         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2606         struct drm_i915_gem_object *obj;
2607         int plane = intel_crtc->plane;
2608         unsigned long linear_offset;
2609         u32 dspcntr;
2610         u32 reg = DSPCNTR(plane);
2611         int pixel_size;
2612
2613         if (!intel_crtc->primary_enabled) {
2614                 I915_WRITE(reg, 0);
2615                 I915_WRITE(DSPSURF(plane), 0);
2616                 POSTING_READ(reg);
2617                 return;
2618         }
2619
2620         obj = intel_fb_obj(fb);
2621         if (WARN_ON(obj == NULL))
2622                 return;
2623
2624         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2625
2626         dspcntr = DISPPLANE_GAMMA_ENABLE;
2627
2628         dspcntr |= DISPLAY_PLANE_ENABLE;
2629
2630         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2631                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2632
2633         switch (fb->pixel_format) {
2634         case DRM_FORMAT_C8:
2635                 dspcntr |= DISPPLANE_8BPP;
2636                 break;
2637         case DRM_FORMAT_RGB565:
2638                 dspcntr |= DISPPLANE_BGRX565;
2639                 break;
2640         case DRM_FORMAT_XRGB8888:
2641         case DRM_FORMAT_ARGB8888:
2642                 dspcntr |= DISPPLANE_BGRX888;
2643                 break;
2644         case DRM_FORMAT_XBGR8888:
2645         case DRM_FORMAT_ABGR8888:
2646                 dspcntr |= DISPPLANE_RGBX888;
2647                 break;
2648         case DRM_FORMAT_XRGB2101010:
2649         case DRM_FORMAT_ARGB2101010:
2650                 dspcntr |= DISPPLANE_BGRX101010;
2651                 break;
2652         case DRM_FORMAT_XBGR2101010:
2653         case DRM_FORMAT_ABGR2101010:
2654                 dspcntr |= DISPPLANE_RGBX101010;
2655                 break;
2656         default:
2657                 BUG();
2658         }
2659
2660         if (obj->tiling_mode != I915_TILING_NONE)
2661                 dspcntr |= DISPPLANE_TILED;
2662
2663         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2664                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2665
2666         linear_offset = y * fb->pitches[0] + x * pixel_size;
2667         intel_crtc->dspaddr_offset =
2668                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2669                                                pixel_size,
2670                                                fb->pitches[0]);
2671         linear_offset -= intel_crtc->dspaddr_offset;
2672         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2673                 dspcntr |= DISPPLANE_ROTATE_180;
2674
2675                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2676                         x += (intel_crtc->config->pipe_src_w - 1);
2677                         y += (intel_crtc->config->pipe_src_h - 1);
2678
2679                         /* Finding the last pixel of the last line of the display
2680                         data and adding to linear_offset*/
2681                         linear_offset +=
2682                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2683                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2684                 }
2685         }
2686
2687         I915_WRITE(reg, dspcntr);
2688
2689         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2690                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2691                       fb->pitches[0]);
2692         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2693         I915_WRITE(DSPSURF(plane),
2694                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2695         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2696                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2697         } else {
2698                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2699                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2700         }
2701         POSTING_READ(reg);
2702 }
2703
2704 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2705                                          struct drm_framebuffer *fb,
2706                                          int x, int y)
2707 {
2708         struct drm_device *dev = crtc->dev;
2709         struct drm_i915_private *dev_priv = dev->dev_private;
2710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2711         struct intel_framebuffer *intel_fb;
2712         struct drm_i915_gem_object *obj;
2713         int pipe = intel_crtc->pipe;
2714         u32 plane_ctl, stride;
2715
2716         if (!intel_crtc->primary_enabled) {
2717                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2718                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2719                 POSTING_READ(PLANE_CTL(pipe, 0));
2720                 return;
2721         }
2722
2723         plane_ctl = PLANE_CTL_ENABLE |
2724                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2725                     PLANE_CTL_PIPE_CSC_ENABLE;
2726
2727         switch (fb->pixel_format) {
2728         case DRM_FORMAT_RGB565:
2729                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2730                 break;
2731         case DRM_FORMAT_XRGB8888:
2732                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2733                 break;
2734         case DRM_FORMAT_ARGB8888:
2735                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2736                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2737                 break;
2738         case DRM_FORMAT_XBGR8888:
2739                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2740                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2741                 break;
2742         case DRM_FORMAT_ABGR8888:
2743                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2744                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2745                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2746                 break;
2747         case DRM_FORMAT_XRGB2101010:
2748                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2749                 break;
2750         case DRM_FORMAT_XBGR2101010:
2751                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2752                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2753                 break;
2754         default:
2755                 BUG();
2756         }
2757
2758         intel_fb = to_intel_framebuffer(fb);
2759         obj = intel_fb->obj;
2760
2761         /*
2762          * The stride is either expressed as a multiple of 64 bytes chunks for
2763          * linear buffers or in number of tiles for tiled buffers.
2764          */
2765         switch (obj->tiling_mode) {
2766         case I915_TILING_NONE:
2767                 stride = fb->pitches[0] >> 6;
2768                 break;
2769         case I915_TILING_X:
2770                 plane_ctl |= PLANE_CTL_TILED_X;
2771                 stride = fb->pitches[0] >> 9;
2772                 break;
2773         default:
2774                 BUG();
2775         }
2776
2777         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2778         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2779                 plane_ctl |= PLANE_CTL_ROTATE_180;
2780
2781         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2782
2783         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2784                       i915_gem_obj_ggtt_offset(obj),
2785                       x, y, fb->width, fb->height,
2786                       fb->pitches[0]);
2787
2788         I915_WRITE(PLANE_POS(pipe, 0), 0);
2789         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2790         I915_WRITE(PLANE_SIZE(pipe, 0),
2791                    (intel_crtc->config->pipe_src_h - 1) << 16 |
2792                    (intel_crtc->config->pipe_src_w - 1));
2793         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2794         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2795
2796         POSTING_READ(PLANE_SURF(pipe, 0));
2797 }
2798
2799 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2800 static int
2801 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2802                            int x, int y, enum mode_set_atomic state)
2803 {
2804         struct drm_device *dev = crtc->dev;
2805         struct drm_i915_private *dev_priv = dev->dev_private;
2806
2807         if (dev_priv->display.disable_fbc)
2808                 dev_priv->display.disable_fbc(dev);
2809
2810         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2811
2812         return 0;
2813 }
2814
2815 static void intel_complete_page_flips(struct drm_device *dev)
2816 {
2817         struct drm_crtc *crtc;
2818
2819         for_each_crtc(dev, crtc) {
2820                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2821                 enum plane plane = intel_crtc->plane;
2822
2823                 intel_prepare_page_flip(dev, plane);
2824                 intel_finish_page_flip_plane(dev, plane);
2825         }
2826 }
2827
2828 static void intel_update_primary_planes(struct drm_device *dev)
2829 {
2830         struct drm_i915_private *dev_priv = dev->dev_private;
2831         struct drm_crtc *crtc;
2832
2833         for_each_crtc(dev, crtc) {
2834                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2835
2836                 drm_modeset_lock(&crtc->mutex, NULL);
2837                 /*
2838                  * FIXME: Once we have proper support for primary planes (and
2839                  * disabling them without disabling the entire crtc) allow again
2840                  * a NULL crtc->primary->fb.
2841                  */
2842                 if (intel_crtc->active && crtc->primary->fb)
2843                         dev_priv->display.update_primary_plane(crtc,
2844                                                                crtc->primary->fb,
2845                                                                crtc->x,
2846                                                                crtc->y);
2847                 drm_modeset_unlock(&crtc->mutex);
2848         }
2849 }
2850
2851 void intel_prepare_reset(struct drm_device *dev)
2852 {
2853         struct drm_i915_private *dev_priv = to_i915(dev);
2854         struct intel_crtc *crtc;
2855
2856         /* no reset support for gen2 */
2857         if (IS_GEN2(dev))
2858                 return;
2859
2860         /* reset doesn't touch the display */
2861         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2862                 return;
2863
2864         drm_modeset_lock_all(dev);
2865
2866         /*
2867          * Disabling the crtcs gracefully seems nicer. Also the
2868          * g33 docs say we should at least disable all the planes.
2869          */
2870         for_each_intel_crtc(dev, crtc) {
2871                 if (crtc->active)
2872                         dev_priv->display.crtc_disable(&crtc->base);
2873         }
2874 }
2875
2876 void intel_finish_reset(struct drm_device *dev)
2877 {
2878         struct drm_i915_private *dev_priv = to_i915(dev);
2879
2880         /*
2881          * Flips in the rings will be nuked by the reset,
2882          * so complete all pending flips so that user space
2883          * will get its events and not get stuck.
2884          */
2885         intel_complete_page_flips(dev);
2886
2887         /* no reset support for gen2 */
2888         if (IS_GEN2(dev))
2889                 return;
2890
2891         /* reset doesn't touch the display */
2892         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2893                 /*
2894                  * Flips in the rings have been nuked by the reset,
2895                  * so update the base address of all primary
2896                  * planes to the the last fb to make sure we're
2897                  * showing the correct fb after a reset.
2898                  */
2899                 intel_update_primary_planes(dev);
2900                 return;
2901         }
2902
2903         /*
2904          * The display has been reset as well,
2905          * so need a full re-initialization.
2906          */
2907         intel_runtime_pm_disable_interrupts(dev_priv);
2908         intel_runtime_pm_enable_interrupts(dev_priv);
2909
2910         intel_modeset_init_hw(dev);
2911
2912         spin_lock_irq(&dev_priv->irq_lock);
2913         if (dev_priv->display.hpd_irq_setup)
2914                 dev_priv->display.hpd_irq_setup(dev);
2915         spin_unlock_irq(&dev_priv->irq_lock);
2916
2917         intel_modeset_setup_hw_state(dev, true);
2918
2919         intel_hpd_init(dev_priv);
2920
2921         drm_modeset_unlock_all(dev);
2922 }
2923
2924 static int
2925 intel_finish_fb(struct drm_framebuffer *old_fb)
2926 {
2927         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2928         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2929         bool was_interruptible = dev_priv->mm.interruptible;
2930         int ret;
2931
2932         /* Big Hammer, we also need to ensure that any pending
2933          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2934          * current scanout is retired before unpinning the old
2935          * framebuffer.
2936          *
2937          * This should only fail upon a hung GPU, in which case we
2938          * can safely continue.
2939          */
2940         dev_priv->mm.interruptible = false;
2941         ret = i915_gem_object_finish_gpu(obj);
2942         dev_priv->mm.interruptible = was_interruptible;
2943
2944         return ret;
2945 }
2946
2947 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2948 {
2949         struct drm_device *dev = crtc->dev;
2950         struct drm_i915_private *dev_priv = dev->dev_private;
2951         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2952         bool pending;
2953
2954         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2955             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2956                 return false;
2957
2958         spin_lock_irq(&dev->event_lock);
2959         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2960         spin_unlock_irq(&dev->event_lock);
2961
2962         return pending;
2963 }
2964
2965 static void intel_update_pipe_size(struct intel_crtc *crtc)
2966 {
2967         struct drm_device *dev = crtc->base.dev;
2968         struct drm_i915_private *dev_priv = dev->dev_private;
2969         const struct drm_display_mode *adjusted_mode;
2970
2971         if (!i915.fastboot)
2972                 return;
2973
2974         /*
2975          * Update pipe size and adjust fitter if needed: the reason for this is
2976          * that in compute_mode_changes we check the native mode (not the pfit
2977          * mode) to see if we can flip rather than do a full mode set. In the
2978          * fastboot case, we'll flip, but if we don't update the pipesrc and
2979          * pfit state, we'll end up with a big fb scanned out into the wrong
2980          * sized surface.
2981          *
2982          * To fix this properly, we need to hoist the checks up into
2983          * compute_mode_changes (or above), check the actual pfit state and
2984          * whether the platform allows pfit disable with pipe active, and only
2985          * then update the pipesrc and pfit state, even on the flip path.
2986          */
2987
2988         adjusted_mode = &crtc->config->base.adjusted_mode;
2989
2990         I915_WRITE(PIPESRC(crtc->pipe),
2991                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2992                    (adjusted_mode->crtc_vdisplay - 1));
2993         if (!crtc->config->pch_pfit.enabled &&
2994             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2995              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2996                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2997                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2998                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2999         }
3000         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3001         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3002 }
3003
3004 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3005 {
3006         struct drm_device *dev = crtc->dev;
3007         struct drm_i915_private *dev_priv = dev->dev_private;
3008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3009         int pipe = intel_crtc->pipe;
3010         u32 reg, temp;
3011
3012         /* enable normal train */
3013         reg = FDI_TX_CTL(pipe);
3014         temp = I915_READ(reg);
3015         if (IS_IVYBRIDGE(dev)) {
3016                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3017                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3018         } else {
3019                 temp &= ~FDI_LINK_TRAIN_NONE;
3020                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3021         }
3022         I915_WRITE(reg, temp);
3023
3024         reg = FDI_RX_CTL(pipe);
3025         temp = I915_READ(reg);
3026         if (HAS_PCH_CPT(dev)) {
3027                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3028                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3029         } else {
3030                 temp &= ~FDI_LINK_TRAIN_NONE;
3031                 temp |= FDI_LINK_TRAIN_NONE;
3032         }
3033         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3034
3035         /* wait one idle pattern time */
3036         POSTING_READ(reg);
3037         udelay(1000);
3038
3039         /* IVB wants error correction enabled */
3040         if (IS_IVYBRIDGE(dev))
3041                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3042                            FDI_FE_ERRC_ENABLE);
3043 }
3044
3045 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3046 {
3047         return crtc->base.enabled && crtc->active &&
3048                 crtc->config->has_pch_encoder;
3049 }
3050
3051 static void ivb_modeset_global_resources(struct drm_device *dev)
3052 {
3053         struct drm_i915_private *dev_priv = dev->dev_private;
3054         struct intel_crtc *pipe_B_crtc =
3055                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3056         struct intel_crtc *pipe_C_crtc =
3057                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3058         uint32_t temp;
3059
3060         /*
3061          * When everything is off disable fdi C so that we could enable fdi B
3062          * with all lanes. Note that we don't care about enabled pipes without
3063          * an enabled pch encoder.
3064          */
3065         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3066             !pipe_has_enabled_pch(pipe_C_crtc)) {
3067                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3068                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3069
3070                 temp = I915_READ(SOUTH_CHICKEN1);
3071                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3072                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3073                 I915_WRITE(SOUTH_CHICKEN1, temp);
3074         }
3075 }
3076
3077 /* The FDI link training functions for ILK/Ibexpeak. */
3078 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3079 {
3080         struct drm_device *dev = crtc->dev;
3081         struct drm_i915_private *dev_priv = dev->dev_private;
3082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3083         int pipe = intel_crtc->pipe;
3084         u32 reg, temp, tries;
3085
3086         /* FDI needs bits from pipe first */
3087         assert_pipe_enabled(dev_priv, pipe);
3088
3089         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3090            for train result */
3091         reg = FDI_RX_IMR(pipe);
3092         temp = I915_READ(reg);
3093         temp &= ~FDI_RX_SYMBOL_LOCK;
3094         temp &= ~FDI_RX_BIT_LOCK;
3095         I915_WRITE(reg, temp);
3096         I915_READ(reg);
3097         udelay(150);
3098
3099         /* enable CPU FDI TX and PCH FDI RX */
3100         reg = FDI_TX_CTL(pipe);
3101         temp = I915_READ(reg);
3102         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3103         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3104         temp &= ~FDI_LINK_TRAIN_NONE;
3105         temp |= FDI_LINK_TRAIN_PATTERN_1;
3106         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3107
3108         reg = FDI_RX_CTL(pipe);
3109         temp = I915_READ(reg);
3110         temp &= ~FDI_LINK_TRAIN_NONE;
3111         temp |= FDI_LINK_TRAIN_PATTERN_1;
3112         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3113
3114         POSTING_READ(reg);
3115         udelay(150);
3116
3117         /* Ironlake workaround, enable clock pointer after FDI enable*/
3118         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3119         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3120                    FDI_RX_PHASE_SYNC_POINTER_EN);
3121
3122         reg = FDI_RX_IIR(pipe);
3123         for (tries = 0; tries < 5; tries++) {
3124                 temp = I915_READ(reg);
3125                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3126
3127                 if ((temp & FDI_RX_BIT_LOCK)) {
3128                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3129                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3130                         break;
3131                 }
3132         }
3133         if (tries == 5)
3134                 DRM_ERROR("FDI train 1 fail!\n");
3135
3136         /* Train 2 */
3137         reg = FDI_TX_CTL(pipe);
3138         temp = I915_READ(reg);
3139         temp &= ~FDI_LINK_TRAIN_NONE;
3140         temp |= FDI_LINK_TRAIN_PATTERN_2;
3141         I915_WRITE(reg, temp);
3142
3143         reg = FDI_RX_CTL(pipe);
3144         temp = I915_READ(reg);
3145         temp &= ~FDI_LINK_TRAIN_NONE;
3146         temp |= FDI_LINK_TRAIN_PATTERN_2;
3147         I915_WRITE(reg, temp);
3148
3149         POSTING_READ(reg);
3150         udelay(150);
3151
3152         reg = FDI_RX_IIR(pipe);
3153         for (tries = 0; tries < 5; tries++) {
3154                 temp = I915_READ(reg);
3155                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3156
3157                 if (temp & FDI_RX_SYMBOL_LOCK) {
3158                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3159                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3160                         break;
3161                 }
3162         }
3163         if (tries == 5)
3164                 DRM_ERROR("FDI train 2 fail!\n");
3165
3166         DRM_DEBUG_KMS("FDI train done\n");
3167
3168 }
3169
3170 static const int snb_b_fdi_train_param[] = {
3171         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3172         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3173         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3174         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3175 };
3176
3177 /* The FDI link training functions for SNB/Cougarpoint. */
3178 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3179 {
3180         struct drm_device *dev = crtc->dev;
3181         struct drm_i915_private *dev_priv = dev->dev_private;
3182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3183         int pipe = intel_crtc->pipe;
3184         u32 reg, temp, i, retry;
3185
3186         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3187            for train result */
3188         reg = FDI_RX_IMR(pipe);
3189         temp = I915_READ(reg);
3190         temp &= ~FDI_RX_SYMBOL_LOCK;
3191         temp &= ~FDI_RX_BIT_LOCK;
3192         I915_WRITE(reg, temp);
3193
3194         POSTING_READ(reg);
3195         udelay(150);
3196
3197         /* enable CPU FDI TX and PCH FDI RX */
3198         reg = FDI_TX_CTL(pipe);
3199         temp = I915_READ(reg);
3200         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3201         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3202         temp &= ~FDI_LINK_TRAIN_NONE;
3203         temp |= FDI_LINK_TRAIN_PATTERN_1;
3204         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3205         /* SNB-B */
3206         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3207         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3208
3209         I915_WRITE(FDI_RX_MISC(pipe),
3210                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3211
3212         reg = FDI_RX_CTL(pipe);
3213         temp = I915_READ(reg);
3214         if (HAS_PCH_CPT(dev)) {
3215                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3216                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3217         } else {
3218                 temp &= ~FDI_LINK_TRAIN_NONE;
3219                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3220         }
3221         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3222
3223         POSTING_READ(reg);
3224         udelay(150);
3225
3226         for (i = 0; i < 4; i++) {
3227                 reg = FDI_TX_CTL(pipe);
3228                 temp = I915_READ(reg);
3229                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3230                 temp |= snb_b_fdi_train_param[i];
3231                 I915_WRITE(reg, temp);
3232
3233                 POSTING_READ(reg);
3234                 udelay(500);
3235
3236                 for (retry = 0; retry < 5; retry++) {
3237                         reg = FDI_RX_IIR(pipe);
3238                         temp = I915_READ(reg);
3239                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3240                         if (temp & FDI_RX_BIT_LOCK) {
3241                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3242                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3243                                 break;
3244                         }
3245                         udelay(50);
3246                 }
3247                 if (retry < 5)
3248                         break;
3249         }
3250         if (i == 4)
3251                 DRM_ERROR("FDI train 1 fail!\n");
3252
3253         /* Train 2 */
3254         reg = FDI_TX_CTL(pipe);
3255         temp = I915_READ(reg);
3256         temp &= ~FDI_LINK_TRAIN_NONE;
3257         temp |= FDI_LINK_TRAIN_PATTERN_2;
3258         if (IS_GEN6(dev)) {
3259                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3260                 /* SNB-B */
3261                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3262         }
3263         I915_WRITE(reg, temp);
3264
3265         reg = FDI_RX_CTL(pipe);
3266         temp = I915_READ(reg);
3267         if (HAS_PCH_CPT(dev)) {
3268                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3269                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3270         } else {
3271                 temp &= ~FDI_LINK_TRAIN_NONE;
3272                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3273         }
3274         I915_WRITE(reg, temp);
3275
3276         POSTING_READ(reg);
3277         udelay(150);
3278
3279         for (i = 0; i < 4; i++) {
3280                 reg = FDI_TX_CTL(pipe);
3281                 temp = I915_READ(reg);
3282                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3283                 temp |= snb_b_fdi_train_param[i];
3284                 I915_WRITE(reg, temp);
3285
3286                 POSTING_READ(reg);
3287                 udelay(500);
3288
3289                 for (retry = 0; retry < 5; retry++) {
3290                         reg = FDI_RX_IIR(pipe);
3291                         temp = I915_READ(reg);
3292                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3293                         if (temp & FDI_RX_SYMBOL_LOCK) {
3294                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3295                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3296                                 break;
3297                         }
3298                         udelay(50);
3299                 }
3300                 if (retry < 5)
3301                         break;
3302         }
3303         if (i == 4)
3304                 DRM_ERROR("FDI train 2 fail!\n");
3305
3306         DRM_DEBUG_KMS("FDI train done.\n");
3307 }
3308
3309 /* Manual link training for Ivy Bridge A0 parts */
3310 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3311 {
3312         struct drm_device *dev = crtc->dev;
3313         struct drm_i915_private *dev_priv = dev->dev_private;
3314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3315         int pipe = intel_crtc->pipe;
3316         u32 reg, temp, i, j;
3317
3318         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3319            for train result */
3320         reg = FDI_RX_IMR(pipe);
3321         temp = I915_READ(reg);
3322         temp &= ~FDI_RX_SYMBOL_LOCK;
3323         temp &= ~FDI_RX_BIT_LOCK;
3324         I915_WRITE(reg, temp);
3325
3326         POSTING_READ(reg);
3327         udelay(150);
3328
3329         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3330                       I915_READ(FDI_RX_IIR(pipe)));
3331
3332         /* Try each vswing and preemphasis setting twice before moving on */
3333         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3334                 /* disable first in case we need to retry */
3335                 reg = FDI_TX_CTL(pipe);
3336                 temp = I915_READ(reg);
3337                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3338                 temp &= ~FDI_TX_ENABLE;
3339                 I915_WRITE(reg, temp);
3340
3341                 reg = FDI_RX_CTL(pipe);
3342                 temp = I915_READ(reg);
3343                 temp &= ~FDI_LINK_TRAIN_AUTO;
3344                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3345                 temp &= ~FDI_RX_ENABLE;
3346                 I915_WRITE(reg, temp);
3347
3348                 /* enable CPU FDI TX and PCH FDI RX */
3349                 reg = FDI_TX_CTL(pipe);
3350                 temp = I915_READ(reg);
3351                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3352                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3353                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3354                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3355                 temp |= snb_b_fdi_train_param[j/2];
3356                 temp |= FDI_COMPOSITE_SYNC;
3357                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3358
3359                 I915_WRITE(FDI_RX_MISC(pipe),
3360                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3361
3362                 reg = FDI_RX_CTL(pipe);
3363                 temp = I915_READ(reg);
3364                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3365                 temp |= FDI_COMPOSITE_SYNC;
3366                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3367
3368                 POSTING_READ(reg);
3369                 udelay(1); /* should be 0.5us */
3370
3371                 for (i = 0; i < 4; i++) {
3372                         reg = FDI_RX_IIR(pipe);
3373                         temp = I915_READ(reg);
3374                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3375
3376                         if (temp & FDI_RX_BIT_LOCK ||
3377                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3378                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3379                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3380                                               i);
3381                                 break;
3382                         }
3383                         udelay(1); /* should be 0.5us */
3384                 }
3385                 if (i == 4) {
3386                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3387                         continue;
3388                 }
3389
3390                 /* Train 2 */
3391                 reg = FDI_TX_CTL(pipe);
3392                 temp = I915_READ(reg);
3393                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3394                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3395                 I915_WRITE(reg, temp);
3396
3397                 reg = FDI_RX_CTL(pipe);
3398                 temp = I915_READ(reg);
3399                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3400                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3401                 I915_WRITE(reg, temp);
3402
3403                 POSTING_READ(reg);
3404                 udelay(2); /* should be 1.5us */
3405
3406                 for (i = 0; i < 4; i++) {
3407                         reg = FDI_RX_IIR(pipe);
3408                         temp = I915_READ(reg);
3409                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3410
3411                         if (temp & FDI_RX_SYMBOL_LOCK ||
3412                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3413                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3414                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3415                                               i);
3416                                 goto train_done;
3417                         }
3418                         udelay(2); /* should be 1.5us */
3419                 }
3420                 if (i == 4)
3421                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3422         }
3423
3424 train_done:
3425         DRM_DEBUG_KMS("FDI train done.\n");
3426 }
3427
3428 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3429 {
3430         struct drm_device *dev = intel_crtc->base.dev;
3431         struct drm_i915_private *dev_priv = dev->dev_private;
3432         int pipe = intel_crtc->pipe;
3433         u32 reg, temp;
3434
3435
3436         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3437         reg = FDI_RX_CTL(pipe);
3438         temp = I915_READ(reg);
3439         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3440         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3441         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3442         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3443
3444         POSTING_READ(reg);
3445         udelay(200);
3446
3447         /* Switch from Rawclk to PCDclk */
3448         temp = I915_READ(reg);
3449         I915_WRITE(reg, temp | FDI_PCDCLK);
3450
3451         POSTING_READ(reg);
3452         udelay(200);
3453
3454         /* Enable CPU FDI TX PLL, always on for Ironlake */
3455         reg = FDI_TX_CTL(pipe);
3456         temp = I915_READ(reg);
3457         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3458                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3459
3460                 POSTING_READ(reg);
3461                 udelay(100);
3462         }
3463 }
3464
3465 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3466 {
3467         struct drm_device *dev = intel_crtc->base.dev;
3468         struct drm_i915_private *dev_priv = dev->dev_private;
3469         int pipe = intel_crtc->pipe;
3470         u32 reg, temp;
3471
3472         /* Switch from PCDclk to Rawclk */
3473         reg = FDI_RX_CTL(pipe);
3474         temp = I915_READ(reg);
3475         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3476
3477         /* Disable CPU FDI TX PLL */
3478         reg = FDI_TX_CTL(pipe);
3479         temp = I915_READ(reg);
3480         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3481
3482         POSTING_READ(reg);
3483         udelay(100);
3484
3485         reg = FDI_RX_CTL(pipe);
3486         temp = I915_READ(reg);
3487         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3488
3489         /* Wait for the clocks to turn off. */
3490         POSTING_READ(reg);
3491         udelay(100);
3492 }
3493
3494 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3495 {
3496         struct drm_device *dev = crtc->dev;
3497         struct drm_i915_private *dev_priv = dev->dev_private;
3498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3499         int pipe = intel_crtc->pipe;
3500         u32 reg, temp;
3501
3502         /* disable CPU FDI tx and PCH FDI rx */
3503         reg = FDI_TX_CTL(pipe);
3504         temp = I915_READ(reg);
3505         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3506         POSTING_READ(reg);
3507
3508         reg = FDI_RX_CTL(pipe);
3509         temp = I915_READ(reg);
3510         temp &= ~(0x7 << 16);
3511         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3512         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3513
3514         POSTING_READ(reg);
3515         udelay(100);
3516
3517         /* Ironlake workaround, disable clock pointer after downing FDI */
3518         if (HAS_PCH_IBX(dev))
3519                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3520
3521         /* still set train pattern 1 */
3522         reg = FDI_TX_CTL(pipe);
3523         temp = I915_READ(reg);
3524         temp &= ~FDI_LINK_TRAIN_NONE;
3525         temp |= FDI_LINK_TRAIN_PATTERN_1;
3526         I915_WRITE(reg, temp);
3527
3528         reg = FDI_RX_CTL(pipe);
3529         temp = I915_READ(reg);
3530         if (HAS_PCH_CPT(dev)) {
3531                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3532                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3533         } else {
3534                 temp &= ~FDI_LINK_TRAIN_NONE;
3535                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3536         }
3537         /* BPC in FDI rx is consistent with that in PIPECONF */
3538         temp &= ~(0x07 << 16);
3539         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3540         I915_WRITE(reg, temp);
3541
3542         POSTING_READ(reg);
3543         udelay(100);
3544 }
3545
3546 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3547 {
3548         struct intel_crtc *crtc;
3549
3550         /* Note that we don't need to be called with mode_config.lock here
3551          * as our list of CRTC objects is static for the lifetime of the
3552          * device and so cannot disappear as we iterate. Similarly, we can
3553          * happily treat the predicates as racy, atomic checks as userspace
3554          * cannot claim and pin a new fb without at least acquring the
3555          * struct_mutex and so serialising with us.
3556          */
3557         for_each_intel_crtc(dev, crtc) {
3558                 if (atomic_read(&crtc->unpin_work_count) == 0)
3559                         continue;
3560
3561                 if (crtc->unpin_work)
3562                         intel_wait_for_vblank(dev, crtc->pipe);
3563
3564                 return true;
3565         }
3566
3567         return false;
3568 }
3569
3570 static void page_flip_completed(struct intel_crtc *intel_crtc)
3571 {
3572         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3573         struct intel_unpin_work *work = intel_crtc->unpin_work;
3574
3575         /* ensure that the unpin work is consistent wrt ->pending. */
3576         smp_rmb();
3577         intel_crtc->unpin_work = NULL;
3578
3579         if (work->event)
3580                 drm_send_vblank_event(intel_crtc->base.dev,
3581                                       intel_crtc->pipe,
3582                                       work->event);
3583
3584         drm_crtc_vblank_put(&intel_crtc->base);
3585
3586         wake_up_all(&dev_priv->pending_flip_queue);
3587         queue_work(dev_priv->wq, &work->work);
3588
3589         trace_i915_flip_complete(intel_crtc->plane,
3590                                  work->pending_flip_obj);
3591 }
3592
3593 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3594 {
3595         struct drm_device *dev = crtc->dev;
3596         struct drm_i915_private *dev_priv = dev->dev_private;
3597
3598         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3599         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3600                                        !intel_crtc_has_pending_flip(crtc),
3601                                        60*HZ) == 0)) {
3602                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3603
3604                 spin_lock_irq(&dev->event_lock);
3605                 if (intel_crtc->unpin_work) {
3606                         WARN_ONCE(1, "Removing stuck page flip\n");
3607                         page_flip_completed(intel_crtc);
3608                 }
3609                 spin_unlock_irq(&dev->event_lock);
3610         }
3611
3612         if (crtc->primary->fb) {
3613                 mutex_lock(&dev->struct_mutex);
3614                 intel_finish_fb(crtc->primary->fb);
3615                 mutex_unlock(&dev->struct_mutex);
3616         }
3617 }
3618
3619 /* Program iCLKIP clock to the desired frequency */
3620 static void lpt_program_iclkip(struct drm_crtc *crtc)
3621 {
3622         struct drm_device *dev = crtc->dev;
3623         struct drm_i915_private *dev_priv = dev->dev_private;
3624         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3625         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3626         u32 temp;
3627
3628         mutex_lock(&dev_priv->dpio_lock);
3629
3630         /* It is necessary to ungate the pixclk gate prior to programming
3631          * the divisors, and gate it back when it is done.
3632          */
3633         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3634
3635         /* Disable SSCCTL */
3636         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3637                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3638                                 SBI_SSCCTL_DISABLE,
3639                         SBI_ICLK);
3640
3641         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3642         if (clock == 20000) {
3643                 auxdiv = 1;
3644                 divsel = 0x41;
3645                 phaseinc = 0x20;
3646         } else {
3647                 /* The iCLK virtual clock root frequency is in MHz,
3648                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3649                  * divisors, it is necessary to divide one by another, so we
3650                  * convert the virtual clock precision to KHz here for higher
3651                  * precision.
3652                  */
3653                 u32 iclk_virtual_root_freq = 172800 * 1000;
3654                 u32 iclk_pi_range = 64;
3655                 u32 desired_divisor, msb_divisor_value, pi_value;
3656
3657                 desired_divisor = (iclk_virtual_root_freq / clock);
3658                 msb_divisor_value = desired_divisor / iclk_pi_range;
3659                 pi_value = desired_divisor % iclk_pi_range;
3660
3661                 auxdiv = 0;
3662                 divsel = msb_divisor_value - 2;
3663                 phaseinc = pi_value;
3664         }
3665
3666         /* This should not happen with any sane values */
3667         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3668                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3669         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3670                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3671
3672         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3673                         clock,
3674                         auxdiv,
3675                         divsel,
3676                         phasedir,
3677                         phaseinc);
3678
3679         /* Program SSCDIVINTPHASE6 */
3680         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3681         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3682         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3683         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3684         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3685         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3686         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3687         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3688
3689         /* Program SSCAUXDIV */
3690         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3691         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3692         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3693         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3694
3695         /* Enable modulator and associated divider */
3696         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3697         temp &= ~SBI_SSCCTL_DISABLE;
3698         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3699
3700         /* Wait for initialization time */
3701         udelay(24);
3702
3703         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3704
3705         mutex_unlock(&dev_priv->dpio_lock);
3706 }
3707
3708 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3709                                                 enum pipe pch_transcoder)
3710 {
3711         struct drm_device *dev = crtc->base.dev;
3712         struct drm_i915_private *dev_priv = dev->dev_private;
3713         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3714
3715         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3716                    I915_READ(HTOTAL(cpu_transcoder)));
3717         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3718                    I915_READ(HBLANK(cpu_transcoder)));
3719         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3720                    I915_READ(HSYNC(cpu_transcoder)));
3721
3722         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3723                    I915_READ(VTOTAL(cpu_transcoder)));
3724         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3725                    I915_READ(VBLANK(cpu_transcoder)));
3726         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3727                    I915_READ(VSYNC(cpu_transcoder)));
3728         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3729                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3730 }
3731
3732 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3733 {
3734         struct drm_i915_private *dev_priv = dev->dev_private;
3735         uint32_t temp;
3736
3737         temp = I915_READ(SOUTH_CHICKEN1);
3738         if (temp & FDI_BC_BIFURCATION_SELECT)
3739                 return;
3740
3741         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3742         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3743
3744         temp |= FDI_BC_BIFURCATION_SELECT;
3745         DRM_DEBUG_KMS("enabling fdi C rx\n");
3746         I915_WRITE(SOUTH_CHICKEN1, temp);
3747         POSTING_READ(SOUTH_CHICKEN1);
3748 }
3749
3750 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3751 {
3752         struct drm_device *dev = intel_crtc->base.dev;
3753         struct drm_i915_private *dev_priv = dev->dev_private;
3754
3755         switch (intel_crtc->pipe) {
3756         case PIPE_A:
3757                 break;
3758         case PIPE_B:
3759                 if (intel_crtc->config->fdi_lanes > 2)
3760                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3761                 else
3762                         cpt_enable_fdi_bc_bifurcation(dev);
3763
3764                 break;
3765         case PIPE_C:
3766                 cpt_enable_fdi_bc_bifurcation(dev);
3767
3768                 break;
3769         default:
3770                 BUG();
3771         }
3772 }
3773
3774 /*
3775  * Enable PCH resources required for PCH ports:
3776  *   - PCH PLLs
3777  *   - FDI training & RX/TX
3778  *   - update transcoder timings
3779  *   - DP transcoding bits
3780  *   - transcoder
3781  */
3782 static void ironlake_pch_enable(struct drm_crtc *crtc)
3783 {
3784         struct drm_device *dev = crtc->dev;
3785         struct drm_i915_private *dev_priv = dev->dev_private;
3786         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3787         int pipe = intel_crtc->pipe;
3788         u32 reg, temp;
3789
3790         assert_pch_transcoder_disabled(dev_priv, pipe);
3791
3792         if (IS_IVYBRIDGE(dev))
3793                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3794
3795         /* Write the TU size bits before fdi link training, so that error
3796          * detection works. */
3797         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3798                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3799
3800         /* For PCH output, training FDI link */
3801         dev_priv->display.fdi_link_train(crtc);
3802
3803         /* We need to program the right clock selection before writing the pixel
3804          * mutliplier into the DPLL. */
3805         if (HAS_PCH_CPT(dev)) {
3806                 u32 sel;
3807
3808                 temp = I915_READ(PCH_DPLL_SEL);
3809                 temp |= TRANS_DPLL_ENABLE(pipe);
3810                 sel = TRANS_DPLLB_SEL(pipe);
3811                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3812                         temp |= sel;
3813                 else
3814                         temp &= ~sel;
3815                 I915_WRITE(PCH_DPLL_SEL, temp);
3816         }
3817
3818         /* XXX: pch pll's can be enabled any time before we enable the PCH
3819          * transcoder, and we actually should do this to not upset any PCH
3820          * transcoder that already use the clock when we share it.
3821          *
3822          * Note that enable_shared_dpll tries to do the right thing, but
3823          * get_shared_dpll unconditionally resets the pll - we need that to have
3824          * the right LVDS enable sequence. */
3825         intel_enable_shared_dpll(intel_crtc);
3826
3827         /* set transcoder timing, panel must allow it */
3828         assert_panel_unlocked(dev_priv, pipe);
3829         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3830
3831         intel_fdi_normal_train(crtc);
3832
3833         /* For PCH DP, enable TRANS_DP_CTL */
3834         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3835                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3836                 reg = TRANS_DP_CTL(pipe);
3837                 temp = I915_READ(reg);
3838                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3839                           TRANS_DP_SYNC_MASK |
3840                           TRANS_DP_BPC_MASK);
3841                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3842                          TRANS_DP_ENH_FRAMING);
3843                 temp |= bpc << 9; /* same format but at 11:9 */
3844
3845                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3846                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3847                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3848                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3849
3850                 switch (intel_trans_dp_port_sel(crtc)) {
3851                 case PCH_DP_B:
3852                         temp |= TRANS_DP_PORT_SEL_B;
3853                         break;
3854                 case PCH_DP_C:
3855                         temp |= TRANS_DP_PORT_SEL_C;
3856                         break;
3857                 case PCH_DP_D:
3858                         temp |= TRANS_DP_PORT_SEL_D;
3859                         break;
3860                 default:
3861                         BUG();
3862                 }
3863
3864                 I915_WRITE(reg, temp);
3865         }
3866
3867         ironlake_enable_pch_transcoder(dev_priv, pipe);
3868 }
3869
3870 static void lpt_pch_enable(struct drm_crtc *crtc)
3871 {
3872         struct drm_device *dev = crtc->dev;
3873         struct drm_i915_private *dev_priv = dev->dev_private;
3874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3875         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3876
3877         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3878
3879         lpt_program_iclkip(crtc);
3880
3881         /* Set transcoder timing. */
3882         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3883
3884         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3885 }
3886
3887 void intel_put_shared_dpll(struct intel_crtc *crtc)
3888 {
3889         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3890
3891         if (pll == NULL)
3892                 return;
3893
3894         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3895                 WARN(1, "bad %s crtc mask\n", pll->name);
3896                 return;
3897         }
3898
3899         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3900         if (pll->config.crtc_mask == 0) {
3901                 WARN_ON(pll->on);
3902                 WARN_ON(pll->active);
3903         }
3904
3905         crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3906 }
3907
3908 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3909                                                 struct intel_crtc_state *crtc_state)
3910 {
3911         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3912         struct intel_shared_dpll *pll;
3913         enum intel_dpll_id i;
3914
3915         if (HAS_PCH_IBX(dev_priv->dev)) {
3916                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3917                 i = (enum intel_dpll_id) crtc->pipe;
3918                 pll = &dev_priv->shared_dplls[i];
3919
3920                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3921                               crtc->base.base.id, pll->name);
3922
3923                 WARN_ON(pll->new_config->crtc_mask);
3924
3925                 goto found;
3926         }
3927
3928         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3929                 pll = &dev_priv->shared_dplls[i];
3930
3931                 /* Only want to check enabled timings first */
3932                 if (pll->new_config->crtc_mask == 0)
3933                         continue;
3934
3935                 if (memcmp(&crtc_state->dpll_hw_state,
3936                            &pll->new_config->hw_state,
3937                            sizeof(pll->new_config->hw_state)) == 0) {
3938                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3939                                       crtc->base.base.id, pll->name,
3940                                       pll->new_config->crtc_mask,
3941                                       pll->active);
3942                         goto found;
3943                 }
3944         }
3945
3946         /* Ok no matching timings, maybe there's a free one? */
3947         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3948                 pll = &dev_priv->shared_dplls[i];
3949                 if (pll->new_config->crtc_mask == 0) {
3950                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3951                                       crtc->base.base.id, pll->name);
3952                         goto found;
3953                 }
3954         }
3955
3956         return NULL;
3957
3958 found:
3959         if (pll->new_config->crtc_mask == 0)
3960                 pll->new_config->hw_state = crtc_state->dpll_hw_state;
3961
3962         crtc_state->shared_dpll = i;
3963         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3964                          pipe_name(crtc->pipe));
3965
3966         pll->new_config->crtc_mask |= 1 << crtc->pipe;
3967
3968         return pll;
3969 }
3970
3971 /**
3972  * intel_shared_dpll_start_config - start a new PLL staged config
3973  * @dev_priv: DRM device
3974  * @clear_pipes: mask of pipes that will have their PLLs freed
3975  *
3976  * Starts a new PLL staged config, copying the current config but
3977  * releasing the references of pipes specified in clear_pipes.
3978  */
3979 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3980                                           unsigned clear_pipes)
3981 {
3982         struct intel_shared_dpll *pll;
3983         enum intel_dpll_id i;
3984
3985         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3986                 pll = &dev_priv->shared_dplls[i];
3987
3988                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3989                                           GFP_KERNEL);
3990                 if (!pll->new_config)
3991                         goto cleanup;
3992
3993                 pll->new_config->crtc_mask &= ~clear_pipes;
3994         }
3995
3996         return 0;
3997
3998 cleanup:
3999         while (--i >= 0) {
4000                 pll = &dev_priv->shared_dplls[i];
4001                 kfree(pll->new_config);
4002                 pll->new_config = NULL;
4003         }
4004
4005         return -ENOMEM;
4006 }
4007
4008 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4009 {
4010         struct intel_shared_dpll *pll;
4011         enum intel_dpll_id i;
4012
4013         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4014                 pll = &dev_priv->shared_dplls[i];
4015
4016                 WARN_ON(pll->new_config == &pll->config);
4017
4018                 pll->config = *pll->new_config;
4019                 kfree(pll->new_config);
4020                 pll->new_config = NULL;
4021         }
4022 }
4023
4024 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4025 {
4026         struct intel_shared_dpll *pll;
4027         enum intel_dpll_id i;
4028
4029         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4030                 pll = &dev_priv->shared_dplls[i];
4031
4032                 WARN_ON(pll->new_config == &pll->config);
4033
4034                 kfree(pll->new_config);
4035                 pll->new_config = NULL;
4036         }
4037 }
4038
4039 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4040 {
4041         struct drm_i915_private *dev_priv = dev->dev_private;
4042         int dslreg = PIPEDSL(pipe);
4043         u32 temp;
4044
4045         temp = I915_READ(dslreg);
4046         udelay(500);
4047         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4048                 if (wait_for(I915_READ(dslreg) != temp, 5))
4049                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4050         }
4051 }
4052
4053 static void skylake_pfit_enable(struct intel_crtc *crtc)
4054 {
4055         struct drm_device *dev = crtc->base.dev;
4056         struct drm_i915_private *dev_priv = dev->dev_private;
4057         int pipe = crtc->pipe;
4058
4059         if (crtc->config->pch_pfit.enabled) {
4060                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4061                 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4062                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4063         }
4064 }
4065
4066 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4067 {
4068         struct drm_device *dev = crtc->base.dev;
4069         struct drm_i915_private *dev_priv = dev->dev_private;
4070         int pipe = crtc->pipe;
4071
4072         if (crtc->config->pch_pfit.enabled) {
4073                 /* Force use of hard-coded filter coefficients
4074                  * as some pre-programmed values are broken,
4075                  * e.g. x201.
4076                  */
4077                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4078                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4079                                                  PF_PIPE_SEL_IVB(pipe));
4080                 else
4081                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4082                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4083                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4084         }
4085 }
4086
4087 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4088 {
4089         struct drm_device *dev = crtc->dev;
4090         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4091         struct drm_plane *plane;
4092         struct intel_plane *intel_plane;
4093
4094         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4095                 intel_plane = to_intel_plane(plane);
4096                 if (intel_plane->pipe == pipe)
4097                         intel_plane_restore(&intel_plane->base);
4098         }
4099 }
4100
4101 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4102 {
4103         struct drm_device *dev = crtc->dev;
4104         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4105         struct drm_plane *plane;
4106         struct intel_plane *intel_plane;
4107
4108         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4109                 intel_plane = to_intel_plane(plane);
4110                 if (intel_plane->pipe == pipe)
4111                         plane->funcs->disable_plane(plane);
4112         }
4113 }
4114
4115 void hsw_enable_ips(struct intel_crtc *crtc)
4116 {
4117         struct drm_device *dev = crtc->base.dev;
4118         struct drm_i915_private *dev_priv = dev->dev_private;
4119
4120         if (!crtc->config->ips_enabled)
4121                 return;
4122
4123         /* We can only enable IPS after we enable a plane and wait for a vblank */
4124         intel_wait_for_vblank(dev, crtc->pipe);
4125
4126         assert_plane_enabled(dev_priv, crtc->plane);
4127         if (IS_BROADWELL(dev)) {
4128                 mutex_lock(&dev_priv->rps.hw_lock);
4129                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4130                 mutex_unlock(&dev_priv->rps.hw_lock);
4131                 /* Quoting Art Runyan: "its not safe to expect any particular
4132                  * value in IPS_CTL bit 31 after enabling IPS through the
4133                  * mailbox." Moreover, the mailbox may return a bogus state,
4134                  * so we need to just enable it and continue on.
4135                  */
4136         } else {
4137                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4138                 /* The bit only becomes 1 in the next vblank, so this wait here
4139                  * is essentially intel_wait_for_vblank. If we don't have this
4140                  * and don't wait for vblanks until the end of crtc_enable, then
4141                  * the HW state readout code will complain that the expected
4142                  * IPS_CTL value is not the one we read. */
4143                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4144                         DRM_ERROR("Timed out waiting for IPS enable\n");
4145         }
4146 }
4147
4148 void hsw_disable_ips(struct intel_crtc *crtc)
4149 {
4150         struct drm_device *dev = crtc->base.dev;
4151         struct drm_i915_private *dev_priv = dev->dev_private;
4152
4153         if (!crtc->config->ips_enabled)
4154                 return;
4155
4156         assert_plane_enabled(dev_priv, crtc->plane);
4157         if (IS_BROADWELL(dev)) {
4158                 mutex_lock(&dev_priv->rps.hw_lock);
4159                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4160                 mutex_unlock(&dev_priv->rps.hw_lock);
4161                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4162                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4163                         DRM_ERROR("Timed out waiting for IPS disable\n");
4164         } else {
4165                 I915_WRITE(IPS_CTL, 0);
4166                 POSTING_READ(IPS_CTL);
4167         }
4168
4169         /* We need to wait for a vblank before we can disable the plane. */
4170         intel_wait_for_vblank(dev, crtc->pipe);
4171 }
4172
4173 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4174 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4175 {
4176         struct drm_device *dev = crtc->dev;
4177         struct drm_i915_private *dev_priv = dev->dev_private;
4178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4179         enum pipe pipe = intel_crtc->pipe;
4180         int palreg = PALETTE(pipe);
4181         int i;
4182         bool reenable_ips = false;
4183
4184         /* The clocks have to be on to load the palette. */
4185         if (!crtc->enabled || !intel_crtc->active)
4186                 return;
4187
4188         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4189                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4190                         assert_dsi_pll_enabled(dev_priv);
4191                 else
4192                         assert_pll_enabled(dev_priv, pipe);
4193         }
4194
4195         /* use legacy palette for Ironlake */
4196         if (!HAS_GMCH_DISPLAY(dev))
4197                 palreg = LGC_PALETTE(pipe);
4198
4199         /* Workaround : Do not read or write the pipe palette/gamma data while
4200          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4201          */
4202         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4203             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4204              GAMMA_MODE_MODE_SPLIT)) {
4205                 hsw_disable_ips(intel_crtc);
4206                 reenable_ips = true;
4207         }
4208
4209         for (i = 0; i < 256; i++) {
4210                 I915_WRITE(palreg + 4 * i,
4211                            (intel_crtc->lut_r[i] << 16) |
4212                            (intel_crtc->lut_g[i] << 8) |
4213                            intel_crtc->lut_b[i]);
4214         }
4215
4216         if (reenable_ips)
4217                 hsw_enable_ips(intel_crtc);
4218 }
4219
4220 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4221 {
4222         if (!enable && intel_crtc->overlay) {
4223                 struct drm_device *dev = intel_crtc->base.dev;
4224                 struct drm_i915_private *dev_priv = dev->dev_private;
4225
4226                 mutex_lock(&dev->struct_mutex);
4227                 dev_priv->mm.interruptible = false;
4228                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4229                 dev_priv->mm.interruptible = true;
4230                 mutex_unlock(&dev->struct_mutex);
4231         }
4232
4233         /* Let userspace switch the overlay on again. In most cases userspace
4234          * has to recompute where to put it anyway.
4235          */
4236 }
4237
4238 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4239 {
4240         struct drm_device *dev = crtc->dev;
4241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4242         int pipe = intel_crtc->pipe;
4243
4244         intel_enable_primary_hw_plane(crtc->primary, crtc);
4245         intel_enable_sprite_planes(crtc);
4246         intel_crtc_update_cursor(crtc, true);
4247         intel_crtc_dpms_overlay(intel_crtc, true);
4248
4249         hsw_enable_ips(intel_crtc);
4250
4251         mutex_lock(&dev->struct_mutex);
4252         intel_fbc_update(dev);
4253         mutex_unlock(&dev->struct_mutex);
4254
4255         /*
4256          * FIXME: Once we grow proper nuclear flip support out of this we need
4257          * to compute the mask of flip planes precisely. For the time being
4258          * consider this a flip from a NULL plane.
4259          */
4260         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4261 }
4262
4263 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4264 {
4265         struct drm_device *dev = crtc->dev;
4266         struct drm_i915_private *dev_priv = dev->dev_private;
4267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4268         int pipe = intel_crtc->pipe;
4269         int plane = intel_crtc->plane;
4270
4271         intel_crtc_wait_for_pending_flips(crtc);
4272
4273         if (dev_priv->fbc.plane == plane)
4274                 intel_fbc_disable(dev);
4275
4276         hsw_disable_ips(intel_crtc);
4277
4278         intel_crtc_dpms_overlay(intel_crtc, false);
4279         intel_crtc_update_cursor(crtc, false);
4280         intel_disable_sprite_planes(crtc);
4281         intel_disable_primary_hw_plane(crtc->primary, crtc);
4282
4283         /*
4284          * FIXME: Once we grow proper nuclear flip support out of this we need
4285          * to compute the mask of flip planes precisely. For the time being
4286          * consider this a flip to a NULL plane.
4287          */
4288         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4289 }
4290
4291 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4292 {
4293         struct drm_device *dev = crtc->dev;
4294         struct drm_i915_private *dev_priv = dev->dev_private;
4295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4296         struct intel_encoder *encoder;
4297         int pipe = intel_crtc->pipe;
4298
4299         WARN_ON(!crtc->enabled);
4300
4301         if (intel_crtc->active)
4302                 return;
4303
4304         if (intel_crtc->config->has_pch_encoder)
4305                 intel_prepare_shared_dpll(intel_crtc);
4306
4307         if (intel_crtc->config->has_dp_encoder)
4308                 intel_dp_set_m_n(intel_crtc);
4309
4310         intel_set_pipe_timings(intel_crtc);
4311
4312         if (intel_crtc->config->has_pch_encoder) {
4313                 intel_cpu_transcoder_set_m_n(intel_crtc,
4314                                      &intel_crtc->config->fdi_m_n, NULL);
4315         }
4316
4317         ironlake_set_pipeconf(crtc);
4318
4319         intel_crtc->active = true;
4320
4321         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4322         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4323
4324         for_each_encoder_on_crtc(dev, crtc, encoder)
4325                 if (encoder->pre_enable)
4326                         encoder->pre_enable(encoder);
4327
4328         if (intel_crtc->config->has_pch_encoder) {
4329                 /* Note: FDI PLL enabling _must_ be done before we enable the
4330                  * cpu pipes, hence this is separate from all the other fdi/pch
4331                  * enabling. */
4332                 ironlake_fdi_pll_enable(intel_crtc);
4333         } else {
4334                 assert_fdi_tx_disabled(dev_priv, pipe);
4335                 assert_fdi_rx_disabled(dev_priv, pipe);
4336         }
4337
4338         ironlake_pfit_enable(intel_crtc);
4339
4340         /*
4341          * On ILK+ LUT must be loaded before the pipe is running but with
4342          * clocks enabled
4343          */
4344         intel_crtc_load_lut(crtc);
4345
4346         intel_update_watermarks(crtc);
4347         intel_enable_pipe(intel_crtc);
4348
4349         if (intel_crtc->config->has_pch_encoder)
4350                 ironlake_pch_enable(crtc);
4351
4352         assert_vblank_disabled(crtc);
4353         drm_crtc_vblank_on(crtc);
4354
4355         for_each_encoder_on_crtc(dev, crtc, encoder)
4356                 encoder->enable(encoder);
4357
4358         if (HAS_PCH_CPT(dev))
4359                 cpt_verify_modeset(dev, intel_crtc->pipe);
4360
4361         intel_crtc_enable_planes(crtc);
4362 }
4363
4364 /* IPS only exists on ULT machines and is tied to pipe A. */
4365 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4366 {
4367         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4368 }
4369
4370 /*
4371  * This implements the workaround described in the "notes" section of the mode
4372  * set sequence documentation. When going from no pipes or single pipe to
4373  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4374  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4375  */
4376 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4377 {
4378         struct drm_device *dev = crtc->base.dev;
4379         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4380
4381         /* We want to get the other_active_crtc only if there's only 1 other
4382          * active crtc. */
4383         for_each_intel_crtc(dev, crtc_it) {
4384                 if (!crtc_it->active || crtc_it == crtc)
4385                         continue;
4386
4387                 if (other_active_crtc)
4388                         return;
4389
4390                 other_active_crtc = crtc_it;
4391         }
4392         if (!other_active_crtc)
4393                 return;
4394
4395         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4396         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4397 }
4398
4399 static void haswell_crtc_enable(struct drm_crtc *crtc)
4400 {
4401         struct drm_device *dev = crtc->dev;
4402         struct drm_i915_private *dev_priv = dev->dev_private;
4403         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4404         struct intel_encoder *encoder;
4405         int pipe = intel_crtc->pipe;
4406
4407         WARN_ON(!crtc->enabled);
4408
4409         if (intel_crtc->active)
4410                 return;
4411
4412         if (intel_crtc_to_shared_dpll(intel_crtc))
4413                 intel_enable_shared_dpll(intel_crtc);
4414
4415         if (intel_crtc->config->has_dp_encoder)
4416                 intel_dp_set_m_n(intel_crtc);
4417
4418         intel_set_pipe_timings(intel_crtc);
4419
4420         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4421                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4422                            intel_crtc->config->pixel_multiplier - 1);
4423         }
4424
4425         if (intel_crtc->config->has_pch_encoder) {
4426                 intel_cpu_transcoder_set_m_n(intel_crtc,
4427                                      &intel_crtc->config->fdi_m_n, NULL);
4428         }
4429
4430         haswell_set_pipeconf(crtc);
4431
4432         intel_set_pipe_csc(crtc);
4433
4434         intel_crtc->active = true;
4435
4436         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4437         for_each_encoder_on_crtc(dev, crtc, encoder)
4438                 if (encoder->pre_enable)
4439                         encoder->pre_enable(encoder);
4440
4441         if (intel_crtc->config->has_pch_encoder) {
4442                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4443                                                       true);
4444                 dev_priv->display.fdi_link_train(crtc);
4445         }
4446
4447         intel_ddi_enable_pipe_clock(intel_crtc);
4448
4449         if (IS_SKYLAKE(dev))
4450                 skylake_pfit_enable(intel_crtc);
4451         else
4452                 ironlake_pfit_enable(intel_crtc);
4453
4454         /*
4455          * On ILK+ LUT must be loaded before the pipe is running but with
4456          * clocks enabled
4457          */
4458         intel_crtc_load_lut(crtc);
4459
4460         intel_ddi_set_pipe_settings(crtc);
4461         intel_ddi_enable_transcoder_func(crtc);
4462
4463         intel_update_watermarks(crtc);
4464         intel_enable_pipe(intel_crtc);
4465
4466         if (intel_crtc->config->has_pch_encoder)
4467                 lpt_pch_enable(crtc);
4468
4469         if (intel_crtc->config->dp_encoder_is_mst)
4470                 intel_ddi_set_vc_payload_alloc(crtc, true);
4471
4472         assert_vblank_disabled(crtc);
4473         drm_crtc_vblank_on(crtc);
4474
4475         for_each_encoder_on_crtc(dev, crtc, encoder) {
4476                 encoder->enable(encoder);
4477                 intel_opregion_notify_encoder(encoder, true);
4478         }
4479
4480         /* If we change the relative order between pipe/planes enabling, we need
4481          * to change the workaround. */
4482         haswell_mode_set_planes_workaround(intel_crtc);
4483         intel_crtc_enable_planes(crtc);
4484 }
4485
4486 static void skylake_pfit_disable(struct intel_crtc *crtc)
4487 {
4488         struct drm_device *dev = crtc->base.dev;
4489         struct drm_i915_private *dev_priv = dev->dev_private;
4490         int pipe = crtc->pipe;
4491
4492         /* To avoid upsetting the power well on haswell only disable the pfit if
4493          * it's in use. The hw state code will make sure we get this right. */
4494         if (crtc->config->pch_pfit.enabled) {
4495                 I915_WRITE(PS_CTL(pipe), 0);
4496                 I915_WRITE(PS_WIN_POS(pipe), 0);
4497                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4498         }
4499 }
4500
4501 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4502 {
4503         struct drm_device *dev = crtc->base.dev;
4504         struct drm_i915_private *dev_priv = dev->dev_private;
4505         int pipe = crtc->pipe;
4506
4507         /* To avoid upsetting the power well on haswell only disable the pfit if
4508          * it's in use. The hw state code will make sure we get this right. */
4509         if (crtc->config->pch_pfit.enabled) {
4510                 I915_WRITE(PF_CTL(pipe), 0);
4511                 I915_WRITE(PF_WIN_POS(pipe), 0);
4512                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4513         }
4514 }
4515
4516 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4517 {
4518         struct drm_device *dev = crtc->dev;
4519         struct drm_i915_private *dev_priv = dev->dev_private;
4520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4521         struct intel_encoder *encoder;
4522         int pipe = intel_crtc->pipe;
4523         u32 reg, temp;
4524
4525         if (!intel_crtc->active)
4526                 return;
4527
4528         intel_crtc_disable_planes(crtc);
4529
4530         for_each_encoder_on_crtc(dev, crtc, encoder)
4531                 encoder->disable(encoder);
4532
4533         drm_crtc_vblank_off(crtc);
4534         assert_vblank_disabled(crtc);
4535
4536         if (intel_crtc->config->has_pch_encoder)
4537                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4538
4539         intel_disable_pipe(intel_crtc);
4540
4541         ironlake_pfit_disable(intel_crtc);
4542
4543         for_each_encoder_on_crtc(dev, crtc, encoder)
4544                 if (encoder->post_disable)
4545                         encoder->post_disable(encoder);
4546
4547         if (intel_crtc->config->has_pch_encoder) {
4548                 ironlake_fdi_disable(crtc);
4549
4550                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4551
4552                 if (HAS_PCH_CPT(dev)) {
4553                         /* disable TRANS_DP_CTL */
4554                         reg = TRANS_DP_CTL(pipe);
4555                         temp = I915_READ(reg);
4556                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4557                                   TRANS_DP_PORT_SEL_MASK);
4558                         temp |= TRANS_DP_PORT_SEL_NONE;
4559                         I915_WRITE(reg, temp);
4560
4561                         /* disable DPLL_SEL */
4562                         temp = I915_READ(PCH_DPLL_SEL);
4563                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4564                         I915_WRITE(PCH_DPLL_SEL, temp);
4565                 }
4566
4567                 /* disable PCH DPLL */
4568                 intel_disable_shared_dpll(intel_crtc);
4569
4570                 ironlake_fdi_pll_disable(intel_crtc);
4571         }
4572
4573         intel_crtc->active = false;
4574         intel_update_watermarks(crtc);
4575
4576         mutex_lock(&dev->struct_mutex);
4577         intel_fbc_update(dev);
4578         mutex_unlock(&dev->struct_mutex);
4579 }
4580
4581 static void haswell_crtc_disable(struct drm_crtc *crtc)
4582 {
4583         struct drm_device *dev = crtc->dev;
4584         struct drm_i915_private *dev_priv = dev->dev_private;
4585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4586         struct intel_encoder *encoder;
4587         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4588
4589         if (!intel_crtc->active)
4590                 return;
4591
4592         intel_crtc_disable_planes(crtc);
4593
4594         for_each_encoder_on_crtc(dev, crtc, encoder) {
4595                 intel_opregion_notify_encoder(encoder, false);
4596                 encoder->disable(encoder);
4597         }
4598
4599         drm_crtc_vblank_off(crtc);
4600         assert_vblank_disabled(crtc);
4601
4602         if (intel_crtc->config->has_pch_encoder)
4603                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4604                                                       false);
4605         intel_disable_pipe(intel_crtc);
4606
4607         if (intel_crtc->config->dp_encoder_is_mst)
4608                 intel_ddi_set_vc_payload_alloc(crtc, false);
4609
4610         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4611
4612         if (IS_SKYLAKE(dev))
4613                 skylake_pfit_disable(intel_crtc);
4614         else
4615                 ironlake_pfit_disable(intel_crtc);
4616
4617         intel_ddi_disable_pipe_clock(intel_crtc);
4618
4619         if (intel_crtc->config->has_pch_encoder) {
4620                 lpt_disable_pch_transcoder(dev_priv);
4621                 intel_ddi_fdi_disable(crtc);
4622         }
4623
4624         for_each_encoder_on_crtc(dev, crtc, encoder)
4625                 if (encoder->post_disable)
4626                         encoder->post_disable(encoder);
4627
4628         intel_crtc->active = false;
4629         intel_update_watermarks(crtc);
4630
4631         mutex_lock(&dev->struct_mutex);
4632         intel_fbc_update(dev);
4633         mutex_unlock(&dev->struct_mutex);
4634
4635         if (intel_crtc_to_shared_dpll(intel_crtc))
4636                 intel_disable_shared_dpll(intel_crtc);
4637 }
4638
4639 static void ironlake_crtc_off(struct drm_crtc *crtc)
4640 {
4641         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4642         intel_put_shared_dpll(intel_crtc);
4643 }
4644
4645
4646 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4647 {
4648         struct drm_device *dev = crtc->base.dev;
4649         struct drm_i915_private *dev_priv = dev->dev_private;
4650         struct intel_crtc_state *pipe_config = crtc->config;
4651
4652         if (!pipe_config->gmch_pfit.control)
4653                 return;
4654
4655         /*
4656          * The panel fitter should only be adjusted whilst the pipe is disabled,
4657          * according to register description and PRM.
4658          */
4659         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4660         assert_pipe_disabled(dev_priv, crtc->pipe);
4661
4662         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4663         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4664
4665         /* Border color in case we don't scale up to the full screen. Black by
4666          * default, change to something else for debugging. */
4667         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4668 }
4669
4670 static enum intel_display_power_domain port_to_power_domain(enum port port)
4671 {
4672         switch (port) {
4673         case PORT_A:
4674                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4675         case PORT_B:
4676                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4677         case PORT_C:
4678                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4679         case PORT_D:
4680                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4681         default:
4682                 WARN_ON_ONCE(1);
4683                 return POWER_DOMAIN_PORT_OTHER;
4684         }
4685 }
4686
4687 #define for_each_power_domain(domain, mask)                             \
4688         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4689                 if ((1 << (domain)) & (mask))
4690
4691 enum intel_display_power_domain
4692 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4693 {
4694         struct drm_device *dev = intel_encoder->base.dev;
4695         struct intel_digital_port *intel_dig_port;
4696
4697         switch (intel_encoder->type) {
4698         case INTEL_OUTPUT_UNKNOWN:
4699                 /* Only DDI platforms should ever use this output type */
4700                 WARN_ON_ONCE(!HAS_DDI(dev));
4701         case INTEL_OUTPUT_DISPLAYPORT:
4702         case INTEL_OUTPUT_HDMI:
4703         case INTEL_OUTPUT_EDP:
4704                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4705                 return port_to_power_domain(intel_dig_port->port);
4706         case INTEL_OUTPUT_DP_MST:
4707                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4708                 return port_to_power_domain(intel_dig_port->port);
4709         case INTEL_OUTPUT_ANALOG:
4710                 return POWER_DOMAIN_PORT_CRT;
4711         case INTEL_OUTPUT_DSI:
4712                 return POWER_DOMAIN_PORT_DSI;
4713         default:
4714                 return POWER_DOMAIN_PORT_OTHER;
4715         }
4716 }
4717
4718 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4719 {
4720         struct drm_device *dev = crtc->dev;
4721         struct intel_encoder *intel_encoder;
4722         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4723         enum pipe pipe = intel_crtc->pipe;
4724         unsigned long mask;
4725         enum transcoder transcoder;
4726
4727         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4728
4729         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4730         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4731         if (intel_crtc->config->pch_pfit.enabled ||
4732             intel_crtc->config->pch_pfit.force_thru)
4733                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4734
4735         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4736                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4737
4738         return mask;
4739 }
4740
4741 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4742 {
4743         struct drm_i915_private *dev_priv = dev->dev_private;
4744         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4745         struct intel_crtc *crtc;
4746
4747         /*
4748          * First get all needed power domains, then put all unneeded, to avoid
4749          * any unnecessary toggling of the power wells.
4750          */
4751         for_each_intel_crtc(dev, crtc) {
4752                 enum intel_display_power_domain domain;
4753
4754                 if (!crtc->base.enabled)
4755                         continue;
4756
4757                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4758
4759                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4760                         intel_display_power_get(dev_priv, domain);
4761         }
4762
4763         if (dev_priv->display.modeset_global_resources)
4764                 dev_priv->display.modeset_global_resources(dev);
4765
4766         for_each_intel_crtc(dev, crtc) {
4767                 enum intel_display_power_domain domain;
4768
4769                 for_each_power_domain(domain, crtc->enabled_power_domains)
4770                         intel_display_power_put(dev_priv, domain);
4771
4772                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4773         }
4774
4775         intel_display_set_init_power(dev_priv, false);
4776 }
4777
4778 /* returns HPLL frequency in kHz */
4779 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4780 {
4781         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4782
4783         /* Obtain SKU information */
4784         mutex_lock(&dev_priv->dpio_lock);
4785         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4786                 CCK_FUSE_HPLL_FREQ_MASK;
4787         mutex_unlock(&dev_priv->dpio_lock);
4788
4789         return vco_freq[hpll_freq] * 1000;
4790 }
4791
4792 static void vlv_update_cdclk(struct drm_device *dev)
4793 {
4794         struct drm_i915_private *dev_priv = dev->dev_private;
4795
4796         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4797         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4798                          dev_priv->vlv_cdclk_freq);
4799
4800         /*
4801          * Program the gmbus_freq based on the cdclk frequency.
4802          * BSpec erroneously claims we should aim for 4MHz, but
4803          * in fact 1MHz is the correct frequency.
4804          */
4805         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4806 }
4807
4808 /* Adjust CDclk dividers to allow high res or save power if possible */
4809 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4810 {
4811         struct drm_i915_private *dev_priv = dev->dev_private;
4812         u32 val, cmd;
4813
4814         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4815
4816         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4817                 cmd = 2;
4818         else if (cdclk == 266667)
4819                 cmd = 1;
4820         else
4821                 cmd = 0;
4822
4823         mutex_lock(&dev_priv->rps.hw_lock);
4824         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4825         val &= ~DSPFREQGUAR_MASK;
4826         val |= (cmd << DSPFREQGUAR_SHIFT);
4827         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4828         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4829                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4830                      50)) {
4831                 DRM_ERROR("timed out waiting for CDclk change\n");
4832         }
4833         mutex_unlock(&dev_priv->rps.hw_lock);
4834
4835         if (cdclk == 400000) {
4836                 u32 divider;
4837
4838                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4839
4840                 mutex_lock(&dev_priv->dpio_lock);
4841                 /* adjust cdclk divider */
4842                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4843                 val &= ~DISPLAY_FREQUENCY_VALUES;
4844                 val |= divider;
4845                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4846
4847                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4848                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4849                              50))
4850                         DRM_ERROR("timed out waiting for CDclk change\n");
4851                 mutex_unlock(&dev_priv->dpio_lock);
4852         }
4853
4854         mutex_lock(&dev_priv->dpio_lock);
4855         /* adjust self-refresh exit latency value */
4856         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4857         val &= ~0x7f;
4858
4859         /*
4860          * For high bandwidth configs, we set a higher latency in the bunit
4861          * so that the core display fetch happens in time to avoid underruns.
4862          */
4863         if (cdclk == 400000)
4864                 val |= 4500 / 250; /* 4.5 usec */
4865         else
4866                 val |= 3000 / 250; /* 3.0 usec */
4867         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4868         mutex_unlock(&dev_priv->dpio_lock);
4869
4870         vlv_update_cdclk(dev);
4871 }
4872
4873 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4874 {
4875         struct drm_i915_private *dev_priv = dev->dev_private;
4876         u32 val, cmd;
4877
4878         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4879
4880         switch (cdclk) {
4881         case 400000:
4882                 cmd = 3;
4883                 break;
4884         case 333333:
4885         case 320000:
4886                 cmd = 2;
4887                 break;
4888         case 266667:
4889                 cmd = 1;
4890                 break;
4891         case 200000:
4892                 cmd = 0;
4893                 break;
4894         default:
4895                 MISSING_CASE(cdclk);
4896                 return;
4897         }
4898
4899         mutex_lock(&dev_priv->rps.hw_lock);
4900         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4901         val &= ~DSPFREQGUAR_MASK_CHV;
4902         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4903         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4904         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4905                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4906                      50)) {
4907                 DRM_ERROR("timed out waiting for CDclk change\n");
4908         }
4909         mutex_unlock(&dev_priv->rps.hw_lock);
4910
4911         vlv_update_cdclk(dev);
4912 }
4913
4914 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4915                                  int max_pixclk)
4916 {
4917         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
4918
4919         /* FIXME: Punit isn't quite ready yet */
4920         if (IS_CHERRYVIEW(dev_priv->dev))
4921                 return 400000;
4922
4923         /*
4924          * Really only a few cases to deal with, as only 4 CDclks are supported:
4925          *   200MHz
4926          *   267MHz
4927          *   320/333MHz (depends on HPLL freq)
4928          *   400MHz
4929          * So we check to see whether we're above 90% of the lower bin and
4930          * adjust if needed.
4931          *
4932          * We seem to get an unstable or solid color picture at 200MHz.
4933          * Not sure what's wrong. For now use 200MHz only when all pipes
4934          * are off.
4935          */
4936         if (max_pixclk > freq_320*9/10)
4937                 return 400000;
4938         else if (max_pixclk > 266667*9/10)
4939                 return freq_320;
4940         else if (max_pixclk > 0)
4941                 return 266667;
4942         else
4943                 return 200000;
4944 }
4945
4946 /* compute the max pixel clock for new configuration */
4947 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4948 {
4949         struct drm_device *dev = dev_priv->dev;
4950         struct intel_crtc *intel_crtc;
4951         int max_pixclk = 0;
4952
4953         for_each_intel_crtc(dev, intel_crtc) {
4954                 if (intel_crtc->new_enabled)
4955                         max_pixclk = max(max_pixclk,
4956                                          intel_crtc->new_config->base.adjusted_mode.crtc_clock);
4957         }
4958
4959         return max_pixclk;
4960 }
4961
4962 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4963                                             unsigned *prepare_pipes)
4964 {
4965         struct drm_i915_private *dev_priv = dev->dev_private;
4966         struct intel_crtc *intel_crtc;
4967         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4968
4969         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4970             dev_priv->vlv_cdclk_freq)
4971                 return;
4972
4973         /* disable/enable all currently active pipes while we change cdclk */
4974         for_each_intel_crtc(dev, intel_crtc)
4975                 if (intel_crtc->base.enabled)
4976                         *prepare_pipes |= (1 << intel_crtc->pipe);
4977 }
4978
4979 static void valleyview_modeset_global_resources(struct drm_device *dev)
4980 {
4981         struct drm_i915_private *dev_priv = dev->dev_private;
4982         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4983         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4984
4985         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4986                 /*
4987                  * FIXME: We can end up here with all power domains off, yet
4988                  * with a CDCLK frequency other than the minimum. To account
4989                  * for this take the PIPE-A power domain, which covers the HW
4990                  * blocks needed for the following programming. This can be
4991                  * removed once it's guaranteed that we get here either with
4992                  * the minimum CDCLK set, or the required power domains
4993                  * enabled.
4994                  */
4995                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
4996
4997                 if (IS_CHERRYVIEW(dev))
4998                         cherryview_set_cdclk(dev, req_cdclk);
4999                 else
5000                         valleyview_set_cdclk(dev, req_cdclk);
5001
5002                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5003         }
5004 }
5005
5006 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5007 {
5008         struct drm_device *dev = crtc->dev;
5009         struct drm_i915_private *dev_priv = to_i915(dev);
5010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5011         struct intel_encoder *encoder;
5012         int pipe = intel_crtc->pipe;
5013         bool is_dsi;
5014
5015         WARN_ON(!crtc->enabled);
5016
5017         if (intel_crtc->active)
5018                 return;
5019
5020         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5021
5022         if (!is_dsi) {
5023                 if (IS_CHERRYVIEW(dev))
5024                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5025                 else
5026                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5027         }
5028
5029         if (intel_crtc->config->has_dp_encoder)
5030                 intel_dp_set_m_n(intel_crtc);
5031
5032         intel_set_pipe_timings(intel_crtc);
5033
5034         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5035                 struct drm_i915_private *dev_priv = dev->dev_private;
5036
5037                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5038                 I915_WRITE(CHV_CANVAS(pipe), 0);
5039         }
5040
5041         i9xx_set_pipeconf(intel_crtc);
5042
5043         intel_crtc->active = true;
5044
5045         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5046
5047         for_each_encoder_on_crtc(dev, crtc, encoder)
5048                 if (encoder->pre_pll_enable)
5049                         encoder->pre_pll_enable(encoder);
5050
5051         if (!is_dsi) {
5052                 if (IS_CHERRYVIEW(dev))
5053                         chv_enable_pll(intel_crtc, intel_crtc->config);
5054                 else
5055                         vlv_enable_pll(intel_crtc, intel_crtc->config);
5056         }
5057
5058         for_each_encoder_on_crtc(dev, crtc, encoder)
5059                 if (encoder->pre_enable)
5060                         encoder->pre_enable(encoder);
5061
5062         i9xx_pfit_enable(intel_crtc);
5063
5064         intel_crtc_load_lut(crtc);
5065
5066         intel_update_watermarks(crtc);
5067         intel_enable_pipe(intel_crtc);
5068
5069         assert_vblank_disabled(crtc);
5070         drm_crtc_vblank_on(crtc);
5071
5072         for_each_encoder_on_crtc(dev, crtc, encoder)
5073                 encoder->enable(encoder);
5074
5075         intel_crtc_enable_planes(crtc);
5076
5077         /* Underruns don't raise interrupts, so check manually. */
5078         i9xx_check_fifo_underruns(dev_priv);
5079 }
5080
5081 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5082 {
5083         struct drm_device *dev = crtc->base.dev;
5084         struct drm_i915_private *dev_priv = dev->dev_private;
5085
5086         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5087         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5088 }
5089
5090 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5091 {
5092         struct drm_device *dev = crtc->dev;
5093         struct drm_i915_private *dev_priv = to_i915(dev);
5094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5095         struct intel_encoder *encoder;
5096         int pipe = intel_crtc->pipe;
5097
5098         WARN_ON(!crtc->enabled);
5099
5100         if (intel_crtc->active)
5101                 return;
5102
5103         i9xx_set_pll_dividers(intel_crtc);
5104
5105         if (intel_crtc->config->has_dp_encoder)
5106                 intel_dp_set_m_n(intel_crtc);
5107
5108         intel_set_pipe_timings(intel_crtc);
5109
5110         i9xx_set_pipeconf(intel_crtc);
5111
5112         intel_crtc->active = true;
5113
5114         if (!IS_GEN2(dev))
5115                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5116
5117         for_each_encoder_on_crtc(dev, crtc, encoder)
5118                 if (encoder->pre_enable)
5119                         encoder->pre_enable(encoder);
5120
5121         i9xx_enable_pll(intel_crtc);
5122
5123         i9xx_pfit_enable(intel_crtc);
5124
5125         intel_crtc_load_lut(crtc);
5126
5127         intel_update_watermarks(crtc);
5128         intel_enable_pipe(intel_crtc);
5129
5130         assert_vblank_disabled(crtc);
5131         drm_crtc_vblank_on(crtc);
5132
5133         for_each_encoder_on_crtc(dev, crtc, encoder)
5134                 encoder->enable(encoder);
5135
5136         intel_crtc_enable_planes(crtc);
5137
5138         /*
5139          * Gen2 reports pipe underruns whenever all planes are disabled.
5140          * So don't enable underrun reporting before at least some planes
5141          * are enabled.
5142          * FIXME: Need to fix the logic to work when we turn off all planes
5143          * but leave the pipe running.
5144          */
5145         if (IS_GEN2(dev))
5146                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5147
5148         /* Underruns don't raise interrupts, so check manually. */
5149         i9xx_check_fifo_underruns(dev_priv);
5150 }
5151
5152 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5153 {
5154         struct drm_device *dev = crtc->base.dev;
5155         struct drm_i915_private *dev_priv = dev->dev_private;
5156
5157         if (!crtc->config->gmch_pfit.control)
5158                 return;
5159
5160         assert_pipe_disabled(dev_priv, crtc->pipe);
5161
5162         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5163                          I915_READ(PFIT_CONTROL));
5164         I915_WRITE(PFIT_CONTROL, 0);
5165 }
5166
5167 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5168 {
5169         struct drm_device *dev = crtc->dev;
5170         struct drm_i915_private *dev_priv = dev->dev_private;
5171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5172         struct intel_encoder *encoder;
5173         int pipe = intel_crtc->pipe;
5174
5175         if (!intel_crtc->active)
5176                 return;
5177
5178         /*
5179          * Gen2 reports pipe underruns whenever all planes are disabled.
5180          * So diasble underrun reporting before all the planes get disabled.
5181          * FIXME: Need to fix the logic to work when we turn off all planes
5182          * but leave the pipe running.
5183          */
5184         if (IS_GEN2(dev))
5185                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5186
5187         /*
5188          * Vblank time updates from the shadow to live plane control register
5189          * are blocked if the memory self-refresh mode is active at that
5190          * moment. So to make sure the plane gets truly disabled, disable
5191          * first the self-refresh mode. The self-refresh enable bit in turn
5192          * will be checked/applied by the HW only at the next frame start
5193          * event which is after the vblank start event, so we need to have a
5194          * wait-for-vblank between disabling the plane and the pipe.
5195          */
5196         intel_set_memory_cxsr(dev_priv, false);
5197         intel_crtc_disable_planes(crtc);
5198
5199         /*
5200          * On gen2 planes are double buffered but the pipe isn't, so we must
5201          * wait for planes to fully turn off before disabling the pipe.
5202          * We also need to wait on all gmch platforms because of the
5203          * self-refresh mode constraint explained above.
5204          */
5205         intel_wait_for_vblank(dev, pipe);
5206
5207         for_each_encoder_on_crtc(dev, crtc, encoder)
5208                 encoder->disable(encoder);
5209
5210         drm_crtc_vblank_off(crtc);
5211         assert_vblank_disabled(crtc);
5212
5213         intel_disable_pipe(intel_crtc);
5214
5215         i9xx_pfit_disable(intel_crtc);
5216
5217         for_each_encoder_on_crtc(dev, crtc, encoder)
5218                 if (encoder->post_disable)
5219                         encoder->post_disable(encoder);
5220
5221         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5222                 if (IS_CHERRYVIEW(dev))
5223                         chv_disable_pll(dev_priv, pipe);
5224                 else if (IS_VALLEYVIEW(dev))
5225                         vlv_disable_pll(dev_priv, pipe);
5226                 else
5227                         i9xx_disable_pll(intel_crtc);
5228         }
5229
5230         if (!IS_GEN2(dev))
5231                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5232
5233         intel_crtc->active = false;
5234         intel_update_watermarks(crtc);
5235
5236         mutex_lock(&dev->struct_mutex);
5237         intel_fbc_update(dev);
5238         mutex_unlock(&dev->struct_mutex);
5239 }
5240
5241 static void i9xx_crtc_off(struct drm_crtc *crtc)
5242 {
5243 }
5244
5245 /* Master function to enable/disable CRTC and corresponding power wells */
5246 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5247 {
5248         struct drm_device *dev = crtc->dev;
5249         struct drm_i915_private *dev_priv = dev->dev_private;
5250         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5251         enum intel_display_power_domain domain;
5252         unsigned long domains;
5253
5254         if (enable) {
5255                 if (!intel_crtc->active) {
5256                         domains = get_crtc_power_domains(crtc);
5257                         for_each_power_domain(domain, domains)
5258                                 intel_display_power_get(dev_priv, domain);
5259                         intel_crtc->enabled_power_domains = domains;
5260
5261                         dev_priv->display.crtc_enable(crtc);
5262                 }
5263         } else {
5264                 if (intel_crtc->active) {
5265                         dev_priv->display.crtc_disable(crtc);
5266
5267                         domains = intel_crtc->enabled_power_domains;
5268                         for_each_power_domain(domain, domains)
5269                                 intel_display_power_put(dev_priv, domain);
5270                         intel_crtc->enabled_power_domains = 0;
5271                 }
5272         }
5273 }
5274
5275 /**
5276  * Sets the power management mode of the pipe and plane.
5277  */
5278 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5279 {
5280         struct drm_device *dev = crtc->dev;
5281         struct intel_encoder *intel_encoder;
5282         bool enable = false;
5283
5284         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5285                 enable |= intel_encoder->connectors_active;
5286
5287         intel_crtc_control(crtc, enable);
5288 }
5289
5290 static void intel_crtc_disable(struct drm_crtc *crtc)
5291 {
5292         struct drm_device *dev = crtc->dev;
5293         struct drm_connector *connector;
5294         struct drm_i915_private *dev_priv = dev->dev_private;
5295
5296         /* crtc should still be enabled when we disable it. */
5297         WARN_ON(!crtc->enabled);
5298
5299         dev_priv->display.crtc_disable(crtc);
5300         dev_priv->display.off(crtc);
5301
5302         crtc->primary->funcs->disable_plane(crtc->primary);
5303
5304         /* Update computed state. */
5305         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5306                 if (!connector->encoder || !connector->encoder->crtc)
5307                         continue;
5308
5309                 if (connector->encoder->crtc != crtc)
5310                         continue;
5311
5312                 connector->dpms = DRM_MODE_DPMS_OFF;
5313                 to_intel_encoder(connector->encoder)->connectors_active = false;
5314         }
5315 }
5316
5317 void intel_encoder_destroy(struct drm_encoder *encoder)
5318 {
5319         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5320
5321         drm_encoder_cleanup(encoder);
5322         kfree(intel_encoder);
5323 }
5324
5325 /* Simple dpms helper for encoders with just one connector, no cloning and only
5326  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5327  * state of the entire output pipe. */
5328 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5329 {
5330         if (mode == DRM_MODE_DPMS_ON) {
5331                 encoder->connectors_active = true;
5332
5333                 intel_crtc_update_dpms(encoder->base.crtc);
5334         } else {
5335                 encoder->connectors_active = false;
5336
5337                 intel_crtc_update_dpms(encoder->base.crtc);
5338         }
5339 }
5340
5341 /* Cross check the actual hw state with our own modeset state tracking (and it's
5342  * internal consistency). */
5343 static void intel_connector_check_state(struct intel_connector *connector)
5344 {
5345         if (connector->get_hw_state(connector)) {
5346                 struct intel_encoder *encoder = connector->encoder;
5347                 struct drm_crtc *crtc;
5348                 bool encoder_enabled;
5349                 enum pipe pipe;
5350
5351                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5352                               connector->base.base.id,
5353                               connector->base.name);
5354
5355                 /* there is no real hw state for MST connectors */
5356                 if (connector->mst_port)
5357                         return;
5358
5359                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5360                      "wrong connector dpms state\n");
5361                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5362                      "active connector not linked to encoder\n");
5363
5364                 if (encoder) {
5365                         I915_STATE_WARN(!encoder->connectors_active,
5366                              "encoder->connectors_active not set\n");
5367
5368                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5369                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5370                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
5371                                 return;
5372
5373                         crtc = encoder->base.crtc;
5374
5375                         I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
5376                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5377                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5378                              "encoder active on the wrong pipe\n");
5379                 }
5380         }
5381 }
5382
5383 /* Even simpler default implementation, if there's really no special case to
5384  * consider. */
5385 void intel_connector_dpms(struct drm_connector *connector, int mode)
5386 {
5387         /* All the simple cases only support two dpms states. */
5388         if (mode != DRM_MODE_DPMS_ON)
5389                 mode = DRM_MODE_DPMS_OFF;
5390
5391         if (mode == connector->dpms)
5392                 return;
5393
5394         connector->dpms = mode;
5395
5396         /* Only need to change hw state when actually enabled */
5397         if (connector->encoder)
5398                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5399
5400         intel_modeset_check_state(connector->dev);
5401 }
5402
5403 /* Simple connector->get_hw_state implementation for encoders that support only
5404  * one connector and no cloning and hence the encoder state determines the state
5405  * of the connector. */
5406 bool intel_connector_get_hw_state(struct intel_connector *connector)
5407 {
5408         enum pipe pipe = 0;
5409         struct intel_encoder *encoder = connector->encoder;
5410
5411         return encoder->get_hw_state(encoder, &pipe);
5412 }
5413
5414 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5415                                      struct intel_crtc_state *pipe_config)
5416 {
5417         struct drm_i915_private *dev_priv = dev->dev_private;
5418         struct intel_crtc *pipe_B_crtc =
5419                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5420
5421         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5422                       pipe_name(pipe), pipe_config->fdi_lanes);
5423         if (pipe_config->fdi_lanes > 4) {
5424                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5425                               pipe_name(pipe), pipe_config->fdi_lanes);
5426                 return false;
5427         }
5428
5429         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5430                 if (pipe_config->fdi_lanes > 2) {
5431                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5432                                       pipe_config->fdi_lanes);
5433                         return false;
5434                 } else {
5435                         return true;
5436                 }
5437         }
5438
5439         if (INTEL_INFO(dev)->num_pipes == 2)
5440                 return true;
5441
5442         /* Ivybridge 3 pipe is really complicated */
5443         switch (pipe) {
5444         case PIPE_A:
5445                 return true;
5446         case PIPE_B:
5447                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5448                     pipe_config->fdi_lanes > 2) {
5449                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5450                                       pipe_name(pipe), pipe_config->fdi_lanes);
5451                         return false;
5452                 }
5453                 return true;
5454         case PIPE_C:
5455                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5456                     pipe_B_crtc->config->fdi_lanes <= 2) {
5457                         if (pipe_config->fdi_lanes > 2) {
5458                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5459                                               pipe_name(pipe), pipe_config->fdi_lanes);
5460                                 return false;
5461                         }
5462                 } else {
5463                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5464                         return false;
5465                 }
5466                 return true;
5467         default:
5468                 BUG();
5469         }
5470 }
5471
5472 #define RETRY 1
5473 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5474                                        struct intel_crtc_state *pipe_config)
5475 {
5476         struct drm_device *dev = intel_crtc->base.dev;
5477         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5478         int lane, link_bw, fdi_dotclock;
5479         bool setup_ok, needs_recompute = false;
5480
5481 retry:
5482         /* FDI is a binary signal running at ~2.7GHz, encoding
5483          * each output octet as 10 bits. The actual frequency
5484          * is stored as a divider into a 100MHz clock, and the
5485          * mode pixel clock is stored in units of 1KHz.
5486          * Hence the bw of each lane in terms of the mode signal
5487          * is:
5488          */
5489         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5490
5491         fdi_dotclock = adjusted_mode->crtc_clock;
5492
5493         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5494                                            pipe_config->pipe_bpp);
5495
5496         pipe_config->fdi_lanes = lane;
5497
5498         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5499                                link_bw, &pipe_config->fdi_m_n);
5500
5501         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5502                                             intel_crtc->pipe, pipe_config);
5503         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5504                 pipe_config->pipe_bpp -= 2*3;
5505                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5506                               pipe_config->pipe_bpp);
5507                 needs_recompute = true;
5508                 pipe_config->bw_constrained = true;
5509
5510                 goto retry;
5511         }
5512
5513         if (needs_recompute)
5514                 return RETRY;
5515
5516         return setup_ok ? 0 : -EINVAL;
5517 }
5518
5519 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5520                                    struct intel_crtc_state *pipe_config)
5521 {
5522         pipe_config->ips_enabled = i915.enable_ips &&
5523                                    hsw_crtc_supports_ips(crtc) &&
5524                                    pipe_config->pipe_bpp <= 24;
5525 }
5526
5527 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5528                                      struct intel_crtc_state *pipe_config)
5529 {
5530         struct drm_device *dev = crtc->base.dev;
5531         struct drm_i915_private *dev_priv = dev->dev_private;
5532         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5533
5534         /* FIXME should check pixel clock limits on all platforms */
5535         if (INTEL_INFO(dev)->gen < 4) {
5536                 int clock_limit =
5537                         dev_priv->display.get_display_clock_speed(dev);
5538
5539                 /*
5540                  * Enable pixel doubling when the dot clock
5541                  * is > 90% of the (display) core speed.
5542                  *
5543                  * GDG double wide on either pipe,
5544                  * otherwise pipe A only.
5545                  */
5546                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5547                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5548                         clock_limit *= 2;
5549                         pipe_config->double_wide = true;
5550                 }
5551
5552                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5553                         return -EINVAL;
5554         }
5555
5556         /*
5557          * Pipe horizontal size must be even in:
5558          * - DVO ganged mode
5559          * - LVDS dual channel mode
5560          * - Double wide pipe
5561          */
5562         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5563              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5564                 pipe_config->pipe_src_w &= ~1;
5565
5566         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5567          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5568          */
5569         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5570                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5571                 return -EINVAL;
5572
5573         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5574                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5575         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5576                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5577                  * for lvds. */
5578                 pipe_config->pipe_bpp = 8*3;
5579         }
5580
5581         if (HAS_IPS(dev))
5582                 hsw_compute_ips_config(crtc, pipe_config);
5583
5584         if (pipe_config->has_pch_encoder)
5585                 return ironlake_fdi_compute_config(crtc, pipe_config);
5586
5587         return 0;
5588 }
5589
5590 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5591 {
5592         struct drm_i915_private *dev_priv = dev->dev_private;
5593         u32 val;
5594         int divider;
5595
5596         /* FIXME: Punit isn't quite ready yet */
5597         if (IS_CHERRYVIEW(dev))
5598                 return 400000;
5599
5600         if (dev_priv->hpll_freq == 0)
5601                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5602
5603         mutex_lock(&dev_priv->dpio_lock);
5604         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5605         mutex_unlock(&dev_priv->dpio_lock);
5606
5607         divider = val & DISPLAY_FREQUENCY_VALUES;
5608
5609         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5610              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5611              "cdclk change in progress\n");
5612
5613         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5614 }
5615
5616 static int i945_get_display_clock_speed(struct drm_device *dev)
5617 {
5618         return 400000;
5619 }
5620
5621 static int i915_get_display_clock_speed(struct drm_device *dev)
5622 {
5623         return 333000;
5624 }
5625
5626 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5627 {
5628         return 200000;
5629 }
5630
5631 static int pnv_get_display_clock_speed(struct drm_device *dev)
5632 {
5633         u16 gcfgc = 0;
5634
5635         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5636
5637         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5638         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5639                 return 267000;
5640         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5641                 return 333000;
5642         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5643                 return 444000;
5644         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5645                 return 200000;
5646         default:
5647                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5648         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5649                 return 133000;
5650         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5651                 return 167000;
5652         }
5653 }
5654
5655 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5656 {
5657         u16 gcfgc = 0;
5658
5659         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5660
5661         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5662                 return 133000;
5663         else {
5664                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5665                 case GC_DISPLAY_CLOCK_333_MHZ:
5666                         return 333000;
5667                 default:
5668                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5669                         return 190000;
5670                 }
5671         }
5672 }
5673
5674 static int i865_get_display_clock_speed(struct drm_device *dev)
5675 {
5676         return 266000;
5677 }
5678
5679 static int i855_get_display_clock_speed(struct drm_device *dev)
5680 {
5681         u16 hpllcc = 0;
5682         /* Assume that the hardware is in the high speed state.  This
5683          * should be the default.
5684          */
5685         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5686         case GC_CLOCK_133_200:
5687         case GC_CLOCK_100_200:
5688                 return 200000;
5689         case GC_CLOCK_166_250:
5690                 return 250000;
5691         case GC_CLOCK_100_133:
5692                 return 133000;
5693         }
5694
5695         /* Shouldn't happen */
5696         return 0;
5697 }
5698
5699 static int i830_get_display_clock_speed(struct drm_device *dev)
5700 {
5701         return 133000;
5702 }
5703
5704 static void
5705 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5706 {
5707         while (*num > DATA_LINK_M_N_MASK ||
5708                *den > DATA_LINK_M_N_MASK) {
5709                 *num >>= 1;
5710                 *den >>= 1;
5711         }
5712 }
5713
5714 static void compute_m_n(unsigned int m, unsigned int n,
5715                         uint32_t *ret_m, uint32_t *ret_n)
5716 {
5717         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5718         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5719         intel_reduce_m_n_ratio(ret_m, ret_n);
5720 }
5721
5722 void
5723 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5724                        int pixel_clock, int link_clock,
5725                        struct intel_link_m_n *m_n)
5726 {
5727         m_n->tu = 64;
5728
5729         compute_m_n(bits_per_pixel * pixel_clock,
5730                     link_clock * nlanes * 8,
5731                     &m_n->gmch_m, &m_n->gmch_n);
5732
5733         compute_m_n(pixel_clock, link_clock,
5734                     &m_n->link_m, &m_n->link_n);
5735 }
5736
5737 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5738 {
5739         if (i915.panel_use_ssc >= 0)
5740                 return i915.panel_use_ssc != 0;
5741         return dev_priv->vbt.lvds_use_ssc
5742                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5743 }
5744
5745 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5746 {
5747         struct drm_device *dev = crtc->base.dev;
5748         struct drm_i915_private *dev_priv = dev->dev_private;
5749         int refclk;
5750
5751         if (IS_VALLEYVIEW(dev)) {
5752                 refclk = 100000;
5753         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5754             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5755                 refclk = dev_priv->vbt.lvds_ssc_freq;
5756                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5757         } else if (!IS_GEN2(dev)) {
5758                 refclk = 96000;
5759         } else {
5760                 refclk = 48000;
5761         }
5762
5763         return refclk;
5764 }
5765
5766 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5767 {
5768         return (1 << dpll->n) << 16 | dpll->m2;
5769 }
5770
5771 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5772 {
5773         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5774 }
5775
5776 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5777                                      struct intel_crtc_state *crtc_state,
5778                                      intel_clock_t *reduced_clock)
5779 {
5780         struct drm_device *dev = crtc->base.dev;
5781         u32 fp, fp2 = 0;
5782
5783         if (IS_PINEVIEW(dev)) {
5784                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5785                 if (reduced_clock)
5786                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5787         } else {
5788                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5789                 if (reduced_clock)
5790                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5791         }
5792
5793         crtc_state->dpll_hw_state.fp0 = fp;
5794
5795         crtc->lowfreq_avail = false;
5796         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5797             reduced_clock && i915.powersave) {
5798                 crtc_state->dpll_hw_state.fp1 = fp2;
5799                 crtc->lowfreq_avail = true;
5800         } else {
5801                 crtc_state->dpll_hw_state.fp1 = fp;
5802         }
5803 }
5804
5805 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5806                 pipe)
5807 {
5808         u32 reg_val;
5809
5810         /*
5811          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5812          * and set it to a reasonable value instead.
5813          */
5814         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5815         reg_val &= 0xffffff00;
5816         reg_val |= 0x00000030;
5817         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5818
5819         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5820         reg_val &= 0x8cffffff;
5821         reg_val = 0x8c000000;
5822         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5823
5824         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5825         reg_val &= 0xffffff00;
5826         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5827
5828         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5829         reg_val &= 0x00ffffff;
5830         reg_val |= 0xb0000000;
5831         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5832 }
5833
5834 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5835                                          struct intel_link_m_n *m_n)
5836 {
5837         struct drm_device *dev = crtc->base.dev;
5838         struct drm_i915_private *dev_priv = dev->dev_private;
5839         int pipe = crtc->pipe;
5840
5841         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5842         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5843         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5844         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5845 }
5846
5847 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5848                                          struct intel_link_m_n *m_n,
5849                                          struct intel_link_m_n *m2_n2)
5850 {
5851         struct drm_device *dev = crtc->base.dev;
5852         struct drm_i915_private *dev_priv = dev->dev_private;
5853         int pipe = crtc->pipe;
5854         enum transcoder transcoder = crtc->config->cpu_transcoder;
5855
5856         if (INTEL_INFO(dev)->gen >= 5) {
5857                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5858                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5859                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5860                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5861                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5862                  * for gen < 8) and if DRRS is supported (to make sure the
5863                  * registers are not unnecessarily accessed).
5864                  */
5865                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5866                         crtc->config->has_drrs) {
5867                         I915_WRITE(PIPE_DATA_M2(transcoder),
5868                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5869                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5870                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5871                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5872                 }
5873         } else {
5874                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5875                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5876                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5877                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5878         }
5879 }
5880
5881 void intel_dp_set_m_n(struct intel_crtc *crtc)
5882 {
5883         if (crtc->config->has_pch_encoder)
5884                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5885         else
5886                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
5887                                                    &crtc->config->dp_m2_n2);
5888 }
5889
5890 static void vlv_update_pll(struct intel_crtc *crtc,
5891                            struct intel_crtc_state *pipe_config)
5892 {
5893         u32 dpll, dpll_md;
5894
5895         /*
5896          * Enable DPIO clock input. We should never disable the reference
5897          * clock for pipe B, since VGA hotplug / manual detection depends
5898          * on it.
5899          */
5900         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5901                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5902         /* We should never disable this, set it here for state tracking */
5903         if (crtc->pipe == PIPE_B)
5904                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5905         dpll |= DPLL_VCO_ENABLE;
5906         pipe_config->dpll_hw_state.dpll = dpll;
5907
5908         dpll_md = (pipe_config->pixel_multiplier - 1)
5909                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5910         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5911 }
5912
5913 static void vlv_prepare_pll(struct intel_crtc *crtc,
5914                             const struct intel_crtc_state *pipe_config)
5915 {
5916         struct drm_device *dev = crtc->base.dev;
5917         struct drm_i915_private *dev_priv = dev->dev_private;
5918         int pipe = crtc->pipe;
5919         u32 mdiv;
5920         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5921         u32 coreclk, reg_val;
5922
5923         mutex_lock(&dev_priv->dpio_lock);
5924
5925         bestn = pipe_config->dpll.n;
5926         bestm1 = pipe_config->dpll.m1;
5927         bestm2 = pipe_config->dpll.m2;
5928         bestp1 = pipe_config->dpll.p1;
5929         bestp2 = pipe_config->dpll.p2;
5930
5931         /* See eDP HDMI DPIO driver vbios notes doc */
5932
5933         /* PLL B needs special handling */
5934         if (pipe == PIPE_B)
5935                 vlv_pllb_recal_opamp(dev_priv, pipe);
5936
5937         /* Set up Tx target for periodic Rcomp update */
5938         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5939
5940         /* Disable target IRef on PLL */
5941         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5942         reg_val &= 0x00ffffff;
5943         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5944
5945         /* Disable fast lock */
5946         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5947
5948         /* Set idtafcrecal before PLL is enabled */
5949         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5950         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5951         mdiv |= ((bestn << DPIO_N_SHIFT));
5952         mdiv |= (1 << DPIO_K_SHIFT);
5953
5954         /*
5955          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5956          * but we don't support that).
5957          * Note: don't use the DAC post divider as it seems unstable.
5958          */
5959         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5960         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5961
5962         mdiv |= DPIO_ENABLE_CALIBRATION;
5963         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5964
5965         /* Set HBR and RBR LPF coefficients */
5966         if (pipe_config->port_clock == 162000 ||
5967             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5968             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5969                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5970                                  0x009f0003);
5971         else
5972                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5973                                  0x00d0000f);
5974
5975         if (pipe_config->has_dp_encoder) {
5976                 /* Use SSC source */
5977                 if (pipe == PIPE_A)
5978                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5979                                          0x0df40000);
5980                 else
5981                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5982                                          0x0df70000);
5983         } else { /* HDMI or VGA */
5984                 /* Use bend source */
5985                 if (pipe == PIPE_A)
5986                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5987                                          0x0df70000);
5988                 else
5989                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5990                                          0x0df40000);
5991         }
5992
5993         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5994         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5995         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5996             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5997                 coreclk |= 0x01000000;
5998         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5999
6000         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6001         mutex_unlock(&dev_priv->dpio_lock);
6002 }
6003
6004 static void chv_update_pll(struct intel_crtc *crtc,
6005                            struct intel_crtc_state *pipe_config)
6006 {
6007         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6008                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6009                 DPLL_VCO_ENABLE;
6010         if (crtc->pipe != PIPE_A)
6011                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6012
6013         pipe_config->dpll_hw_state.dpll_md =
6014                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6015 }
6016
6017 static void chv_prepare_pll(struct intel_crtc *crtc,
6018                             const struct intel_crtc_state *pipe_config)
6019 {
6020         struct drm_device *dev = crtc->base.dev;
6021         struct drm_i915_private *dev_priv = dev->dev_private;
6022         int pipe = crtc->pipe;
6023         int dpll_reg = DPLL(crtc->pipe);
6024         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6025         u32 loopfilter, intcoeff;
6026         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6027         int refclk;
6028
6029         bestn = pipe_config->dpll.n;
6030         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6031         bestm1 = pipe_config->dpll.m1;
6032         bestm2 = pipe_config->dpll.m2 >> 22;
6033         bestp1 = pipe_config->dpll.p1;
6034         bestp2 = pipe_config->dpll.p2;
6035
6036         /*
6037          * Enable Refclk and SSC
6038          */
6039         I915_WRITE(dpll_reg,
6040                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6041
6042         mutex_lock(&dev_priv->dpio_lock);
6043
6044         /* p1 and p2 divider */
6045         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6046                         5 << DPIO_CHV_S1_DIV_SHIFT |
6047                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6048                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6049                         1 << DPIO_CHV_K_DIV_SHIFT);
6050
6051         /* Feedback post-divider - m2 */
6052         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6053
6054         /* Feedback refclk divider - n and m1 */
6055         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6056                         DPIO_CHV_M1_DIV_BY_2 |
6057                         1 << DPIO_CHV_N_DIV_SHIFT);
6058
6059         /* M2 fraction division */
6060         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6061
6062         /* M2 fraction division enable */
6063         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6064                        DPIO_CHV_FRAC_DIV_EN |
6065                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6066
6067         /* Loop filter */
6068         refclk = i9xx_get_refclk(crtc, 0);
6069         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6070                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6071         if (refclk == 100000)
6072                 intcoeff = 11;
6073         else if (refclk == 38400)
6074                 intcoeff = 10;
6075         else
6076                 intcoeff = 9;
6077         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6078         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6079
6080         /* AFC Recal */
6081         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6082                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6083                         DPIO_AFC_RECAL);
6084
6085         mutex_unlock(&dev_priv->dpio_lock);
6086 }
6087
6088 /**
6089  * vlv_force_pll_on - forcibly enable just the PLL
6090  * @dev_priv: i915 private structure
6091  * @pipe: pipe PLL to enable
6092  * @dpll: PLL configuration
6093  *
6094  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6095  * in cases where we need the PLL enabled even when @pipe is not going to
6096  * be enabled.
6097  */
6098 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6099                       const struct dpll *dpll)
6100 {
6101         struct intel_crtc *crtc =
6102                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6103         struct intel_crtc_state pipe_config = {
6104                 .pixel_multiplier = 1,
6105                 .dpll = *dpll,
6106         };
6107
6108         if (IS_CHERRYVIEW(dev)) {
6109                 chv_update_pll(crtc, &pipe_config);
6110                 chv_prepare_pll(crtc, &pipe_config);
6111                 chv_enable_pll(crtc, &pipe_config);
6112         } else {
6113                 vlv_update_pll(crtc, &pipe_config);
6114                 vlv_prepare_pll(crtc, &pipe_config);
6115                 vlv_enable_pll(crtc, &pipe_config);
6116         }
6117 }
6118
6119 /**
6120  * vlv_force_pll_off - forcibly disable just the PLL
6121  * @dev_priv: i915 private structure
6122  * @pipe: pipe PLL to disable
6123  *
6124  * Disable the PLL for @pipe. To be used in cases where we need
6125  * the PLL enabled even when @pipe is not going to be enabled.
6126  */
6127 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6128 {
6129         if (IS_CHERRYVIEW(dev))
6130                 chv_disable_pll(to_i915(dev), pipe);
6131         else
6132                 vlv_disable_pll(to_i915(dev), pipe);
6133 }
6134
6135 static void i9xx_update_pll(struct intel_crtc *crtc,
6136                             struct intel_crtc_state *crtc_state,
6137                             intel_clock_t *reduced_clock,
6138                             int num_connectors)
6139 {
6140         struct drm_device *dev = crtc->base.dev;
6141         struct drm_i915_private *dev_priv = dev->dev_private;
6142         u32 dpll;
6143         bool is_sdvo;
6144         struct dpll *clock = &crtc_state->dpll;
6145
6146         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6147
6148         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6149                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6150
6151         dpll = DPLL_VGA_MODE_DIS;
6152
6153         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6154                 dpll |= DPLLB_MODE_LVDS;
6155         else
6156                 dpll |= DPLLB_MODE_DAC_SERIAL;
6157
6158         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6159                 dpll |= (crtc_state->pixel_multiplier - 1)
6160                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6161         }
6162
6163         if (is_sdvo)
6164                 dpll |= DPLL_SDVO_HIGH_SPEED;
6165
6166         if (crtc_state->has_dp_encoder)
6167                 dpll |= DPLL_SDVO_HIGH_SPEED;
6168
6169         /* compute bitmask from p1 value */
6170         if (IS_PINEVIEW(dev))
6171                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6172         else {
6173                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6174                 if (IS_G4X(dev) && reduced_clock)
6175                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6176         }
6177         switch (clock->p2) {
6178         case 5:
6179                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6180                 break;
6181         case 7:
6182                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6183                 break;
6184         case 10:
6185                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6186                 break;
6187         case 14:
6188                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6189                 break;
6190         }
6191         if (INTEL_INFO(dev)->gen >= 4)
6192                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6193
6194         if (crtc_state->sdvo_tv_clock)
6195                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6196         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6197                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6198                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6199         else
6200                 dpll |= PLL_REF_INPUT_DREFCLK;
6201
6202         dpll |= DPLL_VCO_ENABLE;
6203         crtc_state->dpll_hw_state.dpll = dpll;
6204
6205         if (INTEL_INFO(dev)->gen >= 4) {
6206                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6207                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6208                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6209         }
6210 }
6211
6212 static void i8xx_update_pll(struct intel_crtc *crtc,
6213                             struct intel_crtc_state *crtc_state,
6214                             intel_clock_t *reduced_clock,
6215                             int num_connectors)
6216 {
6217         struct drm_device *dev = crtc->base.dev;
6218         struct drm_i915_private *dev_priv = dev->dev_private;
6219         u32 dpll;
6220         struct dpll *clock = &crtc_state->dpll;
6221
6222         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6223
6224         dpll = DPLL_VGA_MODE_DIS;
6225
6226         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6227                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6228         } else {
6229                 if (clock->p1 == 2)
6230                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6231                 else
6232                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6233                 if (clock->p2 == 4)
6234                         dpll |= PLL_P2_DIVIDE_BY_4;
6235         }
6236
6237         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6238                 dpll |= DPLL_DVO_2X_MODE;
6239
6240         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6241                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6242                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6243         else
6244                 dpll |= PLL_REF_INPUT_DREFCLK;
6245
6246         dpll |= DPLL_VCO_ENABLE;
6247         crtc_state->dpll_hw_state.dpll = dpll;
6248 }
6249
6250 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6251 {
6252         struct drm_device *dev = intel_crtc->base.dev;
6253         struct drm_i915_private *dev_priv = dev->dev_private;
6254         enum pipe pipe = intel_crtc->pipe;
6255         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6256         struct drm_display_mode *adjusted_mode =
6257                 &intel_crtc->config->base.adjusted_mode;
6258         uint32_t crtc_vtotal, crtc_vblank_end;
6259         int vsyncshift = 0;
6260
6261         /* We need to be careful not to changed the adjusted mode, for otherwise
6262          * the hw state checker will get angry at the mismatch. */
6263         crtc_vtotal = adjusted_mode->crtc_vtotal;
6264         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6265
6266         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6267                 /* the chip adds 2 halflines automatically */
6268                 crtc_vtotal -= 1;
6269                 crtc_vblank_end -= 1;
6270
6271                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6272                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6273                 else
6274                         vsyncshift = adjusted_mode->crtc_hsync_start -
6275                                 adjusted_mode->crtc_htotal / 2;
6276                 if (vsyncshift < 0)
6277                         vsyncshift += adjusted_mode->crtc_htotal;
6278         }
6279
6280         if (INTEL_INFO(dev)->gen > 3)
6281                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6282
6283         I915_WRITE(HTOTAL(cpu_transcoder),
6284                    (adjusted_mode->crtc_hdisplay - 1) |
6285                    ((adjusted_mode->crtc_htotal - 1) << 16));
6286         I915_WRITE(HBLANK(cpu_transcoder),
6287                    (adjusted_mode->crtc_hblank_start - 1) |
6288                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6289         I915_WRITE(HSYNC(cpu_transcoder),
6290                    (adjusted_mode->crtc_hsync_start - 1) |
6291                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6292
6293         I915_WRITE(VTOTAL(cpu_transcoder),
6294                    (adjusted_mode->crtc_vdisplay - 1) |
6295                    ((crtc_vtotal - 1) << 16));
6296         I915_WRITE(VBLANK(cpu_transcoder),
6297                    (adjusted_mode->crtc_vblank_start - 1) |
6298                    ((crtc_vblank_end - 1) << 16));
6299         I915_WRITE(VSYNC(cpu_transcoder),
6300                    (adjusted_mode->crtc_vsync_start - 1) |
6301                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6302
6303         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6304          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6305          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6306          * bits. */
6307         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6308             (pipe == PIPE_B || pipe == PIPE_C))
6309                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6310
6311         /* pipesrc controls the size that is scaled from, which should
6312          * always be the user's requested size.
6313          */
6314         I915_WRITE(PIPESRC(pipe),
6315                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6316                    (intel_crtc->config->pipe_src_h - 1));
6317 }
6318
6319 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6320                                    struct intel_crtc_state *pipe_config)
6321 {
6322         struct drm_device *dev = crtc->base.dev;
6323         struct drm_i915_private *dev_priv = dev->dev_private;
6324         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6325         uint32_t tmp;
6326
6327         tmp = I915_READ(HTOTAL(cpu_transcoder));
6328         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6329         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6330         tmp = I915_READ(HBLANK(cpu_transcoder));
6331         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6332         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6333         tmp = I915_READ(HSYNC(cpu_transcoder));
6334         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6335         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6336
6337         tmp = I915_READ(VTOTAL(cpu_transcoder));
6338         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6339         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6340         tmp = I915_READ(VBLANK(cpu_transcoder));
6341         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6342         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6343         tmp = I915_READ(VSYNC(cpu_transcoder));
6344         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6345         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6346
6347         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6348                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6349                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6350                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6351         }
6352
6353         tmp = I915_READ(PIPESRC(crtc->pipe));
6354         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6355         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6356
6357         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6358         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6359 }
6360
6361 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6362                                  struct intel_crtc_state *pipe_config)
6363 {
6364         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6365         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6366         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6367         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6368
6369         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6370         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6371         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6372         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6373
6374         mode->flags = pipe_config->base.adjusted_mode.flags;
6375
6376         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6377         mode->flags |= pipe_config->base.adjusted_mode.flags;
6378 }
6379
6380 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6381 {
6382         struct drm_device *dev = intel_crtc->base.dev;
6383         struct drm_i915_private *dev_priv = dev->dev_private;
6384         uint32_t pipeconf;
6385
6386         pipeconf = 0;
6387
6388         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6389             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6390                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6391
6392         if (intel_crtc->config->double_wide)
6393                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6394
6395         /* only g4x and later have fancy bpc/dither controls */
6396         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6397                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6398                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6399                         pipeconf |= PIPECONF_DITHER_EN |
6400                                     PIPECONF_DITHER_TYPE_SP;
6401
6402                 switch (intel_crtc->config->pipe_bpp) {
6403                 case 18:
6404                         pipeconf |= PIPECONF_6BPC;
6405                         break;
6406                 case 24:
6407                         pipeconf |= PIPECONF_8BPC;
6408                         break;
6409                 case 30:
6410                         pipeconf |= PIPECONF_10BPC;
6411                         break;
6412                 default:
6413                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6414                         BUG();
6415                 }
6416         }
6417
6418         if (HAS_PIPE_CXSR(dev)) {
6419                 if (intel_crtc->lowfreq_avail) {
6420                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6421                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6422                 } else {
6423                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6424                 }
6425         }
6426
6427         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6428                 if (INTEL_INFO(dev)->gen < 4 ||
6429                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6430                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6431                 else
6432                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6433         } else
6434                 pipeconf |= PIPECONF_PROGRESSIVE;
6435
6436         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6437                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6438
6439         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6440         POSTING_READ(PIPECONF(intel_crtc->pipe));
6441 }
6442
6443 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6444                                    struct intel_crtc_state *crtc_state)
6445 {
6446         struct drm_device *dev = crtc->base.dev;
6447         struct drm_i915_private *dev_priv = dev->dev_private;
6448         int refclk, num_connectors = 0;
6449         intel_clock_t clock, reduced_clock;
6450         bool ok, has_reduced_clock = false;
6451         bool is_lvds = false, is_dsi = false;
6452         struct intel_encoder *encoder;
6453         const intel_limit_t *limit;
6454
6455         for_each_intel_encoder(dev, encoder) {
6456                 if (encoder->new_crtc != crtc)
6457                         continue;
6458
6459                 switch (encoder->type) {
6460                 case INTEL_OUTPUT_LVDS:
6461                         is_lvds = true;
6462                         break;
6463                 case INTEL_OUTPUT_DSI:
6464                         is_dsi = true;
6465                         break;
6466                 default:
6467                         break;
6468                 }
6469
6470                 num_connectors++;
6471         }
6472
6473         if (is_dsi)
6474                 return 0;
6475
6476         if (!crtc_state->clock_set) {
6477                 refclk = i9xx_get_refclk(crtc, num_connectors);
6478
6479                 /*
6480                  * Returns a set of divisors for the desired target clock with
6481                  * the given refclk, or FALSE.  The returned values represent
6482                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6483                  * 2) / p1 / p2.
6484                  */
6485                 limit = intel_limit(crtc, refclk);
6486                 ok = dev_priv->display.find_dpll(limit, crtc,
6487                                                  crtc_state->port_clock,
6488                                                  refclk, NULL, &clock);
6489                 if (!ok) {
6490                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6491                         return -EINVAL;
6492                 }
6493
6494                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6495                         /*
6496                          * Ensure we match the reduced clock's P to the target
6497                          * clock.  If the clocks don't match, we can't switch
6498                          * the display clock by using the FP0/FP1. In such case
6499                          * we will disable the LVDS downclock feature.
6500                          */
6501                         has_reduced_clock =
6502                                 dev_priv->display.find_dpll(limit, crtc,
6503                                                             dev_priv->lvds_downclock,
6504                                                             refclk, &clock,
6505                                                             &reduced_clock);
6506                 }
6507                 /* Compat-code for transition, will disappear. */
6508                 crtc_state->dpll.n = clock.n;
6509                 crtc_state->dpll.m1 = clock.m1;
6510                 crtc_state->dpll.m2 = clock.m2;
6511                 crtc_state->dpll.p1 = clock.p1;
6512                 crtc_state->dpll.p2 = clock.p2;
6513         }
6514
6515         if (IS_GEN2(dev)) {
6516                 i8xx_update_pll(crtc, crtc_state,
6517                                 has_reduced_clock ? &reduced_clock : NULL,
6518                                 num_connectors);
6519         } else if (IS_CHERRYVIEW(dev)) {
6520                 chv_update_pll(crtc, crtc_state);
6521         } else if (IS_VALLEYVIEW(dev)) {
6522                 vlv_update_pll(crtc, crtc_state);
6523         } else {
6524                 i9xx_update_pll(crtc, crtc_state,
6525                                 has_reduced_clock ? &reduced_clock : NULL,
6526                                 num_connectors);
6527         }
6528
6529         return 0;
6530 }
6531
6532 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6533                                  struct intel_crtc_state *pipe_config)
6534 {
6535         struct drm_device *dev = crtc->base.dev;
6536         struct drm_i915_private *dev_priv = dev->dev_private;
6537         uint32_t tmp;
6538
6539         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6540                 return;
6541
6542         tmp = I915_READ(PFIT_CONTROL);
6543         if (!(tmp & PFIT_ENABLE))
6544                 return;
6545
6546         /* Check whether the pfit is attached to our pipe. */
6547         if (INTEL_INFO(dev)->gen < 4) {
6548                 if (crtc->pipe != PIPE_B)
6549                         return;
6550         } else {
6551                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6552                         return;
6553         }
6554
6555         pipe_config->gmch_pfit.control = tmp;
6556         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6557         if (INTEL_INFO(dev)->gen < 5)
6558                 pipe_config->gmch_pfit.lvds_border_bits =
6559                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6560 }
6561
6562 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6563                                struct intel_crtc_state *pipe_config)
6564 {
6565         struct drm_device *dev = crtc->base.dev;
6566         struct drm_i915_private *dev_priv = dev->dev_private;
6567         int pipe = pipe_config->cpu_transcoder;
6568         intel_clock_t clock;
6569         u32 mdiv;
6570         int refclk = 100000;
6571
6572         /* In case of MIPI DPLL will not even be used */
6573         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6574                 return;
6575
6576         mutex_lock(&dev_priv->dpio_lock);
6577         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6578         mutex_unlock(&dev_priv->dpio_lock);
6579
6580         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6581         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6582         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6583         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6584         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6585
6586         vlv_clock(refclk, &clock);
6587
6588         /* clock.dot is the fast clock */
6589         pipe_config->port_clock = clock.dot / 5;
6590 }
6591
6592 static void
6593 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6594                               struct intel_initial_plane_config *plane_config)
6595 {
6596         struct drm_device *dev = crtc->base.dev;
6597         struct drm_i915_private *dev_priv = dev->dev_private;
6598         u32 val, base, offset;
6599         int pipe = crtc->pipe, plane = crtc->plane;
6600         int fourcc, pixel_format;
6601         int aligned_height;
6602         struct drm_framebuffer *fb;
6603         struct intel_framebuffer *intel_fb;
6604
6605         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6606         if (!intel_fb) {
6607                 DRM_DEBUG_KMS("failed to alloc fb\n");
6608                 return;
6609         }
6610
6611         fb = &intel_fb->base;
6612
6613         val = I915_READ(DSPCNTR(plane));
6614
6615         if (INTEL_INFO(dev)->gen >= 4)
6616                 if (val & DISPPLANE_TILED)
6617                         plane_config->tiling = I915_TILING_X;
6618
6619         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6620         fourcc = i9xx_format_to_fourcc(pixel_format);
6621         fb->pixel_format = fourcc;
6622         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6623
6624         if (INTEL_INFO(dev)->gen >= 4) {
6625                 if (plane_config->tiling)
6626                         offset = I915_READ(DSPTILEOFF(plane));
6627                 else
6628                         offset = I915_READ(DSPLINOFF(plane));
6629                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6630         } else {
6631                 base = I915_READ(DSPADDR(plane));
6632         }
6633         plane_config->base = base;
6634
6635         val = I915_READ(PIPESRC(pipe));
6636         fb->width = ((val >> 16) & 0xfff) + 1;
6637         fb->height = ((val >> 0) & 0xfff) + 1;
6638
6639         val = I915_READ(DSPSTRIDE(pipe));
6640         fb->pitches[0] = val & 0xffffffc0;
6641
6642         aligned_height = intel_fb_align_height(dev, fb->height,
6643                                                plane_config->tiling);
6644
6645         plane_config->size = fb->pitches[0] * aligned_height;
6646
6647         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6648                       pipe_name(pipe), plane, fb->width, fb->height,
6649                       fb->bits_per_pixel, base, fb->pitches[0],
6650                       plane_config->size);
6651
6652         crtc->base.primary->fb = fb;
6653 }
6654
6655 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6656                                struct intel_crtc_state *pipe_config)
6657 {
6658         struct drm_device *dev = crtc->base.dev;
6659         struct drm_i915_private *dev_priv = dev->dev_private;
6660         int pipe = pipe_config->cpu_transcoder;
6661         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6662         intel_clock_t clock;
6663         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6664         int refclk = 100000;
6665
6666         mutex_lock(&dev_priv->dpio_lock);
6667         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6668         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6669         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6670         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6671         mutex_unlock(&dev_priv->dpio_lock);
6672
6673         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6674         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6675         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6676         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6677         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6678
6679         chv_clock(refclk, &clock);
6680
6681         /* clock.dot is the fast clock */
6682         pipe_config->port_clock = clock.dot / 5;
6683 }
6684
6685 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6686                                  struct intel_crtc_state *pipe_config)
6687 {
6688         struct drm_device *dev = crtc->base.dev;
6689         struct drm_i915_private *dev_priv = dev->dev_private;
6690         uint32_t tmp;
6691
6692         if (!intel_display_power_is_enabled(dev_priv,
6693                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6694                 return false;
6695
6696         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6697         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6698
6699         tmp = I915_READ(PIPECONF(crtc->pipe));
6700         if (!(tmp & PIPECONF_ENABLE))
6701                 return false;
6702
6703         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6704                 switch (tmp & PIPECONF_BPC_MASK) {
6705                 case PIPECONF_6BPC:
6706                         pipe_config->pipe_bpp = 18;
6707                         break;
6708                 case PIPECONF_8BPC:
6709                         pipe_config->pipe_bpp = 24;
6710                         break;
6711                 case PIPECONF_10BPC:
6712                         pipe_config->pipe_bpp = 30;
6713                         break;
6714                 default:
6715                         break;
6716                 }
6717         }
6718
6719         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6720                 pipe_config->limited_color_range = true;
6721
6722         if (INTEL_INFO(dev)->gen < 4)
6723                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6724
6725         intel_get_pipe_timings(crtc, pipe_config);
6726
6727         i9xx_get_pfit_config(crtc, pipe_config);
6728
6729         if (INTEL_INFO(dev)->gen >= 4) {
6730                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6731                 pipe_config->pixel_multiplier =
6732                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6733                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6734                 pipe_config->dpll_hw_state.dpll_md = tmp;
6735         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6736                 tmp = I915_READ(DPLL(crtc->pipe));
6737                 pipe_config->pixel_multiplier =
6738                         ((tmp & SDVO_MULTIPLIER_MASK)
6739                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6740         } else {
6741                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6742                  * port and will be fixed up in the encoder->get_config
6743                  * function. */
6744                 pipe_config->pixel_multiplier = 1;
6745         }
6746         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6747         if (!IS_VALLEYVIEW(dev)) {
6748                 /*
6749                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6750                  * on 830. Filter it out here so that we don't
6751                  * report errors due to that.
6752                  */
6753                 if (IS_I830(dev))
6754                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6755
6756                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6757                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6758         } else {
6759                 /* Mask out read-only status bits. */
6760                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6761                                                      DPLL_PORTC_READY_MASK |
6762                                                      DPLL_PORTB_READY_MASK);
6763         }
6764
6765         if (IS_CHERRYVIEW(dev))
6766                 chv_crtc_clock_get(crtc, pipe_config);
6767         else if (IS_VALLEYVIEW(dev))
6768                 vlv_crtc_clock_get(crtc, pipe_config);
6769         else
6770                 i9xx_crtc_clock_get(crtc, pipe_config);
6771
6772         return true;
6773 }
6774
6775 static void ironlake_init_pch_refclk(struct drm_device *dev)
6776 {
6777         struct drm_i915_private *dev_priv = dev->dev_private;
6778         struct intel_encoder *encoder;
6779         u32 val, final;
6780         bool has_lvds = false;
6781         bool has_cpu_edp = false;
6782         bool has_panel = false;
6783         bool has_ck505 = false;
6784         bool can_ssc = false;
6785
6786         /* We need to take the global config into account */
6787         for_each_intel_encoder(dev, encoder) {
6788                 switch (encoder->type) {
6789                 case INTEL_OUTPUT_LVDS:
6790                         has_panel = true;
6791                         has_lvds = true;
6792                         break;
6793                 case INTEL_OUTPUT_EDP:
6794                         has_panel = true;
6795                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6796                                 has_cpu_edp = true;
6797                         break;
6798                 default:
6799                         break;
6800                 }
6801         }
6802
6803         if (HAS_PCH_IBX(dev)) {
6804                 has_ck505 = dev_priv->vbt.display_clock_mode;
6805                 can_ssc = has_ck505;
6806         } else {
6807                 has_ck505 = false;
6808                 can_ssc = true;
6809         }
6810
6811         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6812                       has_panel, has_lvds, has_ck505);
6813
6814         /* Ironlake: try to setup display ref clock before DPLL
6815          * enabling. This is only under driver's control after
6816          * PCH B stepping, previous chipset stepping should be
6817          * ignoring this setting.
6818          */
6819         val = I915_READ(PCH_DREF_CONTROL);
6820
6821         /* As we must carefully and slowly disable/enable each source in turn,
6822          * compute the final state we want first and check if we need to
6823          * make any changes at all.
6824          */
6825         final = val;
6826         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6827         if (has_ck505)
6828                 final |= DREF_NONSPREAD_CK505_ENABLE;
6829         else
6830                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6831
6832         final &= ~DREF_SSC_SOURCE_MASK;
6833         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6834         final &= ~DREF_SSC1_ENABLE;
6835
6836         if (has_panel) {
6837                 final |= DREF_SSC_SOURCE_ENABLE;
6838
6839                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6840                         final |= DREF_SSC1_ENABLE;
6841
6842                 if (has_cpu_edp) {
6843                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6844                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6845                         else
6846                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6847                 } else
6848                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6849         } else {
6850                 final |= DREF_SSC_SOURCE_DISABLE;
6851                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6852         }
6853
6854         if (final == val)
6855                 return;
6856
6857         /* Always enable nonspread source */
6858         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6859
6860         if (has_ck505)
6861                 val |= DREF_NONSPREAD_CK505_ENABLE;
6862         else
6863                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6864
6865         if (has_panel) {
6866                 val &= ~DREF_SSC_SOURCE_MASK;
6867                 val |= DREF_SSC_SOURCE_ENABLE;
6868
6869                 /* SSC must be turned on before enabling the CPU output  */
6870                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6871                         DRM_DEBUG_KMS("Using SSC on panel\n");
6872                         val |= DREF_SSC1_ENABLE;
6873                 } else
6874                         val &= ~DREF_SSC1_ENABLE;
6875
6876                 /* Get SSC going before enabling the outputs */
6877                 I915_WRITE(PCH_DREF_CONTROL, val);
6878                 POSTING_READ(PCH_DREF_CONTROL);
6879                 udelay(200);
6880
6881                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6882
6883                 /* Enable CPU source on CPU attached eDP */
6884                 if (has_cpu_edp) {
6885                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6886                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6887                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6888                         } else
6889                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6890                 } else
6891                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6892
6893                 I915_WRITE(PCH_DREF_CONTROL, val);
6894                 POSTING_READ(PCH_DREF_CONTROL);
6895                 udelay(200);
6896         } else {
6897                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6898
6899                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6900
6901                 /* Turn off CPU output */
6902                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6903
6904                 I915_WRITE(PCH_DREF_CONTROL, val);
6905                 POSTING_READ(PCH_DREF_CONTROL);
6906                 udelay(200);
6907
6908                 /* Turn off the SSC source */
6909                 val &= ~DREF_SSC_SOURCE_MASK;
6910                 val |= DREF_SSC_SOURCE_DISABLE;
6911
6912                 /* Turn off SSC1 */
6913                 val &= ~DREF_SSC1_ENABLE;
6914
6915                 I915_WRITE(PCH_DREF_CONTROL, val);
6916                 POSTING_READ(PCH_DREF_CONTROL);
6917                 udelay(200);
6918         }
6919
6920         BUG_ON(val != final);
6921 }
6922
6923 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6924 {
6925         uint32_t tmp;
6926
6927         tmp = I915_READ(SOUTH_CHICKEN2);
6928         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6929         I915_WRITE(SOUTH_CHICKEN2, tmp);
6930
6931         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6932                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6933                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6934
6935         tmp = I915_READ(SOUTH_CHICKEN2);
6936         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6937         I915_WRITE(SOUTH_CHICKEN2, tmp);
6938
6939         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6940                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6941                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6942 }
6943
6944 /* WaMPhyProgramming:hsw */
6945 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6946 {
6947         uint32_t tmp;
6948
6949         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6950         tmp &= ~(0xFF << 24);
6951         tmp |= (0x12 << 24);
6952         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6953
6954         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6955         tmp |= (1 << 11);
6956         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6957
6958         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6959         tmp |= (1 << 11);
6960         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6961
6962         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6963         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6964         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6965
6966         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6967         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6968         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6969
6970         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6971         tmp &= ~(7 << 13);
6972         tmp |= (5 << 13);
6973         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6974
6975         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6976         tmp &= ~(7 << 13);
6977         tmp |= (5 << 13);
6978         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6979
6980         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6981         tmp &= ~0xFF;
6982         tmp |= 0x1C;
6983         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6984
6985         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6986         tmp &= ~0xFF;
6987         tmp |= 0x1C;
6988         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6989
6990         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6991         tmp &= ~(0xFF << 16);
6992         tmp |= (0x1C << 16);
6993         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6994
6995         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6996         tmp &= ~(0xFF << 16);
6997         tmp |= (0x1C << 16);
6998         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6999
7000         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7001         tmp |= (1 << 27);
7002         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7003
7004         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7005         tmp |= (1 << 27);
7006         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7007
7008         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7009         tmp &= ~(0xF << 28);
7010         tmp |= (4 << 28);
7011         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7012
7013         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7014         tmp &= ~(0xF << 28);
7015         tmp |= (4 << 28);
7016         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7017 }
7018
7019 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7020  * Programming" based on the parameters passed:
7021  * - Sequence to enable CLKOUT_DP
7022  * - Sequence to enable CLKOUT_DP without spread
7023  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7024  */
7025 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7026                                  bool with_fdi)
7027 {
7028         struct drm_i915_private *dev_priv = dev->dev_private;
7029         uint32_t reg, tmp;
7030
7031         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7032                 with_spread = true;
7033         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7034                  with_fdi, "LP PCH doesn't have FDI\n"))
7035                 with_fdi = false;
7036
7037         mutex_lock(&dev_priv->dpio_lock);
7038
7039         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7040         tmp &= ~SBI_SSCCTL_DISABLE;
7041         tmp |= SBI_SSCCTL_PATHALT;
7042         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7043
7044         udelay(24);
7045
7046         if (with_spread) {
7047                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7048                 tmp &= ~SBI_SSCCTL_PATHALT;
7049                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7050
7051                 if (with_fdi) {
7052                         lpt_reset_fdi_mphy(dev_priv);
7053                         lpt_program_fdi_mphy(dev_priv);
7054                 }
7055         }
7056
7057         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7058                SBI_GEN0 : SBI_DBUFF0;
7059         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7060         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7061         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7062
7063         mutex_unlock(&dev_priv->dpio_lock);
7064 }
7065
7066 /* Sequence to disable CLKOUT_DP */
7067 static void lpt_disable_clkout_dp(struct drm_device *dev)
7068 {
7069         struct drm_i915_private *dev_priv = dev->dev_private;
7070         uint32_t reg, tmp;
7071
7072         mutex_lock(&dev_priv->dpio_lock);
7073
7074         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7075                SBI_GEN0 : SBI_DBUFF0;
7076         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7077         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7078         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7079
7080         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7081         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7082                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7083                         tmp |= SBI_SSCCTL_PATHALT;
7084                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7085                         udelay(32);
7086                 }
7087                 tmp |= SBI_SSCCTL_DISABLE;
7088                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7089         }
7090
7091         mutex_unlock(&dev_priv->dpio_lock);
7092 }
7093
7094 static void lpt_init_pch_refclk(struct drm_device *dev)
7095 {
7096         struct intel_encoder *encoder;
7097         bool has_vga = false;
7098
7099         for_each_intel_encoder(dev, encoder) {
7100                 switch (encoder->type) {
7101                 case INTEL_OUTPUT_ANALOG:
7102                         has_vga = true;
7103                         break;
7104                 default:
7105                         break;
7106                 }
7107         }
7108
7109         if (has_vga)
7110                 lpt_enable_clkout_dp(dev, true, true);
7111         else
7112                 lpt_disable_clkout_dp(dev);
7113 }
7114
7115 /*
7116  * Initialize reference clocks when the driver loads
7117  */
7118 void intel_init_pch_refclk(struct drm_device *dev)
7119 {
7120         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7121                 ironlake_init_pch_refclk(dev);
7122         else if (HAS_PCH_LPT(dev))
7123                 lpt_init_pch_refclk(dev);
7124 }
7125
7126 static int ironlake_get_refclk(struct drm_crtc *crtc)
7127 {
7128         struct drm_device *dev = crtc->dev;
7129         struct drm_i915_private *dev_priv = dev->dev_private;
7130         struct intel_encoder *encoder;
7131         int num_connectors = 0;
7132         bool is_lvds = false;
7133
7134         for_each_intel_encoder(dev, encoder) {
7135                 if (encoder->new_crtc != to_intel_crtc(crtc))
7136                         continue;
7137
7138                 switch (encoder->type) {
7139                 case INTEL_OUTPUT_LVDS:
7140                         is_lvds = true;
7141                         break;
7142                 default:
7143                         break;
7144                 }
7145                 num_connectors++;
7146         }
7147
7148         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7149                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7150                               dev_priv->vbt.lvds_ssc_freq);
7151                 return dev_priv->vbt.lvds_ssc_freq;
7152         }
7153
7154         return 120000;
7155 }
7156
7157 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7158 {
7159         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7161         int pipe = intel_crtc->pipe;
7162         uint32_t val;
7163
7164         val = 0;
7165
7166         switch (intel_crtc->config->pipe_bpp) {
7167         case 18:
7168                 val |= PIPECONF_6BPC;
7169                 break;
7170         case 24:
7171                 val |= PIPECONF_8BPC;
7172                 break;
7173         case 30:
7174                 val |= PIPECONF_10BPC;
7175                 break;
7176         case 36:
7177                 val |= PIPECONF_12BPC;
7178                 break;
7179         default:
7180                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7181                 BUG();
7182         }
7183
7184         if (intel_crtc->config->dither)
7185                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7186
7187         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7188                 val |= PIPECONF_INTERLACED_ILK;
7189         else
7190                 val |= PIPECONF_PROGRESSIVE;
7191
7192         if (intel_crtc->config->limited_color_range)
7193                 val |= PIPECONF_COLOR_RANGE_SELECT;
7194
7195         I915_WRITE(PIPECONF(pipe), val);
7196         POSTING_READ(PIPECONF(pipe));
7197 }
7198
7199 /*
7200  * Set up the pipe CSC unit.
7201  *
7202  * Currently only full range RGB to limited range RGB conversion
7203  * is supported, but eventually this should handle various
7204  * RGB<->YCbCr scenarios as well.
7205  */
7206 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7207 {
7208         struct drm_device *dev = crtc->dev;
7209         struct drm_i915_private *dev_priv = dev->dev_private;
7210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7211         int pipe = intel_crtc->pipe;
7212         uint16_t coeff = 0x7800; /* 1.0 */
7213
7214         /*
7215          * TODO: Check what kind of values actually come out of the pipe
7216          * with these coeff/postoff values and adjust to get the best
7217          * accuracy. Perhaps we even need to take the bpc value into
7218          * consideration.
7219          */
7220
7221         if (intel_crtc->config->limited_color_range)
7222                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7223
7224         /*
7225          * GY/GU and RY/RU should be the other way around according
7226          * to BSpec, but reality doesn't agree. Just set them up in
7227          * a way that results in the correct picture.
7228          */
7229         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7230         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7231
7232         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7233         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7234
7235         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7236         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7237
7238         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7239         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7240         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7241
7242         if (INTEL_INFO(dev)->gen > 6) {
7243                 uint16_t postoff = 0;
7244
7245                 if (intel_crtc->config->limited_color_range)
7246                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7247
7248                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7249                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7250                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7251
7252                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7253         } else {
7254                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7255
7256                 if (intel_crtc->config->limited_color_range)
7257                         mode |= CSC_BLACK_SCREEN_OFFSET;
7258
7259                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7260         }
7261 }
7262
7263 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7264 {
7265         struct drm_device *dev = crtc->dev;
7266         struct drm_i915_private *dev_priv = dev->dev_private;
7267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7268         enum pipe pipe = intel_crtc->pipe;
7269         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7270         uint32_t val;
7271
7272         val = 0;
7273
7274         if (IS_HASWELL(dev) && intel_crtc->config->dither)
7275                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7276
7277         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7278                 val |= PIPECONF_INTERLACED_ILK;
7279         else
7280                 val |= PIPECONF_PROGRESSIVE;
7281
7282         I915_WRITE(PIPECONF(cpu_transcoder), val);
7283         POSTING_READ(PIPECONF(cpu_transcoder));
7284
7285         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7286         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7287
7288         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7289                 val = 0;
7290
7291                 switch (intel_crtc->config->pipe_bpp) {
7292                 case 18:
7293                         val |= PIPEMISC_DITHER_6_BPC;
7294                         break;
7295                 case 24:
7296                         val |= PIPEMISC_DITHER_8_BPC;
7297                         break;
7298                 case 30:
7299                         val |= PIPEMISC_DITHER_10_BPC;
7300                         break;
7301                 case 36:
7302                         val |= PIPEMISC_DITHER_12_BPC;
7303                         break;
7304                 default:
7305                         /* Case prevented by pipe_config_set_bpp. */
7306                         BUG();
7307                 }
7308
7309                 if (intel_crtc->config->dither)
7310                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7311
7312                 I915_WRITE(PIPEMISC(pipe), val);
7313         }
7314 }
7315
7316 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7317                                     struct intel_crtc_state *crtc_state,
7318                                     intel_clock_t *clock,
7319                                     bool *has_reduced_clock,
7320                                     intel_clock_t *reduced_clock)
7321 {
7322         struct drm_device *dev = crtc->dev;
7323         struct drm_i915_private *dev_priv = dev->dev_private;
7324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7325         int refclk;
7326         const intel_limit_t *limit;
7327         bool ret, is_lvds = false;
7328
7329         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7330
7331         refclk = ironlake_get_refclk(crtc);
7332
7333         /*
7334          * Returns a set of divisors for the desired target clock with the given
7335          * refclk, or FALSE.  The returned values represent the clock equation:
7336          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7337          */
7338         limit = intel_limit(intel_crtc, refclk);
7339         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7340                                           crtc_state->port_clock,
7341                                           refclk, NULL, clock);
7342         if (!ret)
7343                 return false;
7344
7345         if (is_lvds && dev_priv->lvds_downclock_avail) {
7346                 /*
7347                  * Ensure we match the reduced clock's P to the target clock.
7348                  * If the clocks don't match, we can't switch the display clock
7349                  * by using the FP0/FP1. In such case we will disable the LVDS
7350                  * downclock feature.
7351                 */
7352                 *has_reduced_clock =
7353                         dev_priv->display.find_dpll(limit, intel_crtc,
7354                                                     dev_priv->lvds_downclock,
7355                                                     refclk, clock,
7356                                                     reduced_clock);
7357         }
7358
7359         return true;
7360 }
7361
7362 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7363 {
7364         /*
7365          * Account for spread spectrum to avoid
7366          * oversubscribing the link. Max center spread
7367          * is 2.5%; use 5% for safety's sake.
7368          */
7369         u32 bps = target_clock * bpp * 21 / 20;
7370         return DIV_ROUND_UP(bps, link_bw * 8);
7371 }
7372
7373 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7374 {
7375         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7376 }
7377
7378 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7379                                       struct intel_crtc_state *crtc_state,
7380                                       u32 *fp,
7381                                       intel_clock_t *reduced_clock, u32 *fp2)
7382 {
7383         struct drm_crtc *crtc = &intel_crtc->base;
7384         struct drm_device *dev = crtc->dev;
7385         struct drm_i915_private *dev_priv = dev->dev_private;
7386         struct intel_encoder *intel_encoder;
7387         uint32_t dpll;
7388         int factor, num_connectors = 0;
7389         bool is_lvds = false, is_sdvo = false;
7390
7391         for_each_intel_encoder(dev, intel_encoder) {
7392                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7393                         continue;
7394
7395                 switch (intel_encoder->type) {
7396                 case INTEL_OUTPUT_LVDS:
7397                         is_lvds = true;
7398                         break;
7399                 case INTEL_OUTPUT_SDVO:
7400                 case INTEL_OUTPUT_HDMI:
7401                         is_sdvo = true;
7402                         break;
7403                 default:
7404                         break;
7405                 }
7406
7407                 num_connectors++;
7408         }
7409
7410         /* Enable autotuning of the PLL clock (if permissible) */
7411         factor = 21;
7412         if (is_lvds) {
7413                 if ((intel_panel_use_ssc(dev_priv) &&
7414                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7415                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7416                         factor = 25;
7417         } else if (crtc_state->sdvo_tv_clock)
7418                 factor = 20;
7419
7420         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7421                 *fp |= FP_CB_TUNE;
7422
7423         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7424                 *fp2 |= FP_CB_TUNE;
7425
7426         dpll = 0;
7427
7428         if (is_lvds)
7429                 dpll |= DPLLB_MODE_LVDS;
7430         else
7431                 dpll |= DPLLB_MODE_DAC_SERIAL;
7432
7433         dpll |= (crtc_state->pixel_multiplier - 1)
7434                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7435
7436         if (is_sdvo)
7437                 dpll |= DPLL_SDVO_HIGH_SPEED;
7438         if (crtc_state->has_dp_encoder)
7439                 dpll |= DPLL_SDVO_HIGH_SPEED;
7440
7441         /* compute bitmask from p1 value */
7442         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7443         /* also FPA1 */
7444         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7445
7446         switch (crtc_state->dpll.p2) {
7447         case 5:
7448                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7449                 break;
7450         case 7:
7451                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7452                 break;
7453         case 10:
7454                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7455                 break;
7456         case 14:
7457                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7458                 break;
7459         }
7460
7461         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7462                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7463         else
7464                 dpll |= PLL_REF_INPUT_DREFCLK;
7465
7466         return dpll | DPLL_VCO_ENABLE;
7467 }
7468
7469 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7470                                        struct intel_crtc_state *crtc_state)
7471 {
7472         struct drm_device *dev = crtc->base.dev;
7473         intel_clock_t clock, reduced_clock;
7474         u32 dpll = 0, fp = 0, fp2 = 0;
7475         bool ok, has_reduced_clock = false;
7476         bool is_lvds = false;
7477         struct intel_shared_dpll *pll;
7478
7479         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7480
7481         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7482              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7483
7484         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7485                                      &has_reduced_clock, &reduced_clock);
7486         if (!ok && !crtc_state->clock_set) {
7487                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7488                 return -EINVAL;
7489         }
7490         /* Compat-code for transition, will disappear. */
7491         if (!crtc_state->clock_set) {
7492                 crtc_state->dpll.n = clock.n;
7493                 crtc_state->dpll.m1 = clock.m1;
7494                 crtc_state->dpll.m2 = clock.m2;
7495                 crtc_state->dpll.p1 = clock.p1;
7496                 crtc_state->dpll.p2 = clock.p2;
7497         }
7498
7499         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7500         if (crtc_state->has_pch_encoder) {
7501                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7502                 if (has_reduced_clock)
7503                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7504
7505                 dpll = ironlake_compute_dpll(crtc, crtc_state,
7506                                              &fp, &reduced_clock,
7507                                              has_reduced_clock ? &fp2 : NULL);
7508
7509                 crtc_state->dpll_hw_state.dpll = dpll;
7510                 crtc_state->dpll_hw_state.fp0 = fp;
7511                 if (has_reduced_clock)
7512                         crtc_state->dpll_hw_state.fp1 = fp2;
7513                 else
7514                         crtc_state->dpll_hw_state.fp1 = fp;
7515
7516                 pll = intel_get_shared_dpll(crtc, crtc_state);
7517                 if (pll == NULL) {
7518                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7519                                          pipe_name(crtc->pipe));
7520                         return -EINVAL;
7521                 }
7522         }
7523
7524         if (is_lvds && has_reduced_clock && i915.powersave)
7525                 crtc->lowfreq_avail = true;
7526         else
7527                 crtc->lowfreq_avail = false;
7528
7529         return 0;
7530 }
7531
7532 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7533                                          struct intel_link_m_n *m_n)
7534 {
7535         struct drm_device *dev = crtc->base.dev;
7536         struct drm_i915_private *dev_priv = dev->dev_private;
7537         enum pipe pipe = crtc->pipe;
7538
7539         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7540         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7541         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7542                 & ~TU_SIZE_MASK;
7543         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7544         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7545                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7546 }
7547
7548 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7549                                          enum transcoder transcoder,
7550                                          struct intel_link_m_n *m_n,
7551                                          struct intel_link_m_n *m2_n2)
7552 {
7553         struct drm_device *dev = crtc->base.dev;
7554         struct drm_i915_private *dev_priv = dev->dev_private;
7555         enum pipe pipe = crtc->pipe;
7556
7557         if (INTEL_INFO(dev)->gen >= 5) {
7558                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7559                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7560                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7561                         & ~TU_SIZE_MASK;
7562                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7563                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7564                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7565                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7566                  * gen < 8) and if DRRS is supported (to make sure the
7567                  * registers are not unnecessarily read).
7568                  */
7569                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7570                         crtc->config->has_drrs) {
7571                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7572                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7573                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7574                                         & ~TU_SIZE_MASK;
7575                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7576                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7577                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7578                 }
7579         } else {
7580                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7581                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7582                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7583                         & ~TU_SIZE_MASK;
7584                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7585                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7586                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7587         }
7588 }
7589
7590 void intel_dp_get_m_n(struct intel_crtc *crtc,
7591                       struct intel_crtc_state *pipe_config)
7592 {
7593         if (pipe_config->has_pch_encoder)
7594                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7595         else
7596                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7597                                              &pipe_config->dp_m_n,
7598                                              &pipe_config->dp_m2_n2);
7599 }
7600
7601 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7602                                         struct intel_crtc_state *pipe_config)
7603 {
7604         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7605                                      &pipe_config->fdi_m_n, NULL);
7606 }
7607
7608 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7609                                     struct intel_crtc_state *pipe_config)
7610 {
7611         struct drm_device *dev = crtc->base.dev;
7612         struct drm_i915_private *dev_priv = dev->dev_private;
7613         uint32_t tmp;
7614
7615         tmp = I915_READ(PS_CTL(crtc->pipe));
7616
7617         if (tmp & PS_ENABLE) {
7618                 pipe_config->pch_pfit.enabled = true;
7619                 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7620                 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7621         }
7622 }
7623
7624 static void
7625 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7626                                  struct intel_initial_plane_config *plane_config)
7627 {
7628         struct drm_device *dev = crtc->base.dev;
7629         struct drm_i915_private *dev_priv = dev->dev_private;
7630         u32 val, base, offset, stride_mult;
7631         int pipe = crtc->pipe;
7632         int fourcc, pixel_format;
7633         int aligned_height;
7634         struct drm_framebuffer *fb;
7635         struct intel_framebuffer *intel_fb;
7636
7637         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7638         if (!intel_fb) {
7639                 DRM_DEBUG_KMS("failed to alloc fb\n");
7640                 return;
7641         }
7642
7643         fb = &intel_fb->base;
7644
7645         val = I915_READ(PLANE_CTL(pipe, 0));
7646         if (val & PLANE_CTL_TILED_MASK)
7647                 plane_config->tiling = I915_TILING_X;
7648
7649         pixel_format = val & PLANE_CTL_FORMAT_MASK;
7650         fourcc = skl_format_to_fourcc(pixel_format,
7651                                       val & PLANE_CTL_ORDER_RGBX,
7652                                       val & PLANE_CTL_ALPHA_MASK);
7653         fb->pixel_format = fourcc;
7654         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7655
7656         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7657         plane_config->base = base;
7658
7659         offset = I915_READ(PLANE_OFFSET(pipe, 0));
7660
7661         val = I915_READ(PLANE_SIZE(pipe, 0));
7662         fb->height = ((val >> 16) & 0xfff) + 1;
7663         fb->width = ((val >> 0) & 0x1fff) + 1;
7664
7665         val = I915_READ(PLANE_STRIDE(pipe, 0));
7666         switch (plane_config->tiling) {
7667         case I915_TILING_NONE:
7668                 stride_mult = 64;
7669                 break;
7670         case I915_TILING_X:
7671                 stride_mult = 512;
7672                 break;
7673         default:
7674                 MISSING_CASE(plane_config->tiling);
7675                 goto error;
7676         }
7677         fb->pitches[0] = (val & 0x3ff) * stride_mult;
7678
7679         aligned_height = intel_fb_align_height(dev, fb->height,
7680                                                plane_config->tiling);
7681
7682         plane_config->size = fb->pitches[0] * aligned_height;
7683
7684         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7685                       pipe_name(pipe), fb->width, fb->height,
7686                       fb->bits_per_pixel, base, fb->pitches[0],
7687                       plane_config->size);
7688
7689         crtc->base.primary->fb = fb;
7690         return;
7691
7692 error:
7693         kfree(fb);
7694 }
7695
7696 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7697                                      struct intel_crtc_state *pipe_config)
7698 {
7699         struct drm_device *dev = crtc->base.dev;
7700         struct drm_i915_private *dev_priv = dev->dev_private;
7701         uint32_t tmp;
7702
7703         tmp = I915_READ(PF_CTL(crtc->pipe));
7704
7705         if (tmp & PF_ENABLE) {
7706                 pipe_config->pch_pfit.enabled = true;
7707                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7708                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7709
7710                 /* We currently do not free assignements of panel fitters on
7711                  * ivb/hsw (since we don't use the higher upscaling modes which
7712                  * differentiates them) so just WARN about this case for now. */
7713                 if (IS_GEN7(dev)) {
7714                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7715                                 PF_PIPE_SEL_IVB(crtc->pipe));
7716                 }
7717         }
7718 }
7719
7720 static void
7721 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7722                                   struct intel_initial_plane_config *plane_config)
7723 {
7724         struct drm_device *dev = crtc->base.dev;
7725         struct drm_i915_private *dev_priv = dev->dev_private;
7726         u32 val, base, offset;
7727         int pipe = crtc->pipe;
7728         int fourcc, pixel_format;
7729         int aligned_height;
7730         struct drm_framebuffer *fb;
7731         struct intel_framebuffer *intel_fb;
7732
7733         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7734         if (!intel_fb) {
7735                 DRM_DEBUG_KMS("failed to alloc fb\n");
7736                 return;
7737         }
7738
7739         fb = &intel_fb->base;
7740
7741         val = I915_READ(DSPCNTR(pipe));
7742
7743         if (INTEL_INFO(dev)->gen >= 4)
7744                 if (val & DISPPLANE_TILED)
7745                         plane_config->tiling = I915_TILING_X;
7746
7747         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7748         fourcc = i9xx_format_to_fourcc(pixel_format);
7749         fb->pixel_format = fourcc;
7750         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7751
7752         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7753         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7754                 offset = I915_READ(DSPOFFSET(pipe));
7755         } else {
7756                 if (plane_config->tiling)
7757                         offset = I915_READ(DSPTILEOFF(pipe));
7758                 else
7759                         offset = I915_READ(DSPLINOFF(pipe));
7760         }
7761         plane_config->base = base;
7762
7763         val = I915_READ(PIPESRC(pipe));
7764         fb->width = ((val >> 16) & 0xfff) + 1;
7765         fb->height = ((val >> 0) & 0xfff) + 1;
7766
7767         val = I915_READ(DSPSTRIDE(pipe));
7768         fb->pitches[0] = val & 0xffffffc0;
7769
7770         aligned_height = intel_fb_align_height(dev, fb->height,
7771                                                plane_config->tiling);
7772
7773         plane_config->size = fb->pitches[0] * aligned_height;
7774
7775         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7776                       pipe_name(pipe), fb->width, fb->height,
7777                       fb->bits_per_pixel, base, fb->pitches[0],
7778                       plane_config->size);
7779
7780         crtc->base.primary->fb = fb;
7781 }
7782
7783 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7784                                      struct intel_crtc_state *pipe_config)
7785 {
7786         struct drm_device *dev = crtc->base.dev;
7787         struct drm_i915_private *dev_priv = dev->dev_private;
7788         uint32_t tmp;
7789
7790         if (!intel_display_power_is_enabled(dev_priv,
7791                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7792                 return false;
7793
7794         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7795         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7796
7797         tmp = I915_READ(PIPECONF(crtc->pipe));
7798         if (!(tmp & PIPECONF_ENABLE))
7799                 return false;
7800
7801         switch (tmp & PIPECONF_BPC_MASK) {
7802         case PIPECONF_6BPC:
7803                 pipe_config->pipe_bpp = 18;
7804                 break;
7805         case PIPECONF_8BPC:
7806                 pipe_config->pipe_bpp = 24;
7807                 break;
7808         case PIPECONF_10BPC:
7809                 pipe_config->pipe_bpp = 30;
7810                 break;
7811         case PIPECONF_12BPC:
7812                 pipe_config->pipe_bpp = 36;
7813                 break;
7814         default:
7815                 break;
7816         }
7817
7818         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7819                 pipe_config->limited_color_range = true;
7820
7821         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7822                 struct intel_shared_dpll *pll;
7823
7824                 pipe_config->has_pch_encoder = true;
7825
7826                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7827                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7828                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7829
7830                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7831
7832                 if (HAS_PCH_IBX(dev_priv->dev)) {
7833                         pipe_config->shared_dpll =
7834                                 (enum intel_dpll_id) crtc->pipe;
7835                 } else {
7836                         tmp = I915_READ(PCH_DPLL_SEL);
7837                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7838                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7839                         else
7840                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7841                 }
7842
7843                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7844
7845                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7846                                            &pipe_config->dpll_hw_state));
7847
7848                 tmp = pipe_config->dpll_hw_state.dpll;
7849                 pipe_config->pixel_multiplier =
7850                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7851                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7852
7853                 ironlake_pch_clock_get(crtc, pipe_config);
7854         } else {
7855                 pipe_config->pixel_multiplier = 1;
7856         }
7857
7858         intel_get_pipe_timings(crtc, pipe_config);
7859
7860         ironlake_get_pfit_config(crtc, pipe_config);
7861
7862         return true;
7863 }
7864
7865 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7866 {
7867         struct drm_device *dev = dev_priv->dev;
7868         struct intel_crtc *crtc;
7869
7870         for_each_intel_crtc(dev, crtc)
7871                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
7872                      pipe_name(crtc->pipe));
7873
7874         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7875         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7876         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7877         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7878         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7879         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7880              "CPU PWM1 enabled\n");
7881         if (IS_HASWELL(dev))
7882                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7883                      "CPU PWM2 enabled\n");
7884         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7885              "PCH PWM1 enabled\n");
7886         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7887              "Utility pin enabled\n");
7888         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7889
7890         /*
7891          * In theory we can still leave IRQs enabled, as long as only the HPD
7892          * interrupts remain enabled. We used to check for that, but since it's
7893          * gen-specific and since we only disable LCPLL after we fully disable
7894          * the interrupts, the check below should be enough.
7895          */
7896         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7897 }
7898
7899 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7900 {
7901         struct drm_device *dev = dev_priv->dev;
7902
7903         if (IS_HASWELL(dev))
7904                 return I915_READ(D_COMP_HSW);
7905         else
7906                 return I915_READ(D_COMP_BDW);
7907 }
7908
7909 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7910 {
7911         struct drm_device *dev = dev_priv->dev;
7912
7913         if (IS_HASWELL(dev)) {
7914                 mutex_lock(&dev_priv->rps.hw_lock);
7915                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7916                                             val))
7917                         DRM_ERROR("Failed to write to D_COMP\n");
7918                 mutex_unlock(&dev_priv->rps.hw_lock);
7919         } else {
7920                 I915_WRITE(D_COMP_BDW, val);
7921                 POSTING_READ(D_COMP_BDW);
7922         }
7923 }
7924
7925 /*
7926  * This function implements pieces of two sequences from BSpec:
7927  * - Sequence for display software to disable LCPLL
7928  * - Sequence for display software to allow package C8+
7929  * The steps implemented here are just the steps that actually touch the LCPLL
7930  * register. Callers should take care of disabling all the display engine
7931  * functions, doing the mode unset, fixing interrupts, etc.
7932  */
7933 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7934                               bool switch_to_fclk, bool allow_power_down)
7935 {
7936         uint32_t val;
7937
7938         assert_can_disable_lcpll(dev_priv);
7939
7940         val = I915_READ(LCPLL_CTL);
7941
7942         if (switch_to_fclk) {
7943                 val |= LCPLL_CD_SOURCE_FCLK;
7944                 I915_WRITE(LCPLL_CTL, val);
7945
7946                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7947                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7948                         DRM_ERROR("Switching to FCLK failed\n");
7949
7950                 val = I915_READ(LCPLL_CTL);
7951         }
7952
7953         val |= LCPLL_PLL_DISABLE;
7954         I915_WRITE(LCPLL_CTL, val);
7955         POSTING_READ(LCPLL_CTL);
7956
7957         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7958                 DRM_ERROR("LCPLL still locked\n");
7959
7960         val = hsw_read_dcomp(dev_priv);
7961         val |= D_COMP_COMP_DISABLE;
7962         hsw_write_dcomp(dev_priv, val);
7963         ndelay(100);
7964
7965         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7966                      1))
7967                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7968
7969         if (allow_power_down) {
7970                 val = I915_READ(LCPLL_CTL);
7971                 val |= LCPLL_POWER_DOWN_ALLOW;
7972                 I915_WRITE(LCPLL_CTL, val);
7973                 POSTING_READ(LCPLL_CTL);
7974         }
7975 }
7976
7977 /*
7978  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7979  * source.
7980  */
7981 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7982 {
7983         uint32_t val;
7984
7985         val = I915_READ(LCPLL_CTL);
7986
7987         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7988                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7989                 return;
7990
7991         /*
7992          * Make sure we're not on PC8 state before disabling PC8, otherwise
7993          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7994          */
7995         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7996
7997         if (val & LCPLL_POWER_DOWN_ALLOW) {
7998                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7999                 I915_WRITE(LCPLL_CTL, val);
8000                 POSTING_READ(LCPLL_CTL);
8001         }
8002
8003         val = hsw_read_dcomp(dev_priv);
8004         val |= D_COMP_COMP_FORCE;
8005         val &= ~D_COMP_COMP_DISABLE;
8006         hsw_write_dcomp(dev_priv, val);
8007
8008         val = I915_READ(LCPLL_CTL);
8009         val &= ~LCPLL_PLL_DISABLE;
8010         I915_WRITE(LCPLL_CTL, val);
8011
8012         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8013                 DRM_ERROR("LCPLL not locked yet\n");
8014
8015         if (val & LCPLL_CD_SOURCE_FCLK) {
8016                 val = I915_READ(LCPLL_CTL);
8017                 val &= ~LCPLL_CD_SOURCE_FCLK;
8018                 I915_WRITE(LCPLL_CTL, val);
8019
8020                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8021                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8022                         DRM_ERROR("Switching back to LCPLL failed\n");
8023         }
8024
8025         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8026 }
8027
8028 /*
8029  * Package states C8 and deeper are really deep PC states that can only be
8030  * reached when all the devices on the system allow it, so even if the graphics
8031  * device allows PC8+, it doesn't mean the system will actually get to these
8032  * states. Our driver only allows PC8+ when going into runtime PM.
8033  *
8034  * The requirements for PC8+ are that all the outputs are disabled, the power
8035  * well is disabled and most interrupts are disabled, and these are also
8036  * requirements for runtime PM. When these conditions are met, we manually do
8037  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8038  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8039  * hang the machine.
8040  *
8041  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8042  * the state of some registers, so when we come back from PC8+ we need to
8043  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8044  * need to take care of the registers kept by RC6. Notice that this happens even
8045  * if we don't put the device in PCI D3 state (which is what currently happens
8046  * because of the runtime PM support).
8047  *
8048  * For more, read "Display Sequences for Package C8" on the hardware
8049  * documentation.
8050  */
8051 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8052 {
8053         struct drm_device *dev = dev_priv->dev;
8054         uint32_t val;
8055
8056         DRM_DEBUG_KMS("Enabling package C8+\n");
8057
8058         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8059                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8060                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8061                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8062         }
8063
8064         lpt_disable_clkout_dp(dev);
8065         hsw_disable_lcpll(dev_priv, true, true);
8066 }
8067
8068 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8069 {
8070         struct drm_device *dev = dev_priv->dev;
8071         uint32_t val;
8072
8073         DRM_DEBUG_KMS("Disabling package C8+\n");
8074
8075         hsw_restore_lcpll(dev_priv);
8076         lpt_init_pch_refclk(dev);
8077
8078         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8079                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8080                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8081                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8082         }
8083
8084         intel_prepare_ddi(dev);
8085 }
8086
8087 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8088                                       struct intel_crtc_state *crtc_state)
8089 {
8090         if (!intel_ddi_pll_select(crtc, crtc_state))
8091                 return -EINVAL;
8092
8093         crtc->lowfreq_avail = false;
8094
8095         return 0;
8096 }
8097
8098 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8099                                 enum port port,
8100                                 struct intel_crtc_state *pipe_config)
8101 {
8102         u32 temp, dpll_ctl1;
8103
8104         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8105         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8106
8107         switch (pipe_config->ddi_pll_sel) {
8108         case SKL_DPLL0:
8109                 /*
8110                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8111                  * of the shared DPLL framework and thus needs to be read out
8112                  * separately
8113                  */
8114                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8115                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8116                 break;
8117         case SKL_DPLL1:
8118                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8119                 break;
8120         case SKL_DPLL2:
8121                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8122                 break;
8123         case SKL_DPLL3:
8124                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8125                 break;
8126         }
8127 }
8128
8129 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8130                                 enum port port,
8131                                 struct intel_crtc_state *pipe_config)
8132 {
8133         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8134
8135         switch (pipe_config->ddi_pll_sel) {
8136         case PORT_CLK_SEL_WRPLL1:
8137                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8138                 break;
8139         case PORT_CLK_SEL_WRPLL2:
8140                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8141                 break;
8142         }
8143 }
8144
8145 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8146                                        struct intel_crtc_state *pipe_config)
8147 {
8148         struct drm_device *dev = crtc->base.dev;
8149         struct drm_i915_private *dev_priv = dev->dev_private;
8150         struct intel_shared_dpll *pll;
8151         enum port port;
8152         uint32_t tmp;
8153
8154         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8155
8156         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8157
8158         if (IS_SKYLAKE(dev))
8159                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8160         else
8161                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8162
8163         if (pipe_config->shared_dpll >= 0) {
8164                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8165
8166                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8167                                            &pipe_config->dpll_hw_state));
8168         }
8169
8170         /*
8171          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8172          * DDI E. So just check whether this pipe is wired to DDI E and whether
8173          * the PCH transcoder is on.
8174          */
8175         if (INTEL_INFO(dev)->gen < 9 &&
8176             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8177                 pipe_config->has_pch_encoder = true;
8178
8179                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8180                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8181                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8182
8183                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8184         }
8185 }
8186
8187 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8188                                     struct intel_crtc_state *pipe_config)
8189 {
8190         struct drm_device *dev = crtc->base.dev;
8191         struct drm_i915_private *dev_priv = dev->dev_private;
8192         enum intel_display_power_domain pfit_domain;
8193         uint32_t tmp;
8194
8195         if (!intel_display_power_is_enabled(dev_priv,
8196                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8197                 return false;
8198
8199         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8200         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8201
8202         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8203         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8204                 enum pipe trans_edp_pipe;
8205                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8206                 default:
8207                         WARN(1, "unknown pipe linked to edp transcoder\n");
8208                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8209                 case TRANS_DDI_EDP_INPUT_A_ON:
8210                         trans_edp_pipe = PIPE_A;
8211                         break;
8212                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8213                         trans_edp_pipe = PIPE_B;
8214                         break;
8215                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8216                         trans_edp_pipe = PIPE_C;
8217                         break;
8218                 }
8219
8220                 if (trans_edp_pipe == crtc->pipe)
8221                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8222         }
8223
8224         if (!intel_display_power_is_enabled(dev_priv,
8225                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8226                 return false;
8227
8228         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8229         if (!(tmp & PIPECONF_ENABLE))
8230                 return false;
8231
8232         haswell_get_ddi_port_state(crtc, pipe_config);
8233
8234         intel_get_pipe_timings(crtc, pipe_config);
8235
8236         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8237         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8238                 if (IS_SKYLAKE(dev))
8239                         skylake_get_pfit_config(crtc, pipe_config);
8240                 else
8241                         ironlake_get_pfit_config(crtc, pipe_config);
8242         }
8243
8244         if (IS_HASWELL(dev))
8245                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8246                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8247
8248         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8249                 pipe_config->pixel_multiplier =
8250                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8251         } else {
8252                 pipe_config->pixel_multiplier = 1;
8253         }
8254
8255         return true;
8256 }
8257
8258 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8259 {
8260         struct drm_device *dev = crtc->dev;
8261         struct drm_i915_private *dev_priv = dev->dev_private;
8262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8263         uint32_t cntl = 0, size = 0;
8264
8265         if (base) {
8266                 unsigned int width = intel_crtc->cursor_width;
8267                 unsigned int height = intel_crtc->cursor_height;
8268                 unsigned int stride = roundup_pow_of_two(width) * 4;
8269
8270                 switch (stride) {
8271                 default:
8272                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8273                                   width, stride);
8274                         stride = 256;
8275                         /* fallthrough */
8276                 case 256:
8277                 case 512:
8278                 case 1024:
8279                 case 2048:
8280                         break;
8281                 }
8282
8283                 cntl |= CURSOR_ENABLE |
8284                         CURSOR_GAMMA_ENABLE |
8285                         CURSOR_FORMAT_ARGB |
8286                         CURSOR_STRIDE(stride);
8287
8288                 size = (height << 12) | width;
8289         }
8290
8291         if (intel_crtc->cursor_cntl != 0 &&
8292             (intel_crtc->cursor_base != base ||
8293              intel_crtc->cursor_size != size ||
8294              intel_crtc->cursor_cntl != cntl)) {
8295                 /* On these chipsets we can only modify the base/size/stride
8296                  * whilst the cursor is disabled.
8297                  */
8298                 I915_WRITE(_CURACNTR, 0);
8299                 POSTING_READ(_CURACNTR);
8300                 intel_crtc->cursor_cntl = 0;
8301         }
8302
8303         if (intel_crtc->cursor_base != base) {
8304                 I915_WRITE(_CURABASE, base);
8305                 intel_crtc->cursor_base = base;
8306         }
8307
8308         if (intel_crtc->cursor_size != size) {
8309                 I915_WRITE(CURSIZE, size);
8310                 intel_crtc->cursor_size = size;
8311         }
8312
8313         if (intel_crtc->cursor_cntl != cntl) {
8314                 I915_WRITE(_CURACNTR, cntl);
8315                 POSTING_READ(_CURACNTR);
8316                 intel_crtc->cursor_cntl = cntl;
8317         }
8318 }
8319
8320 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8321 {
8322         struct drm_device *dev = crtc->dev;
8323         struct drm_i915_private *dev_priv = dev->dev_private;
8324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8325         int pipe = intel_crtc->pipe;
8326         uint32_t cntl;
8327
8328         cntl = 0;
8329         if (base) {
8330                 cntl = MCURSOR_GAMMA_ENABLE;
8331                 switch (intel_crtc->cursor_width) {
8332                         case 64:
8333                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8334                                 break;
8335                         case 128:
8336                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8337                                 break;
8338                         case 256:
8339                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8340                                 break;
8341                         default:
8342                                 MISSING_CASE(intel_crtc->cursor_width);
8343                                 return;
8344                 }
8345                 cntl |= pipe << 28; /* Connect to correct pipe */
8346
8347                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8348                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8349         }
8350
8351         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8352                 cntl |= CURSOR_ROTATE_180;
8353
8354         if (intel_crtc->cursor_cntl != cntl) {
8355                 I915_WRITE(CURCNTR(pipe), cntl);
8356                 POSTING_READ(CURCNTR(pipe));
8357                 intel_crtc->cursor_cntl = cntl;
8358         }
8359
8360         /* and commit changes on next vblank */
8361         I915_WRITE(CURBASE(pipe), base);
8362         POSTING_READ(CURBASE(pipe));
8363
8364         intel_crtc->cursor_base = base;
8365 }
8366
8367 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8368 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8369                                      bool on)
8370 {
8371         struct drm_device *dev = crtc->dev;
8372         struct drm_i915_private *dev_priv = dev->dev_private;
8373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8374         int pipe = intel_crtc->pipe;
8375         int x = crtc->cursor_x;
8376         int y = crtc->cursor_y;
8377         u32 base = 0, pos = 0;
8378
8379         if (on)
8380                 base = intel_crtc->cursor_addr;
8381
8382         if (x >= intel_crtc->config->pipe_src_w)
8383                 base = 0;
8384
8385         if (y >= intel_crtc->config->pipe_src_h)
8386                 base = 0;
8387
8388         if (x < 0) {
8389                 if (x + intel_crtc->cursor_width <= 0)
8390                         base = 0;
8391
8392                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8393                 x = -x;
8394         }
8395         pos |= x << CURSOR_X_SHIFT;
8396
8397         if (y < 0) {
8398                 if (y + intel_crtc->cursor_height <= 0)
8399                         base = 0;
8400
8401                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8402                 y = -y;
8403         }
8404         pos |= y << CURSOR_Y_SHIFT;
8405
8406         if (base == 0 && intel_crtc->cursor_base == 0)
8407                 return;
8408
8409         I915_WRITE(CURPOS(pipe), pos);
8410
8411         /* ILK+ do this automagically */
8412         if (HAS_GMCH_DISPLAY(dev) &&
8413             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8414                 base += (intel_crtc->cursor_height *
8415                         intel_crtc->cursor_width - 1) * 4;
8416         }
8417
8418         if (IS_845G(dev) || IS_I865G(dev))
8419                 i845_update_cursor(crtc, base);
8420         else
8421                 i9xx_update_cursor(crtc, base);
8422 }
8423
8424 static bool cursor_size_ok(struct drm_device *dev,
8425                            uint32_t width, uint32_t height)
8426 {
8427         if (width == 0 || height == 0)
8428                 return false;
8429
8430         /*
8431          * 845g/865g are special in that they are only limited by
8432          * the width of their cursors, the height is arbitrary up to
8433          * the precision of the register. Everything else requires
8434          * square cursors, limited to a few power-of-two sizes.
8435          */
8436         if (IS_845G(dev) || IS_I865G(dev)) {
8437                 if ((width & 63) != 0)
8438                         return false;
8439
8440                 if (width > (IS_845G(dev) ? 64 : 512))
8441                         return false;
8442
8443                 if (height > 1023)
8444                         return false;
8445         } else {
8446                 switch (width | height) {
8447                 case 256:
8448                 case 128:
8449                         if (IS_GEN2(dev))
8450                                 return false;
8451                 case 64:
8452                         break;
8453                 default:
8454                         return false;
8455                 }
8456         }
8457
8458         return true;
8459 }
8460
8461 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8462                                  u16 *blue, uint32_t start, uint32_t size)
8463 {
8464         int end = (start + size > 256) ? 256 : start + size, i;
8465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8466
8467         for (i = start; i < end; i++) {
8468                 intel_crtc->lut_r[i] = red[i] >> 8;
8469                 intel_crtc->lut_g[i] = green[i] >> 8;
8470                 intel_crtc->lut_b[i] = blue[i] >> 8;
8471         }
8472
8473         intel_crtc_load_lut(crtc);
8474 }
8475
8476 /* VESA 640x480x72Hz mode to set on the pipe */
8477 static struct drm_display_mode load_detect_mode = {
8478         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8479                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8480 };
8481
8482 struct drm_framebuffer *
8483 __intel_framebuffer_create(struct drm_device *dev,
8484                            struct drm_mode_fb_cmd2 *mode_cmd,
8485                            struct drm_i915_gem_object *obj)
8486 {
8487         struct intel_framebuffer *intel_fb;
8488         int ret;
8489
8490         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8491         if (!intel_fb) {
8492                 drm_gem_object_unreference(&obj->base);
8493                 return ERR_PTR(-ENOMEM);
8494         }
8495
8496         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8497         if (ret)
8498                 goto err;
8499
8500         return &intel_fb->base;
8501 err:
8502         drm_gem_object_unreference(&obj->base);
8503         kfree(intel_fb);
8504
8505         return ERR_PTR(ret);
8506 }
8507
8508 static struct drm_framebuffer *
8509 intel_framebuffer_create(struct drm_device *dev,
8510                          struct drm_mode_fb_cmd2 *mode_cmd,
8511                          struct drm_i915_gem_object *obj)
8512 {
8513         struct drm_framebuffer *fb;
8514         int ret;
8515
8516         ret = i915_mutex_lock_interruptible(dev);
8517         if (ret)
8518                 return ERR_PTR(ret);
8519         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8520         mutex_unlock(&dev->struct_mutex);
8521
8522         return fb;
8523 }
8524
8525 static u32
8526 intel_framebuffer_pitch_for_width(int width, int bpp)
8527 {
8528         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8529         return ALIGN(pitch, 64);
8530 }
8531
8532 static u32
8533 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8534 {
8535         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8536         return PAGE_ALIGN(pitch * mode->vdisplay);
8537 }
8538
8539 static struct drm_framebuffer *
8540 intel_framebuffer_create_for_mode(struct drm_device *dev,
8541                                   struct drm_display_mode *mode,
8542                                   int depth, int bpp)
8543 {
8544         struct drm_i915_gem_object *obj;
8545         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8546
8547         obj = i915_gem_alloc_object(dev,
8548                                     intel_framebuffer_size_for_mode(mode, bpp));
8549         if (obj == NULL)
8550                 return ERR_PTR(-ENOMEM);
8551
8552         mode_cmd.width = mode->hdisplay;
8553         mode_cmd.height = mode->vdisplay;
8554         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8555                                                                 bpp);
8556         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8557
8558         return intel_framebuffer_create(dev, &mode_cmd, obj);
8559 }
8560
8561 static struct drm_framebuffer *
8562 mode_fits_in_fbdev(struct drm_device *dev,
8563                    struct drm_display_mode *mode)
8564 {
8565 #ifdef CONFIG_DRM_I915_FBDEV
8566         struct drm_i915_private *dev_priv = dev->dev_private;
8567         struct drm_i915_gem_object *obj;
8568         struct drm_framebuffer *fb;
8569
8570         if (!dev_priv->fbdev)
8571                 return NULL;
8572
8573         if (!dev_priv->fbdev->fb)
8574                 return NULL;
8575
8576         obj = dev_priv->fbdev->fb->obj;
8577         BUG_ON(!obj);
8578
8579         fb = &dev_priv->fbdev->fb->base;
8580         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8581                                                                fb->bits_per_pixel))
8582                 return NULL;
8583
8584         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8585                 return NULL;
8586
8587         return fb;
8588 #else
8589         return NULL;
8590 #endif
8591 }
8592
8593 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8594                                 struct drm_display_mode *mode,
8595                                 struct intel_load_detect_pipe *old,
8596                                 struct drm_modeset_acquire_ctx *ctx)
8597 {
8598         struct intel_crtc *intel_crtc;
8599         struct intel_encoder *intel_encoder =
8600                 intel_attached_encoder(connector);
8601         struct drm_crtc *possible_crtc;
8602         struct drm_encoder *encoder = &intel_encoder->base;
8603         struct drm_crtc *crtc = NULL;
8604         struct drm_device *dev = encoder->dev;
8605         struct drm_framebuffer *fb;
8606         struct drm_mode_config *config = &dev->mode_config;
8607         int ret, i = -1;
8608
8609         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8610                       connector->base.id, connector->name,
8611                       encoder->base.id, encoder->name);
8612
8613 retry:
8614         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8615         if (ret)
8616                 goto fail_unlock;
8617
8618         /*
8619          * Algorithm gets a little messy:
8620          *
8621          *   - if the connector already has an assigned crtc, use it (but make
8622          *     sure it's on first)
8623          *
8624          *   - try to find the first unused crtc that can drive this connector,
8625          *     and use that if we find one
8626          */
8627
8628         /* See if we already have a CRTC for this connector */
8629         if (encoder->crtc) {
8630                 crtc = encoder->crtc;
8631
8632                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8633                 if (ret)
8634                         goto fail_unlock;
8635                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8636                 if (ret)
8637                         goto fail_unlock;
8638
8639                 old->dpms_mode = connector->dpms;
8640                 old->load_detect_temp = false;
8641
8642                 /* Make sure the crtc and connector are running */
8643                 if (connector->dpms != DRM_MODE_DPMS_ON)
8644                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8645
8646                 return true;
8647         }
8648
8649         /* Find an unused one (if possible) */
8650         for_each_crtc(dev, possible_crtc) {
8651                 i++;
8652                 if (!(encoder->possible_crtcs & (1 << i)))
8653                         continue;
8654                 if (possible_crtc->enabled)
8655                         continue;
8656                 /* This can occur when applying the pipe A quirk on resume. */
8657                 if (to_intel_crtc(possible_crtc)->new_enabled)
8658                         continue;
8659
8660                 crtc = possible_crtc;
8661                 break;
8662         }
8663
8664         /*
8665          * If we didn't find an unused CRTC, don't use any.
8666          */
8667         if (!crtc) {
8668                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8669                 goto fail_unlock;
8670         }
8671
8672         ret = drm_modeset_lock(&crtc->mutex, ctx);
8673         if (ret)
8674                 goto fail_unlock;
8675         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8676         if (ret)
8677                 goto fail_unlock;
8678         intel_encoder->new_crtc = to_intel_crtc(crtc);
8679         to_intel_connector(connector)->new_encoder = intel_encoder;
8680
8681         intel_crtc = to_intel_crtc(crtc);
8682         intel_crtc->new_enabled = true;
8683         intel_crtc->new_config = intel_crtc->config;
8684         old->dpms_mode = connector->dpms;
8685         old->load_detect_temp = true;
8686         old->release_fb = NULL;
8687
8688         if (!mode)
8689                 mode = &load_detect_mode;
8690
8691         /* We need a framebuffer large enough to accommodate all accesses
8692          * that the plane may generate whilst we perform load detection.
8693          * We can not rely on the fbcon either being present (we get called
8694          * during its initialisation to detect all boot displays, or it may
8695          * not even exist) or that it is large enough to satisfy the
8696          * requested mode.
8697          */
8698         fb = mode_fits_in_fbdev(dev, mode);
8699         if (fb == NULL) {
8700                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8701                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8702                 old->release_fb = fb;
8703         } else
8704                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8705         if (IS_ERR(fb)) {
8706                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8707                 goto fail;
8708         }
8709
8710         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8711                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8712                 if (old->release_fb)
8713                         old->release_fb->funcs->destroy(old->release_fb);
8714                 goto fail;
8715         }
8716         crtc->primary->crtc = crtc;
8717
8718         /* let the connector get through one full cycle before testing */
8719         intel_wait_for_vblank(dev, intel_crtc->pipe);
8720         return true;
8721
8722  fail:
8723         intel_crtc->new_enabled = crtc->enabled;
8724         if (intel_crtc->new_enabled)
8725                 intel_crtc->new_config = intel_crtc->config;
8726         else
8727                 intel_crtc->new_config = NULL;
8728 fail_unlock:
8729         if (ret == -EDEADLK) {
8730                 drm_modeset_backoff(ctx);
8731                 goto retry;
8732         }
8733
8734         return false;
8735 }
8736
8737 void intel_release_load_detect_pipe(struct drm_connector *connector,
8738                                     struct intel_load_detect_pipe *old)
8739 {
8740         struct intel_encoder *intel_encoder =
8741                 intel_attached_encoder(connector);
8742         struct drm_encoder *encoder = &intel_encoder->base;
8743         struct drm_crtc *crtc = encoder->crtc;
8744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8745
8746         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8747                       connector->base.id, connector->name,
8748                       encoder->base.id, encoder->name);
8749
8750         if (old->load_detect_temp) {
8751                 to_intel_connector(connector)->new_encoder = NULL;
8752                 intel_encoder->new_crtc = NULL;
8753                 intel_crtc->new_enabled = false;
8754                 intel_crtc->new_config = NULL;
8755                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8756
8757                 if (old->release_fb) {
8758                         drm_framebuffer_unregister_private(old->release_fb);
8759                         drm_framebuffer_unreference(old->release_fb);
8760                 }
8761
8762                 return;
8763         }
8764
8765         /* Switch crtc and encoder back off if necessary */
8766         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8767                 connector->funcs->dpms(connector, old->dpms_mode);
8768 }
8769
8770 static int i9xx_pll_refclk(struct drm_device *dev,
8771                            const struct intel_crtc_state *pipe_config)
8772 {
8773         struct drm_i915_private *dev_priv = dev->dev_private;
8774         u32 dpll = pipe_config->dpll_hw_state.dpll;
8775
8776         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8777                 return dev_priv->vbt.lvds_ssc_freq;
8778         else if (HAS_PCH_SPLIT(dev))
8779                 return 120000;
8780         else if (!IS_GEN2(dev))
8781                 return 96000;
8782         else
8783                 return 48000;
8784 }
8785
8786 /* Returns the clock of the currently programmed mode of the given pipe. */
8787 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8788                                 struct intel_crtc_state *pipe_config)
8789 {
8790         struct drm_device *dev = crtc->base.dev;
8791         struct drm_i915_private *dev_priv = dev->dev_private;
8792         int pipe = pipe_config->cpu_transcoder;
8793         u32 dpll = pipe_config->dpll_hw_state.dpll;
8794         u32 fp;
8795         intel_clock_t clock;
8796         int refclk = i9xx_pll_refclk(dev, pipe_config);
8797
8798         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8799                 fp = pipe_config->dpll_hw_state.fp0;
8800         else
8801                 fp = pipe_config->dpll_hw_state.fp1;
8802
8803         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8804         if (IS_PINEVIEW(dev)) {
8805                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8806                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8807         } else {
8808                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8809                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8810         }
8811
8812         if (!IS_GEN2(dev)) {
8813                 if (IS_PINEVIEW(dev))
8814                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8815                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8816                 else
8817                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8818                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8819
8820                 switch (dpll & DPLL_MODE_MASK) {
8821                 case DPLLB_MODE_DAC_SERIAL:
8822                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8823                                 5 : 10;
8824                         break;
8825                 case DPLLB_MODE_LVDS:
8826                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8827                                 7 : 14;
8828                         break;
8829                 default:
8830                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8831                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8832                         return;
8833                 }
8834
8835                 if (IS_PINEVIEW(dev))
8836                         pineview_clock(refclk, &clock);
8837                 else
8838                         i9xx_clock(refclk, &clock);
8839         } else {
8840                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8841                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8842
8843                 if (is_lvds) {
8844                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8845                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8846
8847                         if (lvds & LVDS_CLKB_POWER_UP)
8848                                 clock.p2 = 7;
8849                         else
8850                                 clock.p2 = 14;
8851                 } else {
8852                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8853                                 clock.p1 = 2;
8854                         else {
8855                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8856                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8857                         }
8858                         if (dpll & PLL_P2_DIVIDE_BY_4)
8859                                 clock.p2 = 4;
8860                         else
8861                                 clock.p2 = 2;
8862                 }
8863
8864                 i9xx_clock(refclk, &clock);
8865         }
8866
8867         /*
8868          * This value includes pixel_multiplier. We will use
8869          * port_clock to compute adjusted_mode.crtc_clock in the
8870          * encoder's get_config() function.
8871          */
8872         pipe_config->port_clock = clock.dot;
8873 }
8874
8875 int intel_dotclock_calculate(int link_freq,
8876                              const struct intel_link_m_n *m_n)
8877 {
8878         /*
8879          * The calculation for the data clock is:
8880          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8881          * But we want to avoid losing precison if possible, so:
8882          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8883          *
8884          * and the link clock is simpler:
8885          * link_clock = (m * link_clock) / n
8886          */
8887
8888         if (!m_n->link_n)
8889                 return 0;
8890
8891         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8892 }
8893
8894 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8895                                    struct intel_crtc_state *pipe_config)
8896 {
8897         struct drm_device *dev = crtc->base.dev;
8898
8899         /* read out port_clock from the DPLL */
8900         i9xx_crtc_clock_get(crtc, pipe_config);
8901
8902         /*
8903          * This value does not include pixel_multiplier.
8904          * We will check that port_clock and adjusted_mode.crtc_clock
8905          * agree once we know their relationship in the encoder's
8906          * get_config() function.
8907          */
8908         pipe_config->base.adjusted_mode.crtc_clock =
8909                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8910                                          &pipe_config->fdi_m_n);
8911 }
8912
8913 /** Returns the currently programmed mode of the given pipe. */
8914 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8915                                              struct drm_crtc *crtc)
8916 {
8917         struct drm_i915_private *dev_priv = dev->dev_private;
8918         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8919         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8920         struct drm_display_mode *mode;
8921         struct intel_crtc_state pipe_config;
8922         int htot = I915_READ(HTOTAL(cpu_transcoder));
8923         int hsync = I915_READ(HSYNC(cpu_transcoder));
8924         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8925         int vsync = I915_READ(VSYNC(cpu_transcoder));
8926         enum pipe pipe = intel_crtc->pipe;
8927
8928         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8929         if (!mode)
8930                 return NULL;
8931
8932         /*
8933          * Construct a pipe_config sufficient for getting the clock info
8934          * back out of crtc_clock_get.
8935          *
8936          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8937          * to use a real value here instead.
8938          */
8939         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8940         pipe_config.pixel_multiplier = 1;
8941         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8942         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8943         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8944         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8945
8946         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8947         mode->hdisplay = (htot & 0xffff) + 1;
8948         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8949         mode->hsync_start = (hsync & 0xffff) + 1;
8950         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8951         mode->vdisplay = (vtot & 0xffff) + 1;
8952         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8953         mode->vsync_start = (vsync & 0xffff) + 1;
8954         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8955
8956         drm_mode_set_name(mode);
8957
8958         return mode;
8959 }
8960
8961 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8962 {
8963         struct drm_device *dev = crtc->dev;
8964         struct drm_i915_private *dev_priv = dev->dev_private;
8965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8966
8967         if (!HAS_GMCH_DISPLAY(dev))
8968                 return;
8969
8970         if (!dev_priv->lvds_downclock_avail)
8971                 return;
8972
8973         /*
8974          * Since this is called by a timer, we should never get here in
8975          * the manual case.
8976          */
8977         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8978                 int pipe = intel_crtc->pipe;
8979                 int dpll_reg = DPLL(pipe);
8980                 int dpll;
8981
8982                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8983
8984                 assert_panel_unlocked(dev_priv, pipe);
8985
8986                 dpll = I915_READ(dpll_reg);
8987                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8988                 I915_WRITE(dpll_reg, dpll);
8989                 intel_wait_for_vblank(dev, pipe);
8990                 dpll = I915_READ(dpll_reg);
8991                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8992                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8993         }
8994
8995 }
8996
8997 void intel_mark_busy(struct drm_device *dev)
8998 {
8999         struct drm_i915_private *dev_priv = dev->dev_private;
9000
9001         if (dev_priv->mm.busy)
9002                 return;
9003
9004         intel_runtime_pm_get(dev_priv);
9005         i915_update_gfx_val(dev_priv);
9006         dev_priv->mm.busy = true;
9007 }
9008
9009 void intel_mark_idle(struct drm_device *dev)
9010 {
9011         struct drm_i915_private *dev_priv = dev->dev_private;
9012         struct drm_crtc *crtc;
9013
9014         if (!dev_priv->mm.busy)
9015                 return;
9016
9017         dev_priv->mm.busy = false;
9018
9019         if (!i915.powersave)
9020                 goto out;
9021
9022         for_each_crtc(dev, crtc) {
9023                 if (!crtc->primary->fb)
9024                         continue;
9025
9026                 intel_decrease_pllclock(crtc);
9027         }
9028
9029         if (INTEL_INFO(dev)->gen >= 6)
9030                 gen6_rps_idle(dev->dev_private);
9031
9032 out:
9033         intel_runtime_pm_put(dev_priv);
9034 }
9035
9036 static void intel_crtc_set_state(struct intel_crtc *crtc,
9037                                  struct intel_crtc_state *crtc_state)
9038 {
9039         kfree(crtc->config);
9040         crtc->config = crtc_state;
9041         crtc->base.state = &crtc_state->base;
9042 }
9043
9044 static void intel_crtc_destroy(struct drm_crtc *crtc)
9045 {
9046         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9047         struct drm_device *dev = crtc->dev;
9048         struct intel_unpin_work *work;
9049
9050         spin_lock_irq(&dev->event_lock);
9051         work = intel_crtc->unpin_work;
9052         intel_crtc->unpin_work = NULL;
9053         spin_unlock_irq(&dev->event_lock);
9054
9055         if (work) {
9056                 cancel_work_sync(&work->work);
9057                 kfree(work);
9058         }
9059
9060         intel_crtc_set_state(intel_crtc, NULL);
9061         drm_crtc_cleanup(crtc);
9062
9063         kfree(intel_crtc);
9064 }
9065
9066 static void intel_unpin_work_fn(struct work_struct *__work)
9067 {
9068         struct intel_unpin_work *work =
9069                 container_of(__work, struct intel_unpin_work, work);
9070         struct drm_device *dev = work->crtc->dev;
9071         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9072
9073         mutex_lock(&dev->struct_mutex);
9074         intel_unpin_fb_obj(work->old_fb_obj);
9075         drm_gem_object_unreference(&work->pending_flip_obj->base);
9076         drm_gem_object_unreference(&work->old_fb_obj->base);
9077
9078         intel_fbc_update(dev);
9079
9080         if (work->flip_queued_req)
9081                 i915_gem_request_assign(&work->flip_queued_req, NULL);
9082         mutex_unlock(&dev->struct_mutex);
9083
9084         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9085
9086         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9087         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9088
9089         kfree(work);
9090 }
9091
9092 static void do_intel_finish_page_flip(struct drm_device *dev,
9093                                       struct drm_crtc *crtc)
9094 {
9095         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9096         struct intel_unpin_work *work;
9097         unsigned long flags;
9098
9099         /* Ignore early vblank irqs */
9100         if (intel_crtc == NULL)
9101                 return;
9102
9103         /*
9104          * This is called both by irq handlers and the reset code (to complete
9105          * lost pageflips) so needs the full irqsave spinlocks.
9106          */
9107         spin_lock_irqsave(&dev->event_lock, flags);
9108         work = intel_crtc->unpin_work;
9109
9110         /* Ensure we don't miss a work->pending update ... */
9111         smp_rmb();
9112
9113         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9114                 spin_unlock_irqrestore(&dev->event_lock, flags);
9115                 return;
9116         }
9117
9118         page_flip_completed(intel_crtc);
9119
9120         spin_unlock_irqrestore(&dev->event_lock, flags);
9121 }
9122
9123 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9124 {
9125         struct drm_i915_private *dev_priv = dev->dev_private;
9126         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9127
9128         do_intel_finish_page_flip(dev, crtc);
9129 }
9130
9131 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9132 {
9133         struct drm_i915_private *dev_priv = dev->dev_private;
9134         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9135
9136         do_intel_finish_page_flip(dev, crtc);
9137 }
9138
9139 /* Is 'a' after or equal to 'b'? */
9140 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9141 {
9142         return !((a - b) & 0x80000000);
9143 }
9144
9145 static bool page_flip_finished(struct intel_crtc *crtc)
9146 {
9147         struct drm_device *dev = crtc->base.dev;
9148         struct drm_i915_private *dev_priv = dev->dev_private;
9149
9150         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9151             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9152                 return true;
9153
9154         /*
9155          * The relevant registers doen't exist on pre-ctg.
9156          * As the flip done interrupt doesn't trigger for mmio
9157          * flips on gmch platforms, a flip count check isn't
9158          * really needed there. But since ctg has the registers,
9159          * include it in the check anyway.
9160          */
9161         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9162                 return true;
9163
9164         /*
9165          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9166          * used the same base address. In that case the mmio flip might
9167          * have completed, but the CS hasn't even executed the flip yet.
9168          *
9169          * A flip count check isn't enough as the CS might have updated
9170          * the base address just after start of vblank, but before we
9171          * managed to process the interrupt. This means we'd complete the
9172          * CS flip too soon.
9173          *
9174          * Combining both checks should get us a good enough result. It may
9175          * still happen that the CS flip has been executed, but has not
9176          * yet actually completed. But in case the base address is the same
9177          * anyway, we don't really care.
9178          */
9179         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9180                 crtc->unpin_work->gtt_offset &&
9181                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9182                                     crtc->unpin_work->flip_count);
9183 }
9184
9185 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9186 {
9187         struct drm_i915_private *dev_priv = dev->dev_private;
9188         struct intel_crtc *intel_crtc =
9189                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9190         unsigned long flags;
9191
9192
9193         /*
9194          * This is called both by irq handlers and the reset code (to complete
9195          * lost pageflips) so needs the full irqsave spinlocks.
9196          *
9197          * NB: An MMIO update of the plane base pointer will also
9198          * generate a page-flip completion irq, i.e. every modeset
9199          * is also accompanied by a spurious intel_prepare_page_flip().
9200          */
9201         spin_lock_irqsave(&dev->event_lock, flags);
9202         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9203                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9204         spin_unlock_irqrestore(&dev->event_lock, flags);
9205 }
9206
9207 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9208 {
9209         /* Ensure that the work item is consistent when activating it ... */
9210         smp_wmb();
9211         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9212         /* and that it is marked active as soon as the irq could fire. */
9213         smp_wmb();
9214 }
9215
9216 static int intel_gen2_queue_flip(struct drm_device *dev,
9217                                  struct drm_crtc *crtc,
9218                                  struct drm_framebuffer *fb,
9219                                  struct drm_i915_gem_object *obj,
9220                                  struct intel_engine_cs *ring,
9221                                  uint32_t flags)
9222 {
9223         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9224         u32 flip_mask;
9225         int ret;
9226
9227         ret = intel_ring_begin(ring, 6);
9228         if (ret)
9229                 return ret;
9230
9231         /* Can't queue multiple flips, so wait for the previous
9232          * one to finish before executing the next.
9233          */
9234         if (intel_crtc->plane)
9235                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9236         else
9237                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9238         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9239         intel_ring_emit(ring, MI_NOOP);
9240         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9241                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9242         intel_ring_emit(ring, fb->pitches[0]);
9243         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9244         intel_ring_emit(ring, 0); /* aux display base address, unused */
9245
9246         intel_mark_page_flip_active(intel_crtc);
9247         __intel_ring_advance(ring);
9248         return 0;
9249 }
9250
9251 static int intel_gen3_queue_flip(struct drm_device *dev,
9252                                  struct drm_crtc *crtc,
9253                                  struct drm_framebuffer *fb,
9254                                  struct drm_i915_gem_object *obj,
9255                                  struct intel_engine_cs *ring,
9256                                  uint32_t flags)
9257 {
9258         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9259         u32 flip_mask;
9260         int ret;
9261
9262         ret = intel_ring_begin(ring, 6);
9263         if (ret)
9264                 return ret;
9265
9266         if (intel_crtc->plane)
9267                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9268         else
9269                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9270         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9271         intel_ring_emit(ring, MI_NOOP);
9272         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9273                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9274         intel_ring_emit(ring, fb->pitches[0]);
9275         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9276         intel_ring_emit(ring, MI_NOOP);
9277
9278         intel_mark_page_flip_active(intel_crtc);
9279         __intel_ring_advance(ring);
9280         return 0;
9281 }
9282
9283 static int intel_gen4_queue_flip(struct drm_device *dev,
9284                                  struct drm_crtc *crtc,
9285                                  struct drm_framebuffer *fb,
9286                                  struct drm_i915_gem_object *obj,
9287                                  struct intel_engine_cs *ring,
9288                                  uint32_t flags)
9289 {
9290         struct drm_i915_private *dev_priv = dev->dev_private;
9291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9292         uint32_t pf, pipesrc;
9293         int ret;
9294
9295         ret = intel_ring_begin(ring, 4);
9296         if (ret)
9297                 return ret;
9298
9299         /* i965+ uses the linear or tiled offsets from the
9300          * Display Registers (which do not change across a page-flip)
9301          * so we need only reprogram the base address.
9302          */
9303         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9304                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9305         intel_ring_emit(ring, fb->pitches[0]);
9306         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9307                         obj->tiling_mode);
9308
9309         /* XXX Enabling the panel-fitter across page-flip is so far
9310          * untested on non-native modes, so ignore it for now.
9311          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9312          */
9313         pf = 0;
9314         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9315         intel_ring_emit(ring, pf | pipesrc);
9316
9317         intel_mark_page_flip_active(intel_crtc);
9318         __intel_ring_advance(ring);
9319         return 0;
9320 }
9321
9322 static int intel_gen6_queue_flip(struct drm_device *dev,
9323                                  struct drm_crtc *crtc,
9324                                  struct drm_framebuffer *fb,
9325                                  struct drm_i915_gem_object *obj,
9326                                  struct intel_engine_cs *ring,
9327                                  uint32_t flags)
9328 {
9329         struct drm_i915_private *dev_priv = dev->dev_private;
9330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9331         uint32_t pf, pipesrc;
9332         int ret;
9333
9334         ret = intel_ring_begin(ring, 4);
9335         if (ret)
9336                 return ret;
9337
9338         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9339                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9340         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9341         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9342
9343         /* Contrary to the suggestions in the documentation,
9344          * "Enable Panel Fitter" does not seem to be required when page
9345          * flipping with a non-native mode, and worse causes a normal
9346          * modeset to fail.
9347          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9348          */
9349         pf = 0;
9350         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9351         intel_ring_emit(ring, pf | pipesrc);
9352
9353         intel_mark_page_flip_active(intel_crtc);
9354         __intel_ring_advance(ring);
9355         return 0;
9356 }
9357
9358 static int intel_gen7_queue_flip(struct drm_device *dev,
9359                                  struct drm_crtc *crtc,
9360                                  struct drm_framebuffer *fb,
9361                                  struct drm_i915_gem_object *obj,
9362                                  struct intel_engine_cs *ring,
9363                                  uint32_t flags)
9364 {
9365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9366         uint32_t plane_bit = 0;
9367         int len, ret;
9368
9369         switch (intel_crtc->plane) {
9370         case PLANE_A:
9371                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9372                 break;
9373         case PLANE_B:
9374                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9375                 break;
9376         case PLANE_C:
9377                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9378                 break;
9379         default:
9380                 WARN_ONCE(1, "unknown plane in flip command\n");
9381                 return -ENODEV;
9382         }
9383
9384         len = 4;
9385         if (ring->id == RCS) {
9386                 len += 6;
9387                 /*
9388                  * On Gen 8, SRM is now taking an extra dword to accommodate
9389                  * 48bits addresses, and we need a NOOP for the batch size to
9390                  * stay even.
9391                  */
9392                 if (IS_GEN8(dev))
9393                         len += 2;
9394         }
9395
9396         /*
9397          * BSpec MI_DISPLAY_FLIP for IVB:
9398          * "The full packet must be contained within the same cache line."
9399          *
9400          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9401          * cacheline, if we ever start emitting more commands before
9402          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9403          * then do the cacheline alignment, and finally emit the
9404          * MI_DISPLAY_FLIP.
9405          */
9406         ret = intel_ring_cacheline_align(ring);
9407         if (ret)
9408                 return ret;
9409
9410         ret = intel_ring_begin(ring, len);
9411         if (ret)
9412                 return ret;
9413
9414         /* Unmask the flip-done completion message. Note that the bspec says that
9415          * we should do this for both the BCS and RCS, and that we must not unmask
9416          * more than one flip event at any time (or ensure that one flip message
9417          * can be sent by waiting for flip-done prior to queueing new flips).
9418          * Experimentation says that BCS works despite DERRMR masking all
9419          * flip-done completion events and that unmasking all planes at once
9420          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9421          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9422          */
9423         if (ring->id == RCS) {
9424                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9425                 intel_ring_emit(ring, DERRMR);
9426                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9427                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9428                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9429                 if (IS_GEN8(dev))
9430                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9431                                               MI_SRM_LRM_GLOBAL_GTT);
9432                 else
9433                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9434                                               MI_SRM_LRM_GLOBAL_GTT);
9435                 intel_ring_emit(ring, DERRMR);
9436                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9437                 if (IS_GEN8(dev)) {
9438                         intel_ring_emit(ring, 0);
9439                         intel_ring_emit(ring, MI_NOOP);
9440                 }
9441         }
9442
9443         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9444         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9445         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9446         intel_ring_emit(ring, (MI_NOOP));
9447
9448         intel_mark_page_flip_active(intel_crtc);
9449         __intel_ring_advance(ring);
9450         return 0;
9451 }
9452
9453 static bool use_mmio_flip(struct intel_engine_cs *ring,
9454                           struct drm_i915_gem_object *obj)
9455 {
9456         /*
9457          * This is not being used for older platforms, because
9458          * non-availability of flip done interrupt forces us to use
9459          * CS flips. Older platforms derive flip done using some clever
9460          * tricks involving the flip_pending status bits and vblank irqs.
9461          * So using MMIO flips there would disrupt this mechanism.
9462          */
9463
9464         if (ring == NULL)
9465                 return true;
9466
9467         if (INTEL_INFO(ring->dev)->gen < 5)
9468                 return false;
9469
9470         if (i915.use_mmio_flip < 0)
9471                 return false;
9472         else if (i915.use_mmio_flip > 0)
9473                 return true;
9474         else if (i915.enable_execlists)
9475                 return true;
9476         else
9477                 return ring != i915_gem_request_get_ring(obj->last_read_req);
9478 }
9479
9480 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9481 {
9482         struct drm_device *dev = intel_crtc->base.dev;
9483         struct drm_i915_private *dev_priv = dev->dev_private;
9484         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9485         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9486         struct drm_i915_gem_object *obj = intel_fb->obj;
9487         const enum pipe pipe = intel_crtc->pipe;
9488         u32 ctl, stride;
9489
9490         ctl = I915_READ(PLANE_CTL(pipe, 0));
9491         ctl &= ~PLANE_CTL_TILED_MASK;
9492         if (obj->tiling_mode == I915_TILING_X)
9493                 ctl |= PLANE_CTL_TILED_X;
9494
9495         /*
9496          * The stride is either expressed as a multiple of 64 bytes chunks for
9497          * linear buffers or in number of tiles for tiled buffers.
9498          */
9499         stride = fb->pitches[0] >> 6;
9500         if (obj->tiling_mode == I915_TILING_X)
9501                 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9502
9503         /*
9504          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9505          * PLANE_SURF updates, the update is then guaranteed to be atomic.
9506          */
9507         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9508         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9509
9510         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9511         POSTING_READ(PLANE_SURF(pipe, 0));
9512 }
9513
9514 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9515 {
9516         struct drm_device *dev = intel_crtc->base.dev;
9517         struct drm_i915_private *dev_priv = dev->dev_private;
9518         struct intel_framebuffer *intel_fb =
9519                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9520         struct drm_i915_gem_object *obj = intel_fb->obj;
9521         u32 dspcntr;
9522         u32 reg;
9523
9524         reg = DSPCNTR(intel_crtc->plane);
9525         dspcntr = I915_READ(reg);
9526
9527         if (obj->tiling_mode != I915_TILING_NONE)
9528                 dspcntr |= DISPPLANE_TILED;
9529         else
9530                 dspcntr &= ~DISPPLANE_TILED;
9531
9532         I915_WRITE(reg, dspcntr);
9533
9534         I915_WRITE(DSPSURF(intel_crtc->plane),
9535                    intel_crtc->unpin_work->gtt_offset);
9536         POSTING_READ(DSPSURF(intel_crtc->plane));
9537
9538 }
9539
9540 /*
9541  * XXX: This is the temporary way to update the plane registers until we get
9542  * around to using the usual plane update functions for MMIO flips
9543  */
9544 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9545 {
9546         struct drm_device *dev = intel_crtc->base.dev;
9547         bool atomic_update;
9548         u32 start_vbl_count;
9549
9550         intel_mark_page_flip_active(intel_crtc);
9551
9552         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9553
9554         if (INTEL_INFO(dev)->gen >= 9)
9555                 skl_do_mmio_flip(intel_crtc);
9556         else
9557                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9558                 ilk_do_mmio_flip(intel_crtc);
9559
9560         if (atomic_update)
9561                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9562 }
9563
9564 static void intel_mmio_flip_work_func(struct work_struct *work)
9565 {
9566         struct intel_crtc *crtc =
9567                 container_of(work, struct intel_crtc, mmio_flip.work);
9568         struct intel_mmio_flip *mmio_flip;
9569
9570         mmio_flip = &crtc->mmio_flip;
9571         if (mmio_flip->req)
9572                 WARN_ON(__i915_wait_request(mmio_flip->req,
9573                                             crtc->reset_counter,
9574                                             false, NULL, NULL) != 0);
9575
9576         intel_do_mmio_flip(crtc);
9577         if (mmio_flip->req) {
9578                 mutex_lock(&crtc->base.dev->struct_mutex);
9579                 i915_gem_request_assign(&mmio_flip->req, NULL);
9580                 mutex_unlock(&crtc->base.dev->struct_mutex);
9581         }
9582 }
9583
9584 static int intel_queue_mmio_flip(struct drm_device *dev,
9585                                  struct drm_crtc *crtc,
9586                                  struct drm_framebuffer *fb,
9587                                  struct drm_i915_gem_object *obj,
9588                                  struct intel_engine_cs *ring,
9589                                  uint32_t flags)
9590 {
9591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9592
9593         i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9594                                 obj->last_write_req);
9595
9596         schedule_work(&intel_crtc->mmio_flip.work);
9597
9598         return 0;
9599 }
9600
9601 static int intel_gen9_queue_flip(struct drm_device *dev,
9602                                  struct drm_crtc *crtc,
9603                                  struct drm_framebuffer *fb,
9604                                  struct drm_i915_gem_object *obj,
9605                                  struct intel_engine_cs *ring,
9606                                  uint32_t flags)
9607 {
9608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9609         uint32_t plane = 0, stride;
9610         int ret;
9611
9612         switch(intel_crtc->pipe) {
9613         case PIPE_A:
9614                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9615                 break;
9616         case PIPE_B:
9617                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9618                 break;
9619         case PIPE_C:
9620                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9621                 break;
9622         default:
9623                 WARN_ONCE(1, "unknown plane in flip command\n");
9624                 return -ENODEV;
9625         }
9626
9627         switch (obj->tiling_mode) {
9628         case I915_TILING_NONE:
9629                 stride = fb->pitches[0] >> 6;
9630                 break;
9631         case I915_TILING_X:
9632                 stride = fb->pitches[0] >> 9;
9633                 break;
9634         default:
9635                 WARN_ONCE(1, "unknown tiling in flip command\n");
9636                 return -ENODEV;
9637         }
9638
9639         ret = intel_ring_begin(ring, 10);
9640         if (ret)
9641                 return ret;
9642
9643         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9644         intel_ring_emit(ring, DERRMR);
9645         intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9646                                 DERRMR_PIPEB_PRI_FLIP_DONE |
9647                                 DERRMR_PIPEC_PRI_FLIP_DONE));
9648         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9649                               MI_SRM_LRM_GLOBAL_GTT);
9650         intel_ring_emit(ring, DERRMR);
9651         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9652         intel_ring_emit(ring, 0);
9653
9654         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9655         intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9656         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9657
9658         intel_mark_page_flip_active(intel_crtc);
9659         __intel_ring_advance(ring);
9660
9661         return 0;
9662 }
9663
9664 static int intel_default_queue_flip(struct drm_device *dev,
9665                                     struct drm_crtc *crtc,
9666                                     struct drm_framebuffer *fb,
9667                                     struct drm_i915_gem_object *obj,
9668                                     struct intel_engine_cs *ring,
9669                                     uint32_t flags)
9670 {
9671         return -ENODEV;
9672 }
9673
9674 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9675                                          struct drm_crtc *crtc)
9676 {
9677         struct drm_i915_private *dev_priv = dev->dev_private;
9678         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9679         struct intel_unpin_work *work = intel_crtc->unpin_work;
9680         u32 addr;
9681
9682         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9683                 return true;
9684
9685         if (!work->enable_stall_check)
9686                 return false;
9687
9688         if (work->flip_ready_vblank == 0) {
9689                 if (work->flip_queued_req &&
9690                     !i915_gem_request_completed(work->flip_queued_req, true))
9691                         return false;
9692
9693                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9694         }
9695
9696         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9697                 return false;
9698
9699         /* Potential stall - if we see that the flip has happened,
9700          * assume a missed interrupt. */
9701         if (INTEL_INFO(dev)->gen >= 4)
9702                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9703         else
9704                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9705
9706         /* There is a potential issue here with a false positive after a flip
9707          * to the same address. We could address this by checking for a
9708          * non-incrementing frame counter.
9709          */
9710         return addr == work->gtt_offset;
9711 }
9712
9713 void intel_check_page_flip(struct drm_device *dev, int pipe)
9714 {
9715         struct drm_i915_private *dev_priv = dev->dev_private;
9716         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9717         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9718
9719         WARN_ON(!in_irq());
9720
9721         if (crtc == NULL)
9722                 return;
9723
9724         spin_lock(&dev->event_lock);
9725         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9726                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9727                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9728                 page_flip_completed(intel_crtc);
9729         }
9730         spin_unlock(&dev->event_lock);
9731 }
9732
9733 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9734                                 struct drm_framebuffer *fb,
9735                                 struct drm_pending_vblank_event *event,
9736                                 uint32_t page_flip_flags)
9737 {
9738         struct drm_device *dev = crtc->dev;
9739         struct drm_i915_private *dev_priv = dev->dev_private;
9740         struct drm_framebuffer *old_fb = crtc->primary->fb;
9741         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9743         struct drm_plane *primary = crtc->primary;
9744         enum pipe pipe = intel_crtc->pipe;
9745         struct intel_unpin_work *work;
9746         struct intel_engine_cs *ring;
9747         int ret;
9748
9749         /*
9750          * drm_mode_page_flip_ioctl() should already catch this, but double
9751          * check to be safe.  In the future we may enable pageflipping from
9752          * a disabled primary plane.
9753          */
9754         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9755                 return -EBUSY;
9756
9757         /* Can't change pixel format via MI display flips. */
9758         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9759                 return -EINVAL;
9760
9761         /*
9762          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9763          * Note that pitch changes could also affect these register.
9764          */
9765         if (INTEL_INFO(dev)->gen > 3 &&
9766             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9767              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9768                 return -EINVAL;
9769
9770         if (i915_terminally_wedged(&dev_priv->gpu_error))
9771                 goto out_hang;
9772
9773         work = kzalloc(sizeof(*work), GFP_KERNEL);
9774         if (work == NULL)
9775                 return -ENOMEM;
9776
9777         work->event = event;
9778         work->crtc = crtc;
9779         work->old_fb_obj = intel_fb_obj(old_fb);
9780         INIT_WORK(&work->work, intel_unpin_work_fn);
9781
9782         ret = drm_crtc_vblank_get(crtc);
9783         if (ret)
9784                 goto free_work;
9785
9786         /* We borrow the event spin lock for protecting unpin_work */
9787         spin_lock_irq(&dev->event_lock);
9788         if (intel_crtc->unpin_work) {
9789                 /* Before declaring the flip queue wedged, check if
9790                  * the hardware completed the operation behind our backs.
9791                  */
9792                 if (__intel_pageflip_stall_check(dev, crtc)) {
9793                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9794                         page_flip_completed(intel_crtc);
9795                 } else {
9796                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9797                         spin_unlock_irq(&dev->event_lock);
9798
9799                         drm_crtc_vblank_put(crtc);
9800                         kfree(work);
9801                         return -EBUSY;
9802                 }
9803         }
9804         intel_crtc->unpin_work = work;
9805         spin_unlock_irq(&dev->event_lock);
9806
9807         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9808                 flush_workqueue(dev_priv->wq);
9809
9810         ret = i915_mutex_lock_interruptible(dev);
9811         if (ret)
9812                 goto cleanup;
9813
9814         /* Reference the objects for the scheduled work. */
9815         drm_gem_object_reference(&work->old_fb_obj->base);
9816         drm_gem_object_reference(&obj->base);
9817
9818         crtc->primary->fb = fb;
9819
9820         work->pending_flip_obj = obj;
9821
9822         atomic_inc(&intel_crtc->unpin_work_count);
9823         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9824
9825         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9826                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9827
9828         if (IS_VALLEYVIEW(dev)) {
9829                 ring = &dev_priv->ring[BCS];
9830                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9831                         /* vlv: DISPLAY_FLIP fails to change tiling */
9832                         ring = NULL;
9833         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9834                 ring = &dev_priv->ring[BCS];
9835         } else if (INTEL_INFO(dev)->gen >= 7) {
9836                 ring = i915_gem_request_get_ring(obj->last_read_req);
9837                 if (ring == NULL || ring->id != RCS)
9838                         ring = &dev_priv->ring[BCS];
9839         } else {
9840                 ring = &dev_priv->ring[RCS];
9841         }
9842
9843         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9844         if (ret)
9845                 goto cleanup_pending;
9846
9847         work->gtt_offset =
9848                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9849
9850         if (use_mmio_flip(ring, obj)) {
9851                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9852                                             page_flip_flags);
9853                 if (ret)
9854                         goto cleanup_unpin;
9855
9856                 i915_gem_request_assign(&work->flip_queued_req,
9857                                         obj->last_write_req);
9858         } else {
9859                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9860                                                    page_flip_flags);
9861                 if (ret)
9862                         goto cleanup_unpin;
9863
9864                 i915_gem_request_assign(&work->flip_queued_req,
9865                                         intel_ring_get_request(ring));
9866         }
9867
9868         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9869         work->enable_stall_check = true;
9870
9871         i915_gem_track_fb(work->old_fb_obj, obj,
9872                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9873
9874         intel_fbc_disable(dev);
9875         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9876         mutex_unlock(&dev->struct_mutex);
9877
9878         trace_i915_flip_request(intel_crtc->plane, obj);
9879
9880         return 0;
9881
9882 cleanup_unpin:
9883         intel_unpin_fb_obj(obj);
9884 cleanup_pending:
9885         atomic_dec(&intel_crtc->unpin_work_count);
9886         crtc->primary->fb = old_fb;
9887         drm_gem_object_unreference(&work->old_fb_obj->base);
9888         drm_gem_object_unreference(&obj->base);
9889         mutex_unlock(&dev->struct_mutex);
9890
9891 cleanup:
9892         spin_lock_irq(&dev->event_lock);
9893         intel_crtc->unpin_work = NULL;
9894         spin_unlock_irq(&dev->event_lock);
9895
9896         drm_crtc_vblank_put(crtc);
9897 free_work:
9898         kfree(work);
9899
9900         if (ret == -EIO) {
9901 out_hang:
9902                 ret = intel_plane_restore(primary);
9903                 if (ret == 0 && event) {
9904                         spin_lock_irq(&dev->event_lock);
9905                         drm_send_vblank_event(dev, pipe, event);
9906                         spin_unlock_irq(&dev->event_lock);
9907                 }
9908         }
9909         return ret;
9910 }
9911
9912 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9913         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9914         .load_lut = intel_crtc_load_lut,
9915         .atomic_begin = intel_begin_crtc_commit,
9916         .atomic_flush = intel_finish_crtc_commit,
9917 };
9918
9919 /**
9920  * intel_modeset_update_staged_output_state
9921  *
9922  * Updates the staged output configuration state, e.g. after we've read out the
9923  * current hw state.
9924  */
9925 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9926 {
9927         struct intel_crtc *crtc;
9928         struct intel_encoder *encoder;
9929         struct intel_connector *connector;
9930
9931         list_for_each_entry(connector, &dev->mode_config.connector_list,
9932                             base.head) {
9933                 connector->new_encoder =
9934                         to_intel_encoder(connector->base.encoder);
9935         }
9936
9937         for_each_intel_encoder(dev, encoder) {
9938                 encoder->new_crtc =
9939                         to_intel_crtc(encoder->base.crtc);
9940         }
9941
9942         for_each_intel_crtc(dev, crtc) {
9943                 crtc->new_enabled = crtc->base.enabled;
9944
9945                 if (crtc->new_enabled)
9946                         crtc->new_config = crtc->config;
9947                 else
9948                         crtc->new_config = NULL;
9949         }
9950 }
9951
9952 /**
9953  * intel_modeset_commit_output_state
9954  *
9955  * This function copies the stage display pipe configuration to the real one.
9956  */
9957 static void intel_modeset_commit_output_state(struct drm_device *dev)
9958 {
9959         struct intel_crtc *crtc;
9960         struct intel_encoder *encoder;
9961         struct intel_connector *connector;
9962
9963         list_for_each_entry(connector, &dev->mode_config.connector_list,
9964                             base.head) {
9965                 connector->base.encoder = &connector->new_encoder->base;
9966         }
9967
9968         for_each_intel_encoder(dev, encoder) {
9969                 encoder->base.crtc = &encoder->new_crtc->base;
9970         }
9971
9972         for_each_intel_crtc(dev, crtc) {
9973                 crtc->base.enabled = crtc->new_enabled;
9974         }
9975 }
9976
9977 static void
9978 connected_sink_compute_bpp(struct intel_connector *connector,
9979                            struct intel_crtc_state *pipe_config)
9980 {
9981         int bpp = pipe_config->pipe_bpp;
9982
9983         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9984                 connector->base.base.id,
9985                 connector->base.name);
9986
9987         /* Don't use an invalid EDID bpc value */
9988         if (connector->base.display_info.bpc &&
9989             connector->base.display_info.bpc * 3 < bpp) {
9990                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9991                               bpp, connector->base.display_info.bpc*3);
9992                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9993         }
9994
9995         /* Clamp bpp to 8 on screens without EDID 1.4 */
9996         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9997                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9998                               bpp);
9999                 pipe_config->pipe_bpp = 24;
10000         }
10001 }
10002
10003 static int
10004 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10005                           struct drm_framebuffer *fb,
10006                           struct intel_crtc_state *pipe_config)
10007 {
10008         struct drm_device *dev = crtc->base.dev;
10009         struct intel_connector *connector;
10010         int bpp;
10011
10012         switch (fb->pixel_format) {
10013         case DRM_FORMAT_C8:
10014                 bpp = 8*3; /* since we go through a colormap */
10015                 break;
10016         case DRM_FORMAT_XRGB1555:
10017         case DRM_FORMAT_ARGB1555:
10018                 /* checked in intel_framebuffer_init already */
10019                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10020                         return -EINVAL;
10021         case DRM_FORMAT_RGB565:
10022                 bpp = 6*3; /* min is 18bpp */
10023                 break;
10024         case DRM_FORMAT_XBGR8888:
10025         case DRM_FORMAT_ABGR8888:
10026                 /* checked in intel_framebuffer_init already */
10027                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10028                         return -EINVAL;
10029         case DRM_FORMAT_XRGB8888:
10030         case DRM_FORMAT_ARGB8888:
10031                 bpp = 8*3;
10032                 break;
10033         case DRM_FORMAT_XRGB2101010:
10034         case DRM_FORMAT_ARGB2101010:
10035         case DRM_FORMAT_XBGR2101010:
10036         case DRM_FORMAT_ABGR2101010:
10037                 /* checked in intel_framebuffer_init already */
10038                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10039                         return -EINVAL;
10040                 bpp = 10*3;
10041                 break;
10042         /* TODO: gen4+ supports 16 bpc floating point, too. */
10043         default:
10044                 DRM_DEBUG_KMS("unsupported depth\n");
10045                 return -EINVAL;
10046         }
10047
10048         pipe_config->pipe_bpp = bpp;
10049
10050         /* Clamp display bpp to EDID value */
10051         list_for_each_entry(connector, &dev->mode_config.connector_list,
10052                             base.head) {
10053                 if (!connector->new_encoder ||
10054                     connector->new_encoder->new_crtc != crtc)
10055                         continue;
10056
10057                 connected_sink_compute_bpp(connector, pipe_config);
10058         }
10059
10060         return bpp;
10061 }
10062
10063 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10064 {
10065         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10066                         "type: 0x%x flags: 0x%x\n",
10067                 mode->crtc_clock,
10068                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10069                 mode->crtc_hsync_end, mode->crtc_htotal,
10070                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10071                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10072 }
10073
10074 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10075                                    struct intel_crtc_state *pipe_config,
10076                                    const char *context)
10077 {
10078         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10079                       context, pipe_name(crtc->pipe));
10080
10081         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10082         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10083                       pipe_config->pipe_bpp, pipe_config->dither);
10084         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10085                       pipe_config->has_pch_encoder,
10086                       pipe_config->fdi_lanes,
10087                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10088                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10089                       pipe_config->fdi_m_n.tu);
10090         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10091                       pipe_config->has_dp_encoder,
10092                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10093                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10094                       pipe_config->dp_m_n.tu);
10095
10096         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10097                       pipe_config->has_dp_encoder,
10098                       pipe_config->dp_m2_n2.gmch_m,
10099                       pipe_config->dp_m2_n2.gmch_n,
10100                       pipe_config->dp_m2_n2.link_m,
10101                       pipe_config->dp_m2_n2.link_n,
10102                       pipe_config->dp_m2_n2.tu);
10103
10104         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10105                       pipe_config->has_audio,
10106                       pipe_config->has_infoframe);
10107
10108         DRM_DEBUG_KMS("requested mode:\n");
10109         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10110         DRM_DEBUG_KMS("adjusted mode:\n");
10111         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10112         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10113         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10114         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10115                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10116         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10117                       pipe_config->gmch_pfit.control,
10118                       pipe_config->gmch_pfit.pgm_ratios,
10119                       pipe_config->gmch_pfit.lvds_border_bits);
10120         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10121                       pipe_config->pch_pfit.pos,
10122                       pipe_config->pch_pfit.size,
10123                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10124         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10125         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10126 }
10127
10128 static bool encoders_cloneable(const struct intel_encoder *a,
10129                                const struct intel_encoder *b)
10130 {
10131         /* masks could be asymmetric, so check both ways */
10132         return a == b || (a->cloneable & (1 << b->type) &&
10133                           b->cloneable & (1 << a->type));
10134 }
10135
10136 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10137                                          struct intel_encoder *encoder)
10138 {
10139         struct drm_device *dev = crtc->base.dev;
10140         struct intel_encoder *source_encoder;
10141
10142         for_each_intel_encoder(dev, source_encoder) {
10143                 if (source_encoder->new_crtc != crtc)
10144                         continue;
10145
10146                 if (!encoders_cloneable(encoder, source_encoder))
10147                         return false;
10148         }
10149
10150         return true;
10151 }
10152
10153 static bool check_encoder_cloning(struct intel_crtc *crtc)
10154 {
10155         struct drm_device *dev = crtc->base.dev;
10156         struct intel_encoder *encoder;
10157
10158         for_each_intel_encoder(dev, encoder) {
10159                 if (encoder->new_crtc != crtc)
10160                         continue;
10161
10162                 if (!check_single_encoder_cloning(crtc, encoder))
10163                         return false;
10164         }
10165
10166         return true;
10167 }
10168
10169 static bool check_digital_port_conflicts(struct drm_device *dev)
10170 {
10171         struct intel_connector *connector;
10172         unsigned int used_ports = 0;
10173
10174         /*
10175          * Walk the connector list instead of the encoder
10176          * list to detect the problem on ddi platforms
10177          * where there's just one encoder per digital port.
10178          */
10179         list_for_each_entry(connector,
10180                             &dev->mode_config.connector_list, base.head) {
10181                 struct intel_encoder *encoder = connector->new_encoder;
10182
10183                 if (!encoder)
10184                         continue;
10185
10186                 WARN_ON(!encoder->new_crtc);
10187
10188                 switch (encoder->type) {
10189                         unsigned int port_mask;
10190                 case INTEL_OUTPUT_UNKNOWN:
10191                         if (WARN_ON(!HAS_DDI(dev)))
10192                                 break;
10193                 case INTEL_OUTPUT_DISPLAYPORT:
10194                 case INTEL_OUTPUT_HDMI:
10195                 case INTEL_OUTPUT_EDP:
10196                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10197
10198                         /* the same port mustn't appear more than once */
10199                         if (used_ports & port_mask)
10200                                 return false;
10201
10202                         used_ports |= port_mask;
10203                 default:
10204                         break;
10205                 }
10206         }
10207
10208         return true;
10209 }
10210
10211 static struct intel_crtc_state *
10212 intel_modeset_pipe_config(struct drm_crtc *crtc,
10213                           struct drm_framebuffer *fb,
10214                           struct drm_display_mode *mode)
10215 {
10216         struct drm_device *dev = crtc->dev;
10217         struct intel_encoder *encoder;
10218         struct intel_crtc_state *pipe_config;
10219         int plane_bpp, ret = -EINVAL;
10220         bool retry = true;
10221
10222         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10223                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10224                 return ERR_PTR(-EINVAL);
10225         }
10226
10227         if (!check_digital_port_conflicts(dev)) {
10228                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10229                 return ERR_PTR(-EINVAL);
10230         }
10231
10232         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10233         if (!pipe_config)
10234                 return ERR_PTR(-ENOMEM);
10235
10236         drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10237         drm_mode_copy(&pipe_config->base.mode, mode);
10238
10239         pipe_config->cpu_transcoder =
10240                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10241         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10242
10243         /*
10244          * Sanitize sync polarity flags based on requested ones. If neither
10245          * positive or negative polarity is requested, treat this as meaning
10246          * negative polarity.
10247          */
10248         if (!(pipe_config->base.adjusted_mode.flags &
10249               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10250                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10251
10252         if (!(pipe_config->base.adjusted_mode.flags &
10253               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10254                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10255
10256         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10257          * plane pixel format and any sink constraints into account. Returns the
10258          * source plane bpp so that dithering can be selected on mismatches
10259          * after encoders and crtc also have had their say. */
10260         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10261                                               fb, pipe_config);
10262         if (plane_bpp < 0)
10263                 goto fail;
10264
10265         /*
10266          * Determine the real pipe dimensions. Note that stereo modes can
10267          * increase the actual pipe size due to the frame doubling and
10268          * insertion of additional space for blanks between the frame. This
10269          * is stored in the crtc timings. We use the requested mode to do this
10270          * computation to clearly distinguish it from the adjusted mode, which
10271          * can be changed by the connectors in the below retry loop.
10272          */
10273         drm_crtc_get_hv_timing(&pipe_config->base.mode,
10274                                &pipe_config->pipe_src_w,
10275                                &pipe_config->pipe_src_h);
10276
10277 encoder_retry:
10278         /* Ensure the port clock defaults are reset when retrying. */
10279         pipe_config->port_clock = 0;
10280         pipe_config->pixel_multiplier = 1;
10281
10282         /* Fill in default crtc timings, allow encoders to overwrite them. */
10283         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10284                               CRTC_STEREO_DOUBLE);
10285
10286         /* Pass our mode to the connectors and the CRTC to give them a chance to
10287          * adjust it according to limitations or connector properties, and also
10288          * a chance to reject the mode entirely.
10289          */
10290         for_each_intel_encoder(dev, encoder) {
10291
10292                 if (&encoder->new_crtc->base != crtc)
10293                         continue;
10294
10295                 if (!(encoder->compute_config(encoder, pipe_config))) {
10296                         DRM_DEBUG_KMS("Encoder config failure\n");
10297                         goto fail;
10298                 }
10299         }
10300
10301         /* Set default port clock if not overwritten by the encoder. Needs to be
10302          * done afterwards in case the encoder adjusts the mode. */
10303         if (!pipe_config->port_clock)
10304                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10305                         * pipe_config->pixel_multiplier;
10306
10307         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10308         if (ret < 0) {
10309                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10310                 goto fail;
10311         }
10312
10313         if (ret == RETRY) {
10314                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10315                         ret = -EINVAL;
10316                         goto fail;
10317                 }
10318
10319                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10320                 retry = false;
10321                 goto encoder_retry;
10322         }
10323
10324         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10325         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10326                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10327
10328         return pipe_config;
10329 fail:
10330         kfree(pipe_config);
10331         return ERR_PTR(ret);
10332 }
10333
10334 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10335  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10336 static void
10337 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10338                              unsigned *prepare_pipes, unsigned *disable_pipes)
10339 {
10340         struct intel_crtc *intel_crtc;
10341         struct drm_device *dev = crtc->dev;
10342         struct intel_encoder *encoder;
10343         struct intel_connector *connector;
10344         struct drm_crtc *tmp_crtc;
10345
10346         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10347
10348         /* Check which crtcs have changed outputs connected to them, these need
10349          * to be part of the prepare_pipes mask. We don't (yet) support global
10350          * modeset across multiple crtcs, so modeset_pipes will only have one
10351          * bit set at most. */
10352         list_for_each_entry(connector, &dev->mode_config.connector_list,
10353                             base.head) {
10354                 if (connector->base.encoder == &connector->new_encoder->base)
10355                         continue;
10356
10357                 if (connector->base.encoder) {
10358                         tmp_crtc = connector->base.encoder->crtc;
10359
10360                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10361                 }
10362
10363                 if (connector->new_encoder)
10364                         *prepare_pipes |=
10365                                 1 << connector->new_encoder->new_crtc->pipe;
10366         }
10367
10368         for_each_intel_encoder(dev, encoder) {
10369                 if (encoder->base.crtc == &encoder->new_crtc->base)
10370                         continue;
10371
10372                 if (encoder->base.crtc) {
10373                         tmp_crtc = encoder->base.crtc;
10374
10375                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10376                 }
10377
10378                 if (encoder->new_crtc)
10379                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10380         }
10381
10382         /* Check for pipes that will be enabled/disabled ... */
10383         for_each_intel_crtc(dev, intel_crtc) {
10384                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10385                         continue;
10386
10387                 if (!intel_crtc->new_enabled)
10388                         *disable_pipes |= 1 << intel_crtc->pipe;
10389                 else
10390                         *prepare_pipes |= 1 << intel_crtc->pipe;
10391         }
10392
10393
10394         /* set_mode is also used to update properties on life display pipes. */
10395         intel_crtc = to_intel_crtc(crtc);
10396         if (intel_crtc->new_enabled)
10397                 *prepare_pipes |= 1 << intel_crtc->pipe;
10398
10399         /*
10400          * For simplicity do a full modeset on any pipe where the output routing
10401          * changed. We could be more clever, but that would require us to be
10402          * more careful with calling the relevant encoder->mode_set functions.
10403          */
10404         if (*prepare_pipes)
10405                 *modeset_pipes = *prepare_pipes;
10406
10407         /* ... and mask these out. */
10408         *modeset_pipes &= ~(*disable_pipes);
10409         *prepare_pipes &= ~(*disable_pipes);
10410
10411         /*
10412          * HACK: We don't (yet) fully support global modesets. intel_set_config
10413          * obies this rule, but the modeset restore mode of
10414          * intel_modeset_setup_hw_state does not.
10415          */
10416         *modeset_pipes &= 1 << intel_crtc->pipe;
10417         *prepare_pipes &= 1 << intel_crtc->pipe;
10418
10419         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10420                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10421 }
10422
10423 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10424 {
10425         struct drm_encoder *encoder;
10426         struct drm_device *dev = crtc->dev;
10427
10428         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10429                 if (encoder->crtc == crtc)
10430                         return true;
10431
10432         return false;
10433 }
10434
10435 static void
10436 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10437 {
10438         struct drm_i915_private *dev_priv = dev->dev_private;
10439         struct intel_encoder *intel_encoder;
10440         struct intel_crtc *intel_crtc;
10441         struct drm_connector *connector;
10442
10443         intel_shared_dpll_commit(dev_priv);
10444
10445         for_each_intel_encoder(dev, intel_encoder) {
10446                 if (!intel_encoder->base.crtc)
10447                         continue;
10448
10449                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10450
10451                 if (prepare_pipes & (1 << intel_crtc->pipe))
10452                         intel_encoder->connectors_active = false;
10453         }
10454
10455         intel_modeset_commit_output_state(dev);
10456
10457         /* Double check state. */
10458         for_each_intel_crtc(dev, intel_crtc) {
10459                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10460                 WARN_ON(intel_crtc->new_config &&
10461                         intel_crtc->new_config != intel_crtc->config);
10462                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10463         }
10464
10465         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10466                 if (!connector->encoder || !connector->encoder->crtc)
10467                         continue;
10468
10469                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10470
10471                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10472                         struct drm_property *dpms_property =
10473                                 dev->mode_config.dpms_property;
10474
10475                         connector->dpms = DRM_MODE_DPMS_ON;
10476                         drm_object_property_set_value(&connector->base,
10477                                                          dpms_property,
10478                                                          DRM_MODE_DPMS_ON);
10479
10480                         intel_encoder = to_intel_encoder(connector->encoder);
10481                         intel_encoder->connectors_active = true;
10482                 }
10483         }
10484
10485 }
10486
10487 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10488 {
10489         int diff;
10490
10491         if (clock1 == clock2)
10492                 return true;
10493
10494         if (!clock1 || !clock2)
10495                 return false;
10496
10497         diff = abs(clock1 - clock2);
10498
10499         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10500                 return true;
10501
10502         return false;
10503 }
10504
10505 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10506         list_for_each_entry((intel_crtc), \
10507                             &(dev)->mode_config.crtc_list, \
10508                             base.head) \
10509                 if (mask & (1 <<(intel_crtc)->pipe))
10510
10511 static bool
10512 intel_pipe_config_compare(struct drm_device *dev,
10513                           struct intel_crtc_state *current_config,
10514                           struct intel_crtc_state *pipe_config)
10515 {
10516 #define PIPE_CONF_CHECK_X(name) \
10517         if (current_config->name != pipe_config->name) { \
10518                 DRM_ERROR("mismatch in " #name " " \
10519                           "(expected 0x%08x, found 0x%08x)\n", \
10520                           current_config->name, \
10521                           pipe_config->name); \
10522                 return false; \
10523         }
10524
10525 #define PIPE_CONF_CHECK_I(name) \
10526         if (current_config->name != pipe_config->name) { \
10527                 DRM_ERROR("mismatch in " #name " " \
10528                           "(expected %i, found %i)\n", \
10529                           current_config->name, \
10530                           pipe_config->name); \
10531                 return false; \
10532         }
10533
10534 /* This is required for BDW+ where there is only one set of registers for
10535  * switching between high and low RR.
10536  * This macro can be used whenever a comparison has to be made between one
10537  * hw state and multiple sw state variables.
10538  */
10539 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10540         if ((current_config->name != pipe_config->name) && \
10541                 (current_config->alt_name != pipe_config->name)) { \
10542                         DRM_ERROR("mismatch in " #name " " \
10543                                   "(expected %i or %i, found %i)\n", \
10544                                   current_config->name, \
10545                                   current_config->alt_name, \
10546                                   pipe_config->name); \
10547                         return false; \
10548         }
10549
10550 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10551         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10552                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10553                           "(expected %i, found %i)\n", \
10554                           current_config->name & (mask), \
10555                           pipe_config->name & (mask)); \
10556                 return false; \
10557         }
10558
10559 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10560         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10561                 DRM_ERROR("mismatch in " #name " " \
10562                           "(expected %i, found %i)\n", \
10563                           current_config->name, \
10564                           pipe_config->name); \
10565                 return false; \
10566         }
10567
10568 #define PIPE_CONF_QUIRK(quirk)  \
10569         ((current_config->quirks | pipe_config->quirks) & (quirk))
10570
10571         PIPE_CONF_CHECK_I(cpu_transcoder);
10572
10573         PIPE_CONF_CHECK_I(has_pch_encoder);
10574         PIPE_CONF_CHECK_I(fdi_lanes);
10575         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10576         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10577         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10578         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10579         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10580
10581         PIPE_CONF_CHECK_I(has_dp_encoder);
10582
10583         if (INTEL_INFO(dev)->gen < 8) {
10584                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10585                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10586                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10587                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10588                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10589
10590                 if (current_config->has_drrs) {
10591                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10592                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10593                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10594                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10595                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10596                 }
10597         } else {
10598                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10599                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10600                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10601                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10602                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10603         }
10604
10605         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10606         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10607         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10608         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10609         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10610         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10611
10612         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10613         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10614         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10615         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10616         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10617         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10618
10619         PIPE_CONF_CHECK_I(pixel_multiplier);
10620         PIPE_CONF_CHECK_I(has_hdmi_sink);
10621         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10622             IS_VALLEYVIEW(dev))
10623                 PIPE_CONF_CHECK_I(limited_color_range);
10624         PIPE_CONF_CHECK_I(has_infoframe);
10625
10626         PIPE_CONF_CHECK_I(has_audio);
10627
10628         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10629                               DRM_MODE_FLAG_INTERLACE);
10630
10631         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10632                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10633                                       DRM_MODE_FLAG_PHSYNC);
10634                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10635                                       DRM_MODE_FLAG_NHSYNC);
10636                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10637                                       DRM_MODE_FLAG_PVSYNC);
10638                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10639                                       DRM_MODE_FLAG_NVSYNC);
10640         }
10641
10642         PIPE_CONF_CHECK_I(pipe_src_w);
10643         PIPE_CONF_CHECK_I(pipe_src_h);
10644
10645         /*
10646          * FIXME: BIOS likes to set up a cloned config with lvds+external
10647          * screen. Since we don't yet re-compute the pipe config when moving
10648          * just the lvds port away to another pipe the sw tracking won't match.
10649          *
10650          * Proper atomic modesets with recomputed global state will fix this.
10651          * Until then just don't check gmch state for inherited modes.
10652          */
10653         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10654                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10655                 /* pfit ratios are autocomputed by the hw on gen4+ */
10656                 if (INTEL_INFO(dev)->gen < 4)
10657                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10658                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10659         }
10660
10661         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10662         if (current_config->pch_pfit.enabled) {
10663                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10664                 PIPE_CONF_CHECK_I(pch_pfit.size);
10665         }
10666
10667         /* BDW+ don't expose a synchronous way to read the state */
10668         if (IS_HASWELL(dev))
10669                 PIPE_CONF_CHECK_I(ips_enabled);
10670
10671         PIPE_CONF_CHECK_I(double_wide);
10672
10673         PIPE_CONF_CHECK_X(ddi_pll_sel);
10674
10675         PIPE_CONF_CHECK_I(shared_dpll);
10676         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10677         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10678         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10679         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10680         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10681         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10682         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10683         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10684
10685         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10686                 PIPE_CONF_CHECK_I(pipe_bpp);
10687
10688         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10689         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10690
10691 #undef PIPE_CONF_CHECK_X
10692 #undef PIPE_CONF_CHECK_I
10693 #undef PIPE_CONF_CHECK_I_ALT
10694 #undef PIPE_CONF_CHECK_FLAGS
10695 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10696 #undef PIPE_CONF_QUIRK
10697
10698         return true;
10699 }
10700
10701 static void check_wm_state(struct drm_device *dev)
10702 {
10703         struct drm_i915_private *dev_priv = dev->dev_private;
10704         struct skl_ddb_allocation hw_ddb, *sw_ddb;
10705         struct intel_crtc *intel_crtc;
10706         int plane;
10707
10708         if (INTEL_INFO(dev)->gen < 9)
10709                 return;
10710
10711         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10712         sw_ddb = &dev_priv->wm.skl_hw.ddb;
10713
10714         for_each_intel_crtc(dev, intel_crtc) {
10715                 struct skl_ddb_entry *hw_entry, *sw_entry;
10716                 const enum pipe pipe = intel_crtc->pipe;
10717
10718                 if (!intel_crtc->active)
10719                         continue;
10720
10721                 /* planes */
10722                 for_each_plane(pipe, plane) {
10723                         hw_entry = &hw_ddb.plane[pipe][plane];
10724                         sw_entry = &sw_ddb->plane[pipe][plane];
10725
10726                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
10727                                 continue;
10728
10729                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10730                                   "(expected (%u,%u), found (%u,%u))\n",
10731                                   pipe_name(pipe), plane + 1,
10732                                   sw_entry->start, sw_entry->end,
10733                                   hw_entry->start, hw_entry->end);
10734                 }
10735
10736                 /* cursor */
10737                 hw_entry = &hw_ddb.cursor[pipe];
10738                 sw_entry = &sw_ddb->cursor[pipe];
10739
10740                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10741                         continue;
10742
10743                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10744                           "(expected (%u,%u), found (%u,%u))\n",
10745                           pipe_name(pipe),
10746                           sw_entry->start, sw_entry->end,
10747                           hw_entry->start, hw_entry->end);
10748         }
10749 }
10750
10751 static void
10752 check_connector_state(struct drm_device *dev)
10753 {
10754         struct intel_connector *connector;
10755
10756         list_for_each_entry(connector, &dev->mode_config.connector_list,
10757                             base.head) {
10758                 /* This also checks the encoder/connector hw state with the
10759                  * ->get_hw_state callbacks. */
10760                 intel_connector_check_state(connector);
10761
10762                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10763                      "connector's staged encoder doesn't match current encoder\n");
10764         }
10765 }
10766
10767 static void
10768 check_encoder_state(struct drm_device *dev)
10769 {
10770         struct intel_encoder *encoder;
10771         struct intel_connector *connector;
10772
10773         for_each_intel_encoder(dev, encoder) {
10774                 bool enabled = false;
10775                 bool active = false;
10776                 enum pipe pipe, tracked_pipe;
10777
10778                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10779                               encoder->base.base.id,
10780                               encoder->base.name);
10781
10782                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10783                      "encoder's stage crtc doesn't match current crtc\n");
10784                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10785                      "encoder's active_connectors set, but no crtc\n");
10786
10787                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10788                                     base.head) {
10789                         if (connector->base.encoder != &encoder->base)
10790                                 continue;
10791                         enabled = true;
10792                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10793                                 active = true;
10794                 }
10795                 /*
10796                  * for MST connectors if we unplug the connector is gone
10797                  * away but the encoder is still connected to a crtc
10798                  * until a modeset happens in response to the hotplug.
10799                  */
10800                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10801                         continue;
10802
10803                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10804                      "encoder's enabled state mismatch "
10805                      "(expected %i, found %i)\n",
10806                      !!encoder->base.crtc, enabled);
10807                 I915_STATE_WARN(active && !encoder->base.crtc,
10808                      "active encoder with no crtc\n");
10809
10810                 I915_STATE_WARN(encoder->connectors_active != active,
10811                      "encoder's computed active state doesn't match tracked active state "
10812                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10813
10814                 active = encoder->get_hw_state(encoder, &pipe);
10815                 I915_STATE_WARN(active != encoder->connectors_active,
10816                      "encoder's hw state doesn't match sw tracking "
10817                      "(expected %i, found %i)\n",
10818                      encoder->connectors_active, active);
10819
10820                 if (!encoder->base.crtc)
10821                         continue;
10822
10823                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10824                 I915_STATE_WARN(active && pipe != tracked_pipe,
10825                      "active encoder's pipe doesn't match"
10826                      "(expected %i, found %i)\n",
10827                      tracked_pipe, pipe);
10828
10829         }
10830 }
10831
10832 static void
10833 check_crtc_state(struct drm_device *dev)
10834 {
10835         struct drm_i915_private *dev_priv = dev->dev_private;
10836         struct intel_crtc *crtc;
10837         struct intel_encoder *encoder;
10838         struct intel_crtc_state pipe_config;
10839
10840         for_each_intel_crtc(dev, crtc) {
10841                 bool enabled = false;
10842                 bool active = false;
10843
10844                 memset(&pipe_config, 0, sizeof(pipe_config));
10845
10846                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10847                               crtc->base.base.id);
10848
10849                 I915_STATE_WARN(crtc->active && !crtc->base.enabled,
10850                      "active crtc, but not enabled in sw tracking\n");
10851
10852                 for_each_intel_encoder(dev, encoder) {
10853                         if (encoder->base.crtc != &crtc->base)
10854                                 continue;
10855                         enabled = true;
10856                         if (encoder->connectors_active)
10857                                 active = true;
10858                 }
10859
10860                 I915_STATE_WARN(active != crtc->active,
10861                      "crtc's computed active state doesn't match tracked active state "
10862                      "(expected %i, found %i)\n", active, crtc->active);
10863                 I915_STATE_WARN(enabled != crtc->base.enabled,
10864                      "crtc's computed enabled state doesn't match tracked enabled state "
10865                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10866
10867                 active = dev_priv->display.get_pipe_config(crtc,
10868                                                            &pipe_config);
10869
10870                 /* hw state is inconsistent with the pipe quirk */
10871                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10872                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10873                         active = crtc->active;
10874
10875                 for_each_intel_encoder(dev, encoder) {
10876                         enum pipe pipe;
10877                         if (encoder->base.crtc != &crtc->base)
10878                                 continue;
10879                         if (encoder->get_hw_state(encoder, &pipe))
10880                                 encoder->get_config(encoder, &pipe_config);
10881                 }
10882
10883                 I915_STATE_WARN(crtc->active != active,
10884                      "crtc active state doesn't match with hw state "
10885                      "(expected %i, found %i)\n", crtc->active, active);
10886
10887                 if (active &&
10888                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10889                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
10890                         intel_dump_pipe_config(crtc, &pipe_config,
10891                                                "[hw state]");
10892                         intel_dump_pipe_config(crtc, crtc->config,
10893                                                "[sw state]");
10894                 }
10895         }
10896 }
10897
10898 static void
10899 check_shared_dpll_state(struct drm_device *dev)
10900 {
10901         struct drm_i915_private *dev_priv = dev->dev_private;
10902         struct intel_crtc *crtc;
10903         struct intel_dpll_hw_state dpll_hw_state;
10904         int i;
10905
10906         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10907                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10908                 int enabled_crtcs = 0, active_crtcs = 0;
10909                 bool active;
10910
10911                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10912
10913                 DRM_DEBUG_KMS("%s\n", pll->name);
10914
10915                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10916
10917                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10918                      "more active pll users than references: %i vs %i\n",
10919                      pll->active, hweight32(pll->config.crtc_mask));
10920                 I915_STATE_WARN(pll->active && !pll->on,
10921                      "pll in active use but not on in sw tracking\n");
10922                 I915_STATE_WARN(pll->on && !pll->active,
10923                      "pll in on but not on in use in sw tracking\n");
10924                 I915_STATE_WARN(pll->on != active,
10925                      "pll on state mismatch (expected %i, found %i)\n",
10926                      pll->on, active);
10927
10928                 for_each_intel_crtc(dev, crtc) {
10929                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10930                                 enabled_crtcs++;
10931                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10932                                 active_crtcs++;
10933                 }
10934                 I915_STATE_WARN(pll->active != active_crtcs,
10935                      "pll active crtcs mismatch (expected %i, found %i)\n",
10936                      pll->active, active_crtcs);
10937                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10938                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10939                      hweight32(pll->config.crtc_mask), enabled_crtcs);
10940
10941                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10942                                        sizeof(dpll_hw_state)),
10943                      "pll hw state mismatch\n");
10944         }
10945 }
10946
10947 void
10948 intel_modeset_check_state(struct drm_device *dev)
10949 {
10950         check_wm_state(dev);
10951         check_connector_state(dev);
10952         check_encoder_state(dev);
10953         check_crtc_state(dev);
10954         check_shared_dpll_state(dev);
10955 }
10956
10957 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10958                                      int dotclock)
10959 {
10960         /*
10961          * FDI already provided one idea for the dotclock.
10962          * Yell if the encoder disagrees.
10963          */
10964         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
10965              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10966              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
10967 }
10968
10969 static void update_scanline_offset(struct intel_crtc *crtc)
10970 {
10971         struct drm_device *dev = crtc->base.dev;
10972
10973         /*
10974          * The scanline counter increments at the leading edge of hsync.
10975          *
10976          * On most platforms it starts counting from vtotal-1 on the
10977          * first active line. That means the scanline counter value is
10978          * always one less than what we would expect. Ie. just after
10979          * start of vblank, which also occurs at start of hsync (on the
10980          * last active line), the scanline counter will read vblank_start-1.
10981          *
10982          * On gen2 the scanline counter starts counting from 1 instead
10983          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10984          * to keep the value positive), instead of adding one.
10985          *
10986          * On HSW+ the behaviour of the scanline counter depends on the output
10987          * type. For DP ports it behaves like most other platforms, but on HDMI
10988          * there's an extra 1 line difference. So we need to add two instead of
10989          * one to the value.
10990          */
10991         if (IS_GEN2(dev)) {
10992                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
10993                 int vtotal;
10994
10995                 vtotal = mode->crtc_vtotal;
10996                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10997                         vtotal /= 2;
10998
10999                 crtc->scanline_offset = vtotal - 1;
11000         } else if (HAS_DDI(dev) &&
11001                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11002                 crtc->scanline_offset = 2;
11003         } else
11004                 crtc->scanline_offset = 1;
11005 }
11006
11007 static struct intel_crtc_state *
11008 intel_modeset_compute_config(struct drm_crtc *crtc,
11009                              struct drm_display_mode *mode,
11010                              struct drm_framebuffer *fb,
11011                              unsigned *modeset_pipes,
11012                              unsigned *prepare_pipes,
11013                              unsigned *disable_pipes)
11014 {
11015         struct intel_crtc_state *pipe_config = NULL;
11016
11017         intel_modeset_affected_pipes(crtc, modeset_pipes,
11018                                      prepare_pipes, disable_pipes);
11019
11020         if ((*modeset_pipes) == 0)
11021                 goto out;
11022
11023         /*
11024          * Note this needs changes when we start tracking multiple modes
11025          * and crtcs.  At that point we'll need to compute the whole config
11026          * (i.e. one pipe_config for each crtc) rather than just the one
11027          * for this crtc.
11028          */
11029         pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11030         if (IS_ERR(pipe_config)) {
11031                 goto out;
11032         }
11033         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11034                                "[modeset]");
11035
11036 out:
11037         return pipe_config;
11038 }
11039
11040 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11041                                        unsigned modeset_pipes,
11042                                        unsigned disable_pipes)
11043 {
11044         struct drm_i915_private *dev_priv = to_i915(dev);
11045         unsigned clear_pipes = modeset_pipes | disable_pipes;
11046         struct intel_crtc *intel_crtc;
11047         int ret = 0;
11048
11049         if (!dev_priv->display.crtc_compute_clock)
11050                 return 0;
11051
11052         ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11053         if (ret)
11054                 goto done;
11055
11056         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11057                 struct intel_crtc_state *state = intel_crtc->new_config;
11058                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11059                                                            state);
11060                 if (ret) {
11061                         intel_shared_dpll_abort_config(dev_priv);
11062                         goto done;
11063                 }
11064         }
11065
11066 done:
11067         return ret;
11068 }
11069
11070 static int __intel_set_mode(struct drm_crtc *crtc,
11071                             struct drm_display_mode *mode,
11072                             int x, int y, struct drm_framebuffer *fb,
11073                             struct intel_crtc_state *pipe_config,
11074                             unsigned modeset_pipes,
11075                             unsigned prepare_pipes,
11076                             unsigned disable_pipes)
11077 {
11078         struct drm_device *dev = crtc->dev;
11079         struct drm_i915_private *dev_priv = dev->dev_private;
11080         struct drm_display_mode *saved_mode;
11081         struct intel_crtc *intel_crtc;
11082         int ret = 0;
11083
11084         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11085         if (!saved_mode)
11086                 return -ENOMEM;
11087
11088         *saved_mode = crtc->mode;
11089
11090         if (modeset_pipes)
11091                 to_intel_crtc(crtc)->new_config = pipe_config;
11092
11093         /*
11094          * See if the config requires any additional preparation, e.g.
11095          * to adjust global state with pipes off.  We need to do this
11096          * here so we can get the modeset_pipe updated config for the new
11097          * mode set on this crtc.  For other crtcs we need to use the
11098          * adjusted_mode bits in the crtc directly.
11099          */
11100         if (IS_VALLEYVIEW(dev)) {
11101                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11102
11103                 /* may have added more to prepare_pipes than we should */
11104                 prepare_pipes &= ~disable_pipes;
11105         }
11106
11107         ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11108         if (ret)
11109                 goto done;
11110
11111         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11112                 intel_crtc_disable(&intel_crtc->base);
11113
11114         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11115                 if (intel_crtc->base.enabled)
11116                         dev_priv->display.crtc_disable(&intel_crtc->base);
11117         }
11118
11119         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11120          * to set it here already despite that we pass it down the callchain.
11121          *
11122          * Note we'll need to fix this up when we start tracking multiple
11123          * pipes; here we assume a single modeset_pipe and only track the
11124          * single crtc and mode.
11125          */
11126         if (modeset_pipes) {
11127                 crtc->mode = *mode;
11128                 /* mode_set/enable/disable functions rely on a correct pipe
11129                  * config. */
11130                 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11131
11132                 /*
11133                  * Calculate and store various constants which
11134                  * are later needed by vblank and swap-completion
11135                  * timestamping. They are derived from true hwmode.
11136                  */
11137                 drm_calc_timestamping_constants(crtc,
11138                                                 &pipe_config->base.adjusted_mode);
11139         }
11140
11141         /* Only after disabling all output pipelines that will be changed can we
11142          * update the the output configuration. */
11143         intel_modeset_update_state(dev, prepare_pipes);
11144
11145         modeset_update_crtc_power_domains(dev);
11146
11147         /* Set up the DPLL and any encoders state that needs to adjust or depend
11148          * on the DPLL.
11149          */
11150         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11151                 struct drm_plane *primary = intel_crtc->base.primary;
11152                 int vdisplay, hdisplay;
11153
11154                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11155                 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11156                                                    fb, 0, 0,
11157                                                    hdisplay, vdisplay,
11158                                                    x << 16, y << 16,
11159                                                    hdisplay << 16, vdisplay << 16);
11160         }
11161
11162         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11163         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11164                 update_scanline_offset(intel_crtc);
11165
11166                 dev_priv->display.crtc_enable(&intel_crtc->base);
11167         }
11168
11169         /* FIXME: add subpixel order */
11170 done:
11171         if (ret && crtc->enabled)
11172                 crtc->mode = *saved_mode;
11173
11174         kfree(saved_mode);
11175         return ret;
11176 }
11177
11178 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11179                                 struct drm_display_mode *mode,
11180                                 int x, int y, struct drm_framebuffer *fb,
11181                                 struct intel_crtc_state *pipe_config,
11182                                 unsigned modeset_pipes,
11183                                 unsigned prepare_pipes,
11184                                 unsigned disable_pipes)
11185 {
11186         int ret;
11187
11188         ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11189                                prepare_pipes, disable_pipes);
11190
11191         if (ret == 0)
11192                 intel_modeset_check_state(crtc->dev);
11193
11194         return ret;
11195 }
11196
11197 static int intel_set_mode(struct drm_crtc *crtc,
11198                           struct drm_display_mode *mode,
11199                           int x, int y, struct drm_framebuffer *fb)
11200 {
11201         struct intel_crtc_state *pipe_config;
11202         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11203
11204         pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11205                                                    &modeset_pipes,
11206                                                    &prepare_pipes,
11207                                                    &disable_pipes);
11208
11209         if (IS_ERR(pipe_config))
11210                 return PTR_ERR(pipe_config);
11211
11212         return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11213                                     modeset_pipes, prepare_pipes,
11214                                     disable_pipes);
11215 }
11216
11217 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11218 {
11219         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11220 }
11221
11222 #undef for_each_intel_crtc_masked
11223
11224 static void intel_set_config_free(struct intel_set_config *config)
11225 {
11226         if (!config)
11227                 return;
11228
11229         kfree(config->save_connector_encoders);
11230         kfree(config->save_encoder_crtcs);
11231         kfree(config->save_crtc_enabled);
11232         kfree(config);
11233 }
11234
11235 static int intel_set_config_save_state(struct drm_device *dev,
11236                                        struct intel_set_config *config)
11237 {
11238         struct drm_crtc *crtc;
11239         struct drm_encoder *encoder;
11240         struct drm_connector *connector;
11241         int count;
11242
11243         config->save_crtc_enabled =
11244                 kcalloc(dev->mode_config.num_crtc,
11245                         sizeof(bool), GFP_KERNEL);
11246         if (!config->save_crtc_enabled)
11247                 return -ENOMEM;
11248
11249         config->save_encoder_crtcs =
11250                 kcalloc(dev->mode_config.num_encoder,
11251                         sizeof(struct drm_crtc *), GFP_KERNEL);
11252         if (!config->save_encoder_crtcs)
11253                 return -ENOMEM;
11254
11255         config->save_connector_encoders =
11256                 kcalloc(dev->mode_config.num_connector,
11257                         sizeof(struct drm_encoder *), GFP_KERNEL);
11258         if (!config->save_connector_encoders)
11259                 return -ENOMEM;
11260
11261         /* Copy data. Note that driver private data is not affected.
11262          * Should anything bad happen only the expected state is
11263          * restored, not the drivers personal bookkeeping.
11264          */
11265         count = 0;
11266         for_each_crtc(dev, crtc) {
11267                 config->save_crtc_enabled[count++] = crtc->enabled;
11268         }
11269
11270         count = 0;
11271         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11272                 config->save_encoder_crtcs[count++] = encoder->crtc;
11273         }
11274
11275         count = 0;
11276         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11277                 config->save_connector_encoders[count++] = connector->encoder;
11278         }
11279
11280         return 0;
11281 }
11282
11283 static void intel_set_config_restore_state(struct drm_device *dev,
11284                                            struct intel_set_config *config)
11285 {
11286         struct intel_crtc *crtc;
11287         struct intel_encoder *encoder;
11288         struct intel_connector *connector;
11289         int count;
11290
11291         count = 0;
11292         for_each_intel_crtc(dev, crtc) {
11293                 crtc->new_enabled = config->save_crtc_enabled[count++];
11294
11295                 if (crtc->new_enabled)
11296                         crtc->new_config = crtc->config;
11297                 else
11298                         crtc->new_config = NULL;
11299         }
11300
11301         count = 0;
11302         for_each_intel_encoder(dev, encoder) {
11303                 encoder->new_crtc =
11304                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11305         }
11306
11307         count = 0;
11308         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11309                 connector->new_encoder =
11310                         to_intel_encoder(config->save_connector_encoders[count++]);
11311         }
11312 }
11313
11314 static bool
11315 is_crtc_connector_off(struct drm_mode_set *set)
11316 {
11317         int i;
11318
11319         if (set->num_connectors == 0)
11320                 return false;
11321
11322         if (WARN_ON(set->connectors == NULL))
11323                 return false;
11324
11325         for (i = 0; i < set->num_connectors; i++)
11326                 if (set->connectors[i]->encoder &&
11327                     set->connectors[i]->encoder->crtc == set->crtc &&
11328                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11329                         return true;
11330
11331         return false;
11332 }
11333
11334 static void
11335 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11336                                       struct intel_set_config *config)
11337 {
11338
11339         /* We should be able to check here if the fb has the same properties
11340          * and then just flip_or_move it */
11341         if (is_crtc_connector_off(set)) {
11342                 config->mode_changed = true;
11343         } else if (set->crtc->primary->fb != set->fb) {
11344                 /*
11345                  * If we have no fb, we can only flip as long as the crtc is
11346                  * active, otherwise we need a full mode set.  The crtc may
11347                  * be active if we've only disabled the primary plane, or
11348                  * in fastboot situations.
11349                  */
11350                 if (set->crtc->primary->fb == NULL) {
11351                         struct intel_crtc *intel_crtc =
11352                                 to_intel_crtc(set->crtc);
11353
11354                         if (intel_crtc->active) {
11355                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11356                                 config->fb_changed = true;
11357                         } else {
11358                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11359                                 config->mode_changed = true;
11360                         }
11361                 } else if (set->fb == NULL) {
11362                         config->mode_changed = true;
11363                 } else if (set->fb->pixel_format !=
11364                            set->crtc->primary->fb->pixel_format) {
11365                         config->mode_changed = true;
11366                 } else {
11367                         config->fb_changed = true;
11368                 }
11369         }
11370
11371         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11372                 config->fb_changed = true;
11373
11374         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11375                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11376                 drm_mode_debug_printmodeline(&set->crtc->mode);
11377                 drm_mode_debug_printmodeline(set->mode);
11378                 config->mode_changed = true;
11379         }
11380
11381         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11382                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11383 }
11384
11385 static int
11386 intel_modeset_stage_output_state(struct drm_device *dev,
11387                                  struct drm_mode_set *set,
11388                                  struct intel_set_config *config)
11389 {
11390         struct intel_connector *connector;
11391         struct intel_encoder *encoder;
11392         struct intel_crtc *crtc;
11393         int ro;
11394
11395         /* The upper layers ensure that we either disable a crtc or have a list
11396          * of connectors. For paranoia, double-check this. */
11397         WARN_ON(!set->fb && (set->num_connectors != 0));
11398         WARN_ON(set->fb && (set->num_connectors == 0));
11399
11400         list_for_each_entry(connector, &dev->mode_config.connector_list,
11401                             base.head) {
11402                 /* Otherwise traverse passed in connector list and get encoders
11403                  * for them. */
11404                 for (ro = 0; ro < set->num_connectors; ro++) {
11405                         if (set->connectors[ro] == &connector->base) {
11406                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11407                                 break;
11408                         }
11409                 }
11410
11411                 /* If we disable the crtc, disable all its connectors. Also, if
11412                  * the connector is on the changing crtc but not on the new
11413                  * connector list, disable it. */
11414                 if ((!set->fb || ro == set->num_connectors) &&
11415                     connector->base.encoder &&
11416                     connector->base.encoder->crtc == set->crtc) {
11417                         connector->new_encoder = NULL;
11418
11419                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11420                                 connector->base.base.id,
11421                                 connector->base.name);
11422                 }
11423
11424
11425                 if (&connector->new_encoder->base != connector->base.encoder) {
11426                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11427                         config->mode_changed = true;
11428                 }
11429         }
11430         /* connector->new_encoder is now updated for all connectors. */
11431
11432         /* Update crtc of enabled connectors. */
11433         list_for_each_entry(connector, &dev->mode_config.connector_list,
11434                             base.head) {
11435                 struct drm_crtc *new_crtc;
11436
11437                 if (!connector->new_encoder)
11438                         continue;
11439
11440                 new_crtc = connector->new_encoder->base.crtc;
11441
11442                 for (ro = 0; ro < set->num_connectors; ro++) {
11443                         if (set->connectors[ro] == &connector->base)
11444                                 new_crtc = set->crtc;
11445                 }
11446
11447                 /* Make sure the new CRTC will work with the encoder */
11448                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11449                                          new_crtc)) {
11450                         return -EINVAL;
11451                 }
11452                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11453
11454                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11455                         connector->base.base.id,
11456                         connector->base.name,
11457                         new_crtc->base.id);
11458         }
11459
11460         /* Check for any encoders that needs to be disabled. */
11461         for_each_intel_encoder(dev, encoder) {
11462                 int num_connectors = 0;
11463                 list_for_each_entry(connector,
11464                                     &dev->mode_config.connector_list,
11465                                     base.head) {
11466                         if (connector->new_encoder == encoder) {
11467                                 WARN_ON(!connector->new_encoder->new_crtc);
11468                                 num_connectors++;
11469                         }
11470                 }
11471
11472                 if (num_connectors == 0)
11473                         encoder->new_crtc = NULL;
11474                 else if (num_connectors > 1)
11475                         return -EINVAL;
11476
11477                 /* Only now check for crtc changes so we don't miss encoders
11478                  * that will be disabled. */
11479                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11480                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11481                         config->mode_changed = true;
11482                 }
11483         }
11484         /* Now we've also updated encoder->new_crtc for all encoders. */
11485         list_for_each_entry(connector, &dev->mode_config.connector_list,
11486                             base.head) {
11487                 if (connector->new_encoder)
11488                         if (connector->new_encoder != connector->encoder)
11489                                 connector->encoder = connector->new_encoder;
11490         }
11491         for_each_intel_crtc(dev, crtc) {
11492                 crtc->new_enabled = false;
11493
11494                 for_each_intel_encoder(dev, encoder) {
11495                         if (encoder->new_crtc == crtc) {
11496                                 crtc->new_enabled = true;
11497                                 break;
11498                         }
11499                 }
11500
11501                 if (crtc->new_enabled != crtc->base.enabled) {
11502                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11503                                       crtc->new_enabled ? "en" : "dis");
11504                         config->mode_changed = true;
11505                 }
11506
11507                 if (crtc->new_enabled)
11508                         crtc->new_config = crtc->config;
11509                 else
11510                         crtc->new_config = NULL;
11511         }
11512
11513         return 0;
11514 }
11515
11516 static void disable_crtc_nofb(struct intel_crtc *crtc)
11517 {
11518         struct drm_device *dev = crtc->base.dev;
11519         struct intel_encoder *encoder;
11520         struct intel_connector *connector;
11521
11522         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11523                       pipe_name(crtc->pipe));
11524
11525         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11526                 if (connector->new_encoder &&
11527                     connector->new_encoder->new_crtc == crtc)
11528                         connector->new_encoder = NULL;
11529         }
11530
11531         for_each_intel_encoder(dev, encoder) {
11532                 if (encoder->new_crtc == crtc)
11533                         encoder->new_crtc = NULL;
11534         }
11535
11536         crtc->new_enabled = false;
11537         crtc->new_config = NULL;
11538 }
11539
11540 static int intel_crtc_set_config(struct drm_mode_set *set)
11541 {
11542         struct drm_device *dev;
11543         struct drm_mode_set save_set;
11544         struct intel_set_config *config;
11545         struct intel_crtc_state *pipe_config;
11546         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11547         int ret;
11548
11549         BUG_ON(!set);
11550         BUG_ON(!set->crtc);
11551         BUG_ON(!set->crtc->helper_private);
11552
11553         /* Enforce sane interface api - has been abused by the fb helper. */
11554         BUG_ON(!set->mode && set->fb);
11555         BUG_ON(set->fb && set->num_connectors == 0);
11556
11557         if (set->fb) {
11558                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11559                                 set->crtc->base.id, set->fb->base.id,
11560                                 (int)set->num_connectors, set->x, set->y);
11561         } else {
11562                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11563         }
11564
11565         dev = set->crtc->dev;
11566
11567         ret = -ENOMEM;
11568         config = kzalloc(sizeof(*config), GFP_KERNEL);
11569         if (!config)
11570                 goto out_config;
11571
11572         ret = intel_set_config_save_state(dev, config);
11573         if (ret)
11574                 goto out_config;
11575
11576         save_set.crtc = set->crtc;
11577         save_set.mode = &set->crtc->mode;
11578         save_set.x = set->crtc->x;
11579         save_set.y = set->crtc->y;
11580         save_set.fb = set->crtc->primary->fb;
11581
11582         /* Compute whether we need a full modeset, only an fb base update or no
11583          * change at all. In the future we might also check whether only the
11584          * mode changed, e.g. for LVDS where we only change the panel fitter in
11585          * such cases. */
11586         intel_set_config_compute_mode_changes(set, config);
11587
11588         ret = intel_modeset_stage_output_state(dev, set, config);
11589         if (ret)
11590                 goto fail;
11591
11592         pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11593                                                    set->fb,
11594                                                    &modeset_pipes,
11595                                                    &prepare_pipes,
11596                                                    &disable_pipes);
11597         if (IS_ERR(pipe_config)) {
11598                 ret = PTR_ERR(pipe_config);
11599                 goto fail;
11600         } else if (pipe_config) {
11601                 if (pipe_config->has_audio !=
11602                     to_intel_crtc(set->crtc)->config->has_audio)
11603                         config->mode_changed = true;
11604
11605                 /*
11606                  * Note we have an issue here with infoframes: current code
11607                  * only updates them on the full mode set path per hw
11608                  * requirements.  So here we should be checking for any
11609                  * required changes and forcing a mode set.
11610                  */
11611         }
11612
11613         /* set_mode will free it in the mode_changed case */
11614         if (!config->mode_changed)
11615                 kfree(pipe_config);
11616
11617         intel_update_pipe_size(to_intel_crtc(set->crtc));
11618
11619         if (config->mode_changed) {
11620                 ret = intel_set_mode_pipes(set->crtc, set->mode,
11621                                            set->x, set->y, set->fb, pipe_config,
11622                                            modeset_pipes, prepare_pipes,
11623                                            disable_pipes);
11624         } else if (config->fb_changed) {
11625                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11626                 struct drm_plane *primary = set->crtc->primary;
11627                 int vdisplay, hdisplay;
11628
11629                 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11630                 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11631                                                    0, 0, hdisplay, vdisplay,
11632                                                    set->x << 16, set->y << 16,
11633                                                    hdisplay << 16, vdisplay << 16);
11634
11635                 /*
11636                  * We need to make sure the primary plane is re-enabled if it
11637                  * has previously been turned off.
11638                  */
11639                 if (!intel_crtc->primary_enabled && ret == 0) {
11640                         WARN_ON(!intel_crtc->active);
11641                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11642                 }
11643
11644                 /*
11645                  * In the fastboot case this may be our only check of the
11646                  * state after boot.  It would be better to only do it on
11647                  * the first update, but we don't have a nice way of doing that
11648                  * (and really, set_config isn't used much for high freq page
11649                  * flipping, so increasing its cost here shouldn't be a big
11650                  * deal).
11651                  */
11652                 if (i915.fastboot && ret == 0)
11653                         intel_modeset_check_state(set->crtc->dev);
11654         }
11655
11656         if (ret) {
11657                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11658                               set->crtc->base.id, ret);
11659 fail:
11660                 intel_set_config_restore_state(dev, config);
11661
11662                 /*
11663                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11664                  * force the pipe off to avoid oopsing in the modeset code
11665                  * due to fb==NULL. This should only happen during boot since
11666                  * we don't yet reconstruct the FB from the hardware state.
11667                  */
11668                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11669                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11670
11671                 /* Try to restore the config */
11672                 if (config->mode_changed &&
11673                     intel_set_mode(save_set.crtc, save_set.mode,
11674                                    save_set.x, save_set.y, save_set.fb))
11675                         DRM_ERROR("failed to restore config after modeset failure\n");
11676         }
11677
11678 out_config:
11679         intel_set_config_free(config);
11680         return ret;
11681 }
11682
11683 static const struct drm_crtc_funcs intel_crtc_funcs = {
11684         .gamma_set = intel_crtc_gamma_set,
11685         .set_config = intel_crtc_set_config,
11686         .destroy = intel_crtc_destroy,
11687         .page_flip = intel_crtc_page_flip,
11688         .atomic_duplicate_state = intel_crtc_duplicate_state,
11689         .atomic_destroy_state = intel_crtc_destroy_state,
11690 };
11691
11692 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11693                                       struct intel_shared_dpll *pll,
11694                                       struct intel_dpll_hw_state *hw_state)
11695 {
11696         uint32_t val;
11697
11698         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11699                 return false;
11700
11701         val = I915_READ(PCH_DPLL(pll->id));
11702         hw_state->dpll = val;
11703         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11704         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11705
11706         return val & DPLL_VCO_ENABLE;
11707 }
11708
11709 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11710                                   struct intel_shared_dpll *pll)
11711 {
11712         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11713         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11714 }
11715
11716 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11717                                 struct intel_shared_dpll *pll)
11718 {
11719         /* PCH refclock must be enabled first */
11720         ibx_assert_pch_refclk_enabled(dev_priv);
11721
11722         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11723
11724         /* Wait for the clocks to stabilize. */
11725         POSTING_READ(PCH_DPLL(pll->id));
11726         udelay(150);
11727
11728         /* The pixel multiplier can only be updated once the
11729          * DPLL is enabled and the clocks are stable.
11730          *
11731          * So write it again.
11732          */
11733         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11734         POSTING_READ(PCH_DPLL(pll->id));
11735         udelay(200);
11736 }
11737
11738 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11739                                  struct intel_shared_dpll *pll)
11740 {
11741         struct drm_device *dev = dev_priv->dev;
11742         struct intel_crtc *crtc;
11743
11744         /* Make sure no transcoder isn't still depending on us. */
11745         for_each_intel_crtc(dev, crtc) {
11746                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11747                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11748         }
11749
11750         I915_WRITE(PCH_DPLL(pll->id), 0);
11751         POSTING_READ(PCH_DPLL(pll->id));
11752         udelay(200);
11753 }
11754
11755 static char *ibx_pch_dpll_names[] = {
11756         "PCH DPLL A",
11757         "PCH DPLL B",
11758 };
11759
11760 static void ibx_pch_dpll_init(struct drm_device *dev)
11761 {
11762         struct drm_i915_private *dev_priv = dev->dev_private;
11763         int i;
11764
11765         dev_priv->num_shared_dpll = 2;
11766
11767         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11768                 dev_priv->shared_dplls[i].id = i;
11769                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11770                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11771                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11772                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11773                 dev_priv->shared_dplls[i].get_hw_state =
11774                         ibx_pch_dpll_get_hw_state;
11775         }
11776 }
11777
11778 static void intel_shared_dpll_init(struct drm_device *dev)
11779 {
11780         struct drm_i915_private *dev_priv = dev->dev_private;
11781
11782         if (HAS_DDI(dev))
11783                 intel_ddi_pll_init(dev);
11784         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11785                 ibx_pch_dpll_init(dev);
11786         else
11787                 dev_priv->num_shared_dpll = 0;
11788
11789         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11790 }
11791
11792 /**
11793  * intel_prepare_plane_fb - Prepare fb for usage on plane
11794  * @plane: drm plane to prepare for
11795  * @fb: framebuffer to prepare for presentation
11796  *
11797  * Prepares a framebuffer for usage on a display plane.  Generally this
11798  * involves pinning the underlying object and updating the frontbuffer tracking
11799  * bits.  Some older platforms need special physical address handling for
11800  * cursor planes.
11801  *
11802  * Returns 0 on success, negative error code on failure.
11803  */
11804 int
11805 intel_prepare_plane_fb(struct drm_plane *plane,
11806                        struct drm_framebuffer *fb)
11807 {
11808         struct drm_device *dev = plane->dev;
11809         struct intel_plane *intel_plane = to_intel_plane(plane);
11810         enum pipe pipe = intel_plane->pipe;
11811         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11812         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11813         unsigned frontbuffer_bits = 0;
11814         int ret = 0;
11815
11816         if (!obj)
11817                 return 0;
11818
11819         switch (plane->type) {
11820         case DRM_PLANE_TYPE_PRIMARY:
11821                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11822                 break;
11823         case DRM_PLANE_TYPE_CURSOR:
11824                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11825                 break;
11826         case DRM_PLANE_TYPE_OVERLAY:
11827                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11828                 break;
11829         }
11830
11831         mutex_lock(&dev->struct_mutex);
11832
11833         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11834             INTEL_INFO(dev)->cursor_needs_physical) {
11835                 int align = IS_I830(dev) ? 16 * 1024 : 256;
11836                 ret = i915_gem_object_attach_phys(obj, align);
11837                 if (ret)
11838                         DRM_DEBUG_KMS("failed to attach phys object\n");
11839         } else {
11840                 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11841         }
11842
11843         if (ret == 0)
11844                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11845
11846         mutex_unlock(&dev->struct_mutex);
11847
11848         return ret;
11849 }
11850
11851 /**
11852  * intel_cleanup_plane_fb - Cleans up an fb after plane use
11853  * @plane: drm plane to clean up for
11854  * @fb: old framebuffer that was on plane
11855  *
11856  * Cleans up a framebuffer that has just been removed from a plane.
11857  */
11858 void
11859 intel_cleanup_plane_fb(struct drm_plane *plane,
11860                        struct drm_framebuffer *fb)
11861 {
11862         struct drm_device *dev = plane->dev;
11863         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11864
11865         if (WARN_ON(!obj))
11866                 return;
11867
11868         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11869             !INTEL_INFO(dev)->cursor_needs_physical) {
11870                 mutex_lock(&dev->struct_mutex);
11871                 intel_unpin_fb_obj(obj);
11872                 mutex_unlock(&dev->struct_mutex);
11873         }
11874 }
11875
11876 static int
11877 intel_check_primary_plane(struct drm_plane *plane,
11878                           struct intel_plane_state *state)
11879 {
11880         struct drm_device *dev = plane->dev;
11881         struct drm_i915_private *dev_priv = dev->dev_private;
11882         struct drm_crtc *crtc = state->base.crtc;
11883         struct intel_crtc *intel_crtc;
11884         struct drm_framebuffer *fb = state->base.fb;
11885         struct drm_rect *dest = &state->dst;
11886         struct drm_rect *src = &state->src;
11887         const struct drm_rect *clip = &state->clip;
11888         int ret;
11889
11890         crtc = crtc ? crtc : plane->crtc;
11891         intel_crtc = to_intel_crtc(crtc);
11892
11893         ret = drm_plane_helper_check_update(plane, crtc, fb,
11894                                             src, dest, clip,
11895                                             DRM_PLANE_HELPER_NO_SCALING,
11896                                             DRM_PLANE_HELPER_NO_SCALING,
11897                                             false, true, &state->visible);
11898         if (ret)
11899                 return ret;
11900
11901         if (intel_crtc->active) {
11902                 intel_crtc->atomic.wait_for_flips = true;
11903
11904                 /*
11905                  * FBC does not work on some platforms for rotated
11906                  * planes, so disable it when rotation is not 0 and
11907                  * update it when rotation is set back to 0.
11908                  *
11909                  * FIXME: This is redundant with the fbc update done in
11910                  * the primary plane enable function except that that
11911                  * one is done too late. We eventually need to unify
11912                  * this.
11913                  */
11914                 if (intel_crtc->primary_enabled &&
11915                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11916                     dev_priv->fbc.plane == intel_crtc->plane &&
11917                     state->base.rotation != BIT(DRM_ROTATE_0)) {
11918                         intel_crtc->atomic.disable_fbc = true;
11919                 }
11920
11921                 if (state->visible) {
11922                         /*
11923                          * BDW signals flip done immediately if the plane
11924                          * is disabled, even if the plane enable is already
11925                          * armed to occur at the next vblank :(
11926                          */
11927                         if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
11928                                 intel_crtc->atomic.wait_vblank = true;
11929                 }
11930
11931                 intel_crtc->atomic.fb_bits |=
11932                         INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11933
11934                 intel_crtc->atomic.update_fbc = true;
11935         }
11936
11937         return 0;
11938 }
11939
11940 static void
11941 intel_commit_primary_plane(struct drm_plane *plane,
11942                            struct intel_plane_state *state)
11943 {
11944         struct drm_crtc *crtc = state->base.crtc;
11945         struct drm_framebuffer *fb = state->base.fb;
11946         struct drm_device *dev = plane->dev;
11947         struct drm_i915_private *dev_priv = dev->dev_private;
11948         struct intel_crtc *intel_crtc;
11949         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11950         struct intel_plane *intel_plane = to_intel_plane(plane);
11951         struct drm_rect *src = &state->src;
11952
11953         crtc = crtc ? crtc : plane->crtc;
11954         intel_crtc = to_intel_crtc(crtc);
11955
11956         plane->fb = fb;
11957         crtc->x = src->x1 >> 16;
11958         crtc->y = src->y1 >> 16;
11959
11960         intel_plane->obj = obj;
11961
11962         if (intel_crtc->active) {
11963                 if (state->visible) {
11964                         /* FIXME: kill this fastboot hack */
11965                         intel_update_pipe_size(intel_crtc);
11966
11967                         intel_crtc->primary_enabled = true;
11968
11969                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11970                                         crtc->x, crtc->y);
11971                 } else {
11972                         /*
11973                          * If clipping results in a non-visible primary plane,
11974                          * we'll disable the primary plane.  Note that this is
11975                          * a bit different than what happens if userspace
11976                          * explicitly disables the plane by passing fb=0
11977                          * because plane->fb still gets set and pinned.
11978                          */
11979                         intel_disable_primary_hw_plane(plane, crtc);
11980                 }
11981         }
11982 }
11983
11984 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
11985 {
11986         struct drm_device *dev = crtc->dev;
11987         struct drm_i915_private *dev_priv = dev->dev_private;
11988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11989         struct intel_plane *intel_plane;
11990         struct drm_plane *p;
11991         unsigned fb_bits = 0;
11992
11993         /* Track fb's for any planes being disabled */
11994         list_for_each_entry(p, &dev->mode_config.plane_list, head) {
11995                 intel_plane = to_intel_plane(p);
11996
11997                 if (intel_crtc->atomic.disabled_planes &
11998                     (1 << drm_plane_index(p))) {
11999                         switch (p->type) {
12000                         case DRM_PLANE_TYPE_PRIMARY:
12001                                 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12002                                 break;
12003                         case DRM_PLANE_TYPE_CURSOR:
12004                                 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12005                                 break;
12006                         case DRM_PLANE_TYPE_OVERLAY:
12007                                 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12008                                 break;
12009                         }
12010
12011                         mutex_lock(&dev->struct_mutex);
12012                         i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12013                         mutex_unlock(&dev->struct_mutex);
12014                 }
12015         }
12016
12017         if (intel_crtc->atomic.wait_for_flips)
12018                 intel_crtc_wait_for_pending_flips(crtc);
12019
12020         if (intel_crtc->atomic.disable_fbc)
12021                 intel_fbc_disable(dev);
12022
12023         if (intel_crtc->atomic.pre_disable_primary)
12024                 intel_pre_disable_primary(crtc);
12025
12026         if (intel_crtc->atomic.update_wm)
12027                 intel_update_watermarks(crtc);
12028
12029         intel_runtime_pm_get(dev_priv);
12030
12031         /* Perform vblank evasion around commit operation */
12032         if (intel_crtc->active)
12033                 intel_crtc->atomic.evade =
12034                         intel_pipe_update_start(intel_crtc,
12035                                                 &intel_crtc->atomic.start_vbl_count);
12036 }
12037
12038 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12039 {
12040         struct drm_device *dev = crtc->dev;
12041         struct drm_i915_private *dev_priv = dev->dev_private;
12042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12043         struct drm_plane *p;
12044
12045         if (intel_crtc->atomic.evade)
12046                 intel_pipe_update_end(intel_crtc,
12047                                       intel_crtc->atomic.start_vbl_count);
12048
12049         intel_runtime_pm_put(dev_priv);
12050
12051         if (intel_crtc->atomic.wait_vblank)
12052                 intel_wait_for_vblank(dev, intel_crtc->pipe);
12053
12054         intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12055
12056         if (intel_crtc->atomic.update_fbc) {
12057                 mutex_lock(&dev->struct_mutex);
12058                 intel_fbc_update(dev);
12059                 mutex_unlock(&dev->struct_mutex);
12060         }
12061
12062         if (intel_crtc->atomic.post_enable_primary)
12063                 intel_post_enable_primary(crtc);
12064
12065         drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12066                 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12067                         intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12068                                                        false, false);
12069
12070         memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12071 }
12072
12073 /**
12074  * intel_plane_destroy - destroy a plane
12075  * @plane: plane to destroy
12076  *
12077  * Common destruction function for all types of planes (primary, cursor,
12078  * sprite).
12079  */
12080 void intel_plane_destroy(struct drm_plane *plane)
12081 {
12082         struct intel_plane *intel_plane = to_intel_plane(plane);
12083         drm_plane_cleanup(plane);
12084         kfree(intel_plane);
12085 }
12086
12087 const struct drm_plane_funcs intel_plane_funcs = {
12088         .update_plane = drm_plane_helper_update,
12089         .disable_plane = drm_plane_helper_disable,
12090         .destroy = intel_plane_destroy,
12091         .set_property = drm_atomic_helper_plane_set_property,
12092         .atomic_get_property = intel_plane_atomic_get_property,
12093         .atomic_set_property = intel_plane_atomic_set_property,
12094         .atomic_duplicate_state = intel_plane_duplicate_state,
12095         .atomic_destroy_state = intel_plane_destroy_state,
12096
12097 };
12098
12099 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12100                                                     int pipe)
12101 {
12102         struct intel_plane *primary;
12103         struct intel_plane_state *state;
12104         const uint32_t *intel_primary_formats;
12105         int num_formats;
12106
12107         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12108         if (primary == NULL)
12109                 return NULL;
12110
12111         state = intel_create_plane_state(&primary->base);
12112         if (!state) {
12113                 kfree(primary);
12114                 return NULL;
12115         }
12116         primary->base.state = &state->base;
12117
12118         primary->can_scale = false;
12119         primary->max_downscale = 1;
12120         primary->pipe = pipe;
12121         primary->plane = pipe;
12122         primary->check_plane = intel_check_primary_plane;
12123         primary->commit_plane = intel_commit_primary_plane;
12124         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12125                 primary->plane = !pipe;
12126
12127         if (INTEL_INFO(dev)->gen <= 3) {
12128                 intel_primary_formats = intel_primary_formats_gen2;
12129                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12130         } else {
12131                 intel_primary_formats = intel_primary_formats_gen4;
12132                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12133         }
12134
12135         drm_universal_plane_init(dev, &primary->base, 0,
12136                                  &intel_plane_funcs,
12137                                  intel_primary_formats, num_formats,
12138                                  DRM_PLANE_TYPE_PRIMARY);
12139
12140         if (INTEL_INFO(dev)->gen >= 4) {
12141                 if (!dev->mode_config.rotation_property)
12142                         dev->mode_config.rotation_property =
12143                                 drm_mode_create_rotation_property(dev,
12144                                                         BIT(DRM_ROTATE_0) |
12145                                                         BIT(DRM_ROTATE_180));
12146                 if (dev->mode_config.rotation_property)
12147                         drm_object_attach_property(&primary->base.base,
12148                                 dev->mode_config.rotation_property,
12149                                 state->base.rotation);
12150         }
12151
12152         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12153
12154         return &primary->base;
12155 }
12156
12157 static int
12158 intel_check_cursor_plane(struct drm_plane *plane,
12159                          struct intel_plane_state *state)
12160 {
12161         struct drm_crtc *crtc = state->base.crtc;
12162         struct drm_device *dev = plane->dev;
12163         struct drm_framebuffer *fb = state->base.fb;
12164         struct drm_rect *dest = &state->dst;
12165         struct drm_rect *src = &state->src;
12166         const struct drm_rect *clip = &state->clip;
12167         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12168         struct intel_crtc *intel_crtc;
12169         unsigned stride;
12170         int ret;
12171
12172         crtc = crtc ? crtc : plane->crtc;
12173         intel_crtc = to_intel_crtc(crtc);
12174
12175         ret = drm_plane_helper_check_update(plane, crtc, fb,
12176                                             src, dest, clip,
12177                                             DRM_PLANE_HELPER_NO_SCALING,
12178                                             DRM_PLANE_HELPER_NO_SCALING,
12179                                             true, true, &state->visible);
12180         if (ret)
12181                 return ret;
12182
12183
12184         /* if we want to turn off the cursor ignore width and height */
12185         if (!obj)
12186                 goto finish;
12187
12188         /* Check for which cursor types we support */
12189         if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12190                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12191                           state->base.crtc_w, state->base.crtc_h);
12192                 return -EINVAL;
12193         }
12194
12195         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12196         if (obj->base.size < stride * state->base.crtc_h) {
12197                 DRM_DEBUG_KMS("buffer is too small\n");
12198                 return -ENOMEM;
12199         }
12200
12201         /* we only need to pin inside GTT if cursor is non-phy */
12202         mutex_lock(&dev->struct_mutex);
12203         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12204                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12205                 ret = -EINVAL;
12206         }
12207         mutex_unlock(&dev->struct_mutex);
12208
12209 finish:
12210         if (intel_crtc->active) {
12211                 if (intel_crtc->cursor_width != state->base.crtc_w)
12212                         intel_crtc->atomic.update_wm = true;
12213
12214                 intel_crtc->atomic.fb_bits |=
12215                         INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12216         }
12217
12218         return ret;
12219 }
12220
12221 static void
12222 intel_commit_cursor_plane(struct drm_plane *plane,
12223                           struct intel_plane_state *state)
12224 {
12225         struct drm_crtc *crtc = state->base.crtc;
12226         struct drm_device *dev = plane->dev;
12227         struct intel_crtc *intel_crtc;
12228         struct intel_plane *intel_plane = to_intel_plane(plane);
12229         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12230         uint32_t addr;
12231
12232         crtc = crtc ? crtc : plane->crtc;
12233         intel_crtc = to_intel_crtc(crtc);
12234
12235         plane->fb = state->base.fb;
12236         crtc->cursor_x = state->base.crtc_x;
12237         crtc->cursor_y = state->base.crtc_y;
12238
12239         intel_plane->obj = obj;
12240
12241         if (intel_crtc->cursor_bo == obj)
12242                 goto update;
12243
12244         if (!obj)
12245                 addr = 0;
12246         else if (!INTEL_INFO(dev)->cursor_needs_physical)
12247                 addr = i915_gem_obj_ggtt_offset(obj);
12248         else
12249                 addr = obj->phys_handle->busaddr;
12250
12251         intel_crtc->cursor_addr = addr;
12252         intel_crtc->cursor_bo = obj;
12253 update:
12254         intel_crtc->cursor_width = state->base.crtc_w;
12255         intel_crtc->cursor_height = state->base.crtc_h;
12256
12257         if (intel_crtc->active)
12258                 intel_crtc_update_cursor(crtc, state->visible);
12259 }
12260
12261 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12262                                                    int pipe)
12263 {
12264         struct intel_plane *cursor;
12265         struct intel_plane_state *state;
12266
12267         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12268         if (cursor == NULL)
12269                 return NULL;
12270
12271         state = intel_create_plane_state(&cursor->base);
12272         if (!state) {
12273                 kfree(cursor);
12274                 return NULL;
12275         }
12276         cursor->base.state = &state->base;
12277
12278         cursor->can_scale = false;
12279         cursor->max_downscale = 1;
12280         cursor->pipe = pipe;
12281         cursor->plane = pipe;
12282         cursor->check_plane = intel_check_cursor_plane;
12283         cursor->commit_plane = intel_commit_cursor_plane;
12284
12285         drm_universal_plane_init(dev, &cursor->base, 0,
12286                                  &intel_plane_funcs,
12287                                  intel_cursor_formats,
12288                                  ARRAY_SIZE(intel_cursor_formats),
12289                                  DRM_PLANE_TYPE_CURSOR);
12290
12291         if (INTEL_INFO(dev)->gen >= 4) {
12292                 if (!dev->mode_config.rotation_property)
12293                         dev->mode_config.rotation_property =
12294                                 drm_mode_create_rotation_property(dev,
12295                                                         BIT(DRM_ROTATE_0) |
12296                                                         BIT(DRM_ROTATE_180));
12297                 if (dev->mode_config.rotation_property)
12298                         drm_object_attach_property(&cursor->base.base,
12299                                 dev->mode_config.rotation_property,
12300                                 state->base.rotation);
12301         }
12302
12303         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12304
12305         return &cursor->base;
12306 }
12307
12308 static void intel_crtc_init(struct drm_device *dev, int pipe)
12309 {
12310         struct drm_i915_private *dev_priv = dev->dev_private;
12311         struct intel_crtc *intel_crtc;
12312         struct intel_crtc_state *crtc_state = NULL;
12313         struct drm_plane *primary = NULL;
12314         struct drm_plane *cursor = NULL;
12315         int i, ret;
12316
12317         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12318         if (intel_crtc == NULL)
12319                 return;
12320
12321         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12322         if (!crtc_state)
12323                 goto fail;
12324         intel_crtc_set_state(intel_crtc, crtc_state);
12325
12326         primary = intel_primary_plane_create(dev, pipe);
12327         if (!primary)
12328                 goto fail;
12329
12330         cursor = intel_cursor_plane_create(dev, pipe);
12331         if (!cursor)
12332                 goto fail;
12333
12334         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12335                                         cursor, &intel_crtc_funcs);
12336         if (ret)
12337                 goto fail;
12338
12339         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12340         for (i = 0; i < 256; i++) {
12341                 intel_crtc->lut_r[i] = i;
12342                 intel_crtc->lut_g[i] = i;
12343                 intel_crtc->lut_b[i] = i;
12344         }
12345
12346         /*
12347          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12348          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12349          */
12350         intel_crtc->pipe = pipe;
12351         intel_crtc->plane = pipe;
12352         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12353                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12354                 intel_crtc->plane = !pipe;
12355         }
12356
12357         intel_crtc->cursor_base = ~0;
12358         intel_crtc->cursor_cntl = ~0;
12359         intel_crtc->cursor_size = ~0;
12360
12361         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12362                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12363         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12364         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12365
12366         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12367
12368         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12369
12370         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12371         return;
12372
12373 fail:
12374         if (primary)
12375                 drm_plane_cleanup(primary);
12376         if (cursor)
12377                 drm_plane_cleanup(cursor);
12378         kfree(crtc_state);
12379         kfree(intel_crtc);
12380 }
12381
12382 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12383 {
12384         struct drm_encoder *encoder = connector->base.encoder;
12385         struct drm_device *dev = connector->base.dev;
12386
12387         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12388
12389         if (!encoder || WARN_ON(!encoder->crtc))
12390                 return INVALID_PIPE;
12391
12392         return to_intel_crtc(encoder->crtc)->pipe;
12393 }
12394
12395 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12396                                 struct drm_file *file)
12397 {
12398         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12399         struct drm_crtc *drmmode_crtc;
12400         struct intel_crtc *crtc;
12401
12402         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12403                 return -ENODEV;
12404
12405         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12406
12407         if (!drmmode_crtc) {
12408                 DRM_ERROR("no such CRTC id\n");
12409                 return -ENOENT;
12410         }
12411
12412         crtc = to_intel_crtc(drmmode_crtc);
12413         pipe_from_crtc_id->pipe = crtc->pipe;
12414
12415         return 0;
12416 }
12417
12418 static int intel_encoder_clones(struct intel_encoder *encoder)
12419 {
12420         struct drm_device *dev = encoder->base.dev;
12421         struct intel_encoder *source_encoder;
12422         int index_mask = 0;
12423         int entry = 0;
12424
12425         for_each_intel_encoder(dev, source_encoder) {
12426                 if (encoders_cloneable(encoder, source_encoder))
12427                         index_mask |= (1 << entry);
12428
12429                 entry++;
12430         }
12431
12432         return index_mask;
12433 }
12434
12435 static bool has_edp_a(struct drm_device *dev)
12436 {
12437         struct drm_i915_private *dev_priv = dev->dev_private;
12438
12439         if (!IS_MOBILE(dev))
12440                 return false;
12441
12442         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12443                 return false;
12444
12445         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12446                 return false;
12447
12448         return true;
12449 }
12450
12451 static bool intel_crt_present(struct drm_device *dev)
12452 {
12453         struct drm_i915_private *dev_priv = dev->dev_private;
12454
12455         if (INTEL_INFO(dev)->gen >= 9)
12456                 return false;
12457
12458         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12459                 return false;
12460
12461         if (IS_CHERRYVIEW(dev))
12462                 return false;
12463
12464         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12465                 return false;
12466
12467         return true;
12468 }
12469
12470 static void intel_setup_outputs(struct drm_device *dev)
12471 {
12472         struct drm_i915_private *dev_priv = dev->dev_private;
12473         struct intel_encoder *encoder;
12474         struct drm_connector *connector;
12475         bool dpd_is_edp = false;
12476
12477         intel_lvds_init(dev);
12478
12479         if (intel_crt_present(dev))
12480                 intel_crt_init(dev);
12481
12482         if (HAS_DDI(dev)) {
12483                 int found;
12484
12485                 /* Haswell uses DDI functions to detect digital outputs */
12486                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12487                 /* DDI A only supports eDP */
12488                 if (found)
12489                         intel_ddi_init(dev, PORT_A);
12490
12491                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12492                  * register */
12493                 found = I915_READ(SFUSE_STRAP);
12494
12495                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12496                         intel_ddi_init(dev, PORT_B);
12497                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12498                         intel_ddi_init(dev, PORT_C);
12499                 if (found & SFUSE_STRAP_DDID_DETECTED)
12500                         intel_ddi_init(dev, PORT_D);
12501         } else if (HAS_PCH_SPLIT(dev)) {
12502                 int found;
12503                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12504
12505                 if (has_edp_a(dev))
12506                         intel_dp_init(dev, DP_A, PORT_A);
12507
12508                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12509                         /* PCH SDVOB multiplex with HDMIB */
12510                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12511                         if (!found)
12512                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12513                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12514                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12515                 }
12516
12517                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12518                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12519
12520                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12521                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12522
12523                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12524                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12525
12526                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12527                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12528         } else if (IS_VALLEYVIEW(dev)) {
12529                 /*
12530                  * The DP_DETECTED bit is the latched state of the DDC
12531                  * SDA pin at boot. However since eDP doesn't require DDC
12532                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12533                  * eDP ports may have been muxed to an alternate function.
12534                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12535                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12536                  * detect eDP ports.
12537                  */
12538                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12539                     !intel_dp_is_edp(dev, PORT_B))
12540                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12541                                         PORT_B);
12542                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12543                     intel_dp_is_edp(dev, PORT_B))
12544                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12545
12546                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12547                     !intel_dp_is_edp(dev, PORT_C))
12548                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12549                                         PORT_C);
12550                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12551                     intel_dp_is_edp(dev, PORT_C))
12552                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12553
12554                 if (IS_CHERRYVIEW(dev)) {
12555                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12556                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12557                                                 PORT_D);
12558                         /* eDP not supported on port D, so don't check VBT */
12559                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12560                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12561                 }
12562
12563                 intel_dsi_init(dev);
12564         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12565                 bool found = false;
12566
12567                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12568                         DRM_DEBUG_KMS("probing SDVOB\n");
12569                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12570                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12571                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12572                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12573                         }
12574
12575                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12576                                 intel_dp_init(dev, DP_B, PORT_B);
12577                 }
12578
12579                 /* Before G4X SDVOC doesn't have its own detect register */
12580
12581                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12582                         DRM_DEBUG_KMS("probing SDVOC\n");
12583                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12584                 }
12585
12586                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12587
12588                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12589                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12590                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12591                         }
12592                         if (SUPPORTS_INTEGRATED_DP(dev))
12593                                 intel_dp_init(dev, DP_C, PORT_C);
12594                 }
12595
12596                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12597                     (I915_READ(DP_D) & DP_DETECTED))
12598                         intel_dp_init(dev, DP_D, PORT_D);
12599         } else if (IS_GEN2(dev))
12600                 intel_dvo_init(dev);
12601
12602         if (SUPPORTS_TV(dev))
12603                 intel_tv_init(dev);
12604
12605         /*
12606          * FIXME:  We don't have full atomic support yet, but we want to be
12607          * able to enable/test plane updates via the atomic interface in the
12608          * meantime.  However as soon as we flip DRIVER_ATOMIC on, the DRM core
12609          * will take some atomic codepaths to lookup properties during
12610          * drmModeGetConnector() that unconditionally dereference
12611          * connector->state.
12612          *
12613          * We create a dummy connector state here for each connector to ensure
12614          * the DRM core doesn't try to dereference a NULL connector->state.
12615          * The actual connector properties will never be updated or contain
12616          * useful information, but since we're doing this specifically for
12617          * testing/debug of the plane operations (and only when a specific
12618          * kernel module option is given), that shouldn't really matter.
12619          *
12620          * Once atomic support for crtc's + connectors lands, this loop should
12621          * be removed since we'll be setting up real connector state, which
12622          * will contain Intel-specific properties.
12623          */
12624         if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12625                 list_for_each_entry(connector,
12626                                     &dev->mode_config.connector_list,
12627                                     head) {
12628                         if (!WARN_ON(connector->state)) {
12629                                 connector->state =
12630                                         kzalloc(sizeof(*connector->state),
12631                                                 GFP_KERNEL);
12632                         }
12633                 }
12634         }
12635
12636         intel_psr_init(dev);
12637
12638         for_each_intel_encoder(dev, encoder) {
12639                 encoder->base.possible_crtcs = encoder->crtc_mask;
12640                 encoder->base.possible_clones =
12641                         intel_encoder_clones(encoder);
12642         }
12643
12644         intel_init_pch_refclk(dev);
12645
12646         drm_helper_move_panel_connectors_to_head(dev);
12647 }
12648
12649 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12650 {
12651         struct drm_device *dev = fb->dev;
12652         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12653
12654         drm_framebuffer_cleanup(fb);
12655         mutex_lock(&dev->struct_mutex);
12656         WARN_ON(!intel_fb->obj->framebuffer_references--);
12657         drm_gem_object_unreference(&intel_fb->obj->base);
12658         mutex_unlock(&dev->struct_mutex);
12659         kfree(intel_fb);
12660 }
12661
12662 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12663                                                 struct drm_file *file,
12664                                                 unsigned int *handle)
12665 {
12666         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12667         struct drm_i915_gem_object *obj = intel_fb->obj;
12668
12669         return drm_gem_handle_create(file, &obj->base, handle);
12670 }
12671
12672 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12673         .destroy = intel_user_framebuffer_destroy,
12674         .create_handle = intel_user_framebuffer_create_handle,
12675 };
12676
12677 static int intel_framebuffer_init(struct drm_device *dev,
12678                                   struct intel_framebuffer *intel_fb,
12679                                   struct drm_mode_fb_cmd2 *mode_cmd,
12680                                   struct drm_i915_gem_object *obj)
12681 {
12682         int aligned_height;
12683         int pitch_limit;
12684         int ret;
12685
12686         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12687
12688         if (obj->tiling_mode == I915_TILING_Y) {
12689                 DRM_DEBUG("hardware does not support tiling Y\n");
12690                 return -EINVAL;
12691         }
12692
12693         if (mode_cmd->pitches[0] & 63) {
12694                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12695                           mode_cmd->pitches[0]);
12696                 return -EINVAL;
12697         }
12698
12699         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12700                 pitch_limit = 32*1024;
12701         } else if (INTEL_INFO(dev)->gen >= 4) {
12702                 if (obj->tiling_mode)
12703                         pitch_limit = 16*1024;
12704                 else
12705                         pitch_limit = 32*1024;
12706         } else if (INTEL_INFO(dev)->gen >= 3) {
12707                 if (obj->tiling_mode)
12708                         pitch_limit = 8*1024;
12709                 else
12710                         pitch_limit = 16*1024;
12711         } else
12712                 /* XXX DSPC is limited to 4k tiled */
12713                 pitch_limit = 8*1024;
12714
12715         if (mode_cmd->pitches[0] > pitch_limit) {
12716                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12717                           obj->tiling_mode ? "tiled" : "linear",
12718                           mode_cmd->pitches[0], pitch_limit);
12719                 return -EINVAL;
12720         }
12721
12722         if (obj->tiling_mode != I915_TILING_NONE &&
12723             mode_cmd->pitches[0] != obj->stride) {
12724                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12725                           mode_cmd->pitches[0], obj->stride);
12726                 return -EINVAL;
12727         }
12728
12729         /* Reject formats not supported by any plane early. */
12730         switch (mode_cmd->pixel_format) {
12731         case DRM_FORMAT_C8:
12732         case DRM_FORMAT_RGB565:
12733         case DRM_FORMAT_XRGB8888:
12734         case DRM_FORMAT_ARGB8888:
12735                 break;
12736         case DRM_FORMAT_XRGB1555:
12737         case DRM_FORMAT_ARGB1555:
12738                 if (INTEL_INFO(dev)->gen > 3) {
12739                         DRM_DEBUG("unsupported pixel format: %s\n",
12740                                   drm_get_format_name(mode_cmd->pixel_format));
12741                         return -EINVAL;
12742                 }
12743                 break;
12744         case DRM_FORMAT_XBGR8888:
12745         case DRM_FORMAT_ABGR8888:
12746         case DRM_FORMAT_XRGB2101010:
12747         case DRM_FORMAT_ARGB2101010:
12748         case DRM_FORMAT_XBGR2101010:
12749         case DRM_FORMAT_ABGR2101010:
12750                 if (INTEL_INFO(dev)->gen < 4) {
12751                         DRM_DEBUG("unsupported pixel format: %s\n",
12752                                   drm_get_format_name(mode_cmd->pixel_format));
12753                         return -EINVAL;
12754                 }
12755                 break;
12756         case DRM_FORMAT_YUYV:
12757         case DRM_FORMAT_UYVY:
12758         case DRM_FORMAT_YVYU:
12759         case DRM_FORMAT_VYUY:
12760                 if (INTEL_INFO(dev)->gen < 5) {
12761                         DRM_DEBUG("unsupported pixel format: %s\n",
12762                                   drm_get_format_name(mode_cmd->pixel_format));
12763                         return -EINVAL;
12764                 }
12765                 break;
12766         default:
12767                 DRM_DEBUG("unsupported pixel format: %s\n",
12768                           drm_get_format_name(mode_cmd->pixel_format));
12769                 return -EINVAL;
12770         }
12771
12772         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12773         if (mode_cmd->offsets[0] != 0)
12774                 return -EINVAL;
12775
12776         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12777                                                obj->tiling_mode);
12778         /* FIXME drm helper for size checks (especially planar formats)? */
12779         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12780                 return -EINVAL;
12781
12782         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12783         intel_fb->obj = obj;
12784         intel_fb->obj->framebuffer_references++;
12785
12786         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12787         if (ret) {
12788                 DRM_ERROR("framebuffer init failed %d\n", ret);
12789                 return ret;
12790         }
12791
12792         return 0;
12793 }
12794
12795 static struct drm_framebuffer *
12796 intel_user_framebuffer_create(struct drm_device *dev,
12797                               struct drm_file *filp,
12798                               struct drm_mode_fb_cmd2 *mode_cmd)
12799 {
12800         struct drm_i915_gem_object *obj;
12801
12802         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12803                                                 mode_cmd->handles[0]));
12804         if (&obj->base == NULL)
12805                 return ERR_PTR(-ENOENT);
12806
12807         return intel_framebuffer_create(dev, mode_cmd, obj);
12808 }
12809
12810 #ifndef CONFIG_DRM_I915_FBDEV
12811 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12812 {
12813 }
12814 #endif
12815
12816 static const struct drm_mode_config_funcs intel_mode_funcs = {
12817         .fb_create = intel_user_framebuffer_create,
12818         .output_poll_changed = intel_fbdev_output_poll_changed,
12819         .atomic_check = intel_atomic_check,
12820         .atomic_commit = intel_atomic_commit,
12821 };
12822
12823 /* Set up chip specific display functions */
12824 static void intel_init_display(struct drm_device *dev)
12825 {
12826         struct drm_i915_private *dev_priv = dev->dev_private;
12827
12828         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12829                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12830         else if (IS_CHERRYVIEW(dev))
12831                 dev_priv->display.find_dpll = chv_find_best_dpll;
12832         else if (IS_VALLEYVIEW(dev))
12833                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12834         else if (IS_PINEVIEW(dev))
12835                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12836         else
12837                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12838
12839         if (INTEL_INFO(dev)->gen >= 9) {
12840                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12841                 dev_priv->display.get_initial_plane_config =
12842                         skylake_get_initial_plane_config;
12843                 dev_priv->display.crtc_compute_clock =
12844                         haswell_crtc_compute_clock;
12845                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12846                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12847                 dev_priv->display.off = ironlake_crtc_off;
12848                 dev_priv->display.update_primary_plane =
12849                         skylake_update_primary_plane;
12850         } else if (HAS_DDI(dev)) {
12851                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12852                 dev_priv->display.get_initial_plane_config =
12853                         ironlake_get_initial_plane_config;
12854                 dev_priv->display.crtc_compute_clock =
12855                         haswell_crtc_compute_clock;
12856                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12857                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12858                 dev_priv->display.off = ironlake_crtc_off;
12859                 dev_priv->display.update_primary_plane =
12860                         ironlake_update_primary_plane;
12861         } else if (HAS_PCH_SPLIT(dev)) {
12862                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12863                 dev_priv->display.get_initial_plane_config =
12864                         ironlake_get_initial_plane_config;
12865                 dev_priv->display.crtc_compute_clock =
12866                         ironlake_crtc_compute_clock;
12867                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12868                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12869                 dev_priv->display.off = ironlake_crtc_off;
12870                 dev_priv->display.update_primary_plane =
12871                         ironlake_update_primary_plane;
12872         } else if (IS_VALLEYVIEW(dev)) {
12873                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12874                 dev_priv->display.get_initial_plane_config =
12875                         i9xx_get_initial_plane_config;
12876                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12877                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12878                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12879                 dev_priv->display.off = i9xx_crtc_off;
12880                 dev_priv->display.update_primary_plane =
12881                         i9xx_update_primary_plane;
12882         } else {
12883                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12884                 dev_priv->display.get_initial_plane_config =
12885                         i9xx_get_initial_plane_config;
12886                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12887                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12888                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12889                 dev_priv->display.off = i9xx_crtc_off;
12890                 dev_priv->display.update_primary_plane =
12891                         i9xx_update_primary_plane;
12892         }
12893
12894         /* Returns the core display clock speed */
12895         if (IS_VALLEYVIEW(dev))
12896                 dev_priv->display.get_display_clock_speed =
12897                         valleyview_get_display_clock_speed;
12898         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12899                 dev_priv->display.get_display_clock_speed =
12900                         i945_get_display_clock_speed;
12901         else if (IS_I915G(dev))
12902                 dev_priv->display.get_display_clock_speed =
12903                         i915_get_display_clock_speed;
12904         else if (IS_I945GM(dev) || IS_845G(dev))
12905                 dev_priv->display.get_display_clock_speed =
12906                         i9xx_misc_get_display_clock_speed;
12907         else if (IS_PINEVIEW(dev))
12908                 dev_priv->display.get_display_clock_speed =
12909                         pnv_get_display_clock_speed;
12910         else if (IS_I915GM(dev))
12911                 dev_priv->display.get_display_clock_speed =
12912                         i915gm_get_display_clock_speed;
12913         else if (IS_I865G(dev))
12914                 dev_priv->display.get_display_clock_speed =
12915                         i865_get_display_clock_speed;
12916         else if (IS_I85X(dev))
12917                 dev_priv->display.get_display_clock_speed =
12918                         i855_get_display_clock_speed;
12919         else /* 852, 830 */
12920                 dev_priv->display.get_display_clock_speed =
12921                         i830_get_display_clock_speed;
12922
12923         if (IS_GEN5(dev)) {
12924                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12925         } else if (IS_GEN6(dev)) {
12926                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12927         } else if (IS_IVYBRIDGE(dev)) {
12928                 /* FIXME: detect B0+ stepping and use auto training */
12929                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12930                 dev_priv->display.modeset_global_resources =
12931                         ivb_modeset_global_resources;
12932         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12933                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12934         } else if (IS_VALLEYVIEW(dev)) {
12935                 dev_priv->display.modeset_global_resources =
12936                         valleyview_modeset_global_resources;
12937         }
12938
12939         /* Default just returns -ENODEV to indicate unsupported */
12940         dev_priv->display.queue_flip = intel_default_queue_flip;
12941
12942         switch (INTEL_INFO(dev)->gen) {
12943         case 2:
12944                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12945                 break;
12946
12947         case 3:
12948                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12949                 break;
12950
12951         case 4:
12952         case 5:
12953                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12954                 break;
12955
12956         case 6:
12957                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12958                 break;
12959         case 7:
12960         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12961                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12962                 break;
12963         case 9:
12964                 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12965                 break;
12966         }
12967
12968         intel_panel_init_backlight_funcs(dev);
12969
12970         mutex_init(&dev_priv->pps_mutex);
12971 }
12972
12973 /*
12974  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12975  * resume, or other times.  This quirk makes sure that's the case for
12976  * affected systems.
12977  */
12978 static void quirk_pipea_force(struct drm_device *dev)
12979 {
12980         struct drm_i915_private *dev_priv = dev->dev_private;
12981
12982         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12983         DRM_INFO("applying pipe a force quirk\n");
12984 }
12985
12986 static void quirk_pipeb_force(struct drm_device *dev)
12987 {
12988         struct drm_i915_private *dev_priv = dev->dev_private;
12989
12990         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12991         DRM_INFO("applying pipe b force quirk\n");
12992 }
12993
12994 /*
12995  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12996  */
12997 static void quirk_ssc_force_disable(struct drm_device *dev)
12998 {
12999         struct drm_i915_private *dev_priv = dev->dev_private;
13000         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13001         DRM_INFO("applying lvds SSC disable quirk\n");
13002 }
13003
13004 /*
13005  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13006  * brightness value
13007  */
13008 static void quirk_invert_brightness(struct drm_device *dev)
13009 {
13010         struct drm_i915_private *dev_priv = dev->dev_private;
13011         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13012         DRM_INFO("applying inverted panel brightness quirk\n");
13013 }
13014
13015 /* Some VBT's incorrectly indicate no backlight is present */
13016 static void quirk_backlight_present(struct drm_device *dev)
13017 {
13018         struct drm_i915_private *dev_priv = dev->dev_private;
13019         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13020         DRM_INFO("applying backlight present quirk\n");
13021 }
13022
13023 struct intel_quirk {
13024         int device;
13025         int subsystem_vendor;
13026         int subsystem_device;
13027         void (*hook)(struct drm_device *dev);
13028 };
13029
13030 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13031 struct intel_dmi_quirk {
13032         void (*hook)(struct drm_device *dev);
13033         const struct dmi_system_id (*dmi_id_list)[];
13034 };
13035
13036 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13037 {
13038         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13039         return 1;
13040 }
13041
13042 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13043         {
13044                 .dmi_id_list = &(const struct dmi_system_id[]) {
13045                         {
13046                                 .callback = intel_dmi_reverse_brightness,
13047                                 .ident = "NCR Corporation",
13048                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13049                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
13050                                 },
13051                         },
13052                         { }  /* terminating entry */
13053                 },
13054                 .hook = quirk_invert_brightness,
13055         },
13056 };
13057
13058 static struct intel_quirk intel_quirks[] = {
13059         /* HP Mini needs pipe A force quirk (LP: #322104) */
13060         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13061
13062         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13063         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13064
13065         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13066         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13067
13068         /* 830 needs to leave pipe A & dpll A up */
13069         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13070
13071         /* 830 needs to leave pipe B & dpll B up */
13072         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13073
13074         /* Lenovo U160 cannot use SSC on LVDS */
13075         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13076
13077         /* Sony Vaio Y cannot use SSC on LVDS */
13078         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13079
13080         /* Acer Aspire 5734Z must invert backlight brightness */
13081         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13082
13083         /* Acer/eMachines G725 */
13084         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13085
13086         /* Acer/eMachines e725 */
13087         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13088
13089         /* Acer/Packard Bell NCL20 */
13090         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13091
13092         /* Acer Aspire 4736Z */
13093         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13094
13095         /* Acer Aspire 5336 */
13096         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13097
13098         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13099         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13100
13101         /* Acer C720 Chromebook (Core i3 4005U) */
13102         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13103
13104         /* Apple Macbook 2,1 (Core 2 T7400) */
13105         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13106
13107         /* Toshiba CB35 Chromebook (Celeron 2955U) */
13108         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13109
13110         /* HP Chromebook 14 (Celeron 2955U) */
13111         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13112
13113         /* Dell Chromebook 11 */
13114         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13115 };
13116
13117 static void intel_init_quirks(struct drm_device *dev)
13118 {
13119         struct pci_dev *d = dev->pdev;
13120         int i;
13121
13122         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13123                 struct intel_quirk *q = &intel_quirks[i];
13124
13125                 if (d->device == q->device &&
13126                     (d->subsystem_vendor == q->subsystem_vendor ||
13127                      q->subsystem_vendor == PCI_ANY_ID) &&
13128                     (d->subsystem_device == q->subsystem_device ||
13129                      q->subsystem_device == PCI_ANY_ID))
13130                         q->hook(dev);
13131         }
13132         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13133                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13134                         intel_dmi_quirks[i].hook(dev);
13135         }
13136 }
13137
13138 /* Disable the VGA plane that we never use */
13139 static void i915_disable_vga(struct drm_device *dev)
13140 {
13141         struct drm_i915_private *dev_priv = dev->dev_private;
13142         u8 sr1;
13143         u32 vga_reg = i915_vgacntrl_reg(dev);
13144
13145         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13146         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13147         outb(SR01, VGA_SR_INDEX);
13148         sr1 = inb(VGA_SR_DATA);
13149         outb(sr1 | 1<<5, VGA_SR_DATA);
13150         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13151         udelay(300);
13152
13153         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13154         POSTING_READ(vga_reg);
13155 }
13156
13157 void intel_modeset_init_hw(struct drm_device *dev)
13158 {
13159         intel_prepare_ddi(dev);
13160
13161         if (IS_VALLEYVIEW(dev))
13162                 vlv_update_cdclk(dev);
13163
13164         intel_init_clock_gating(dev);
13165
13166         intel_enable_gt_powersave(dev);
13167 }
13168
13169 void intel_modeset_init(struct drm_device *dev)
13170 {
13171         struct drm_i915_private *dev_priv = dev->dev_private;
13172         int sprite, ret;
13173         enum pipe pipe;
13174         struct intel_crtc *crtc;
13175
13176         drm_mode_config_init(dev);
13177
13178         dev->mode_config.min_width = 0;
13179         dev->mode_config.min_height = 0;
13180
13181         dev->mode_config.preferred_depth = 24;
13182         dev->mode_config.prefer_shadow = 1;
13183
13184         dev->mode_config.funcs = &intel_mode_funcs;
13185
13186         intel_init_quirks(dev);
13187
13188         intel_init_pm(dev);
13189
13190         if (INTEL_INFO(dev)->num_pipes == 0)
13191                 return;
13192
13193         intel_init_display(dev);
13194         intel_init_audio(dev);
13195
13196         if (IS_GEN2(dev)) {
13197                 dev->mode_config.max_width = 2048;
13198                 dev->mode_config.max_height = 2048;
13199         } else if (IS_GEN3(dev)) {
13200                 dev->mode_config.max_width = 4096;
13201                 dev->mode_config.max_height = 4096;
13202         } else {
13203                 dev->mode_config.max_width = 8192;
13204                 dev->mode_config.max_height = 8192;
13205         }
13206
13207         if (IS_845G(dev) || IS_I865G(dev)) {
13208                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13209                 dev->mode_config.cursor_height = 1023;
13210         } else if (IS_GEN2(dev)) {
13211                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13212                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13213         } else {
13214                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13215                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13216         }
13217
13218         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13219
13220         DRM_DEBUG_KMS("%d display pipe%s available.\n",
13221                       INTEL_INFO(dev)->num_pipes,
13222                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13223
13224         for_each_pipe(dev_priv, pipe) {
13225                 intel_crtc_init(dev, pipe);
13226                 for_each_sprite(pipe, sprite) {
13227                         ret = intel_plane_init(dev, pipe, sprite);
13228                         if (ret)
13229                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13230                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
13231                 }
13232         }
13233
13234         intel_init_dpio(dev);
13235
13236         intel_shared_dpll_init(dev);
13237
13238         /* Just disable it once at startup */
13239         i915_disable_vga(dev);
13240         intel_setup_outputs(dev);
13241
13242         /* Just in case the BIOS is doing something questionable. */
13243         intel_fbc_disable(dev);
13244
13245         drm_modeset_lock_all(dev);
13246         intel_modeset_setup_hw_state(dev, false);
13247         drm_modeset_unlock_all(dev);
13248
13249         for_each_intel_crtc(dev, crtc) {
13250                 if (!crtc->active)
13251                         continue;
13252
13253                 /*
13254                  * Note that reserving the BIOS fb up front prevents us
13255                  * from stuffing other stolen allocations like the ring
13256                  * on top.  This prevents some ugliness at boot time, and
13257                  * can even allow for smooth boot transitions if the BIOS
13258                  * fb is large enough for the active pipe configuration.
13259                  */
13260                 if (dev_priv->display.get_initial_plane_config) {
13261                         dev_priv->display.get_initial_plane_config(crtc,
13262                                                            &crtc->plane_config);
13263                         /*
13264                          * If the fb is shared between multiple heads, we'll
13265                          * just get the first one.
13266                          */
13267                         intel_find_plane_obj(crtc, &crtc->plane_config);
13268                 }
13269         }
13270 }
13271
13272 static void intel_enable_pipe_a(struct drm_device *dev)
13273 {
13274         struct intel_connector *connector;
13275         struct drm_connector *crt = NULL;
13276         struct intel_load_detect_pipe load_detect_temp;
13277         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13278
13279         /* We can't just switch on the pipe A, we need to set things up with a
13280          * proper mode and output configuration. As a gross hack, enable pipe A
13281          * by enabling the load detect pipe once. */
13282         list_for_each_entry(connector,
13283                             &dev->mode_config.connector_list,
13284                             base.head) {
13285                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13286                         crt = &connector->base;
13287                         break;
13288                 }
13289         }
13290
13291         if (!crt)
13292                 return;
13293
13294         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13295                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13296 }
13297
13298 static bool
13299 intel_check_plane_mapping(struct intel_crtc *crtc)
13300 {
13301         struct drm_device *dev = crtc->base.dev;
13302         struct drm_i915_private *dev_priv = dev->dev_private;
13303         u32 reg, val;
13304
13305         if (INTEL_INFO(dev)->num_pipes == 1)
13306                 return true;
13307
13308         reg = DSPCNTR(!crtc->plane);
13309         val = I915_READ(reg);
13310
13311         if ((val & DISPLAY_PLANE_ENABLE) &&
13312             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13313                 return false;
13314
13315         return true;
13316 }
13317
13318 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13319 {
13320         struct drm_device *dev = crtc->base.dev;
13321         struct drm_i915_private *dev_priv = dev->dev_private;
13322         u32 reg;
13323
13324         /* Clear any frame start delays used for debugging left by the BIOS */
13325         reg = PIPECONF(crtc->config->cpu_transcoder);
13326         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13327
13328         /* restore vblank interrupts to correct state */
13329         if (crtc->active) {
13330                 update_scanline_offset(crtc);
13331                 drm_vblank_on(dev, crtc->pipe);
13332         } else
13333                 drm_vblank_off(dev, crtc->pipe);
13334
13335         /* We need to sanitize the plane -> pipe mapping first because this will
13336          * disable the crtc (and hence change the state) if it is wrong. Note
13337          * that gen4+ has a fixed plane -> pipe mapping.  */
13338         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13339                 struct intel_connector *connector;
13340                 bool plane;
13341
13342                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13343                               crtc->base.base.id);
13344
13345                 /* Pipe has the wrong plane attached and the plane is active.
13346                  * Temporarily change the plane mapping and disable everything
13347                  * ...  */
13348                 plane = crtc->plane;
13349                 crtc->plane = !plane;
13350                 crtc->primary_enabled = true;
13351                 dev_priv->display.crtc_disable(&crtc->base);
13352                 crtc->plane = plane;
13353
13354                 /* ... and break all links. */
13355                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13356                                     base.head) {
13357                         if (connector->encoder->base.crtc != &crtc->base)
13358                                 continue;
13359
13360                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13361                         connector->base.encoder = NULL;
13362                 }
13363                 /* multiple connectors may have the same encoder:
13364                  *  handle them and break crtc link separately */
13365                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13366                                     base.head)
13367                         if (connector->encoder->base.crtc == &crtc->base) {
13368                                 connector->encoder->base.crtc = NULL;
13369                                 connector->encoder->connectors_active = false;
13370                         }
13371
13372                 WARN_ON(crtc->active);
13373                 crtc->base.enabled = false;
13374         }
13375
13376         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13377             crtc->pipe == PIPE_A && !crtc->active) {
13378                 /* BIOS forgot to enable pipe A, this mostly happens after
13379                  * resume. Force-enable the pipe to fix this, the update_dpms
13380                  * call below we restore the pipe to the right state, but leave
13381                  * the required bits on. */
13382                 intel_enable_pipe_a(dev);
13383         }
13384
13385         /* Adjust the state of the output pipe according to whether we
13386          * have active connectors/encoders. */
13387         intel_crtc_update_dpms(&crtc->base);
13388
13389         if (crtc->active != crtc->base.enabled) {
13390                 struct intel_encoder *encoder;
13391
13392                 /* This can happen either due to bugs in the get_hw_state
13393                  * functions or because the pipe is force-enabled due to the
13394                  * pipe A quirk. */
13395                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13396                               crtc->base.base.id,
13397                               crtc->base.enabled ? "enabled" : "disabled",
13398                               crtc->active ? "enabled" : "disabled");
13399
13400                 crtc->base.enabled = crtc->active;
13401
13402                 /* Because we only establish the connector -> encoder ->
13403                  * crtc links if something is active, this means the
13404                  * crtc is now deactivated. Break the links. connector
13405                  * -> encoder links are only establish when things are
13406                  *  actually up, hence no need to break them. */
13407                 WARN_ON(crtc->active);
13408
13409                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13410                         WARN_ON(encoder->connectors_active);
13411                         encoder->base.crtc = NULL;
13412                 }
13413         }
13414
13415         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13416                 /*
13417                  * We start out with underrun reporting disabled to avoid races.
13418                  * For correct bookkeeping mark this on active crtcs.
13419                  *
13420                  * Also on gmch platforms we dont have any hardware bits to
13421                  * disable the underrun reporting. Which means we need to start
13422                  * out with underrun reporting disabled also on inactive pipes,
13423                  * since otherwise we'll complain about the garbage we read when
13424                  * e.g. coming up after runtime pm.
13425                  *
13426                  * No protection against concurrent access is required - at
13427                  * worst a fifo underrun happens which also sets this to false.
13428                  */
13429                 crtc->cpu_fifo_underrun_disabled = true;
13430                 crtc->pch_fifo_underrun_disabled = true;
13431         }
13432 }
13433
13434 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13435 {
13436         struct intel_connector *connector;
13437         struct drm_device *dev = encoder->base.dev;
13438
13439         /* We need to check both for a crtc link (meaning that the
13440          * encoder is active and trying to read from a pipe) and the
13441          * pipe itself being active. */
13442         bool has_active_crtc = encoder->base.crtc &&
13443                 to_intel_crtc(encoder->base.crtc)->active;
13444
13445         if (encoder->connectors_active && !has_active_crtc) {
13446                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13447                               encoder->base.base.id,
13448                               encoder->base.name);
13449
13450                 /* Connector is active, but has no active pipe. This is
13451                  * fallout from our resume register restoring. Disable
13452                  * the encoder manually again. */
13453                 if (encoder->base.crtc) {
13454                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13455                                       encoder->base.base.id,
13456                                       encoder->base.name);
13457                         encoder->disable(encoder);
13458                         if (encoder->post_disable)
13459                                 encoder->post_disable(encoder);
13460                 }
13461                 encoder->base.crtc = NULL;
13462                 encoder->connectors_active = false;
13463
13464                 /* Inconsistent output/port/pipe state happens presumably due to
13465                  * a bug in one of the get_hw_state functions. Or someplace else
13466                  * in our code, like the register restore mess on resume. Clamp
13467                  * things to off as a safer default. */
13468                 list_for_each_entry(connector,
13469                                     &dev->mode_config.connector_list,
13470                                     base.head) {
13471                         if (connector->encoder != encoder)
13472                                 continue;
13473                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13474                         connector->base.encoder = NULL;
13475                 }
13476         }
13477         /* Enabled encoders without active connectors will be fixed in
13478          * the crtc fixup. */
13479 }
13480
13481 void i915_redisable_vga_power_on(struct drm_device *dev)
13482 {
13483         struct drm_i915_private *dev_priv = dev->dev_private;
13484         u32 vga_reg = i915_vgacntrl_reg(dev);
13485
13486         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13487                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13488                 i915_disable_vga(dev);
13489         }
13490 }
13491
13492 void i915_redisable_vga(struct drm_device *dev)
13493 {
13494         struct drm_i915_private *dev_priv = dev->dev_private;
13495
13496         /* This function can be called both from intel_modeset_setup_hw_state or
13497          * at a very early point in our resume sequence, where the power well
13498          * structures are not yet restored. Since this function is at a very
13499          * paranoid "someone might have enabled VGA while we were not looking"
13500          * level, just check if the power well is enabled instead of trying to
13501          * follow the "don't touch the power well if we don't need it" policy
13502          * the rest of the driver uses. */
13503         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13504                 return;
13505
13506         i915_redisable_vga_power_on(dev);
13507 }
13508
13509 static bool primary_get_hw_state(struct intel_crtc *crtc)
13510 {
13511         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13512
13513         if (!crtc->active)
13514                 return false;
13515
13516         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13517 }
13518
13519 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13520 {
13521         struct drm_i915_private *dev_priv = dev->dev_private;
13522         enum pipe pipe;
13523         struct intel_crtc *crtc;
13524         struct intel_encoder *encoder;
13525         struct intel_connector *connector;
13526         int i;
13527
13528         for_each_intel_crtc(dev, crtc) {
13529                 memset(crtc->config, 0, sizeof(*crtc->config));
13530
13531                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13532
13533                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13534                                                                  crtc->config);
13535
13536                 crtc->base.enabled = crtc->active;
13537                 crtc->primary_enabled = primary_get_hw_state(crtc);
13538
13539                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13540                               crtc->base.base.id,
13541                               crtc->active ? "enabled" : "disabled");
13542         }
13543
13544         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13545                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13546
13547                 pll->on = pll->get_hw_state(dev_priv, pll,
13548                                             &pll->config.hw_state);
13549                 pll->active = 0;
13550                 pll->config.crtc_mask = 0;
13551                 for_each_intel_crtc(dev, crtc) {
13552                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13553                                 pll->active++;
13554                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13555                         }
13556                 }
13557
13558                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13559                               pll->name, pll->config.crtc_mask, pll->on);
13560
13561                 if (pll->config.crtc_mask)
13562                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13563         }
13564
13565         for_each_intel_encoder(dev, encoder) {
13566                 pipe = 0;
13567
13568                 if (encoder->get_hw_state(encoder, &pipe)) {
13569                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13570                         encoder->base.crtc = &crtc->base;
13571                         encoder->get_config(encoder, crtc->config);
13572                 } else {
13573                         encoder->base.crtc = NULL;
13574                 }
13575
13576                 encoder->connectors_active = false;
13577                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13578                               encoder->base.base.id,
13579                               encoder->base.name,
13580                               encoder->base.crtc ? "enabled" : "disabled",
13581                               pipe_name(pipe));
13582         }
13583
13584         list_for_each_entry(connector, &dev->mode_config.connector_list,
13585                             base.head) {
13586                 if (connector->get_hw_state(connector)) {
13587                         connector->base.dpms = DRM_MODE_DPMS_ON;
13588                         connector->encoder->connectors_active = true;
13589                         connector->base.encoder = &connector->encoder->base;
13590                 } else {
13591                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13592                         connector->base.encoder = NULL;
13593                 }
13594                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13595                               connector->base.base.id,
13596                               connector->base.name,
13597                               connector->base.encoder ? "enabled" : "disabled");
13598         }
13599 }
13600
13601 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13602  * and i915 state tracking structures. */
13603 void intel_modeset_setup_hw_state(struct drm_device *dev,
13604                                   bool force_restore)
13605 {
13606         struct drm_i915_private *dev_priv = dev->dev_private;
13607         enum pipe pipe;
13608         struct intel_crtc *crtc;
13609         struct intel_encoder *encoder;
13610         int i;
13611
13612         intel_modeset_readout_hw_state(dev);
13613
13614         /*
13615          * Now that we have the config, copy it to each CRTC struct
13616          * Note that this could go away if we move to using crtc_config
13617          * checking everywhere.
13618          */
13619         for_each_intel_crtc(dev, crtc) {
13620                 if (crtc->active && i915.fastboot) {
13621                         intel_mode_from_pipe_config(&crtc->base.mode,
13622                                                     crtc->config);
13623                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13624                                       crtc->base.base.id);
13625                         drm_mode_debug_printmodeline(&crtc->base.mode);
13626                 }
13627         }
13628
13629         /* HW state is read out, now we need to sanitize this mess. */
13630         for_each_intel_encoder(dev, encoder) {
13631                 intel_sanitize_encoder(encoder);
13632         }
13633
13634         for_each_pipe(dev_priv, pipe) {
13635                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13636                 intel_sanitize_crtc(crtc);
13637                 intel_dump_pipe_config(crtc, crtc->config,
13638                                        "[setup_hw_state]");
13639         }
13640
13641         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13642                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13643
13644                 if (!pll->on || pll->active)
13645                         continue;
13646
13647                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13648
13649                 pll->disable(dev_priv, pll);
13650                 pll->on = false;
13651         }
13652
13653         if (IS_GEN9(dev))
13654                 skl_wm_get_hw_state(dev);
13655         else if (HAS_PCH_SPLIT(dev))
13656                 ilk_wm_get_hw_state(dev);
13657
13658         if (force_restore) {
13659                 i915_redisable_vga(dev);
13660
13661                 /*
13662                  * We need to use raw interfaces for restoring state to avoid
13663                  * checking (bogus) intermediate states.
13664                  */
13665                 for_each_pipe(dev_priv, pipe) {
13666                         struct drm_crtc *crtc =
13667                                 dev_priv->pipe_to_crtc_mapping[pipe];
13668
13669                         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13670                                        crtc->primary->fb);
13671                 }
13672         } else {
13673                 intel_modeset_update_staged_output_state(dev);
13674         }
13675
13676         intel_modeset_check_state(dev);
13677 }
13678
13679 void intel_modeset_gem_init(struct drm_device *dev)
13680 {
13681         struct drm_i915_private *dev_priv = dev->dev_private;
13682         struct drm_crtc *c;
13683         struct drm_i915_gem_object *obj;
13684
13685         mutex_lock(&dev->struct_mutex);
13686         intel_init_gt_powersave(dev);
13687         mutex_unlock(&dev->struct_mutex);
13688
13689         /*
13690          * There may be no VBT; and if the BIOS enabled SSC we can
13691          * just keep using it to avoid unnecessary flicker.  Whereas if the
13692          * BIOS isn't using it, don't assume it will work even if the VBT
13693          * indicates as much.
13694          */
13695         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13696                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13697                                                 DREF_SSC1_ENABLE);
13698
13699         intel_modeset_init_hw(dev);
13700
13701         intel_setup_overlay(dev);
13702
13703         /*
13704          * Make sure any fbs we allocated at startup are properly
13705          * pinned & fenced.  When we do the allocation it's too early
13706          * for this.
13707          */
13708         mutex_lock(&dev->struct_mutex);
13709         for_each_crtc(dev, c) {
13710                 obj = intel_fb_obj(c->primary->fb);
13711                 if (obj == NULL)
13712                         continue;
13713
13714                 if (intel_pin_and_fence_fb_obj(c->primary,
13715                                                c->primary->fb,
13716                                                NULL)) {
13717                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13718                                   to_intel_crtc(c)->pipe);
13719                         drm_framebuffer_unreference(c->primary->fb);
13720                         c->primary->fb = NULL;
13721                 }
13722         }
13723         mutex_unlock(&dev->struct_mutex);
13724
13725         intel_backlight_register(dev);
13726 }
13727
13728 void intel_connector_unregister(struct intel_connector *intel_connector)
13729 {
13730         struct drm_connector *connector = &intel_connector->base;
13731
13732         intel_panel_destroy_backlight(connector);
13733         drm_connector_unregister(connector);
13734 }
13735
13736 void intel_modeset_cleanup(struct drm_device *dev)
13737 {
13738         struct drm_i915_private *dev_priv = dev->dev_private;
13739         struct drm_connector *connector;
13740
13741         intel_disable_gt_powersave(dev);
13742
13743         intel_backlight_unregister(dev);
13744
13745         /*
13746          * Interrupts and polling as the first thing to avoid creating havoc.
13747          * Too much stuff here (turning of connectors, ...) would
13748          * experience fancy races otherwise.
13749          */
13750         intel_irq_uninstall(dev_priv);
13751
13752         /*
13753          * Due to the hpd irq storm handling the hotplug work can re-arm the
13754          * poll handlers. Hence disable polling after hpd handling is shut down.
13755          */
13756         drm_kms_helper_poll_fini(dev);
13757
13758         mutex_lock(&dev->struct_mutex);
13759
13760         intel_unregister_dsm_handler();
13761
13762         intel_fbc_disable(dev);
13763
13764         ironlake_teardown_rc6(dev);
13765
13766         mutex_unlock(&dev->struct_mutex);
13767
13768         /* flush any delayed tasks or pending work */
13769         flush_scheduled_work();
13770
13771         /* destroy the backlight and sysfs files before encoders/connectors */
13772         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13773                 struct intel_connector *intel_connector;
13774
13775                 intel_connector = to_intel_connector(connector);
13776                 intel_connector->unregister(intel_connector);
13777         }
13778
13779         drm_mode_config_cleanup(dev);
13780
13781         intel_cleanup_overlay(dev);
13782
13783         mutex_lock(&dev->struct_mutex);
13784         intel_cleanup_gt_powersave(dev);
13785         mutex_unlock(&dev->struct_mutex);
13786 }
13787
13788 /*
13789  * Return which encoder is currently attached for connector.
13790  */
13791 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13792 {
13793         return &intel_attached_encoder(connector)->base;
13794 }
13795
13796 void intel_connector_attach_encoder(struct intel_connector *connector,
13797                                     struct intel_encoder *encoder)
13798 {
13799         connector->encoder = encoder;
13800         drm_mode_connector_attach_encoder(&connector->base,
13801                                           &encoder->base);
13802 }
13803
13804 /*
13805  * set vga decode state - true == enable VGA decode
13806  */
13807 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13808 {
13809         struct drm_i915_private *dev_priv = dev->dev_private;
13810         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13811         u16 gmch_ctrl;
13812
13813         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13814                 DRM_ERROR("failed to read control word\n");
13815                 return -EIO;
13816         }
13817
13818         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13819                 return 0;
13820
13821         if (state)
13822                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13823         else
13824                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13825
13826         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13827                 DRM_ERROR("failed to write control word\n");
13828                 return -EIO;
13829         }
13830
13831         return 0;
13832 }
13833
13834 struct intel_display_error_state {
13835
13836         u32 power_well_driver;
13837
13838         int num_transcoders;
13839
13840         struct intel_cursor_error_state {
13841                 u32 control;
13842                 u32 position;
13843                 u32 base;
13844                 u32 size;
13845         } cursor[I915_MAX_PIPES];
13846
13847         struct intel_pipe_error_state {
13848                 bool power_domain_on;
13849                 u32 source;
13850                 u32 stat;
13851         } pipe[I915_MAX_PIPES];
13852
13853         struct intel_plane_error_state {
13854                 u32 control;
13855                 u32 stride;
13856                 u32 size;
13857                 u32 pos;
13858                 u32 addr;
13859                 u32 surface;
13860                 u32 tile_offset;
13861         } plane[I915_MAX_PIPES];
13862
13863         struct intel_transcoder_error_state {
13864                 bool power_domain_on;
13865                 enum transcoder cpu_transcoder;
13866
13867                 u32 conf;
13868
13869                 u32 htotal;
13870                 u32 hblank;
13871                 u32 hsync;
13872                 u32 vtotal;
13873                 u32 vblank;
13874                 u32 vsync;
13875         } transcoder[4];
13876 };
13877
13878 struct intel_display_error_state *
13879 intel_display_capture_error_state(struct drm_device *dev)
13880 {
13881         struct drm_i915_private *dev_priv = dev->dev_private;
13882         struct intel_display_error_state *error;
13883         int transcoders[] = {
13884                 TRANSCODER_A,
13885                 TRANSCODER_B,
13886                 TRANSCODER_C,
13887                 TRANSCODER_EDP,
13888         };
13889         int i;
13890
13891         if (INTEL_INFO(dev)->num_pipes == 0)
13892                 return NULL;
13893
13894         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13895         if (error == NULL)
13896                 return NULL;
13897
13898         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13899                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13900
13901         for_each_pipe(dev_priv, i) {
13902                 error->pipe[i].power_domain_on =
13903                         __intel_display_power_is_enabled(dev_priv,
13904                                                          POWER_DOMAIN_PIPE(i));
13905                 if (!error->pipe[i].power_domain_on)
13906                         continue;
13907
13908                 error->cursor[i].control = I915_READ(CURCNTR(i));
13909                 error->cursor[i].position = I915_READ(CURPOS(i));
13910                 error->cursor[i].base = I915_READ(CURBASE(i));
13911
13912                 error->plane[i].control = I915_READ(DSPCNTR(i));
13913                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13914                 if (INTEL_INFO(dev)->gen <= 3) {
13915                         error->plane[i].size = I915_READ(DSPSIZE(i));
13916                         error->plane[i].pos = I915_READ(DSPPOS(i));
13917                 }
13918                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13919                         error->plane[i].addr = I915_READ(DSPADDR(i));
13920                 if (INTEL_INFO(dev)->gen >= 4) {
13921                         error->plane[i].surface = I915_READ(DSPSURF(i));
13922                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13923                 }
13924
13925                 error->pipe[i].source = I915_READ(PIPESRC(i));
13926
13927                 if (HAS_GMCH_DISPLAY(dev))
13928                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13929         }
13930
13931         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13932         if (HAS_DDI(dev_priv->dev))
13933                 error->num_transcoders++; /* Account for eDP. */
13934
13935         for (i = 0; i < error->num_transcoders; i++) {
13936                 enum transcoder cpu_transcoder = transcoders[i];
13937
13938                 error->transcoder[i].power_domain_on =
13939                         __intel_display_power_is_enabled(dev_priv,
13940                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13941                 if (!error->transcoder[i].power_domain_on)
13942                         continue;
13943
13944                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13945
13946                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13947                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13948                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13949                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13950                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13951                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13952                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13953         }
13954
13955         return error;
13956 }
13957
13958 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13959
13960 void
13961 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13962                                 struct drm_device *dev,
13963                                 struct intel_display_error_state *error)
13964 {
13965         struct drm_i915_private *dev_priv = dev->dev_private;
13966         int i;
13967
13968         if (!error)
13969                 return;
13970
13971         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13972         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13973                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13974                            error->power_well_driver);
13975         for_each_pipe(dev_priv, i) {
13976                 err_printf(m, "Pipe [%d]:\n", i);
13977                 err_printf(m, "  Power: %s\n",
13978                            error->pipe[i].power_domain_on ? "on" : "off");
13979                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13980                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13981
13982                 err_printf(m, "Plane [%d]:\n", i);
13983                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13984                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13985                 if (INTEL_INFO(dev)->gen <= 3) {
13986                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13987                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13988                 }
13989                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13990                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13991                 if (INTEL_INFO(dev)->gen >= 4) {
13992                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13993                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13994                 }
13995
13996                 err_printf(m, "Cursor [%d]:\n", i);
13997                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13998                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13999                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
14000         }
14001
14002         for (i = 0; i < error->num_transcoders; i++) {
14003                 err_printf(m, "CPU transcoder: %c\n",
14004                            transcoder_name(error->transcoder[i].cpu_transcoder));
14005                 err_printf(m, "  Power: %s\n",
14006                            error->transcoder[i].power_domain_on ? "on" : "off");
14007                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
14008                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
14009                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
14010                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
14011                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
14012                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
14013                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
14014         }
14015 }
14016
14017 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14018 {
14019         struct intel_crtc *crtc;
14020
14021         for_each_intel_crtc(dev, crtc) {
14022                 struct intel_unpin_work *work;
14023
14024                 spin_lock_irq(&dev->event_lock);
14025
14026                 work = crtc->unpin_work;
14027
14028                 if (work && work->event &&
14029                     work->event->base.file_priv == file) {
14030                         kfree(work->event);
14031                         work->event = NULL;
14032                 }
14033
14034                 spin_unlock_irq(&dev->event_lock);
14035         }
14036 }