2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
11 #include <asm/processor.h>
12 #include <asm/arch/clock.h>
13 #include <linux/ctype.h>
14 #ifdef CONFIG_FSL_ESDHC
15 #include <fsl_esdhc.h>
18 #include <asm/arch/immap_ls102xa.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 void ft_fixup_enet_phy_connect_type(void *fdt)
25 struct eth_device *dev;
26 struct tsec_private *priv;
27 const char *enet_path, *phy_path;
35 while ((dev = eth_get_dev_by_index(i++)) != NULL) {
36 if (strstr(dev->name, "eTSEC1"))
38 else if (strstr(dev->name, "eTSEC2"))
40 else if (strstr(dev->name, "eTSEC3"))
46 if (priv->flags & TSEC_SGMII)
49 sprintf(enet, "ethernet%d", enet_id);
50 enet_path = fdt_get_alias(fdt, enet);
54 sprintf(phy, "enet%d_rgmii_phy", enet_id);
55 phy_path = fdt_get_alias(fdt, phy);
59 phy_node = fdt_path_offset(fdt, phy_path);
63 ph = fdt_create_phandle(fdt, phy_node);
65 do_fixup_by_path_u32(fdt, enet_path,
68 do_fixup_by_path(fdt, enet_path, "phy-connection-type",
69 phy_string_for_interface(
70 PHY_INTERFACE_MODE_RGMII_ID),
71 sizeof(phy_string_for_interface(
72 PHY_INTERFACE_MODE_RGMII_ID)),
77 void ft_cpu_setup(void *blob, bd_t *bd)
81 const char *sysclk_path;
82 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
84 svr = in_be32(&gur->svr);
86 unsigned long busclk = get_bus_freq(0);
88 /* delete crypto node if not on an E-processor */
89 if (!IS_E_PROCESSOR(svr))
90 fdt_fixup_crypto_node(blob, 0);
91 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
93 ccsr_sec_t __iomem *sec;
95 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
96 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
100 fdt_fixup_ethernet(blob);
102 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
103 while (off != -FDT_ERR_NOTFOUND) {
105 fdt_setprop(blob, off, "clock-frequency", &val, 4);
106 off = fdt_node_offset_by_prop_value(blob, off,
107 "device_type", "cpu", 4);
110 do_fixup_by_prop_u32(blob, "device_type", "soc",
111 4, "bus-frequency", busclk, 1);
113 ft_fixup_enet_phy_connect_type(blob);
115 #ifdef CONFIG_SYS_NS16550
116 do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
117 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
120 sysclk_path = fdt_get_alias(blob, "sysclk");
122 do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
123 CONFIG_SYS_CLK_FREQ, 1);
124 do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
125 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
127 #if defined(CONFIG_FSL_ESDHC)
128 fdt_fixup_esdhc(blob, bd);
132 * platform bus clock = system bus clock/2
133 * Here busclk = system bus clock
134 * We are using the platform bus clock as 1588 Timer reference
135 * clock source select
137 do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
138 "timer-frequency", busclk / 2, 1);
141 * clock-freq should change to clock-frequency and
142 * flexcan-v1.0 should change to p1010-flexcan respectively
145 do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
146 "clock_freq", busclk / 2, 1);
148 do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
149 "clock-frequency", busclk / 2, 1);
151 do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
152 "clock-frequency", busclk / 2, 1);