arch/powerpc/cpu/mpc85xx/ddr-gen3.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/fsl_ddr_sdram.h>
  12 #include <asm/processor.h>
  13
  14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  16 #endif
  17
  18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  19                              unsigned int ctrl_num)
  20 {
  21         unsigned int i, bus_width;
  22         volatile ccsr_ddr_t *ddr;
  23         u32 temp_sdram_cfg;
  24         u32 total_gb_size_per_controller;
  25         int timeout, timeout_save;
  26 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  27         volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
  28         unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
  29         int csn = -1;
  30 #endif
  31
  32         switch (ctrl_num) {
  33         case 0:
  34                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  35                 break;
  36 #if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  37         case 1:
  38                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
  39                 break;
  40 #endif
  41 #if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  42         case 2:
  43                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
  44                 break;
  45 #endif
  46 #if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  47         case 3:
  48                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
  49                 break;
  50 #endif
  51         default:
  52                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  53                 return;
  54         }
  55
  56         if (regs->ddr_eor)
  57                 out_be32(&ddr->eor, regs->ddr_eor);
  58 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  59         debug("Workaround for ERRATUM_DDR111_DDR134\n");
  60         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  61                 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
  62                 cs_ea = regs->cs[i].bnds & 0xfff;
  63                 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
  64                         csn = i;
  65                         csn_bnds_backup = regs->cs[i].bnds;
  66                         csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
  67                         if (cs_ea > 0xeff)
  68                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
  69                         else
  70                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
  71                         debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
  72                                 "change it to 0x%x\n",
  73                                 csn, csn_bnds_backup, regs->cs[i].bnds);
  74                         break;
  75                 }
  76         }
  77 #endif
  78         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  79                 if (i == 0) {
  80                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  81                         out_be32(&ddr->cs0_config, regs->cs[i].config);
  82                         out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
  83
  84                 } else if (i == 1) {
  85                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  86                         out_be32(&ddr->cs1_config, regs->cs[i].config);
  87                         out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
  88
  89                 } else if (i == 2) {
  90                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  91                         out_be32(&ddr->cs2_config, regs->cs[i].config);
  92                         out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
  93
  94                 } else if (i == 3) {
  95                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  96                         out_be32(&ddr->cs3_config, regs->cs[i].config);
  97                         out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
  98                 }
  99         }
 100
 101         out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 102         out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 103         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 104         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 105         out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 106         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 107         out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 108         out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 109         out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 110         out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 111         out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 112         out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 113         out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 114         out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 115         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 116         out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
 117         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 118         out_be32(&ddr->init_addr, regs->ddr_init_addr);
 119         out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 120
 121         out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 122         out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 123         out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 124         out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 125         if (regs->ddr_wrlvl_cntl_2)
 126                 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 127         if (regs->ddr_wrlvl_cntl_3)
 128                 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 129
 130         out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 131         out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 132         out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 133         out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 134         out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 135         out_be32(&ddr->err_disable, regs->err_disable);
 136         out_be32(&ddr->err_int_en, regs->err_int_en);
 137         for (i = 0; i < 32; i++) {
 138                 if (regs->debug[i]) {
 139                         debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
 140                         out_be32(&ddr->debug[i], regs->debug[i]);
 141                 }
 142         }
 143 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
 144         out_be32(&ddr->debug[28], 0x00003000);
 145 #endif
 146
 147 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 148         out_be32(&ddr->debug[12], 0x00000015);
 149         out_be32(&ddr->debug[21], 0x24000000);
 150 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
 151
 152         /* Set, but do not enable the memory */
 153         temp_sdram_cfg = regs->ddr_sdram_cfg;
 154         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 155         out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 156 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 157         debug("Workaround for ERRATUM_DDR_A003\n");
 158         if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 159                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
 160                 out_be32(&ddr->debug[2], 0x00000400);
 161                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
 162                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
 163                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
 164                 out_be32(&ddr->mtcr, 0);
 165                 out_be32(&ddr->debug[12], 0x00000015);
 166                 out_be32(&ddr->debug[21], 0x24000000);
 167                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
 168                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
 169
 170                 asm volatile("sync;isync");
 171                 while (!(in_be32(&ddr->debug[1]) & 0x2))
 172                         ;
 173
 174                 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 175                 case 0x00000000:
 176                         out_be32(&ddr->sdram_md_cntl,
 177                                 MD_CNTL_MD_EN           |
 178                                 MD_CNTL_CS_SEL_CS0_CS1  |
 179                                 0x04000000              |
 180                                 MD_CNTL_WRCW            |
 181                                 MD_CNTL_MD_VALUE(0x02));
 182                         break;
 183                 case 0x00100000:
 184                         out_be32(&ddr->sdram_md_cntl,
 185                                 MD_CNTL_MD_EN           |
 186                                 MD_CNTL_CS_SEL_CS0_CS1  |
 187                                 0x04000000              |
 188                                 MD_CNTL_WRCW            |
 189                                 MD_CNTL_MD_VALUE(0x0a));
 190                         break;
 191                 case 0x00200000:
 192                         out_be32(&ddr->sdram_md_cntl,
 193                                 MD_CNTL_MD_EN           |
 194                                 MD_CNTL_CS_SEL_CS0_CS1  |
 195                                 0x04000000              |
 196                                 MD_CNTL_WRCW            |
 197                                 MD_CNTL_MD_VALUE(0x12));
 198                         break;
 199                 case 0x00300000:
 200                         out_be32(&ddr->sdram_md_cntl,
 201                                 MD_CNTL_MD_EN           |
 202                                 MD_CNTL_CS_SEL_CS0_CS1  |
 203                                 0x04000000              |
 204                                 MD_CNTL_WRCW            |
 205                                 MD_CNTL_MD_VALUE(0x1a));
 206                         break;
 207                 default:
 208                         out_be32(&ddr->sdram_md_cntl,
 209                                 MD_CNTL_MD_EN           |
 210                                 MD_CNTL_CS_SEL_CS0_CS1  |
 211                                 0x04000000              |
 212                                 MD_CNTL_WRCW            |
 213                                 MD_CNTL_MD_VALUE(0x02));
 214                         printf("Unsupported RC10\n");
 215                         break;
 216                 }
 217
 218                 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
 219                         ;
 220                 udelay(6);
 221                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 222                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 223                 out_be32(&ddr->debug[2], 0x0);
 224                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 225                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 226                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 227                 out_be32(&ddr->debug[12], 0x0);
 228                 out_be32(&ddr->debug[21], 0x0);
 229                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 230
 231         }
 232 #endif
 233         /*
 234          * For 8572 DDR1 erratum - DDR controller may enter illegal state
 235          * when operatiing in 32-bit bus mode with 4-beat bursts,
 236          * This erratum does not affect DDR3 mode, only for DDR2 mode.
 237          */
 238 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
 239         debug("Workaround for ERRATUM_DDR_115\n");
 240         if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
 241             && in_be32(&ddr->sdram_cfg) & 0x80000) {
 242                 /* set DEBUG_1[31] */
 243                 setbits_be32(&ddr->debug[0], 1);
 244         }
 245 #endif
 246 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 247         debug("Workaround for ERRATUM_DDR111_DDR134\n");
 248         /*
 249          * This is the combined workaround for DDR111 and DDR134
 250          * following the published errata for MPC8572
 251          */
 252
 253         /* 1. Set EEBACR[3] */
 254         setbits_be32(&ecm->eebacr, 0x10000000);
 255         debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 256
 257         /* 2. Set DINIT in SDRAM_CFG_2*/
 258         setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
 259         debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
 260                 in_be32(&ddr->sdram_cfg_2));
 261
 262         /* 3. Set DEBUG_3[21] */
 263         setbits_be32(&ddr->debug[2], 0x400);
 264         debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 265
 266 #endif  /* part 1 of the workaound */
 267
 268         /*
 269          * 500 painful micro-seconds must elapse between
 270          * the DDR clock setup and the DDR config enable.
 271          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 272          * we choose the max, that is 500 us for all of case.
 273          */
 274         udelay(500);
 275         asm volatile("sync;isync");
 276
 277         /* Let the controller go */
 278         temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 279         out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 280         asm volatile("sync;isync");
 281
 282         total_gb_size_per_controller = 0;
 283         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 284                 if (!(regs->cs[i].config & 0x80000000))
 285                         continue;
 286                 total_gb_size_per_controller += 1 << (
 287                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 288                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 289                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 290                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 291                         26);                    /* minus 26 (count of 64M) */
 292         }
 293         if (fsl_ddr_get_intl3r() & 0x80000000)  /* 3-way interleaving */
 294                 total_gb_size_per_controller *= 3;
 295         else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
 296                 total_gb_size_per_controller <<= 1;
 297         /*
 298          * total memory / bus width = transactions needed
 299          * transactions needed / data rate = seconds
 300          * to add plenty of buffer, double the time
 301          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 302          * Let's wait for 800ms
 303          */
 304         bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
 305                         >> SDRAM_CFG_DBW_SHIFT);
 306         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 307                 (get_ddr_freq(0) >> 20)) << 1;
 308         timeout_save = timeout;
 309         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 310         debug("total %d GB\n", total_gb_size_per_controller);
 311         debug("Need to wait up to %d * 10ms\n", timeout);
 312
 313         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 314         while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 315                 (timeout >= 0)) {
 316                 udelay(10000);          /* throttle polling rate */
 317                 timeout--;
 318         }
 319
 320         if (timeout <= 0)
 321                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 322
 323 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 324         /* continue this workaround */
 325
 326         /* 4. Clear DEBUG3[21] */
 327         clrbits_be32(&ddr->debug[2], 0x400);
 328         debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 329
 330         /* DDR134 workaround starts */
 331         /* A: Clear sdram_cfg_2[odt_cfg] */
 332         clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
 333         debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
 334                 in_be32(&ddr->sdram_cfg_2));
 335
 336         /* B: Set DEBUG1[15] */
 337         setbits_be32(&ddr->debug[0], 0x10000);
 338         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 339
 340         /* C: Set timing_cfg_2[cpo] to 0b11111 */
 341         setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
 342         debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
 343                 in_be32(&ddr->timing_cfg_2));
 344
 345         /* D: Set D6 to 0x9f9f9f9f */
 346         out_be32(&ddr->debug[5], 0x9f9f9f9f);
 347         debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
 348
 349         /* E: Set D7 to 0x9f9f9f9f */
 350         out_be32(&ddr->debug[6], 0x9f9f9f9f);
 351         debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
 352
 353         /* F: Set D2[20] */
 354         setbits_be32(&ddr->debug[1], 0x800);
 355         debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
 356
 357         /* G: Poll on D2[20] until cleared */
 358         while (in_be32(&ddr->debug[1]) & 0x800)
 359                 udelay(10000);          /* throttle polling rate */
 360
 361         /* H: Clear D1[15] */
 362         clrbits_be32(&ddr->debug[0], 0x10000);
 363         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 364
 365         /* I: Set sdram_cfg_2[odt_cfg] */
 366         setbits_be32(&ddr->sdram_cfg_2,
 367                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
 368         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 369
 370         /* Continuing with the DDR111 workaround */
 371         /* 5. Set D2[21] */
 372         setbits_be32(&ddr->debug[1], 0x400);
 373         debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
 374
 375         /* 6. Poll D2[21] until its cleared */
 376         while (in_be32(&ddr->debug[1]) & 0x400)
 377                 udelay(10000);          /* throttle polling rate */
 378
 379         /* 7. Wait for state machine 2nd run, roughly 400ms/GB */
 380         debug("Wait for %d * 10ms\n", timeout_save);
 381         udelay(timeout_save * 10000);
 382
 383         /* 8. Set sdram_cfg_2[dinit] if options requires */
 384         setbits_be32(&ddr->sdram_cfg_2,
 385                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
 386         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 387
 388         /* 9. Poll until dinit is cleared */
 389         timeout = timeout_save;
 390         debug("Need to wait up to %d * 10ms\n", timeout);
 391         while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 392                 (timeout >= 0)) {
 393                 udelay(10000);          /* throttle polling rate */
 394                 timeout--;
 395         }
 396
 397         if (timeout <= 0)
 398                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 399
 400         /* 10. Clear EEBACR[3] */
 401         clrbits_be32(&ecm->eebacr, 10000000);
 402         debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 403
 404         if (csn != -1) {
 405                 csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
 406                 *csn_bnds_t = csn_bnds_backup;
 407                 debug("Change cs%d_bnds back to 0x%08x\n",
 408                         csn, regs->cs[csn].bnds);
 409                 setbits_be32(&ddr->sdram_cfg, 0x2);     /* MEM_HALT */
 410                 switch (csn) {
 411                 case 0:
 412                         out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
 413                         break;
 414                 case 1:
 415                         out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
 416                         break;
 417                 case 2:
 418                         out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
 419                         break;
 420                 case 3:
 421                         out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
 422                         break;
 423                 }
 424                 clrbits_be32(&ddr->sdram_cfg, 0x2);
 425         }
 426 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
 427 }