drivers/mtd/nand/omap_gpmc.c

   1 /*
   2  * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
   3  * Rohit Choraria <rohitkc@ti.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/mem.h>
  12 #include <linux/mtd/omap_gpmc.h>
  13 #include <linux/mtd/nand_ecc.h>
  14 #include <linux/bch.h>
  15 #include <linux/compiler.h>
  16 #include <nand.h>
  17 #include <linux/mtd/omap_elm.h>
  18
  19 #define BADBLOCK_MARKER_LENGTH  2
  20 #define SECTOR_BYTES            512
  21 #define ECCCLEAR                (0x1 << 8)
  22 #define ECCRESULTREG1           (0x1 << 0)
  23 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
  24 #define BCH4_BIT_PAD            4
  25
  26 #ifdef CONFIG_BCH
  27 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
  28                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
  29 #endif
  30 static uint8_t cs_next;
  31 static __maybe_unused struct nand_ecclayout omap_ecclayout;
  32
  33 /*
  34  * Driver configurations
  35  */
  36 struct omap_nand_info {
  37         struct bch_control *control;
  38         enum omap_ecc ecc_scheme;
  39         int cs;
  40 };
  41
  42 /* We are wasting a bit of memory but al least we are safe */
  43 static struct omap_nand_info omap_nand_info[GPMC_MAX_CS];
  44
  45 /*
  46  * omap_nand_hwcontrol - Set the address pointers corretly for the
  47  *                      following address/data/command operation
  48  */
  49 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
  50                                 uint32_t ctrl)
  51 {
  52         register struct nand_chip *this = mtd->priv;
  53         struct omap_nand_info *info = this->priv;
  54         int cs = info->cs;
  55
  56         /*
  57          * Point the IO_ADDR to DATA and ADDRESS registers instead
  58          * of chip address
  59          */
  60         switch (ctrl) {
  61         case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
  62                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
  63                 break;
  64         case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
  65                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
  66                 break;
  67         case NAND_CTRL_CHANGE | NAND_NCE:
  68                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
  69                 break;
  70         }
  71
  72         if (cmd != NAND_CMD_NONE)
  73                 writeb(cmd, this->IO_ADDR_W);
  74 }
  75
  76 #ifdef CONFIG_SPL_BUILD
  77 /* Check wait pin as dev ready indicator */
  78 int omap_spl_dev_ready(struct mtd_info *mtd)
  79 {
  80         return gpmc_cfg->status & (1 << 8);
  81 }
  82 #endif
  83
  84
  85 /*
  86  * gen_true_ecc - This function will generate true ECC value, which
  87  * can be used when correcting data read from NAND flash memory core
  88  *
  89  * @ecc_buf:    buffer to store ecc code
  90  *
  91  * @return:     re-formatted ECC value
  92  */
  93 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
  94 {
  95         return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
  96                 ((ecc_buf[2] & 0x0F) << 8);
  97 }
  98
  99 /*
 100  * omap_correct_data - Compares the ecc read from nand spare area with ECC
 101  * registers values and corrects one bit error if it has occured
 102  * Further details can be had from OMAP TRM and the following selected links:
 103  * http://en.wikipedia.org/wiki/Hamming_code
 104  * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
 105  *
 106  * @mtd:                 MTD device structure
 107  * @dat:                 page data
 108  * @read_ecc:            ecc read from nand flash
 109  * @calc_ecc:            ecc read from ECC registers
 110  *
 111  * @return 0 if data is OK or corrected, else returns -1
 112  */
 113 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 114                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 115 {
 116         uint32_t orig_ecc, new_ecc, res, hm;
 117         uint16_t parity_bits, byte;
 118         uint8_t bit;
 119
 120         /* Regenerate the orginal ECC */
 121         orig_ecc = gen_true_ecc(read_ecc);
 122         new_ecc = gen_true_ecc(calc_ecc);
 123         /* Get the XOR of real ecc */
 124         res = orig_ecc ^ new_ecc;
 125         if (res) {
 126                 /* Get the hamming width */
 127                 hm = hweight32(res);
 128                 /* Single bit errors can be corrected! */
 129                 if (hm == 12) {
 130                         /* Correctable data! */
 131                         parity_bits = res >> 16;
 132                         bit = (parity_bits & 0x7);
 133                         byte = (parity_bits >> 3) & 0x1FF;
 134                         /* Flip the bit to correct */
 135                         dat[byte] ^= (0x1 << bit);
 136                 } else if (hm == 1) {
 137                         printf("Error: Ecc is wrong\n");
 138                         /* ECC itself is corrupted */
 139                         return 2;
 140                 } else {
 141                         /*
 142                          * hm distance != parity pairs OR one, could mean 2 bit
 143                          * error OR potentially be on a blank page..
 144                          * orig_ecc: contains spare area data from nand flash.
 145                          * new_ecc: generated ecc while reading data area.
 146                          * Note: if the ecc = 0, all data bits from which it was
 147                          * generated are 0xFF.
 148                          * The 3 byte(24 bits) ecc is generated per 512byte
 149                          * chunk of a page. If orig_ecc(from spare area)
 150                          * is 0xFF && new_ecc(computed now from data area)=0x0,
 151                          * this means that data area is 0xFF and spare area is
 152                          * 0xFF. A sure sign of a erased page!
 153                          */
 154                         if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
 155                                 return 0;
 156                         printf("Error: Bad compare! failed\n");
 157                         /* detected 2 bit error */
 158                         return -1;
 159                 }
 160         }
 161         return 0;
 162 }
 163
 164 /*
 165  * omap_reverse_list - re-orders list elements in reverse order [internal]
 166  * @list:       pointer to start of list
 167  * @length:     length of list
 168 */
 169 void omap_reverse_list(u8 *list, unsigned int length)
 170 {
 171         unsigned int i, j;
 172         unsigned int half_length = length / 2;
 173         u8 tmp;
 174         for (i = 0, j = length - 1; i < half_length; i++, j--) {
 175                 tmp = list[i];
 176                 list[i] = list[j];
 177                 list[j] = tmp;
 178         }
 179 }
 180
 181 /*
 182  * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
 183  * @mtd:        MTD device structure
 184  * @mode:       Read/Write mode
 185  */
 186 __maybe_unused
 187 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 188 {
 189         struct nand_chip        *nand   = mtd->priv;
 190         struct omap_nand_info   *info   = nand->priv;
 191         unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
 192         unsigned int ecc_algo = 0;
 193         unsigned int bch_type = 0;
 194         unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
 195         u32 ecc_size_config_val = 0;
 196         u32 ecc_config_val = 0;
 197         int cs = info->cs;
 198
 199         /* configure GPMC for specific ecc-scheme */
 200         switch (info->ecc_scheme) {
 201         case OMAP_ECC_HAM1_CODE_SW:
 202                 return;
 203         case OMAP_ECC_HAM1_CODE_HW:
 204                 ecc_algo = 0x0;
 205                 bch_type = 0x0;
 206                 bch_wrapmode = 0x00;
 207                 eccsize0 = 0xFF;
 208                 eccsize1 = 0xFF;
 209                 break;
 210         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 211         case OMAP_ECC_BCH8_CODE_HW:
 212                 ecc_algo = 0x1;
 213                 bch_type = 0x1;
 214                 if (mode == NAND_ECC_WRITE) {
 215                         bch_wrapmode = 0x01;
 216                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 217                         eccsize1 = 28; /* OOB bits in nibbles per sector */
 218                 } else {
 219                         bch_wrapmode = 0x01;
 220                         eccsize0 = 26; /* ECC bits in nibbles per sector */
 221                         eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
 222                 }
 223                 break;
 224         case OMAP_ECC_BCH16_CODE_HW:
 225                 ecc_algo = 0x1;
 226                 bch_type = 0x2;
 227                 if (mode == NAND_ECC_WRITE) {
 228                         bch_wrapmode = 0x01;
 229                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 230                         eccsize1 = 52; /* OOB bits in nibbles per sector */
 231                 } else {
 232                         bch_wrapmode = 0x01;
 233                         eccsize0 = 52; /* ECC bits in nibbles per sector */
 234                         eccsize1 = 0;  /* non-ECC bits in nibbles per sector */
 235                 }
 236                 break;
 237         default:
 238                 return;
 239         }
 240         /* Clear ecc and enable bits */
 241         writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
 242         /* Configure ecc size for BCH */
 243         ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
 244         writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
 245
 246         /* Configure device details for BCH engine */
 247         ecc_config_val = ((ecc_algo << 16)      | /* HAM1 | BCHx */
 248                         (bch_type << 12)        | /* BCH4/BCH8/BCH16 */
 249                         (bch_wrapmode << 8)     | /* wrap mode */
 250                         (dev_width << 7)        | /* bus width */
 251                         (0x0 << 4)              | /* number of sectors */
 252                         (cs <<  1)              | /* ECC CS */
 253                         (0x1));                   /* enable ECC */
 254         writel(ecc_config_val, &gpmc_cfg->ecc_config);
 255 }
 256
 257 /*
 258  *  omap_calculate_ecc - Read ECC result
 259  *  @mtd:       MTD structure
 260  *  @dat:       unused
 261  *  @ecc_code:  ecc_code buffer
 262  *  Using noninverted ECC can be considered ugly since writing a blank
 263  *  page ie. padding will clear the ECC bytes. This is no problem as
 264  *  long nobody is trying to write data on the seemingly unused page.
 265  *  Reading an erased page will produce an ECC mismatch between
 266  *  generated and read ECC bytes that has to be dealt with separately.
 267  *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
 268  *  is used, the result of read will be 0x0 while the ECC offsets of the
 269  *  spare area will be 0xFF which will result in an ECC mismatch.
 270  */
 271 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 272                                 uint8_t *ecc_code)
 273 {
 274         struct nand_chip *chip = mtd->priv;
 275         struct omap_nand_info *info = chip->priv;
 276         uint32_t *ptr, val = 0;
 277         int8_t i = 0, j;
 278
 279         switch (info->ecc_scheme) {
 280         case OMAP_ECC_HAM1_CODE_HW:
 281                 val = readl(&gpmc_cfg->ecc1_result);
 282                 ecc_code[0] = val & 0xFF;
 283                 ecc_code[1] = (val >> 16) & 0xFF;
 284                 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
 285                 break;
 286 #ifdef CONFIG_BCH
 287         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 288 #endif
 289         case OMAP_ECC_BCH8_CODE_HW:
 290                 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
 291                 val = readl(ptr);
 292                 ecc_code[i++] = (val >>  0) & 0xFF;
 293                 ptr--;
 294                 for (j = 0; j < 3; j++) {
 295                         val = readl(ptr);
 296                         ecc_code[i++] = (val >> 24) & 0xFF;
 297                         ecc_code[i++] = (val >> 16) & 0xFF;
 298                         ecc_code[i++] = (val >>  8) & 0xFF;
 299                         ecc_code[i++] = (val >>  0) & 0xFF;
 300                         ptr--;
 301                 }
 302                 break;
 303         case OMAP_ECC_BCH16_CODE_HW:
 304                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
 305                 ecc_code[i++] = (val >>  8) & 0xFF;
 306                 ecc_code[i++] = (val >>  0) & 0xFF;
 307                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
 308                 ecc_code[i++] = (val >> 24) & 0xFF;
 309                 ecc_code[i++] = (val >> 16) & 0xFF;
 310                 ecc_code[i++] = (val >>  8) & 0xFF;
 311                 ecc_code[i++] = (val >>  0) & 0xFF;
 312                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
 313                 ecc_code[i++] = (val >> 24) & 0xFF;
 314                 ecc_code[i++] = (val >> 16) & 0xFF;
 315                 ecc_code[i++] = (val >>  8) & 0xFF;
 316                 ecc_code[i++] = (val >>  0) & 0xFF;
 317                 for (j = 3; j >= 0; j--) {
 318                         val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
 319                                                                         );
 320                         ecc_code[i++] = (val >> 24) & 0xFF;
 321                         ecc_code[i++] = (val >> 16) & 0xFF;
 322                         ecc_code[i++] = (val >>  8) & 0xFF;
 323                         ecc_code[i++] = (val >>  0) & 0xFF;
 324                 }
 325                 break;
 326         default:
 327                 return -EINVAL;
 328         }
 329         /* ECC scheme specific syndrome customizations */
 330         switch (info->ecc_scheme) {
 331         case OMAP_ECC_HAM1_CODE_HW:
 332                 break;
 333 #ifdef CONFIG_BCH
 334         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 335
 336                 for (i = 0; i < chip->ecc.bytes; i++)
 337                         *(ecc_code + i) = *(ecc_code + i) ^
 338                                                 bch8_polynomial[i];
 339                 break;
 340 #endif
 341         case OMAP_ECC_BCH8_CODE_HW:
 342                 ecc_code[chip->ecc.bytes - 1] = 0x00;
 343                 break;
 344         case OMAP_ECC_BCH16_CODE_HW:
 345                 break;
 346         default:
 347                 return -EINVAL;
 348         }
 349         return 0;
 350 }
 351
 352 #ifdef CONFIG_NAND_OMAP_ELM
 353 /*
 354  * omap_correct_data_bch - Compares the ecc read from nand spare area
 355  * with ECC registers values and corrects one bit error if it has occured
 356  *
 357  * @mtd:        MTD device structure
 358  * @dat:        page data
 359  * @read_ecc:   ecc read from nand flash (ignored)
 360  * @calc_ecc:   ecc read from ECC registers
 361  *
 362  * @return 0 if data is OK or corrected, else returns -1
 363  */
 364 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
 365                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 366 {
 367         struct nand_chip *chip = mtd->priv;
 368         struct omap_nand_info *info = chip->priv;
 369         struct nand_ecc_ctrl *ecc = &chip->ecc;
 370         uint32_t error_count = 0, error_max;
 371         uint32_t error_loc[ELM_MAX_ERROR_COUNT];
 372         enum bch_level bch_type;
 373         uint32_t i, ecc_flag = 0;
 374         uint8_t count, err = 0;
 375         uint32_t byte_pos, bit_pos;
 376
 377         /* check calculated ecc */
 378         for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
 379                 if (calc_ecc[i] != 0x00)
 380                         ecc_flag = 1;
 381         }
 382         if (!ecc_flag)
 383                 return 0;
 384
 385         /* check for whether its a erased-page */
 386         ecc_flag = 0;
 387         for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
 388                 if (read_ecc[i] != 0xff)
 389                         ecc_flag = 1;
 390         }
 391         if (!ecc_flag)
 392                 return 0;
 393
 394         /*
 395          * while reading ECC result we read it in big endian.
 396          * Hence while loading to ELM we have rotate to get the right endian.
 397          */
 398         switch (info->ecc_scheme) {
 399         case OMAP_ECC_BCH8_CODE_HW:
 400                 bch_type = BCH_8_BIT;
 401                 omap_reverse_list(calc_ecc, ecc->bytes - 1);
 402                 break;
 403         case OMAP_ECC_BCH16_CODE_HW:
 404                 bch_type = BCH_16_BIT;
 405                 omap_reverse_list(calc_ecc, ecc->bytes);
 406                 break;
 407         default:
 408                 return -EINVAL;
 409         }
 410         /* use elm module to check for errors */
 411         elm_config(bch_type);
 412         err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc);
 413         if (err)
 414                 return err;
 415
 416         /* correct bch error */
 417         for (count = 0; count < error_count; count++) {
 418                 switch (info->ecc_scheme) {
 419                 case OMAP_ECC_BCH8_CODE_HW:
 420                         /* 14th byte in ECC is reserved to match ROM layout */
 421                         error_max = SECTOR_BYTES + (ecc->bytes - 1);
 422                         break;
 423                 case OMAP_ECC_BCH16_CODE_HW:
 424                         error_max = SECTOR_BYTES + ecc->bytes;
 425                         break;
 426                 default:
 427                         return -EINVAL;
 428                 }
 429                 byte_pos = error_max - (error_loc[count] / 8) - 1;
 430                 bit_pos  = error_loc[count] % 8;
 431                 if (byte_pos < SECTOR_BYTES) {
 432                         dat[byte_pos] ^= 1 << bit_pos;
 433                         printf("nand: bit-flip corrected @data=%d\n", byte_pos);
 434                 } else if (byte_pos < error_max) {
 435                         read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos;
 436                         printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
 437                                                                 SECTOR_BYTES);
 438                 } else {
 439                         err = -EBADMSG;
 440                         printf("nand: error: invalid bit-flip location\n");
 441                 }
 442         }
 443         return (err) ? err : error_count;
 444 }
 445
 446 /**
 447  * omap_read_page_bch - hardware ecc based page read function
 448  * @mtd:        mtd info structure
 449  * @chip:       nand chip info structure
 450  * @buf:        buffer to store read data
 451  * @oob_required: caller expects OOB data read to chip->oob_poi
 452  * @page:       page number to read
 453  *
 454  */
 455 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
 456                                 uint8_t *buf, int oob_required, int page)
 457 {
 458         int i, eccsize = chip->ecc.size;
 459         int eccbytes = chip->ecc.bytes;
 460         int eccsteps = chip->ecc.steps;
 461         uint8_t *p = buf;
 462         uint8_t *ecc_calc = chip->buffers->ecccalc;
 463         uint8_t *ecc_code = chip->buffers->ecccode;
 464         uint32_t *eccpos = chip->ecc.layout->eccpos;
 465         uint8_t *oob = chip->oob_poi;
 466         uint32_t data_pos;
 467         uint32_t oob_pos;
 468
 469         data_pos = 0;
 470         /* oob area start */
 471         oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
 472         oob += chip->ecc.layout->eccpos[0];
 473
 474         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
 475                                 oob += eccbytes) {
 476                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 477                 /* read data */
 478                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);
 479                 chip->read_buf(mtd, p, eccsize);
 480
 481                 /* read respective ecc from oob area */
 482                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
 483                 chip->read_buf(mtd, oob, eccbytes);
 484                 /* read syndrome */
 485                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 486
 487                 data_pos += eccsize;
 488                 oob_pos += eccbytes;
 489         }
 490
 491         for (i = 0; i < chip->ecc.total; i++)
 492                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 493
 494         eccsteps = chip->ecc.steps;
 495         p = buf;
 496
 497         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 498                 int stat;
 499
 500                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 501                 if (stat < 0)
 502                         mtd->ecc_stats.failed++;
 503                 else
 504                         mtd->ecc_stats.corrected += stat;
 505         }
 506         return 0;
 507 }
 508 #endif /* CONFIG_NAND_OMAP_ELM */
 509
 510 /*
 511  * OMAP3 BCH8 support (with BCH library)
 512  */
 513 #ifdef CONFIG_BCH
 514 /**
 515  * omap_correct_data_bch_sw - Decode received data and correct errors
 516  * @mtd: MTD device structure
 517  * @data: page data
 518  * @read_ecc: ecc read from nand flash
 519  * @calc_ecc: ecc read from HW ECC registers
 520  */
 521 static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
 522                                  u_char *read_ecc, u_char *calc_ecc)
 523 {
 524         int i, count;
 525         /* cannot correct more than 8 errors */
 526         unsigned int errloc[8];
 527         struct nand_chip *chip = mtd->priv;
 528         struct omap_nand_info *info = chip->priv;
 529
 530         count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
 531                                                         NULL, errloc);
 532         if (count > 0) {
 533                 /* correct errors */
 534                 for (i = 0; i < count; i++) {
 535                         /* correct data only, not ecc bytes */
 536                         if (errloc[i] < 8*512)
 537                                 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
 538                         printf("corrected bitflip %u\n", errloc[i]);
 539 #ifdef DEBUG
 540                         puts("read_ecc: ");
 541                         /*
 542                          * BCH8 have 13 bytes of ECC; BCH4 needs adoption
 543                          * here!
 544                          */
 545                         for (i = 0; i < 13; i++)
 546                                 printf("%02x ", read_ecc[i]);
 547                         puts("\n");
 548                         puts("calc_ecc: ");
 549                         for (i = 0; i < 13; i++)
 550                                 printf("%02x ", calc_ecc[i]);
 551                         puts("\n");
 552 #endif
 553                 }
 554         } else if (count < 0) {
 555                 puts("ecc unrecoverable error\n");
 556         }
 557         return count;
 558 }
 559
 560 /**
 561  * omap_free_bch - Release BCH ecc resources
 562  * @mtd: MTD device structure
 563  */
 564 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
 565 {
 566         struct nand_chip *chip = mtd->priv;
 567         struct omap_nand_info *info = chip->priv;
 568
 569         if (info->control) {
 570                 free_bch(info->control);
 571                 info->control = NULL;
 572         }
 573 }
 574 #endif /* CONFIG_BCH */
 575
 576 /**
 577  * omap_select_ecc_scheme - configures driver for particular ecc-scheme
 578  * @nand: NAND chip device structure
 579  * @ecc_scheme: ecc scheme to configure
 580  * @pagesize: number of main-area bytes per page of NAND device
 581  * @oobsize: number of OOB/spare bytes per page of NAND device
 582  */
 583 static int omap_select_ecc_scheme(struct nand_chip *nand,
 584         enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
 585         struct omap_nand_info   *info           = nand->priv;
 586         struct nand_ecclayout   *ecclayout      = &omap_ecclayout;
 587         int eccsteps = pagesize / SECTOR_BYTES;
 588         int i;
 589
 590         switch (ecc_scheme) {
 591         case OMAP_ECC_HAM1_CODE_SW:
 592                 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
 593                 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
 594                  * initialized in nand_scan_tail(), so just set ecc.mode */
 595                 info->control           = NULL;
 596                 nand->ecc.mode          = NAND_ECC_SOFT;
 597                 nand->ecc.layout        = NULL;
 598                 nand->ecc.size          = 0;
 599                 break;
 600
 601         case OMAP_ECC_HAM1_CODE_HW:
 602                 debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
 603                 /* check ecc-scheme requirements before updating ecc info */
 604                 if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 605                         printf("nand: error: insufficient OOB: require=%d\n", (
 606                                 (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 607                         return -EINVAL;
 608                 }
 609                 info->control           = NULL;
 610                 /* populate ecc specific fields */
 611                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 612                 nand->ecc.mode          = NAND_ECC_HW;
 613                 nand->ecc.strength      = 1;
 614                 nand->ecc.size          = SECTOR_BYTES;
 615                 nand->ecc.bytes         = 3;
 616                 nand->ecc.hwctl         = omap_enable_hwecc;
 617                 nand->ecc.correct       = omap_correct_data;
 618                 nand->ecc.calculate     = omap_calculate_ecc;
 619                 /* define ecc-layout */
 620                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 621                 for (i = 0; i < ecclayout->eccbytes; i++) {
 622                         if (nand->options & NAND_BUSWIDTH_16)
 623                                 ecclayout->eccpos[i] = i + 2;
 624                         else
 625                                 ecclayout->eccpos[i] = i + 1;
 626                 }
 627                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 628                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 629                                                 BADBLOCK_MARKER_LENGTH;
 630                 break;
 631
 632         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 633 #ifdef CONFIG_BCH
 634                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
 635                 /* check ecc-scheme requirements before updating ecc info */
 636                 if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 637                         printf("nand: error: insufficient OOB: require=%d\n", (
 638                                 (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 639                         return -EINVAL;
 640                 }
 641                 /* check if BCH S/W library can be used for error detection */
 642                 info->control = init_bch(13, 8, 0x201b);
 643                 if (!info->control) {
 644                         printf("nand: error: could not init_bch()\n");
 645                         return -ENODEV;
 646                 }
 647                 /* populate ecc specific fields */
 648                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 649                 nand->ecc.mode          = NAND_ECC_HW;
 650                 nand->ecc.strength      = 8;
 651                 nand->ecc.size          = SECTOR_BYTES;
 652                 nand->ecc.bytes         = 13;
 653                 nand->ecc.hwctl         = omap_enable_hwecc;
 654                 nand->ecc.correct       = omap_correct_data_bch_sw;
 655                 nand->ecc.calculate     = omap_calculate_ecc;
 656                 /* define ecc-layout */
 657                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 658                 ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
 659                 for (i = 1; i < ecclayout->eccbytes; i++) {
 660                         if (i % nand->ecc.bytes)
 661                                 ecclayout->eccpos[i] =
 662                                                 ecclayout->eccpos[i - 1] + 1;
 663                         else
 664                                 ecclayout->eccpos[i] =
 665                                                 ecclayout->eccpos[i - 1] + 2;
 666                 }
 667                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 668                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 669                                                 BADBLOCK_MARKER_LENGTH;
 670                 break;
 671 #else
 672                 printf("nand: error: CONFIG_BCH required for ECC\n");
 673                 return -EINVAL;
 674 #endif
 675
 676         case OMAP_ECC_BCH8_CODE_HW:
 677 #ifdef CONFIG_NAND_OMAP_ELM
 678                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
 679                 /* check ecc-scheme requirements before updating ecc info */
 680                 if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 681                         printf("nand: error: insufficient OOB: require=%d\n", (
 682                                 (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 683                         return -EINVAL;
 684                 }
 685                 /* intialize ELM for ECC error detection */
 686                 elm_init();
 687                 info->control           = NULL;
 688                 /* populate ecc specific fields */
 689                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 690                 nand->ecc.mode          = NAND_ECC_HW;
 691                 nand->ecc.strength      = 8;
 692                 nand->ecc.size          = SECTOR_BYTES;
 693                 nand->ecc.bytes         = 14;
 694                 nand->ecc.hwctl         = omap_enable_hwecc;
 695                 nand->ecc.correct       = omap_correct_data_bch;
 696                 nand->ecc.calculate     = omap_calculate_ecc;
 697                 nand->ecc.read_page     = omap_read_page_bch;
 698                 /* define ecc-layout */
 699                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 700                 for (i = 0; i < ecclayout->eccbytes; i++)
 701                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
 702                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 703                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 704                                                 BADBLOCK_MARKER_LENGTH;
 705                 break;
 706 #else
 707                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
 708                 return -EINVAL;
 709 #endif
 710
 711         case OMAP_ECC_BCH16_CODE_HW:
 712 #ifdef CONFIG_NAND_OMAP_ELM
 713                 debug("nand: using OMAP_ECC_BCH16_CODE_HW\n");
 714                 /* check ecc-scheme requirements before updating ecc info */
 715                 if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 716                         printf("nand: error: insufficient OOB: require=%d\n", (
 717                                 (26 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 718                         return -EINVAL;
 719                 }
 720                 /* intialize ELM for ECC error detection */
 721                 elm_init();
 722                 /* populate ecc specific fields */
 723                 nand->ecc.mode          = NAND_ECC_HW;
 724                 nand->ecc.size          = SECTOR_BYTES;
 725                 nand->ecc.bytes         = 26;
 726                 nand->ecc.strength      = 16;
 727                 nand->ecc.hwctl         = omap_enable_hwecc;
 728                 nand->ecc.correct       = omap_correct_data_bch;
 729                 nand->ecc.calculate     = omap_calculate_ecc;
 730                 nand->ecc.read_page     = omap_read_page_bch;
 731                 /* define ecc-layout */
 732                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 733                 for (i = 0; i < ecclayout->eccbytes; i++)
 734                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
 735                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 736                 ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes -
 737                                                 BADBLOCK_MARKER_LENGTH;
 738                 break;
 739 #else
 740                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
 741                 return -EINVAL;
 742 #endif
 743         default:
 744                 debug("nand: error: ecc scheme not enabled or supported\n");
 745                 return -EINVAL;
 746         }
 747
 748         /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
 749         if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
 750                 nand->ecc.layout = ecclayout;
 751
 752         info->ecc_scheme = ecc_scheme;
 753         return 0;
 754 }
 755
 756 #ifndef CONFIG_SPL_BUILD
 757 /*
 758  * omap_nand_switch_ecc - switch the ECC operation between different engines
 759  * (h/w and s/w) and different algorithms (hamming and BCHx)
 760  *
 761  * @hardware            - true if one of the HW engines should be used
 762  * @eccstrength         - the number of bits that could be corrected
 763  *                        (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
 764  */
 765 int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
 766 {
 767         struct nand_chip *nand;
 768         struct mtd_info *mtd;
 769         int err = 0;
 770
 771         if (nand_curr_device < 0 ||
 772             nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
 773             !nand_info[nand_curr_device].name) {
 774                 printf("nand: error: no NAND devices found\n");
 775                 return -ENODEV;
 776         }
 777
 778         mtd = &nand_info[nand_curr_device];
 779         nand = mtd->priv;
 780         nand->options |= NAND_OWN_BUFFERS;
 781         nand->options &= ~NAND_SUBPAGE_READ;
 782         /* Setup the ecc configurations again */
 783         if (hardware) {
 784                 if (eccstrength == 1) {
 785                         err = omap_select_ecc_scheme(nand,
 786                                         OMAP_ECC_HAM1_CODE_HW,
 787                                         mtd->writesize, mtd->oobsize);
 788                 } else if (eccstrength == 8) {
 789                         err = omap_select_ecc_scheme(nand,
 790                                         OMAP_ECC_BCH8_CODE_HW,
 791                                         mtd->writesize, mtd->oobsize);
 792                 } else {
 793                         printf("nand: error: unsupported ECC scheme\n");
 794                         return -EINVAL;
 795                 }
 796         } else {
 797                 err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
 798                                         mtd->writesize, mtd->oobsize);
 799         }
 800
 801         /* Update NAND handling after ECC mode switch */
 802         if (!err)
 803                 err = nand_scan_tail(mtd);
 804         return err;
 805 }
 806 #endif /* CONFIG_SPL_BUILD */
 807
 808 /*
 809  * Board-specific NAND initialization. The following members of the
 810  * argument are board-specific:
 811  * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
 812  * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
 813  * - cmd_ctrl: hardwarespecific function for accesing control-lines
 814  * - waitfunc: hardwarespecific function for accesing device ready/busy line
 815  * - ecc.hwctl: function to enable (reset) hardware ecc generator
 816  * - ecc.mode: mode of ecc, see defines
 817  * - chip_delay: chip dependent delay for transfering data from array to
 818  *   read regs (tR)
 819  * - options: various chip options. They can partly be set to inform
 820  *   nand_scan about special functionality. See the defines for further
 821  *   explanation
 822  */
 823 int board_nand_init(struct nand_chip *nand)
 824 {
 825         int32_t gpmc_config = 0;
 826         int cs = cs_next++;
 827         int err = 0;
 828         /*
 829          * xloader/Uboot's gpmc configuration would have configured GPMC for
 830          * nand type of memory. The following logic scans and latches on to the
 831          * first CS with NAND type memory.
 832          * TBD: need to make this logic generic to handle multiple CS NAND
 833          * devices.
 834          */
 835         while (cs < GPMC_MAX_CS) {
 836                 /* Check if NAND type is set */
 837                 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
 838                         /* Found it!! */
 839                         break;
 840                 }
 841                 cs++;
 842         }
 843         if (cs >= GPMC_MAX_CS) {
 844                 printf("nand: error: Unable to find NAND settings in "
 845                         "GPMC Configuration - quitting\n");
 846                 return -ENODEV;
 847         }
 848
 849         gpmc_config = readl(&gpmc_cfg->config);
 850         /* Disable Write protect */
 851         gpmc_config |= 0x10;
 852         writel(gpmc_config, &gpmc_cfg->config);
 853
 854         nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
 855         nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
 856         omap_nand_info[cs].control = NULL;
 857         omap_nand_info[cs].cs = cs;
 858         nand->priv      = &omap_nand_info[cs];
 859         nand->cmd_ctrl  = omap_nand_hwcontrol;
 860         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
 861         nand->chip_delay = 100;
 862         nand->ecc.layout = &omap_ecclayout;
 863
 864         /* configure driver and controller based on NAND device bus-width */
 865         gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
 866 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
 867         nand->options |= NAND_BUSWIDTH_16;
 868         writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
 869 #else
 870         nand->options &= ~NAND_BUSWIDTH_16;
 871         writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
 872 #endif
 873         /* select ECC scheme */
 874 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
 875         err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
 876                         CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
 877 #else
 878         /* pagesize and oobsize are not required to configure sw ecc-scheme */
 879         err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
 880                         0, 0);
 881 #endif
 882         if (err)
 883                 return err;
 884
 885 #ifdef CONFIG_SPL_BUILD
 886         if (nand->options & NAND_BUSWIDTH_16)
 887                 nand->read_buf = nand_read_buf16;
 888         else
 889                 nand->read_buf = nand_read_buf;
 890         nand->dev_ready = omap_spl_dev_ready;
 891 #endif
 892         return 0;
 893 }