drivers/mtd/nand/omap_gpmc.c

   1 /*
   2  * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
   3  * Rohit Choraria <rohitkc@ti.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/mem.h>
  12 #include <linux/mtd/omap_gpmc.h>
  13 #include <linux/mtd/nand_ecc.h>
  14 #include <linux/bch.h>
  15 #include <linux/compiler.h>
  16 #include <nand.h>
  17 #include <linux/mtd/omap_elm.h>
  18
  19 #define BADBLOCK_MARKER_LENGTH  2
  20 #define SECTOR_BYTES            512
  21 #define ECCCLEAR                (0x1 << 8)
  22 #define ECCRESULTREG1           (0x1 << 0)
  23 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
  24 #define BCH4_BIT_PAD            4
  25
  26 #ifdef CONFIG_BCH
  27 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
  28                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
  29 #endif
  30 static uint8_t cs;
  31 static __maybe_unused struct nand_ecclayout omap_ecclayout;
  32
  33 /*
  34  * omap_nand_hwcontrol - Set the address pointers corretly for the
  35  *                      following address/data/command operation
  36  */
  37 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
  38                                 uint32_t ctrl)
  39 {
  40         register struct nand_chip *this = mtd->priv;
  41
  42         /*
  43          * Point the IO_ADDR to DATA and ADDRESS registers instead
  44          * of chip address
  45          */
  46         switch (ctrl) {
  47         case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
  48                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
  49                 break;
  50         case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
  51                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
  52                 break;
  53         case NAND_CTRL_CHANGE | NAND_NCE:
  54                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
  55                 break;
  56         }
  57
  58         if (cmd != NAND_CMD_NONE)
  59                 writeb(cmd, this->IO_ADDR_W);
  60 }
  61
  62 #ifdef CONFIG_SPL_BUILD
  63 /* Check wait pin as dev ready indicator */
  64 int omap_spl_dev_ready(struct mtd_info *mtd)
  65 {
  66         return gpmc_cfg->status & (1 << 8);
  67 }
  68 #endif
  69
  70
  71 /*
  72  * gen_true_ecc - This function will generate true ECC value, which
  73  * can be used when correcting data read from NAND flash memory core
  74  *
  75  * @ecc_buf:    buffer to store ecc code
  76  *
  77  * @return:     re-formatted ECC value
  78  */
  79 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
  80 {
  81         return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
  82                 ((ecc_buf[2] & 0x0F) << 8);
  83 }
  84
  85 /*
  86  * omap_correct_data - Compares the ecc read from nand spare area with ECC
  87  * registers values and corrects one bit error if it has occured
  88  * Further details can be had from OMAP TRM and the following selected links:
  89  * http://en.wikipedia.org/wiki/Hamming_code
  90  * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
  91  *
  92  * @mtd:                 MTD device structure
  93  * @dat:                 page data
  94  * @read_ecc:            ecc read from nand flash
  95  * @calc_ecc:            ecc read from ECC registers
  96  *
  97  * @return 0 if data is OK or corrected, else returns -1
  98  */
  99 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 100                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 101 {
 102         uint32_t orig_ecc, new_ecc, res, hm;
 103         uint16_t parity_bits, byte;
 104         uint8_t bit;
 105
 106         /* Regenerate the orginal ECC */
 107         orig_ecc = gen_true_ecc(read_ecc);
 108         new_ecc = gen_true_ecc(calc_ecc);
 109         /* Get the XOR of real ecc */
 110         res = orig_ecc ^ new_ecc;
 111         if (res) {
 112                 /* Get the hamming width */
 113                 hm = hweight32(res);
 114                 /* Single bit errors can be corrected! */
 115                 if (hm == 12) {
 116                         /* Correctable data! */
 117                         parity_bits = res >> 16;
 118                         bit = (parity_bits & 0x7);
 119                         byte = (parity_bits >> 3) & 0x1FF;
 120                         /* Flip the bit to correct */
 121                         dat[byte] ^= (0x1 << bit);
 122                 } else if (hm == 1) {
 123                         printf("Error: Ecc is wrong\n");
 124                         /* ECC itself is corrupted */
 125                         return 2;
 126                 } else {
 127                         /*
 128                          * hm distance != parity pairs OR one, could mean 2 bit
 129                          * error OR potentially be on a blank page..
 130                          * orig_ecc: contains spare area data from nand flash.
 131                          * new_ecc: generated ecc while reading data area.
 132                          * Note: if the ecc = 0, all data bits from which it was
 133                          * generated are 0xFF.
 134                          * The 3 byte(24 bits) ecc is generated per 512byte
 135                          * chunk of a page. If orig_ecc(from spare area)
 136                          * is 0xFF && new_ecc(computed now from data area)=0x0,
 137                          * this means that data area is 0xFF and spare area is
 138                          * 0xFF. A sure sign of a erased page!
 139                          */
 140                         if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
 141                                 return 0;
 142                         printf("Error: Bad compare! failed\n");
 143                         /* detected 2 bit error */
 144                         return -1;
 145                 }
 146         }
 147         return 0;
 148 }
 149
 150 /*
 151  * Generic BCH interface
 152  */
 153 struct nand_bch_priv {
 154         uint8_t mode;
 155         uint8_t type;
 156         struct bch_control *control;
 157         enum omap_ecc ecc_scheme;
 158 };
 159
 160 /* bch types */
 161 #define ECC_BCH4        0
 162 #define ECC_BCH8        1
 163 #define ECC_BCH16       2
 164
 165 /*
 166  * This can be a single instance cause all current users have only one NAND
 167  * with nearly the same setup (BCH8, some with ELM and others with sw BCH
 168  * library).
 169  * When some users with other BCH strength will exists this have to change!
 170  */
 171 static __maybe_unused struct nand_bch_priv bch_priv = {
 172         .type = ECC_BCH8,
 173         .control = NULL
 174 };
 175
 176 /*
 177  * omap_reverse_list - re-orders list elements in reverse order [internal]
 178  * @list:       pointer to start of list
 179  * @length:     length of list
 180 */
 181 void omap_reverse_list(u8 *list, unsigned int length)
 182 {
 183         unsigned int i, j;
 184         unsigned int half_length = length / 2;
 185         u8 tmp;
 186         for (i = 0, j = length - 1; i < half_length; i++, j--) {
 187                 tmp = list[i];
 188                 list[i] = list[j];
 189                 list[j] = tmp;
 190         }
 191 }
 192
 193 /*
 194  * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
 195  * @mtd:        MTD device structure
 196  * @mode:       Read/Write mode
 197  */
 198 __maybe_unused
 199 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 200 {
 201         struct nand_chip        *nand   = mtd->priv;
 202         struct nand_bch_priv    *bch    = nand->priv;
 203         unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
 204         unsigned int ecc_algo = 0;
 205         unsigned int bch_type = 0;
 206         unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
 207         u32 ecc_size_config_val = 0;
 208         u32 ecc_config_val = 0;
 209
 210         /* configure GPMC for specific ecc-scheme */
 211         switch (bch->ecc_scheme) {
 212         case OMAP_ECC_HAM1_CODE_SW:
 213                 return;
 214         case OMAP_ECC_HAM1_CODE_HW:
 215                 ecc_algo = 0x0;
 216                 bch_type = 0x0;
 217                 bch_wrapmode = 0x00;
 218                 eccsize0 = 0xFF;
 219                 eccsize1 = 0xFF;
 220                 break;
 221         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 222         case OMAP_ECC_BCH8_CODE_HW:
 223                 ecc_algo = 0x1;
 224                 bch_type = 0x1;
 225                 if (mode == NAND_ECC_WRITE) {
 226                         bch_wrapmode = 0x01;
 227                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 228                         eccsize1 = 28; /* OOB bits in nibbles per sector */
 229                 } else {
 230                         bch_wrapmode = 0x01;
 231                         eccsize0 = 26; /* ECC bits in nibbles per sector */
 232                         eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
 233                 }
 234                 break;
 235         default:
 236                 return;
 237         }
 238         /* Clear ecc and enable bits */
 239         writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
 240         /* Configure ecc size for BCH */
 241         ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
 242         writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
 243
 244         /* Configure device details for BCH engine */
 245         ecc_config_val = ((ecc_algo << 16)      | /* HAM1 | BCHx */
 246                         (bch_type << 12)        | /* BCH4/BCH8/BCH16 */
 247                         (bch_wrapmode << 8)     | /* wrap mode */
 248                         (dev_width << 7)        | /* bus width */
 249                         (0x0 << 4)              | /* number of sectors */
 250                         (cs <<  1)              | /* ECC CS */
 251                         (0x1));                   /* enable ECC */
 252         writel(ecc_config_val, &gpmc_cfg->ecc_config);
 253 }
 254
 255 /*
 256  *  omap_calculate_ecc - Read ECC result
 257  *  @mtd:       MTD structure
 258  *  @dat:       unused
 259  *  @ecc_code:  ecc_code buffer
 260  *  Using noninverted ECC can be considered ugly since writing a blank
 261  *  page ie. padding will clear the ECC bytes. This is no problem as
 262  *  long nobody is trying to write data on the seemingly unused page.
 263  *  Reading an erased page will produce an ECC mismatch between
 264  *  generated and read ECC bytes that has to be dealt with separately.
 265  *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
 266  *  is used, the result of read will be 0x0 while the ECC offsets of the
 267  *  spare area will be 0xFF which will result in an ECC mismatch.
 268  */
 269 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 270                                 uint8_t *ecc_code)
 271 {
 272         struct nand_chip *chip = mtd->priv;
 273         struct nand_bch_priv *bch = chip->priv;
 274         uint32_t *ptr, val = 0;
 275         int8_t i = 0, j;
 276
 277         switch (bch->ecc_scheme) {
 278         case OMAP_ECC_HAM1_CODE_HW:
 279                 val = readl(&gpmc_cfg->ecc1_result);
 280                 ecc_code[0] = val & 0xFF;
 281                 ecc_code[1] = (val >> 16) & 0xFF;
 282                 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
 283                 break;
 284 #ifdef CONFIG_BCH
 285         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 286 #endif
 287         case OMAP_ECC_BCH8_CODE_HW:
 288                 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
 289                 val = readl(ptr);
 290                 ecc_code[i++] = (val >>  0) & 0xFF;
 291                 ptr--;
 292                 for (j = 0; j < 3; j++) {
 293                         val = readl(ptr);
 294                         ecc_code[i++] = (val >> 24) & 0xFF;
 295                         ecc_code[i++] = (val >> 16) & 0xFF;
 296                         ecc_code[i++] = (val >>  8) & 0xFF;
 297                         ecc_code[i++] = (val >>  0) & 0xFF;
 298                         ptr--;
 299                 }
 300                 break;
 301         default:
 302                 return -EINVAL;
 303         }
 304         /* ECC scheme specific syndrome customizations */
 305         switch (bch->ecc_scheme) {
 306         case OMAP_ECC_HAM1_CODE_HW:
 307                 break;
 308 #ifdef CONFIG_BCH
 309         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 310
 311                 for (i = 0; i < chip->ecc.bytes; i++)
 312                         *(ecc_code + i) = *(ecc_code + i) ^
 313                                                 bch8_polynomial[i];
 314                 break;
 315 #endif
 316         case OMAP_ECC_BCH8_CODE_HW:
 317                 ecc_code[chip->ecc.bytes - 1] = 0x00;
 318                 break;
 319         default:
 320                 return -EINVAL;
 321         }
 322         return 0;
 323 }
 324
 325 #ifdef CONFIG_NAND_OMAP_ELM
 326 /*
 327  * omap_correct_data_bch - Compares the ecc read from nand spare area
 328  * with ECC registers values and corrects one bit error if it has occured
 329  *
 330  * @mtd:        MTD device structure
 331  * @dat:        page data
 332  * @read_ecc:   ecc read from nand flash (ignored)
 333  * @calc_ecc:   ecc read from ECC registers
 334  *
 335  * @return 0 if data is OK or corrected, else returns -1
 336  */
 337 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
 338                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 339 {
 340         struct nand_chip *chip = mtd->priv;
 341         struct nand_bch_priv *bch = chip->priv;
 342         uint32_t eccbytes = chip->ecc.bytes;
 343         uint32_t error_count = 0, error_max;
 344         uint32_t error_loc[8];
 345         uint32_t i, ecc_flag = 0;
 346         uint8_t count, err = 0;
 347         uint32_t byte_pos, bit_pos;
 348
 349         /* check calculated ecc */
 350         for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
 351                 if (calc_ecc[i] != 0x00)
 352                         ecc_flag = 1;
 353         }
 354         if (!ecc_flag)
 355                 return 0;
 356
 357         /* check for whether its a erased-page */
 358         ecc_flag = 0;
 359         for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
 360                 if (read_ecc[i] != 0xff)
 361                         ecc_flag = 1;
 362         }
 363         if (!ecc_flag)
 364                 return 0;
 365
 366         /*
 367          * while reading ECC result we read it in big endian.
 368          * Hence while loading to ELM we have rotate to get the right endian.
 369          */
 370         switch (bch->ecc_scheme) {
 371         case OMAP_ECC_BCH8_CODE_HW:
 372                 omap_reverse_list(calc_ecc, eccbytes - 1);
 373                 break;
 374         default:
 375                 return -EINVAL;
 376         }
 377         /* use elm module to check for errors */
 378         elm_config((enum bch_level)(bch->type));
 379         if (elm_check_error(calc_ecc, (enum bch_level)bch->type,
 380                                         &error_count, error_loc)) {
 381                 printf("nand: error: uncorrectable ECC errors\n");
 382                 return -EINVAL;
 383         }
 384         /* correct bch error */
 385         for (count = 0; count < error_count; count++) {
 386                 switch (bch->type) {
 387                 case ECC_BCH8:
 388                         /* 14th byte in ECC is reserved to match ROM layout */
 389                         error_max = SECTOR_BYTES + (eccbytes - 1);
 390                         break;
 391                 default:
 392                         return -EINVAL;
 393                 }
 394                 byte_pos = error_max - (error_loc[count] / 8) - 1;
 395                 bit_pos  = error_loc[count] % 8;
 396                 if (byte_pos < SECTOR_BYTES) {
 397                         dat[byte_pos] ^= 1 << bit_pos;
 398                         printf("nand: bit-flip corrected @data=%d\n", byte_pos);
 399                 } else if (byte_pos < error_max) {
 400                         read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos;
 401                         printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
 402                                                                 SECTOR_BYTES);
 403                 } else {
 404                         err = -EBADMSG;
 405                         printf("nand: error: invalid bit-flip location\n");
 406                 }
 407         }
 408         return (err) ? err : error_count;
 409 }
 410
 411 /**
 412  * omap_read_page_bch - hardware ecc based page read function
 413  * @mtd:        mtd info structure
 414  * @chip:       nand chip info structure
 415  * @buf:        buffer to store read data
 416  * @oob_required: caller expects OOB data read to chip->oob_poi
 417  * @page:       page number to read
 418  *
 419  */
 420 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
 421                                 uint8_t *buf, int oob_required, int page)
 422 {
 423         int i, eccsize = chip->ecc.size;
 424         int eccbytes = chip->ecc.bytes;
 425         int eccsteps = chip->ecc.steps;
 426         uint8_t *p = buf;
 427         uint8_t *ecc_calc = chip->buffers->ecccalc;
 428         uint8_t *ecc_code = chip->buffers->ecccode;
 429         uint32_t *eccpos = chip->ecc.layout->eccpos;
 430         uint8_t *oob = chip->oob_poi;
 431         uint32_t data_pos;
 432         uint32_t oob_pos;
 433
 434         data_pos = 0;
 435         /* oob area start */
 436         oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
 437         oob += chip->ecc.layout->eccpos[0];
 438
 439         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
 440                                 oob += eccbytes) {
 441                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 442                 /* read data */
 443                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
 444                 chip->read_buf(mtd, p, eccsize);
 445
 446                 /* read respective ecc from oob area */
 447                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
 448                 chip->read_buf(mtd, oob, eccbytes);
 449                 /* read syndrome */
 450                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 451
 452                 data_pos += eccsize;
 453                 oob_pos += eccbytes;
 454         }
 455
 456         for (i = 0; i < chip->ecc.total; i++)
 457                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 458
 459         eccsteps = chip->ecc.steps;
 460         p = buf;
 461
 462         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 463                 int stat;
 464
 465                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 466                 if (stat < 0)
 467                         mtd->ecc_stats.failed++;
 468                 else
 469                         mtd->ecc_stats.corrected += stat;
 470         }
 471         return 0;
 472 }
 473 #endif /* CONFIG_NAND_OMAP_ELM */
 474
 475 /*
 476  * OMAP3 BCH8 support (with BCH library)
 477  */
 478 #ifdef CONFIG_BCH
 479 /**
 480  * omap_correct_data_bch_sw - Decode received data and correct errors
 481  * @mtd: MTD device structure
 482  * @data: page data
 483  * @read_ecc: ecc read from nand flash
 484  * @calc_ecc: ecc read from HW ECC registers
 485  */
 486 static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
 487                                  u_char *read_ecc, u_char *calc_ecc)
 488 {
 489         int i, count;
 490         /* cannot correct more than 8 errors */
 491         unsigned int errloc[8];
 492         struct nand_chip *chip = mtd->priv;
 493         struct nand_bch_priv *chip_priv = chip->priv;
 494         struct bch_control *bch = chip_priv->control;
 495
 496         count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc);
 497         if (count > 0) {
 498                 /* correct errors */
 499                 for (i = 0; i < count; i++) {
 500                         /* correct data only, not ecc bytes */
 501                         if (errloc[i] < 8*512)
 502                                 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
 503                         printf("corrected bitflip %u\n", errloc[i]);
 504 #ifdef DEBUG
 505                         puts("read_ecc: ");
 506                         /*
 507                          * BCH8 have 13 bytes of ECC; BCH4 needs adoption
 508                          * here!
 509                          */
 510                         for (i = 0; i < 13; i++)
 511                                 printf("%02x ", read_ecc[i]);
 512                         puts("\n");
 513                         puts("calc_ecc: ");
 514                         for (i = 0; i < 13; i++)
 515                                 printf("%02x ", calc_ecc[i]);
 516                         puts("\n");
 517 #endif
 518                 }
 519         } else if (count < 0) {
 520                 puts("ecc unrecoverable error\n");
 521         }
 522         return count;
 523 }
 524
 525 /**
 526  * omap_free_bch - Release BCH ecc resources
 527  * @mtd: MTD device structure
 528  */
 529 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
 530 {
 531         struct nand_chip *chip = mtd->priv;
 532         struct nand_bch_priv *chip_priv = chip->priv;
 533         struct bch_control *bch = NULL;
 534
 535         if (chip_priv)
 536                 bch = chip_priv->control;
 537
 538         if (bch) {
 539                 free_bch(bch);
 540                 chip_priv->control = NULL;
 541         }
 542 }
 543 #endif /* CONFIG_BCH */
 544
 545 /**
 546  * omap_select_ecc_scheme - configures driver for particular ecc-scheme
 547  * @nand: NAND chip device structure
 548  * @ecc_scheme: ecc scheme to configure
 549  * @pagesize: number of main-area bytes per page of NAND device
 550  * @oobsize: number of OOB/spare bytes per page of NAND device
 551  */
 552 static int omap_select_ecc_scheme(struct nand_chip *nand,
 553         enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
 554         struct nand_bch_priv    *bch            = nand->priv;
 555         struct nand_ecclayout   *ecclayout      = &omap_ecclayout;
 556         int eccsteps = pagesize / SECTOR_BYTES;
 557         int i;
 558
 559         switch (ecc_scheme) {
 560         case OMAP_ECC_HAM1_CODE_SW:
 561                 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
 562                 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
 563                  * initialized in nand_scan_tail(), so just set ecc.mode */
 564                 bch_priv.control        = NULL;
 565                 bch_priv.type           = 0;
 566                 nand->ecc.mode          = NAND_ECC_SOFT;
 567                 nand->ecc.layout        = NULL;
 568                 nand->ecc.size          = 0;
 569                 bch->ecc_scheme         = OMAP_ECC_HAM1_CODE_SW;
 570                 break;
 571
 572         case OMAP_ECC_HAM1_CODE_HW:
 573                 debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
 574                 /* check ecc-scheme requirements before updating ecc info */
 575                 if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 576                         printf("nand: error: insufficient OOB: require=%d\n", (
 577                                 (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 578                         return -EINVAL;
 579                 }
 580                 bch_priv.control        = NULL;
 581                 bch_priv.type           = 0;
 582                 /* populate ecc specific fields */
 583                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 584                 nand->ecc.mode          = NAND_ECC_HW;
 585                 nand->ecc.strength      = 1;
 586                 nand->ecc.size          = SECTOR_BYTES;
 587                 nand->ecc.bytes         = 3;
 588                 nand->ecc.hwctl         = omap_enable_hwecc;
 589                 nand->ecc.correct       = omap_correct_data;
 590                 nand->ecc.calculate     = omap_calculate_ecc;
 591                 /* define ecc-layout */
 592                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 593                 for (i = 0; i < ecclayout->eccbytes; i++) {
 594                         if (nand->options & NAND_BUSWIDTH_16)
 595                                 ecclayout->eccpos[i] = i + 2;
 596                         else
 597                                 ecclayout->eccpos[i] = i + 1;
 598                 }
 599                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 600                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 601                                                 BADBLOCK_MARKER_LENGTH;
 602                 bch->ecc_scheme         = OMAP_ECC_HAM1_CODE_HW;
 603                 break;
 604
 605         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 606 #ifdef CONFIG_BCH
 607                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
 608                 /* check ecc-scheme requirements before updating ecc info */
 609                 if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 610                         printf("nand: error: insufficient OOB: require=%d\n", (
 611                                 (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 612                         return -EINVAL;
 613                 }
 614                 /* check if BCH S/W library can be used for error detection */
 615                 bch_priv.control = init_bch(13, 8, 0x201b);
 616                 if (!bch_priv.control) {
 617                         printf("nand: error: could not init_bch()\n");
 618                         return -ENODEV;
 619                 }
 620                 bch_priv.type = ECC_BCH8;
 621                 /* populate ecc specific fields */
 622                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 623                 nand->ecc.mode          = NAND_ECC_HW;
 624                 nand->ecc.strength      = 8;
 625                 nand->ecc.size          = SECTOR_BYTES;
 626                 nand->ecc.bytes         = 13;
 627                 nand->ecc.hwctl         = omap_enable_hwecc;
 628                 nand->ecc.correct       = omap_correct_data_bch_sw;
 629                 nand->ecc.calculate     = omap_calculate_ecc;
 630                 /* define ecc-layout */
 631                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 632                 ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
 633                 for (i = 1; i < ecclayout->eccbytes; i++) {
 634                         if (i % nand->ecc.bytes)
 635                                 ecclayout->eccpos[i] =
 636                                                 ecclayout->eccpos[i - 1] + 1;
 637                         else
 638                                 ecclayout->eccpos[i] =
 639                                                 ecclayout->eccpos[i - 1] + 2;
 640                 }
 641                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 642                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 643                                                 BADBLOCK_MARKER_LENGTH;
 644                 bch->ecc_scheme         = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
 645                 break;
 646 #else
 647                 printf("nand: error: CONFIG_BCH required for ECC\n");
 648                 return -EINVAL;
 649 #endif
 650
 651         case OMAP_ECC_BCH8_CODE_HW:
 652 #ifdef CONFIG_NAND_OMAP_ELM
 653                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
 654                 /* check ecc-scheme requirements before updating ecc info */
 655                 if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 656                         printf("nand: error: insufficient OOB: require=%d\n", (
 657                                 (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 658                         return -EINVAL;
 659                 }
 660                 /* intialize ELM for ECC error detection */
 661                 elm_init();
 662                 bch_priv.type           = ECC_BCH8;
 663                 /* populate ecc specific fields */
 664                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 665                 nand->ecc.mode          = NAND_ECC_HW;
 666                 nand->ecc.strength      = 8;
 667                 nand->ecc.size          = SECTOR_BYTES;
 668                 nand->ecc.bytes         = 14;
 669                 nand->ecc.hwctl         = omap_enable_hwecc;
 670                 nand->ecc.correct       = omap_correct_data_bch;
 671                 nand->ecc.calculate     = omap_calculate_ecc;
 672                 nand->ecc.read_page     = omap_read_page_bch;
 673                 /* define ecc-layout */
 674                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 675                 for (i = 0; i < ecclayout->eccbytes; i++)
 676                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
 677                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 678                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 679                                                 BADBLOCK_MARKER_LENGTH;
 680                 bch->ecc_scheme         = OMAP_ECC_BCH8_CODE_HW;
 681                 break;
 682 #else
 683                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
 684                 return -EINVAL;
 685 #endif
 686
 687         default:
 688                 debug("nand: error: ecc scheme not enabled or supported\n");
 689                 return -EINVAL;
 690         }
 691
 692         /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
 693         if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
 694                 nand->ecc.layout = ecclayout;
 695
 696         return 0;
 697 }
 698
 699 #ifndef CONFIG_SPL_BUILD
 700 /*
 701  * omap_nand_switch_ecc - switch the ECC operation between different engines
 702  * (h/w and s/w) and different algorithms (hamming and BCHx)
 703  *
 704  * @hardware            - true if one of the HW engines should be used
 705  * @eccstrength         - the number of bits that could be corrected
 706  *                        (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
 707  */
 708 int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
 709 {
 710         struct nand_chip *nand;
 711         struct mtd_info *mtd;
 712         int err = 0;
 713
 714         if (nand_curr_device < 0 ||
 715             nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
 716             !nand_info[nand_curr_device].name) {
 717                 printf("nand: error: no NAND devices found\n");
 718                 return -ENODEV;
 719         }
 720
 721         mtd = &nand_info[nand_curr_device];
 722         nand = mtd->priv;
 723         nand->options |= NAND_OWN_BUFFERS;
 724         nand->options &= ~NAND_SUBPAGE_READ;
 725         /* Setup the ecc configurations again */
 726         if (hardware) {
 727                 if (eccstrength == 1) {
 728                         err = omap_select_ecc_scheme(nand,
 729                                         OMAP_ECC_HAM1_CODE_HW,
 730                                         mtd->writesize, mtd->oobsize);
 731                 } else if (eccstrength == 8) {
 732                         err = omap_select_ecc_scheme(nand,
 733                                         OMAP_ECC_BCH8_CODE_HW,
 734                                         mtd->writesize, mtd->oobsize);
 735                 } else {
 736                         printf("nand: error: unsupported ECC scheme\n");
 737                         return -EINVAL;
 738                 }
 739         } else {
 740                 err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
 741                                         mtd->writesize, mtd->oobsize);
 742         }
 743
 744         /* Update NAND handling after ECC mode switch */
 745         if (!err)
 746                 err = nand_scan_tail(mtd);
 747         return err;
 748 }
 749 #endif /* CONFIG_SPL_BUILD */
 750
 751 /*
 752  * Board-specific NAND initialization. The following members of the
 753  * argument are board-specific:
 754  * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
 755  * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
 756  * - cmd_ctrl: hardwarespecific function for accesing control-lines
 757  * - waitfunc: hardwarespecific function for accesing device ready/busy line
 758  * - ecc.hwctl: function to enable (reset) hardware ecc generator
 759  * - ecc.mode: mode of ecc, see defines
 760  * - chip_delay: chip dependent delay for transfering data from array to
 761  *   read regs (tR)
 762  * - options: various chip options. They can partly be set to inform
 763  *   nand_scan about special functionality. See the defines for further
 764  *   explanation
 765  */
 766 int board_nand_init(struct nand_chip *nand)
 767 {
 768         int32_t gpmc_config = 0;
 769         cs = 0;
 770         int err = 0;
 771         /*
 772          * xloader/Uboot's gpmc configuration would have configured GPMC for
 773          * nand type of memory. The following logic scans and latches on to the
 774          * first CS with NAND type memory.
 775          * TBD: need to make this logic generic to handle multiple CS NAND
 776          * devices.
 777          */
 778         while (cs < GPMC_MAX_CS) {
 779                 /* Check if NAND type is set */
 780                 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
 781                         /* Found it!! */
 782                         break;
 783                 }
 784                 cs++;
 785         }
 786         if (cs >= GPMC_MAX_CS) {
 787                 printf("nand: error: Unable to find NAND settings in "
 788                         "GPMC Configuration - quitting\n");
 789                 return -ENODEV;
 790         }
 791
 792         gpmc_config = readl(&gpmc_cfg->config);
 793         /* Disable Write protect */
 794         gpmc_config |= 0x10;
 795         writel(gpmc_config, &gpmc_cfg->config);
 796
 797         nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
 798         nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
 799         nand->priv      = &bch_priv;
 800         nand->cmd_ctrl  = omap_nand_hwcontrol;
 801         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
 802         /* If we are 16 bit dev, our gpmc config tells us that */
 803         if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
 804                 nand->options |= NAND_BUSWIDTH_16;
 805
 806         nand->chip_delay = 100;
 807         nand->ecc.layout = &omap_ecclayout;
 808
 809         /* select ECC scheme */
 810 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
 811         err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
 812                         CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
 813 #else
 814         /* pagesize and oobsize are not required to configure sw ecc-scheme */
 815         err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
 816                         0, 0);
 817 #endif
 818         if (err)
 819                 return err;
 820
 821 #ifdef CONFIG_SPL_BUILD
 822         if (nand->options & NAND_BUSWIDTH_16)
 823                 nand->read_buf = nand_read_buf16;
 824         else
 825                 nand->read_buf = nand_read_buf;
 826         nand->dev_ready = omap_spl_dev_ready;
 827 #endif
 828
 829         return 0;
 830 }