LIST_4xx=" \
acadia ADCIOP alpr AP1000 \
- AR405 ASH405 bamboo bubinga \
- CANBT CMS700 CPCI2DP CPCI405 \
- CPCI4052 CPCI405AB CPCI405DT CPCI440 \
- CPCIISER4 CRAYL1 csb272 csb472 \
- DASA_SIM DP405 DU405 ebony \
- ERIC EXBITGEN G2000 HH405 \
- HUB405 JSE KAREF katmai \
- luan METROBOX MIP405 MIP405T \
- ML2 ml300 ocotea OCRTC \
- ORSG p3p440 PCI405 pcs440ep \
- PIP405 PLU405 PMC405 PPChameleonEVB \
- sbc405 sc3 sequoia sequoia_nand \
- taishan VOH405 VOM405 W7OLMC \
- W7OLMG walnut WUH405 XPEDITE1K \
- yellowstone yosemite yucca \
+ AR405 ASH405 bamboo bamboo_nand \
+ bubinga CANBT CMS700 CPCI2DP \
+ CPCI405 CPCI4052 CPCI405AB CPCI405DT \
+ CPCI440 CPCIISER4 CRAYL1 csb272 \
+ csb472 DASA_SIM DP405 DU405 \
+ ebony ERIC EXBITGEN G2000 \
+ HH405 HUB405 JSE KAREF \
+ katmai luan METROBOX MIP405 \
+ MIP405T ML2 ml300 ocotea \
+ OCRTC ORSG p3p440 PCI405 \
+ pcs440ep PIP405 PLU405 PMC405 \
+ PPChameleonEVB sbc405 sc3 sequoia \
+ sequoia_nand taishan VOH405 VOM405 \
+ W7OLMC W7OLMG walnut WUH405 \
+ XPEDITE1K yellowstone yosemite yucca \
"
#########################################################################
#########################################################################
LIST_83xx=" \
- MPC832XEMDS MPC8349EMDS MPC8349ITX MPC8349ITXGP \
- MPC8360EMDS sbc8349 TQM834x \
+ MPC8313ERDB MPC832XEMDS MPC8349EMDS MPC8349ITX \
+ MPC8349ITXGP MPC8360EMDS sbc8349 TQM834x \
"
#########################################################################
LIST_85xx=" \
- MPC8540ADS MPC8540EVAL MPC8541CDS MPC8548CDS \
- MPC8555CDS MPC8560ADS PM854 PM856 \
- sbc8540 sbc8560 stxgp3 TQM8540 \
- TQM8541 TQM8555 TQM8560 \
+ MPC8540ADS MPC8540EVAL MPC8541CDS MPC8544DS \
+ MPC8548CDS MPC8555CDS MPC8560ADS PM854 \
+ PM856 sbc8540 sbc8560 stxgp3 \
+ stxssa TQM8540 TQM8541 TQM8555 \
+ TQM8560 \
"
#########################################################################
LIST_74xx=" \
DB64360 DB64460 EVB64260 P3G4 \
p3m7448 PCIPPC2 PCIPPC6 ZUMA \
+ mpc7448hpc2
"
LIST_7xx=" \
CROSS_COMPILE = bfin-uclinux-
endif
ifeq ($(ARCH),avr32)
-CROSS_COMPILE = avr32-
+CROSS_COMPILE = avr32-linux-
endif
endif
endif
ifdef SOC
LIBS += cpu/$(CPU)/$(SOC)/lib$(SOC).a
endif
+ifeq ($(CPU),ixp)
+LIBS += cpu/ixp/npe/libnpe.a
+endif
LIBS += lib_$(ARCH)/lib$(ARCH).a
LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a
LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
"post/board/$(BOARDDIR)/libpost$(BOARD).a"; fi)
LIBS += common/libcommon.a
-LIBS += $(BOARDLIBS)
+LIBS += libfdt/libfdt.a
LIBS := $(addprefix $(obj),$(LIBS))
.PHONY : $(LIBS)
bamboo_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx bamboo amcc
- @echo "Compile NAND boot image for bamboo"
- @$(MKCONFIG) -a bamboo ppc ppc4xx bamboo amcc
+ bamboo_nand_config: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)nand_spl
+ @mkdir -p $(obj)board/amcc/bamboo
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
++ @$(MKCONFIG) -n $@ -a bamboo ppc ppc4xx bamboo amcc
+ @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/bamboo/config.tmp
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
bubinga_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx bubinga amcc
## MPC83xx Systems
#########################################################################
+MPC8313ERDB_33_config \
+MPC8313ERDB_66_config: unconfig
+ @echo "" >include/config.h ; \
+ if [ "$(findstring _33_,$@)" ] ; then \
+ echo -n "...33M ..." ; \
+ echo "#define CFG_33MHZ" >>include/config.h ; \
+ fi ; \
+ if [ "$(findstring _66_,$@)" ] ; then \
+ echo -n "...66M..." ; \
+ echo "#define CFG_66MHZ" >>include/config.h ; \
+ fi ;
+ @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb
+
MPC832XEMDS_config \
MPC832XEMDS_HOST_33_config \
MPC832XEMDS_HOST_66_config \
MPC8541CDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds
+MPC8544DS_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
+
MPC8548CDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds
MPC8555CDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8555cds cds
+MPC8568MDS_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds
+
PM854_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
stxgp3_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3
+stxssa_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxssa
+
TQM8540_config \
TQM8541_config \
TQM8555_config \
EVB64260_750CX_config: unconfig
@$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260
+mpc7448hpc2_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2
+
P3G4_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260
}
#endif /* CONFIG_DDR_DATA_EYE */
+#if defined(CONFIG_NAND_SPL)
+/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+ * for the 4k NAND boot image so define bus_frequency to 133MHz here
+ * which is save for the refresh counter setup.
+ */
+#define get_bus_freq(val) 133000000
+#endif
+
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
long int initdram (int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+ #if !defined(CONFIG_NAND_SPL)
ulong speed = get_bus_freq(0);
+ #else
+ ulong speed = 133333333; /* 133MHz is on the safe side */
+ #endif
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_22, 0x00267F0B);
mtsdram(DDR0_23, 0x00000000);
mtsdram(DDR0_24, 0x01010002);
- if (speed > 133333333)
+ if (speed > 133333334)
mtsdram(DDR0_26, 0x5B26050C);
else
mtsdram(DDR0_26, 0x5B260408);
* Platform independend driver for NDFC (NanD Flash Controller)
* integrated into EP440 cores
*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Based on original work by
#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \
(defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EZ))
#include <nand.h>
#include <linux/mtd/ndfc.h>
+ #include <linux/mtd/nand_ecc.h>
#include <asm/processor.h>
-#include <ppc440.h>
+ #include <asm/io.h>
+#include <ppc4xx.h>
static u8 hwctl = 0;
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
if (hwctl & 0x1)
- out8(base + NDFC_CMD, byte);
+ out_8((u8 *)(base + NDFC_CMD), byte);
else if (hwctl & 0x2)
- out8(base + NDFC_ALE, byte);
+ out_8((u8 *)(base + NDFC_ALE), byte);
else
- out8(base + NDFC_DATA, byte);
+ out_8((u8 *)(base + NDFC_DATA), byte);
}
static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
- return (in8(base + NDFC_DATA));
+ return (in_8((u8 *)(base + NDFC_DATA)));
}
static int ndfc_dev_ready(struct mtd_info *mtdinfo)
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
- while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY))
+ while (!(in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY))
;
return 1;
}
- #ifndef CONFIG_NAND_SPL
- /*
- * Don't use these speedup functions in NAND boot image, since the image
- * has to fit into 4kByte.
- */
+ static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
+ {
+ struct nand_chip *this = mtdinfo->priv;
+ ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
+ u32 ccr;
+
+ ccr = in_be32((u32 *)(base + NDFC_CCR));
+ ccr |= NDFC_CCR_RESET_ECC;
+ out_be32((u32 *)(base + NDFC_CCR), ccr);
+ }
+
+ static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
+ const u_char *dat, u_char *ecc_code)
+ {
+ struct nand_chip *this = mtdinfo->priv;
+ ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
+ u32 ecc;
+ u8 *p = (u8 *)&ecc;
+
+ ecc = in_be32((u32 *)(base + NDFC_ECC));
+
+ /* The NDFC uses Smart Media (SMC) bytes order
+ */
+ ecc_code[0] = p[2];
+ ecc_code[1] = p[1];
+ ecc_code[2] = p[3];
+
+ return 0;
+ }
/*
* Speedups for buffer read/write/verify
uint32_t *p = (uint32_t *) buf;
for (;len > 0; len -= 4)
- *p++ = in32(base + NDFC_DATA);
+ *p++ = in_be32((u32 *)(base + NDFC_DATA));
}
+ #ifndef CONFIG_NAND_SPL
+ /*
+ * Don't use these speedup functions in NAND boot image, since the image
+ * has to fit into 4kByte.
+ */
static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
uint32_t *p = (uint32_t *) buf;
for (; len > 0; len -= 4)
- out32(base + NDFC_DATA, *p++);
+ out_be32((u32 *)(base + NDFC_DATA), *p++);
}
static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
uint32_t *p = (uint32_t *) buf;
for (; len > 0; len -= 4)
- if (*p++ != in32(base + NDFC_DATA))
+ if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
return -1;
return 0;
ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
/* Set NandFlash Core Configuration Register */
- /* 1col x 2 rows */
- out32(base + NDFC_CCR, 0x00000000 | (cs << 24));
+ /* 1 col x 2 rows */
+ out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
}
int board_nand_init(struct nand_chip *nand)
int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
- nand->eccmode = NAND_ECC_SOFT;
-
nand->hwcontrol = ndfc_hwcontrol;
nand->read_byte = ndfc_read_byte;
+ nand->read_buf = ndfc_read_buf;
nand->write_byte = ndfc_write_byte;
nand->dev_ready = ndfc_dev_ready;
+ nand->eccmode = NAND_ECC_HW3_256;
+ nand->enable_hwecc = ndfc_enable_hwecc;
+ nand->calculate_ecc = ndfc_calculate_ecc;
+ nand->correct_data = nand_correct_data;
+
#ifndef CONFIG_NAND_SPL
nand->write_buf = ndfc_write_buf;
- nand->read_buf = ndfc_read_buf;
nand->verify_buf = ndfc_verify_buf;
#else
/*
* Setup EBC (CS0 only right now)
*/
- mtdcr(ebccfga, xbcfg);
- mtdcr(ebccfgd, 0xb8400000);
+ mtebc(EBC0_CFG, 0xb8400000);
mtebc(pb0cr, CFG_EBC_PB0CR);
mtebc(pb0ap, CFG_EBC_PB0AP);
* Select required NAND chip in NDFC
*/
board_nand_select_device(nand, cs);
- out32(base + NDFC_BCFG0 + (cs << 2), 0x80002222);
+ out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), 0x80002222);
return 0;
}
# endif
#endif /* CFG_INIT_DCACHE_CS */
+ #define function_prolog(func_name) .text; \
+ .align 2; \
+ .globl func_name; \
+ func_name:
+ #define function_epilog(func_name) .type func_name,@function; \
+ .size func_name,.-func_name
+
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
2:
#if defined(CONFIG_NAND_SPL)
+ #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/*
- * Enable internal SRAM
+ * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
*/
lis r2,0x7fff
ori r2,r2,0xffff
mfdcr r1,isram0_pmeg
and r1,r1,r2 /* Disable pwr mgmt */
mtdcr isram0_pmeg,r1
+ #endif
+ #if defined(CONFIG_440EP)
+ /*
+ * On 440EP with no internal SRAM, we setup SDRAM very early
+ * and copy the NAND_SPL to SDRAM and jump to it
+ */
+ /* Clear Dcache to use as RAM */
+ addis r3,r0,CFG_INIT_RAM_ADDR@h
+ ori r3,r3,CFG_INIT_RAM_ADDR@l
+ addis r4,r0,CFG_INIT_RAM_END@h
+ ori r4,r4,CFG_INIT_RAM_END@l
+ rlwinm. r5,r4,0,27,31
+ rlwinm r5,r4,27,5,31
+ beq ..d_ran3
+ addi r5,r5,0x0001
+ ..d_ran3:
+ mtctr r5
+ ..d_ag3:
+ dcbz r0,r3
+ addi r3,r3,32
+ bdnz ..d_ag3
+ /*----------------------------------------------------------------*/
+ /* Setup the stack in internal SRAM */
+ /*----------------------------------------------------------------*/
+ lis r1,CFG_INIT_RAM_ADDR@h
+ ori r1,r1,CFG_INIT_SP_OFFSET@l
+ li r0,0
+ stwu r0,-4(r1)
+ stwu r0,-4(r1) /* Terminate call chain */
+
+ stwu r1,-8(r1) /* Save back chain and move SP */
+ lis r0,RESET_VECTOR@h /* Address of reset vector */
+ ori r0,r0, RESET_VECTOR@l
+ stwu r1,-8(r1) /* Save back chain and move SP */
+ stw r0,+12(r1) /* Save return addr (underflow vect) */
+ sync
+ bl early_sdram_init
+ sync
+ #endif /* CONFIG_440EP */
/*
* Copy SPL from cache into internal SRAM
start_ram:
sync
isync
- #endif
+ #endif /* CONFIG_NAND_SPL */
bl 3f
b _start
mtdcr ocmdscr2, r3 /* Set Data Side */
mtdcr ocmiscr2, r3 /* Set Instruction Side */
addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
- mtdcr ocmdsisdpc,r4
+ mtdcr ocmdsisdpc,r3
isync
#else /* CONFIG_405EZ */
lwz r1,GPR1(r1)
SYNC
rfci
- #endif /* CONFIG_NAND_SPL */
/* Cache functions.
*/
mtspr tcr, r3
blr
- /*------------------------------------------------------------------------------- */
- /* Function: in8 */
- /* Description: Input 8 bits */
- /*------------------------------------------------------------------------------- */
- .globl in8
- in8:
- lbz r3,0x0000(r3)
- blr
-
- /*------------------------------------------------------------------------------- */
- /* Function: out8 */
- /* Description: Output 8 bits */
- /*------------------------------------------------------------------------------- */
- .globl out8
- out8:
- stb r4,0x0000(r3)
- blr
-
/*------------------------------------------------------------------------------- */
/* Function: out16 */
/* Description: Output 16 bits */
sthbrx r4,r0,r3
blr
- /*------------------------------------------------------------------------------- */
- /* Function: out32 */
- /* Description: Output 32 bits */
- /*------------------------------------------------------------------------------- */
- .globl out32
- out32:
- stw r4,0x0000(r3)
- blr
-
/*------------------------------------------------------------------------------- */
/* Function: out32r */
/* Description: Byte reverse and output 32 bits */
lhbrx r3,r0,r3
blr
- /*------------------------------------------------------------------------------- */
- /* Function: in32 */
- /* Description: Input 32 bits */
- /*------------------------------------------------------------------------------- */
- .globl in32
- in32:
- lwz 3,0x0000(3)
- blr
-
/*------------------------------------------------------------------------------- */
/* Function: in32r */
/* Description: Input 32 bits and byte reverse */
sync
blr
- /*------------------------------------------------------------------------------*/
-
- #ifndef CONFIG_NAND_SPL
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
stw r0, 4(r7)
blr
+
+ #if defined(CONFIG_440)
+ /*----------------------------------------------------------------------------+
+ | dcbz_area.
+ +----------------------------------------------------------------------------*/
+ function_prolog(dcbz_area)
+ rlwinm. r5,r4,0,27,31
+ rlwinm r5,r4,27,5,31
+ beq ..d_ra2
+ addi r5,r5,0x0001
+ ..d_ra2:mtctr r5
+ ..d_ag2:dcbz r0,r3
+ addi r3,r3,32
+ bdnz ..d_ag2
+ sync
+ blr
+ function_epilog(dcbz_area)
+
+ /*----------------------------------------------------------------------------+
+ | dflush. Assume 32K at vector address is cachable.
+ +----------------------------------------------------------------------------*/
+ function_prolog(dflush)
+ mfmsr r9
+ rlwinm r8,r9,0,15,13
+ rlwinm r8,r8,0,17,15
+ mtmsr r8
+ addi r3,r0,0x0000
+ mtspr dvlim,r3
+ mfspr r3,ivpr
+ addi r4,r0,1024
+ mtctr r4
+ ..dflush_loop:
+ lwz r6,0x0(r3)
+ addi r3,r3,32
+ bdnz ..dflush_loop
+ addi r3,r3,-32
+ mtctr r4
+ ..ag: dcbf r0,r3
+ addi r3,r3,-32
+ bdnz ..ag
+ sync
+ mtmsr r9
+ blr
+ function_epilog(dflush)
+ #endif /* CONFIG_440 */
#endif /* CONFIG_NAND_SPL */
+ /*------------------------------------------------------------------------------- */
+ /* Function: in8 */
+ /* Description: Input 8 bits */
+ /*------------------------------------------------------------------------------- */
+ .globl in8
+ in8:
+ lbz r3,0x0000(r3)
+ blr
+
+ /*------------------------------------------------------------------------------- */
+ /* Function: out8 */
+ /* Description: Output 8 bits */
+ /*------------------------------------------------------------------------------- */
+ .globl out8
+ out8:
+ stb r4,0x0000(r3)
+ blr
+
+ /*------------------------------------------------------------------------------- */
+ /* Function: out32 */
+ /* Description: Output 32 bits */
+ /*------------------------------------------------------------------------------- */
+ .globl out32
+ out32:
+ stw r4,0x0000(r3)
+ blr
+
+ /*------------------------------------------------------------------------------- */
+ /* Function: in32 */
+ /* Description: Input 32 bits */
+ /*------------------------------------------------------------------------------- */
+ .globl in32
+ in32:
+ lwz 3,0x0000(3)
+ blr
/**************************************************************************/
/* PPC405EP specific stuff */
#endif /* CONFIG_405EP */
#if defined(CONFIG_440)
- #define function_prolog(func_name) .text; \
- .align 2; \
- .globl func_name; \
- func_name:
- #define function_epilog(func_name) .type func_name,@function; \
- .size func_name,.-func_name
-
/*----------------------------------------------------------------------------+
| mttlb3.
+----------------------------------------------------------------------------*/
TLBRE(3,3,0)
blr
function_epilog(mftlb1)
-
- /*----------------------------------------------------------------------------+
- | dcbz_area.
- +----------------------------------------------------------------------------*/
- function_prolog(dcbz_area)
- rlwinm. r5,r4,0,27,31
- rlwinm r5,r4,27,5,31
- beq ..d_ra2
- addi r5,r5,0x0001
- ..d_ra2:mtctr r5
- ..d_ag2:dcbz r0,r3
- addi r3,r3,32
- bdnz ..d_ag2
- sync
- blr
- function_epilog(dcbz_area)
-
- /*----------------------------------------------------------------------------+
- | dflush. Assume 32K at vector address is cachable.
- +----------------------------------------------------------------------------*/
- function_prolog(dflush)
- mfmsr r9
- rlwinm r8,r9,0,15,13
- rlwinm r8,r8,0,17,15
- mtmsr r8
- addi r3,r0,0x0000
- mtspr dvlim,r3
- mfspr r3,ivpr
- addi r4,r0,1024
- mtctr r4
- ..dflush_loop:
- lwz r6,0x0(r3)
- addi r3,r3,32
- bdnz ..dflush_loop
- addi r3,r3,-32
- mtctr r4
- ..ag: dcbf r0,r3
- addi r3,r3,-32
- bdnz ..ag
- sync
- mtmsr r9
- blr
- function_epilog(dflush)
#endif /* CONFIG_440 */
#define CONFIG_440GRX 1 /* Specific PPC440GRx */
#endif
#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external freq to pll */
+/* Detect Sequoia PLL input clock automatically via CPLD bit */
+#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
+ 33333333 : 33000000)
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
/*
* Now the NAND chip has to be defined (no autodetection used!)
*/
- #define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */
+ #define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
- #define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */
- #define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */
+ #define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
+ #define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
+ #define CFG_NAND_ECCSIZE 256
+ #define CFG_NAND_ECCBYTES 3
+ #define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+ #define CFG_NAND_OOBSIZE 16
+ #define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+ #define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
+
#ifdef CFG_ENV_IS_IN_NAND
/*
* For NAND booting the environment is embedded in the U-Boot image. Please take
#
--# (C) Copyright 2006
++# (C) Copyright 2006-2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o init.o resetvec.o
- COBJS = nand_boot.o ndfc.o sdram.o
+ COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
+ # from drivers/nand directory
+ $(obj)nand_ecc.c:
+ @rm -f $(obj)nand_ecc.c
+ ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c
+
#########################################################################
$(obj)%.o: $(obj)%.S
projects / karo-tx-uboot.git / commitdiff