2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/errno.h>
27 #include <asm/arch/imx-regs.h>
28 #include <asm/arch/crm_regs.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch/sys_proto.h>
33 PLL_ARM, /* PLL1: ARM PLL */
34 PLL_BUS, /* PLL2: System Bus PLL*/
35 PLL_USBOTG, /* PLL3: OTG USB PLL */
36 PLL_AUDIO, /* PLL4: Audio PLL */
37 PLL_VIDEO, /* PLL5: Video PLL */
38 PLL_ENET, /* PLL6: ENET PLL */
39 PLL_USB2, /* PLL7: USB2 PLL */
40 PLL_MLB, /* PLL8: MLB PLL */
43 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
44 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
46 int clk_enable(struct clk *clk)
52 if (clk->usecount == 0) {
53 debug("%s: Enabling %s clock\n", __func__, clk->name);
54 ret = clk->enable(clk);
59 assert(clk->usecount > 0);
63 void clk_disable(struct clk *clk)
68 assert(clk->usecount > 0);
69 if (!(--clk->usecount)) {
71 debug("%s: Disabling %s clock\n", __func__, clk->name);
77 void enable_usboh3_clk(unsigned char enable)
81 reg = __raw_readl(&imx_ccm->CCGR6);
83 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
85 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
86 __raw_writel(reg, &imx_ccm->CCGR6);
91 /* i2c_num can be from 0 - 2 */
92 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
100 mask = MXC_CCM_CCGR_CG_MASK
101 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
102 reg = __raw_readl(&imx_ccm->CCGR2);
107 __raw_writel(reg, &imx_ccm->CCGR2);
112 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
118 div = __raw_readl(&anatop->pll_arm);
119 if (div & BM_ANADIG_PLL_ARM_BYPASS)
120 /* Assume the bypass clock is always derived from OSC */
122 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
124 return infreq * div / 2;
126 div = __raw_readl(&anatop->pll_528);
127 if (div & BM_ANADIG_PLL_SYS_BYPASS)
129 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
131 return infreq * (20 + div * 2);
133 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
134 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
136 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
138 return infreq * (20 + div * 2);
140 div = __raw_readl(&anatop->pll_audio);
141 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
143 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
147 div = __raw_readl(&anatop->pll_video);
148 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
150 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
154 div = __raw_readl(&anatop->pll_enet);
155 if (div & BM_ANADIG_PLL_ENET_BYPASS)
157 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
159 return (div == 3 ? 125000000 : 25000000 * div * 2);
161 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
162 if (div & BM_ANADIG_USB2_PLL_480_CTRL_BYPASS)
164 div &= BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT;
166 return infreq * (20 + div * 2);
168 div = __raw_readl(&anatop->pll_mlb);
169 if (div & BM_ANADIG_PLL_MLB_BYPASS)
171 /* unknown external clock provided on MLB_CLK pin */
177 static u32 get_mcu_main_clk(void)
181 reg = __raw_readl(&imx_ccm->cacrr);
182 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
183 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
184 freq = decode_pll(PLL_ARM, MXC_HCLK);
186 return freq / (reg + 1);
189 u32 get_periph_clk(void)
193 reg = __raw_readl(&imx_ccm->cbcdr);
194 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
195 reg = __raw_readl(&imx_ccm->cbcmr);
196 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
197 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
201 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
209 reg = __raw_readl(&imx_ccm->cbcmr);
210 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
211 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
215 freq = decode_pll(PLL_BUS, MXC_HCLK);
218 freq = PLL2_PFD2_FREQ;
221 freq = PLL2_PFD0_FREQ;
224 freq = PLL2_PFD2_DIV_FREQ;
232 static u32 get_ipg_clk(void)
236 reg = __raw_readl(&imx_ccm->cbcdr);
237 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
238 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
240 return get_ahb_clk() / (ipg_podf + 1);
243 static u32 get_ipg_per_clk(void)
245 u32 reg, perclk_podf;
247 reg = __raw_readl(&imx_ccm->cscmr1);
248 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
250 return get_ipg_clk() / (perclk_podf + 1);
253 static u32 get_uart_clk(void)
257 reg = __raw_readl(&imx_ccm->cscdr1);
258 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
259 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
261 return PLL3_80M / (uart_podf + 1);
264 static u32 get_cspi_clk(void)
268 reg = __raw_readl(&imx_ccm->cscdr2);
269 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
270 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
272 return PLL3_60M / (cspi_podf + 1);
275 static u32 get_axi_clk(void)
277 u32 root_freq, axi_podf;
278 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
280 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
281 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
283 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
284 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
285 root_freq = PLL2_PFD2_FREQ;
287 root_freq = PLL3_PFD1_FREQ;
289 root_freq = get_periph_clk();
291 return root_freq / (axi_podf + 1);
294 static u32 get_emi_slow_clk(void)
296 u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
298 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
299 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
300 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
301 emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
302 emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
304 switch (emi_clk_sel) {
306 root_freq = get_axi_clk();
309 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
312 root_freq = PLL2_PFD2_FREQ;
315 root_freq = PLL2_PFD0_FREQ;
319 return root_freq / (emi_slow_pof + 1);
322 static u32 get_nfc_clk(void)
324 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
325 u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
326 u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
327 int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
328 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
331 switch (nfc_clk_sel) {
333 root_freq = PLL2_PFD0_FREQ;
336 root_freq = decode_pll(PLL_BUS, MXC_HCLK);
339 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
342 root_freq = PLL2_PFD2_FREQ;
346 return root_freq / (pred + 1) / (podf + 1);
349 static u32 get_mmdc_ch0_clk(void)
351 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
352 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
353 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
355 return get_periph_clk() / (mmdc_ch0_podf + 1);
358 static u32 get_usdhc_clk(u32 port)
360 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
361 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
362 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
366 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
367 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
368 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
372 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
373 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
374 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
378 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
379 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
380 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
384 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
385 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
386 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
394 root_freq = PLL2_PFD0_FREQ;
396 root_freq = PLL2_PFD2_FREQ;
398 return root_freq / (usdhc_podf + 1);
401 u32 imx_get_uartclk(void)
403 return get_uart_clk();
406 u32 imx_get_fecclk(void)
408 return decode_pll(PLL_ENET, MXC_HCLK);
411 int enable_sata_clock(void)
414 s32 timeout = 100000;
416 /* Enable sata clock */
417 reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
418 reg |= MXC_CCM_CCGR5_SATA_MASK;
419 writel(reg, &imx_ccm->CCGR5);
422 reg = readl(&anatop->pll_enet);
423 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
424 writel(reg, &anatop->pll_enet);
425 reg |= BM_ANADIG_PLL_ENET_ENABLE;
427 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
432 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
433 writel(reg, &anatop->pll_enet);
434 reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
435 writel(reg, &anatop->pll_enet);
440 void ipu_clk_enable(void)
442 u32 reg = readl(&imx_ccm->CCGR3);
443 reg |= MXC_CCM_CCGR3_CG0_MASK;
444 writel(reg, &imx_ccm->CCGR3);
447 void ipu_clk_disable(void)
449 u32 reg = readl(&imx_ccm->CCGR3);
450 reg &= ~MXC_CCM_CCGR3_CG0_MASK;
451 writel(reg, &imx_ccm->CCGR3);
454 void ocotp_clk_enable(void)
456 u32 reg = readl(&imx_ccm->CCGR2);
457 reg |= MXC_CCM_CCGR2_CG6_MASK;
458 writel(reg, &imx_ccm->CCGR2);
461 void ocotp_clk_disable(void)
463 u32 reg = readl(&imx_ccm->CCGR2);
464 reg &= ~MXC_CCM_CCGR2_CG6_MASK;
465 writel(reg, &imx_ccm->CCGR2);
468 unsigned int mxc_get_clock(enum mxc_clock clk)
472 return get_mcu_main_clk();
474 return get_periph_clk();
476 return get_ahb_clk();
478 return get_ipg_clk();
481 return get_ipg_per_clk();
483 return get_uart_clk();
485 return get_cspi_clk();
487 return get_axi_clk();
488 case MXC_EMI_SLOW_CLK:
489 return get_emi_slow_clk();
491 return get_mmdc_ch0_clk();
493 return get_usdhc_clk(0);
495 return get_usdhc_clk(1);
497 return get_usdhc_clk(2);
499 return get_usdhc_clk(3);
501 return get_ahb_clk();
503 return get_nfc_clk();
509 static inline int gcd(int m, int n)
523 /* Config CPU clock */
524 static int config_core_clk(u32 ref, u32 freq)
529 int min_err = ~0 >> 1;
532 if (freq / ref > 108 || freq / ref * 8 < 54) {
536 for (d = 1; d < 8; d++) {
537 int m = (freq + (ref - 1)) / ref;
541 if (m > 108 || m < 54)
560 printf("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
561 mul, div, freq / 1000000, freq / 1000 % 1000,
562 ref * mul / div / 1000000, ref * mul / div / 1000 % 1000);
564 reg = readl(&anatop->pll_arm);
565 printf("anadig_pll_arm=%08x -> %08x\n",
566 reg, (reg & ~0x7f) | mul);
568 writel(div - 1, &imx_ccm->caccr);
570 writel(reg | mul, &anatop->pll_arm);
576 * This function assumes the expected core clock has to be changed by
577 * modifying the PLL. This is NOT true always but for most of the times,
578 * it is. So it assumes the PLL output freq is the same as the expected
579 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
580 * In the latter case, it will try to increase the presc value until
581 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
582 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
583 * on the targeted PLL and reference input clock to the PLL. Lastly,
584 * it sets the register based on these values along with the dividers.
585 * Note 1) There is no value checking for the passed-in divider values
586 * so the caller has to make sure those values are sensible.
587 * 2) Also adjust the NFC divider such that the NFC clock doesn't
588 * exceed NFC_CLK_MAX.
589 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
590 * 177MHz for higher voltage, this function fixes the max to 133MHz.
591 * 4) This function should not have allowed diag_printf() calls since
592 * the serial driver has been stoped. But leave then here to allow
593 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
595 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
601 if (config_core_clk(ref, freq))
606 if (config_periph_clk(ref, freq))
610 if (config_ddr_clk(freq))
614 if (config_nfc_clk(freq))
619 printf("Warning: Unsupported or invalid clock type: %d\n",
628 * Dump some core clocks.
630 #define print_pll(pll) printf("%-12s %4d.%03d MHz\n", #pll, \
631 decode_pll(pll, MXC_HCLK) / 1000000, \
632 decode_pll(pll, MXC_HCLK) / 1000 % 1000)
634 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
635 #define print_clk(clk) printf("%-12s %4d.%03d MHz\n", #clk, \
636 mxc_get_clock(MXC_##clk##_CLK) / 1000000, \
637 mxc_get_clock(MXC_##clk##_CLK) / 1000 % 1000)
639 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
643 print_pll(PLL_USBOTG);
644 print_pll(PLL_AUDIO);
645 print_pll(PLL_VIDEO);
668 /***************************************************/
671 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,