arch/x86/dts/bayleybay.dts

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/gpio/x86-gpio.h>
  10 #include <dt-bindings/interrupt-router/intel-irq.h>
  11
  12 /include/ "skeleton.dtsi"
  13 /include/ "serial.dtsi"
  14 /include/ "rtc.dtsi"
  15
  16 / {
  17         model = "Intel Bayley Bay";
  18         compatible = "intel,bayleybay", "intel,baytrail";
  19
  20         aliases {
  21                 serial0 = &serial;
  22                 spi0 = "/spi";
  23         };
  24
  25         config {
  26                 silent_console = <0>;
  27         };
  28
  29         chosen {
  30                 stdout-path = "/serial";
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "intel,baytrail-cpu";
  40                         reg = <0>;
  41                         intel,apic-id = <0>;
  42                 };
  43
  44                 cpu@1 {
  45                         device_type = "cpu";
  46                         compatible = "intel,baytrail-cpu";
  47                         reg = <1>;
  48                         intel,apic-id = <2>;
  49                 };
  50
  51                 cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "intel,baytrail-cpu";
  54                         reg = <2>;
  55                         intel,apic-id = <4>;
  56                 };
  57
  58                 cpu@3 {
  59                         device_type = "cpu";
  60                         compatible = "intel,baytrail-cpu";
  61                         reg = <3>;
  62                         intel,apic-id = <6>;
  63                 };
  64         };
  65
  66         spi {
  67                 #address-cells = <1>;
  68                 #size-cells = <0>;
  69                 compatible = "intel,ich-spi";
  70                 spi-flash@0 {
  71                         reg = <0>;
  72                         compatible = "winbond,w25q64dw", "spi-flash";
  73                         memory-map = <0xff800000 0x00800000>;
  74                 };
  75         };
  76
  77         gpioa {
  78                 compatible = "intel,ich6-gpio";
  79                 u-boot,dm-pre-reloc;
  80                 reg = <0 0x20>;
  81                 bank-name = "A";
  82         };
  83
  84         gpiob {
  85                 compatible = "intel,ich6-gpio";
  86                 u-boot,dm-pre-reloc;
  87                 reg = <0x20 0x20>;
  88                 bank-name = "B";
  89         };
  90
  91         gpioc {
  92                 compatible = "intel,ich6-gpio";
  93                 u-boot,dm-pre-reloc;
  94                 reg = <0x40 0x20>;
  95                 bank-name = "C";
  96         };
  97
  98         gpiod {
  99                 compatible = "intel,ich6-gpio";
 100                 u-boot,dm-pre-reloc;
 101                 reg = <0x60 0x20>;
 102                 bank-name = "D";
 103         };
 104
 105         gpioe {
 106                 compatible = "intel,ich6-gpio";
 107                 u-boot,dm-pre-reloc;
 108                 reg = <0x80 0x20>;
 109                 bank-name = "E";
 110         };
 111
 112         gpiof {
 113                 compatible = "intel,ich6-gpio";
 114                 u-boot,dm-pre-reloc;
 115                 reg = <0xA0 0x20>;
 116                 bank-name = "F";
 117         };
 118
 119         pci {
 120                 compatible = "pci-x86";
 121                 #address-cells = <3>;
 122                 #size-cells = <2>;
 123                 u-boot,dm-pre-reloc;
 124                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
 125                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
 126                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
 127
 128                 irq-router@1f,0 {
 129                         reg = <0x0000f800 0 0 0 0>;
 130                         compatible = "intel,irq-router";
 131                         intel,pirq-config = "ibase";
 132                         intel,ibase-offset = <0x50>;
 133                         intel,pirq-link = <8 8>;
 134                         intel,pirq-mask = <0xdee0>;
 135                         intel,pirq-routing = <
 136                                 /* BayTrail PCI devices */
 137                                 PCI_BDF(0, 2, 0) INTA PIRQA
 138                                 PCI_BDF(0, 3, 0) INTA PIRQA
 139                                 PCI_BDF(0, 16, 0) INTA PIRQA
 140                                 PCI_BDF(0, 17, 0) INTA PIRQA
 141                                 PCI_BDF(0, 18, 0) INTA PIRQA
 142                                 PCI_BDF(0, 19, 0) INTA PIRQA
 143                                 PCI_BDF(0, 20, 0) INTA PIRQA
 144                                 PCI_BDF(0, 21, 0) INTA PIRQA
 145                                 PCI_BDF(0, 22, 0) INTA PIRQA
 146                                 PCI_BDF(0, 23, 0) INTA PIRQA
 147                                 PCI_BDF(0, 24, 0) INTA PIRQA
 148                                 PCI_BDF(0, 24, 1) INTC PIRQC
 149                                 PCI_BDF(0, 24, 2) INTD PIRQD
 150                                 PCI_BDF(0, 24, 3) INTB PIRQB
 151                                 PCI_BDF(0, 24, 4) INTA PIRQA
 152                                 PCI_BDF(0, 24, 5) INTC PIRQC
 153                                 PCI_BDF(0, 24, 6) INTD PIRQD
 154                                 PCI_BDF(0, 24, 7) INTB PIRQB
 155                                 PCI_BDF(0, 26, 0) INTA PIRQA
 156                                 PCI_BDF(0, 27, 0) INTA PIRQA
 157                                 PCI_BDF(0, 28, 0) INTA PIRQA
 158                                 PCI_BDF(0, 28, 1) INTB PIRQB
 159                                 PCI_BDF(0, 28, 2) INTC PIRQC
 160                                 PCI_BDF(0, 28, 3) INTD PIRQD
 161                                 PCI_BDF(0, 29, 0) INTA PIRQA
 162                                 PCI_BDF(0, 30, 0) INTA PIRQA
 163                                 PCI_BDF(0, 30, 1) INTD PIRQD
 164                                 PCI_BDF(0, 30, 2) INTB PIRQB
 165                                 PCI_BDF(0, 30, 3) INTC PIRQC
 166                                 PCI_BDF(0, 30, 4) INTD PIRQD
 167                                 PCI_BDF(0, 30, 5) INTB PIRQB
 168                                 PCI_BDF(0, 31, 3) INTB PIRQB
 169
 170                                 /* PCIe root ports downstream interrupts */
 171                                 PCI_BDF(1, 0, 0) INTA PIRQA
 172                                 PCI_BDF(1, 0, 0) INTB PIRQB
 173                                 PCI_BDF(1, 0, 0) INTC PIRQC
 174                                 PCI_BDF(1, 0, 0) INTD PIRQD
 175                                 PCI_BDF(2, 0, 0) INTA PIRQB
 176                                 PCI_BDF(2, 0, 0) INTB PIRQC
 177                                 PCI_BDF(2, 0, 0) INTC PIRQD
 178                                 PCI_BDF(2, 0, 0) INTD PIRQA
 179                                 PCI_BDF(3, 0, 0) INTA PIRQC
 180                                 PCI_BDF(3, 0, 0) INTB PIRQD
 181                                 PCI_BDF(3, 0, 0) INTC PIRQA
 182                                 PCI_BDF(3, 0, 0) INTD PIRQB
 183                                 PCI_BDF(4, 0, 0) INTA PIRQD
 184                                 PCI_BDF(4, 0, 0) INTB PIRQA
 185                                 PCI_BDF(4, 0, 0) INTC PIRQB
 186                                 PCI_BDF(4, 0, 0) INTD PIRQC
 187                         >;
 188                 };
 189         };
 190
 191         microcode {
 192                 update@0 {
 193 #include "microcode/m0230671117.dtsi"
 194                 };
 195         };
 196
 197 };