board/freescale/vf610twr/vf610twr.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  */
  19
  20 #include <common.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/imx-regs.h>
  23 #include <asm/arch/iomux-vf610.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/arch/clock.h>
  26 #include <mmc.h>
  27 #include <fsl_esdhc.h>
  28 #include <miiphy.h>
  29 #include <netdev.h>
  30 #include <i2c.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #define UART_PAD_CTRL   (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  35                         PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
  36
  37 #define ESDHC_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
  38                         PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
  39
  40 #define ENET_PAD_CTRL   (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
  41                         PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
  42
  43 void setup_iomux_ddr(void)
  44 {
  45         static const iomux_v3_cfg_t ddr_pads[] = {
  46                 VF610_PAD_DDR_A15__DDR_A_15,
  47                 VF610_PAD_DDR_A15__DDR_A_15,
  48                 VF610_PAD_DDR_A14__DDR_A_14,
  49                 VF610_PAD_DDR_A13__DDR_A_13,
  50                 VF610_PAD_DDR_A12__DDR_A_12,
  51                 VF610_PAD_DDR_A11__DDR_A_11,
  52                 VF610_PAD_DDR_A10__DDR_A_10,
  53                 VF610_PAD_DDR_A9__DDR_A_9,
  54                 VF610_PAD_DDR_A8__DDR_A_8,
  55                 VF610_PAD_DDR_A7__DDR_A_7,
  56                 VF610_PAD_DDR_A6__DDR_A_6,
  57                 VF610_PAD_DDR_A5__DDR_A_5,
  58                 VF610_PAD_DDR_A4__DDR_A_4,
  59                 VF610_PAD_DDR_A3__DDR_A_3,
  60                 VF610_PAD_DDR_A2__DDR_A_2,
  61                 VF610_PAD_DDR_A1__DDR_A_1,
  62                 VF610_PAD_DDR_BA2__DDR_BA_2,
  63                 VF610_PAD_DDR_BA1__DDR_BA_1,
  64                 VF610_PAD_DDR_BA0__DDR_BA_0,
  65                 VF610_PAD_DDR_CAS__DDR_CAS_B,
  66                 VF610_PAD_DDR_CKE__DDR_CKE_0,
  67                 VF610_PAD_DDR_CLK__DDR_CLK_0,
  68                 VF610_PAD_DDR_CS__DDR_CS_B_0,
  69                 VF610_PAD_DDR_D15__DDR_D_15,
  70                 VF610_PAD_DDR_D14__DDR_D_14,
  71                 VF610_PAD_DDR_D13__DDR_D_13,
  72                 VF610_PAD_DDR_D12__DDR_D_12,
  73                 VF610_PAD_DDR_D11__DDR_D_11,
  74                 VF610_PAD_DDR_D10__DDR_D_10,
  75                 VF610_PAD_DDR_D9__DDR_D_9,
  76                 VF610_PAD_DDR_D8__DDR_D_8,
  77                 VF610_PAD_DDR_D7__DDR_D_7,
  78                 VF610_PAD_DDR_D6__DDR_D_6,
  79                 VF610_PAD_DDR_D5__DDR_D_5,
  80                 VF610_PAD_DDR_D4__DDR_D_4,
  81                 VF610_PAD_DDR_D3__DDR_D_3,
  82                 VF610_PAD_DDR_D2__DDR_D_2,
  83                 VF610_PAD_DDR_D1__DDR_D_1,
  84                 VF610_PAD_DDR_D0__DDR_D_0,
  85                 VF610_PAD_DDR_DQM1__DDR_DQM_1,
  86                 VF610_PAD_DDR_DQM0__DDR_DQM_0,
  87                 VF610_PAD_DDR_DQS1__DDR_DQS_1,
  88                 VF610_PAD_DDR_DQS0__DDR_DQS_0,
  89                 VF610_PAD_DDR_RAS__DDR_RAS_B,
  90                 VF610_PAD_DDR_WE__DDR_WE_B,
  91                 VF610_PAD_DDR_ODT1__DDR_ODT_0,
  92                 VF610_PAD_DDR_ODT0__DDR_ODT_1,
  93         };
  94
  95         imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
  96 }
  97
  98 void ddr_phy_init(void)
  99 {
 100         struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
 101
 102         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
 103         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
 104         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
 105         writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
 106
 107         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
 108         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
 109         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
 110         writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
 111
 112         writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
 113         writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
 114         writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
 115         writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
 116
 117         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
 118         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
 119         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
 120         writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
 121
 122         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
 123         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
 124         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
 125         writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
 126
 127         writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
 128                 &ddrmr->phy[50]);
 129 }
 130
 131 void ddr_ctrl_init(void)
 132 {
 133         struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
 134
 135         writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
 136         writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
 137         writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
 138
 139         writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
 140         writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
 141         writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
 142                 DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
 143         writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
 144                 DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
 145         writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
 146         writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12),
 147                 &ddrmr->cr[17]);
 148         writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
 149
 150         writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
 151         writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
 152                 DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
 153
 154         writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
 155         writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
 156         writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
 157
 158         writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
 159         writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
 160         writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
 161         writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
 162
 163         writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
 164         writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
 165         writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
 166         writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
 167
 168         writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
 169         writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
 170                 DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
 171
 172         writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
 173         writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056),
 174                 &ddrmr->cr[48]);
 175
 176         writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]);
 177         writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]);
 178         writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
 179
 180         writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
 181         writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
 182
 183         writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
 184                 DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
 185         writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
 186                 DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
 187                 &ddrmr->cr[74]);
 188         writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
 189                 DDRMC_CR75_PLEN, &ddrmr->cr[75]);
 190         writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
 191                 DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
 192         writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
 193                 DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
 194         writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
 195         writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
 196
 197         writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
 198
 199         writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
 200                 &ddrmr->cr[87]);
 201         writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
 202         writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
 203
 204         writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
 205         writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
 206
 207         writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
 208         writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
 209         writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
 210
 211         writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
 212                 &ddrmr->cr[117]);
 213         writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
 214                 &ddrmr->cr[118]);
 215
 216         writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2),
 217                 &ddrmr->cr[120]);
 218         writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2),
 219                 &ddrmr->cr[121]);
 220         writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
 221                 DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
 222         writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
 223                 &ddrmr->cr[123]);
 224         writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
 225
 226         writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
 227         writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
 228                 &ddrmr->cr[132]);
 229         writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
 230                 DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
 231                 &ddrmr->cr[139]);
 232
 233         writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
 234                 DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);
 235         writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
 236                 &ddrmr->cr[155]);
 237         writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
 238
 239         ddr_phy_init();
 240
 241         writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
 242
 243         udelay(200);
 244 }
 245
 246 int dram_init(void)
 247 {
 248         setup_iomux_ddr();
 249
 250         ddr_ctrl_init();
 251         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 252
 253         return 0;
 254 }
 255
 256 static void setup_iomux_uart(void)
 257 {
 258         static const iomux_v3_cfg_t uart1_pads[] = {
 259                 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
 260                 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
 261         };
 262
 263         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 264 }
 265
 266 static void setup_iomux_enet(void)
 267 {
 268         static const iomux_v3_cfg_t enet0_pads[] = {
 269                 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
 270                 NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
 271                 NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
 272                 NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
 273                 NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
 274                 NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
 275                 NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
 276                 NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
 277                 NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
 278                 NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
 279         };
 280
 281         imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
 282 }
 283
 284 static void setup_iomux_i2c(void)
 285 {
 286         static const iomux_v3_cfg_t i2c0_pads[] = {
 287                 VF610_PAD_PTB14__I2C0_SCL,
 288                 VF610_PAD_PTB15__I2C0_SDA,
 289         };
 290
 291         imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
 292 }
 293
 294 #ifdef CONFIG_FSL_ESDHC
 295 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 296         {ESDHC1_BASE_ADDR},
 297 };
 298
 299 int board_mmc_getcd(struct mmc *mmc)
 300 {
 301         /* eSDHC1 is always present */
 302         return 1;
 303 }
 304
 305 int board_mmc_init(bd_t *bis)
 306 {
 307         static const iomux_v3_cfg_t esdhc1_pads[] = {
 308                 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
 309                 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
 310                 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
 311                 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
 312                 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
 313                 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
 314         };
 315
 316         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 317
 318         imx_iomux_v3_setup_multiple_pads(
 319                 esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
 320
 321         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 322 }
 323 #endif
 324
 325 static void clock_init(void)
 326 {
 327         struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
 328         struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
 329
 330         clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
 331                 CCM_CCGR0_UART1_CTRL_MASK);
 332         clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
 333                 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
 334         clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
 335                 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
 336                 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
 337                 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
 338         clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
 339                 CCM_CCGR3_ANADIG_CTRL_MASK);
 340         clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
 341                 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
 342                 CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
 343         clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
 344                 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
 345         clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
 346                 CCM_CCGR7_SDHC1_CTRL_MASK);
 347         clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
 348                 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
 349
 350         clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
 351                 ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
 352         clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
 353                 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
 354
 355         clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
 356                 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
 357         clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
 358                 CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
 359                 CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
 360                 CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
 361                 CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
 362                 CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
 363                 CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
 364         clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
 365                 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
 366                 CCM_CACRR_ARM_CLK_DIV(0));
 367         clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
 368                 CCM_CSCMR1_ESDHC1_CLK_SEL(3));
 369         clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
 370                 CCM_CSCDR1_RMII_CLK_EN);
 371         clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
 372                 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
 373         clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
 374                 CCM_CSCMR2_RMII_CLK_SEL(0));
 375 }
 376
 377 static void mscm_init(void)
 378 {
 379         struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
 380         int i;
 381
 382         for (i = 0; i < MSCM_IRSPRC_NUM; i++)
 383                 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
 384 }
 385
 386 int board_phy_config(struct phy_device *phydev)
 387 {
 388         if (phydev->drv->config)
 389                 phydev->drv->config(phydev);
 390
 391         return 0;
 392 }
 393
 394 int board_early_init_f(void)
 395 {
 396         clock_init();
 397         mscm_init();
 398
 399         setup_iomux_uart();
 400         setup_iomux_enet();
 401         setup_iomux_i2c();
 402
 403         return 0;
 404 }
 405
 406 int board_init(void)
 407 {
 408         /* address of boot parameters */
 409         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 410
 411         return 0;
 412 }
 413
 414 int checkboard(void)
 415 {
 416         puts("Board: vf610twr\n");
 417
 418         return 0;
 419 }