board/karo/tx51/tx51.c

   1 /*
   2  * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <common.h>
  21 #include <errno.h>
  22 #include <libfdt.h>
  23 #include <fdt_support.h>
  24 #include <lcd.h>
  25 #include <netdev.h>
  26 #include <mmc.h>
  27 #include <fsl_esdhc.h>
  28 #include <video_fb.h>
  29 #include <ipu.h>
  30 #include <mxcfb.h>
  31 #include <linux/fb.h>
  32 #include <asm/io.h>
  33 #include <asm/gpio.h>
  34 #include <asm/arch/iomux-mx51.h>
  35 #include <asm/arch/clock.h>
  36 #include <asm/arch/imx-regs.h>
  37 #include <asm/arch/crm_regs.h>
  38 #include <asm/arch/sys_proto.h>
  39
  40 #include "../common/karo.h"
  41
  42 #define TX51_FEC_RST_GPIO       IMX_GPIO_NR(2, 14)
  43 #define TX51_FEC_PWR_GPIO       IMX_GPIO_NR(1, 3)
  44 #define TX51_FEC_INT_GPIO       IMX_GPIO_NR(3, 18)
  45 #define TX51_LED_GPIO           IMX_GPIO_NR(4, 10)
  46
  47 #define TX51_LCD_PWR_GPIO       IMX_GPIO_NR(4, 14)
  48 #define TX51_LCD_RST_GPIO       IMX_GPIO_NR(4, 13)
  49 #define TX51_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 2)
  50
  51 #define TX51_RESET_OUT_GPIO     IMX_GPIO_NR(2, 15)
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 #define IOMUX_SION              IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  56
  57 #define FEC_PAD_CTRL            MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
  58                                         PAD_CTL_SRE_FAST)
  59 #define FEC_PAD_CTRL2           MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_SRE_FAST)
  60 #define GPIO_PAD_CTRL           MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP)
  61
  62 static iomux_v3_cfg_t tx51_pads[] = {
  63         /* NAND flash pads are set up in lowlevel_init.S */
  64
  65         /* RESET_OUT */
  66         MX51_PAD_EIM_A21__GPIO2_15 | GPIO_PAD_CTRL,
  67
  68         /* UART pads */
  69 #if CONFIG_MXC_UART_BASE == UART1_BASE
  70         MX51_PAD_UART1_RXD__UART1_RXD,
  71         MX51_PAD_UART1_TXD__UART1_TXD,
  72         MX51_PAD_UART1_RTS__UART1_RTS,
  73         MX51_PAD_UART1_CTS__UART1_CTS,
  74 #endif
  75 #if CONFIG_MXC_UART_BASE == UART2_BASE
  76         MX51_PAD_UART2_RXD__UART2_RXD,
  77         MX51_PAD_UART2_TXD__UART2_TXD,
  78         MX51_PAD_EIM_D26__UART2_RTS,
  79         MX51_PAD_EIM_D25__UART2_CTS,
  80 #endif
  81 #if CONFIG_MXC_UART_BASE == UART3_BASE
  82         MX51_PAD_UART3_RXD__UART3_RXD,
  83         MX51_PAD_UART3_TXD__UART3_TXD,
  84         MX51_PAD_EIM_D18__UART3_RTS,
  85         MX51_PAD_EIM_D17__UART3_CTS,
  86 #endif
  87         /* internal I2C */
  88         MX51_PAD_I2C1_DAT__GPIO4_17 | IOMUX_SION,
  89         MX51_PAD_I2C1_CLK__GPIO4_16 | IOMUX_SION,
  90
  91         /* FEC PHY GPIO functions */
  92         MX51_PAD_GPIO1_3__GPIO1_3 | GPIO_PAD_CTRL,    /* PHY POWER */
  93         MX51_PAD_EIM_A20__GPIO2_14 | GPIO_PAD_CTRL,   /* PHY RESET */
  94         MX51_PAD_NANDF_CS2__GPIO3_18 | GPIO_PAD_CTRL, /* PHY INT */
  95
  96         /* FEC functions */
  97         MX51_PAD_NANDF_CS3__FEC_MDC | FEC_PAD_CTRL,
  98         MX51_PAD_EIM_EB2__FEC_MDIO | FEC_PAD_CTRL,
  99         MX51_PAD_NANDF_D11__FEC_RX_DV | FEC_PAD_CTRL2,
 100         MX51_PAD_EIM_CS4__FEC_RX_ER | FEC_PAD_CTRL2,
 101         MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | FEC_PAD_CTRL2,
 102         MX51_PAD_NANDF_CS7__FEC_TX_EN | FEC_PAD_CTRL,
 103         MX51_PAD_NANDF_D8__FEC_TDATA0 | FEC_PAD_CTRL,
 104         MX51_PAD_NANDF_CS4__FEC_TDATA1 | FEC_PAD_CTRL,
 105         MX51_PAD_NANDF_CS5__FEC_TDATA2 | FEC_PAD_CTRL,
 106         MX51_PAD_NANDF_CS6__FEC_TDATA3 | FEC_PAD_CTRL,
 107
 108         /* strap pins for PHY configuration */
 109         MX51_PAD_NANDF_RB3__GPIO3_11 | GPIO_PAD_CTRL, /* RX_CLK/REGOFF */
 110         MX51_PAD_NANDF_D9__GPIO3_31 | GPIO_PAD_CTRL,  /* RXD0/Mode0 */
 111         MX51_PAD_EIM_EB3__GPIO2_23 | GPIO_PAD_CTRL,   /* RXD1/Mode1 */
 112         MX51_PAD_EIM_CS2__GPIO2_27 | GPIO_PAD_CTRL,   /* RXD2/Mode2 */
 113         MX51_PAD_EIM_CS3__GPIO2_28 | GPIO_PAD_CTRL,   /* RXD3/nINTSEL */
 114         MX51_PAD_NANDF_RB2__GPIO3_10 | GPIO_PAD_CTRL, /* COL/RMII/CRSDV */
 115         MX51_PAD_EIM_CS5__GPIO2_30 | GPIO_PAD_CTRL,   /* CRS/PHYAD4 */
 116
 117         /* unusable pins on TX51 */
 118         MX51_PAD_GPIO1_0__GPIO1_0,
 119         MX51_PAD_GPIO1_1__GPIO1_1,
 120 };
 121
 122 static const struct gpio tx51_gpios[] = {
 123         /* RESET_OUT */
 124         { TX51_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_LOW, "RESET_OUT", },
 125
 126         /* FEC PHY control GPIOs */
 127         { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */
 128         { TX51_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */
 129         { TX51_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },         /* PHY INT (TX_ER) */
 130
 131         /* FEC PHY strap pins */
 132         { IMX_GPIO_NR(3, 11), GPIOF_OUTPUT_INIT_LOW, "FEC PHY REGOFF", },  /* RX_CLK/REGOFF */
 133         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE0", },   /* RXD0/Mode0 */
 134         { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE1", },   /* RXD1/Mode1 */
 135         { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE2", },   /* RXD2/Mode2 */
 136         { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
 137         { IMX_GPIO_NR(3, 10), GPIOF_OUTPUT_INIT_LOW, "FEC PHY RMII", },    /* COL/RMII/CRSDV */
 138         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", },  /* CRS/PHYAD4 */
 139
 140         /* module internal I2C bus */
 141         { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", },
 142         { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", },
 143
 144         /* Unconnected pins */
 145         { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "N/C", },
 146         { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "N/C", },
 147 };
 148
 149 /*
 150  * Functions
 151  */
 152 /* placed in section '.data' to prevent overwriting relocation info
 153  * overlayed with bss
 154  */
 155 static u32 wrsr __attribute__((section(".data")));
 156
 157 #define WRSR_POR        (1 << 4)
 158 #define WRSR_TOUT       (1 << 1)
 159 #define WRSR_SFTW       (1 << 0)
 160
 161 static void print_reset_cause(void)
 162 {
 163         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 164         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 165         u32 srsr;
 166         char *dlm = "";
 167
 168         printf("Reset cause: ");
 169
 170         srsr = readl(&src_regs->srsr);
 171         wrsr = readw(wdt_base + 4);
 172
 173         if (wrsr & WRSR_POR) {
 174                 printf("%sPOR", dlm);
 175                 dlm = " | ";
 176         }
 177         if (srsr & 0x00004) {
 178                 printf("%sCSU", dlm);
 179                 dlm = " | ";
 180         }
 181         if (srsr & 0x00008) {
 182                 printf("%sIPP USER", dlm);
 183                 dlm = " | ";
 184         }
 185         if (srsr & 0x00010) {
 186                 if (wrsr & WRSR_SFTW) {
 187                         printf("%sSOFT", dlm);
 188                         dlm = " | ";
 189                 }
 190                 if (wrsr & WRSR_TOUT) {
 191                         printf("%sWDOG", dlm);
 192                         dlm = " | ";
 193                 }
 194         }
 195         if (srsr & 0x00020) {
 196                 printf("%sJTAG HIGH-Z", dlm);
 197                 dlm = " | ";
 198         }
 199         if (srsr & 0x00040) {
 200                 printf("%sJTAG SW", dlm);
 201                 dlm = " | ";
 202         }
 203         if (srsr & 0x10000) {
 204                 printf("%sWARM BOOT", dlm);
 205                 dlm = " | ";
 206         }
 207         if (dlm[0] == '\0')
 208                 printf("unknown");
 209
 210         printf("\n");
 211 }
 212
 213 static void tx51_print_cpuinfo(void)
 214 {
 215         u32 cpurev;
 216
 217         cpurev = get_cpu_rev();
 218
 219         printf("CPU:   Freescale i.MX51 rev%d.%d at %d MHz\n",
 220                 (cpurev & 0x000F0) >> 4,
 221                 (cpurev & 0x0000F) >> 0,
 222                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 223
 224         print_reset_cause();
 225 }
 226
 227 int board_early_init_f(void)
 228 {
 229         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 230
 231         gpio_request_array(tx51_gpios, ARRAY_SIZE(tx51_gpios));
 232         imx_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads));
 233
 234         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 235         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 236
 237         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 238         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 239         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 240         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 241         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 242
 243         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 244         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 245
 246         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 247         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 248         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 249         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 250         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 251
 252         writel(0xffcffffc, &ccm_regs->CCGR0);
 253         writel(0x003fffff, &ccm_regs->CCGR1);
 254         writel(0x030c003c, &ccm_regs->CCGR2);
 255         writel(0x000000ff, &ccm_regs->CCGR3);
 256         writel(0x00000000, &ccm_regs->CCGR4);
 257         writel(0x003fc003, &ccm_regs->CCGR5);
 258         writel(0x00000000, &ccm_regs->CCGR6);
 259         writel(0x00000000, &ccm_regs->cmeor);
 260 #ifdef CONFIG_CMD_BOOTCE
 261         /* WinCE fails to enable these clocks */
 262         writel(readl(&ccm_regs->CCGR2) | 0x0c000000, &ccm_regs->CCGR2); /* usboh3_ipg_ahb */
 263         writel(readl(&ccm_regs->CCGR4) | 0x30000000, &ccm_regs->CCGR4); /* srtc */
 264         writel(readl(&ccm_regs->CCGR6) | 0x00000300, &ccm_regs->CCGR6); /* emi_garb */
 265 #endif
 266         return 0;
 267 }
 268
 269 int board_init(void)
 270 {
 271         /* Address of boot parameters */
 272         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 273         return 0;
 274 }
 275
 276 int dram_init(void)
 277 {
 278         int ret;
 279
 280         /* dram_init must store complete ramsize in gd->ram_size */
 281         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 282                                 PHYS_SDRAM_1_SIZE);
 283
 284         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 285                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 286         if (ret)
 287                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 288                         CONFIG_SYS_SDRAM_CLK, ret);
 289         else
 290                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 291                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 292                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 293                         CONFIG_SYS_SDRAM_CLK);
 294         return ret;
 295 }
 296
 297 void dram_init_banksize(void)
 298 {
 299         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 300         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 301                         PHYS_SDRAM_1_SIZE);
 302 #if CONFIG_NR_DRAM_BANKS > 1
 303         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 304         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 305                         PHYS_SDRAM_2_SIZE);
 306 #endif
 307 }
 308
 309 #ifdef  CONFIG_CMD_MMC
 310 static const iomux_v3_cfg_t mmc0_pads[] = {
 311         MX51_PAD_SD1_CMD__SD1_CMD,
 312         MX51_PAD_SD1_CLK__SD1_CLK,
 313         MX51_PAD_SD1_DATA0__SD1_DATA0,
 314         MX51_PAD_SD1_DATA1__SD1_DATA1,
 315         MX51_PAD_SD1_DATA2__SD1_DATA2,
 316         MX51_PAD_SD1_DATA3__SD1_DATA3,
 317         /* SD1 CD */
 318         MX51_PAD_DISPB2_SER_RS__GPIO3_8 | GPIO_PAD_CTRL,
 319 };
 320
 321 static const iomux_v3_cfg_t mmc1_pads[] = {
 322         MX51_PAD_SD2_CMD__SD2_CMD,
 323         MX51_PAD_SD2_CLK__SD2_CLK,
 324         MX51_PAD_SD2_DATA0__SD2_DATA0,
 325         MX51_PAD_SD2_DATA1__SD2_DATA1,
 326         MX51_PAD_SD2_DATA2__SD2_DATA2,
 327         MX51_PAD_SD2_DATA3__SD2_DATA3,
 328         /* SD2 CD */
 329         MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | GPIO_PAD_CTRL,
 330 };
 331
 332 static struct tx51_esdhc_cfg {
 333         const iomux_v3_cfg_t *pads;
 334         int num_pads;
 335         struct fsl_esdhc_cfg cfg;
 336         int cd_gpio;
 337 } tx51_esdhc_cfg[] = {
 338         {
 339                 .pads = mmc0_pads,
 340                 .num_pads = ARRAY_SIZE(mmc0_pads),
 341                 .cfg = {
 342                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 343                 },
 344                 .cd_gpio = IMX_GPIO_NR(3, 8),
 345         },
 346         {
 347                 .pads = mmc1_pads,
 348                 .num_pads = ARRAY_SIZE(mmc1_pads),
 349                 .cfg = {
 350                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 351                 },
 352                 .cd_gpio = IMX_GPIO_NR(3, 6),
 353         },
 354 };
 355
 356 static struct tx51_esdhc_cfg *to_tx51_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 357 {
 358         return container_of(cfg, struct tx51_esdhc_cfg, cfg);
 359 }
 360
 361 int board_mmc_getcd(struct mmc *mmc)
 362 {
 363         struct tx51_esdhc_cfg *cfg = to_tx51_esdhc_cfg(mmc->priv);
 364
 365         if (cfg->cd_gpio < 0)
 366                 return cfg->cd_gpio;
 367
 368         debug("SD card %d is %spresent\n",
 369                 cfg - tx51_esdhc_cfg,
 370                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 371         return !gpio_get_value(cfg->cd_gpio);
 372 }
 373
 374 int board_mmc_init(bd_t *bis)
 375 {
 376         int i;
 377
 378         for (i = 0; i < ARRAY_SIZE(tx51_esdhc_cfg); i++) {
 379                 struct mmc *mmc;
 380                 struct tx51_esdhc_cfg *cfg = &tx51_esdhc_cfg[i];
 381                 int ret;
 382
 383                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 384                         break;
 385
 386                 imx_iomux_v3_setup_multiple_pads(cfg->pads,
 387                                                 cfg->num_pads);
 388                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 389
 390                 fsl_esdhc_initialize(bis, &cfg->cfg);
 391
 392                 ret = gpio_request_one(cfg->cd_gpio,
 393                                 GPIOF_INPUT, "MMC CD");
 394                 if (ret) {
 395                         printf("Error %d requesting GPIO%d_%d\n",
 396                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 397                         continue;
 398                 }
 399
 400                 mmc = find_mmc_device(i);
 401                 if (mmc == NULL)
 402                         continue;
 403                 if (board_mmc_getcd(mmc) > 0)
 404                         mmc_init(mmc);
 405         }
 406         return 0;
 407 }
 408 #endif /* CONFIG_CMD_MMC */
 409
 410 #ifdef CONFIG_FEC_MXC
 411
 412 #ifndef ETH_ALEN
 413 #define ETH_ALEN 6
 414 #endif
 415
 416 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 417 {
 418         int i;
 419         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 420         struct fuse_bank *bank = &iim->bank[1];
 421         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 422
 423         if (dev_id > 0)
 424                 return;
 425
 426         for (i = 0; i < ETH_ALEN; i++)
 427                 mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]);
 428 }
 429
 430 static iomux_v3_cfg_t tx51_fec_pads[] = {
 431         /* reconfigure strap pins for FEC function */
 432         MX51_PAD_NANDF_RB3__FEC_RX_CLK | FEC_PAD_CTRL2,
 433         MX51_PAD_NANDF_D9__FEC_RDATA0 | FEC_PAD_CTRL2,
 434         MX51_PAD_EIM_EB3__FEC_RDATA1 | FEC_PAD_CTRL2,
 435         MX51_PAD_EIM_CS2__FEC_RDATA2 | FEC_PAD_CTRL2,
 436         MX51_PAD_EIM_CS3__FEC_RDATA3 | FEC_PAD_CTRL2,
 437         MX51_PAD_NANDF_RB2__FEC_COL | FEC_PAD_CTRL2,
 438         MX51_PAD_EIM_CS5__FEC_CRS | FEC_PAD_CTRL,
 439 };
 440
 441 /* take bit 4 of PHY address from configured PHY address or
 442  * set it to 0 if PHYADDR is -1 (probe for PHY)
 443  */
 444 #define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5))
 445
 446 static struct gpio tx51_fec_gpios[] = {
 447         { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY POWER", },
 448         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode0", },       /* RXD0/Mode0 */
 449         { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode1", },       /* RXD1/Mode1 */
 450         { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode2", },       /* RXD2/Mode2 */
 451         { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", },     /* RXD3/nINTSEL */
 452 #if PHYAD4
 453         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
 454 #else
 455         { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
 456 #endif
 457 };
 458
 459 int board_eth_init(bd_t *bis)
 460 {
 461         int ret;
 462         unsigned char mac[ETH_ALEN];
 463
 464         /* Power up the external phy and assert strap options */
 465         gpio_request_array(tx51_fec_gpios, ARRAY_SIZE(tx51_fec_gpios));
 466
 467         /* delay at least 21ms for the PHY internal POR signal to deassert */
 468         udelay(22000);
 469
 470         /* Deassert RESET to the external phy */
 471         gpio_set_value(TX51_FEC_RST_GPIO, 1);
 472
 473         /* Without this delay the PHY won't work, though nothing in
 474          * the datasheets suggests that it should be necessary!
 475          */
 476         udelay(400);
 477         imx_iomux_v3_setup_multiple_pads(tx51_fec_pads,
 478                                         ARRAY_SIZE(tx51_fec_pads));
 479
 480         ret = cpu_eth_init(bis);
 481         if (ret) {
 482                 printf("cpu_eth_init() failed: %d\n", ret);
 483                 return ret;
 484         }
 485
 486         imx_get_mac_from_fuse(0, mac);
 487         eth_setenv_enetaddr("ethaddr", mac);
 488         printf("MAC addr from fuse: %pM\n", mac);
 489
 490         return ret;
 491 }
 492 #endif /* CONFIG_FEC_MXC */
 493
 494 enum {
 495         LED_STATE_INIT = -1,
 496         LED_STATE_OFF,
 497         LED_STATE_ON,
 498 };
 499
 500 void show_activity(int arg)
 501 {
 502         static int led_state = LED_STATE_INIT;
 503         static ulong last;
 504
 505         if (led_state == LED_STATE_INIT) {
 506                 last = get_timer(0);
 507                 gpio_set_value(TX51_LED_GPIO, 1);
 508                 led_state = LED_STATE_ON;
 509         } else {
 510                 if (get_timer(last) > CONFIG_SYS_HZ) {
 511                         last = get_timer(0);
 512                         if (led_state == LED_STATE_ON) {
 513                                 gpio_set_value(TX51_LED_GPIO, 0);
 514                         } else {
 515                                 gpio_set_value(TX51_LED_GPIO, 1);
 516                         }
 517                         led_state = 1 - led_state;
 518                 }
 519         }
 520 }
 521
 522 static const iomux_v3_cfg_t stk5_pads[] = {
 523         /* SW controlled LED on STK5 baseboard */
 524         MX51_PAD_CSI2_D13__GPIO4_10 | GPIO_PAD_CTRL,
 525
 526         /* USB PHY reset */
 527         MX51_PAD_GPIO1_4__GPIO1_4 | GPIO_PAD_CTRL,
 528         /* USBOTG OC */
 529         MX51_PAD_GPIO1_6__GPIO1_6 | GPIO_PAD_CTRL,
 530         /* USB PHY clock enable */
 531         MX51_PAD_GPIO1_7__GPIO1_7 | GPIO_PAD_CTRL,
 532         /* USBH1 VBUS enable */
 533         MX51_PAD_GPIO1_8__GPIO1_8 | GPIO_PAD_CTRL,
 534         /* USBH1 OC */
 535         MX51_PAD_GPIO1_9__GPIO1_9 | GPIO_PAD_CTRL,
 536 };
 537
 538 static const struct gpio stk5_gpios[] = {
 539         { TX51_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 540
 541         { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
 542         { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", },
 543         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", },
 544         { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 545         { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", },
 546 };
 547
 548 #ifdef CONFIG_LCD
 549 static ushort tx51_cmap[256];
 550 vidinfo_t panel_info = {
 551         /* set to max. size supported by SoC */
 552         .vl_col = 1600,
 553         .vl_row = 1200,
 554
 555         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 556         .cmap = tx51_cmap,
 557 };
 558
 559 static struct fb_videomode tx51_fb_modes[] = {
 560         {
 561                 /* Standard VGA timing */
 562                 .name           = "VGA",
 563                 .refresh        = 60,
 564                 .xres           = 640,
 565                 .yres           = 480,
 566                 .pixclock       = KHZ2PICOS(25175),
 567                 .left_margin    = 48,
 568                 .hsync_len      = 96,
 569                 .right_margin   = 16,
 570                 .upper_margin   = 31,
 571                 .vsync_len      = 2,
 572                 .lower_margin   = 12,
 573                 .sync           = FB_SYNC_CLK_LAT_FALL,
 574         },
 575         {
 576                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 577                  * DE high active, 115.2 mm x 86.4 mm display area
 578                  * VGA compatible timing
 579                  */
 580                 .name           = "ETV570",
 581                 .refresh        = 60,
 582                 .xres           = 640,
 583                 .yres           = 480,
 584                 .pixclock       = KHZ2PICOS(25175),
 585                 .left_margin    = 114,
 586                 .hsync_len      = 30,
 587                 .right_margin   = 16,
 588                 .upper_margin   = 32,
 589                 .vsync_len      = 3,
 590                 .lower_margin   = 10,
 591                 .sync           = FB_SYNC_CLK_LAT_FALL,
 592         },
 593         {
 594                 /* Emerging ET0350G0DH6 320 x 240 display.
 595                  * 70.08 mm x 52.56 mm display area.
 596                  */
 597                 .name           = "ET0350",
 598                 .refresh        = 60,
 599                 .xres           = 320,
 600                 .yres           = 240,
 601                 .pixclock       = KHZ2PICOS(6500),
 602                 .left_margin    = 68 - 34,
 603                 .hsync_len      = 34,
 604                 .right_margin   = 20,
 605                 .upper_margin   = 18 - 3,
 606                 .vsync_len      = 3,
 607                 .lower_margin   = 4,
 608                 .sync           = FB_SYNC_CLK_LAT_FALL,
 609         },
 610         {
 611                 /* Emerging ET0430G0DH6 480 x 272 display.
 612                  * 95.04 mm x 53.856 mm display area.
 613                  */
 614                 .name           = "ET0430",
 615                 .refresh        = 60,
 616                 .xres           = 480,
 617                 .yres           = 272,
 618                 .pixclock       = KHZ2PICOS(9000),
 619                 .left_margin    = 2,
 620                 .hsync_len      = 41,
 621                 .right_margin   = 2,
 622                 .upper_margin   = 2,
 623                 .vsync_len      = 10,
 624                 .lower_margin   = 2,
 625                 .sync           = FB_SYNC_CLK_LAT_FALL,
 626         },
 627         {
 628                 /* Emerging ET0500G0DH6 800 x 480 display.
 629                  * 109.6 mm x 66.4 mm display area.
 630                  */
 631                 .name           = "ET0500",
 632                 .refresh        = 60,
 633                 .xres           = 800,
 634                 .yres           = 480,
 635                 .pixclock       = KHZ2PICOS(33260),
 636                 .left_margin    = 216 - 128,
 637                 .hsync_len      = 128,
 638                 .right_margin   = 1056 - 800 - 216,
 639                 .upper_margin   = 35 - 2,
 640                 .vsync_len      = 2,
 641                 .lower_margin   = 525 - 480 - 35,
 642                 .sync           = FB_SYNC_CLK_LAT_FALL,
 643         },
 644         {
 645                 /* Emerging ETQ570G0DH6 320 x 240 display.
 646                  * 115.2 mm x 86.4 mm display area.
 647                  */
 648                 .name           = "ETQ570",
 649                 .refresh        = 60,
 650                 .xres           = 320,
 651                 .yres           = 240,
 652                 .pixclock       = KHZ2PICOS(6400),
 653                 .left_margin    = 38,
 654                 .hsync_len      = 30,
 655                 .right_margin   = 30,
 656                 .upper_margin   = 16, /* 15 according to datasheet */
 657                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 658                 .lower_margin   = 4, /* 4.5 according to datasheet */
 659                 .sync           = FB_SYNC_CLK_LAT_FALL,
 660         },
 661         {
 662                 /* Emerging ET0700G0DH6 800 x 480 display.
 663                  * 152.4 mm x 91.44 mm display area.
 664                  */
 665                 .name           = "ET0700",
 666                 .refresh        = 60,
 667                 .xres           = 800,
 668                 .yres           = 480,
 669                 .pixclock       = KHZ2PICOS(33260),
 670                 .left_margin    = 216 - 128,
 671                 .hsync_len      = 128,
 672                 .right_margin   = 1056 - 800 - 216,
 673                 .upper_margin   = 35 - 2,
 674                 .vsync_len      = 2,
 675                 .lower_margin   = 525 - 480 - 35,
 676                 .sync           = FB_SYNC_CLK_LAT_FALL,
 677         },
 678         {
 679                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 680                 .refresh        = 60,
 681                 .left_margin    = 48,
 682                 .hsync_len      = 96,
 683                 .right_margin   = 16,
 684                 .upper_margin   = 31,
 685                 .vsync_len      = 2,
 686                 .lower_margin   = 12,
 687                 .sync           = FB_SYNC_CLK_LAT_FALL,
 688         },
 689 };
 690
 691 static int lcd_enabled = 1;
 692
 693 void lcd_enable(void)
 694 {
 695         /* HACK ALERT:
 696          * global variable from common/lcd.c
 697          * Set to 0 here to prevent messages from going to LCD
 698          * rather than serial console
 699          */
 700         lcd_is_enabled = 0;
 701
 702         karo_load_splashimage(1);
 703         if (lcd_enabled) {
 704                 debug("Switching LCD on\n");
 705                 gpio_set_value(TX51_LCD_PWR_GPIO, 1);
 706                 udelay(100);
 707                 gpio_set_value(TX51_LCD_RST_GPIO, 1);
 708                 udelay(300000);
 709                 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 0);
 710         }
 711 }
 712
 713 void lcd_disable(void)
 714 {
 715         printf("Disabling LCD\n");
 716 }
 717
 718 void lcd_panel_disable(void)
 719 {
 720         if (lcd_enabled) {
 721                 debug("Switching LCD off\n");
 722                 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 1);
 723                 gpio_set_value(TX51_LCD_RST_GPIO, 0);
 724                 gpio_set_value(TX51_LCD_PWR_GPIO, 0);
 725         }
 726 }
 727
 728 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 729         /* LCD RESET */
 730         MX51_PAD_CSI2_VSYNC__GPIO4_13,
 731         /* LCD POWER_ENABLE */
 732         MX51_PAD_CSI2_HSYNC__GPIO4_14,
 733         /* LCD Backlight (PWM) */
 734         MX51_PAD_GPIO1_2__GPIO1_2,
 735
 736         /* Display */
 737         MX51_PAD_DISP1_DAT0__DISP1_DAT0,
 738         MX51_PAD_DISP1_DAT1__DISP1_DAT1,
 739         MX51_PAD_DISP1_DAT2__DISP1_DAT2,
 740         MX51_PAD_DISP1_DAT3__DISP1_DAT3,
 741         MX51_PAD_DISP1_DAT4__DISP1_DAT4,
 742         MX51_PAD_DISP1_DAT5__DISP1_DAT5,
 743         MX51_PAD_DISP1_DAT6__DISP1_DAT6,
 744         MX51_PAD_DISP1_DAT7__DISP1_DAT7,
 745         MX51_PAD_DISP1_DAT8__DISP1_DAT8,
 746         MX51_PAD_DISP1_DAT9__DISP1_DAT9,
 747         MX51_PAD_DISP1_DAT10__DISP1_DAT10,
 748         MX51_PAD_DISP1_DAT11__DISP1_DAT11,
 749         MX51_PAD_DISP1_DAT12__DISP1_DAT12,
 750         MX51_PAD_DISP1_DAT13__DISP1_DAT13,
 751         MX51_PAD_DISP1_DAT14__DISP1_DAT14,
 752         MX51_PAD_DISP1_DAT15__DISP1_DAT15,
 753         MX51_PAD_DISP1_DAT16__DISP1_DAT16,
 754         MX51_PAD_DISP1_DAT17__DISP1_DAT17,
 755         MX51_PAD_DISP1_DAT18__DISP1_DAT18,
 756         MX51_PAD_DISP1_DAT19__DISP1_DAT19,
 757         MX51_PAD_DISP1_DAT20__DISP1_DAT20,
 758         MX51_PAD_DISP1_DAT21__DISP1_DAT21,
 759         MX51_PAD_DISP1_DAT22__DISP1_DAT22,
 760         MX51_PAD_DISP1_DAT23__DISP1_DAT23,
 761         MX51_PAD_DI1_PIN2__DI1_PIN2, /* HSYNC */
 762         MX51_PAD_DI1_PIN3__DI1_PIN3, /* VSYNC */
 763 };
 764
 765 static const struct gpio stk5_lcd_gpios[] = {
 766         { TX51_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 767         { TX51_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 768         { TX51_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 769 };
 770
 771 void lcd_ctrl_init(void *lcdbase)
 772 {
 773         int color_depth = 24;
 774         char *vm;
 775         unsigned long val;
 776         int refresh = 60;
 777         struct fb_videomode *p = &tx51_fb_modes[0];
 778         struct fb_videomode fb_mode;
 779         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 780         int pix_fmt = 0;
 781         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 782         unsigned long di_clk_rate = 65000000;
 783
 784         if (!lcd_enabled) {
 785                 debug("LCD disabled\n");
 786                 return;
 787         }
 788
 789         if (tstc() || (wrsr & WRSR_TOUT)) {
 790                 debug("Disabling LCD\n");
 791                 lcd_enabled = 0;
 792                 return;
 793         }
 794
 795         karo_fdt_move_fdt();
 796
 797         vm = getenv("video_mode");
 798         if (vm == NULL) {
 799                 debug("Disabling LCD\n");
 800                 lcd_enabled = 0;
 801                 return;
 802         }
 803         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 804                 p = &fb_mode;
 805                 debug("Using video mode from FDT\n");
 806                 vm += strlen(vm);
 807                 if (fb_mode.xres < panel_info.vl_col)
 808                         panel_info.vl_col = fb_mode.xres;
 809                 if (fb_mode.yres < panel_info.vl_row)
 810                         panel_info.vl_row = fb_mode.yres;
 811         }
 812         if (p->name != NULL)
 813                 debug("Trying compiled-in video modes\n");
 814         while (p->name != NULL) {
 815                 if (strcmp(p->name, vm) == 0) {
 816                         debug("Using video mode: '%s'\n", p->name);
 817                         vm += strlen(vm);
 818                         break;
 819                 }
 820                 p++;
 821         }
 822         if (*vm != '\0')
 823                 debug("Trying to decode video_mode: '%s'\n", vm);
 824         while (*vm != '\0') {
 825                 if (*vm >= '0' && *vm <= '9') {
 826                         char *end;
 827
 828                         val = simple_strtoul(vm, &end, 0);
 829                         if (end > vm) {
 830                                 if (!xres_set) {
 831                                         if (val > panel_info.vl_col)
 832                                                 val = panel_info.vl_col;
 833                                         p->xres = val;
 834                                         panel_info.vl_col = val;
 835                                         xres_set = 1;
 836                                 } else if (!yres_set) {
 837                                         if (val > panel_info.vl_row)
 838                                                 val = panel_info.vl_row;
 839                                         p->yres = val;
 840                                         panel_info.vl_row = val;
 841                                         yres_set = 1;
 842                                 } else if (!bpp_set) {
 843                                         switch (val) {
 844                                         case 8:
 845                                         case 16:
 846                                         case 24:
 847                                                 color_depth = val;
 848                                                 break;
 849
 850                                         default:
 851                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 852                                                         end - vm, vm, color_depth);
 853                                         }
 854                                         bpp_set = 1;
 855                                 } else if (!refresh_set) {
 856                                         refresh = val;
 857                                         refresh_set = 1;
 858                                 }
 859                         }
 860                         vm = end;
 861                 }
 862                 switch (*vm) {
 863                 case '@':
 864                         bpp_set = 1;
 865                         /* fallthru */
 866                 case '-':
 867                         yres_set = 1;
 868                         /* fallthru */
 869                 case 'x':
 870                         xres_set = 1;
 871                         /* fallthru */
 872                 case 'M':
 873                 case 'R':
 874                         vm++;
 875                         break;
 876
 877                 default:
 878                         if (!pix_fmt) {
 879                                 char *tmp;
 880
 881                                 pix_fmt = IPU_PIX_FMT_RGB24;
 882                                 tmp = strchr(vm, ':');
 883                                 if (tmp)
 884                                         vm = tmp;
 885                         }
 886                         if (*vm != '\0')
 887                                 vm++;
 888                 }
 889         }
 890         if (p->xres == 0 || p->yres == 0) {
 891                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 892                 lcd_enabled = 0;
 893                 printf("Supported video modes are:");
 894                 for (p = &tx51_fb_modes[0]; p->name != NULL; p++) {
 895                         printf(" %s", p->name);
 896                 }
 897                 printf("\n");
 898                 return;
 899         }
 900
 901         p->pixclock = KHZ2PICOS(refresh *
 902                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 903                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 904                 / 1000);
 905         debug("Pixel clock set to %lu.%03lu MHz\n",
 906                 PICOS2KHZ(p->pixclock) / 1000,
 907                 PICOS2KHZ(p->pixclock) % 1000);
 908
 909         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 910         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 911                                         ARRAY_SIZE(stk5_lcd_pads));
 912
 913         debug("Initializing FB driver\n");
 914         if (!pix_fmt)
 915                 pix_fmt = IPU_PIX_FMT_RGB24;
 916
 917         if (karo_load_splashimage(0) == 0) {
 918                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 919                 u32 ccgr4 = readl(&ccm_regs->CCGR4);
 920
 921                 /* MIPI HSC clock is required for initialization */
 922                 writel(ccgr4 | (3 << 12), &ccm_regs->CCGR4);
 923
 924                 debug("Initializing LCD controller\n");
 925                 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
 926
 927                 writel(ccgr4 & ~(3 << 12), &ccm_regs->CCGR4);
 928         } else {
 929                 debug("Skipping initialization of LCD controller\n");
 930         }
 931 }
 932 #else
 933 #define lcd_enabled 0
 934 #endif /* CONFIG_LCD */
 935
 936 static void stk5_board_init(void)
 937 {
 938         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 939         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 940 }
 941
 942 static void stk5v3_board_init(void)
 943 {
 944         stk5_board_init();
 945 }
 946
 947 static void tx51_set_cpu_clock(void)
 948 {
 949         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 950         int ret;
 951
 952         if (tstc() || (wrsr & WRSR_TOUT))
 953                 return;
 954
 955         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
 956                 return;
 957
 958         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
 959         if (ret != 0) {
 960                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
 961                 return;
 962         }
 963         printf("CPU clock set to %u.%03u MHz\n",
 964                 mxc_get_clock(MXC_ARM_CLK) / 1000000,
 965                 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
 966 }
 967
 968 int board_late_init(void)
 969 {
 970         int ret = 0;
 971         const char *baseboard;
 972
 973         tx51_set_cpu_clock();
 974         karo_fdt_move_fdt();
 975
 976         baseboard = getenv("baseboard");
 977         if (!baseboard)
 978                 goto exit;
 979
 980         if (strncmp(baseboard, "stk5", 4) == 0) {
 981                 printf("Baseboard: %s\n", baseboard);
 982                 if ((strlen(baseboard) == 4) ||
 983                         strcmp(baseboard, "stk5-v3") == 0) {
 984                         stk5v3_board_init();
 985                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 986                         printf("ERROR: Baseboard '%s' incompatible with TX51 module!\n",
 987                                 baseboard);
 988                         stk5v3_board_init();
 989                 } else {
 990                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 991                                 baseboard + 4);
 992                 }
 993         } else {
 994                 printf("WARNING: Unsupported baseboard: '%s'\n",
 995                         baseboard);
 996                 ret = -EINVAL;
 997         }
 998
 999 exit:
1000         gpio_set_value(TX51_RESET_OUT_GPIO, 1);
1001         return ret;
1002 }
1003
1004 int checkboard(void)
1005 {
1006         tx51_print_cpuinfo();
1007
1008         printf("Board: Ka-Ro TX51-%sxx%s\n",
1009                 TX51_MOD_PREFIX, TX51_MOD_SUFFIX);
1010
1011         return 0;
1012 }
1013
1014 #if defined(CONFIG_OF_BOARD_SETUP)
1015 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1016 #include <jffs2/jffs2.h>
1017 #include <mtd_node.h>
1018 struct node_info nodes[] = {
1019         { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, },
1020 };
1021
1022 #else
1023 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1024 #endif
1025
1026 void ft_board_setup(void *blob, bd_t *bd)
1027 {
1028         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1029         fdt_fixup_ethernet(blob);
1030
1031         karo_fdt_fixup_touchpanel(blob);
1032         karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
1033 }
1034 #endif