2 * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
14 #include <fsl_esdhc.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
29 #include "../common/karo.h"
32 #define __data __attribute__((section(".data")))
34 #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
35 #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
36 #define TX6_FEC_INT_GPIO IMX_GPIO_NR(7, 1)
37 #define TX6_LED_GPIO IMX_GPIO_NR(2, 20)
39 #define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
40 #define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
41 #define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
43 #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
44 #define TX6_I2C1_SCL_GPIO IMX_GPIO_NR(3, 21)
45 #define TX6_I2C1_SDA_GPIO IMX_GPIO_NR(3, 28)
47 #ifdef CONFIG_MX6_TEMPERATURE_MIN
48 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
50 #define TEMPERATURE_MIN (-40)
52 #ifdef CONFIG_MX6_TEMPERATURE_HOT
53 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
55 #define TEMPERATURE_HOT 80
58 DECLARE_GLOBAL_DATA_PTR;
60 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
63 #ifdef CONFIG_SECURE_BOOT
64 char __csf_data[0] __attribute__((section(".__csf_data")));
67 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
69 MX6_PAD_GPIO_17__GPIO7_IO12,
72 #if CONFIG_MXC_UART_BASE == UART1_BASE
73 MX6_PAD_SD3_DAT7__UART1_TX_DATA,
74 MX6_PAD_SD3_DAT6__UART1_RX_DATA,
75 MX6_PAD_SD3_DAT1__UART1_RTS_B,
76 MX6_PAD_SD3_DAT0__UART1_CTS_B,
78 #if CONFIG_MXC_UART_BASE == UART2_BASE
79 MX6_PAD_SD4_DAT4__UART2_RX_DATA,
80 MX6_PAD_SD4_DAT7__UART2_TX_DATA,
81 MX6_PAD_SD4_DAT5__UART2_RTS_B,
82 MX6_PAD_SD4_DAT6__UART2_CTS_B,
84 #if CONFIG_MXC_UART_BASE == UART3_BASE
85 MX6_PAD_EIM_D24__UART3_TX_DATA,
86 MX6_PAD_EIM_D25__UART3_RX_DATA,
87 MX6_PAD_SD3_RST__UART3_RTS_B,
88 MX6_PAD_SD3_DAT3__UART3_CTS_B,
91 MX6_PAD_EIM_D28__I2C1_SDA,
92 MX6_PAD_EIM_D21__I2C1_SCL,
94 /* FEC PHY GPIO functions */
95 MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
96 MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
97 MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
100 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
102 MX6_PAD_ENET_MDC__ENET_MDC,
103 MX6_PAD_ENET_MDIO__ENET_MDIO,
104 MX6_PAD_GPIO_16__ENET_REF_CLK,
105 MX6_PAD_ENET_RX_ER__ENET_RX_ER,
106 MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
107 MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
108 MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
109 MX6_PAD_ENET_TX_EN__ENET_TX_EN,
110 MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
111 MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
114 #define TX6_I2C_GPIO_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
115 PAD_CTL_SPEED_MED | \
116 PAD_CTL_DSE_34ohm | \
119 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
121 MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
122 MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
125 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
127 MX6_PAD_EIM_D28__I2C1_SDA,
128 MX6_PAD_EIM_D21__I2C1_SCL,
131 static const struct gpio const tx6qdl_gpios[] = {
132 /* These two entries are used to forcefully reinitialize the I2C bus */
133 { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
134 { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
136 { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
137 { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
138 { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
139 { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
142 static int pmic_addr __data;
144 #if defined(CONFIG_SOC_MX6Q)
145 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e00a4
146 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e00c4
147 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e03b8
148 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e03d8
149 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0898
150 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e089c
151 #define I2C1_SEL_INPUT_VAL 0
153 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
154 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e0158
155 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e0174
156 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e0528
157 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e0544
158 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0868
159 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e086c
160 #define I2C1_SEL_INPUT_VAL 1
167 static void tx6_i2c_recover(void)
171 #define SCL_BIT (1 << (TX6_I2C1_SCL_GPIO % 32))
172 #define SDA_BIT (1 << (TX6_I2C1_SDA_GPIO % 32))
174 if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
175 (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
178 debug("Clearing I2C bus\n");
179 if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
180 printf("I2C SCL stuck LOW\n");
183 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
184 GPIO3_BASE_ADDR + GPIO_DR);
185 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
186 GPIO3_BASE_ADDR + GPIO_DIR);
188 if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
189 printf("I2C SDA stuck LOW\n");
192 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
193 GPIO3_BASE_ADDR + GPIO_DIR);
194 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
195 GPIO3_BASE_ADDR + GPIO_DR);
196 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
197 GPIO3_BASE_ADDR + GPIO_DIR);
199 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
200 ARRAY_SIZE(tx6_i2c_gpio_pads));
203 for (i = 0; i < 18; i++) {
204 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
206 debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
207 writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
210 readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
215 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
217 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
218 printf("I2C bus recovery succeeded\n");
220 printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
224 debug("Setting up I2C Pads\n");
225 imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
226 ARRAY_SIZE(tx6_i2c_pads));
229 /* placed in section '.data' to prevent overwriting relocation info
232 static u32 wrsr __data;
234 #define WRSR_POR (1 << 4)
235 #define WRSR_TOUT (1 << 1)
236 #define WRSR_SFTW (1 << 0)
238 static void print_reset_cause(void)
240 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
241 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
245 printf("Reset cause: ");
247 srsr = readl(&src_regs->srsr);
248 wrsr = readw(wdt_base + 4);
250 if (wrsr & WRSR_POR) {
251 printf("%sPOR", dlm);
254 if (srsr & 0x00004) {
255 printf("%sCSU", dlm);
258 if (srsr & 0x00008) {
259 printf("%sIPP USER", dlm);
262 if (srsr & 0x00010) {
263 if (wrsr & WRSR_SFTW) {
264 printf("%sSOFT", dlm);
267 if (wrsr & WRSR_TOUT) {
268 printf("%sWDOG", dlm);
272 if (srsr & 0x00020) {
273 printf("%sJTAG HIGH-Z", dlm);
276 if (srsr & 0x00040) {
277 printf("%sJTAG SW", dlm);
280 if (srsr & 0x10000) {
281 printf("%sWARM BOOT", dlm);
290 static const char __data *tx6_mod_suffix;
292 #ifdef CONFIG_IMX6_THERMAL
294 #include <imx_thermal.h>
297 static void print_temperature(void)
299 struct udevice *thermal_dev;
300 int cpu_tmp, minc, maxc, ret;
301 char const *grade_str;
302 static u32 __data thermal_calib;
304 puts("Temperature: ");
305 switch (get_cpu_temp_grade(&minc, &maxc)) {
306 case TEMP_AUTOMOTIVE:
307 grade_str = "Automotive";
309 case TEMP_INDUSTRIAL:
310 grade_str = "Industrial";
312 case TEMP_EXTCOMMERCIAL:
313 grade_str = "Extended Commercial";
316 grade_str = "Commercial";
318 printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
319 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
321 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
324 printf(" at %dC", cpu_tmp);
326 puts(" - failed to read sensor data");
328 puts(" - no sensor device found");
331 if (fuse_read(1, 6, &thermal_calib) == 0) {
332 printf(" - calibration data 0x%08x\n", thermal_calib);
334 puts(" - Failed to read thermal calib fuse\n");
338 static inline void print_temperature(void)
345 u32 cpurev = get_cpu_rev();
348 if (is_cpu_type(MXC_CPU_MX6SL)) {
350 tx6_mod_suffix = "?";
351 } else if (is_cpu_type(MXC_CPU_MX6DL)) {
353 tx6_mod_suffix = "U";
354 } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
356 tx6_mod_suffix = "S";
357 } else if (is_cpu_type(MXC_CPU_MX6Q)) {
359 tx6_mod_suffix = "Q";
362 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
364 (cpurev & 0x000F0) >> 4,
365 (cpurev & 0x0000F) >> 0,
366 mxc_get_clock(MXC_ARM_CLK) / 1000000);
370 #ifdef CONFIG_MX6_TEMPERATURE_HOT
371 check_cpu_temperature(1);
377 /* serial port not initialized at this point */
378 int board_early_init_f(void)
383 #ifndef CONFIG_MX6_TEMPERATURE_HOT
384 static bool tx6_temp_check_enabled = true;
386 #define tx6_temp_check_enabled 0
389 #ifdef CONFIG_TX6_NAND
390 #define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
392 #ifdef CONFIG_MMC_BOOT_SIZE
393 #define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
395 #define TX6_FLASH_SZ 2
397 #endif /* CONFIG_TX6_NAND */
399 #define TX6_DDR_SZ (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
401 static char tx6_mem_table[] = {
402 '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
403 '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
404 '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
405 '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
406 '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
407 '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
408 '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
409 '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
410 '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
411 '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
412 '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
413 '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
425 static inline char tx6_mem_suffix(void)
427 size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
429 debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
430 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
432 if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
435 return tx6_mem_table[mem_idx];
438 static int tx6_get_mod_rev(unsigned int pmic_id)
440 if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
441 return tx6_mod_revs[pmic_id].rev;
446 static int tx6_pmic_probe(void)
450 debug("%s@%d: \n", __func__, __LINE__);
452 for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
453 u8 i2c_addr = tx6_mod_revs[i].addr;
454 int ret = i2c_probe(i2c_addr);
457 debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
460 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
470 debug("%s@%d: \n", __func__, __LINE__);
472 pmic_id = tx6_pmic_probe();
473 if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs))
474 pmic_addr = tx6_mod_revs[pmic_id].addr;
476 printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
478 is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8,
479 is_lvds(), tx6_get_mod_rev(pmic_id),
484 ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
486 printf("Failed to request tx6qdl_gpios: %d\n", ret);
488 imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
490 /* Address of boot parameters */
491 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
492 gd->bd->bi_arch_number = -1;
494 if (ctrlc() || (wrsr & WRSR_TOUT)) {
495 if (wrsr & WRSR_TOUT)
496 printf("WDOG RESET detected; Skipping PMIC setup\n");
498 printf("<CTRL-C> detected; safeboot enabled\n");
499 #ifndef CONFIG_MX6_TEMPERATURE_HOT
500 tx6_temp_check_enabled = false;
505 ret = tx6_pmic_init(pmic_addr, NULL, 0);
507 printf("Failed to setup PMIC voltages: %d\n", ret);
515 debug("%s@%d: \n", __func__, __LINE__);
517 /* dram_init must store complete ramsize in gd->ram_size */
518 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
519 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
523 void dram_init_banksize(void)
525 debug("%s@%d: chip_size=%u (%u bit bus width)\n", __func__, __LINE__,
526 CONFIG_SYS_SDRAM_CHIP_SIZE, CONFIG_SYS_SDRAM_BUS_WIDTH);
527 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
528 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
530 #if CONFIG_NR_DRAM_BANKS > 1
531 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
532 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
537 #ifdef CONFIG_FSL_ESDHC
538 #define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
539 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
542 static const iomux_v3_cfg_t mmc0_pads[] = {
543 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
544 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
545 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
546 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
547 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
548 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
550 MX6_PAD_SD3_CMD__GPIO7_IO02,
553 static const iomux_v3_cfg_t mmc1_pads[] = {
554 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
555 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
556 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
557 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
558 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
559 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
561 MX6_PAD_SD3_CLK__GPIO7_IO03,
564 #ifdef CONFIG_TX6_EMMC
565 static const iomux_v3_cfg_t mmc3_pads[] = {
566 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
567 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
568 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
569 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
570 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
571 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
573 MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
578 static struct tx6_esdhc_cfg {
579 const iomux_v3_cfg_t *pads;
581 enum mxc_clock clkid;
582 struct fsl_esdhc_cfg cfg;
584 } tx6qdl_esdhc_cfg[] = {
585 #ifdef CONFIG_TX6_EMMC
588 .num_pads = ARRAY_SIZE(mmc3_pads),
589 .clkid = MXC_ESDHC4_CLK,
591 .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
599 .num_pads = ARRAY_SIZE(mmc0_pads),
600 .clkid = MXC_ESDHC_CLK,
602 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
605 .cd_gpio = IMX_GPIO_NR(7, 2),
609 .num_pads = ARRAY_SIZE(mmc1_pads),
610 .clkid = MXC_ESDHC2_CLK,
612 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
615 .cd_gpio = IMX_GPIO_NR(7, 3),
619 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
621 return container_of(cfg, struct tx6_esdhc_cfg, cfg);
624 int board_mmc_getcd(struct mmc *mmc)
626 struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
628 if (cfg->cd_gpio < 0)
631 debug("SD card %d is %spresent (GPIO %d)\n",
632 cfg - tx6qdl_esdhc_cfg,
633 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
635 return !gpio_get_value(cfg->cd_gpio);
638 int board_mmc_init(bd_t *bis)
642 debug("%s@%d: \n", __func__, __LINE__);
644 for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
646 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
649 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
650 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
652 if (cfg->cd_gpio >= 0) {
653 ret = gpio_request_one(cfg->cd_gpio,
654 GPIOFLAG_INPUT, "MMC CD");
656 printf("Error %d requesting GPIO%d_%d\n",
657 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
662 debug("%s: Initializing MMC slot %d\n", __func__, i);
663 fsl_esdhc_initialize(bis, &cfg->cfg);
665 mmc = find_mmc_device(i);
668 if (board_mmc_getcd(mmc))
673 #endif /* CONFIG_CMD_MMC */
675 #ifdef CONFIG_FEC_MXC
681 int board_eth_init(bd_t *bis)
685 debug("%s@%d: \n", __func__, __LINE__);
687 /* delay at least 21ms for the PHY internal POR signal to deassert */
690 imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
691 ARRAY_SIZE(tx6qdl_fec_pads));
693 /* Deassert RESET to the external phy */
694 gpio_set_value(TX6_FEC_RST_GPIO, 1);
696 ret = cpu_eth_init(bis);
698 printf("cpu_eth_init() failed: %d\n", ret);
703 static void tx6_init_mac(void)
707 imx_get_mac_from_fuse(0, mac);
708 if (!is_valid_ethaddr(mac)) {
709 printf("No valid MAC address programmed\n");
713 printf("MAC addr from fuse: %pM\n", mac);
714 eth_setenv_enetaddr("ethaddr", mac);
717 static inline void tx6_init_mac(void)
720 #endif /* CONFIG_FEC_MXC */
728 static inline int calc_blink_rate(void)
730 if (!tx6_temp_check_enabled)
731 return CONFIG_SYS_HZ;
733 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
734 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
735 (TEMPERATURE_HOT - TEMPERATURE_MIN);
738 void show_activity(int arg)
740 static int led_state = LED_STATE_INIT;
741 static int blink_rate;
744 if (led_state == LED_STATE_INIT) {
746 gpio_set_value(TX6_LED_GPIO, 1);
747 led_state = LED_STATE_ON;
748 blink_rate = calc_blink_rate();
750 if (get_timer(last) > blink_rate) {
751 blink_rate = calc_blink_rate();
752 last = get_timer_masked();
753 if (led_state == LED_STATE_ON) {
754 gpio_set_value(TX6_LED_GPIO, 0);
756 gpio_set_value(TX6_LED_GPIO, 1);
758 led_state = 1 - led_state;
763 static const iomux_v3_cfg_t stk5_pads[] = {
764 /* SW controlled LED on STK5 baseboard */
765 MX6_PAD_EIM_A18__GPIO2_IO20,
767 /* I2C bus on DIMM pins 40/41 */
768 MX6_PAD_GPIO_6__I2C3_SDA,
769 MX6_PAD_GPIO_3__I2C3_SCL,
771 /* TSC200x PEN IRQ */
772 MX6_PAD_EIM_D26__GPIO3_IO26,
774 /* EDT-FT5x06 Polytouch panel */
775 MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
776 MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
777 MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
780 MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
781 MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
783 MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
784 MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
785 MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
788 static const struct gpio stk5_gpios[] = {
789 { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
791 { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
792 { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
793 { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
794 { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
795 { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
799 vidinfo_t panel_info = {
800 /* set to max. size supported by SoC */
804 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
807 static struct fb_videomode tx6_fb_modes[] = {
808 #ifndef CONFIG_SYS_LVDS_IF
810 /* Standard VGA timing */
815 .pixclock = KHZ2PICOS(25175),
822 .sync = FB_SYNC_CLK_LAT_FALL,
825 /* Emerging ETV570 640 x 480 display. Syncs low active,
826 * DE high active, 115.2 mm x 86.4 mm display area
827 * VGA compatible timing
833 .pixclock = KHZ2PICOS(25175),
840 .sync = FB_SYNC_CLK_LAT_FALL,
843 /* Emerging ET0350G0DH6 320 x 240 display.
844 * 70.08 mm x 52.56 mm display area.
850 .pixclock = KHZ2PICOS(6500),
851 .left_margin = 68 - 34,
854 .upper_margin = 18 - 3,
857 .sync = FB_SYNC_CLK_LAT_FALL,
860 /* Emerging ET0430G0DH6 480 x 272 display.
861 * 95.04 mm x 53.856 mm display area.
867 .pixclock = KHZ2PICOS(9000),
876 /* Emerging ET0500G0DH6 800 x 480 display.
877 * 109.6 mm x 66.4 mm display area.
883 .pixclock = KHZ2PICOS(33260),
884 .left_margin = 216 - 128,
886 .right_margin = 1056 - 800 - 216,
887 .upper_margin = 35 - 2,
889 .lower_margin = 525 - 480 - 35,
890 .sync = FB_SYNC_CLK_LAT_FALL,
893 /* Emerging ETQ570G0DH6 320 x 240 display.
894 * 115.2 mm x 86.4 mm display area.
900 .pixclock = KHZ2PICOS(6400),
904 .upper_margin = 16, /* 15 according to datasheet */
905 .vsync_len = 3, /* TVP -> 1>x>5 */
906 .lower_margin = 4, /* 4.5 according to datasheet */
907 .sync = FB_SYNC_CLK_LAT_FALL,
910 /* Emerging ET0700G0DH6 800 x 480 display.
911 * 152.4 mm x 91.44 mm display area.
917 .pixclock = KHZ2PICOS(33260),
918 .left_margin = 216 - 128,
920 .right_margin = 1056 - 800 - 216,
921 .upper_margin = 35 - 2,
923 .lower_margin = 525 - 480 - 35,
924 .sync = FB_SYNC_CLK_LAT_FALL,
927 /* Emerging ET070001DM6 800 x 480 display.
928 * 152.4 mm x 91.44 mm display area.
930 .name = "ET070001DM6",
934 .pixclock = KHZ2PICOS(33260),
935 .left_margin = 216 - 128,
937 .right_margin = 1056 - 800 - 216,
938 .upper_margin = 35 - 2,
940 .lower_margin = 525 - 480 - 35,
945 /* HannStar HSD100PXN1
946 * 202.7m mm x 152.06 mm display area.
948 .name = "HSD100PXN1",
952 .pixclock = KHZ2PICOS(65000),
959 .sync = FB_SYNC_CLK_LAT_FALL,
963 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
971 .sync = FB_SYNC_CLK_LAT_FALL,
975 static int lcd_enabled = 1;
976 static int lcd_bl_polarity;
978 static int lcd_backlight_polarity(void)
980 return lcd_bl_polarity;
983 void lcd_enable(void)
986 * global variable from common/lcd.c
987 * Set to 0 here to prevent messages from going to LCD
988 * rather than serial console
993 karo_load_splashimage(1);
995 debug("Switching LCD on\n");
996 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
998 gpio_set_value(TX6_LCD_RST_GPIO, 1);
1000 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1001 lcd_backlight_polarity());
1005 void lcd_disable(void)
1008 printf("Disabling LCD\n");
1009 ipuv3_fb_shutdown();
1013 void lcd_panel_disable(void)
1016 debug("Switching LCD off\n");
1017 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1018 !lcd_backlight_polarity());
1019 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1020 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1024 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1026 MX6_PAD_EIM_D29__GPIO3_IO29,
1027 /* LCD POWER_ENABLE */
1028 MX6_PAD_EIM_EB3__GPIO2_IO31,
1029 /* LCD Backlight (PWM) */
1030 MX6_PAD_GPIO_1__GPIO1_IO01,
1032 #ifndef CONFIG_SYS_LVDS_IF
1034 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
1035 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
1036 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
1037 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
1038 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
1039 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
1040 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
1041 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
1042 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
1043 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
1044 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
1045 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
1046 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
1047 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
1048 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
1049 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
1050 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
1051 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
1052 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
1053 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
1054 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
1055 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
1056 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
1057 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
1058 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
1059 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
1060 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
1061 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
1065 static const struct gpio stk5_lcd_gpios[] = {
1066 { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1067 { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1068 { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1071 void lcd_ctrl_init(void *lcdbase)
1073 int color_depth = 24;
1074 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1078 struct fb_videomode *p = &tx6_fb_modes[0];
1079 struct fb_videomode fb_mode;
1080 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1083 unsigned long di_clk_rate = 65000000;
1086 debug("LCD disabled\n");
1091 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1092 debug("Disabling LCD\n");
1094 setenv("splashimage", NULL);
1099 karo_fdt_move_fdt();
1100 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1102 if (video_mode == NULL) {
1103 debug("Disabling LCD\n");
1109 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1111 debug("Using video mode from FDT\n");
1113 if (fb_mode.xres > panel_info.vl_col ||
1114 fb_mode.yres > panel_info.vl_row) {
1115 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1116 fb_mode.xres, fb_mode.yres,
1117 panel_info.vl_col, panel_info.vl_row);
1123 if (p->name != NULL)
1124 debug("Trying compiled-in video modes\n");
1125 while (p->name != NULL) {
1126 if (strcmp(p->name, vm) == 0) {
1127 debug("Using video mode: '%s'\n", p->name);
1134 debug("Trying to decode video_mode: '%s'\n", vm);
1135 while (*vm != '\0') {
1136 if (*vm >= '0' && *vm <= '9') {
1139 val = simple_strtoul(vm, &end, 0);
1142 if (val > panel_info.vl_col)
1143 val = panel_info.vl_col;
1145 panel_info.vl_col = val;
1147 } else if (!yres_set) {
1148 if (val > panel_info.vl_row)
1149 val = panel_info.vl_row;
1151 panel_info.vl_row = val;
1153 } else if (!bpp_set) {
1158 pix_fmt = IPU_PIX_FMT_LVDS888;
1172 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1173 end - vm, vm, color_depth);
1176 } else if (!refresh_set) {
1203 if (p->xres == 0 || p->yres == 0) {
1204 printf("Invalid video mode: %s\n", getenv("video_mode"));
1206 printf("Supported video modes are:");
1207 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1208 printf(" %s", p->name);
1214 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1215 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1216 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1221 panel_info.vl_col = p->xres;
1222 panel_info.vl_row = p->yres;
1224 switch (color_depth) {
1226 panel_info.vl_bpix = LCD_COLOR8;
1229 panel_info.vl_bpix = LCD_COLOR16;
1232 panel_info.vl_bpix = LCD_COLOR32;
1235 p->pixclock = KHZ2PICOS(refresh *
1236 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1237 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1239 debug("Pixel clock set to %lu.%03lu MHz\n",
1240 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1242 if (p != &fb_mode) {
1245 debug("Creating new display-timing node from '%s'\n",
1247 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1249 printf("Failed to create new display-timing node from '%s': %d\n",
1253 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1254 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1255 ARRAY_SIZE(stk5_lcd_pads));
1257 lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1258 switch (lcd_bus_width) {
1260 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1264 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1269 pix_fmt = IPU_PIX_FMT_RGB565;
1275 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1281 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1282 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1286 if (lvds_chan_mask == 0) {
1287 printf("No LVDS channel active\n");
1293 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1294 if (lcd_bus_width == 24)
1295 gpr2 |= (1 << 5) | (1 << 7);
1296 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1297 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1298 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1299 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1301 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1302 gpr3 &= ~((3 << 8) | (3 << 6));
1303 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1305 if (karo_load_splashimage(0) == 0) {
1308 debug("Initializing LCD controller\n");
1309 ret = ipuv3_fb_init(p, 0, pix_fmt,
1310 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1313 printf("Failed to initialize FB driver: %d\n", ret);
1317 debug("Skipping initialization of LCD controller\n");
1323 panel_info.vl_col = 0;
1324 panel_info.vl_row = 0;
1328 #define lcd_enabled 0
1329 #endif /* CONFIG_LCD */
1331 static void stk5_board_init(void)
1335 ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1337 printf("Failed to request stk5_gpios: %d\n", ret);
1340 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1343 static void stk5v3_board_init(void)
1348 static void stk5v5_board_init(void)
1354 ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1355 "Flexcan Transceiver");
1357 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1361 imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
1364 static void tx6qdl_set_cpu_clock(void)
1366 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1368 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1371 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1372 printf("%s detected; skipping cpu clock change\n",
1373 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1376 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1377 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1378 printf("CPU clock set to %lu.%03lu MHz\n",
1379 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1381 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1385 int board_late_init(void)
1387 const char *baseboard;
1389 debug("%s@%d: \n", __func__, __LINE__);
1393 if (tx6_temp_check_enabled)
1394 check_cpu_temperature(1);
1396 tx6qdl_set_cpu_clock();
1399 setenv_ulong("safeboot", 1);
1400 else if (wrsr & WRSR_TOUT)
1401 setenv_ulong("wdreset", 1);
1403 karo_fdt_move_fdt();
1405 baseboard = getenv("baseboard");
1409 printf("Baseboard: %s\n", baseboard);
1411 if (strncmp(baseboard, "stk5", 4) == 0) {
1412 if ((strlen(baseboard) == 4) ||
1413 strcmp(baseboard, "stk5-v3") == 0) {
1414 stk5v3_board_init();
1415 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1416 const char *otg_mode = getenv("otg_mode");
1418 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1419 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1420 otg_mode, baseboard);
1421 setenv("otg_mode", "none");
1423 stk5v5_board_init();
1425 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1429 printf("WARNING: Unsupported baseboard: '%s'\n",
1438 gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1443 #ifdef CONFIG_SERIAL_TAG
1444 void get_board_serial(struct tag_serialnr *serialnr)
1446 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1447 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1449 serialnr->low = readl(&fuse->cfg0);
1450 serialnr->high = readl(&fuse->cfg1);
1454 #if defined(CONFIG_OF_BOARD_SETUP)
1455 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1456 #include <jffs2/jffs2.h>
1457 #include <mtd_node.h>
1458 static struct node_info nodes[] = {
1459 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1462 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1465 static const char *tx6_touchpanels[] = {
1471 int ft_board_setup(void *blob, bd_t *bd)
1473 const char *baseboard = getenv("baseboard");
1474 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1475 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1478 ret = fdt_increase_size(blob, 4096);
1480 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1484 karo_fdt_enable_node(blob, "stk5led", 0);
1486 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1488 karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1489 ARRAY_SIZE(tx6_touchpanels));
1490 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1491 karo_fdt_fixup_flexcan(blob, stk5_v5);
1493 karo_fdt_update_fb_mode(blob, video_mode);
1497 #endif /* CONFIG_OF_BOARD_SETUP */