2 * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <fdt_support.h>
30 #include <fsl_esdhc.h>
38 #include <asm/arch/iomux-mx6.h>
39 #include <asm/arch/clock.h>
40 #include <asm/arch/imx-regs.h>
41 #include <asm/arch/crm_regs.h>
42 #include <asm/arch/sys_proto.h>
44 #include "../common/karo.h"
46 #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
47 #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
48 #define TX6_FEC_INT_GPIO IMX_GPIO_NR(2, 4)
49 #define TX6_LED_GPIO IMX_GPIO_NR(2, 20)
51 #define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
52 #define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
53 #define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
55 #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
57 #define TEMPERATURE_MIN -40
58 #define TEMPERATURE_HOT 80
59 #define TEMPERATURE_MAX 125
61 DECLARE_GLOBAL_DATA_PTR;
63 #define MUX_CFG_SION IOMUX_PAD(0, 0, MUX_CONFIG_SION, 0, 0, 0)
65 static const iomux_v3_cfg_t tx6qdl_pads[] = {
67 MX6_PAD_NANDF_CLE__RAWNAND_CLE,
68 MX6_PAD_NANDF_ALE__RAWNAND_ALE,
69 MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
70 MX6_PAD_NANDF_RB0__RAWNAND_READY0,
71 MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
72 MX6_PAD_SD4_CMD__RAWNAND_RDN,
73 MX6_PAD_SD4_CLK__RAWNAND_WRN,
74 MX6_PAD_NANDF_D0__RAWNAND_D0,
75 MX6_PAD_NANDF_D1__RAWNAND_D1,
76 MX6_PAD_NANDF_D2__RAWNAND_D2,
77 MX6_PAD_NANDF_D3__RAWNAND_D3,
78 MX6_PAD_NANDF_D4__RAWNAND_D4,
79 MX6_PAD_NANDF_D5__RAWNAND_D5,
80 MX6_PAD_NANDF_D6__RAWNAND_D6,
81 MX6_PAD_NANDF_D7__RAWNAND_D7,
84 MX6_PAD_GPIO_17__GPIO_7_12,
87 #if CONFIG_MXC_UART_BASE == UART1_BASE
88 MX6_PAD_SD3_DAT7__UART1_TXD,
89 MX6_PAD_SD3_DAT6__UART1_RXD,
90 MX6_PAD_SD3_DAT1__UART1_RTS,
91 MX6_PAD_SD3_DAT0__UART1_CTS,
93 #if CONFIG_MXC_UART_BASE == UART2_BASE
94 MX6_PAD_SD4_DAT4__UART2_RXD,
95 MX6_PAD_SD4_DAT7__UART2_TXD,
96 MX6_PAD_SD4_DAT5__UART2_RTS,
97 MX6_PAD_SD4_DAT6__UART2_CTS,
99 #if CONFIG_MXC_UART_BASE == UART3_BASE
100 MX6_PAD_EIM_D24__UART3_TXD,
101 MX6_PAD_EIM_D25__UART3_RXD,
102 MX6_PAD_SD3_RST__UART3_RTS,
103 MX6_PAD_SD3_DAT3__UART3_CTS,
106 MX6_PAD_EIM_D28__I2C1_SDA,
107 MX6_PAD_EIM_D21__I2C1_SCL,
109 /* FEC PHY GPIO functions */
110 MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
111 MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
112 MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
115 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
117 MX6_PAD_ENET_MDC__ENET_MDC,
118 MX6_PAD_ENET_MDIO__ENET_MDIO,
119 MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
120 MX6_PAD_ENET_RX_ER__ENET_RX_ER,
121 MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
122 MX6_PAD_ENET_RXD1__ENET_RDATA_1,
123 MX6_PAD_ENET_RXD0__ENET_RDATA_0,
124 MX6_PAD_ENET_TX_EN__ENET_TX_EN,
125 MX6_PAD_ENET_TXD1__ENET_TDATA_1,
126 MX6_PAD_ENET_TXD0__ENET_TDATA_0,
129 static const struct gpio tx6qdl_gpios[] = {
130 { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
131 { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
132 { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
133 { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
139 /* placed in section '.data' to prevent overwriting relocation info
142 static u32 wrsr __attribute__((section(".data")));
144 #define WRSR_POR (1 << 4)
145 #define WRSR_TOUT (1 << 1)
146 #define WRSR_SFTW (1 << 0)
148 static void print_reset_cause(void)
150 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
151 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
155 printf("Reset cause: ");
157 srsr = readl(&src_regs->srsr);
158 wrsr = readw(wdt_base + 4);
160 if (wrsr & WRSR_POR) {
161 printf("%sPOR", dlm);
164 if (srsr & 0x00004) {
165 printf("%sCSU", dlm);
168 if (srsr & 0x00008) {
169 printf("%sIPP USER", dlm);
172 if (srsr & 0x00010) {
173 if (wrsr & WRSR_SFTW) {
174 printf("%sSOFT", dlm);
177 if (wrsr & WRSR_TOUT) {
178 printf("%sWDOG", dlm);
182 if (srsr & 0x00020) {
183 printf("%sJTAG HIGH-Z", dlm);
186 if (srsr & 0x00040) {
187 printf("%sJTAG SW", dlm);
190 if (srsr & 0x10000) {
191 printf("%sWARM BOOT", dlm);
200 int read_cpu_temperature(void);
201 int check_cpu_temperature(int boot);
203 static void print_cpuinfo(void)
205 u32 cpurev = get_cpu_rev();
208 switch ((cpurev >> 12) & 0xff) {
215 case MXC_CPU_MX6SOLO:
223 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
225 (cpurev & 0x000F0) >> 4,
226 (cpurev & 0x0000F) >> 0,
227 mxc_get_clock(MXC_ARM_CLK) / 1000000);
230 check_cpu_temperature(1);
233 #define LTC3676_DVB2A 0x0C
234 #define LTC3676_DVB2B 0x0D
235 #define LTC3676_DVB4A 0x10
236 #define LTC3676_DVB4B 0x11
238 #define VDD_SOC_mV (1375 + 50)
239 #define VDD_CORE_mV (1375 + 50)
241 #define mV_to_regval(mV) (((mV) * 360 / 330 - 825 + 1) / 25)
242 #define regval_to_mV(v) (((v) * 25 + 825) * 330 / 360)
244 static int setup_pmic_voltages(void)
249 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
251 ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
253 printf("Failed to initialize I2C\n");
257 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
259 printf("%s: i2c_read error: %d\n", __func__, ret);
263 /* VDDCORE/VDDSOC default 1.375V is not enough, considering
264 pfuze tolerance and IR drop and ripple, need increase
265 to 1.425V for SabreSD */
267 value = 0x39; /* VB default value & PGOOD not forced when slewing */
268 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1);
270 printf("%s: failed to write PMIC DVB2B register: %d\n",
274 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1);
276 printf("%s: failed to write PMIC DVB4B register: %d\n",
281 value = mV_to_regval(VDD_SOC_mV);
282 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1);
284 printf("%s: failed to write PMIC DVB2A register: %d\n",
288 printf("VDDSOC set to %dmV\n", regval_to_mV(value));
290 value = mV_to_regval(VDD_CORE_mV);
291 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1);
293 printf("%s: failed to write PMIC DVB4A register: %d\n",
297 printf("VDDCORE set to %dmV\n", regval_to_mV(value));
301 int board_early_init_f(void)
303 gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
304 imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
313 /* Address of boot parameters */
314 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
315 #ifdef CONFIG_OF_LIBFDT
316 gd->bd->bi_arch_number = -1;
318 gd->bd->bi_arch_number = 4429;
320 ret = setup_pmic_voltages();
322 printf("Failed to setup PMIC voltages\n");
330 /* dram_init must store complete ramsize in gd->ram_size */
331 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
336 void dram_init_banksize(void)
338 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
339 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
341 #if CONFIG_NR_DRAM_BANKS > 1
342 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
343 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
348 #ifdef CONFIG_CMD_MMC
349 static const iomux_v3_cfg_t mmc0_pads[] = {
350 MX6_PAD_SD1_CMD__USDHC1_CMD,
351 MX6_PAD_SD1_CLK__USDHC1_CLK,
352 MX6_PAD_SD1_DAT0__USDHC1_DAT0,
353 MX6_PAD_SD1_DAT1__USDHC1_DAT1,
354 MX6_PAD_SD1_DAT2__USDHC1_DAT2,
355 MX6_PAD_SD1_DAT3__USDHC1_DAT3,
357 MX6_PAD_SD3_CMD__GPIO_7_2,
360 static const iomux_v3_cfg_t mmc1_pads[] = {
361 MX6_PAD_SD2_CMD__USDHC2_CMD,
362 MX6_PAD_SD2_CLK__USDHC2_CLK,
363 MX6_PAD_SD2_DAT0__USDHC2_DAT0,
364 MX6_PAD_SD2_DAT1__USDHC2_DAT1,
365 MX6_PAD_SD2_DAT2__USDHC2_DAT2,
366 MX6_PAD_SD2_DAT3__USDHC2_DAT3,
368 MX6_PAD_SD3_CLK__GPIO_7_3,
371 static struct tx6q_esdhc_cfg {
372 const iomux_v3_cfg_t *pads;
374 enum mxc_clock clkid;
375 struct fsl_esdhc_cfg cfg;
376 } tx6qdl_esdhc_cfg[] = {
379 .num_pads = ARRAY_SIZE(mmc0_pads),
380 .clkid = MXC_ESDHC_CLK,
382 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
383 .cd_gpio = IMX_GPIO_NR(7, 2),
389 .num_pads = ARRAY_SIZE(mmc1_pads),
390 .clkid = MXC_ESDHC2_CLK,
392 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
393 .cd_gpio = IMX_GPIO_NR(7, 3),
399 static inline struct tx6q_esdhc_cfg *to_tx6q_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
403 return p - offsetof(struct tx6q_esdhc_cfg, cfg);
406 int board_mmc_getcd(struct mmc *mmc)
408 struct fsl_esdhc_cfg *cfg = mmc->priv;
410 if (cfg->cd_gpio < 0)
413 debug("SD card %d is %spresent\n",
414 to_tx6q_esdhc_cfg(cfg) - tx6qdl_esdhc_cfg,
415 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
416 return !gpio_get_value(cfg->cd_gpio);
419 int board_mmc_init(bd_t *bis)
423 for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
425 struct fsl_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i].cfg;
427 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
430 cfg->sdhc_clk = mxc_get_clock(tx6qdl_esdhc_cfg[i].clkid);
431 imx_iomux_v3_setup_multiple_pads(tx6qdl_esdhc_cfg[i].pads,
432 tx6qdl_esdhc_cfg[i].num_pads);
434 debug("%s: Initializing MMC slot %d\n", __func__, i);
435 fsl_esdhc_initialize(bis, cfg);
437 mmc = find_mmc_device(i);
440 if (board_mmc_getcd(mmc) > 0)
445 #endif /* CONFIG_CMD_MMC */
447 #ifdef CONFIG_FEC_MXC
449 #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
451 #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
452 #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
458 int board_eth_init(bd_t *bis)
462 /* delay at least 21ms for the PHY internal POR signal to deassert */
465 imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
467 /* Deassert RESET to the external phy */
468 gpio_set_value(TX6_FEC_RST_GPIO, 1);
470 ret = cpu_eth_init(bis);
472 printf("cpu_eth_init() failed: %d\n", ret);
476 #endif /* CONFIG_FEC_MXC */
484 static inline int calc_blink_rate(int tmp)
486 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
487 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
488 (TEMPERATURE_HOT - TEMPERATURE_MIN);
491 void show_activity(int arg)
493 static int led_state = LED_STATE_INIT;
494 static int blink_rate;
497 if (led_state == LED_STATE_INIT) {
499 gpio_set_value(TX6_LED_GPIO, 1);
500 led_state = LED_STATE_ON;
501 blink_rate = calc_blink_rate(check_cpu_temperature(0));
503 if (get_timer(last) > blink_rate) {
504 blink_rate = calc_blink_rate(check_cpu_temperature(0));
505 last = get_timer_masked();
506 if (led_state == LED_STATE_ON) {
507 gpio_set_value(TX6_LED_GPIO, 0);
509 gpio_set_value(TX6_LED_GPIO, 1);
511 led_state = 1 - led_state;
516 static const iomux_v3_cfg_t stk5_pads[] = {
517 /* SW controlled LED on STK5 baseboard */
518 MX6_PAD_EIM_A18__GPIO_2_20,
521 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
522 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
523 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
524 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
525 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
526 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
527 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
528 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
529 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
530 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
531 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
532 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
533 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
534 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
535 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
536 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
537 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
538 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
539 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
540 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
541 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
542 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
543 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
544 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
545 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
546 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
547 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
548 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
550 /* I2C bus on DIMM pins 40/41 */
551 MX6_PAD_GPIO_6__I2C3_SDA,
552 MX6_PAD_GPIO_3__I2C3_SCL,
554 /* TSC200x PEN IRQ */
555 MX6_PAD_EIM_D26__GPIO_3_26,
557 /* EDT-FT5x06 Polytouch panel */
558 MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
559 MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
560 MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
563 MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
564 MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
566 MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
567 MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
568 MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
571 static const struct gpio stk5_gpios[] = {
572 { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
574 { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
575 { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
576 { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
577 { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
578 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
582 vidinfo_t panel_info = {
583 /* set to max. size supported by SoC */
587 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
590 static struct fb_videomode tx6_fb_modes[] = {
592 /* Standard VGA timing */
597 .pixclock = KHZ2PICOS(25175),
604 .sync = FB_SYNC_CLK_LAT_FALL,
607 /* Emerging ETV570 640 x 480 display. Syncs low active,
608 * DE high active, 115.2 mm x 86.4 mm display area
609 * VGA compatible timing
615 .pixclock = KHZ2PICOS(25175),
622 .sync = FB_SYNC_CLK_LAT_FALL,
625 /* Emerging ET0350G0DH6 320 x 240 display.
626 * 70.08 mm x 52.56 mm display area.
632 .pixclock = KHZ2PICOS(6500),
633 .left_margin = 68 - 34,
636 .upper_margin = 18 - 3,
639 .sync = FB_SYNC_CLK_LAT_FALL,
642 /* Emerging ET0430G0DH6 480 x 272 display.
643 * 95.04 mm x 53.856 mm display area.
649 .pixclock = KHZ2PICOS(9000),
656 .sync = FB_SYNC_CLK_LAT_FALL,
659 /* Emerging ET0500G0DH6 800 x 480 display.
660 * 109.6 mm x 66.4 mm display area.
666 .pixclock = KHZ2PICOS(33260),
667 .left_margin = 216 - 128,
669 .right_margin = 1056 - 800 - 216,
670 .upper_margin = 35 - 2,
672 .lower_margin = 525 - 480 - 35,
673 .sync = FB_SYNC_CLK_LAT_FALL,
676 /* Emerging ETQ570G0DH6 320 x 240 display.
677 * 115.2 mm x 86.4 mm display area.
683 .pixclock = KHZ2PICOS(6400),
687 .upper_margin = 16, /* 15 according to datasheet */
688 .vsync_len = 3, /* TVP -> 1>x>5 */
689 .lower_margin = 4, /* 4.5 according to datasheet */
690 .sync = FB_SYNC_CLK_LAT_FALL,
693 /* Emerging ET0700G0DH6 800 x 480 display.
694 * 152.4 mm x 91.44 mm display area.
700 .pixclock = KHZ2PICOS(33260),
701 .left_margin = 216 - 128,
703 .right_margin = 1056 - 800 - 216,
704 .upper_margin = 35 - 2,
706 .lower_margin = 525 - 480 - 35,
707 .sync = FB_SYNC_CLK_LAT_FALL,
710 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
718 .sync = FB_SYNC_CLK_LAT_FALL,
722 static int lcd_enabled = 1;
724 void lcd_enable(void)
727 * global variable from common/lcd.c
728 * Set to 0 here to prevent messages from going to LCD
729 * rather than serial console
733 karo_load_splashimage(1);
735 debug("Switching LCD on\n");
736 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
738 gpio_set_value(TX6_LCD_RST_GPIO, 1);
740 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0);
744 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
746 MX6_PAD_EIM_D29__GPIO_3_29,
747 /* LCD POWER_ENABLE */
748 MX6_PAD_EIM_EB3__GPIO_2_31,
749 /* LCD Backlight (PWM) */
750 MX6_PAD_GPIO_1__GPIO_1_1,
753 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
754 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
755 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
756 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
757 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
758 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
759 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
760 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
761 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
762 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
763 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
764 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
765 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
766 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
767 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
768 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
769 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
770 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
771 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
772 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
773 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
774 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
775 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
776 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
777 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
778 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
779 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
780 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
783 static const struct gpio stk5_lcd_gpios[] = {
784 { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
785 { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
786 { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
789 void lcd_ctrl_init(void *lcdbase)
791 int color_depth = 24;
795 struct fb_videomode *p = &tx6_fb_modes[0];
796 struct fb_videomode fb_mode;
797 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
799 ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
800 unsigned long di_clk_rate = 65000000;
803 debug("LCD disabled\n");
807 if (tstc() || (wrsr & WRSR_TOUT)) {
808 debug("Disabling LCD\n");
815 vm = getenv("video_mode");
817 debug("Disabling LCD\n");
821 if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
823 debug("Using video mode from FDT\n");
825 if (fb_mode.xres < panel_info.vl_col)
826 panel_info.vl_col = fb_mode.xres;
827 if (fb_mode.yres < panel_info.vl_row)
828 panel_info.vl_row = fb_mode.yres;
831 debug("Trying compiled-in video modes\n");
832 while (p->name != NULL) {
833 if (strcmp(p->name, vm) == 0) {
834 debug("Using video mode: '%s'\n", p->name);
841 debug("Trying to decode video_mode: '%s'\n", vm);
842 while (*vm != '\0') {
843 if (*vm >= '0' && *vm <= '9') {
846 val = simple_strtoul(vm, &end, 0);
849 if (val > panel_info.vl_col)
850 val = panel_info.vl_col;
852 panel_info.vl_col = val;
854 } else if (!yres_set) {
855 if (val > panel_info.vl_row)
856 val = panel_info.vl_row;
858 panel_info.vl_row = val;
860 } else if (!bpp_set) {
863 if (pix_fmt == IPU_PIX_FMT_LVDS666)
864 pix_fmt = IPU_PIX_FMT_LVDS888;
872 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
878 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
879 end - vm, vm, color_depth);
882 } else if (!refresh_set) {
908 if (strncmp(vm, "LVDS", 4) == 0) {
909 pix_fmt = IPU_PIX_FMT_LVDS666;
910 di_clk_parent = DI_PCLK_LDB;
912 pix_fmt = IPU_PIX_FMT_RGB24;
914 tmp = strchr(vm, ':');
922 if (p->xres == 0 || p->yres == 0) {
923 printf("Invalid video mode: %s\n", getenv("video_mode"));
925 printf("Supported video modes are:");
926 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
927 printf(" %s", p->name);
933 p->pixclock = KHZ2PICOS(refresh *
934 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
935 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
937 debug("Pixel clock set to %lu.%03lu MHz\n",
938 PICOS2KHZ(p->pixclock) / 1000,
939 PICOS2KHZ(p->pixclock) % 1000);
941 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
942 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
943 ARRAY_SIZE(stk5_lcd_pads));
945 debug("Initializing FB driver\n");
947 pix_fmt = IPU_PIX_FMT_RGB24;
948 else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
949 writel(0x01, IOMUXC_BASE_ADDR + 8);
950 } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
951 writel(0x21, IOMUXC_BASE_ADDR + 8);
953 if (pix_fmt != IPU_PIX_FMT_RGB24) {
954 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
955 /* enable LDB & DI0 clock */
956 writel(readl(&ccm_regs->CCGR3) | (3 << 12) | (3 << 2),
960 if (karo_load_splashimage(0) == 0) {
961 debug("Initializing LCD controller\n");
962 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
964 debug("Skipping initialization of LCD controller\n");
968 #define lcd_enabled 0
969 #endif /* CONFIG_LCD */
971 static void stk5_board_init(void)
973 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
974 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
977 static void stk5v3_board_init(void)
982 static void stk5v5_board_init(void)
986 gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
987 "Flexcan Transceiver");
988 imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
991 static void tx6qdl_set_cpu_clock(void)
993 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
995 if (tstc() || (wrsr & WRSR_TOUT))
998 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1001 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1002 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1003 printf("CPU clock set to %lu.%03lu MHz\n",
1004 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1006 printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
1010 static void tx6_init_mac(void)
1013 char mac_str[ETH_ALEN * 3] = "";
1015 imx_get_mac_from_fuse(-1, mac);
1016 if (!is_valid_ether_addr(mac)) {
1017 printf("No valid MAC address programmed\n");
1021 snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
1022 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
1023 setenv("ethaddr", mac_str);
1024 printf("MAC addr from fuse: %02x:%02x:%02x:%02x:%02x:%02x\n",
1025 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
1028 int board_late_init(void)
1031 const char *baseboard;
1033 tx6qdl_set_cpu_clock();
1034 karo_fdt_move_fdt();
1036 baseboard = getenv("baseboard");
1040 printf("Baseboard: %s\n", baseboard);
1042 if (strncmp(baseboard, "stk5", 4) == 0) {
1043 if ((strlen(baseboard) == 4) ||
1044 strcmp(baseboard, "stk5-v3") == 0) {
1045 stk5v3_board_init();
1046 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1047 stk5v5_board_init();
1049 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1053 printf("WARNING: Unsupported baseboard: '%s'\n",
1061 gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1065 int checkboard(void)
1067 u32 cpurev = get_cpu_rev();
1068 int cpu_variant = (cpurev >> 12) & 0xff;
1072 printf("Board: Ka-Ro TX6%c-%dxx%d\n",
1073 cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
1074 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1075 1 - PHYS_SDRAM_1_WIDTH / 64);
1080 #ifdef CONFIG_SERIAL_TAG
1081 void get_board_serial(struct tag_serialnr *serialnr)
1083 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
1084 struct fuse_bank0_regs *fuse = (void *)iim->bank[0].fuse_regs;
1086 serialnr->low = readl(&fuse->cfg0);
1087 serialnr->high = readl(&fuse->cfg1);
1091 #if defined(CONFIG_OF_BOARD_SETUP)
1092 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1093 #include <jffs2/jffs2.h>
1094 #include <mtd_node.h>
1095 struct node_info nodes[] = {
1096 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1100 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1103 static void tx6qdl_fixup_flexcan(void *blob)
1105 const char *baseboard = getenv("baseboard");
1107 if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
1110 karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02090000, "transceiver-switch");
1111 karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02094000, "transceiver-switch");
1114 void ft_board_setup(void *blob, bd_t *bd)
1116 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1117 fdt_fixup_ethernet(blob);
1119 karo_fdt_fixup_touchpanel(blob);
1120 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
1121 tx6qdl_fixup_flexcan(blob);
1122 karo_fdt_update_fb_mode(blob, getenv("video_mode"));