drivers/ddr/fsl/main.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  11  * Based on code from spd_sdram.c
  12  * Author: James Yang [at freescale.com]
  13  */
  14
  15 #include <common.h>
  16 #include <i2c.h>
  17 #include <fsl_ddr_sdram.h>
  18 #include <fsl_ddr.h>
  19
  20 #ifdef CONFIG_PPC
  21 #include <asm/fsl_law.h>
  22
  23 void fsl_ddr_set_lawbar(
  24                 const common_timing_params_t *memctl_common_params,
  25                 unsigned int memctl_interleaved,
  26                 unsigned int ctrl_num);
  27 #endif
  28
  29 void fsl_ddr_set_intl3r(const unsigned int granule_size);
  30 #if defined(SPD_EEPROM_ADDRESS) || \
  31     defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
  32     defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
  33 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  34 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  35         [0][0] = SPD_EEPROM_ADDRESS,
  36 };
  37 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  38 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  39         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  40         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  41 };
  42 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  43 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  44         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  45         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  46 };
  47 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  48 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  49         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  50         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  51         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  52         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  53 };
  54 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  55 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  56         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  57         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  58         [2][0] = SPD_EEPROM_ADDRESS3,   /* controller 3 */
  59 };
  60 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  61 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  62         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  63         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  64         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  65         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  66         [2][0] = SPD_EEPROM_ADDRESS5,   /* controller 3 */
  67         [2][1] = SPD_EEPROM_ADDRESS6,   /* controller 3 */
  68 };
  69
  70 #endif
  71
  72 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  73 {
  74         int ret;
  75
  76         i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
  77
  78         ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
  79                                 sizeof(generic_spd_eeprom_t));
  80
  81         if (ret) {
  82                 if (i2c_address ==
  83 #ifdef SPD_EEPROM_ADDRESS
  84                                 SPD_EEPROM_ADDRESS
  85 #elif defined(SPD_EEPROM_ADDRESS1)
  86                                 SPD_EEPROM_ADDRESS1
  87 #endif
  88                                 ) {
  89                         printf("DDR: failed to read SPD from address %u\n",
  90                                 i2c_address);
  91                 } else {
  92                         debug("DDR: failed to read SPD from address %u\n",
  93                                 i2c_address);
  94                 }
  95                 memset(spd, 0, sizeof(generic_spd_eeprom_t));
  96         }
  97 }
  98
  99 __attribute__((weak, alias("__get_spd")))
 100 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
 101
 102 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 103                       unsigned int ctrl_num)
 104 {
 105         unsigned int i;
 106         unsigned int i2c_address = 0;
 107
 108         if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
 109                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
 110                 return;
 111         }
 112
 113         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
 114                 i2c_address = spd_i2c_addr[ctrl_num][i];
 115                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
 116         }
 117 }
 118 #else
 119 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 120                       unsigned int ctrl_num)
 121 {
 122 }
 123 #endif /* SPD_EEPROM_ADDRESSx */
 124
 125 /*
 126  * ASSUMPTIONS:
 127  *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
 128  *    - Same memory data bus width on all controllers
 129  *
 130  * NOTES:
 131  *
 132  * The memory controller and associated documentation use confusing
 133  * terminology when referring to the orgranization of DRAM.
 134  *
 135  * Here is a terminology translation table:
 136  *
 137  * memory controller/documention  |industry   |this code  |signals
 138  * -------------------------------|-----------|-----------|-----------------
 139  * physical bank/bank             |rank       |rank       |chip select (CS)
 140  * logical bank/sub-bank          |bank       |bank       |bank address (BA)
 141  * page/row                       |row        |page       |row address
 142  * ???                            |column     |column     |column address
 143  *
 144  * The naming confusion is further exacerbated by the descriptions of the
 145  * memory controller interleaving feature, where accesses are interleaved
 146  * _BETWEEN_ two seperate memory controllers.  This is configured only in
 147  * CS0_CONFIG[INTLV_CTL] of each memory controller.
 148  *
 149  * memory controller documentation | number of chip selects
 150  *                                 | per memory controller supported
 151  * --------------------------------|-----------------------------------------
 152  * cache line interleaving         | 1 (CS0 only)
 153  * page interleaving               | 1 (CS0 only)
 154  * bank interleaving               | 1 (CS0 only)
 155  * superbank interleraving         | depends on bank (chip select)
 156  *                                 |   interleraving [rank interleaving]
 157  *                                 |   mode used on every memory controller
 158  *
 159  * Even further confusing is the existence of the interleaving feature
 160  * _WITHIN_ each memory controller.  The feature is referred to in
 161  * documentation as chip select interleaving or bank interleaving,
 162  * although it is configured in the DDR_SDRAM_CFG field.
 163  *
 164  * Name of field                | documentation name    | this code
 165  * -----------------------------|-----------------------|------------------
 166  * DDR_SDRAM_CFG[BA_INTLV_CTL]  | Bank (chip select)    | rank interleaving
 167  *                              |  interleaving
 168  */
 169
 170 const char *step_string_tbl[] = {
 171         "STEP_GET_SPD",
 172         "STEP_COMPUTE_DIMM_PARMS",
 173         "STEP_COMPUTE_COMMON_PARMS",
 174         "STEP_GATHER_OPTS",
 175         "STEP_ASSIGN_ADDRESSES",
 176         "STEP_COMPUTE_REGS",
 177         "STEP_PROGRAM_REGS",
 178         "STEP_ALL"
 179 };
 180
 181 const char * step_to_string(unsigned int step) {
 182
 183         unsigned int s = __ilog2(step);
 184
 185         if ((1 << s) != step)
 186                 return step_string_tbl[7];
 187
 188         return step_string_tbl[s];
 189 }
 190
 191 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 192                           unsigned int dbw_cap_adj[])
 193 {
 194         int i, j;
 195         unsigned long long total_mem, current_mem_base, total_ctlr_mem;
 196         unsigned long long rank_density, ctlr_density = 0;
 197
 198         /*
 199          * If a reduced data width is requested, but the SPD
 200          * specifies a physically wider device, adjust the
 201          * computed dimm capacities accordingly before
 202          * assigning addresses.
 203          */
 204         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 205                 unsigned int found = 0;
 206
 207                 switch (pinfo->memctl_opts[i].data_bus_width) {
 208                 case 2:
 209                         /* 16-bit */
 210                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 211                                 unsigned int dw;
 212                                 if (!pinfo->dimm_params[i][j].n_ranks)
 213                                         continue;
 214                                 dw = pinfo->dimm_params[i][j].primary_sdram_width;
 215                                 if ((dw == 72 || dw == 64)) {
 216                                         dbw_cap_adj[i] = 2;
 217                                         break;
 218                                 } else if ((dw == 40 || dw == 32)) {
 219                                         dbw_cap_adj[i] = 1;
 220                                         break;
 221                                 }
 222                         }
 223                         break;
 224
 225                 case 1:
 226                         /* 32-bit */
 227                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 228                                 unsigned int dw;
 229                                 dw = pinfo->dimm_params[i][j].data_width;
 230                                 if (pinfo->dimm_params[i][j].n_ranks
 231                                     && (dw == 72 || dw == 64)) {
 232                                         /*
 233                                          * FIXME: can't really do it
 234                                          * like this because this just
 235                                          * further reduces the memory
 236                                          */
 237                                         found = 1;
 238                                         break;
 239                                 }
 240                         }
 241                         if (found) {
 242                                 dbw_cap_adj[i] = 1;
 243                         }
 244                         break;
 245
 246                 case 0:
 247                         /* 64-bit */
 248                         break;
 249
 250                 default:
 251                         printf("unexpected data bus width "
 252                                 "specified controller %u\n", i);
 253                         return 1;
 254                 }
 255                 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
 256         }
 257
 258         current_mem_base = CONFIG_SYS_DDR_SDRAM_BASE;
 259         total_mem = 0;
 260         if (pinfo->memctl_opts[0].memctl_interleaving) {
 261                 rank_density = pinfo->dimm_params[0][0].rank_density >>
 262                                         dbw_cap_adj[0];
 263                 switch (pinfo->memctl_opts[0].ba_intlv_ctl &
 264                                         FSL_DDR_CS0_CS1_CS2_CS3) {
 265                 case FSL_DDR_CS0_CS1_CS2_CS3:
 266                         ctlr_density = 4 * rank_density;
 267                         break;
 268                 case FSL_DDR_CS0_CS1:
 269                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 270                         ctlr_density = 2 * rank_density;
 271                         break;
 272                 case FSL_DDR_CS2_CS3:
 273                 default:
 274                         ctlr_density = rank_density;
 275                         break;
 276                 }
 277                 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
 278                         rank_density, ctlr_density);
 279                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 280                         if (pinfo->memctl_opts[i].memctl_interleaving) {
 281                                 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
 282                                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 283                                 case FSL_DDR_PAGE_INTERLEAVING:
 284                                 case FSL_DDR_BANK_INTERLEAVING:
 285                                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 286                                         total_ctlr_mem = 2 * ctlr_density;
 287                                         break;
 288                                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 289                                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 290                                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 291                                         total_ctlr_mem = 3 * ctlr_density;
 292                                         break;
 293                                 case FSL_DDR_4WAY_1KB_INTERLEAVING:
 294                                 case FSL_DDR_4WAY_4KB_INTERLEAVING:
 295                                 case FSL_DDR_4WAY_8KB_INTERLEAVING:
 296                                         total_ctlr_mem = 4 * ctlr_density;
 297                                         break;
 298                                 default:
 299                                         panic("Unknown interleaving mode");
 300                                 }
 301                                 pinfo->common_timing_params[i].base_address =
 302                                                         current_mem_base;
 303                                 pinfo->common_timing_params[i].total_mem =
 304                                                         total_ctlr_mem;
 305                                 total_mem = current_mem_base + total_ctlr_mem;
 306                                 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
 307                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 308                         } else {
 309                                 /* when 3rd controller not interleaved */
 310                                 current_mem_base = total_mem;
 311                                 total_ctlr_mem = 0;
 312                                 pinfo->common_timing_params[i].base_address =
 313                                                         current_mem_base;
 314                                 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 315                                         unsigned long long cap =
 316                                                 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 317                                         pinfo->dimm_params[i][j].base_address =
 318                                                 current_mem_base;
 319                                         debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 320                                         current_mem_base += cap;
 321                                         total_ctlr_mem += cap;
 322                                 }
 323                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 324                                 pinfo->common_timing_params[i].total_mem =
 325                                                         total_ctlr_mem;
 326                                 total_mem += total_ctlr_mem;
 327                         }
 328                 }
 329         } else {
 330                 /*
 331                  * Simple linear assignment if memory
 332                  * controllers are not interleaved.
 333                  */
 334                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 335                         total_ctlr_mem = 0;
 336                         pinfo->common_timing_params[i].base_address =
 337                                                 current_mem_base;
 338                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 339                                 /* Compute DIMM base addresses. */
 340                                 unsigned long long cap =
 341                                         pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 342                                 pinfo->dimm_params[i][j].base_address =
 343                                         current_mem_base;
 344                                 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 345                                 current_mem_base += cap;
 346                                 total_ctlr_mem += cap;
 347                         }
 348                         debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 349                         pinfo->common_timing_params[i].total_mem =
 350                                                         total_ctlr_mem;
 351                         total_mem += total_ctlr_mem;
 352                 }
 353         }
 354         debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
 355
 356         return total_mem;
 357 }
 358
 359 /* Use weak function to allow board file to override the address assignment */
 360 __attribute__((weak, alias("__step_assign_addresses")))
 361 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 362                           unsigned int dbw_cap_adj[]);
 363
 364 unsigned long long
 365 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 366                                        unsigned int size_only)
 367 {
 368         unsigned int i, j;
 369         unsigned long long total_mem = 0;
 370         int assert_reset;
 371
 372         fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 373         common_timing_params_t *timing_params = pinfo->common_timing_params;
 374         assert_reset = board_need_mem_reset();
 375
 376         /* data bus width capacity adjust shift amount */
 377         unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
 378
 379         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 380                 dbw_capacity_adjust[i] = 0;
 381         }
 382
 383         debug("starting at step %u (%s)\n",
 384               start_step, step_to_string(start_step));
 385
 386         switch (start_step) {
 387         case STEP_GET_SPD:
 388 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 389                 /* STEP 1:  Gather all DIMM SPD data */
 390                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 391                         fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
 392                 }
 393
 394         case STEP_COMPUTE_DIMM_PARMS:
 395                 /* STEP 2:  Compute DIMM parameters from SPD data */
 396
 397                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 398                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 399                                 unsigned int retval;
 400                                 generic_spd_eeprom_t *spd =
 401                                         &(pinfo->spd_installed_dimms[i][j]);
 402                                 dimm_params_t *pdimm =
 403                                         &(pinfo->dimm_params[i][j]);
 404
 405                                 retval = compute_dimm_parameters(spd, pdimm, i);
 406 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 407                                 if (!i && !j && retval) {
 408                                         printf("SPD error on controller %d! "
 409                                         "Trying fallback to raw timing "
 410                                         "calculation\n", i);
 411                                         fsl_ddr_get_dimm_params(pdimm, i, j);
 412                                 }
 413 #else
 414                                 if (retval == 2) {
 415                                         printf("Error: compute_dimm_parameters"
 416                                         " non-zero returned FATAL value "
 417                                         "for memctl=%u dimm=%u\n", i, j);
 418                                         return 0;
 419                                 }
 420 #endif
 421                                 if (retval) {
 422                                         debug("Warning: compute_dimm_parameters"
 423                                         " non-zero return value for memctl=%u "
 424                                         "dimm=%u\n", i, j);
 425                                 }
 426                         }
 427                 }
 428
 429 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
 430         case STEP_COMPUTE_DIMM_PARMS:
 431                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 432                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 433                                 dimm_params_t *pdimm =
 434                                         &(pinfo->dimm_params[i][j]);
 435                                 fsl_ddr_get_dimm_params(pdimm, i, j);
 436                         }
 437                 }
 438                 debug("Filling dimm parameters from board specific file\n");
 439 #endif
 440         case STEP_COMPUTE_COMMON_PARMS:
 441                 /*
 442                  * STEP 3: Compute a common set of timing parameters
 443                  * suitable for all of the DIMMs on each memory controller
 444                  */
 445                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 446                         debug("Computing lowest common DIMM"
 447                                 " parameters for memctl=%u\n", i);
 448                         compute_lowest_common_dimm_parameters(
 449                                 pinfo->dimm_params[i],
 450                                 &timing_params[i],
 451                                 CONFIG_DIMM_SLOTS_PER_CTLR);
 452                 }
 453
 454         case STEP_GATHER_OPTS:
 455                 /* STEP 4:  Gather configuration requirements from user */
 456                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 457                         debug("Reloading memory controller "
 458                                 "configuration options for memctl=%u\n", i);
 459                         /*
 460                          * This "reloads" the memory controller options
 461                          * to defaults.  If the user "edits" an option,
 462                          * next_step points to the step after this,
 463                          * which is currently STEP_ASSIGN_ADDRESSES.
 464                          */
 465                         populate_memctl_options(
 466                                         timing_params[i].all_dimms_registered,
 467                                         &pinfo->memctl_opts[i],
 468                                         pinfo->dimm_params[i], i);
 469                         /*
 470                          * For RDIMMs, JEDEC spec requires clocks to be stable
 471                          * before reset signal is deasserted. For the boards
 472                          * using fixed parameters, this function should be
 473                          * be called from board init file.
 474                          */
 475                         if (timing_params[i].all_dimms_registered)
 476                                 assert_reset = 1;
 477                 }
 478                 if (assert_reset) {
 479                         debug("Asserting mem reset\n");
 480                         board_assert_mem_reset();
 481                 }
 482
 483         case STEP_ASSIGN_ADDRESSES:
 484                 /* STEP 5:  Assign addresses to chip selects */
 485                 check_interleaving_options(pinfo);
 486                 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
 487
 488         case STEP_COMPUTE_REGS:
 489                 /* STEP 6:  compute controller register values */
 490                 debug("FSL Memory ctrl register computation\n");
 491                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 492                         if (timing_params[i].ndimms_present == 0) {
 493                                 memset(&ddr_reg[i], 0,
 494                                         sizeof(fsl_ddr_cfg_regs_t));
 495                                 continue;
 496                         }
 497
 498                         compute_fsl_memctl_config_regs(
 499                                         &pinfo->memctl_opts[i],
 500                                         &ddr_reg[i], &timing_params[i],
 501                                         pinfo->dimm_params[i],
 502                                         dbw_capacity_adjust[i],
 503                                         size_only);
 504                 }
 505
 506         default:
 507                 break;
 508         }
 509
 510         {
 511                 /*
 512                  * Compute the amount of memory available just by
 513                  * looking for the highest valid CSn_BNDS value.
 514                  * This allows us to also experiment with using
 515                  * only CS0 when using dual-rank DIMMs.
 516                  */
 517                 unsigned int max_end = 0;
 518
 519                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 520                         for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
 521                                 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
 522                                 if (reg->cs[j].config & 0x80000000) {
 523                                         unsigned int end;
 524                                         /*
 525                                          * 0xfffffff is a special value we put
 526                                          * for unused bnds
 527                                          */
 528                                         if (reg->cs[j].bnds == 0xffffffff)
 529                                                 continue;
 530                                         end = reg->cs[j].bnds & 0xffff;
 531                                         if (end > max_end) {
 532                                                 max_end = end;
 533                                         }
 534                                 }
 535                         }
 536                 }
 537
 538                 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
 539                             0xFFFFFFULL) - CONFIG_SYS_DDR_SDRAM_BASE;
 540         }
 541
 542         return total_mem;
 543 }
 544
 545 /*
 546  * fsl_ddr_sdram() -- this is the main function to be called by
 547  *      initdram() in the board file.
 548  *
 549  * It returns amount of memory configured in bytes.
 550  */
 551 phys_size_t fsl_ddr_sdram(void)
 552 {
 553         unsigned int i;
 554 #ifdef CONFIG_PPC
 555         unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
 556 #endif
 557         unsigned long long total_memory;
 558         fsl_ddr_info_t info;
 559         int deassert_reset;
 560
 561         /* Reset info structure. */
 562         memset(&info, 0, sizeof(fsl_ddr_info_t));
 563
 564         /* Compute it once normally. */
 565 #ifdef CONFIG_FSL_DDR_INTERACTIVE
 566         if (tstc() && (getc() == 'd')) {        /* we got a key press of 'd' */
 567                 total_memory = fsl_ddr_interactive(&info, 0);
 568         } else if (fsl_ddr_interactive_env_var_exists()) {
 569                 total_memory = fsl_ddr_interactive(&info, 1);
 570         } else
 571 #endif
 572                 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
 573
 574         /* setup 3-way interleaving before enabling DDRC */
 575         if (info.memctl_opts[0].memctl_interleaving) {
 576                 switch (info.memctl_opts[0].memctl_interleaving_mode) {
 577                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 578                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 579                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 580                         fsl_ddr_set_intl3r(
 581                                 info.memctl_opts[0].memctl_interleaving_mode);
 582                         break;
 583                 default:
 584                         break;
 585                 }
 586         }
 587
 588         /*
 589          * Program configuration registers.
 590          * JEDEC specs requires clocks to be stable before deasserting reset
 591          * for RDIMMs. Clocks start after chip select is enabled and clock
 592          * control register is set. During step 1, all controllers have their
 593          * registers set but not enabled. Step 2 proceeds after deasserting
 594          * reset through board FPGA or GPIO.
 595          * For non-registered DIMMs, initialization can go through but it is
 596          * also OK to follow the same flow.
 597          */
 598         deassert_reset = board_need_mem_reset();
 599         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 600                 if (info.common_timing_params[i].all_dimms_registered)
 601                         deassert_reset = 1;
 602         }
 603         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 604                 debug("Programming controller %u\n", i);
 605                 if (info.common_timing_params[i].ndimms_present == 0) {
 606                         debug("No dimms present on controller %u; "
 607                                         "skipping programming\n", i);
 608                         continue;
 609                 }
 610                 /*
 611                  * The following call with step = 1 returns before enabling
 612                  * the controller. It has to finish with step = 2 later.
 613                  */
 614                 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i,
 615                                         deassert_reset ? 1 : 0);
 616         }
 617         if (deassert_reset) {
 618                 /* Use board FPGA or GPIO to deassert reset signal */
 619                 debug("Deasserting mem reset\n");
 620                 board_deassert_mem_reset();
 621                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 622                         /* Call with step = 2 to continue initialization */
 623                         fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]),
 624                                                 i, 2);
 625                 }
 626         }
 627
 628 #ifdef CONFIG_PPC
 629         /* program LAWs */
 630         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 631                 if (info.memctl_opts[i].memctl_interleaving) {
 632                         switch (info.memctl_opts[i].memctl_interleaving_mode) {
 633                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 634                         case FSL_DDR_PAGE_INTERLEAVING:
 635                         case FSL_DDR_BANK_INTERLEAVING:
 636                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 637                                 if (i == 0) {
 638                                         law_memctl = LAW_TRGT_IF_DDR_INTRLV;
 639                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 640                                                 law_memctl, i);
 641                                 } else if (i == 2) {
 642                                         law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
 643                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 644                                                 law_memctl, i);
 645                                 }
 646                                 break;
 647                         case FSL_DDR_3WAY_1KB_INTERLEAVING:
 648                         case FSL_DDR_3WAY_4KB_INTERLEAVING:
 649                         case FSL_DDR_3WAY_8KB_INTERLEAVING:
 650                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
 651                                 if (i == 0) {
 652                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 653                                                 law_memctl, i);
 654                                 }
 655                                 break;
 656                         case FSL_DDR_4WAY_1KB_INTERLEAVING:
 657                         case FSL_DDR_4WAY_4KB_INTERLEAVING:
 658                         case FSL_DDR_4WAY_8KB_INTERLEAVING:
 659                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
 660                                 if (i == 0)
 661                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 662                                                 law_memctl, i);
 663                                 /* place holder for future 4-way interleaving */
 664                                 break;
 665                         default:
 666                                 break;
 667                         }
 668                 } else {
 669                         switch (i) {
 670                         case 0:
 671                                 law_memctl = LAW_TRGT_IF_DDR_1;
 672                                 break;
 673                         case 1:
 674                                 law_memctl = LAW_TRGT_IF_DDR_2;
 675                                 break;
 676                         case 2:
 677                                 law_memctl = LAW_TRGT_IF_DDR_3;
 678                                 break;
 679                         case 3:
 680                                 law_memctl = LAW_TRGT_IF_DDR_4;
 681                                 break;
 682                         default:
 683                                 break;
 684                         }
 685                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 686                                         law_memctl, i);
 687                 }
 688         }
 689 #endif
 690
 691         debug("total_memory by %s = %llu\n", __func__, total_memory);
 692
 693 #if !defined(CONFIG_PHYS_64BIT)
 694         /* Check for 4G or more.  Bad. */
 695         if (total_memory >= (1ull << 32)) {
 696                 puts("Detected ");
 697                 print_size(total_memory, " of memory\n");
 698                 printf("       This U-Boot only supports < 4G of DDR\n");
 699                 printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
 700                 printf("       "); /* re-align to match init_func_ram print */
 701                 total_memory = CONFIG_MAX_MEM_MAPPED;
 702         }
 703 #endif
 704
 705         return total_memory;
 706 }
 707
 708 /*
 709  * fsl_ddr_sdram_size() - This function only returns the size of the total
 710  * memory without setting ddr control registers.
 711  */
 712 phys_size_t
 713 fsl_ddr_sdram_size(void)
 714 {
 715         fsl_ddr_info_t  info;
 716         unsigned long long total_memory = 0;
 717
 718         memset(&info, 0 , sizeof(fsl_ddr_info_t));
 719
 720         /* Compute it once normally. */
 721         total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
 722
 723         return total_memory;
 724 }