Add support for Freescale M5271: Merge with /work/u-boot.mcf5271

diff --git a/CHANGELOG b/CHANGELOG
index 6379cc458553aed21d6c5244e9d1f29481c6c2f7..7483fa605c460c93d9a0c761519ba9ff79915ae6 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,473 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Added support for BC3450 board
+  Patch by Stefan Strobl, 21. Oct 2005
+
+* Update for NC650 board:
+  - Support rev1 and rev2 hardware
+  - adapt to new NAND layer
+  - add CP850 configuration based on NC650
+
+* MPC5200: enable snooping of DMA transactions on XLB even if no PCI
+  is configured; othrwise DMA accesses aren't cache coherent which
+  causes for example USB to fail.
+
+* Some code cleanup
+
+* Fix dbau1x00 boards broken by dbau1550 patch
+  PLL:s were not set for boards other than 1550.
+  Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST.
+  Default boot is now bootp for cards other than 1550.
+  Patch by Thomas Lange, 10 Aug 2005
+
+* Fixes common/cmd_flash.c:
+  - fix some compiler/parser error, if using m68k tool chain
+  - optical fix for protect on/off all messages, if using more
+    then one bank
+  Patch by Jens Scharsig, 28 Jul 2005
+
+* Fix Quad UART mapping on MCC200 board due to new HW revision
+
+* Fix JFFS2 support for legacy NAND driver.
+
+* Remove dependencies between DoC code and old legacy NAND driver.
+
+* Fix PM828_PCI target, for which PCI was *not* configured in.
+
+* Fix Lite5200B support: initialize SDelay register
+  See Freescale's AN3221 "MPC5200B SDRAM Initialization and
+  Configuration", 3.3.1 SDelay--MBAR + 0x0190
+
+* Changes/fixes for drivers/cfi_flash.c:
+
+  - Add Intel legacy lock/unlock support to common CFI driver
+
+    On some Intel flash's (e.g. Intel J3) legacy unlocking is
+    supported, meaning that unlocking of one sector will unlock
+    all sectors of this bank. Using this feature, unlocking
+    of all sectors upon startup (via env var "unlock=yes") will
+    get much faster.
+
+  - Fixed problem with multiple reads of envronment variable
+    "unlock" as pointed out by Reinhard Arlt & Anders Larsen.
+
+  - Removed unwanted linefeeds from "protect" command when
+    CFG_FLASH_PROTECTION is enabled.
+
+  - Changed p3p400 board to use CFG_FLASH_PROTECTION
+
+  Patch by Stefan Roese, 01 Apr 2006
+
+* Changes/fixes for drivers/cfi_flash.c:
+  - Correctly handle the cases where CFG_HZ != 1000 (several
+    XScale-based boards)
+  - Fix the timeout calculation of buffered writes (off by a
+    factor of 1000)
+  Patch by Anders Larsen, 31 Mar 2006
+
+* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
+
+  405 SDRAM: - The SDRAM parameters can now be defined in the board
+              config file and the 405 SDRAM controller values will
+              be calculated upon bootup (see PPChameleonEVB).
+              When those settings are not defined in the board
+              config file, the register setup will be as it is now,
+              so this implementation should not break any current
+              design using this code.
+
+              Thanks to Andrea Marson from DAVE for this patch.
+
+  440 DDR:   - Added function sdram_tr1_set to auto calculate the
+              TR1 value for the DDR.
+            - Added ECC support (see p3p440).
+
+  Patch by Stefan Roese, 17 Mar 2006
+
+* Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S
+  Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473]
+
+* Add support for ymodem protocol download
+  Patch by Stefano Babic, 29 Mar 2006
+
+* Memory Map Update for Delta board: U-Boot is at 0x80000000-0x84000000
+  Merge from Markus Klotzbücher's repo, 01 Apr 2006
+
+* GCC-4.x fixes: clean up global data pointer initialization for all
+  boards
+
+* Update for Delta board:
+  - redundant NAND environment
+  - misc Monahans cleanups (remove dead code etc.)
+  - DA9030 Initialization; some minimal changes to PXA I2C driver to
+    make it work with the Monahans.
+  - Make Monahans clock frequency configurable using
+    CFG_MONAHANS_RUN_MODE_OSC_RATIO and
+    CFG_MONAHANS_TURBO_RUN_MODE_RATIO.
+  Merge from Markus Klotzbücher's repo, 25 Mar 2006
+
+* Enable Quad UART om MCC200 board.
+
+* Cleanup MCC200 board configuration; omit non-existent stuff.
+
+* Add support for MPC859/866 Rev. A.0
+
+* Add command for handling DDR ECC registers on MPC8349EE MDS board.
+
+* Fix DDR ECC bit definitions for MPC83xx.
+
+* Add initial support for MPC8349E MDS board.
+
+* Add support for ECC DDR initialization on MPC83xx.
+
+* Add DMA support for MPC83xx.
+
+* Add sync in do_reset() routine for MPC83xx after RPR register
+  was written to. It is need on some targets when BAT translation
+  is enabled.
+
+* Add bit definitions for MPC83xx DDR controller registers.
+
+* Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.
+
+* Correct shift offsets in icache_status and dcache_status for MPC83xx.
+
+* Add support for DS1374 RTC chip.
+
+* Add support for Lite5200B board.
+  Patch by  Patch by Jose Maria (Txema) Lopez, 16 Jan 2006
+
+* Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific
+  timer and cpu_reset code from cpu/$(CPU) into the new
+  cpu/$(CPU)/$(SOC) directories
+  Patch by Andreas Engel, 13 Mar 2006
+
+* Change max size of uncompressed uImage's to 8MByte and add
+  CFG_BOOTM_LEN to adjust this setting.
+
+  As mentioned by Robin Getz on 2005-05-24 the size of uncompressed
+  uImages was restricted to 4MBytes. This default size is now
+  increased to 8Mbytes and can be overrided by setting CFG_BOOTM_LEN
+  in the board config file.
+
+  Patch by Stefan Roese, 13 Mar 2006
+
+* Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.c
+  Patch by Stefan Roese, 13 Mar 2006
+
+* cpu/ppc4xx/start.S : exceptions are enabled after relocation
+  Patch by Cedric Vincent, 06 Jul 2005
+
+* au1x00_eth.c: check malloc return value and abort if it failed
+  Patch by Andrew Dyer, 26 Jul 2005
+
+* Change the sequence of events in soft_i2c.c:send_ack() to keep from
+  incorrectly generating start/stop conditions on the bus.
+  Patch by Andrew Dyer, 26 Jul 2005
+
+* Fix bug in [id]cache_status commands for MPC85xx processors;
+  should look at LSB of L1CSRn registers to determine if L1 cache is
+  enabled, not the MSB.
+  Patch by Murray Jensen, 19 Jul 2005
+
+* Fix array overflow with fw_setenv on uninitialised environment
+  Patch by Murray Jensen, 15 Jul 2005
+
+* Add support for EmbeddedPlanet EP88x boards
+  Patch by Yuli Barcohen, 13 Jul 2005
+
+* Remove board specific configuration includes from the common xilinx
+  ethernet and iic adapter code.
+  Patch by Michael Libeskind, 12 Jul 2005
+
+* Add Nat Semi DP83865 PHY support to MPC85xx TSEC driver
+  Patch by Murray Jensen, 08 Jul 2005
+
+* Add (some) definitions for the MPC85xx local bus controller
+  Patch by Murray Jensen, 08 Jul 2005
+
+* Add CPM2 I/O pin functions for MPC85xx processors
+  Patch by Murray Jensen, 08 Jul 2005
+
+* Fix compile problem
+
+* Added PCI support for MPC8349ADS board
+  Patch by Kumar Gala 11 Jan 2006
+
+* Enable address translation on MPC83xx
+  Patch by Kumar Gala, 10 Feb 2006
+
+* Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx
+  Patch by Kumar Gala, 25 Jan 2006
+
+* Fixed defines for MPC83xx SICRL register to match current specs
+  Patch by Kumar Gala, 23 Jan 2006
+
+* Only disable the MPC83xx watchdog if its enabled out of reset.
+  If its disabled out of reset SW can later enable it if so desired
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Allow config of GPIO direction & data registers at boot on 83xx
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Enable time handling on 83xx
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Make System IO Config Registers board configurable on MPC83xx
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Fixed PCI indirect config ops to handle multiple PCI controllers
+  We need to adjust the bus number we are trying to access based
+  on which PCI controller its on
+  Patch by Kumar Gala, 12 Jan 2006
+
+* Report back PCI bus when doing table based device config
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Added support for PCI prefetchable region and BARs
+  If a host controller sets up a region as prefetchable and
+  a device's BAR denotes it as prefetchable, allocate the
+  BAR into the prefetch region.
+
+  If a BAR is prefetchable and no prefetchable region has
+  been setup by the controller we fall back to allocating
+  the BAR into the normally memory region.
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Add helper function for generic flat device tree fixups for mpc83xx
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Add support for passing initrd information via flat device tree
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Added OF_STDOUT_PATH and OF_SOC
+
+  OF_STDOUT_PATH specifies the path to the device the kernel can use
+  for console output
+
+  OF_SOC specifies the proper name of the SOC node if one exists.
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Allow board code to fixup the flat device tree before booting a kernel
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Added CONFIG_ options for bd_t and env in flat dev tree
+
+       CONFIG_OF_HAS_BD_T will put a copy of the bd_t
+       into the resulting flat device tree.
+
+       CONFIG_OF_HAS_UBOOT_ENV will copy the environment
+       variables from u-boot into the flat device tree
+
+  Patch by Kumar Gala, 11 Jan 2006
+
+* Add support for the DHCP vendor optional bootfile (#67).
+  Ignores the vendor TFTP server name option (#66).
+  Patch by Murray Jensen, 30 Jun 2005
+
+* Fix a HW timing issue on 8548 CDS for eTSEC 3 in RGMII mode
+  Patch by Andy Fleming, 14 Jun 2005
+
+* Fix bad register definitions for LTX971 PHY on MPC85xx boards.
+  Patch by Gerhard Jaeger, 21 Jun 2005
+
+* Add netconsole and some more commands to RPXlite_DW board
+  Patch by Sam Song, 19 Jun 2005
+
+* Fix bad declaration on pci_cfgfunc_nothing
+  Patch by Sam Song, 19 Jun 2005
+
+* Adjust "echo" as a default command
+  Patch by Sam Song, 19 Jun 2005
+
+* Fix PCIDF calculation in cpu/mpc8260/speed.c for MPC8280EC
+  Patch by KokHow Teh, 16 Jun 2005
+
+* Add crc of data to jffs2 (in jffs2_1pass_build_lists()).
+  Patch by Rick Bronson, 15 Jun 2005
+
+* Coding Style cleanup
+
+* Avoid dereferencing NULL in find_cmd() if no valid commands were found
+  Patch by Andrew Dyer, 13 Jun 2005
+
+* Add ADI Blackfin support
+  - add support for Analog Devices Blackfin BF533 CPU
+  - add support for the ADI BF533 Stamp uClinux board
+  - add support for the ADI BF533 EZKit board
+  Patches by Richard Klingler, 11 Jun 2005
+
+* Add loads of ntohl() in image header handling
+  Patch by Steven Scholz, 10 Jun 2005
+
+* Switch MPC86xADS and MPC885ADS boards to use cpuclk environment
+  variable to set clock
+  Patch by Yuli Barcohen, 05 Jun 2005
+
+* RPXlite configuration fixes
+  - Use correct flash sector size
+  - Use correct memory test end address
+  - Add support for bzip2 compression
+  - Various small fixes
+  Patch by Yuli Barcohen, 05 Jun 2005
+
+* Memory configuration changes for ZPC.1900 board
+  - Fix SDRAM timing on both local bus and 60x bus
+  - Add support for second flash bank (SIMM)
+  - Change boot flash base
+  Patch by Yuli Barcohen, 05 Jun 2005
+
+* Add support for Adder boards with 16MB SDRAM;
+  add support for second FEC on Adder87x board.
+  Patch by Yuli Barcohen, 05 Jun 2005
+
+* Fix conditional for including ks8695eth driver
+  Patch by Greg Ungerer, 04 Jun 2005
+
+* Fix Makefile: include config.mk only after CROSS_COMPILE is defined
+  Patch by Friedrich Lobenstock, 02 Jun 2005
+
+* Fix comment in common/soft_i2c.c
+  Patches by Peter Korsgaard/Tolunay Orkun, 26 May 2005
+
+* Cleanup compiler warnings.
+  Patch by Greg Ungerer, 21 May 2005
+
+* Word alignment fixes for word aligned NS16550 UART
+  Patch by Jean-Paul Saman, 01 Mar 2005
+
+  Fixes bug with UART that only supports word aligned access: removed
+  "__attribute__ ((packed));" for "(CFG_NS16550_REG_SIZE == 4)" some
+  (broken!) versions of GCC generate byte accesses when encountering
+  the packed attribute regardless if the struct is already correctly
+  aligned for a platform. Peripherals that can only handle word
+  aligned access won't work properly when accessed with byte access.
+  The struct NS16550 is already word aligned for REG_SIZE = 4, so
+  there is no need to packed the struct in that case.
+
+* Fix behaviour if gatewayip is not set
+  Patch by Robin Gilks, 23 Dec 2004
+
+* Fix cleanup for netstart board.
+  Remove build results from repository
+
+* Some code cleanup for GCC 4.x
+
+* Fixes to support environment in NAND flash;
+  enable NAND flash based environment for delta board.
+
+* Add support for Intel Monahans CPU on Zylonite and Delta boards
+  (This is Work in Progress!)
+
+* Add support for TQM8260-AI boards.
+
+* Minor code cleanup
+
+* Merge the new NAND code (testing-NAND brach); see doc/README.nand
+  Rewrite of NAND code based on what is in 2.6.12 Linux kernel
+  Patch by Ladislav Michl, 29 Jun 2005
+
+* Add lowboot target to mcc200 board
+  Patch by Stefan Roese, 4 Mar 2006
+
+* Fix problem with flash_get_size() from CFI driver update
+  Patch by Stefan Roese, 1 Mar 2006
+
+* Make CFG_NO_FLASH work on ARM systems
+  Patch by Markus Klotzbuecher, 27 Feb 2006
+
+* Update mcc200 config: Disable PCI and DoC, use 133 MHz IPB clock,
+  use hush shell.
+
+* Convert mcc200 to use common CFI flash driver
+  Patch by Stefan Roese, 28 Feb 2006
+
+* Add env-variable "unlock" to handle initial state of sectors
+  (locked/unlocked).
+
+  Only the U-Boot image and it's environment is protected,
+  all other sectors are unprotected (unlocked) if flash
+  hardware protection is used (CFG_FLASH_PROTECTION) and
+  the environment variable "unlock" is set to "yes".
+
+  Patch by Stefan Roese, 28 Feb 2006
+
+* Update drivers/cfi_flash.c:
+  - find_sector() called in both versions of flash_write_cfiword()
+  Patch by Peter Pearse, 27th Feb 2006
+
+* CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode
+  Patch by Jose Maria Lopez, 16 Jan 2006
+
+* Add support for AMD/Spansion Flashes in flash_write_cfibuffer
+  Patch by Alex Bastos and Thomas Schaefer, 2005-08-29
+
+* Changes/fixes for drivers/cfi_flash.c:
+  We *should* check if there are any error bits if the previous call
+  returned ERR_OK (Otherwise we will have output an error message in
+  flash_status_check() already.)  The original code would only check for
+  error bits if flash_status_check() returns ERR_TIMEOUT.
+  Patch by Marcus Hall, 23 Aug 2005
+
+* Changes/fixes for drivers/cfi_flash.c:
+  - Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c
+  - Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c
+  Patch by Sangmoon Kim, 19 Aug 2005
+
+* Fixes for drivers/cfi_flash.c:
+  - Fix wrong timeout value usage in flash_status_check()
+  - Round write_tout up when converting to msec in flash_get_size()
+  - Remove clearing flash status at the end of flash_write_cfibuffer()
+    which sets Intel 28F640J3 flash back to command mode on CSB472
+  Patch by Tolunay Orkun, 02 July 2005
+
+* Add basic support for the SMMACO4 Board from PanDaCom.
+  Patch by Heiko Schocher, 20 Feb 2006
+
+* Add GIT version information (commid ID) to untagged U-Boot versions
+
+  As done in the linux kernel, the U-Boot version (U_BOOT_VERSION)
+  of all unreleased (untagged) U-Boot images will be automatically
+  extended upon compiletime with a part of the GIT commit ID and
+  possibly with "dirty" if uncommited changes are detected.
+
+  Here an example for the resulting version:
+  "U-Boot 1.1.4-g3457ac18-dirty"
+
+  The version is now maintained in the toplevel Makefile and the
+  version headers are autogenerated.
+
+  Patch by Stefan Roese, 9 Feb 2006
+
+* Update default environment for INKA4x00 board.
+
+* Convert CPCI750 to use common CFI flash driver
+  Patch by Reinhard Arlt, 8 Feb 2006
+
+* Various changes to esd HH405 board specific files
+  Patch by Matthias Fuchs, 07 Feb 2006
+
+* Cleanup U-Boot boot messages on ARM.
+
+  To match the U-Boot user interface on ARM platforms to the U-Boot
+  standard (as on PPC platforms), some messages with debug character
+  are removed from the default U-Boot build.
+  Enable DEBUG for lib_arm/board.c to enable debug messages.
+  New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options.
+  Patch         by Stefan Roese, 24 Jan 2006
+
+* Fix various compiler warnings on ppc4xx builds (ELDK 4.0)
+  Patch by Stefan Roese, 18 Jan 2006
+
+* Add VGA support (CT69000) to CPCI750 board.
+  Insert missing __le32_to_cpu() for filesize in ext2fs_read_file().
+  Patch by Reinhard Arlt, 30 Dec 2005
+
+* PMC405 and CPCI405: Moved configuration of pci resources
+  into config file.
+  PMC405 and CPCI2DP: Added firmware download and booting via pci.
+  Patch by Matthias Fuchs, 20 Dec 2005
+
 * Add ColdFire targets to MAKEALL script
   Patch by Zachary Landau, 26 Jan 2006
 
@@ -143,11 +610,11 @@ Changes for U-Boot 1.1.4:
 
 * Add support for multiple PHYs.
   Tested on the following boards:
-       cmcpu2      (at91rm9200/ether.c)
+       cmcpu2      (at91rm9200/ether.c)
        PPChameleon (ppc4xx/4xx_enet.c)
-       yukon       (mpc8220/fec.c)
-       uc100       (mpc8xx/fec.c)
-       tqm834x     (mpc834x/tsec.c) with EEPRO100
+       yukon       (mpc8220/fec.c)
+       uc100       (mpc8xx/fec.c)
+       tqm834x     (mpc834x/tsec.c) with EEPRO100
        lite5200    (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c)
   Main changes include:
   common/miiphyutil.c
@@ -687,18 +1154,18 @@ Changes for U-Boot 1.1.3:
   The first one is to define a single, static partition:
 
   #undef CONFIG_JFFS2_CMDLINE
-  #define CONFIG_JFFS2_DEV               "nor0"
-  #define CONFIG_JFFS2_PART_SIZE         0xFFFFFFFF    /* use whole device */
-  #define CONFIG_JFFS2_PART_SIZE         0x00100000    /* use 1MB */
-  #define CONFIG_JFFS2_PART_OFFSET       0x00000000
+  #define CONFIG_JFFS2_DEV              "nor0"
+  #define CONFIG_JFFS2_PART_SIZE        0xFFFFFFFF     /* use whole device */
+  #define CONFIG_JFFS2_PART_SIZE        0x00100000     /* use 1MB */
+  #define CONFIG_JFFS2_PART_OFFSET      0x00000000
 
   The second method uses the mtdparts command line option and dynamic
   partitioning:
 
   /* mtdparts command line support */
   #define CONFIG_JFFS2_CMDLINE
-  #define MTDIDS_DEFAULT         "nor1=zuma-1,nor2=zuma-2"
-  #define MTDPARTS_DEFAULT       "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
+  #define MTDIDS_DEFAULT        "nor1=zuma-1,nor2=zuma-2"
+  #define MTDPARTS_DEFAULT      "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
 
   Command line of course produces bigger images, and may be inappropriate
   for some targets, so by default it's off.
@@ -3011,7 +3478,7 @@ Changes for U-Boot 1.0.1:
   Bring ARM memory layout in sync with the documentation:
   stack and malloc-heap are now located _below_ the U-Boot code
 
-* Accelerate booting on TRAB board: read and check  autoupdate  image
+* Accelerate booting on TRAB board: read and check  autoupdate image
   headers first instead of always reading the whole images.
 
 * Fix type in MPC5XXX code (pointed out by Victor Wren)
@@ -3131,7 +3598,7 @@ Changes for U-Boot 1.0.0:
 * Make 5200 reset command _really_ reset the board, without running
   any other code after it
 
-* Fix errors with flash erase when range spans  across banks
+* Fix errors with flash erase when range spans across banks
   that are mapped in reverse order
 
 * Fix flash mapping and display on P3G4 board
@@ -3375,7 +3842,7 @@ Changes for U-Boot 0.4.8:
   or 1 x AM29LV652 (two LV065 in one chip = 16 MB);
   Run IPB at 133 Mhz; adjust the MII clock frequency accordingly
 
-* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16  MHz)
+* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16         MHz)
   to allow for more accurate baudrate settings
   (error now 0.7% at 115 kbps, instead of 3.5% before)
 
@@ -3862,7 +4329,7 @@ Changes for U-Boot 0.4.0:
   Update for MPC8266ADS board
 
 * Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length
-  instead CFG_MONITOR_LEN is now only used to determine  _at_compile_
+  instead CFG_MONITOR_LEN is now only used to determine         _at_compile_
   _time_  (!) if the environment is embedded within the U-Boot image,
   or in a separate flash sector.
 
@@ -3912,7 +4379,7 @@ Changes for U-Boot 0.4.0:
 * Patch by Thomas Schäfer, 28 Apr 2003:
   Fix SPD handling for 256 ECC DIMM on Walnut
 
-* Add support for arbitrary bitmaps for TRAB's  VFD command;
+* Add support for arbitrary bitmaps for TRAB's VFD command;
   allow to pass boot bitmap addresses in environment variables;
   allow for zero boot delay
 
@@ -4255,7 +4722,7 @@ Changes for U-Boot 0.3.0:
 
 * Add VFD type detection to trab board
 
-* extend drivers/cs8900.c driver to synchronize  ethaddr  environment
+* extend drivers/cs8900.c driver to synchronize         ethaddr  environment
   variable with value in the EEPROM
 
 * Patch by Stefan Roese, 10 Feb 2003:
@@ -4415,7 +4882,7 @@ Changes for U-Boot 0.2.0:
 * Patch by Pierre Aubert, 05 Nov 2002
   Add support for slave serial Spartan 2 FPGAs
 
-* Fix uninitialized memory (MAC  address)  in  8xx  SCC/FEC  ethernet
+* Fix uninitialized memory (MAC         address)  in  8xx  SCC/FEC  ethernet
   drivers
 
 * Add support for log buffer which can be passed to Linux kernel's

diff --git a/MAKEALL b/MAKEALL
index dce3611fead4e4ec036fde11e66109da6d9bceed..cbc105ba6f6a7c5783b7295c59b6b5c9296376c3 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -25,9 +25,10 @@ LIST_5xx="   \
 #########################################################################
 
 LIST_5xxx="    \
-       cpci5200        icecube_5100    icecube_5200    EVAL5200        \
+       BC3450          cpci5200        EVAL5200        icecube_5100    \
+       icecube_5200    lite5200b       mcc200          o2dnt           \
        pf5200          PM520           Total5100       Total5200       \
-       Total5200_Rev2  TQM5200_auto    o2dnt                           \
+       Total5200_Rev2  TQM5200_auto                                    \
 "
 
 #########################################################################
@@ -43,16 +44,16 @@ LIST_8xx="  \
        CCM             IP860           NETPHONE        RPXlite_DW      \
        cogent_mpc8xx   IVML24          NETTA           RRvision        \
        ELPT860         IVML24_128      NETTA2          SM850           \
-       ESTEEM192E      IVML24_256      NETTA_ISDN      SPD823TS        \
-       ETX094          IVMS8           NETVIA          svm_sc8xx       \
-       FADS823         IVMS8_128       NETVIA_V2       SXNI855T        \
-       FADS850SAR      IVMS8_256       NX823           TOP860          \
-       FADS860T        KUP4K           pcu_e           TQM823L         \
-       FLAGADM         KUP4X           QS823           TQM823L_LCD     \
-       FPS850L         LANTEC          QS850           TQM850L         \
-       GEN860T         lwmon           QS860T          TQM855L         \
-       GEN860T_SC      MBX             quantum         TQM860L         \
-                                                       uc100           \
+       EP88x           IVML24_256      NETTA_ISDN      SPD823TS        \
+       ESTEEM192E      IVMS8           NETVIA          svm_sc8xx       \
+       ETX094          IVMS8_128       NETVIA_V2       SXNI855T        \
+       FADS823         IVMS8_256       NX823           TOP860          \
+       FADS850SAR      KUP4K           pcu_e           TQM823L         \
+       FADS860T        KUP4X           QS823           TQM823L_LCD     \
+       FLAGADM         LANTEC          QS850           TQM850L         \
+       FPS850L         lwmon           QS860T          TQM855L         \
+       GEN860T         MBX             quantum         TQM860L         \
+       GEN860T_SC                                      uc100           \
                                                        v37             \
 "
 
@@ -116,7 +117,7 @@ LIST_8260=" \
 #########################################################################
 
 LIST_83xx="    \
-       MPC8349ADS      TQM834x\
+       MPC8349ADS      TQM834x         MPC8349EMDS                     \
 "
 
 
@@ -177,10 +178,10 @@ LIST_ARM9="       \
        ap920t          ap922_XA10      ap926ejs        ap946es         \
        ap966           cp920t          cp922_XA10      cp926ejs        \
        cp946es         cp966           lpd7a400        mp2usb          \
-       mx1ads          mx1fs2          omap1510inn     omap1610h2      \
-       omap1610inn     omap730p2       scb9328         smdk2400        \
-       smdk2410        trab            VCMA9           versatile       \
-       versatileab     versatilepb     voiceblue
+       mx1ads          mx1fs2          netstar         omap1510inn     \
+       omap1610h2      omap1610inn     omap730p2       scb9328         \
+       smdk2400        smdk2410        trab            VCMA9           \
+       versatile       versatileab     versatilepb     voiceblue
 "
 
 #########################################################################
@@ -203,8 +204,9 @@ LIST_ARM11="        \
 
 LIST_pxa="     \
        adsvix          cerf250         cradle          csb226          \
-       innokom         lubbock         pxa255_idp      wepep250        \
-       xaeniax         xm250           xsengine                        \
+       delta           innokom         lubbock         pxa255_idp      \
+       wepep250        xaeniax         xm250           xsengine        \
+       zylonite                                                        \
 "
 
 LIST_ixp="ixdp425"

diff --git a/Makefile b/Makefile
index 2ac35a6728c78a8e532c39902c7a9abb27f5d370..0470f33bd7bd330783a482648613c96c56bbab8d 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2005
+# (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -21,6 +21,13 @@
 # MA 02111-1307 USA
 #
 
+VERSION = 1
+PATCHLEVEL = 1
+SUBLEVEL = 4
+EXTRAVERSION =
+U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+VERSION_FILE = include/version_autogenerated.h
+
 HOSTARCH := $(shell uname -m | \
        sed -e s/i.86/i386/ \
            -e s/sun4u/sparc64/ \
@@ -46,9 +53,6 @@ ifeq (include/config.mk,$(wildcard include/config.mk))
 # load ARCH, BOARD, and CPU configuration
 include include/config.mk
 export ARCH CPU BOARD VENDOR SOC
-# load other configuration
-include $(TOPDIR)/config.mk
-
 ifndef CROSS_COMPILE
 ifeq ($(HOSTARCH),ppc)
 CROSS_COMPILE =
@@ -81,11 +85,18 @@ endif
 ifeq ($(ARCH),microblaze)
 CROSS_COMPILE = mb-
 endif
+ifeq ($(ARCH),blackfin)
+CROSS_COMPILE = bfin-elf-
+endif
 endif
 endif
 
 export CROSS_COMPILE
 
+# load other configuration
+include $(TOPDIR)/config.mk
+
+
 #########################################################################
 # U-Boot objects....order is important (i.e. start must be first)
 
@@ -103,6 +114,10 @@ endif
 ifeq ($(CPU),mpc85xx)
 OBJS += cpu/$(CPU)/resetvec.o
 endif
+ifeq ($(CPU),bf533)
+OBJS += cpu/$(CPU)/start1.o    cpu/$(CPU)/interrupt.o  cpu/$(CPU)/cache.o
+OBJS += cpu/$(CPU)/cplbhdlr.o  cpu/$(CPU)/cplbmgr.o    cpu/$(CPU)/flush.o
+endif
 
 LIBS  = lib_generic/libgeneric.a
 LIBS += board/$(BOARDDIR)/lib$(BOARD).a
@@ -118,9 +133,12 @@ LIBS += disk/libdisk.a
 LIBS += rtc/librtc.a
 LIBS += dtt/libdtt.a
 LIBS += drivers/libdrivers.a
+LIBS += drivers/nand/libnand.a
+LIBS += drivers/nand_legacy/libnand_legacy.a
 LIBS += drivers/sk98lin/libsk98lin.a
 LIBS += post/libpost.a post/cpu/libcpu.a
 LIBS += common/libcommon.a
+LIBS += $(BOARDLIBS)
 .PHONY : $(LIBS)
 
 # Add GCC lib
@@ -154,14 +172,14 @@ u-boot.bin:       u-boot
 u-boot.img:    u-boot.bin
                ./tools/mkimage -A $(ARCH) -T firmware -C none \
                -a $(TEXT_BASE) -e 0 \
-               -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' include/version.h | \
+               -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
                        sed -e 's/"[     ]*$$/ for $(BOARD) board"/') \
                -d $< $@
 
 u-boot.dis:    u-boot
                $(OBJDUMP) -d $< > $@
 
-u-boot:                depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
+u-boot:                depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
                UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed  -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
                $(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
                        --start-group $(LIBS) --end-group $(PLATFORM_LIBS) \
@@ -173,6 +191,13 @@ $(LIBS):
 $(SUBDIRS):
                $(MAKE) -C $@ all
 
+version:
+               @echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \
+               echo -n "$(U_BOOT_VERSION)" >> $(VERSION_FILE); \
+               echo -n $(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion \
+                        $(TOPDIR)) >> $(VERSION_FILE); \
+               echo "\"" >> $(VERSION_FILE)
+
 gdbtools:
                $(MAKE) -C tools/gdb || exit 1
 
@@ -234,6 +259,9 @@ PATI_config:                unconfig
 aev_config: unconfig
        @./mkconfig -a aev ppc mpc5xxx tqm5200
 
+BC3450_config: unconfig
+       @./mkconfig -a BC3450 ppc mpc5xxx bc3450
+
 cpci5200_config:  unconfig
        @./mkconfig -a cpci5200  ppc mpc5xxx cpci5200 esd
 
@@ -277,14 +305,37 @@ icecube_5100_config:                      unconfig
                }
        @./mkconfig -a IceCube ppc mpc5xxx icecube
 
-inka4x0_config:                unconfig
+inka4x0_config:        unconfig
        @./mkconfig inka4x0 ppc mpc5xxx inka4x0
 
+lite5200b_config       \
+lite5200b_LOWBOOT_config:      unconfig
+       @ >include/config.h
+       @ echo "#define CONFIG_MPC5200_DDR"     >>include/config.h
+       @ echo "... DDR memory revision"
+       @ echo "#define CONFIG_MPC5200"         >>include/config.h
+       @ echo "#define CONFIG_LITE5200B"       >>include/config.h
+       @[ -z "$(findstring LOWBOOT_,$@)" ] || \
+               { echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \
+                 echo "... with LOWBOOT configuration" ; \
+               }
+       @ echo "... with MPC5200B processor"
+       @./mkconfig -a IceCube  ppc mpc5xxx icecube
+
+mcc200_config  \
+mcc200_lowboot_config: unconfig
+       @ >include/config.h
+       @[ -z "$(findstring lowboot_,$@)" ] || \
+               { echo "TEXT_BASE = 0xFE000000" >board/mcc200/config.tmp ; \
+                 echo "... with lowboot configuration" ; \
+               }
+       @./mkconfig mcc200 ppc mpc5xxx mcc200
+
 o2dnt_config:
-       @./mkconfig -a o2dnt ppc mpc5xxx o2dnt
+       @./mkconfig o2dnt ppc mpc5xxx o2dnt
 
 pf5200_config:  unconfig
-       @./mkconfig -a pf5200  ppc mpc5xxx pf5200 esd
+       @./mkconfig pf5200  ppc mpc5xxx pf5200 esd
 
 PM520_config \
 PM520_DDR_config \
@@ -301,6 +352,14 @@ PM520_ROMBOOT_DDR_config:  unconfig
                }
        @./mkconfig -a PM520 ppc mpc5xxx pm520
 
+smmaco4_config: unconfig
+       @./mkconfig -a smmaco4 ppc mpc5xxx tqm5200
+
+spieval_config:        unconfig
+       echo "#define CONFIG_CS_AUTOCONF">>include/config.h
+       echo "... with automatic CS configuration"
+       @./mkconfig -a spieval ppc mpc5xxx tqm5200
+
 MINI5200_config        \
 EVAL5200_config        \
 TOP5200_config:        unconfig
@@ -366,11 +425,6 @@ MiniFAP_config:    unconfig
                }
        @./mkconfig -a TQM5200 ppc mpc5xxx tqm5200
 
-spieval_config:        unconfig
-       echo "#define CONFIG_CS_AUTOCONF">>include/config.h
-       echo "... with automatic CS configuration"
-       @./mkconfig -a spieval ppc mpc5xxx tqm5200
-
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
@@ -406,6 +460,9 @@ cogent_mpc8xx_config:       unconfig
 ELPT860_config:                unconfig
        @./mkconfig $(@:_config=) ppc mpc8xx elpt860 LEOX
 
+EP88x_config:          unconfig
+       @./mkconfig $(@:_config=) ppc mpc8xx ep88x
+
 ESTEEM192E_config:     unconfig
        @./mkconfig $(@:_config=) ppc mpc8xx esteem192e
 
@@ -579,8 +636,21 @@ NETTA2_config:             unconfig
                 }
        @./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2
 
-NC650_config:  unconfig
-       @./mkconfig $(@:_config=) ppc mpc8xx nc650
+NC650_Rev1_config \
+NC650_Rev2_config \
+CP850_config:  unconfig
+       @ >include/config.h
+       @[ -z "$(findstring CP850,$@)" ] || \
+                { echo "#define CONFIG_CP850 1" >>include/config.h ; \
+                  echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \
+                }
+       @[ -z "$(findstring Rev1,$@)" ] || \
+                { echo "#define CONFIG_IDS852_REV1 1" >>include/config.h ; \
+                }
+       @[ -z "$(findstring Rev2,$@)" ] || \
+                { echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \
+                }
+       @./mkconfig -a NC650 ppc mpc8xx nc650
 
 NX823_config:          unconfig
        @./mkconfig $(@:_config=) ppc mpc8xx nx823
@@ -1135,7 +1205,7 @@ PM828_config      \
 PM828_PCI_config       \
 PM828_ROMBOOT_config   \
 PM828_ROMBOOT_PCI_config:      unconfig
-       @if [ -z "$(findstring _PCI_,$@)" ] ; then \
+       @if [ "$(findstring _PCI_,$@)" ] ; then \
                echo "#define CONFIG_PCI"  >>include/config.h ; \
                echo "... with PCI enabled" ; \
        else \
@@ -1181,18 +1251,20 @@ TQM8260_AE_config \
 TQM8260_AF_config \
 TQM8260_AG_config \
 TQM8260_AH_config \
+TQM8260_AI_config \
 TQM8265_AA_config:  unconfig
        @case "$@" in \
-       TQM8255_AA_config) CTYPE=MPC8255; CFREQ=300; CACHE=no;  BMODE=8260;;  \
-       TQM8260_AA_config) CTYPE=MPC8260; CFREQ=200; CACHE=no;  BMODE=8260;; \
-       TQM8260_AB_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;;  \
-       TQM8260_AC_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;;  \
-       TQM8260_AD_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=60x;;  \
-       TQM8260_AE_config) CTYPE=MPC8260; CFREQ=266; CACHE=no;  BMODE=8260;; \
-       TQM8260_AF_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=60x;;  \
-       TQM8260_AG_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=8260;; \
-       TQM8260_AH_config) CTYPE=MPC8260; CFREQ=300; CACHE=yes; BMODE=60x;;  \
-       TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no;  BMODE=60x;;  \
+       TQM8255_AA_config) CTYPE=MPC8255; CFREQ=300; CACHE=no;  BMODE=8260;;  \
+       TQM8260_AA_config) CTYPE=MPC8260; CFREQ=200; CACHE=no;  BMODE=8260;; \
+       TQM8260_AB_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;;  \
+       TQM8260_AC_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;;  \
+       TQM8260_AD_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=60x;;  \
+       TQM8260_AE_config) CTYPE=MPC8260; CFREQ=266; CACHE=no;  BMODE=8260;; \
+       TQM8260_AF_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=60x;;  \
+       TQM8260_AG_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=8260;; \
+       TQM8260_AH_config) CTYPE=MPC8260; CFREQ=300; CACHE=yes; BMODE=60x;;  \
+       TQM8260_AI_config) CTYPE=MPC8260; CFREQ=300; CACHE=no;  BMODE=60x;;  \
+       TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no;  BMODE=60x;;  \
        esac; \
        >include/config.h ; \
        if [ "$${CTYPE}" != "MPC8260" ] ; then \
@@ -1256,6 +1328,9 @@ MPC8349ADS_config:        unconfig
 TQM834x_config:        unconfig
        @./mkconfig $(@:_config=) ppc mpc83xx tqm834x
 
+MPC8349EMDS_config:    unconfig
+       @./mkconfig $(@:_config=) ppc mpc83xx mpc8349emds
+
 #########################################################################
 ## MPC85xx Systems
 #########################################################################
@@ -1462,11 +1537,22 @@ mx1ads_config   :       unconfig
 mx1fs2_config  :       unconfig
        @./mkconfig $(@:_config=) arm arm920t mx1fs2 NULL imx
 
+netstar_32_config      \
+netstar_config:                unconfig
+       @if [ "$(findstring _32_,$@)" ] ; then \
+               echo "... 32MB SDRAM" ; \
+               echo "#define PHYS_SDRAM_1_SIZE SZ_32M" >>include/config.h ; \
+       else \
+               echo "... 64MB SDRAM" ; \
+               echo "#define PHYS_SDRAM_1_SIZE SZ_64M" >>include/config.h ; \
+       fi
+       @./mkconfig -a netstar arm arm925t netstar
+
 omap1510inn_config :   unconfig
        @./mkconfig $(@:_config=) arm arm925t omap1510inn
 
 omap5912osk_config :   unconfig
-       @./mkconfig $(@:_config=) arm arm926ejs omap5912osk
+       @./mkconfig $(@:_config=) arm arm926ejs omap5912osk NULL omap
 
 omap1610inn_config \
 omap1610inn_cs0boot_config \
@@ -1486,7 +1572,7 @@ omap1610h2_cs_autoboot_config:    unconfig
                echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
                echo "... configured for CS3 boot"; \
        fi;
-       @./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn
+       @./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn NULL omap
 
 omap730p2_config \
 omap730p2_cs0boot_config \
@@ -1498,7 +1584,7 @@ omap730p2_cs3boot_config :        unconfig
                echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
                echo "... configured for CS3 boot"; \
        fi;
-       @./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2
+       @./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap
 
 scb9328_config :       unconfig
        @./mkconfig $(@:_config=) arm arm920t scb9328 NULL imx
@@ -1609,6 +1695,9 @@ cradle_config     :       unconfig
 csb226_config  :       unconfig
        @./mkconfig $(@:_config=) arm pxa csb226
 
+delta_config :
+       @./mkconfig $(@:_config=) arm pxa delta
+
 innokom_config :       unconfig
        @./mkconfig $(@:_config=) arm pxa innokom
 
@@ -1636,6 +1725,9 @@ xm250_config      :       unconfig
 xsengine_config :      unconfig
        @./mkconfig $(@:_config=) arm pxa xsengine
 
+zylonite_config :
+       @./mkconfig $(@:_config=) arm pxa zylonite
+
 #########################################################################
 ## ARM1136 Systems
 #########################################################################
@@ -1815,6 +1907,19 @@ suzaku_config:   unconfig
        @echo "#define CONFIG_SUZAKU 1" >> include/config.h
        @./mkconfig -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
 
+#########################################################################
+## Blackfin
+#########################################################################
+ezkit533_config        :       unconfig
+       @./mkconfig $(@:_config=) blackfin bf533 ezkit533
+
+stamp_config   :       unconfig
+       @./mkconfig $(@:_config=) blackfin bf533 stamp
+
+dspstamp_config        :       unconfig
+       @./mkconfig $(@:_config=) blackfin bf533 dsp_stamp
+
+#########################################################################
 #########################################################################
 #########################################################################
 
@@ -1826,6 +1931,7 @@ clean:
        rm -f examples/hello_world examples/timer \
              examples/eepro100_eeprom examples/sched \
              examples/mem_to_mem_idma2intr examples/82559_eeprom \
+             examples/smc91111_eeprom \
              examples/test_burst
        rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
        rm -f tools/mpc86x_clk tools/ncb
@@ -1833,6 +1939,8 @@ clean:
        rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
        rm -f tools/env/fw_printenv tools/env/fw_setenv
        rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
+       rm -f board/netstar/eeprom board/netstar/crcek
+       rm -f board/netstar/*.srec board/netstar/*.bin
        rm -f board/trab/trab_fkt board/voiceblue/eeprom
        rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds
 
@@ -1841,7 +1949,7 @@ clobber:  clean
                -o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
                -print0 \
                | xargs -0 rm -f
-       rm -f $(OBJS) *.bak tags TAGS
+       rm -f $(OBJS) *.bak tags TAGS include/version_autogenerated.h
        rm -fr *.*~
        rm -f u-boot u-boot.map u-boot.hex $(ALL)
        rm -f tools/crc32.c tools/environment.c tools/env/crc32.c

diff --git a/README b/README
index 6f610082224e54fc0a31246cdea7ad688df1e6d1..3ffef62538fe2612c1ba2379d982d5ac7e0a1565 100644 (file)
--- a/README
+++ b/README
@@ -246,6 +246,7 @@ The following options need to be configured:
                CONFIG_SA1110
                CONFIG_ARM7
                CONFIG_PXA250
+               CONFIG_CPU_MONAHANS
 
                MicroBlaze based CPUs:
                ----------------------
@@ -261,56 +262,56 @@ The following options need to be configured:
                PowerPC based boards:
                ---------------------
 
-               CONFIG_ADCIOP           CONFIG_GEN860T          CONFIG_PCIPPC2
-               CONFIG_ADS860           CONFIG_GENIETV          CONFIG_PCIPPC6
-               CONFIG_AMX860           CONFIG_GTH              CONFIG_pcu_e
-               CONFIG_AP1000           CONFIG_gw8260           CONFIG_PIP405
-               CONFIG_AR405            CONFIG_hermes           CONFIG_PM826
-               CONFIG_BAB7xx           CONFIG_hymod            CONFIG_ppmc8260
-               CONFIG_c2mon            CONFIG_IAD210           CONFIG_QS823
-               CONFIG_CANBT            CONFIG_ICU862           CONFIG_QS850
-               CONFIG_CCM              CONFIG_IP860            CONFIG_QS860T
-               CONFIG_CMI              CONFIG_IPHASE4539       CONFIG_RBC823
-               CONFIG_cogent_mpc8260   CONFIG_IVML24           CONFIG_RPXClassic
-               CONFIG_cogent_mpc8xx    CONFIG_IVML24_128       CONFIG_RPXlite
-               CONFIG_CPCI405          CONFIG_IVML24_256       CONFIG_RPXsuper
-               CONFIG_CPCI4052         CONFIG_IVMS8            CONFIG_rsdproto
-               CONFIG_CPCIISER4        CONFIG_IVMS8_128        CONFIG_sacsng
-               CONFIG_CPU86            CONFIG_IVMS8_256        CONFIG_Sandpoint8240
-               CONFIG_CRAYL1           CONFIG_JSE              CONFIG_Sandpoint8245
-               CONFIG_CSB272           CONFIG_LANTEC           CONFIG_sbc8260
-               CONFIG_CU824            CONFIG_lwmon            CONFIG_sbc8560
-               CONFIG_DASA_SIM         CONFIG_MBX              CONFIG_SM850
-               CONFIG_DB64360          CONFIG_MBX860T          CONFIG_SPD823TS
-               CONFIG_DB64460          CONFIG_MHPC             CONFIG_STXGP3
-               CONFIG_DU405            CONFIG_MIP405           CONFIG_SXNI855T
-               CONFIG_DUET_ADS         CONFIG_MOUSSE           CONFIG_TQM823L
-               CONFIG_EBONY            CONFIG_MPC8260ADS       CONFIG_TQM8260
-               CONFIG_ELPPC            CONFIG_MPC8540ADS       CONFIG_TQM850L
-               CONFIG_ELPT860          CONFIG_MPC8540EVAL      CONFIG_TQM855L
-               CONFIG_ep8260           CONFIG_MPC8560ADS       CONFIG_TQM860L
-               CONFIG_ERIC             CONFIG_MUSENKI          CONFIG_TTTech
-               CONFIG_ESTEEM192E       CONFIG_MVS1             CONFIG_UTX8245
-               CONFIG_ETX094           CONFIG_NETPHONE         CONFIG_V37
-               CONFIG_EVB64260         CONFIG_NETTA            CONFIG_W7OLMC
-               CONFIG_FADS823          CONFIG_NETVIA           CONFIG_W7OLMG
-               CONFIG_FADS850SAR       CONFIG_NX823            CONFIG_WALNUT
-               CONFIG_FADS860T         CONFIG_OCRTC            CONFIG_ZPC1900
-               CONFIG_FLAGADM          CONFIG_ORSG             CONFIG_ZUMA
-               CONFIG_FPS850L          CONFIG_OXC
-               CONFIG_FPS860L          CONFIG_PCI405
+               CONFIG_ADCIOP           CONFIG_FPS860L          CONFIG_OXC
+               CONFIG_ADS860           CONFIG_GEN860T          CONFIG_PCI405
+               CONFIG_AMX860           CONFIG_GENIETV          CONFIG_PCIPPC2
+               CONFIG_AP1000           CONFIG_GTH              CONFIG_PCIPPC6
+               CONFIG_AR405            CONFIG_gw8260           CONFIG_pcu_e
+               CONFIG_BAB7xx           CONFIG_hermes           CONFIG_PIP405
+               CONFIG_BC3450           CONFIG_hymod            CONFIG_PM826
+               CONFIG_c2mon            CONFIG_IAD210           CONFIG_ppmc8260
+               CONFIG_CANBT            CONFIG_ICU862           CONFIG_QS823
+               CONFIG_CCM              CONFIG_IP860            CONFIG_QS850
+               CONFIG_CMI              CONFIG_IPHASE4539       CONFIG_QS860T
+               CONFIG_cogent_mpc8260   CONFIG_IVML24           CONFIG_RBC823
+               CONFIG_cogent_mpc8xx    CONFIG_IVML24_128       CONFIG_RPXClassic
+               CONFIG_CPCI405          CONFIG_IVML24_256       CONFIG_RPXlite
+               CONFIG_CPCI4052         CONFIG_IVMS8            CONFIG_RPXsuper
+               CONFIG_CPCIISER4        CONFIG_IVMS8_128        CONFIG_rsdproto
+               CONFIG_CPU86            CONFIG_IVMS8_256        CONFIG_sacsng
+               CONFIG_CRAYL1           CONFIG_JSE              CONFIG_Sandpoint8240
+               CONFIG_CSB272           CONFIG_LANTEC           CONFIG_Sandpoint8245
+               CONFIG_CU824            CONFIG_LITE5200B        CONFIG_sbc8260
+               CONFIG_DASA_SIM         CONFIG_lwmon            CONFIG_sbc8560
+               CONFIG_DB64360          CONFIG_MBX              CONFIG_SM850
+               CONFIG_DB64460          CONFIG_MBX860T          CONFIG_SPD823TS
+               CONFIG_DU405            CONFIG_MHPC             CONFIG_STXGP3
+               CONFIG_DUET_ADS         CONFIG_MIP405           CONFIG_SXNI855T
+               CONFIG_EBONY            CONFIG_MOUSSE           CONFIG_TQM823L
+               CONFIG_ELPPC            CONFIG_MPC8260ADS       CONFIG_TQM8260
+               CONFIG_ELPT860          CONFIG_MPC8540ADS       CONFIG_TQM850L
+               CONFIG_ep8260           CONFIG_MPC8540EVAL      CONFIG_TQM855L
+               CONFIG_ERIC             CONFIG_MPC8560ADS       CONFIG_TQM860L
+               CONFIG_ESTEEM192E       CONFIG_MUSENKI          CONFIG_TTTech
+               CONFIG_ETX094           CONFIG_MVS1             CONFIG_UTX8245
+               CONFIG_EVB64260         CONFIG_NETPHONE         CONFIG_V37
+               CONFIG_FADS823          CONFIG_NETTA            CONFIG_W7OLMC
+               CONFIG_FADS850SAR       CONFIG_NETVIA           CONFIG_W7OLMG
+               CONFIG_FADS860T         CONFIG_NX823            CONFIG_WALNUT
+               CONFIG_FLAGADM          CONFIG_OCRTC            CONFIG_ZPC1900
+               CONFIG_FPS850L          CONFIG_ORSG             CONFIG_ZUMA
 
                ARM based boards:
                -----------------
 
                CONFIG_ARMADILLO,       CONFIG_AT91RM9200DK,    CONFIG_CERF250,
-               CONFIG_CSB637,          CONFIG_DNP1110,         CONFIG_EP7312,
-               CONFIG_H2_OMAP1610,     CONFIG_HHP_CRADLE,      CONFIG_IMPA7,
-               CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, CONFIG_KB9202,
-               CONFIG_LART,            CONFIG_LPD7A400,        CONFIG_LUBBOCK,
-               CONFIG_OSK_OMAP5912,    CONFIG_OMAP2420H4,      CONFIG_SHANNON,
-               CONFIG_P2_OMAP730,      CONFIG_SMDK2400,        CONFIG_SMDK2410,
-               CONFIG_TRAB,            CONFIG_VCMA9
+               CONFIG_CSB637,          CONFIG_DELTA,           CONFIG_DNP1110,
+               CONFIG_EP7312,          CONFIG_H2_OMAP1610,     CONFIG_HHP_CRADLE,
+               CONFIG_IMPA7,       CONFIG_INNOVATOROMAP1510,   CONFIG_INNOVATOROMAP1610,
+               CONFIG_KB9202,          CONFIG_LART,            CONFIG_LPD7A400,
+               CONFIG_LUBBOCK,         CONFIG_OSK_OMAP5912,    CONFIG_OMAP2420H4,
+               CONFIG_SHANNON,         CONFIG_P2_OMAP730,      CONFIG_SMDK2400,
+               CONFIG_SMDK2410,        CONFIG_TRAB,            CONFIG_VCMA9
 
                MicroBlaze based boards:
                ------------------------
@@ -379,6 +380,20 @@ The following options need to be configured:
                that this requires a (stable) reference clock (32 kHz
                RTC clock or CFG_8XX_XIN)
 
+- Intel Monahans options:
+               CFG_MONAHANS_RUN_MODE_OSC_RATIO
+
+               Defines the Monahans run mode to oscillator
+               ratio. Valid values are 8, 16, 24, 31. The core
+               frequency is this value multiplied by 13 MHz.
+
+               CFG_MONAHANS_TURBO_RUN_MODE_RATIO
+
+               Defines the Monahans turbo mode to oscillator
+               ratio. Valid values are 1 (default if undefined) and
+               2. The core frequency as calculated above is multiplied
+               by this value.
+
 - Linux Kernel Interface:
                CONFIG_CLOCKS_IN_MHZ
 
@@ -411,7 +426,24 @@ The following options need to be configured:
                The maximum size of the constructed OF tree.
 
                OF_CPU - The proper name of the cpus node.
+               OF_SOC - The proper name of the soc node.
                OF_TBCLK - The timebase frequency.
+               OF_STDOUT_PATH - The path to the console device
+
+               CONFIG_OF_HAS_BD_T
+
+               The resulting flat device tree will have a copy of the bd_t.
+               Space should be pre-allocated in the dts for the bd_t.
+
+               CONFIG_OF_HAS_UBOOT_ENV
+
+               The resulting flat device tree will have a copy of u-boot's
+               environment variables
+
+               CONFIG_OF_BOARD_SETUP
+
+               Board code has addition modification that it wants to make
+               to the flat device tree before handing it off to the kernel
 
 - Serial Ports:
                CFG_PL010_SERIAL
@@ -606,7 +638,7 @@ The following options need to be configured:
                CFG_CMD_DIAG    * Diagnostics
                CFG_CMD_DOC     * Disk-On-Chip Support
                CFG_CMD_DTT     * Digital Therm and Thermostat
-               CFG_CMD_ECHO    * echo arguments
+               CFG_CMD_ECHO      echo arguments
                CFG_CMD_EEPROM  * EEPROM read/write support
                CFG_CMD_ELF     * bootelf, bootvx
                CFG_CMD_ENV       saveenv
@@ -1717,6 +1749,12 @@ Configuration Settings:
 - CFG_MALLOC_LEN:
                Size of DRAM reserved for malloc() use.
 
+- CFG_BOOTM_LEN:
+               Normally compressed uImages are limited to an
+               uncompressed size of 8 MBytes. If this is not enough,
+               you can define CFG_BOOTM_LEN in your board config file
+               to adjust this setting to your needs.
+
 - CFG_BOOTMAPSZ:
                Maximum size of memory mapped by the startup code of
                the Linux kernel; all data that must be processed by
@@ -1946,6 +1984,17 @@ to save the current settings.
          These two #defines specify the offset and size of the environment
          area within the first NAND device.
 
+       - CFG_ENV_OFFSET_REDUND
+
+         This setting describes a second storage area of CFG_ENV_SIZE
+         size used to hold a redundant copy of the environment data,
+         so that there is a valid backup copy in case there is a
+         power failure during a "saveenv" operation.
+
+       Note: CFG_ENV_OFFSET and CFG_ENV_OFFSET_REDUND must be aligned
+       to a block boundary, and CFG_ENV_SIZE must be a multiple of
+       the NAND devices block size.
+
 - CFG_SPI_INIT_OFFSET
 
        Defines offset to the initial SPI buffer area in DPRAM. The
@@ -3260,6 +3309,8 @@ On ARM, the following registers are used:
 
     ==> U-Boot will use R8 to hold a pointer to the global data
 
+NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
+or current versions of GCC may "optimize" the code too much.
 
 Memory Management:
 ------------------

diff --git a/blackfin_config.mk b/blackfin_config.mk
new file mode 100644 (file)
index 0000000..e2747aa
--- /dev/null
+++ b/blackfin_config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__blackfin__

diff --git a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
index 0934e1b693aeb7fd0e16d60e04e5e8deace8a1d9..40f41c78185dbf6de24cc6fe3822af5650029fcb 100644 (file)
--- a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
+++ b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
@@ -1,6 +1,7 @@
 /*
  * (C) Copyright 2002
  * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
+ * (C) Copyright 2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -88,8 +89,6 @@ long initdram (int board_type)
 
 void after_reloc (ulong dest_addr, gd_t *gd)
 {
-/* HJF:        DECLARE_GLOBAL_DATA_PTR; */
-
        board_init_r (gd, dest_addr);
 }
 

diff --git a/board/MAI/AmigaOneG3SE/articiaS.c b/board/MAI/AmigaOneG3SE/articiaS.c
index a4dad6486b043ad130fd1ccaf4470f152e2d75aa..3901b80c1124395200b2f950b021812651448523 100644 (file)
--- a/board/MAI/AmigaOneG3SE/articiaS.c
+++ b/board/MAI/AmigaOneG3SE/articiaS.c
@@ -29,6 +29,8 @@
 #include "smbus.h"
 #include "via686.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef DEBUG
 
 struct dimm_bank {
@@ -82,7 +84,6 @@ static inline unsigned short NSto10PS (unsigned char spd_byte)
 
 long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks)
 {
-    DECLARE_GLOBAL_DATA_PTR;
        int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR;
        uint32 busclock = gd->bus_clk;
        uint32 memclock = busclock;
@@ -394,8 +395,6 @@ uint32 burst_to_len (uint32 support)
 
 long articiaS_ram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        register uint32 i;
        register uint32 value1;
        register uint32 value2;

diff --git a/board/MAI/AmigaOneG3SE/articiaS_pci.c b/board/MAI/AmigaOneG3SE/articiaS_pci.c
index d2e9f292e084d8dec2c55dbc418b782976489f58..480dae5b968c3efe948b438f4a3c27f8a506fbb7 100644 (file)
--- a/board/MAI/AmigaOneG3SE/articiaS_pci.c
+++ b/board/MAI/AmigaOneG3SE/articiaS_pci.c
@@ -26,6 +26,8 @@
 #include "memio.h"
 #include "articiaS.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef ARTICIA_PCI_DEBUG
 
 #ifdef  ARTICIA_PCI_DEBUG
@@ -493,8 +495,6 @@ pci_dev_t video_dev;
 
 int articiaS_init_vga (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
     extern void shutdown_bios(void);
     pci_dev_t dev = ~0;
     int busnr = 0;

diff --git a/board/MAI/AmigaOneG3SE/cmd_boota.c b/board/MAI/AmigaOneG3SE/cmd_boota.c
index 3e2835aaeba5a12554905bdd6c6c73ffee50d03a..143bba2f154099f17837ee4b9875ef1eea4b491e 100644 (file)
--- a/board/MAI/AmigaOneG3SE/cmd_boota.c
+++ b/board/MAI/AmigaOneG3SE/cmd_boota.c
@@ -3,6 +3,7 @@
 #include "../disk/part_amiga.h"
 #include <asm/cache.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 #undef BOOTA_DEBUG
 
@@ -108,8 +109,6 @@ int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
        s = getenv ("autostart");
        if (s && strcmp (s, "yes") == 0) {
-               DECLARE_GLOBAL_DATA_PTR;
-
                void (*boot) (bd_t *, char *, block_dev_desc_t *);
                char *args;
 

diff --git a/board/MAI/AmigaOneG3SE/serial.c b/board/MAI/AmigaOneG3SE/serial.c
index e83fb46c73550f300cae3338b453857df1304103..b6f57c7246bd652cc33ff66159261e1e1ea891cb 100644 (file)
--- a/board/MAI/AmigaOneG3SE/serial.c
+++ b/board/MAI/AmigaOneG3SE/serial.c
@@ -4,6 +4,8 @@
 #include "memio.h"
 #include "articiaS.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CFG_NS16550
 static uint32 ComPort1;
 
@@ -150,8 +152,6 @@ const NS16550_t Com1 = (NS16550_t) CFG_NS16550_COM2;
 
 int serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        uint32 clock_divisor = 115200 / gd->baudrate;
 
        NS16550_init (Com0, clock_divisor);
@@ -239,8 +239,6 @@ void serial_puts (const char *string)
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        uint32 clock_divisor = 115200 / gd->baudrate;
 
        NS16550_init (Com0, clock_divisor);

diff --git a/board/MAI/AmigaOneG3SE/via686.c b/board/MAI/AmigaOneG3SE/via686.c
index c797e47691b9d893ab69388ed9c3e9c2121c6aa1..3606db82e0a7d48d63424a36d98e0051eb853d21 100644 (file)
--- a/board/MAI/AmigaOneG3SE/via686.c
+++ b/board/MAI/AmigaOneG3SE/via686.c
@@ -28,6 +28,8 @@
 #include "via686.h"
 #include "i8259.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef VIA_DEBUG
 
 #ifdef  VIA_DEBUG
@@ -226,33 +228,31 @@ __asm         ("    .globl via_calibrate_time_base \n"
 
 extern unsigned long via_calibrate_time_base(void);
 
-void via_calibrate_bus_freq(void)
+void via_calibrate_bus_freq (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
-    unsigned long tb;
+       unsigned long tb;
 
-    /* This is 20 microseconds */
-    #define CALIBRATE_TIME 28636
+       /* This is 20 microseconds */
+#define CALIBRATE_TIME 28636
 
+       /* Enable the timer (and disable speaker) */
+       unsigned char c;
 
-    /* Enable the timer (and disable speaker) */
-    unsigned char c;
-    c = in_byte(0x61);
-    out_byte(0x61, ((c & ~0x02) | 0x01));
+       c = in_byte (0x61);
+       out_byte (0x61, ((c & ~0x02) | 0x01));
 
-    /* Set timer 2 to low/high writing */
-    out_byte(0x43, 0xb0);
-    out_byte(0x42, CALIBRATE_TIME & 0xff);
-    out_byte(0x42, CALIBRATE_TIME >>8);
+       /* Set timer 2 to low/high writing */
+       out_byte (0x43, 0xb0);
+       out_byte (0x42, CALIBRATE_TIME & 0xff);
+       out_byte (0x42, CALIBRATE_TIME >> 8);
 
-    /* Read the time base */
-    tb = via_calibrate_time_base();
+       /* Read the time base */
+       tb = via_calibrate_time_base ();
 
-    if (tb >= 700000)
-       gd->bus_clk = 133333333;
-    else
-       gd->bus_clk = 100000000;
+       if (tb >= 700000)
+               gd->bus_clk = 133333333;
+       else
+               gd->bus_clk = 100000000;
 
 }
 

diff --git a/board/MAI/AmigaOneG3SE/video.c b/board/MAI/AmigaOneG3SE/video.c
index 36e3c624a982c7f5a3d09a9fa12f33fcb05922ea..f6327f72038c83862c9483b7fd9cd28b54a95aaf 100644 (file)
--- a/board/MAI/AmigaOneG3SE/video.c
+++ b/board/MAI/AmigaOneG3SE/video.c
@@ -26,6 +26,8 @@
 #include "memio.h"
 #include <part.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 unsigned char *cursor_position;
 unsigned int cursor_row;
 unsigned int cursor_col;
@@ -480,7 +482,6 @@ extern char version_string[];
 void video_banner(void)
 {
     block_dev_desc_t *ide;
-    DECLARE_GLOBAL_DATA_PTR;
     int i;
     char *s;
     int maxdev;

diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c
index 9d0d2138e21785d9193e531bad74bbfa7c235ba2..6a1d4d7f5c7632498d013ba92158bce9c4f2f1c3 100644 (file)
--- a/board/Marvell/common/serial.c
+++ b/board/Marvell/common/serial.c
@@ -45,13 +45,13 @@
 
 #include "ns16550.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_MPSC
 
 
 int serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
 #if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
        int clock_divisor = 230400 / gd->baudrate;
 #endif
@@ -88,8 +88,6 @@ int serial_tstc (void)
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
 }
 
@@ -97,8 +95,6 @@ void serial_setbrg (void)
 
 int serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int clock_divisor = 230400 / gd->baudrate;
 
 #ifdef CFG_INIT_CHAN1
@@ -130,8 +126,6 @@ int serial_tstc (void)
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int clock_divisor = 230400 / gd->baudrate;
 
 #ifdef CFG_INIT_CHAN1

diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c
index ccb3adc66c859f1d0ac371a725c94314f012314e..d8acd31953177f765a0941e758236b641030d75e 100644 (file)
--- a/board/Marvell/db64360/mpsc.c
+++ b/board/Marvell/db64360/mpsc.c
@@ -42,6 +42,8 @@
 
 #include "../include/memory.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Define this if you wish to use the MPSC as a register based UART.
  * This will force the serial port to not use the SDMA engine at all.
  */
@@ -114,9 +116,7 @@ static void mpsc_debug_init (void)
 
        /* Clear the CFR  (CHR4) */
        /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
-       temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&".  Assuming "= &"
-
-REG_GAP));
+       temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
        temp &= 0xffffff00;
        temp |= BIT29;
        GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
@@ -158,7 +158,6 @@ char mpsc_getchar_debug (void)
  * global variables [josh] */
 int mpsc_putchar_early (char ch)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int mpsc = CHANNEL;
        int temp =
                GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
@@ -511,7 +510,6 @@ void mpsc_init2 (void)
 
 int galbrg_set_baudrate (int channel, int rate)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int clock;
 
        galbrg_disable (channel);       /*ok */

diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c
index 3c5dee73b7fbdb97ea5031566d66165be489bd03..e5a87ad295208358119effb128bcb1e8c371cd50 100644 (file)
--- a/board/Marvell/db64360/mv_eth.c
+++ b/board/Marvell/db64360/mv_eth.c
@@ -732,6 +732,7 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
        pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;        /* DMA owned, first last */
        pkt_info.byte_cnt = dataSize;
        pkt_info.buf_ptr = (unsigned int) dataPtr;
+       pkt_info.return_info = 0;
 
        status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
        if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {

diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c
index d2635f88ebd63293d90ec1372f6c12c030dfd139..f04aaf9a6edb12f0228187826acc3dd1c4b5d85d 100644 (file)
--- a/board/Marvell/db64360/sdram_init.c
+++ b/board/Marvell/db64360/sdram_init.c
@@ -42,6 +42,8 @@
 #include "64360.h"
 #include "mv_regs.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef DEBUG
 #define MAP_PCI
 
@@ -246,8 +248,6 @@ static inline unsigned short NSto10PS (unsigned char spd_byte)
 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long spd_checksum;
 
 #ifdef ZUMA_NTL

diff --git a/board/Marvell/db64460/mpsc.c b/board/Marvell/db64460/mpsc.c
index 33fbc491626ed22a0a425fc0e66cbb8f9957c8f3..b783aff8d1c585bebc8f7b1afc178879ee70250a 100644 (file)
--- a/board/Marvell/db64460/mpsc.c
+++ b/board/Marvell/db64460/mpsc.c
@@ -42,6 +42,8 @@
 
 #include "../include/memory.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Define this if you wish to use the MPSC as a register based UART.
  * This will force the serial port to not use the SDMA engine at all.
  */
@@ -114,9 +116,7 @@ static void mpsc_debug_init (void)
 
        /* Clear the CFR  (CHR4) */
        /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
-       temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&".  Assuming "= &"
-
-REG_GAP));
+       temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
        temp &= 0xffffff00;
        temp |= BIT29;
        GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
@@ -158,7 +158,6 @@ char mpsc_getchar_debug (void)
  * global variables [josh] */
 int mpsc_putchar_early (char ch)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int mpsc = CHANNEL;
        int temp =
                GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
@@ -511,7 +510,6 @@ void mpsc_init2 (void)
 
 int galbrg_set_baudrate (int channel, int rate)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int clock;
 
        galbrg_disable (channel);       /*ok */

diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c
index ec5d581065c7f6beb9c3838426ca27352829735e..b2c7835a57981a5497540d2a9d8b4e8ab58b69d2 100644 (file)
--- a/board/Marvell/db64460/mv_eth.c
+++ b/board/Marvell/db64460/mv_eth.c
@@ -731,6 +731,7 @@ int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
        pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;        /* DMA owned, first last */
        pkt_info.byte_cnt = dataSize;
        pkt_info.buf_ptr = (unsigned int) dataPtr;
+       pkt_info.return_info = 0;
 
        status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
        if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {

diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c
index 8cfe84c217619367d898dca0deec354f9b8627d7..176220232e5de79e3510a838a6af867d4ce6cd6b 100644 (file)
--- a/board/Marvell/db64460/sdram_init.c
+++ b/board/Marvell/db64460/sdram_init.c
@@ -42,6 +42,8 @@
 #include "64460.h"
 #include "mv_regs.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef DEBUG
 #define        MAP_PCI
 
@@ -246,8 +248,6 @@ static inline unsigned short NSto10PS (unsigned char spd_byte)
 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long spd_checksum;
 
 #ifdef ZUMA_NTL

diff --git a/board/adder/adder.c b/board/adder/adder.c
index cab6e2f66aaf1f91adf0dff7702f725aa20587ef..aa7815848c8e8085b4fe589bee31e1036d75fb9f 100644 (file)
--- a/board/adder/adder.c
+++ b/board/adder/adder.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004 Arabella Software Ltd.
+ * Copyright (C) 2004-2005 Arabella Software Ltd.
  * Yuli Barcohen <yuli@arabellasw.com>
  *
  * Support for Analogue&Micro Adder boards family.
@@ -28,7 +28,8 @@
 #include <mpc8xx.h>
 
 /*
- * SDRAM is single Samsung K4S643232F-T70 chip.
+ * SDRAM is single Samsung K4S643232F-T70   chip (8MB)
+ *       or single Micron  MT48LC4M32B2TG-7 chip (16MB).
  * Minimal CPU frequency is 40MHz.
  */
 static uint sdram_table[] = {
@@ -53,7 +54,7 @@ static uint sdram_table[] = {
        0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
 
        /* Refresh      (offset 0x30 in UPM RAM) */
-       0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+       0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
        0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
        0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
 
@@ -63,7 +64,7 @@ static uint sdram_table[] = {
 
 long int initdram (int board_type)
 {
-       long int msize = CFG_SDRAM_SIZE;
+       long int msize;
        volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
 
@@ -72,11 +73,11 @@ long int initdram (int board_type)
        /* Configure SDRAM refresh */
        memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
 
-       memctl->memc_mamr = (94 << 24) | CFG_MAMR;
-       memctl->memc_mar  = 0x0;
+       memctl->memc_mamr = (94 << 24) | CFG_MAMR; /* No refresh */
        udelay(200);
 
        /* Run precharge from location 0x15 */
+       memctl->memc_mar = 0x0;
        memctl->memc_mcr = 0x80002115;
        udelay(200);
 
@@ -84,13 +85,18 @@ long int initdram (int board_type)
        memctl->memc_mcr = 0x80002830;
        udelay(200);
 
-       memctl->memc_mar = 0x88;
-       udelay(200);
-
        /* Run MRS pattern from location 0x16 */
+       memctl->memc_mar = 0x88;
        memctl->memc_mcr = 0x80002116;
        udelay(200);
 
+       memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
+       memctl->memc_or1   = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
+       memctl->memc_br1   =  CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
+
+       msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
+       memctl->memc_or1  |= ~(msize - 1);
+
        return msize;
 }
 

diff --git a/board/adsvix/adsvix.c b/board/adsvix/adsvix.c
index 5e770e9493d2649ae2f2595151d7c242031cb8ff..c430d634e12f9cf4aa09dc2748aa7d79ab8fa8b2 100644 (file)
--- a/board/adsvix/adsvix.c
+++ b/board/adsvix/adsvix.c
@@ -30,6 +30,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 /*
@@ -38,8 +40,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* memory and cpu-speed are setup before relocation */
        /* so we do _nothing_ here */
 
@@ -62,8 +62,6 @@ int board_late_init(void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 803995ae5d0645d24d38b91296e8a5556d5c1b85..7c989200fe18f0a5500ec79989eee6fc0103ccdf 100644 (file)
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -277,7 +277,7 @@ int board_early_init_f(void)
 }
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 
 /*----------------------------------------------------------------------------+

diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index a2595eec520e82c94af18edaead7beeb975ba567..dcafac950d67bcf96ca35828f8c0e2e11131f883 100644 (file)
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -28,6 +28,8 @@
 #define FLASH_ONBD_N           2       /* 00000010 */
 #define FLASH_SRAM_SEL         1       /* 00000001 */
 
+DECLARE_GLOBAL_DATA_PTR;
+
 long int fixed_sdram(void);
 
 int board_early_init_f(void)
@@ -107,7 +109,7 @@ long int initdram(int board_type)
        long dram_size = 0;
 
 #if defined(CONFIG_SPD_EEPROM)
-       dram_size = spd_sdram(0);
+       dram_size = spd_sdram();
 #else
        dram_size = fixed_sdram();
 #endif
@@ -235,8 +237,6 @@ int pci_pre_init(struct pci_controller *hose)
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/

diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index c6b79a9f5ffdabd6f60788613e2cf632835e3527..06a57f6c4aac3c8b2df8282b764d50b9901b5a5b 100644 (file)
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -28,6 +28,7 @@
 #include <spd_sdram.h>
 #include "epld.h"
 
+DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
@@ -291,8 +292,6 @@ int pci_pre_init( struct pci_controller *hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/

diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index d1a29c52a513787b4f48f1365dd2153d682c7aaa..3f6d2042d72150b39a4a157a1dcb9050f6f6a216 100644 (file)
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -30,6 +30,8 @@
 #include <spd_sdram.h>
 #include <ppc4xx_enet.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define BOOT_SMALL_FLASH       32      /* 00100000 */
 #define FLASH_ONBD_N           2       /* 00000010 */
 #define FLASH_SRAM_SEL         1       /* 00000001 */
@@ -204,7 +206,7 @@ long int initdram (int board_type)
        long dram_size = 0;
 
 #if defined(CONFIG_SPD_EEPROM)
-       dram_size = spd_sdram (0);
+       dram_size = spd_sdram ();
 #else
        dram_size = fixed_sdram ();
 #endif
@@ -334,8 +336,6 @@ int pci_pre_init(struct pci_controller * hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/

diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c
index f1a96a6e7d23a9c90209ccb7caa66d32b74548ef..292e02609e2380847ef92e2493d6b4dab4ff144b 100644 (file)
--- a/board/amcc/walnut/walnut.c
+++ b/board/amcc/walnut/walnut.c
@@ -99,7 +99,7 @@ void sdram_init(void)
  */
 long int initdram(int board_type)
 {
-       return spd_sdram(0);
+       return spd_sdram();
 }
 
 int testdram(void)

diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c
index 8ddf910c8e4e37264ab8e4f292bc9abb3da241f1..20965c8e3ead7e039b17eb289f5e864af425e6ea 100644 (file)
--- a/board/amcc/yellowstone/yellowstone.c
+++ b/board/amcc/yellowstone/yellowstone.c
@@ -24,6 +24,8 @@
 #include <asm/processor.h>
 #include <spd_sdram.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips   */
 
 int board_early_init_f(void)
@@ -136,7 +138,6 @@ int board_early_init_f(void)
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        uint pbcr;
        int size_val = 0;
 

diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 509d8e4cce422daa8c23f09dd2efe734a94f53da..392d0dc34e40b07077916d717cb41d22e4232827 100644 (file)
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -24,6 +24,8 @@
 #include <asm/processor.h>
 #include <spd_sdram.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips   */
 
 int board_early_init_f(void)
@@ -132,7 +134,6 @@ int board_early_init_f(void)
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        uint pbcr;
        int size_val = 0;
 

diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c
index dd836ce221d9c541696e504e0c1dd00ed5d2af69..7d11b29b59ab714775953d7a092f424d0b17400c 100644 (file)
--- a/board/amirix/ap1000/ap1000.c
+++ b/board/amirix/ap1000/ap1000.c
@@ -36,8 +36,8 @@ int board_pre_init (void)
 /** serial number and platform display at startup */
 int checkboard (void)
 {
-       unsigned char *s = getenv ("serial#");
-       unsigned char *e;
+       char *s = getenv ("serial#");
+       char *e;
 
        /* After a loadace command, the SystemAce control register is left in a wonky state. */
        /* this code did not work in board_pre_init */
@@ -135,13 +135,13 @@ int checkboard (void)
 
 long int initdram (int board_type)
 {
-       unsigned char *s = getenv ("dramsize");
+       char *s = getenv ("dramsize");
 
        if (s != NULL) {
                if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) {
                        s += 2;
                }
-               return simple_strtoul (s, NULL, 16);
+               return (long int)simple_strtoul (s, NULL, 16);
        } else {
                /* give all 64 MB */
                return 64 * 1024 * 1024;
@@ -293,7 +293,7 @@ int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
        printf ("Writing to Flash... ");
        write_result =
-               flash_write (sector_buffer, SW_BYTE_SECTOR_ADDR,
+               flash_write ((char *)sector_buffer, SW_BYTE_SECTOR_ADDR,
                             SW_BYTE_SECTOR_SIZE);
        if (write_result != 0) {
                flash_perror (write_result);

diff --git a/board/amirix/ap1000/serial.c b/board/amirix/ap1000/serial.c
index 39c415792592e91157adc6eeee57ac464d9af091..c6ee7728129db67f0cfa3dab0b3b5fcb8019ebc8 100644 (file)
--- a/board/amirix/ap1000/serial.c
+++ b/board/amirix/ap1000/serial.c
@@ -27,9 +27,7 @@
 
 #include <ns16550.h>
 
-#if 0
-#include "serial.h"
-#endif
+DECLARE_GLOBAL_DATA_PTR;
 
 const NS16550_t COM_PORTS[] =
        { (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 };
@@ -40,8 +38,6 @@ static int gComPort = 0;
 
 int serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
 
        (void) NS16550_init (COM_PORTS[0], clock_divisor);
@@ -71,8 +67,6 @@ int serial_tstc (void)
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
 
 #ifdef CFG_INIT_CHAN1

diff --git a/board/armadillo/armadillo.c b/board/armadillo/armadillo.c
index de04c66385462bdfb6e9066df5000765a4d1b936..ca5bd1d1640403de06d81afbd88f854ebfb21492 100644 (file)
--- a/board/armadillo/armadillo.c
+++ b/board/armadillo/armadillo.c
@@ -28,6 +28,8 @@
 #include <common.h>
 #include <clps7111.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 
@@ -37,8 +39,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Activate LED flasher */
        IO_LEDFLSH = 0x40;
 
@@ -53,8 +53,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/assabet/assabet.c b/board/assabet/assabet.c
index d3ccbb536763453e669a43949fa49d0049dcbcd4..4f84a58117b6a6069a4278326fa823d240c7c71f 100644 (file)
--- a/board/assabet/assabet.c
+++ b/board/assabet/assabet.c
@@ -27,6 +27,8 @@
 #include <common.h>
 #include <SA-1100.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 /*
@@ -99,8 +101,6 @@ neponset_init(void)
 int
 board_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_arch_number = MACH_TYPE_ASSABET;
        gd->bd->bi_boot_params = 0xc0000100;
 
@@ -112,8 +112,6 @@ board_init(void)
 int
 dram_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/at91rm9200dk/at45.c b/board/at91rm9200dk/at45.c
index 3c0013216436433d439c67101fdbe4e549987b89..f886fe482010caaa507875a62963f25c188aec5e 100644 (file)
--- a/board/at91rm9200dk/at45.c
+++ b/board/at91rm9200dk/at45.c
@@ -593,7 +593,7 @@ int AT91F_DataFlashRead(
                if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
                        return -1;
 
-               if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK)
+               if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (uchar *)buffer, SizeToRead) != DATAFLASH_OK)
                        return -1;
 
                size -= SizeToRead;

diff --git a/board/at91rm9200dk/at91rm9200dk.c b/board/at91rm9200dk/at91rm9200dk.c
index 90167768539174d40dae3f14d21d64b0781402cc..002981a762481e01cd3ce1816946d13c9bebdd13 100644 (file)
--- a/board/at91rm9200dk/at91rm9200dk.c
+++ b/board/at91rm9200dk/at91rm9200dk.c
@@ -27,6 +27,8 @@
 #include <at91rm9200_net.h>
 #include <dm9161.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 /*
  * Miscelaneous platform dependent initialisations
@@ -34,8 +36,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Enable Ctrlc */
        console_init_f ();
 
@@ -56,8 +56,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
        return 0;

diff --git a/board/at91rm9200dk/flash.c b/board/at91rm9200dk/flash.c
index f6228ef03e4511de21daec2b6a62c72c4220a299..0513d61d73f2df9d211c39bbf0e2b481e85aef57 100644 (file)
--- a/board/at91rm9200dk/flash.c
+++ b/board/at91rm9200dk/flash.c
@@ -393,8 +393,7 @@ outahere:
  * Copy memory to flash
  */
 
-volatile static int write_word (flash_info_t * info, ulong dest,
-                                                               ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
        volatile u16 *addr = (volatile u16 *) dest;
        ulong result;
@@ -409,7 +408,6 @@ volatile static int write_word (flash_info_t * info, ulong dest,
        if ((result & data) != data)
                return ERR_NOT_ERASED;
 
-
        /*
         * Disable interrupts which might cause a timeout
         * here. Remember that our exception vectors are

diff --git a/board/bc3450/Makefile b/board/bc3450/Makefile
new file mode 100644 (file)
index 0000000..4dec44f
--- /dev/null
+++ b/board/bc3450/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   := $(BOARD).o cmd_bc3450.o
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c
new file mode 100644 (file)
index 0000000..a030b82
--- /dev/null
+++ b/board/bc3450/bc3450.c
@@ -0,0 +1,677 @@
+/*
+ * -- Version 1.1 --
+ *
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * (C) Copyright 2006
+ * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
+ *
+ * History:
+ *     1.1 - improved SM501 init to meet spec timing
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#ifdef CONFIG_VIDEO_SM501
+#include <sm501.h>
+#endif
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+#ifdef CONFIG_RTC_MPC5200
+#include <rtc.h>
+#endif 
+
+#ifdef CONFIG_PS2MULT
+void ps2mult_early_init(void);
+#endif
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+       long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+       /* unlock mode register */
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
+               hi_addr_bit;
+       __asm__ volatile ("sync");
+
+       /* precharge all banks */
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+               hi_addr_bit;
+       __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+       /* set mode register: extended mode */
+       *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+       __asm__ volatile ("sync");
+
+       /* set mode register: reset DLL */
+       *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+       __asm__ volatile ("sync");
+#endif
+
+       /* precharge all banks */
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+               hi_addr_bit;
+       __asm__ volatile ("sync");
+
+       /* auto refresh */
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+               hi_addr_bit;
+       __asm__ volatile ("sync");
+
+       /* set mode register */
+       *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+       __asm__ volatile ("sync");
+
+       /* normal operation */
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+       __asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *           use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *           is something else than 0x00000000.
+ */
+
+#if defined(CONFIG_MPC5200)
+long int initdram (int board_type)
+{
+       ulong dramsize = 0;
+       ulong dramsize2 = 0;
+#ifndef CFG_RAMBOOT
+       ulong test1, test2;
+
+       /* setup SDRAM chip selects */
+       *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
+       *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
+       __asm__ volatile ("sync");
+
+       /* setup config registers */
+       *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+       *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+       __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+       /* set tap delay */
+       *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+       __asm__ volatile ("sync");
+#endif
+
+       /* find RAM size using SDRAM CS0 only */
+       sdram_start(0);
+       test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+       sdram_start(1);
+       test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+       if (test1 > test2) {
+               sdram_start(0);
+               dramsize = test1;
+       } else {
+               dramsize = test2;
+       }
+
+       /* memory smaller than 1MB is impossible */
+       if (dramsize < (1 << 20)) {
+               dramsize = 0;
+       }
+
+       /* set SDRAM CS0 size according to the amount of RAM found */
+       if (dramsize > 0) {
+               *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+                       __builtin_ffs(dramsize >> 20) - 1;
+       } else {
+               *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+       }
+
+       /* let SDRAM CS1 start right after CS0 */
+       *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
+
+       /* find RAM size using SDRAM CS1 only */
+       sdram_start(0);
+       test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+       sdram_start(1);
+       test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+       if (test1 > test2) {
+               sdram_start(0);
+               dramsize2 = test1;
+       } else {
+               dramsize2 = test2;
+       }
+
+       /* memory smaller than 1MB is impossible */
+       if (dramsize2 < (1 << 20)) {
+               dramsize2 = 0;
+       }
+
+       /* set SDRAM CS1 size according to the amount of RAM found */
+       if (dramsize2 > 0) {
+               *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+                       | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+       } else {
+               *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+       }
+
+#else /* CFG_RAMBOOT */
+
+       /* retrieve size of memory connected to SDRAM CS0 */
+       dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+       if (dramsize >= 0x13) {
+               dramsize = (1 << (dramsize - 0x13)) << 20;
+       } else {
+               dramsize = 0;
+       }
+
+       /* retrieve size of memory connected to SDRAM CS1 */
+       dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+       if (dramsize2 >= 0x13) {
+               dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+       } else {
+               dramsize2 = 0;
+       }
+
+#endif /* CFG_RAMBOOT */
+
+       return dramsize;
+}
+
+#elif defined(CONFIG_MGT5100)
+
+long int initdram (int board_type)
+{
+       ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+       ulong test1, test2;
+
+       /* setup and enable SDRAM chip selects */
+       *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+       *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;    /* 2G           */
+       *(vu_long *)MPC5XXX_ADDECR |= (1 << 22);        /* Enable SDRAM */
+       __asm__ volatile ("sync");
+
+       /* setup config registers */
+       *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+       *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+       /* address select register */
+       *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
+       __asm__ volatile ("sync");
+
+       /* find RAM size */
+       sdram_start(0);
+       test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+       sdram_start(1);
+       test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+       if (test1 > test2) {
+               sdram_start(0);
+               dramsize = test1;
+       } else {
+               dramsize = test2;
+       }
+
+       /* set SDRAM end address according to size */
+       *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+
+#else /* CFG_RAMBOOT */
+
+       /* Retrieve amount of SDRAM available */
+       dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+
+#endif /* CFG_RAMBOOT */
+
+       return dramsize;
+}
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
+
+int checkboard (void)
+{
+#if defined (CONFIG_TQM5200)
+       puts ("Board: TQM5200 (TQ-Components GmbH)\n");
+#endif
+
+#if defined (CONFIG_BC3450)
+       puts ("Dev:   GERSYS BC3450\n");
+#endif
+
+       return 0;
+}
+
+void flash_preinit(void)
+{
+       /*
+        * Now, when we are in RAM, enable flash write
+        * access for detection process.
+        * Note that CS_BOOT cannot be cleared when
+        * executing in flash.
+        */
+#if defined(CONFIG_MGT5100)
+       *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);       /* disable CS_BOOT */
+       *(vu_long *)MPC5XXX_ADDECR |= (1 << 16);        /* enable CS0      */
+#endif
+       *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1;         /* clear RO        */
+}
+
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+       pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+#define GPIO_PSC1_4    0x01000000UL
+
+void init_ide_reset (void)
+{
+       debug ("init_ide_reset\n");
+
+       /* Configure PSC1_4 as GPIO output for ATA reset */
+       *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+       *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+       debug ("ide_reset(%d)\n", idereset);
+
+       if (idereset) {
+               *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+       } else {
+               *(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
+       }
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#ifdef CONFIG_POST
+/*
+ * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
+ * is left open, no keypress is detected.
+ */
+int post_hotkeys_pressed(void)
+{
+       struct mpc5xxx_gpio *gpio;
+
+       gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
+
+       /*
+        * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
+        * CODEC or UART mode. Consumer IrDA should still be possible.
+        */
+       gpio->port_config &= ~(0x07000000);
+       gpio->port_config |=   0x03000000;
+
+       /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
+       gpio->simple_gpioe |= 0x20000000;
+
+       /* Configure GPIO_IRDA_1 as input */
+       gpio->simple_ddr &= ~(0x20000000);
+
+       return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
+}
+#endif
+
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+
+void post_word_store (ulong a)
+{
+       volatile ulong *save_addr =
+               (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
+
+       *save_addr = a;
+}
+
+ulong post_word_load (void)
+{
+       volatile ulong *save_addr =
+               (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
+
+       return *save_addr;
+}
+#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
+
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+#ifdef CONFIG_RTC_MPC5200
+        struct rtc_time t;
+
+       /* set to Wed Dec 31 19:00:00 1969 */
+       t.tm_sec = t.tm_min = 0;
+       t.tm_hour = 19;
+       t.tm_mday = 31;
+       t.tm_mon = 12;
+       t.tm_year = 1969;
+       t.tm_wday = 3;
+       
+       rtc_set(&t);
+#endif /* CONFIG_RTC_MPC5200 */
+
+#ifdef CONFIG_PS2MULT
+       ps2mult_early_init();
+#endif /* CONFIG_PS2MULT */
+       return (0);
+}
+#endif /* CONFIG_BOARD_EARLY_INIT_R */
+
+
+int last_stage_init (void)
+{
+       /*
+        * auto scan for really existing devices and re-set chip select
+        * configuration.
+        */
+       u16 save, tmp;
+       int restore;
+
+       /*
+        * Check for SRAM and SRAM size
+        */
+
+       /* save original SRAM content  */
+       save = *(volatile u16 *)CFG_CS2_START;
+       restore = 1;
+
+       /* write test pattern to SRAM */
+       *(volatile u16 *)CFG_CS2_START = 0xA5A5;
+       __asm__ volatile ("sync");
+       /*
+        * Put a different pattern on the data lines: otherwise they may float
+        * long enough to read back what we wrote.
+        */
+       tmp = *(volatile u16 *)CFG_FLASH_BASE;
+       if (tmp == 0xA5A5)
+               puts ("!! possible error in SRAM detection\n");
+
+       if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
+               /* no SRAM at all, disable cs */
+               *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
+               *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
+               *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
+               restore = 0;
+               __asm__ volatile ("sync");
+       } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
+               /* make sure that we access a mirrored address */
+               *(volatile u16 *)CFG_CS2_START = 0x1111;
+               __asm__ volatile ("sync");
+               if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
+                       /* SRAM size = 512 kByte */
+                       *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
+                                                               0x80000);
+                       __asm__ volatile ("sync");
+                       puts ("SRAM:  512 kB\n");
+               }
+               else
+                       puts ("!! possible error in SRAM detection\n");
+       } else {
+               puts ("SRAM:  1 MB\n");
+       }
+       /* restore origianl SRAM content  */
+       if (restore) {
+               *(volatile u16 *)CFG_CS2_START = save;
+               __asm__ volatile ("sync");
+       }
+
+       /*
+        * Check for Grafic Controller
+        */
+
+       /* save origianl FB content  */
+       save = *(volatile u16 *)CFG_CS1_START;
+       restore = 1;
+
+       /* write test pattern to FB memory */
+       *(volatile u16 *)CFG_CS1_START = 0xA5A5;
+       __asm__ volatile ("sync");
+       /*
+        * Put a different pattern on the data lines: otherwise they may float
+        * long enough to read back what we wrote.
+        */
+       tmp = *(volatile u16 *)CFG_FLASH_BASE;
+       if (tmp == 0xA5A5)
+               puts ("!! possible error in grafic controller detection\n");
+
+       if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
+               /* no grafic controller at all, disable cs */
+               *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
+               *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
+               *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
+               restore = 0;
+               __asm__ volatile ("sync");
+       } else {
+               puts ("VGA:   SMI501 (Voyager) with 8 MB\n");
+       }
+       /* restore origianl FB content  */
+       if (restore) {
+               *(volatile u16 *)CFG_CS1_START = save;
+               __asm__ volatile ("sync");
+       }
+
+       return 0;
+}
+
+#ifdef CONFIG_VIDEO_SM501
+
+#define DISPLAY_WIDTH   640
+#define DISPLAY_HEIGHT  480
+
+#ifdef CONFIG_VIDEO_SM501_8BPP
+#error CONFIG_VIDEO_SM501_8BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_8BPP */
+
+#ifdef CONFIG_VIDEO_SM501_16BPP
+#error CONFIG_VIDEO_SM501_16BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_16BPP */
+
+#ifdef CONFIG_VIDEO_SM501_32BPP
+static const SMI_REGS init_regs [] =
+{
+#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
+       /* FP only */
+       {0x00004, 0x0},
+       {0x00048, 0x00021807},
+       {0x0004C, 0x091a0a01},
+       {0x00054, 0x1},
+       {0x00040, 0x00021807},
+       {0x00044, 0x091a0a01},
+       {0x00054, 0x0},
+       {0x80000, 0x01013106},
+       {0x80004, 0xc428bb17},
+       {0x80000, 0x03013106},
+       {0x8000C, 0x00000000},
+       {0x80010, 0x0a000a00},
+       {0x80014, 0x02800000},
+       {0x80018, 0x01e00000},
+       {0x8001C, 0x00000000},
+       {0x80020, 0x01e00280},
+       {0x80024, 0x02fa027f},
+       {0x80028, 0x004a028b},
+       {0x8002C, 0x020c01df},
+       {0x80030, 0x000201e9},
+       {0x80200, 0x00010200},
+       {0x80000, 0x0f013106},
+#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
+       /* CRT only */
+       {0x00004, 0x0},
+       {0x00048, 0x00021807},
+       {0x0004C, 0x10090a01},
+       {0x00054, 0x1},
+       {0x00040, 0x00021807},
+       {0x00044, 0x10090a01},
+       {0x00054, 0x0},
+       {0x80200, 0x00010000},
+       {0x80204, 0x0},
+       {0x80208, 0x0A000A00},
+       {0x8020C, 0x02fa027f},
+       {0x80210, 0x004a028b},
+       {0x80214, 0x020c01df},
+       {0x80218, 0x000201e9},
+       {0x80200, 0x00013306},
+#else  /* panel + CRT */
+       {0x00004, 0x0},
+       {0x00048, 0x00021807},
+       {0x0004C, 0x091a0a01},
+       {0x00054, 0x1},
+       {0x00040, 0x00021807},
+       {0x00044, 0x091a0a01},
+       {0x00054, 0x0},
+       {0x80000, 0x0f013106},
+       {0x80004, 0xc428bb17},
+       {0x8000C, 0x00000000},
+       {0x80010, 0x0a000a00},
+       {0x80014, 0x02800000},
+       {0x80018, 0x01e00000},
+       {0x8001C, 0x00000000},
+       {0x80020, 0x01e00280},
+       {0x80024, 0x02fa027f},
+       {0x80028, 0x004a028b},
+       {0x8002C, 0x020c01df},
+       {0x80030, 0x000201e9},
+       {0x80200, 0x00010000},
+#endif
+       {0, 0}
+};
+#endif /* CONFIG_VIDEO_SM501_32BPP */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+       if (line_number == 1) {
+#if defined (CONFIG_TQM5200)
+           strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
+#else
+#error No supported board selected
+#endif /* CONFIG_TQM5200 */
+
+#if defined (CONFIG_BC3450)
+       } else if (line_number == 2) {
+           strcpy (info, " Dev:   GERSYS BC3450");
+#endif /* CONFIG_BC3450 */
+       }
+       else {
+               info [0] = '\0';
+       }
+}
+#endif
+
+/*
+ * Returns SM501 register base address. First thing called in the
+ * driver. Checks if SM501 is physically present.
+ */
+unsigned int board_video_init (void)
+{
+       u16 save, tmp;
+       int restore, ret;
+
+       /*
+        * Check for Grafic Controller
+        */
+
+       /* save origianl FB content  */
+       save = *(volatile u16 *)CFG_CS1_START;
+       restore = 1;
+
+       /* write test pattern to FB memory */
+       *(volatile u16 *)CFG_CS1_START = 0xA5A5;
+       __asm__ volatile ("sync");
+       /*
+        * Put a different pattern on the data lines: otherwise they may float
+        * long enough to read back what we wrote.
+        */
+       tmp = *(volatile u16 *)CFG_FLASH_BASE;
+       if (tmp == 0xA5A5)
+               puts ("!! possible error in grafic controller detection\n");
+
+       if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
+               /* no grafic controller found */
+               restore = 0;
+               ret = 0;
+       } else {
+           ret = SM501_MMIO_BASE;
+       }
+       
+       if (restore) {
+               *(volatile u16 *)CFG_CS1_START = save;
+               __asm__ volatile ("sync");
+       }
+       return ret;
+}
+
+/*
+ * Returns SM501 framebuffer address
+ */
+unsigned int board_video_get_fb (void)
+{
+       return SM501_FB_BASE;
+}
+
+/*
+ * Called after initializing the SM501 and before clearing the screen.
+ */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/*
+ * Return a pointer to the initialization sequence.
+ */
+const SMI_REGS *board_get_regs (void)
+{
+       return init_regs;
+}
+
+int board_get_width (void)
+{
+       return DISPLAY_WIDTH;
+}
+
+int board_get_height (void)
+{
+       return DISPLAY_HEIGHT;
+}
+
+#endif /* CONFIG_VIDEO_SM501 */

diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c
new file mode 100644 (file)
index 0000000..1442b68
--- /dev/null
+++ b/board/bc3450/cmd_bc3450.c
@@ -0,0 +1,813 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
+ *
+ * (C) Copyright 2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+/* 
+ * BC3450 specific commands
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+#undef DEBUG
+#ifdef DEBUG
+# define dprintf(fmt,args...)  printf(fmt, ##args)
+#else
+# define dprintf(fmt,args...)
+#endif
+
+/* 
+ * Definitions for DS1620 chip
+ */
+#define THERM_START_CONVERT    0xee
+#define THERM_RESET            0xaf
+#define THERM_READ_CONFIG      0xac
+#define THERM_READ_TEMP                0xaa
+#define THERM_READ_TL          0xa2
+#define THERM_READ_TH          0xa1
+#define THERM_WRITE_CONFIG     0x0c
+#define THERM_WRITE_TL         0x02
+#define THERM_WRITE_TH         0x01
+
+#define CFG_CPU                        2
+#define CFG_1SHOT              1
+#define CFG_STANDALONE         0
+
+struct therm {
+    int hi;
+    int lo;
+};
+
+/*
+ * SM501 Register
+ */
+#define SM501_GPIO_CTRL_LOW            0x00000008UL    /* gpio pins 0..31  */
+#define SM501_GPIO_CTRL_HIGH           0x0000000CUL    /* gpio pins 32..63 */
+#define SM501_POWER_MODE0_GATE         0x00000040UL
+#define SM501_POWER_MODE1_GATE         0x00000048UL
+#define POWER_MODE_GATE_GPIO_PWM_I2C   0x00000040UL
+#define SM501_GPIO_DATA_LOW            0x00010000UL
+#define SM501_GPIO_DATA_HIGH           0x00010004UL
+#define SM501_GPIO_DATA_DIR_LOW                0x00010008UL
+#define SM501_GPIO_DATA_DIR_HIGH       0x0001000CUL
+#define SM501_PANEL_DISPLAY_CONTROL    0x00080000UL
+#define SM501_CRT_DISPLAY_CONTROL      0x00080200UL
+
+/* SM501 CRT Display Control Bits */
+#define SM501_CDC_SEL                  (1 << 9)
+#define SM501_CDC_TE                   (1 << 8)
+#define SM501_CDC_E                    (1 << 2)
+
+/* SM501 Panel Display Control Bits */
+#define SM501_PDC_FPEN                 (1 << 27)
+#define SM501_PDC_BIAS                 (1 << 26)
+#define SM501_PDC_DATA                 (1 << 25)
+#define SM501_PDC_VDDEN                        (1 << 24)
+
+/* SM501 GPIO Data LOW Bits */
+#define SM501_GPIO24                   0x01000000
+#define SM501_GPIO25                   0x02000000
+#define SM501_GPIO26                   0x04000000
+#define SM501_GPIO27                   0x08000000
+#define SM501_GPIO28                   0x10000000
+#define SM501_GPIO29                   0x20000000
+#define SM501_GPIO30                   0x40000000
+#define SM501_GPIO31                   0x80000000
+
+/* SM501 GPIO Data HIGH Bits */
+#define SM501_GPIO46                   0x00004000
+#define SM501_GPIO47                   0x00008000
+#define SM501_GPIO48                   0x00010000
+#define SM501_GPIO49                   0x00020000
+#define SM501_GPIO50                   0x00040000
+#define SM501_GPIO51                   0x00080000
+
+/* BC3450 GPIOs @ SM501 Data LOW */
+#define DIP                            (SM501_GPIO24 | SM501_GPIO25 | SM501_GPIO26 | SM501_GPIO27)
+#define DS1620_DQ                      SM501_GPIO29    /* I/O             */
+#define DS1620_CLK                     SM501_GPIO30    /* High active O/P */
+#define DS1620_RES                     SM501_GPIO31    /* Low active O/P  */
+/* BC3450 GPIOs @ SM501 Data HIGH */
+#define BUZZER                         SM501_GPIO47    /* Low active O/P  */
+#define DS1620_TLOW                    SM501_GPIO48    /* High active I/P */
+#define PWR_OFF                                SM501_GPIO49    /* Low active O/P  */
+#define FP_DATA_TRI                    SM501_GPIO50    /* High active O/P */
+
+
+/*
+ * Initialise GPIO on SM501
+ *
+ * This function may be called from several other functions.
+ * Yet, the initialisation sequence is executed only the first
+ * time the function is called.
+ */
+int sm501_gpio_init(void)
+{
+    static int init_done = 0;
+
+    if(init_done) {
+/*     dprintf("sm501_gpio_init: nothing to be done.\n"); */
+       return 1;
+    }
+
+    /* enable SM501 GPIO control (in both power modes) */
+    *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE0_GATE) |= POWER_MODE_GATE_GPIO_PWM_I2C;
+    *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE1_GATE) |= POWER_MODE_GATE_GPIO_PWM_I2C;
+
+    /* set up default O/Ps */
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~(DS1620_RES | DS1620_CLK);
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ;
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= ~(FP_DATA_TRI);
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |= (BUZZER | PWR_OFF);
+
+    /* configure directions for SM501 GPIO pins */
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_LOW) &= ~(0xFF << 24);
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_HIGH) &= ~(0x3F << 14);
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~(DIP | DS1620_DQ);
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= (DS1620_RES | DS1620_CLK);
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) &= ~DS1620_TLOW;
+    *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) |= (PWR_OFF | BUZZER | FP_DATA_TRI);
+
+    init_done = 1;
+/*  dprintf("sm501_gpio_init: done.\n"); */
+    return 0;
+}
+
+
+/*
+ * dip - read Config Inputs
+ *
+ * read and prints the dip switch
+ * and/or external config inputs (4bits) 0...0x0F
+ */
+int cmd_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+    vu_long rc = 0;
+
+    sm501_gpio_init();
+
+    /* read dip switch */
+    rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
+    rc = ~rc;
+    rc &= DIP;
+    rc = (int)(rc >> 24);
+
+    /* plausibility check */
+    if (rc > 0x0F)
+       return -1;
+
+    printf ("0x%x\n", rc);
+    return 0;
+}
+
+U_BOOT_CMD(
+       dip ,   1,      1,      cmd_dip,
+       "dip     - read dip switch and config inputs\n",
+       "\n"
+       "     - prints the state of the dip switch and/or\n"
+       "       external configuration inputs as hex value.\n"
+       "     - \"Config 1\" is the LSB\n"
+    );
+
+
+/*
+ * buz - turns Buzzer on/off
+ */
+#ifdef CONFIG_BC3450_BUZZER
+static int cmd_buz (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+    if (argc != 2) {
+       printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
+       return 1;
+    }
+
+    sm501_gpio_init();
+
+    if (strncmp (argv[1], "on", 2) == 0) {
+       *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= ~(BUZZER);
+       return 0;
+    }
+    else if (strncmp (argv[1], "off", 3) == 0) {
+       *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |= BUZZER;
+       return 0;
+    }
+    printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
+    return 1;
+}
+
+U_BOOT_CMD(
+       buz ,   2,      1,      cmd_buz,
+       "buz     - turns buzzer on/off\n",
+       "\n"
+       "buz <on/off>\n"
+       "     - turns the buzzer on or off\n"
+    );
+#endif /* CONFIG_BC3450_BUZZER */
+
+
+/*
+ * fp - front panel commands
+ */
+static int cmd_fp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+    sm501_gpio_init();
+
+    if (strncmp (argv[1], "on", 2) == 0) {
+       /* turn on VDD first */
+       *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_VDDEN;
+       udelay(1000);
+       /* then put data on */
+       *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_DATA;
+       /* wait some time and enable backlight */
+       udelay(1000);
+       *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS;
+       udelay(1000);
+       *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN;
+       return 0;
+    }
+    else if (strncmp (argv[1], "off", 3) == 0) {
+       /* turn off the backlight first */
+       *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN;
+       udelay(1000);
+       *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS;
+       udelay(200000);
+       /* wait some time, then remove data */
+       *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_DATA;
+       udelay(1000);
+       /* and remove VDD last */
+       *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_VDDEN;
+       return 0;
+    }
+    else if (strncmp (argv[1], "bl", 2) == 0) {
+       /* turn on/off backlight only */
+       if (strncmp (argv[2], "on", 2) == 0) {
+           *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS;
+           udelay(1000);
+           *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN;
+           return 0;
+       }
+       else if (strncmp (argv[2], "off", 3) == 0) {
+           *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN;
+           udelay(1000);
+           *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS;
+           return 0;
+       }
+    }
+#ifdef CONFIG_BC3450_CRT
+    else if (strncmp (argv[1], "crt", 3) == 0) {
+       /* enables/disables the crt output (debug only) */
+       if(strncmp (argv[2], "on", 2) == 0) {
+           *(vu_long *)(SM501_MMIO_BASE + SM501_CRT_DISPLAY_CONTROL) |= 
+               (SM501_CDC_TE | SM501_CDC_E);
+           *(vu_long *)(SM501_MMIO_BASE + SM501_CRT_DISPLAY_CONTROL) &= 
+               ~SM501_CDC_SEL;
+           return 0;
+       }
+       else if (strncmp (argv[2], "off", 3) == 0) {
+           *(vu_long *)(SM501_MMIO_BASE + SM501_CRT_DISPLAY_CONTROL) &= 
+               ~(SM501_CDC_TE | SM501_CDC_E);
+           *(vu_long *)(SM501_MMIO_BASE + SM501_CRT_DISPLAY_CONTROL) |= 
+               SM501_CDC_SEL;
+           return 0;
+       }
+    }
+#endif /* CONFIG_BC3450_CRT */
+    printf("Usage:%s\n", cmdtp->help);
+    return 1;
+}
+
+U_BOOT_CMD(
+       fp ,    3,      1,      cmd_fp,
+       "fp      - front panes access functions\n",
+       "\n"
+       "fp bl <on/off>\n"
+       "     - turns the CCFL backlight of the display on/off\n"
+       "fp <on/off>\n"
+       "     - turns the whole display on/off\n"
+#ifdef CONFIG_BC3450_CRT
+       "fp crt <on/off>\n"
+       "     - enables/disables the crt output (debug only)\n"
+#endif /* CONFIG_BC3450_CRT */
+    );
+
+
+/*
+ * temp - DS1620 thermometer
+ */
+/* GERSYS BC3450 specific functions */
+static inline void bc_ds1620_set_clk(int clk)
+{
+    if(clk)
+       *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_CLK;
+    else
+       *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_CLK;
+}
+
+static inline void bc_ds1620_set_data(int dat)
+{
+    if(dat)
+       *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ;
+    else
+       *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_DQ;
+}
+
+static inline int bc_ds1620_get_data(void)
+{
+    vu_long rc;
+    rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
+    rc &= DS1620_DQ;
+    if(rc != 0)
+       rc = 1;
+    return (int)rc;
+}
+
+static inline void bc_ds1620_set_data_dir(int dir)
+{
+    if(dir) /* in */
+       *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~DS1620_DQ;
+    else /* out */
+       *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= DS1620_DQ;
+}
+
+static inline void bc_ds1620_set_reset(int res)
+{
+    if(res)
+       *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_RES;
+    else
+       *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_RES;
+}
+
+/* hardware independent functions */
+static void ds1620_send_bits(int nr, int value)
+{
+    int i;
+    
+    for (i = 0; i < nr; i++) {
+       bc_ds1620_set_data(value & 1);
+       bc_ds1620_set_clk(0);
+       udelay(1);
+       bc_ds1620_set_clk(1);
+       udelay(1);
+       
+       value >>= 1;
+    }
+}
+
+static unsigned int ds1620_recv_bits(int nr)
+{
+    unsigned int value = 0, mask = 1;
+    int i;
+
+    bc_ds1620_set_data(0);
+
+    for (i = 0; i < nr; i++) {
+       bc_ds1620_set_clk(0);
+       udelay(1);
+
+       if (bc_ds1620_get_data())
+           value |= mask;
+
+       mask <<= 1;
+
+       bc_ds1620_set_clk(1);
+       udelay(1);
+    }
+
+    return value;
+}
+
+static void ds1620_out(int cmd, int bits, int value)
+{
+    bc_ds1620_set_clk(1);
+    bc_ds1620_set_data_dir(0);
+
+    bc_ds1620_set_reset(0);
+    udelay(1);
+    bc_ds1620_set_reset(1);
+
+    udelay(1);
+
+    ds1620_send_bits(8, cmd);
+    if (bits)
+       ds1620_send_bits(bits, value);
+
+    udelay(1);
+
+    /* go stand alone */
+    bc_ds1620_set_data_dir(1);
+    bc_ds1620_set_reset(0);
+    bc_ds1620_set_clk(0);
+
+    udelay(10000);
+}
+
+static unsigned int ds1620_in(int cmd, int bits)
+{
+    unsigned int value;
+
+    bc_ds1620_set_clk(1);
+    bc_ds1620_set_data_dir(0);
+
+    bc_ds1620_set_reset(0);
+    udelay(1);
+    bc_ds1620_set_reset(1);
+
+    udelay(1);
+
+    ds1620_send_bits(8, cmd);
+
+    bc_ds1620_set_data_dir(1);
+    value = ds1620_recv_bits(bits);
+
+    /* go stand alone */
+    bc_ds1620_set_data_dir(1);
+    bc_ds1620_set_reset(0);
+    bc_ds1620_set_clk(0);
+
+    return value;
+}
+
+static int cvt_9_to_int(unsigned int val)
+{
+    if (val & 0x100)
+       val |= 0xfffffe00;
+
+    return val;
+}
+
+/* set thermostate thresholds */
+static void ds1620_write_state(struct therm *therm)
+{
+    ds1620_out(THERM_WRITE_TL, 9, therm->lo);
+    ds1620_out(THERM_WRITE_TH, 9, therm->hi);
+    ds1620_out(THERM_START_CONVERT, 0, 0);
+}
+
+static int cmd_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+    int i;
+    struct therm therm;
+
+    sm501_gpio_init();
+
+    /* print temperature */
+    if (argc == 1) {
+       i = cvt_9_to_int(ds1620_in(THERM_READ_TEMP, 9));
+       printf("%d.%d C\n", i >> 1, i & 1 ? 5 : 0);
+       return 0;
+    }
+
+    /* set to default operation */
+    if (strncmp (argv[1], "set", 3) == 0) {
+       if(strncmp (argv[2], "default", 3) == 0) {
+           therm.hi = +88;
+           therm.lo = -20;
+           therm.hi <<= 1;
+           therm.lo <<= 1;
+           ds1620_write_state(&therm);
+           ds1620_out(THERM_WRITE_CONFIG, 8, CFG_STANDALONE);
+           return 0;
+       }
+    }
+
+    printf ("Usage:%s\n", cmdtp->help);
+    return 1;
+}
+
+U_BOOT_CMD(
+       temp ,  3,      1,      cmd_temp,
+       "temp    - print current temperature\n",
+       "\n"
+       "temp\n"
+       "     - print current temperature\n"
+);
+
+#ifdef CONFIG_BC3450_CAN
+/*
+ * Initialise CAN interface
+ *
+ * return 1 on CAN initialization failure
+ * return 0 if no failure
+ */
+int can_init(void)
+{
+       static int init_done = 0;
+       int i;
+       struct mpc5xxx_mscan *can1 =
+               (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900);
+       struct mpc5xxx_mscan *can2 =
+               (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980);
+
+       /* GPIO configuration of the CAN pins is done in BC3450.h */
+
+       if (!init_done) {
+               /* init CAN 1 */
+               can1->canctl1 |= 0x80;  /* CAN enable */
+               udelay(100);
+
+               i = 0;
+               can1->canctl0 |= 0x02;  /* sleep mode */
+               /* wait until sleep mode reached */
+               while (!(can1->canctl1 & 0x02)) {
+                       udelay(10);
+               i++;
+               if (i == 10) {
+                       printf ("%s: CAN1 initialize error, "
+                               "can not enter sleep mode!\n",
+                               __FUNCTION__);
+                       return 1;
+               }
+               }
+               i = 0;
+               can1->canctl0 = 0x01;   /* enter init mode */
+               /* wait until init mode reached */
+               while (!(can1->canctl1 & 0x01)) {
+                       udelay(10);
+                       i++;
+                       if (i == 10) {
+                               printf ("%s: CAN1 initialize error, "
+                                       "can not enter init mode!\n",
+                                       __FUNCTION__);
+                               return 1;
+                       }
+               }
+               can1->canctl1 = 0x80;
+               can1->canctl1 |= 0x40;
+               can1->canbtr0 = 0x0F;
+               can1->canbtr1 = 0x7F;
+               can1->canidac &= ~(0x30);
+               can1->canidar1 = 0x00;
+               can1->canidar3 = 0x00;
+               can1->canidar5 = 0x00;
+               can1->canidar7 = 0x00;
+               can1->canidmr0 = 0xFF;
+               can1->canidmr1 = 0xFF;
+               can1->canidmr2 = 0xFF;
+               can1->canidmr3 = 0xFF;
+               can1->canidmr4 = 0xFF;
+               can1->canidmr5 = 0xFF;
+               can1->canidmr6 = 0xFF;
+               can1->canidmr7 = 0xFF;
+
+               i = 0;
+               can1->canctl0 &= ~(0x01);       /* leave init mode */
+               can1->canctl0 &= ~(0x02);
+               /* wait until init and sleep mode left */
+               while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
+                       udelay(10);
+                       i++;
+                       if (i == 10) {
+                               printf ("%s: CAN1 initialize error, "
+                                       "can not leave init/sleep mode!\n",
+                                       __FUNCTION__);
+                               return 1;
+                       }
+               }
+
+               /* init CAN 2 */
+               can2->canctl1 |= 0x80;  /* CAN enable */
+               udelay(100);
+
+               i = 0;
+               can2->canctl0 |= 0x02;  /* sleep mode */
+               /* wait until sleep mode reached */
+               while (!(can2->canctl1 & 0x02)) {
+                       udelay(10);
+                       i++;
+                       if (i == 10) {
+                               printf ("%s: CAN2 initialize error, "
+                                       "can not enter sleep mode!\n",
+                                       __FUNCTION__);
+                               return 1;
+                       }
+               }
+               i = 0;
+               can2->canctl0 = 0x01;   /* enter init mode */
+               /* wait until init mode reached */
+               while (!(can2->canctl1 & 0x01)) {
+                       udelay(10);
+                       i++;
+                       if (i == 10) {
+                               printf ("%s: CAN2 initialize error, "
+                                       "can not enter init mode!\n",
+                                       __FUNCTION__);
+                               return 1;
+                       }
+               }
+               can2->canctl1 = 0x80;
+               can2->canctl1 |= 0x40;
+               can2->canbtr0 = 0x0F;
+               can2->canbtr1 = 0x7F;
+               can2->canidac &= ~(0x30);
+               can2->canidar1 = 0x00;
+               can2->canidar3 = 0x00;
+               can2->canidar5 = 0x00;
+               can2->canidar7 = 0x00;
+               can2->canidmr0 = 0xFF;
+               can2->canidmr1 = 0xFF;
+               can2->canidmr2 = 0xFF;
+               can2->canidmr3 = 0xFF;
+               can2->canidmr4 = 0xFF;
+               can2->canidmr5 = 0xFF;
+               can2->canidmr6 = 0xFF;
+               can2->canidmr7 = 0xFF;
+               can2->canctl0 &= ~(0x01);       /* leave init mode */
+               can2->canctl0 &= ~(0x02);
+
+               i = 0;
+               /* wait until init mode left */
+               while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
+                       udelay(10);
+                       i++;
+                       if (i == 10) {
+                               printf ("%s: CAN2 initialize error, "
+                                       "can not leave init/sleep mode!\n",
+                                       __FUNCTION__);
+                               return 1;
+                       }
+               }
+               init_done = 1;
+       }
+       return 0;
+}
+
+/*
+ * Do CAN test
+ * by sending message between CAN1 and CAN2
+ *
+ * return 1 on CAN failure
+ * return 0 if no failure
+ */
+int do_can(char *argv[])
+{
+       int i;
+       struct mpc5xxx_mscan *can1 = 
+               (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900);
+       struct mpc5xxx_mscan *can2 = 
+               (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980);
+
+       /* send a message on CAN1 */
+       can1->cantbsel = 0x01;
+       can1->cantxfg.idr[0] = 0x55;
+       can1->cantxfg.idr[1] = 0x00;
+       can1->cantxfg.idr[1] &= ~0x8;
+       can1->cantxfg.idr[1] &= ~0x10;
+       can1->cantxfg.dsr[0] = 0xCC;
+       can1->cantxfg.dlr = 1;
+       can1->cantxfg.tbpr = 0;
+       can1->cantflg = 0x01;
+
+       i = 0;
+       while ((can1->cantflg & 0x01) == 0) {
+               i++;
+               if (i == 10) {
+                       printf ("%s: CAN1 send timeout, "
+                               "can not send message!\n",
+                               __FUNCTION__);
+                       return 1;
+               }
+               udelay(1000);
+       }
+       udelay(1000);
+
+       i = 0;
+       while (!(can2->canrflg & 0x01)) {
+               i++;
+               if (i == 10) {
+                       printf ("%s: CAN2 receive timeout, "
+                               "no message received!\n",
+                               __FUNCTION__);
+                       return 1;
+               }
+               udelay(1000);
+       }
+       
+       if (can2->canrxfg.dsr[0] != 0xCC) {
+               printf ("%s: CAN2 receive error, "
+                        "data mismatch!\n",
+                       __FUNCTION__);
+               return 1;
+       }
+
+       /* send a message on CAN2 */
+       can2->cantbsel = 0x01;
+       can2->cantxfg.idr[0] = 0x55;
+       can2->cantxfg.idr[1] = 0x00;
+       can2->cantxfg.idr[1] &= ~0x8;
+       can2->cantxfg.idr[1] &= ~0x10;
+       can2->cantxfg.dsr[0] = 0xCC;
+       can2->cantxfg.dlr = 1;
+       can2->cantxfg.tbpr = 0;
+       can2->cantflg = 0x01;
+
+       i = 0;
+       while ((can2->cantflg & 0x01) == 0) {
+               i++;
+               if (i == 10) {
+                       printf ("%s: CAN2 send error, "
+                               "can not send message!\n",
+                               __FUNCTION__);
+                       return 1;
+               }
+               udelay(1000);
+       }
+       udelay(1000);
+
+       i = 0;
+       while (!(can1->canrflg & 0x01)) {
+               i++;
+               if (i == 10) {
+                       printf ("%s: CAN1 receive timeout, "
+                               "no message received!\n",
+                               __FUNCTION__);
+                       return 1;
+               }
+               udelay(1000);
+       }
+
+       if (can1->canrxfg.dsr[0] != 0xCC) {
+               printf ("%s: CAN1 receive error 0x%02x\n",
+                       __FUNCTION__, (can1->canrxfg.dsr[0]));
+               return 1;
+       }
+
+       return 0;
+}
+#endif /* CONFIG_BC3450_CAN */
+
+/*
+ * test - BC3450 HW test routines
+ */
+int cmd_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+#ifdef CONFIG_BC3450_CAN
+    int rcode;
+    can_init();
+#endif /* CONFIG_BC3450_CAN */
+
+    sm501_gpio_init();
+
+    if (argc != 2) {
+       printf ("Usage:%s\n", cmdtp->help);
+       return 1;
+    }
+
+    if (strncmp (argv[1], "unit-off", 8) == 0) {
+       printf ("waiting 2 seconds...\n");
+       udelay(2000000);
+       *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= ~PWR_OFF;
+       return 0;
+    }
+#ifdef CONFIG_BC3450_CAN
+    else if (strncmp (argv[1], "can", 2) == 0) {
+       rcode = do_can (argv);
+       if (simple_strtoul(argv[2], NULL, 10) == 2) {
+           if (rcode == 0)
+               printf ("OK\n");
+           else
+               printf ("Error\n");
+       }
+       return rcode;
+    }
+#endif /* CONFIG_BC3450_CAN */
+
+    printf ("Usage:%s\n", cmdtp->help);
+    return 1;
+}
+
+U_BOOT_CMD(
+       test ,  2,      1,      cmd_test,
+       "test    - unit test routines\n",
+       "\n"
+#ifdef CONFIG_BC3450_CAN
+       "test can\n"
+       "     - connect CAN1 (X8) with CAN2 (X9) for this test\n"
+#endif /* CONFIG_BC3450_CAN */
+       "test unit-off\n"
+       "     - turns off the BC3450 unit\n"
+       "       WARNING: Unsaved environment variables will be lost!\n"
+    );
+#endif /* CFG_CMD_BSP */

diff --git a/board/bc3450/config.mk b/board/bc3450/config.mk
new file mode 100644 (file)
index 0000000..47e9955
--- /dev/null
+++ b/board/bc3450/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# BC3450 board:
+#
+#      Valid values for TEXT_BASE are:
+#
+#      0xFC000000   boot low (standard configuration with room for max 64 MByte
+#                   Flash ROM)
+#      0x00100000   boot from RAM (for testing only)
+#
+
+ifndef TEXT_BASE
+## Standard: boot low
+TEXT_BASE = 0xFC000000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

diff --git a/board/bc3450/mt48lc16m16a2-75.h b/board/bc3450/mt48lc16m16a2-75.h
new file mode 100644 (file)
index 0000000..3f1e169
--- /dev/null
+++ b/board/bc3450/mt48lc16m16a2-75.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR      0               /* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE     0x00CD0000
+/* #define SDRAM_MODE  0x008D0000 */ /* CAS latency 2 */
+#define SDRAM_CONTROL  0x504F0000
+#define SDRAM_CONFIG1  0xD2322800
+/* #define SDRAM_CONFIG1       0xD2222800 */ /* CAS latency 2 */
+/*#define SDRAM_CONFIG1        0xD7322800 */ /* SDRAM controller bug workaround */
+#define SDRAM_CONFIG2  0x8AD70000
+/*#define SDRAM_CONFIG2        0xDDD70000 */ /* SDRAM controller bug workaround */
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE     0x008D0000
+#define SDRAM_CONTROL  0x504F0000
+#define SDRAM_CONFIG1  0xC2222600
+#define SDRAM_CONFIG2  0x88B70004
+#define SDRAM_ADDRSEL  0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif

diff --git a/board/bc3450/u-boot.lds b/board/bc3450/u-boot.lds
new file mode 100644 (file)
index 0000000..93b98a8
--- /dev/null
+++ b/board/bc3450/u-boot.lds
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)              }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)              }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)               }
+  .rela.got      : { *(.rela.got)              }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)               }
+  .rela.bss      : { *(.rela.bss)              }
+  .rel.plt       : { *(.rel.plt)               }
+  .rela.plt      : { *(.rela.plt)              }
+  .init          : { *(.init)  }
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o        (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

diff --git a/board/bmw/serial.c b/board/bmw/serial.c
index f36a41b9ffaa4dcc457de8eb4a6b28e51f94e98f..712a95b19e50e50e4b39449708d1a90d42369ba1 100644 (file)
--- a/board/bmw/serial.c
+++ b/board/bmw/serial.c
@@ -24,6 +24,8 @@
 #include <common.h>
 #include "ns16550.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if CONFIG_CONS_INDEX == 1
 static struct NS16550 *console =
                (struct NS16550 *) (CFG_EUMB_ADDR + 0x4500);
@@ -38,8 +40,6 @@ extern ulong get_bus_freq (ulong);
 
 int serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int clock_divisor = gd->bus_clk / 16 / gd->baudrate;
 
        NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor);
@@ -75,8 +75,6 @@ int serial_tstc (void)
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate;
 
        NS16550_reinit (console, clock_divisor);

diff --git a/board/cerf250/cerf250.c b/board/cerf250/cerf250.c
index cc1bc16f6e127904548a26535d93c47bb30fc29d..307894fd613d4ff44f7b4c105db0c20d94de22a1 100644 (file)
--- a/board/cerf250/cerf250.c
+++ b/board/cerf250/cerf250.c
@@ -27,6 +27,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 
@@ -36,8 +38,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* memory and cpu-speed are setup before relocation */
        /* so we do _nothing_ here */
 
@@ -60,8 +60,6 @@ int board_late_init(void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

diff --git a/board/cm4008/cm4008.c b/board/cm4008/cm4008.c
index 4d2013b4073c6e8053f511f3b0a11556d863623f..d34737c4979af53539acd9cf36ee5bd9a058ee03 100644 (file)
--- a/board/cm4008/cm4008.c
+++ b/board/cm4008/cm4008.c
@@ -31,6 +31,8 @@
 #include <common.h>
 #include <asm/arch/platform.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 #define        ks8695_read(a)    *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
@@ -75,8 +77,6 @@ int board_late_init (void)
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* arch number of CM4008 */
        gd->bd->bi_arch_number = 624;
 
@@ -92,8 +92,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/cm41xx/cm41xx.c b/board/cm41xx/cm41xx.c
index 65eaa942c54c3a03484e50cae6b5143f3bd573ca..02d05afef6e824b618e872670a3af75c7e6723e2 100644 (file)
--- a/board/cm41xx/cm41xx.c
+++ b/board/cm41xx/cm41xx.c
@@ -31,6 +31,8 @@
 #include <common.h>
 #include <asm/arch/platform.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 #define        ks8695_read(a)    *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
@@ -75,8 +77,6 @@ int board_late_init (void)
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* arch number of CM41xx */
        gd->bd->bi_arch_number = 672;
 
@@ -92,8 +92,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/cmc_pu2/cmc_pu2.c b/board/cmc_pu2/cmc_pu2.c
index 14168e636bb8a06694bf0de5d9941608866b51e8..9ae3c42be50685ef92ff5e78f348348b08a68991 100644 (file)
--- a/board/cmc_pu2/cmc_pu2.c
+++ b/board/cmc_pu2/cmc_pu2.c
@@ -33,6 +33,8 @@
 #include <at91rm9200_net.h>
 #include <dm9161.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 /*
  * Miscelaneous platform dependent initialisations
@@ -45,7 +47,6 @@ int hw_detect (void);
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        AT91PS_PIO piob = AT91C_BASE_PIOB;
        AT91PS_PIO pioc = AT91C_BASE_PIOC;
 
@@ -109,8 +110,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
        return 0;

diff --git a/board/cmc_pu2/load_sernum_ethaddr.c b/board/cmc_pu2/load_sernum_ethaddr.c
index 94aa30df96248897e8e93be2cf23d47a3b0a85b0..354566c05df7339b35adb28d7d7e744ea861ae22 100644 (file)
--- a/board/cmc_pu2/load_sernum_ethaddr.c
+++ b/board/cmc_pu2/load_sernum_ethaddr.c
@@ -69,8 +69,8 @@ int i2c_read (unsigned char chip, unsigned int addr, int alen,
 void load_sernum_ethaddr (void)
 {
        struct manufacturer_data data;
-       unsigned char  serial [9];
-       unsigned char  ethaddr[18];
+       char  ethaddr[18];
+       char  serial [9];
        unsigned short chksum;
        unsigned char *p;
        unsigned short i, is, id;

diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c
index 6f5874a6719d75d15f822311c8aecf5d86333d24..73cc2f2c10c1e563ef5e458e070b2a01f9ac895b 100644 (file)
--- a/board/cobra5272/flash.c
+++ b/board/cobra5272/flash.c
@@ -256,8 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
        return rc;
 }
 
-
-volatile static int write_word (flash_info_t * info, ulong dest, ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
        volatile u16 *addr = (volatile u16 *) dest;
        ulong result;

diff --git a/board/cogent/serial.c b/board/cogent/serial.c
index 4c200170d0db13daed80ac597d9ab49941f45974..2b595a85aea872c000407245c438fdcb0581e704 100644 (file)
--- a/board/cogent/serial.c
+++ b/board/cogent/serial.c
@@ -6,6 +6,8 @@
 #include <common.h>
 #include <board/cogent/serial.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
 
 #if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \
@@ -25,76 +27,65 @@
 
 int serial_init (void)
 {
-/*  DECLARE_GLOBAL_DATA_PTR; */
-
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
+       cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
 
-    cma_mb_reg_write(&mbsp->ser_ier, 0x00);    /* turn off interrupts */
-    serial_setbrg ();
-    cma_mb_reg_write(&mbsp->ser_lcr, 0x03);    /* 8 data, 1 stop, no parity */
-    cma_mb_reg_write(&mbsp->ser_mcr, 0x03);    /* RTS/DTR */
-    cma_mb_reg_write(&mbsp->ser_fcr, 0x07);    /* Clear & enable FIFOs */
+       cma_mb_reg_write (&mbsp->ser_ier, 0x00);        /* turn off interrupts */
+       serial_setbrg ();
+       cma_mb_reg_write (&mbsp->ser_lcr, 0x03);        /* 8 data, 1 stop, no parity */
+       cma_mb_reg_write (&mbsp->ser_mcr, 0x03);        /* RTS/DTR */
+       cma_mb_reg_write (&mbsp->ser_fcr, 0x07);        /* Clear & enable FIFOs */
 
-    return (0);
+       return (0);
 }
 
-void
-serial_setbrg (void)
+void serial_setbrg (void)
 {
-    DECLARE_GLOBAL_DATA_PTR;
-
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
-    unsigned int divisor;
-    unsigned char lcr;
-
-    if ((divisor = br_to_div(gd->baudrate)) == 0)
-       divisor = DEFDIV;
-
-    lcr = cma_mb_reg_read(&mbsp->ser_lcr);
-    cma_mb_reg_write(&mbsp->ser_lcr, lcr|0x80);/* Access baud rate(set DLAB)*/
-    cma_mb_reg_write(&mbsp->ser_brl, divisor & 0xff);
-    cma_mb_reg_write(&mbsp->ser_brh, (divisor >> 8) & 0xff);
-    cma_mb_reg_write(&mbsp->ser_lcr, lcr);     /* unset DLAB */
+       cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
+       unsigned int divisor;
+       unsigned char lcr;
+
+       if ((divisor = br_to_div (gd->baudrate)) == 0)
+               divisor = DEFDIV;
+
+       lcr = cma_mb_reg_read (&mbsp->ser_lcr);
+       cma_mb_reg_write (&mbsp->ser_lcr, lcr | 0x80);  /* Access baud rate(set DLAB) */
+       cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff);
+       cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff);
+       cma_mb_reg_write (&mbsp->ser_lcr, lcr); /* unset DLAB */
 }
 
-void
-serial_putc(const char c)
+void serial_putc (const char c)
 {
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
+       cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
 
-    if (c == '\n')
-       serial_putc('\r');
+       if (c == '\n')
+               serial_putc ('\r');
 
-    while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_THRE) == 0)
-       ;
+       while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0);
 
-    cma_mb_reg_write(&mbsp->ser_thr, c);
+       cma_mb_reg_write (&mbsp->ser_thr, c);
 }
 
-void
-serial_puts(const char *s)
+void serial_puts (const char *s)
 {
-    while (*s != '\0')
-       serial_putc(*s++);
+       while (*s != '\0')
+               serial_putc (*s++);
 }
 
-int
-serial_getc(void)
+int serial_getc (void)
 {
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
+       cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
 
-    while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) == 0)
-       ;
+       while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0);
 
-    return ((int)cma_mb_reg_read(&mbsp->ser_rhr) & 0x7f);
+       return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f);
 }
 
-int
-serial_tstc(void)
+int serial_tstc (void)
 {
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
+       cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
 
-    return ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) != 0);
+       return ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) != 0);
 }
 
 #endif /* CONS_NONE */
@@ -118,71 +109,63 @@ serial_tstc(void)
 #error CONFIG_KGDB_INDEX must be configured for Cogent motherboard serial
 #endif
 
-void
-kgdb_serial_init(void)
+void kgdb_serial_init (void)
 {
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE;
-    unsigned int divisor;
+       cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
+       unsigned int divisor;
 
-    if ((divisor = br_to_div(CONFIG_KGDB_BAUDRATE)) == 0)
-       divisor = DEFDIV;
+       if ((divisor = br_to_div (CONFIG_KGDB_BAUDRATE)) == 0)
+               divisor = DEFDIV;
 
-    cma_mb_reg_write(&mbsp->ser_ier, 0x00);    /* turn off interrupts */
-    cma_mb_reg_write(&mbsp->ser_lcr, 0x80);    /* Access baud rate(set DLAB)*/
-    cma_mb_reg_write(&mbsp->ser_brl, divisor & 0xff);
-    cma_mb_reg_write(&mbsp->ser_brh, (divisor >> 8) & 0xff);
-    cma_mb_reg_write(&mbsp->ser_lcr, 0x03);    /* 8 data, 1 stop, no parity */
-    cma_mb_reg_write(&mbsp->ser_mcr, 0x03);    /* RTS/DTR */
-    cma_mb_reg_write(&mbsp->ser_fcr, 0x07);    /* Clear & enable FIFOs */
+       cma_mb_reg_write (&mbsp->ser_ier, 0x00);        /* turn off interrupts */
+       cma_mb_reg_write (&mbsp->ser_lcr, 0x80);        /* Access baud rate(set DLAB) */
+       cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff);
+       cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff);
+       cma_mb_reg_write (&mbsp->ser_lcr, 0x03);        /* 8 data, 1 stop, no parity */
+       cma_mb_reg_write (&mbsp->ser_mcr, 0x03);        /* RTS/DTR */
+       cma_mb_reg_write (&mbsp->ser_fcr, 0x07);        /* Clear & enable FIFOs */
 
-    printf("[on cma10x serial port B] ");
+       printf ("[on cma10x serial port B] ");
 }
 
-void
-putDebugChar(int c)
+void putDebugChar (int c)
 {
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE;
+       cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
 
-    while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_THRE) == 0)
-       ;
+       while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0);
 
-    cma_mb_reg_write(&mbsp->ser_thr, c & 0xff);
+       cma_mb_reg_write (&mbsp->ser_thr, c & 0xff);
 }
 
-void
-putDebugStr(const char *str)
+void putDebugStr (const char *str)
 {
-    while (*str != '\0') {
-       if (*str == '\n')
-           putDebugChar('\r');
-       putDebugChar(*str++);
-    }
+       while (*str != '\0') {
+               if (*str == '\n')
+                       putDebugChar ('\r');
+               putDebugChar (*str++);
+       }
 }
 
-int
-getDebugChar(void)
+int getDebugChar (void)
 {
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE;
+       cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
 
-    while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) == 0)
-       ;
+       while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0);
 
-    return ((int)cma_mb_reg_read(&mbsp->ser_rhr) & 0x7f);
+       return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f);
 }
 
-void
-kgdb_interruptible(int yes)
+void kgdb_interruptible (int yes)
 {
-    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE;
-
-    if (yes == 1) {
-       printf("kgdb: turning serial ints on\n");
-       cma_mb_reg_write(&mbsp->ser_ier, 0xf);
-    }
-    else {
-       printf("kgdb: turning serial ints off\n");
-       cma_mb_reg_write(&mbsp->ser_ier, 0x0);
-    }
+       cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
+
+       if (yes == 1) {
+               printf ("kgdb: turning serial ints on\n");
+               cma_mb_reg_write (&mbsp->ser_ier, 0xf);
+       } else {
+               printf ("kgdb: turning serial ints off\n");
+               cma_mb_reg_write (&mbsp->ser_ier, 0x0);
+       }
 }
 
 #endif /* KGDB && KGDB_NONE */

diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c
index 6f65f3275731294158deb8c6e5ec7fec98879529..6d8d55570f8eb0bb3f10b776ad18083c8c1185b5 100644 (file)
--- a/board/cradle/cradle.c
+++ b/board/cradle/cradle.c
@@ -28,6 +28,8 @@
 #include <asm/arch/pxa-regs.h>
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 
@@ -181,8 +183,6 @@ int
 board_init (void)
 /**********************************************************/
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        led_code (0xf, YELLOW);
 
        /* arch number of HHP Cradle */
@@ -209,8 +209,6 @@ int
 dram_init (void)
 /**********************************************************/
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c
index c99a71557c0799b3a7cc4bb753415c762ccbd24b..80caf8b464e17e5bda816760a9248a799845454b 100644 (file)
--- a/board/csb226/csb226.c
+++ b/board/csb226/csb226.c
@@ -26,6 +26,8 @@
 #include <common.h>
 #include <asm/arch/pxa-regs.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 # define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
 #else
@@ -65,8 +67,6 @@ int misc_init_r(void)
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* memory and cpu-speed are setup before relocation */
        /* so we do _nothing_ here */
 
@@ -88,8 +88,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/csb637/csb637.c b/board/csb637/csb637.c
index 6100a53fb7763d00f1df394ee1ea5ddc7394e868..aeb1a138d254aa727784ef965c8e204b960f5b43 100644 (file)
--- a/board/csb637/csb637.c
+++ b/board/csb637/csb637.c
@@ -26,6 +26,8 @@
 #include <at91rm9200_net.h>
 #include <bcm5221.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 /*
  * Miscelaneous platform dependent initialisations
@@ -33,8 +35,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Enable Ctrlc */
        console_init_f ();
 
@@ -51,8 +51,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
        return 0;

diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c
index 5844a5cf324b137b41ef1b569c4c63a8774be370..3edd27a3ebd101443f439d26857c35acda5cb9e0 100644 (file)
--- a/board/cu824/cu824.c
+++ b/board/cu824/cu824.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2001
  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
  *
- * (C) Copyright 2001, 2002
+ * (C) Copyright 2001-2006
  * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
 
  * See file CREDITS for list of people who contributed to this
@@ -29,12 +29,12 @@
 #include <asm/processor.h>
 #include <pci.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define BOARD_REV_REG 0xFE80002B
 
 int checkboard (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        char  revision = *(volatile char *)(BOARD_REV_REG);
        char  buf[32];
 

diff --git a/board/dave/B2/B2.c b/board/dave/B2/B2.c
index 29676b800fc58bb1146569cb3c68688b0ea2dc2e..64fe948fcce840155976b355922a13c46b9afdab 100644 (file)
--- a/board/dave/B2/B2.c
+++ b/board/dave/B2/B2.c
@@ -27,13 +27,14 @@
 #include <common.h>
 #include <asm/hardware.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Miscelaneous platform dependent initialization
  */
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        u32 temp;
 
        /* Configuration Port Control Register*/
@@ -119,8 +120,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/dave/PPChameleonEVB/Makefile b/board/dave/PPChameleonEVB/Makefile
index 39d2feceb422d6fc6b586a0eed4085da53497cf8..581a5802b4c684641e6414505fc618988eeb65ca 100644 (file)
--- a/board/dave/PPChameleonEVB/Makefile
+++ b/board/dave/PPChameleonEVB/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = lib$(BOARD).a
 
-OBJS   = $(BOARD).o flash.o
+OBJS   = $(BOARD).o flash.o nand.o
 
 $(LIB):        $(OBJS) $(SOBJS)
        $(AR) crv $@ $^

diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c
index 5f2c705f1230ab7b47580cacf8f0ac03b2e7ab01..e8302d9fc7f72befebaa790f499ab098201474ab 100644 (file)
--- a/board/dave/PPChameleonEVB/PPChameleonEVB.c
+++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c
@@ -29,6 +29,8 @@
 #include <command.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 /* Prototypes */
@@ -81,8 +83,6 @@ extern flash_info_t flash_info[];     /* info for FLASH chips */
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* adjust flash start and size as well as the offset */
        gd->bd->bi_flashstart = 0 - flash_info[0].size;
        gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN;
@@ -238,33 +238,6 @@ int testdram (void)
 
 /* ------------------------------------------------------------------------- */
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-extern ulong
-nand_probe(ulong physadr);
-
-void
-nand_init(void)
-{
-       ulong totlen = 0;
-
-/*
-       The HI model is equipped with a large block NAND chip not supported yet
-       by U-Boot
-    (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
-*/
-
-#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
-       debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
-       totlen += nand_probe (CFG_NAND0_BASE);
-#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
-
-       debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
-       totlen += nand_probe (CFG_NAND1_BASE);
-
-       printf ("%3lu MB\n", totlen >>20);
-}
-#endif
-
 #ifdef CONFIG_CFB_CONSOLE
 # ifdef CONFIG_CONSOLE_EXTRA_INFO
 # include <video_fb.h>

diff --git a/board/dave/PPChameleonEVB/config.mk b/board/dave/PPChameleonEVB/config.mk
index 5856aec0ce595f2ca2de5496e964abfbb19e54cd..9083aacfabf049bf03cbc5f2b7121abb04e2b892 100644 (file)
--- a/board/dave/PPChameleonEVB/config.mk
+++ b/board/dave/PPChameleonEVB/config.mk
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000
+# (C) Copyright 2000, 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -22,7 +22,7 @@
 #
 
 # Reserve 256 kB for Monitor
-TEXT_BASE = 0xFFFC0000
+#TEXT_BASE = 0xFFFC0000
 
 # Reserve 320 kB for Monitor
-#TEXT_BASE = 0xFFFB0000
+TEXT_BASE = 0xFFFB0000

diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c
new file mode 100644 (file)
index 0000000..40a827c
--- /dev/null
+++ b/board/dave/PPChameleonEVB/nand.c
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
+ */
+static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+       struct nand_chip *this = mtdinfo->priv;
+       ulong base = (ulong) this->IO_ADDR_W;
+
+       switch(cmd) {
+       case NAND_CTL_SETCLE:
+               MACRO_NAND_CTL_SETCLE((unsigned long)base);
+               break;
+       case NAND_CTL_CLRCLE:
+               MACRO_NAND_CTL_CLRCLE((unsigned long)base);
+               break;
+       case NAND_CTL_SETALE:
+               MACRO_NAND_CTL_SETALE((unsigned long)base);
+               break;
+       case NAND_CTL_CLRALE:
+               MACRO_NAND_CTL_CLRALE((unsigned long)base);
+               break;
+       case NAND_CTL_SETNCE:
+               MACRO_NAND_ENABLE_CE((unsigned long)base);
+               break;
+       case NAND_CTL_CLRNCE:
+               MACRO_NAND_DISABLE_CE((unsigned long)base);
+               break;
+       }
+}
+
+
+/*
+ * read device ready pin
+ * function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
+ */
+static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
+{
+       struct nand_chip *this = mtdinfo->priv;
+       ulong rb_gpio_pin;
+
+       /* use the base addr to find out which chip are we dealing with */
+       switch((ulong) this->IO_ADDR_W) {
+       case CFG_NAND0_BASE:
+               rb_gpio_pin = CFG_NAND0_RDY;
+               break;
+       case CFG_NAND1_BASE:
+               rb_gpio_pin = CFG_NAND1_RDY;
+               break;
+       default: /* this should never happen */
+               return 0;
+               break;
+       }
+
+       if (in32(GPIO0_IR) & rb_gpio_pin)
+               return 1;
+       return 0;
+}
+
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for  accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
+ *   only be provided if a hardware ECC is available
+ * - eccmode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ *   read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ *   nand_scan about special functionality. See the defines for further
+ *   explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+void board_nand_init(struct nand_chip *nand)
+{
+
+       nand->hwcontrol = ppchameleonevb_hwcontrol;
+       nand->dev_ready = ppchameleonevb_device_ready;
+       nand->eccmode = NAND_ECC_SOFT;
+       nand->chip_delay = NAND_BIG_DELAY_US;
+       nand->options = NAND_SAMSUNG_LP_OPTIONS;
+}
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */

diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S
index 7afd5840c8628a6925e0067035ea2d6c79d15656..14a78465f3659a0420bc18e42c3a5b85e2243315 100644 (file)
--- a/board/dbau1x00/lowlevel_init.S
+++ b/board/dbau1x00/lowlevel_init.S
@@ -185,6 +185,8 @@ tlbloop:
        bne     t0, t2, tlbloop
        nop
 
+#endif /* CONFIG_DBAU1550 */
+
        /* First setup pll:s to make serial work ok */
        /* We have a 12 MHz crystal */
        li      t0, SYS_CPUPLL
@@ -205,6 +207,7 @@ tlbloop:
        sw      t1, 0(t0) /* aux pll */
        sync
 
+#ifdef CONFIG_DBAU1550
        /*  Static memory controller */
        /* RCE0 - can not change while fetching, do so from icache */
        move            t2, ra /* Store return address */
@@ -237,7 +240,7 @@ noCacheJump:
        sw      t1, 0(t0)
 #else /* CONFIG_DBAU1550 */
        li      t0, MEM_STTIME0
-       li      t1, 0x00014C0F
+       li      t1, 0x040181D7
        sw      t1, 0(t0)
 
        /* RCE0 AMD 29LV640M MirrorBit Flash */

diff --git a/board/delta/Makefile b/board/delta/Makefile
new file mode 100644 (file)
index 0000000..e744eec
--- /dev/null
+++ b/board/delta/Makefile
@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   := delta.o nand.o
+SOBJS  := lowlevel_init.o
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

diff --git a/board/delta/config.mk b/board/delta/config.mk
new file mode 100644 (file)
index 0000000..3fe406c
--- /dev/null
+++ b/board/delta/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x83008000

diff --git a/board/delta/delta.c b/board/delta/delta.c
new file mode 100644 (file)
index 0000000..b7671dd
--- /dev/null
+++ b/board/delta/delta.c
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <da9030.h>
+#include <asm/arch/pxa-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+static void init_DA9030(void);
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+       /* memory and cpu-speed are setup before relocation */
+       /* so we do _nothing_ here */
+
+       /* arch number of Lubbock-Board mk@tbd: fix this! */
+       gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
+
+       /* adress of boot parameters */
+       gd->bd->bi_boot_params = 0xa0000100;
+
+       return 0;
+}
+
+int board_late_init(void)
+{
+       setenv("stdout", "serial");
+       setenv("stderr", "serial");
+       init_DA9030();
+       return 0;
+}
+
+
+int dram_init (void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+       gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+       gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+       gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+       gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+       gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+       return 0;
+}
+
+void i2c_init_board()
+{
+       CKENB |= (CKENB_4_I2C);
+
+       /* setup I2C GPIO's */
+       GPIO32 = 0x801;         /* SCL = Alt. Fkt. 1 */
+       GPIO33 = 0x801;         /* SDA = Alt. Fkt. 1 */
+}
+
+/* initialize the DA9030 Power Controller */
+static void init_DA9030()
+{
+       uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
+
+       CKENB |= CKENB_7_GPIO;
+       udelay(100);
+
+       /* Rising Edge on EXTON to reset DA9030 */
+       GPIO17 = 0x8800;        /* configure GPIO17, no pullup, -down */
+       GPDR0 |= (1<<17);       /* GPIO17 is output */
+       GSDR0 = (1<<17);
+       GPCR0 = (1<<17);        /* drive GPIO17 low */
+       GPSR0 = (1<<17);        /* drive GPIO17 high */
+
+#if CFG_DA9030_EXTON_DELAY
+       udelay((unsigned long) CFG_DA9030_EXTON_DELAY); /* wait for DA9030 */
+#endif
+       GPCR0 = (1<<17);        /* drive GPIO17 low */
+
+       /* reset the watchdog and go active (0xec) */
+       val = (SYS_CONTROL_A_HWRES_ENABLE |
+              (0x6<<4) |
+              SYS_CONTROL_A_WDOG_ACTION |
+              SYS_CONTROL_A_WATCHDOG);
+       if(i2c_write(addr, SYS_CONTROL_A, 1, &val, 1)) {
+               printf("Error accessing DA9030 via i2c.\n");
+               return;
+       }
+
+       i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */
+       i2c_reg_write(addr, LDO2_3, 0xd1);      /* LDO2 =1,9V, LDO3=3,1V */
+       i2c_reg_write(addr, LDO4_5, 0xcc);      /* LDO2 =1,9V, LDO3=3,1V */
+       i2c_reg_write(addr, LDO6_SIMCP, 0x3e);  /* LDO6=3,2V, SIMCP = 5V support */
+       i2c_reg_write(addr, LDO7_8, 0xc9);      /* LDO7=2,7V, LDO8=3,0V */
+       i2c_reg_write(addr, LDO9_12, 0xec);     /* LDO9=3,0V, LDO12=3,2V */
+       i2c_reg_write(addr, BUCK, 0x0c);        /* Buck=1.2V */
+       i2c_reg_write(addr, REG_CONTROL_2_98, 0x7f); /* All LDO'S on 8,9,10,11,12,14 */
+       i2c_reg_write(addr, LDO_10_11, 0xcc);   /* LDO10=3.0V  LDO11=3.0V */
+       i2c_reg_write(addr, LDO_15, 0xae);      /* LDO15=1.8V, dislock first 3bit */
+       i2c_reg_write(addr, LDO_14_16, 0x05);   /* LDO14=2.8V, LDO16=NB */
+       i2c_reg_write(addr, LDO_18_19, 0x9c);   /* LDO18=3.0V, LDO19=2.7V */
+       i2c_reg_write(addr, LDO_17_SIMCP0, 0x2c); /* LDO17=3.0V, SIMCP=3V support */
+       i2c_reg_write(addr, BUCK2_DVC1, 0x9a);  /* Buck2=1.5V plus Update support of 520 MHz */
+       i2c_reg_write(addr, REG_CONTROL_2_18, 0x43); /* Ball on */
+       i2c_reg_write(addr, MISC_CONTROLB, 0x08); /* session valid enable */
+       i2c_reg_write(addr, USBPUMP, 0xc1);     /* start pump, ignore HW signals */
+
+       val = i2c_reg_read(addr, STATUS);
+       if(val & STATUS_CHDET)
+               printf("Charger detected, turning on LED.\n");
+       else {
+               printf("No charger detetected.\n");
+               /* undervoltage? print error and power down */
+       }
+}
+
+
+#if 0
+/* reset the DA9030 watchdog */
+void hw_watchdog_reset(void)
+{
+       uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
+       val = i2c_reg_read(addr, SYS_CONTROL_A);
+       val |= SYS_CONTROL_A_WATCHDOG;
+       i2c_reg_write(addr, SYS_CONTROL_A, val);
+}
+#endif

diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S
new file mode 100644 (file)
index 0000000..f059db5
--- /dev/null
+++ b/board/delta/lowlevel_init.S
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+.macro wait time
+       ldr             r2, =OSCR
+       mov             r3, #0
+       str             r3, [r2]
+0:
+       ldr             r3, [r2]
+       cmp             r3, \time
+       bls             0b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+       /* Set up GPIO pins first */
+       mov      r10, lr
+
+       /*  Configure GPIO  Pins 97, 98 UART1 / altern. Fkt. 1 */
+       ldr             r0, =GPIO97
+       ldr             r1, =0x801
+       str             r1, [r0]
+
+       ldr             r0, =GPIO98
+       ldr             r1, =0x801
+       str             r1, [r0]
+
+       /* tebrandt - ASCR, clear the RDH bit */
+       ldr             r0, =ASCR
+       ldr             r1, [r0]
+       bic             r1, r1, #0x80000000
+       str             r1, [r0]
+
+mem_init:
+       /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
+       ldr             r0, =ACCR
+       ldr             r1, [r0]
+       orr             r1, r1, #0x3000
+       str             r1, [r0]
+       ldr             r1, [r0]
+
+       /* 2. Programm MDCNFG, leaving DMCEN de-asserted */
+       ldr             r0, =MDCNFG
+       ldr             r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
+       /* ldr          r1, =0x80000403 */
+       str             r1, [r0]
+       ldr             r1, [r0]        /* delay until written */
+
+       /* 3. wait nop power up waiting period (200ms)
+        * optimization: Steps 4+6 can be done during this
+        */
+       wait #300
+
+       /* 4. Perform an initial Rcomp-calibration cycle */
+       ldr             r0, =RCOMP
+       ldr             r1, =0x80000000
+       str             r1, [r0]
+       ldr             r1, [r0]        /* delay until written */
+       /* missing: program for automatic rcomp evaluation cycles */
+
+       /* 5. DDR DRAM strobe delay calibration */
+       ldr             r0, =DDR_HCAL
+       ldr             r1, =0x88000007
+       str             r1, [r0]
+       wait            #5
+       ldr             r1, [r0]        /* delay until written */
+
+       /* Set MDMRS */
+       ldr             r0, =MDMRS
+       ldr             r1, =0x60000033
+       str             r1, [r0]
+       wait    #300
+
+       /* Configure MDREFR */
+       ldr             r0, =MDREFR
+       ldr             r1, =0x00000006
+       str             r1, [r0]
+       ldr             r1, [r0]
+
+       /* Enable the dynamic memory controller */
+       ldr             r0, =MDCNFG
+       ldr             r1, [r0]
+       orr             r1, r1, #MDCNFG_DMCEN
+       str             r1, [r0]
+
+#ifndef CFG_SKIP_DRAM_SCRUB
+       /* scrub/init SDRAM if enabled/present */
+       ldr     r8, =CFG_DRAM_BASE      /* base address of SDRAM (CFG_DRAM_BASE) */
+       ldr     r9, =CFG_DRAM_SIZE      /* size of memory to scrub (CFG_DRAM_SIZE) */
+       mov     r0, #0                  /* scrub with 0x0000:0000 */
+       mov     r1, #0
+       mov     r2, #0
+       mov     r3, #0
+       mov     r4, #0
+       mov     r5, #0
+       mov     r6, #0
+       mov     r7, #0
+10:    /* fastScrubLoop */
+       subs    r9, r9, #32     /* 8 words/line */
+       stmia   r8!, {r0-r7}
+       beq     15f
+       b       10b
+#endif /* CFG_SKIP_DRAM_SCRUB */
+
+15:
+       /* Mask all interrupts */
+       mov     r1, #0
+       mcr     p6, 0, r1, c1, c0, 0    @ ICMR
+
+       /* Disable software and data breakpoints */
+       mov     r0, #0
+       mcr     p15,0,r0,c14,c8,0  /* ibcr0 */
+       mcr     p15,0,r0,c14,c9,0  /* ibcr1 */
+       mcr     p15,0,r0,c14,c4,0  /* dbcon */
+
+       /* Enable all debug functionality */
+       mov     r0,#0x80000000
+       mcr     p14,0,r0,c10,c0,0  /* dcsr */
+
+endlowlevel_init:
+       mov     pc, lr

diff --git a/board/delta/nand.c b/board/delta/nand.c
new file mode 100644 (file)
index 0000000..fe648fc
--- /dev/null
+++ b/board/delta/nand.c
@@ -0,0 +1,584 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if !defined(CFG_NAND_LEGACY)
+
+#include <nand.h>
+#include <asm/arch/pxa-regs.h>
+
+#ifdef CFG_DFC_DEBUG1
+# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG1(fmt, args...)
+#endif
+
+#ifdef CFG_DFC_DEBUG2
+# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG2(fmt, args...)
+#endif
+
+#ifdef CFG_DFC_DEBUG3
+# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG3(fmt, args...)
+#endif
+
+#define MIN(x, y)              ((x < y) ? x : y)
+
+/* These really don't belong here, as they are specific to the NAND Model */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr delta_bbt_descr = {
+       .options = 0,
+       .offs = 0,
+       .len = 2,
+       .pattern = scan_ff_pattern
+};
+
+static struct nand_oobinfo delta_oob = {
+       .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
+       .eccbytes = 6,
+       .eccpos = {2, 3, 4, 5, 6, 7},
+       .oobfree = { {8, 2}, {12, 4} }
+};
+
+
+/*
+ * not required for Monahans DFC
+ */
+static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+       return;
+}
+
+#if 0
+/* read device ready pin */
+static int dfc_device_ready(struct mtd_info *mtdinfo)
+{
+       if(NDSR & NDSR_RDY)
+               return 1;
+       else
+               return 0;
+       return 0;
+}
+#endif
+
+/*
+ * Write buf to the DFC Controller Data Buffer
+ */
+static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+       unsigned long bytes_multi = len & 0xfffffffc;
+       unsigned long rest = len & 0x3;
+       unsigned long *long_buf;
+       int i;
+
+       DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
+       if(bytes_multi) {
+               for(i=0; i<bytes_multi; i+=4) {
+                       long_buf = (unsigned long*) &buf[i];
+                       NDDB = *long_buf;
+               }
+       }
+       if(rest) {
+               printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
+       }
+       return;
+}
+
+
+/*
+ * These functions are quite problematic for the DFC. Luckily they are
+ * not used in the current nand code, except for nand_command, which
+ * we've defined our own anyway. The problem is, that we always need
+ * to write 4 bytes to the DFC Data Buffer, but in these functions we
+ * don't know if to buffer the bytes/half words until we've gathered 4
+ * bytes or if to send them straight away.
+ *
+ * Solution: Don't use these with Mona's DFC and complain loudly.
+ */
+static void dfc_write_word(struct mtd_info *mtd, u16 word)
+{
+       printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n");
+}
+static void dfc_write_byte(struct mtd_info *mtd, u_char byte)
+{
+       printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
+}
+
+/* The original:
+ * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
+ *
+ * Shouldn't this be "u_char * const buf" ?
+ */
+static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
+{
+       int i=0, j;
+
+       /* we have to be carefull not to overflow the buffer if len is
+        * not a multiple of 4 */
+       unsigned long bytes_multi = len & 0xfffffffc;
+       unsigned long rest = len & 0x3;
+       unsigned long *long_buf;
+
+       DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
+       /* if there are any, first copy multiple of 4 bytes */
+       if(bytes_multi) {
+               for(i=0; i<bytes_multi; i+=4) {
+                       long_buf = (unsigned long*) &buf[i];
+                       *long_buf = NDDB;
+               }
+       }
+
+       /* ...then the rest */
+       if(rest) {
+               unsigned long rest_data = NDDB;
+               for(j=0;j<rest; j++)
+                       buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
+       }
+
+       return;
+}
+
+/*
+ * read a word. Not implemented as not used in NAND code.
+ */
+static u16 dfc_read_word(struct mtd_info *mtd)
+{
+       printf("dfc_write_byte: UNIMPLEMENTED.\n");
+       return 0;
+}
+
+/* global var, too bad: mk@tbd: move to ->priv pointer */
+static unsigned long read_buf = 0;
+static int bytes_read = -1;
+
+/*
+ * read a byte from NDDB Because we can only read 4 bytes from NDDB at
+ * a time, we buffer the remaining bytes. The buffer is reset when a
+ * new command is sent to the chip.
+ *
+ * WARNING:
+ * This function is currently only used to read status and id
+ * bytes. For these commands always 8 bytes need to be read from
+ * NDDB. So we read and discard these bytes right now. In case this
+ * function is used for anything else in the future, we must check
+ * what was the last command issued and read the appropriate amount of
+ * bytes respectively.
+ */
+static u_char dfc_read_byte(struct mtd_info *mtd)
+{
+       unsigned char byte;
+       unsigned long dummy;
+
+       if(bytes_read < 0) {
+               read_buf = NDDB;
+               dummy = NDDB;
+               bytes_read = 0;
+       }
+       byte = (unsigned char) (read_buf>>(8 * bytes_read++));
+       if(bytes_read >= 4)
+               bytes_read = -1;
+
+       DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
+       return byte;
+}
+
+/* calculate delta between OSCR values start and now  */
+static unsigned long get_delta(unsigned long start)
+{
+       unsigned long cur = OSCR;
+
+       if(cur < start) /* OSCR overflowed */
+               return (cur + (start^0xffffffff));
+       else
+               return (cur - start);
+}
+
+/* delay function, this doesn't belong here */
+static void wait_us(unsigned long us)
+{
+       unsigned long start = OSCR;
+       us *= OSCR_CLK_FREQ;
+
+       while (get_delta(start) < us) {
+               /* do nothing */
+       }
+}
+
+static void dfc_clear_nddb(void)
+{
+       NDCR &= ~NDCR_ND_RUN;
+       wait_us(CFG_NAND_OTHER_TO);
+}
+
+/* wait_event with timeout */
+static unsigned long dfc_wait_event(unsigned long event)
+{
+       unsigned long ndsr, timeout, start = OSCR;
+
+       if(!event)
+               return 0xff000000;
+       else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
+               timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
+       else
+               timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
+
+       while(1) {
+               ndsr = NDSR;
+               if(ndsr & event) {
+                       NDSR |= event;
+                       break;
+               }
+               if(get_delta(start) > timeout) {
+                       DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
+                       return 0xff000000;
+               }
+
+       }
+       return ndsr;
+}
+
+/* we don't always wan't to do this */
+static void dfc_new_cmd(void)
+{
+       int retry = 0;
+       unsigned long status;
+
+       while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
+               /* Clear NDSR */
+               NDSR = 0xFFF;
+
+               /* set NDCR[NDRUN] */
+               if(!(NDCR & NDCR_ND_RUN))
+                       NDCR |= NDCR_ND_RUN;
+
+               status = dfc_wait_event(NDSR_WRCMDREQ);
+
+               if(status & NDSR_WRCMDREQ)
+                       return;
+
+               DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
+               dfc_clear_nddb();
+       }
+       DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
+}
+
+/* this function is called after Programm and Erase Operations to
+ * check for success or failure */
+static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
+{
+       unsigned long ndsr=0, event=0;
+
+       if(state == FL_WRITING) {
+               event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
+       } else if(state == FL_ERASING) {
+               event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
+       }
+
+       ndsr = dfc_wait_event(event);
+
+       if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
+               return(0x1); /* Status Read error */
+       return 0;
+}
+
+/* cmdfunc send commands to the DFC */
+static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
+                       int column, int page_addr)
+{
+       /* register struct nand_chip *this = mtd->priv; */
+       unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
+
+       /* clear the ugly byte read buffer */
+       bytes_read = -1;
+       read_buf = 0;
+
+       switch (command) {
+       case NAND_CMD_READ0:
+               DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+               dfc_new_cmd();
+               ndcb0 = (NAND_CMD_READ0 | (4<<16));
+               column >>= 1; /* adjust for 16 bit bus */
+               ndcb1 = (((column>>1) & 0xff) |
+                        ((page_addr<<8) & 0xff00) |
+                        ((page_addr<<8) & 0xff0000) |
+                        ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
+               event = NDSR_RDDREQ;
+               goto write_cmd;
+       case NAND_CMD_READ1:
+               DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
+               goto end;
+       case NAND_CMD_READOOB:
+               DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
+               goto end;
+       case NAND_CMD_READID:
+               dfc_new_cmd();
+               DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
+               ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
+               event = NDSR_RDDREQ;
+               goto write_cmd;
+       case NAND_CMD_PAGEPROG:
+               /* sent as a multicommand in NAND_CMD_SEQIN */
+               DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
+               goto end;
+       case NAND_CMD_ERASE1:
+               DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1,  page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+               dfc_new_cmd();
+               ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
+               ndcb1 = (page_addr & 0x00ffffff);
+               goto write_cmd;
+       case NAND_CMD_ERASE2:
+               DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
+               goto end;
+       case NAND_CMD_SEQIN:
+               /* send PAGE_PROG command(0x1080) */
+               dfc_new_cmd();
+               DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG,  page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+               ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
+               column >>= 1; /* adjust for 16 bit bus */
+               ndcb1 = (((column>>1) & 0xff) |
+                        ((page_addr<<8) & 0xff00) |
+                        ((page_addr<<8) & 0xff0000) |
+                        ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
+               event = NDSR_WRDREQ;
+               goto write_cmd;
+       case NAND_CMD_STATUS:
+               DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
+               dfc_new_cmd();
+               ndcb0 = NAND_CMD_STATUS | (4<<21);
+               event = NDSR_RDDREQ;
+               goto write_cmd;
+       case NAND_CMD_RESET:
+               DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
+               ndcb0 = NAND_CMD_RESET | (5<<21);
+               event = NDSR_CS0_CMDD;
+               goto write_cmd;
+       default:
+               printk("dfc_cmdfunc: error, unsupported command.\n");
+               goto end;
+       }
+
+ write_cmd:
+       NDCB0 = ndcb0;
+       NDCB0 = ndcb1;
+       NDCB0 = ndcb2;
+
+       /*  wait_event: */
+       dfc_wait_event(event);
+ end:
+       return;
+}
+
+static void dfc_gpio_init(void)
+{
+       DFC_DEBUG2("Setting up DFC GPIO's.\n");
+
+       /* no idea what is done here, see zylonite.c */
+       GPIO4 = 0x1;
+
+       DF_ALE_WE1 = 0x00000001;
+       DF_ALE_WE2 = 0x00000001;
+       DF_nCS0 = 0x00000001;
+       DF_nCS1 = 0x00000001;
+       DF_nWE = 0x00000001;
+       DF_nRE = 0x00000001;
+       DF_IO0 = 0x00000001;
+       DF_IO8 = 0x00000001;
+       DF_IO1 = 0x00000001;
+       DF_IO9 = 0x00000001;
+       DF_IO2 = 0x00000001;
+       DF_IO10 = 0x00000001;
+       DF_IO3 = 0x00000001;
+       DF_IO11 = 0x00000001;
+       DF_IO4 = 0x00000001;
+       DF_IO12 = 0x00000001;
+       DF_IO5 = 0x00000001;
+       DF_IO13 = 0x00000001;
+       DF_IO6 = 0x00000001;
+       DF_IO14 = 0x00000001;
+       DF_IO7 = 0x00000001;
+       DF_IO15 = 0x00000001;
+
+       DF_nWE = 0x1901;
+       DF_nRE = 0x1901;
+       DF_CLE_NOE = 0x1900;
+       DF_ALE_WE1 = 0x1901;
+       DF_INT_RnB = 0x1900;
+}
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand_new.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for  accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
+ *   only be provided if a hardware ECC is available
+ * - eccmode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ *   read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ *   nand_scan about special functionality. See the defines for further
+ *   explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+void board_nand_init(struct nand_chip *nand)
+{
+       unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
+
+       /* set up GPIO Control Registers */
+       dfc_gpio_init();
+
+       /* turn on the NAND Controller Clock (104 MHz @ D0) */
+       CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+
+#undef CFG_TIMING_TIGHT
+#ifndef CFG_TIMING_TIGHT
+       tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
+                 DFC_MAX_tCH);
+       tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
+                 DFC_MAX_tCS);
+       tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
+                 DFC_MAX_tWH);
+       tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
+                 DFC_MAX_tWP);
+       tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
+                 DFC_MAX_tRH);
+       tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
+                 DFC_MAX_tRP);
+       tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
+                DFC_MAX_tR);
+       tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
+                  DFC_MAX_tWHR);
+       tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
+                 DFC_MAX_tAR);
+#else /* this is the tight timing */
+
+       tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
+                 DFC_MAX_tCH);
+       tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
+                 DFC_MAX_tCS);
+       tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
+                 DFC_MAX_tWH);
+       tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
+                 DFC_MAX_tWP);
+       tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
+                 DFC_MAX_tRH);
+       tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
+                 DFC_MAX_tRP);
+       tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
+                DFC_MAX_tR);
+       tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
+                  DFC_MAX_tWHR);
+       tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
+                 DFC_MAX_tAR);
+#endif /* CFG_TIMING_TIGHT */
+
+
+       DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
+
+       /* tRP value is split in the register */
+       if(tRP & (1 << 4)) {
+               tRP_high = 1;
+               tRP &= ~(1 << 4);
+       } else {
+               tRP_high = 0;
+       }
+
+       NDTR0CS0 = (tCH << 19) |
+               (tCS << 16) |
+               (tWH << 11) |
+               (tWP << 8) |
+               (tRP_high << 6) |
+               (tRH << 3) |
+               (tRP << 0);
+
+       NDTR1CS0 = (tR << 16) |
+               (tWHR << 4) |
+               (tAR << 0);
+
+       /* If it doesn't work (unlikely) think about:
+        *  - ecc enable
+        *  - chip select don't care
+        *  - read id byte count
+        *
+        * Intentionally enabled by not setting bits:
+        *  - dma (DMA_EN)
+        *  - page size = 512
+        *  - cs don't care, see if we can enable later!
+        *  - row address start position (after second cycle)
+        *  - pages per block = 32
+        *  - ND_RDY : clears command buffer
+        */
+       /* NDCR_NCSX |          /\* Chip select busy don't care *\/ */
+
+       NDCR = (NDCR_SPARE_EN |         /* use the spare area */
+               NDCR_DWIDTH_C |         /* 16bit DFC data bus width  */
+               NDCR_DWIDTH_M |         /* 16 bit Flash device data bus width */
+               (2 << 16) |             /* read id count = 7 ???? mk@tbd */
+               NDCR_ND_ARB_EN |        /* enable bus arbiter */
+               NDCR_RDYM |             /* flash device ready ir masked */
+               NDCR_CS0_PAGEDM |       /* ND_nCSx page done ir masked */
+               NDCR_CS1_PAGEDM |
+               NDCR_CS0_CMDDM |        /* ND_CSx command done ir masked */
+               NDCR_CS1_CMDDM |
+               NDCR_CS0_BBDM |         /* ND_CSx bad block detect ir masked */
+               NDCR_CS1_BBDM |
+               NDCR_DBERRM |           /* double bit error ir masked */
+               NDCR_SBERRM |           /* single bit error ir masked */
+               NDCR_WRDREQM |          /* write data request ir masked */
+               NDCR_RDDREQM |          /* read data request ir masked */
+               NDCR_WRCMDREQM);        /* write command request ir masked */
+
+
+       /* wait 10 us due to cmd buffer clear reset */
+       /*      wait(10); */
+
+
+       nand->hwcontrol = dfc_hwcontrol;
+/*     nand->dev_ready = dfc_device_ready; */
+       nand->eccmode = NAND_ECC_SOFT;
+       nand->options = NAND_BUSWIDTH_16;
+       nand->waitfunc = dfc_wait;
+       nand->read_byte = dfc_read_byte;
+       nand->write_byte = dfc_write_byte;
+       nand->read_word = dfc_read_word;
+       nand->write_word = dfc_write_word;
+       nand->read_buf = dfc_read_buf;
+       nand->write_buf = dfc_write_buf;
+
+       nand->cmdfunc = dfc_cmdfunc;
+       nand->autooob = &delta_oob;
+       nand->badblock_pattern = &delta_bbt_descr;
+}
+
+#else
+ #error "U-Boot legacy NAND support not available for Monahans DFC."
+#endif
+#endif

diff --git a/board/delta/u-boot.lds b/board/delta/u-boot.lds
new file mode 100644 (file)
index 0000000..f010239
--- /dev/null
+++ b/board/delta/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text      :
+       {
+         cpu/pxa/start.o       (.text)
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data : { *(.data) }
+
+       . = ALIGN(4);
+       .got : { *(.got) }
+
+       . = .;
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       __bss_start = .;
+       .bss : { *(.bss) }
+       _end = .;
+}

diff --git a/board/dnp1110/dnp1110.c b/board/dnp1110/dnp1110.c
index 24c3e00c7f57ae423d90f856b3b4b74650e8f5f8..ab8e7beb99b0e2a9d9f3408f313360cc11cc53f9 100644 (file)
--- a/board/dnp1110/dnp1110.c
+++ b/board/dnp1110/dnp1110.c
@@ -24,8 +24,8 @@
 
 #include <common.h>
 #include <SA-1100.h>
-/* ------------------------------------------------------------------------- */
 
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -33,25 +33,21 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* memory and cpu-speed are setup before relocation */
        /* so we do _nothing_ here */
 
        /* arch number of DNP1110-Board */
        gd->bd->bi_arch_number = MACH_TYPE_DNP1110;
 
-    /* flash vpp on */
-    PPDR |= 0x80;      /* assumes LCD controller is off */
-    PPSR |= 0x80;
+       /* flash vpp on */
+       PPDR |= 0x80;   /* assumes LCD controller is off */
+       PPSR |= 0x80;
 
        return 0;
 }
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/eltec/bab7xx/bab7xx.c b/board/eltec/bab7xx/bab7xx.c
index fc48ed547e707fe41d3871d4ddeadc90f2962eb0..555475e4d9c5872a3d52bc3f9465def4aa88466c 100644 (file)
--- a/board/eltec/bab7xx/bab7xx.c
+++ b/board/eltec/bab7xx/bab7xx.c
@@ -31,6 +31,8 @@
 #include <ns87308.h>
 #include <video_fb.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*---------------------------------------------------------------------------*/
 /*
  * Get Bus clock frequency
@@ -169,8 +171,6 @@ long int initdram (int board_type)
 
 void after_reloc (ulong dest_addr)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /*
         * Jump to the main U-Boot board init code
         */

diff --git a/board/eltec/elppc/elppc.c b/board/eltec/elppc/elppc.c
index a9dbeb209599eb71978253afdb72e45ae5b1616a..108adb13d5fb70c4d9ab79973756e562ba43c6ee 100644 (file)
--- a/board/eltec/elppc/elppc.c
+++ b/board/eltec/elppc/elppc.c
@@ -26,6 +26,8 @@
 #include <mpc106.h>
 #include <video_fb.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 int checkboard (void)
@@ -137,8 +139,6 @@ void watchdog_reset (void)
 
 void after_reloc (ulong dest_addr)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /*
         * Jump to the main U-Boot board init code
         */

diff --git a/board/ep7312/ep7312.c b/board/ep7312/ep7312.c
index 11eab234bce967bbfe19660b8c57d8a1ab02d2a3..6968a5dbdd11d41404dacfd3ae533e1cd281c7b9 100644 (file)
--- a/board/ep7312/ep7312.c
+++ b/board/ep7312/ep7312.c
@@ -25,8 +25,7 @@
 #include <common.h>
 #include <clps7111.h>
 
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -34,8 +33,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Activate LED flasher */
        IO_LEDFLSH = 0x40;
 
@@ -50,8 +47,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/ep88x/Makefile b/board/ep88x/Makefile
new file mode 100644 (file)
index 0000000..9123a80
--- /dev/null
+++ b/board/ep88x/Makefile
@@ -0,0 +1,46 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   := $(BOARD).o
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

diff --git a/board/ep88x/config.mk b/board/ep88x/config.mk
new file mode 100644 (file)
index 0000000..72b326c
--- /dev/null
+++ b/board/ep88x/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2005 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Embedded Planet EP88x boards
+#
+TEXT_BASE = 0xFC000000

diff --git a/board/ep88x/ep88x.c b/board/ep88x/ep88x.c
new file mode 100644 (file)
index 0000000..5f57f36
--- /dev/null
+++ b/board/ep88x/ep88x.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2005 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Embedded Planet EP88x boards.
+ * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*
+ * SDRAM uses two Micron chips.
+ * Minimal CPU frequency is 40MHz.
+ */
+static uint sdram_table[] = {
+       /* Single read  (offset 0x00 in UPM RAM) */
+       0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404,
+       0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+       /* Burst read   (offset 0x08 in UPM RAM) */
+       0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404,
+       0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00,
+       0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+       0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+       /* Single write (offset 0x18 in UPM RAM) */
+       0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404,
+       0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+       /* Burst write  (offset 0x20 in UPM RAM) */
+       0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400,
+       0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05,
+       0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+       0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
+
+       /* Refresh      (offset 0x30 in UPM RAM) */
+       0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04,
+       0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34,
+       0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4,
+
+       /* Exception    (offset 0x3C in UPM RAM) */
+       0x0FEA8034, 0x1FB54034, 0xFFFFCC34, 0xFFFFCC05
+};
+
+int board_early_init_f (void)
+{
+       vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+       bcsr[0] |= 0x0C; /* Turn the LEDs off */
+       bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for
+                           flash detection by CFI driver
+                        */
+
+#if defined(CONFIG_8xx_CONS_SMC1)
+       bcsr[6] |= 0x10; /* Enables RS-232 transceiver */
+#endif
+#if defined(CONFIG_8xx_CONS_SCC2)
+       bcsr[7] |= 0x10; /* Enables RS-232 transceiver */
+#endif
+#ifdef CONFIG_ETHER_ON_FEC1
+       bcsr[8] |= 0xC0; /* Enable Ethernet 1 PHY */
+#endif
+#ifdef CONFIG_ETHER_ON_FEC2
+       bcsr[8] |= 0x30; /* Enable Ethernet 2 PHY */
+#endif
+
+       return 0;
+}
+
+long int initdram (int board_type)
+{
+       long int msize;
+       volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;
+       volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+       upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+       /* Configure SDRAM refresh */
+       memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */
+
+       memctl->memc_mamr = (65 << 24) | CFG_MAMR; /* No refresh */
+       udelay(100);
+
+       /* Run MRS pattern from location 0x36 */
+       memctl->memc_mar = 0x88;
+       memctl->memc_mcr = 0x80002236;
+       udelay(100);
+
+       memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
+       memctl->memc_or1   = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
+       memctl->memc_br1   =  CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
+
+       msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
+       memctl->memc_or1  |= ~(msize - 1);
+
+       return msize;
+}
+
+int checkboard( void )
+{
+       vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+       puts("Board: ");
+       switch (bcsr[15]) {
+       case 0xE7:
+               puts("EP88xC 1.0");
+               break;
+       default:
+               printf("unknown ID=%02X", bcsr[15]);
+       }
+       printf("  CPLD revision %d\n", bcsr[14]);
+
+       return 0;
+}

diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds
new file mode 100644 (file)
index 0000000..1d2a7d7
--- /dev/null
+++ b/board/ep88x/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp        : { *(.interp)                }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)      }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)      }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)       }
+  .rela.got      : { *(.rela.got)      }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)       }
+  .rela.bss      : { *(.rela.bss)      }
+  .rel.plt       : { *(.rel.plt)       }
+  .rela.plt      : { *(.rela.plt)      }
+  .init          : { *(.init)          }
+  .plt           : { *(.plt)           }
+  .text          :
+  {
+    cpu/mpc8xx/start.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)

diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
index 4b2b07a39303dd6c9564eeb261b98b69f1b0ca22..078df001e95cdf7307532818222350bd65413b10 100644 (file)
--- a/board/esd/apc405/apc405.c
+++ b/board/esd/apc405/apc405.c
@@ -26,7 +26,7 @@
 #include <command.h>
 #include <malloc.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
 
 #if 0
 #define FPGA_DEBUG
@@ -166,8 +166,6 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile unsigned short *fpga_mode =
                (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
        volatile unsigned short *fpga_ctrl2 =
@@ -301,8 +299,6 @@ int misc_init_r (void)
 
 int checkboard (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned char str[64];
        int i = getenv_r ("serial#", str, sizeof(str));
 

diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c
index 3aac3c6732936ce5a12807d83ee25db2c542ef67..dfead3363c208a0eb95068cb1f41fb7f40f23335 100644 (file)
--- a/board/esd/ar405/ar405.c
+++ b/board/esd/ar405/ar405.c
@@ -26,6 +26,8 @@
 #include <asm/processor.h>
 #include <command.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*cmd_boot.c*/
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 extern void lxt971_no_sleep(void);
@@ -53,8 +55,6 @@ const unsigned char fpgadata_xl30[] = {
 
 int board_early_init_f (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int index, len, i;
        int status;
 
@@ -151,8 +151,6 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int index;
        int len;
        char str[64];

diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c
index 03ae7fda4bfd3bd0dddb49dd316159c26a0029c5..84fc3a01dc21e6e684b04c02b34ac5ea1c68c2b6 100644 (file)
--- a/board/esd/ash405/ash405.c
+++ b/board/esd/ash405/ash405.c
@@ -239,7 +239,7 @@ int testdram (void)
 /* ------------------------------------------------------------------------- */
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 
 void nand_init(void)

diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c
index 2ced6cb17f282767fbf8aad2a658a165da19f2aa..055a39773061ac05cb8839d07b4d8d1a0430e701 100644 (file)
--- a/board/esd/canbt/canbt.c
+++ b/board/esd/canbt/canbt.c
@@ -26,6 +26,7 @@
 #include <asm/processor.h>
 #include <command.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 /*cmd_boot.c*/
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
@@ -50,8 +51,6 @@ const unsigned char fpgadata[] = {
 
 int board_early_init_f (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long cntrl0Reg;
        int index, len, i;
        int status;

diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
index 649619d45406e65d1a47c8c3c6e5915dcdead73b..cb04710737426121fe203211b755bda849df039e 100644 (file)
--- a/board/esd/cms700/cms700.c
+++ b/board/esd/cms700/cms700.c
@@ -26,10 +26,10 @@
 #include <command.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 extern void lxt971_no_sleep(void);
 
-
 /* fpga configuration data - not compressed, generated by bin2c */
 const unsigned char fpgadata[] =
 {
@@ -87,8 +87,6 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* adjust flash start and offset */
        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
        gd->bd->bi_flashoffset = 0;
@@ -114,7 +112,7 @@ int misc_init_r (void)
 
 int checkboard (void)
 {
-       unsigned char str[64];
+       char str[64];
        int flashcnt;
        int delay;
        volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000);
@@ -238,7 +236,7 @@ U_BOOT_CMD(eepwren, 2,      0,      do_eep_wren,
 /* ------------------------------------------------------------------------- */
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 
 void nand_init(void)

diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
index d48e97286669030b4c1a02879066e16bc7f0be59..5cd342332f51fd3bdb6a3ab9e1c239e1f4430cc7 100644 (file)
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -23,10 +23,15 @@
  */
 
 #include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
+#warning CFG_NAND_LEGACY not defined in a file using the legacy NAND support!
+#endif
+
 #include <command.h>
 #include <image.h>
 #include <asm/byteorder.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 #include <fat.h>
 
 #include "auto_update.h"
@@ -69,17 +74,17 @@ extern int flash_write (char *, ulong, ulong);
 /* change char* to void* to shutup the compiler */
 extern block_dev_desc_t *get_dev (char*, int);
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
 /* references to names in cmd_nand.c */
 #define NANDRW_READ    0x01
 #define NANDRW_WRITE   0x00
 #define NANDRW_JFFS2   0x02
 #define NANDRW_JFFS2_SKIP      0x04
 extern struct nand_chip nand_dev_desc[];
-extern int nand_rw(struct nand_chip* nand, int cmd, size_t start, size_t len,
+extern int nand_legacy_rw(struct nand_chip* nand, int cmd, size_t start, size_t len,
                   size_t * retlen, u_char * buf);
-extern int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean);
-#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
+extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean);
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) */
 
 extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE];
 
@@ -183,7 +188,7 @@ int au_do_update(int i, long sz)
        int off, rc;
        uint nbytes;
        int k;
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
        int total;
 #endif
 
@@ -257,11 +262,11 @@ int au_do_update(int i, long sz)
                        debug ("flash_sect_erase(%lx, %lx);\n", start, end);
                        flash_sect_erase(start, end);
                } else {
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
                        printf("Updating NAND FLASH with image %s\n", au_image[i].name);
-                       debug ("nand_erase(%lx, %lx);\n", start, end);
-                       rc = nand_erase (nand_dev_desc, start, end - start + 1, 0);
-                       debug ("nand_erase returned %x\n", rc);
+                       debug ("nand_legacy_erase(%lx, %lx);\n", start, end);
+                       rc = nand_legacy_erase (nand_dev_desc, start, end - start + 1, 0);
+                       debug ("nand_legacy_erase returned %x\n", rc);
 #endif
                }
 
@@ -283,13 +288,13 @@ int au_do_update(int i, long sz)
                 */
                if (au_image[i].type != AU_NAND) {
                        debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
-                       rc = flash_write((uchar *)addr, start, nbytes);
+                       rc = flash_write((char *)addr, start, nbytes);
                } else {
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-                       debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes);
-                       rc = nand_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+                       debug ("nand_legacy_rw(%p, %lx %x)\n", addr, start, nbytes);
+                       rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
                                     start, nbytes, (size_t *)&total, (uchar *)addr);
-                       debug ("nand_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
+                       debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
 #endif
                }
                if (rc != 0) {
@@ -303,8 +308,8 @@ int au_do_update(int i, long sz)
                if (au_image[i].type != AU_NAND) {
                        rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size));
                } else {
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-                       rc = nand_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP,
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+                       rc = nand_legacy_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP,
                                     start, nbytes, (size_t *)&total, (uchar *)addr);
                        rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size));
 #endif

diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c
new file mode 100644 (file)
index 0000000..bf796ff
--- /dev/null
+++ b/board/esd/common/cmd_loadpci.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
+extern int do_autoscript (cmd_tbl_t *, int, int, char *[]);
+
+#define ADDRMASK 0xfffff000
+
+/*
+ * Command loadpci: wait for signal from host and boot image.
+ */
+int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+       unsigned int *ptr = 0;
+       int count = 0;
+       int count2 = 0;
+       char addr[16];
+       char str[] = "\\|/-";
+       char *local_args[2];
+
+       while(1) {
+               /*
+                * Mark sync address
+                */
+               ptr = 0;
+               memset(ptr, 0, 0x20);
+
+               *ptr = 0xffffffff;
+               puts("\nWaiting for action from pci host -");
+
+               /*
+                * Wait for host to write the start address
+                */
+               while (*ptr == 0xffffffff) {
+                       count++;
+                       if (!(count % 100)) {
+                               count2++;
+                               putc(0x08); /* backspace */
+                               putc(str[count2 % 4]);
+                       }
+
+                       /* Abort if ctrl-c was pressed */
+                       if (ctrlc()) {
+                               puts("\nAbort\n");
+                               return 0;
+                       }
+
+                       udelay(1000);
+               }
+
+               printf("\nGot bootcode %08x: ", *ptr);
+               sprintf(addr, "%08x", *ptr & ADDRMASK);
+
+               switch (*ptr & ~ADDRMASK) {
+               case 0:
+                       /*
+                        * Boot image via bootm
+                        */
+                       printf("booting image at addr 0x%s ...\n", addr);
+                       setenv("loadaddr", addr);
+
+                       do_bootm (cmdtp, 0, 0, NULL);
+                       break;
+
+               case 1:
+                       /*
+                        * Boot image via autoscr
+                        */
+                       printf("executing script at addr 0x%s ...\n", addr);
+
+                       local_args[0] = addr;
+                       local_args[1] = NULL;
+                       do_autoscript(cmdtp, 0, 1, local_args);
+                       break;
+
+               case 2:
+                       /*
+                        * Call run_cmd
+                        */
+                       printf("running command at addr 0x%s ...\n", addr);
+                       run_command ((char*)(*ptr & ADDRMASK), 0);
+                       break;
+
+               default:
+                       printf("unhandled boot method\n");
+                       break;
+               }
+       }
+}
+
+U_BOOT_CMD(
+       loadpci,        1,      1,      do_loadpci,
+       "loadpci - Wait for pci bootcmd and boot it\n",
+       NULL
+       );
+
+#endif

diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c
index 0edc08308a1320d0bc7db82e54d5443988ee7d34..196171ce5aa9dab779def53adb4952fa47352765 100644 (file)
--- a/board/esd/common/lcd.c
+++ b/board/esd/common/lcd.c
@@ -229,6 +229,9 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
        /*
         * Detect epson
         */
+       lcd_reg[0] = 0x00;
+       lcd_reg[1] = 0x00;
+
        if (lcd_reg[0] == 0x1c) {
                /*
                 * Big epson detected

diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile
index a60495a59aa0b4d6e1225072884f4cd8f698cd5b..88b0ae3435ec76072e2ac7e7e386cb409764982f 100644 (file)
--- a/board/esd/cpci2dp/Makefile
+++ b/board/esd/cpci2dp/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = lib$(BOARD).a
 
-OBJS   = $(BOARD).o flash.o ../common/misc.o
+OBJS   = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o
 
 $(LIB):        $(OBJS) $(SOBJS)
        $(AR) crv $@ $(OBJS)

diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c
index df10c0e6aa37805d5087eae592b75aaffd586916..36bf329f8192f8962159f3caaa22b7aea955b746 100644 (file)
--- a/board/esd/cpci2dp/cpci2dp.c
+++ b/board/esd/cpci2dp/cpci2dp.c
@@ -26,22 +26,22 @@
 #include <command.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int board_early_init_f (void)
 {
        unsigned long cntrl0Reg;
 
        /*
-        * Setup GPIO pins (CS4+CS7 as GPIO)
+        * Setup GPIO pins
         */
        cntrl0Reg = mfdcr(cntrl0);
-       mtdcr(cntrl0, cntrl0Reg | 0x00900000);
+       mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5));
 
        /* set output pins to high */
-       out32(GPIO0_OR,  CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED);
-       /* INTA# is open drain */
-       out32(GPIO0_ODR, CFG_INTA_FAKE);
-       /* setup for output */
-       out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP);
+       out32(GPIO0_OR,  CFG_EEPROM_WP);
+       /* setup for output (LED=off) */
+       out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED);
 
        /*
         * IRQ 0-15  405GP internally generated; active high; level sensitive
@@ -76,7 +76,6 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned long cntrl0Reg;
 
        /* adjust flash start and offset */
@@ -130,16 +129,6 @@ long int initdram (int board_type)
 
 /* ------------------------------------------------------------------------- */
 
-int testdram (void)
-{
-       /* TODO: XXX XXX XXX */
-       printf ("test: 64 MB - ok\n");
-
-       return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
 #if defined(CFG_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
  *        <state>     -1: deliver current state
@@ -207,8 +196,8 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }
 
 U_BOOT_CMD(
-          eepwren,     2,      0,      do_eep_wren,
-          "eepwren - Enable / disable / query EEPROM write access\n",
-          NULL
-          );
+       eepwren,        2,      0,      do_eep_wren,
+       "eepwren - Enable / disable / query EEPROM write access\n",
+       NULL
+       );
 #endif /* #if defined(CFG_EEPROM_WREN) */

diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index 2ab96731e04138181ede471b992e36c5ead969d2..f80361081a6c080d6011a5fa168724515f8fea3e 100644 (file)
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -27,7 +27,8 @@
 #include <malloc.h>
 #include <net.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
+
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);       /*cmd_boot.c*/
 #if 0
 #define FPGA_DEBUG
@@ -100,8 +101,6 @@ int board_early_init_f (void)
 #endif
 
 #ifdef FPGA_DEBUG
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* set up serial port with default baudrate */
        (void) get_clocks ();
        gd->baudrate = CONFIG_BAUDRATE;
@@ -126,8 +125,6 @@ int board_early_init_f (void)
                if (status != 0) {
                        /* booting FPGA failed */
 #ifndef FPGA_DEBUG
-                       DECLARE_GLOBAL_DATA_PTR;
-
                        /* set up serial port with default baudrate */
                        (void) get_clocks ();
                        gd->baudrate = CONFIG_BAUDRATE;
@@ -268,7 +265,6 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned long cntrl0Reg;
 
        /* adjust flash start and offset */
@@ -707,8 +703,6 @@ U_BOOT_CMD(
  */
 int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        bd_t *bd = gd->bd;
        char *buf;
        ulong crc;

diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile
index 04867295ccc07fafabf76b1222b84a5b5f578687..cd38b2d8d8173925767ae495ba5bad3f4649fa78 100644 (file)
--- a/board/esd/cpci750/Makefile
+++ b/board/esd/cpci750/Makefile
@@ -29,7 +29,7 @@ SOBJS = misc.o
 
 OBJS   = $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \
          mv_eth.o  mpsc.o i2c.o \
-         sdram_init.o strataflash.o ide.o
+         sdram_init.o ide.o
 
 $(LIB):        .depend $(OBJS) $(SOBJS)
        $(AR) crv $@ $(OBJS) $(SOBJS)

diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index e4b062bdd04f206b367af9f4e24d94519c7dfd92..dbed5971738324d24a63f9a750958c117533fb09 100644 (file)
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -56,6 +56,7 @@
 
 extern void flush_data_cache (void);
 extern void invalidate_l1_instruction_cache (void);
+extern flash_info_t flash_info[];
 
 /* ------------------------------------------------------------------------- */
 
@@ -363,6 +364,21 @@ int misc_init_r ()
        /* disable the dcache and MMU */
        dcache_lock ();
 #endif
+       if (flash_info[3].size < CFG_FLASH_INCREMENT) {
+               unsigned int flash_offset;
+               unsigned int l;
+
+               flash_offset =  CFG_FLASH_INCREMENT - flash_info[3].size;
+               for (l = 0; l < CFG_MAX_FLASH_SECT; l++) {
+                       if (flash_info[3].start[l] != 0) {
+                             flash_info[3].start[l] += flash_offset;
+                       }
+               }
+               flash_protect (FLAG_PROTECT_SET,
+                              CFG_MONITOR_BASE,
+                              CFG_MONITOR_BASE + monitor_flash_len  - 1,
+                              &flash_info[3]);
+       }
        return 0;
 }
 

diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c
index 52398b24ea41665c1f3cd4f66b7de9a0c29d12aa..25c10e062ebfe403e9d142d7ff9d5f76ccf94c20 100644 (file)
--- a/board/esd/cpci750/mpsc.c
+++ b/board/esd/cpci750/mpsc.c
@@ -42,6 +42,8 @@
 
 #include "../../Marvell/include/memory.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Define this if you wish to use the MPSC as a register based UART.
  * This will force the serial port to not use the SDMA engine at all.
  */
@@ -157,7 +159,6 @@ char mpsc_getchar_debug (void)
  * global variables [josh] */
 int mpsc_putchar_early (char ch)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int mpsc = CHANNEL;
        int temp =
                GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
@@ -510,7 +511,6 @@ void mpsc_init2 (void)
 
 int galbrg_set_baudrate (int channel, int rate)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int clock;
 
        galbrg_disable (channel);       /*ok */

diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c
index be176dcc845693f150dba3dda4e01ebccbd5ea04..bc84ef08e6905b12b1bc2583abc5ed9e7a60c53d 100644 (file)
--- a/board/esd/cpci750/mv_eth.c
+++ b/board/esd/cpci750/mv_eth.c
@@ -733,6 +733,7 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
        pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;        /* DMA owned, first last */
        pkt_info.byte_cnt = dataSize;
        pkt_info.buf_ptr = (unsigned int) dataPtr;
+       pkt_info.return_info = 0;
 
        status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
        if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {

diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c
index 3e44fb97376b0f9c371c1db9be168d6d1a9b6d7f..c335ebf0bf83209b9bbf9965ddbf72ad4d0c799b 100644 (file)
--- a/board/esd/cpci750/pci.c
+++ b/board/esd/cpci750/pci.c
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -44,6 +44,14 @@ static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
        {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
 };
 
+#ifdef CONFIG_USE_CPCIDVI
+typedef struct {
+       unsigned int base;
+       unsigned int init;
+} GT_CPCIDVI_ROM_T;
+
+static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
+#endif
 
 #ifdef DEBUG
 static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
@@ -125,20 +133,20 @@ static const unsigned int pci_p2p_configuration[] = {
 
 /********************************************************************
 * pciWriteConfigReg - Write to a PCI configuration register
-*                    - Make sure the GT is configured as a master before writing
-*                      to another device on the PCI.
-*                    - The function takes care of Big/Little endian conversion.
+*                  - Make sure the GT is configured as a master before writing
+*                    to another device on the PCI.
+*                  - The function takes care of Big/Little endian conversion.
 *
 *
 * Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
-*                   (or any other PCI device spec)
-*           pciDevNum: The device number needs to be addressed.
+*                 (or any other PCI device spec)
+*          pciDevNum: The device number needs to be addressed.
 *
 *  Configuration Address 0xCF8:
 *
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*      31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 *  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*  |Enable|       |Number|Number| Number | Number |  |    <=field Name
 *
 *********************************************************************/
 void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
@@ -172,20 +180,20 @@ void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
 
 /********************************************************************
 * pciReadConfigReg  - Read from a PCI0 configuration register
-*                    - Make sure the GT is configured as a master before reading
-*                     from another device on the PCI.
-*                   - The function takes care of Big/Little endian conversion.
+*                  - Make sure the GT is configured as a master before reading
+*                    from another device on the PCI.
+*                  - The function takes care of Big/Little endian conversion.
 * INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*                        spec)
-*           pciDevNum: The device number needs to be addressed.
+*                      spec)
+*          pciDevNum: The device number needs to be addressed.
 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-*                 cause register to make sure the data is valid
+*                cause register to make sure the data is valid
 *
 *  Configuration Address 0xCF8:
 *
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*      31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 *  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*  |Enable|       |Number|Number| Number | Number |  |    <=field Name
 *
 *********************************************************************/
 unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
@@ -220,21 +228,21 @@ unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
 
 /********************************************************************
 * pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
-*                               the agent is placed on another Bus. For more
-*                               information read P2P in the PCI spec.
+*                              the agent is placed on another Bus. For more
+*                              information read P2P in the PCI spec.
 *
 * Inputs:   unsigned int regOffset - The register offset as it apears in the
-*           GT spec (or any other PCI device spec).
-*           unsigned int pciDevNum - The device number needs to be addressed.
-*           unsigned int busNum - On which bus does the Target agent connect
-*                                 to.
-*           unsigned int data - data to be written.
+*          GT spec (or any other PCI device spec).
+*          unsigned int pciDevNum - The device number needs to be addressed.
+*          unsigned int busNum - On which bus does the Target agent connect
+*                                to.
+*          unsigned int data - data to be written.
 *
 *  Configuration Address 0xCF8:
 *
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*      31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 *  |congif|Reserved|  Bus |Device|Function|Register|01|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*  |Enable|       |Number|Number| Number | Number |  |    <=field Name
 *
 *  The configuration Address is configure as type-I (bits[1:0] = '01') due to
 *   PCI spec referring to P2P.
@@ -265,23 +273,23 @@ void pciOverBridgeWriteConfigReg (PCI_HOST host,
 
 /********************************************************************
 * pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
-*                               the agent target locate on another PCI bus.
-*                             - Make sure the GT is configured as a master
-*                               before reading from another device on the PCI.
-*                             - The function takes care of Big/Little endian
-*                               conversion.
+*                              the agent target locate on another PCI bus.
+*                            - Make sure the GT is configured as a master
+*                              before reading from another device on the PCI.
+*                            - The function takes care of Big/Little endian
+*                              conversion.
 * INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*                        spec). (configuration register offset.)
-*           pciDevNum: The device number needs to be addressed.
-*           busNum: the Bus number where the agent is place.
+*                       spec). (configuration register offset.)
+*          pciDevNum: The device number needs to be addressed.
+*          busNum: the Bus number where the agent is place.
 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-*                 cause register to make sure the data is valid
+*                cause register to make sure the data is valid
 *
 *  Configuration Address 0xCF8:
 *
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*      31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
 *  |congif|Reserved|  Bus |Device|Function|Register|01|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*  |Enable|       |Number|Number| Number | Number |  |    <=field Name
 *
 *********************************************************************/
 unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
@@ -385,7 +393,7 @@ static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
 
 /********************************************************************
 * pciGetBaseAddress - Gets the base address of a PCI.
-*           - If the PCI size is 0 then this base address has no meaning!!!
+*          - If the PCI size is 0 then this base address has no meaning!!!
 *
 *
 * INPUT:   Bus, Region - The bus and region we ask for its base address.
@@ -493,13 +501,13 @@ void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
 
 /********************************************************************
 * pciSetRegionFeatures - This function modifys one of the 8 regions with
-*                         feature bits given as an input.
-*                       - Be advised to check the spec before modifying them.
+*                        feature bits given as an input.
+*                      - Be advised to check the spec before modifying them.
 * Inputs: PCI_PROTECT_REGION region - one of the eight regions.
-*         unsigned int features - See file: pci.h there are defintion for those
-*                                 region features.
-*         unsigned int baseAddress - The region base Address.
-*         unsigned int topAddress - The region top Address.
+*        unsigned int features - See file: pci.h there are defintion for those
+*                                region features.
+*        unsigned int baseAddress - The region base Address.
+*        unsigned int topAddress - The region top Address.
 * Returns: false if one of the parameters is erroneous true otherwise.
 *********************************************************************/
 bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
@@ -533,7 +541,7 @@ bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
 
 /********************************************************************
 * pciDisableAccessRegion - Disable The given Region by writing MAX size
-*                           to its low Address and MIN size to its high Address.
+*                          to its low Address and MIN size to its high Address.
 *
 * Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
 * Returns:  N/A.
@@ -580,12 +588,12 @@ bool pciArbiterDisable (PCI_HOST host)
 * pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
 *
 * Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
-*           PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
-*           PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
-*           PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
-*           PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
-*           PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
-*           PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
+*          PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
+*          PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
+*          PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
+*          PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
+*          PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
+*          PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
 * Returns:  true
 *********************************************************************/
 bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
@@ -611,17 +619,17 @@ bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
 
 /********************************************************************
 * pciParkingDisable - Park on last option disable, with this function you can
-*                      disable the park on last mechanism for each agent.
-*                      disabling this option for all agents results parking
-*                      on the internal master.
+*                     disable the park on last mechanism for each agent.
+*                     disabling this option for all agents results parking
+*                     on the internal master.
 *
 * Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
-*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
-*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
-*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
-*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
-*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
-*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+*        PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+*        PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+*        PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+*        PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+*        PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+*        PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
 * Returns:  true
 *********************************************************************/
 bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
@@ -647,11 +655,11 @@ bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
 
 /********************************************************************
 * pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
-*                       respond to grant assertion within a window specified in
-*                       the input value: 'brokenValue'.
+*                      respond to grant assertion within a window specified in
+*                      the input value: 'brokenValue'.
 *
 * Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
-*                       grant without asserting frame.
+*                      grant without asserting frame.
 * Returns:  Error for illegal broken value otherwise true.
 *********************************************************************/
 bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
@@ -670,9 +678,9 @@ bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
 
 /********************************************************************
 * pciDisableBrokenAgentDetection - This function disable the Broken agent
-*                           Detection mechanism.
-*                           NOTE: This operation may cause a dead lock on the
-*                           pci0 arbitration.
+*                          Detection mechanism.
+*                          NOTE: This operation may cause a dead lock on the
+*                          pci0 arbitration.
 *
 * Inputs:   N/A
 * Returns:  true.
@@ -689,15 +697,15 @@ bool pciDisableBrokenAgentDetection (PCI_HOST host)
 
 /********************************************************************
 * pciP2PConfig - This function set the PCI_n P2P configurate.
-*                 For more information on the P2P read PCI spec.
+*                For more information on the P2P read PCI spec.
 *
 * Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
-*                                      Boundry.
-*          unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
-*                                      Boundry.
-*          unsigned int busNum - The CPI bus number to which the PCI interface
-*                                      is connected.
-*          unsigned int devNum - The PCI interface's device number.
+*                                     Boundry.
+*         unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
+*                                     Boundry.
+*         unsigned int busNum - The CPI bus number to which the PCI interface
+*                                     is connected.
+*         unsigned int devNum - The PCI interface's device number.
 *
 * Returns:  true.
 *********************************************************************/
@@ -715,15 +723,15 @@ bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
 
 /********************************************************************
 * pciSetRegionSnoopMode - This function modifys one of the 4 regions which
-*                          supports Cache Coherency in the PCI_n interface.
+*                         supports Cache Coherency in the PCI_n interface.
 * Inputs: region - One of the four regions.
-*         snoopType - There is four optional Types:
-*                        1. No Snoop.
-*                        2. Snoop to WT region.
-*                        3. Snoop to WB region.
-*                        4. Snoop & Invalidate to WB region.
-*         baseAddress - Base Address of this region.
-*         regionLength - Region length.
+*        snoopType - There is four optional Types:
+*                       1. No Snoop.
+*                       2. Snoop to WT region.
+*                       3. Snoop to WB region.
+*                       4. Snoop & Invalidate to WB region.
+*        baseAddress - Base Address of this region.
+*        regionLength - Region length.
 * Returns: false if one of the parameters is wrong otherwise return true.
 *********************************************************************/
 bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
@@ -746,7 +754,7 @@ bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
                GT_REG_WRITE (snoopXtopAddress, 0);
                return true;
        }
-       baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
+       baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
        data = (baseAddress >> 20) | snoopType << 12;
        GT_REG_WRITE (snoopXbaseAddress, data);
        snoopHigh = (snoopHigh & 0xfff00000) >> 20;
@@ -800,23 +808,65 @@ static void gt_setup_ide (struct pci_controller *hose,
                unsigned int offset =
                        (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
 
-               pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
-                                       0x0);
-               pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
-                                      &bar_response);
+               pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
+                                            0x0);
+               pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
+                                           &bar_response);
 
                pciauto_region_allocate (bar_response &
                                         PCI_BASE_ADDRESS_SPACE_IO ? hose->
                                         pci_io : hose->pci_mem, ide_bar[bar],
                                         &bar_value);
 
-               pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
-                                       bar_value);
+               pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
+                                            bar_value);
        }
 }
 
+#ifdef CONFIG_USE_CPCIDVI
+static void gt_setup_cpcidvi (struct pci_controller *hose,
+                             pci_dev_t dev, struct pci_config_table *entry)
+{
+       u32               bar_value, pci_response;
+
+       pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
+       pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
+       pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
+       pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
+       pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
+       pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
+       pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
+       pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
+       gt_cpcidvi_rom.base = bar_value & 0xffffff00;
+       gt_cpcidvi_rom.init = 1;
+}
+
+unsigned char gt_cpcidvi_in8(unsigned int offset)
+{
+       unsigned char     data;
+
+       if (gt_cpcidvi_rom.init == 0) {
+               return(0);
+               }
+       data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
+       return(data);
+}
+
+void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
+{
+       unsigned int      off;
 
-/* TODO BJW: Change this for DB64360. This was pulled from the EV64260  */
+       if (gt_cpcidvi_rom.init == 0) {
+               return;
+       }
+       off = data;
+       off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
+       in8(off);
+       return;
+}
+#endif
+
+/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
 /* and is curently not called *. */
 #if 0
 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
@@ -835,9 +885,12 @@ static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 #endif
 
 struct pci_config_table gt_config_table[] = {
+#ifdef CONFIG_USE_CPCIDVI
+       {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
+        PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
+#endif
        {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
         PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
-
        {}
 };
 
@@ -857,10 +910,21 @@ void pci_init_board (void)
 #ifdef CONFIG_PCI_PNP
        unsigned int bar;
 #endif
-
 #ifdef DEBUG
        gt_pci_bus_mode_display (PCI_HOST0);
 #endif
+#ifdef CONFIG_USE_CPCIDVI
+       gt_cpcidvi_rom.init = 0;
+       gt_cpcidvi_rom.base = 0;
+#endif
+
+       pci0_hose.config_table = gt_config_table;
+       pci1_hose.config_table = gt_config_table;
+
+#ifdef CONFIG_USE_CPCIDVI
+       gt_config_table[0].config_device =  gt_setup_cpcidvi;
+#endif
+       gt_config_table[1].config_device =  gt_setup_ide;
 
        pci0_hose.first_busno = 0;
        pci0_hose.last_busno = 0xff;

diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c
index db545ef68df0739762aea6a3a55b202f0a4dbb92..6bdfc1d1cc00e39386327ec2ad189f7d00447493 100644 (file)
--- a/board/esd/cpci750/sdram_init.c
+++ b/board/esd/cpci750/sdram_init.c
@@ -45,6 +45,7 @@
 #include "64360.h"
 #include "mv_regs.h"
 
+DECLARE_GLOBAL_DATA_PTR;
 
 #undef DEBUG
 /* #define DEBUG */
@@ -250,8 +251,6 @@ NSto10PS(unsigned char spd_byte)
 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long spd_checksum;
 
        uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;

diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c
index 44de052566774f6c63fda8a798384a9215e660c8..ba32ac12acedd54ee1b329a5592e55d361a4e5de 100644 (file)
--- a/board/esd/cpci750/serial.c
+++ b/board/esd/cpci750/serial.c
@@ -38,13 +38,12 @@
 #include "../../Marvell/include/memory.h"
 #include "serial.h"
 
-
 #include "mpsc.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        mpsc_init (gd->baudrate);
 
        return (0);
@@ -70,8 +69,6 @@ int serial_tstc (void)
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
 }
 

diff --git a/board/esd/cpci750/strataflash.c b/board/esd/cpci750/strataflash.c
deleted file mode 100644 (file)
index c22fe5d..0000000
--- a/board/esd/cpci750/strataflash.c
+++ /dev/null
@@ -1,763 +0,0 @@
-/*
- * (C) Copyright 2002
- * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-
-#undef  DEBUG_FLASH
-/*
- * This file implements a Common Flash Interface (CFI) driver for U-Boot.
- * The width of the port and the width of the chips are determined at initialization.
- * These widths are used to calculate the address for access CFI data structures.
- * It has been tested on an Intel Strataflash implementation.
- *
- * References
- * JEDEC Standard JESD68 - Common Flash Interface (CFI)
- * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
- * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
- * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
- *
- * TODO
- * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
- * Add support for other command sets Use the PRI and ALT to determine command set
- * Verify erase and program timeouts.
- */
-
-#define FLASH_CMD_CFI                  0x98
-#define FLASH_CMD_READ_ID              0x90
-#define FLASH_CMD_RESET                        0xff
-#define FLASH_CMD_BLOCK_ERASE          0x20
-#define FLASH_CMD_ERASE_CONFIRM                0xD0
-#define FLASH_CMD_WRITE                        0x40
-#define FLASH_CMD_PROTECT              0x60
-#define FLASH_CMD_PROTECT_SET          0x01
-#define FLASH_CMD_PROTECT_CLEAR                0xD0
-#define FLASH_CMD_CLEAR_STATUS         0x50
-#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
-#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
-
-#define FLASH_STATUS_DONE              0x80
-#define FLASH_STATUS_ESS               0x40
-#define FLASH_STATUS_ECLBS             0x20
-#define FLASH_STATUS_PSLBS             0x10
-#define FLASH_STATUS_VPENS             0x08
-#define FLASH_STATUS_PSS               0x04
-#define FLASH_STATUS_DPS               0x02
-#define FLASH_STATUS_R                 0x01
-#define FLASH_STATUS_PROTECT           0x01
-
-#define FLASH_OFFSET_CFI               0x55
-#define FLASH_OFFSET_CFI_RESP          0x10
-#define FLASH_OFFSET_WTOUT             0x1F
-#define FLASH_OFFSET_WBTOUT             0x20
-#define FLASH_OFFSET_ETOUT             0x21
-#define FLASH_OFFSET_CETOUT             0x22
-#define FLASH_OFFSET_WMAX_TOUT         0x23
-#define FLASH_OFFSET_WBMAX_TOUT         0x24
-#define FLASH_OFFSET_EMAX_TOUT         0x25
-#define FLASH_OFFSET_CEMAX_TOUT         0x26
-#define FLASH_OFFSET_SIZE              0x27
-#define FLASH_OFFSET_INTERFACE          0x28
-#define FLASH_OFFSET_BUFFER_SIZE        0x2A
-#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
-#define FLASH_OFFSET_ERASE_REGIONS     0x2D
-#define FLASH_OFFSET_PROTECT           0x02
-#define FLASH_OFFSET_USER_PROTECTION    0x85
-#define FLASH_OFFSET_INTEL_PROTECTION   0x81
-
-
-#define FLASH_MAN_CFI                  0x01000000
-
-
-typedef union {
-       unsigned char c;
-       unsigned short w;
-       unsigned long l;
-} cfiword_t;
-
-typedef union {
-       unsigned char * cp;
-       unsigned short *wp;
-       unsigned long *lp;
-} cfiptr_t;
-
-#define NUM_ERASE_REGIONS 4
-
-flash_info_t   flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips        */
-
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-
-static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_detect_cfi(flash_info_t * info);
-static ulong flash_get_size (ulong base, int banknum);
-static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
-static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
-#endif
-/*-----------------------------------------------------------------------
- * create an address based on the offset and the port width
- */
-inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
-{
-       return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
-}
-/*-----------------------------------------------------------------------
- * read a character at a port width address
- */
-inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
-{
-       uchar *cp;
-       cp = flash_make_addr(info, 0, offset);
-       return (cp[info->portwidth - 1]);
-}
-
-/*-----------------------------------------------------------------------
- * read a short word by swapping for ppc format.
- */
-ushort flash_read_ushort(flash_info_t * info, int sect,  uchar offset)
-{
-    uchar * addr;
-
-    addr = flash_make_addr(info, sect, offset);
-    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- * read a long word by picking the least significant byte of each maiximum
- * port size word. Swap for ppc format.
- */
-ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
-{
-    uchar * addr;
-
-    addr = flash_make_addr(info, sect, offset);
-    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
-           (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
-       unsigned long size;
-       int i;
-       unsigned long  address;
-
-
-       /* The flash is positioned back to back, with the demultiplexing of the chip
-        * based on the A24 address line.
-        *
-        */
-
-       address = CFG_FLASH_BASE;
-       size = 0;
-
-       /* Init: no FLASHes known */
-       for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
-               flash_info[i].flash_id = FLASH_UNKNOWN;
-               size += flash_info[i].size = flash_get_size(address, i);
-               address += CFG_FLASH_INCREMENT;
-               if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-                       printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
-                               flash_info[0].size, flash_info[i].size<<20);
-               }
-       }
-
-#if 0 /* test-only */
-       /* Monitor protection ON by default */
-#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
-       for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++)
-               (void)flash_real_protect(&flash_info[0], i, 1);
-#endif
-#endif
-
-       return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-       int rcode = 0;
-       int prot;
-       int sect;
-
-       if( info->flash_id != FLASH_MAN_CFI) {
-               printf ("Can't erase unknown flash type - aborted\n");
-               return 1;
-       }
-       if ((s_first < 0) || (s_first > s_last)) {
-               printf ("- no sectors to erase\n");
-               return 1;
-       }
-
-       prot = 0;
-       for (sect=s_first; sect<=s_last; ++sect) {
-               if (info->protect[sect]) {
-                       prot++;
-               }
-       }
-       if (prot) {
-               printf ("- Warning: %d protected sectors will not be erased!\n",
-                       prot);
-       } else {
-               printf ("\n");
-       }
-
-
-       for (sect = s_first; sect<=s_last; sect++) {
-               if (info->protect[sect] == 0) { /* not protected */
-                       flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
-                       flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
-                       flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
-
-                       if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
-                               rcode = 1;
-                       } else
-                               printf(".");
-               }
-       }
-       printf (" done\n");
-       return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-       int i;
-
-       if (info->flash_id != FLASH_MAN_CFI) {
-               printf ("missing or unknown FLASH type\n");
-               return;
-       }
-
-       printf("CFI conformant FLASH (%d x %d)",
-              (info->portwidth  << 3 ), (info->chipwidth  << 3 ));
-       printf ("  Size: %ld MB in %d Sectors\n",
-               info->size >> 20, info->sector_count);
-       printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
-              info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
-
-       printf ("  Sector Start Addresses:");
-       for (i=0; i<info->sector_count; ++i) {
-               if ((i % 5) == 0)
-                       printf ("\n");
-               printf (" %08lX%5s",
-                       info->start[i],
-                       info->protect[i] ? " (RO)" : " "
-                       );
-       }
-       printf ("\n");
-       return;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-       ulong wp;
-       ulong cp;
-       int aln;
-       cfiword_t cword;
-       int i, rc;
-
-       /* get lower aligned address */
-       wp = (addr & ~(info->portwidth - 1));
-
-       /* handle unaligned start */
-       if((aln = addr - wp) != 0) {
-               cword.l = 0;
-               cp = wp;
-               for(i=0;i<aln; ++i, ++cp)
-                       flash_add_byte(info, &cword, (*(uchar *)cp));
-
-               for(; (i< info->portwidth) && (cnt > 0) ; i++) {
-                       flash_add_byte(info, &cword, *src++);
-                       cnt--;
-                       cp++;
-               }
-               for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
-                       flash_add_byte(info, &cword, (*(uchar *)cp));
-               if((rc = flash_write_cfiword(info, wp, cword)) != 0)
-                       return rc;
-               wp = cp;
-       }
-
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
-       while(cnt >= info->portwidth) {
-               i = info->buffer_size > cnt? cnt: info->buffer_size;
-               if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
-                       return rc;
-               wp += i;
-               src += i;
-               cnt -=i;
-       }
-#else
-       /* handle the aligned part */
-       while(cnt >= info->portwidth) {
-               cword.l = 0;
-               for(i = 0; i < info->portwidth; i++) {
-                       flash_add_byte(info, &cword, *src++);
-               }
-               if((rc = flash_write_cfiword(info, wp, cword)) != 0)
-                       return rc;
-               wp += info->portwidth;
-               cnt -= info->portwidth;
-       }
-#endif /* CFG_FLASH_USE_BUFFER_WRITE */
-       if (cnt == 0) {
-               return (0);
-       }
-
-       /*
-        * handle unaligned tail bytes
-        */
-       cword.l = 0;
-       for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
-               flash_add_byte(info, &cword, *src++);
-               --cnt;
-       }
-       for (; i<info->portwidth; ++i, ++cp) {
-               flash_add_byte(info, & cword, (*(uchar *)cp));
-       }
-
-       return flash_write_cfiword(info, wp, cword);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
-       int retcode = 0;
-
-       flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
-       flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
-       if(prot)
-               flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
-       else
-               flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
-
-       if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
-                                        prot?"protect":"unprotect")) == 0) {
-
-               info->protect[sector] = prot;
-               /* Intel's unprotect unprotects all locking */
-               if(prot == 0) {
-                       int i;
-                       for(i = 0 ; i<info->sector_count; i++) {
-                               if(info->protect[i])
-                                       flash_real_protect(info, i, 1);
-                       }
-               }
-       }
-
-       return retcode;
-}
-/*-----------------------------------------------------------------------
- *  wait for XSR.7 to be set. Time out with an error if it does not.
- *  This routine does not set the flash to read-array mode.
- */
-static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
-{
-       ulong start;
-
-       /* Wait for command completion */
-       start = get_timer (0);
-       while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
-               if (get_timer(start) > info->erase_blk_tout) {
-                       printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
-                       flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
-                       return ERR_TIMOUT;
-               }
-       }
-       return ERR_OK;
-}
-/*-----------------------------------------------------------------------
- * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
- * This routine sets the flash to read-array mode.
- */
-static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
-{
-       int retcode;
-       retcode = flash_status_check(info, sector, tout, prompt);
-       if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
-               retcode = ERR_INVAL;
-               printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
-               if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
-                       printf("Command Sequence Error.\n");
-               } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
-                       printf("Block Erase Error.\n");
-                       retcode = ERR_NOT_ERASED;
-               } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
-                       printf("Locking Error\n");
-               }
-               if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
-                       printf("Block locked.\n");
-                       retcode = ERR_PROTECTED;
-               }
-               if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
-                       printf("Vpp Low Error.\n");
-       }
-       flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
-       return retcode;
-}
-/*-----------------------------------------------------------------------
- */
-static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
-{
-       switch(info->portwidth) {
-       case FLASH_CFI_8BIT:
-               cword->c = c;
-               break;
-       case FLASH_CFI_16BIT:
-               cword->w = (cword->w << 8) | c;
-               break;
-       case FLASH_CFI_32BIT:
-               cword->l = (cword->l << 8) | c;
-       }
-}
-
-
-/*-----------------------------------------------------------------------
- * make a proper sized command based on the port and chip widths
- */
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
-{
-       int i;
-       uchar *cp = (uchar *)cmdbuf;
-       for(i=0; i< info->portwidth; i++)
-               *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
-}
-
-/*
- * Write a proper sized command to the correct address
- */
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
-
-       volatile cfiptr_t addr;
-       cfiword_t cword;
-       addr.cp = flash_make_addr(info, sect, offset);
-       flash_make_cmd(info, cmd, &cword);
-       switch(info->portwidth) {
-       case FLASH_CFI_8BIT:
-               *addr.cp = cword.c;
-               break;
-       case FLASH_CFI_16BIT:
-               *addr.wp = cword.w;
-               break;
-       case FLASH_CFI_32BIT:
-               *addr.lp = cword.l;
-               break;
-       }
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
-       cfiptr_t cptr;
-       cfiword_t cword;
-       int retval;
-       cptr.cp = flash_make_addr(info, sect, offset);
-       flash_make_cmd(info, cmd, &cword);
-       switch(info->portwidth) {
-       case FLASH_CFI_8BIT:
-               retval = (cptr.cp[0] == cword.c);
-               break;
-       case FLASH_CFI_16BIT:
-               retval = (cptr.wp[0] == cword.w);
-               break;
-       case FLASH_CFI_32BIT:
-               retval = (cptr.lp[0] == cword.l);
-               break;
-       default:
-               retval = 0;
-               break;
-       }
-       return retval;
-}
-/*-----------------------------------------------------------------------
- */
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
-       cfiptr_t cptr;
-       cfiword_t cword;
-       int retval;
-       cptr.cp = flash_make_addr(info, sect, offset);
-       flash_make_cmd(info, cmd, &cword);
-       switch(info->portwidth) {
-       case FLASH_CFI_8BIT:
-               retval = ((cptr.cp[0] & cword.c) == cword.c);
-               break;
-       case FLASH_CFI_16BIT:
-               retval = ((cptr.wp[0] & cword.w) == cword.w);
-               break;
-       case FLASH_CFI_32BIT:
-               retval = ((cptr.lp[0] & cword.l) == cword.l);
-               break;
-       default:
-               retval = 0;
-               break;
-       }
-       return retval;
-}
-
-/*-----------------------------------------------------------------------
- * detect if flash is compatible with the Common Flash Interface (CFI)
- * http://www.jedec.org/download/search/jesd68.pdf
- *
- */
-static int flash_detect_cfi(flash_info_t * info)
-{
-
-       for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
-           info->portwidth <<= 1) {
-               for(info->chipwidth =FLASH_CFI_BY8;
-                   info->chipwidth <= info->portwidth;
-                   info->chipwidth <<= 1) {
-                       flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
-                       flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
-                       if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
-                          flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
-                          flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
-                               return 1;
-               }
-       }
-       return 0;
-}
-/*
- * The following code cannot be run from FLASH!
- *
- */
-static ulong flash_get_size (ulong base, int banknum)
-{
-       flash_info_t * info = &flash_info[banknum];
-       int i, j;
-       int sect_cnt;
-       unsigned long sector;
-       unsigned long tmp;
-       int size_ratio = 0;
-       uchar num_erase_regions;
-       int  erase_region_size;
-       int  erase_region_count;
-
-       info->start[0] = base;
-
-       invalidate_dcache_range(base, base+0x400);
-
-       if(flash_detect_cfi(info)){
-
-               size_ratio = info->portwidth / info->chipwidth;
-               num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
-
-               sect_cnt = 0;
-               sector = base;
-               for(i = 0 ; i < num_erase_regions; i++) {
-                       if(i > NUM_ERASE_REGIONS) {
-                               printf("%d erase regions found, only %d used\n",
-                                      num_erase_regions, NUM_ERASE_REGIONS);
-                               break;
-                       }
-                       tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
-                       erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
-                       tmp >>= 16;
-                       erase_region_count = (tmp & 0xffff) +1;
-                       for(j = 0; j< erase_region_count; j++) {
-                               info->start[sect_cnt] = sector;
-                               sector += (erase_region_size * size_ratio);
-                               info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
-                               sect_cnt++;
-                       }
-               }
-
-               info->sector_count = sect_cnt;
-               /* multiply the size by the number of chips */
-               info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
-               info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
-               tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
-               info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
-               tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
-               info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
-               tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
-               info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
-               info->flash_id = FLASH_MAN_CFI;
-       }
-
-       flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
-#ifdef DEBUG_FLASH
-       printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
-#endif
-#ifdef DEBUG_FLASH
-       printf("found %d erase regions\n", num_erase_regions);
-#endif
-#ifdef DEBUG_FLASH
-       printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
-#endif
-       return(info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
-{
-
-       cfiptr_t ctladdr;
-       cfiptr_t cptr;
-       int flag;
-
-       ctladdr.cp = flash_make_addr(info, 0, 0);
-       cptr.cp = (uchar *)dest;
-
-
-       /* Check if Flash is (sufficiently) erased */
-       switch(info->portwidth) {
-       case FLASH_CFI_8BIT:
-               flag = ((cptr.cp[0] & cword.c) == cword.c);
-               break;
-       case FLASH_CFI_16BIT:
-               flag = ((cptr.wp[0] & cword.w) == cword.w);
-               break;
-       case FLASH_CFI_32BIT:
-               flag = ((cptr.lp[0] & cword.l)  == cword.l);
-               break;
-       default:
-               return 2;
-       }
-       if(!flag)
-               return 2;
-
-       /* Disable interrupts which might cause a timeout here */
-       flag = disable_interrupts();
-
-       flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
-       flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
-
-       switch(info->portwidth) {
-       case FLASH_CFI_8BIT:
-               cptr.cp[0] = cword.c;
-               break;
-       case FLASH_CFI_16BIT:
-               cptr.wp[0] = cword.w;
-               break;
-       case FLASH_CFI_32BIT:
-               cptr.lp[0] = cword.l;
-               break;
-       }
-
-       /* re-enable interrupts if necessary */
-       if(flag)
-               enable_interrupts();
-
-       return flash_full_status_check(info, 0, info->write_tout, "write");
-}
-
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
-
-/* loop through the sectors from the highest address
- * when the passed address is greater or equal to the sector address
- * we have a match
- */
-static int find_sector(flash_info_t *info, ulong addr)
-{
-       int sector;
-       for(sector = info->sector_count - 1; sector >= 0; sector--) {
-               if(addr >= info->start[sector])
-                       break;
-       }
-       return sector;
-}
-
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
-{
-
-       int sector;
-       int cnt;
-       int retcode;
-       volatile cfiptr_t src;
-       volatile cfiptr_t dst;
-
-       src.cp = cp;
-       dst.cp = (uchar *)dest;
-       sector = find_sector(info, dest);
-       flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
-       flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
-       if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
-                                        "write to buffer")) == ERR_OK) {
-               switch(info->portwidth) {
-               case FLASH_CFI_8BIT:
-                       cnt = len;
-                       break;
-               case FLASH_CFI_16BIT:
-                       cnt = len >> 1;
-                       break;
-               case FLASH_CFI_32BIT:
-                       cnt = len >> 2;
-                       break;
-               default:
-                       return ERR_INVAL;
-                       break;
-               }
-               flash_write_cmd(info, sector, 0, (uchar)cnt-1);
-               while(cnt-- > 0) {
-                       switch(info->portwidth) {
-                       case FLASH_CFI_8BIT:
-                               *dst.cp++ = *src.cp++;
-                               break;
-                       case FLASH_CFI_16BIT:
-                               *dst.wp++ = *src.wp++;
-                               break;
-                       case FLASH_CFI_32BIT:
-                               *dst.lp++ = *src.lp++;
-                               break;
-                       default:
-                               return ERR_INVAL;
-                               break;
-                       }
-               }
-               flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
-               retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
-                                            "buffer write");
-       }
-       flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
-       return retcode;
-}
-#endif /* CFG_USE_FLASH_BUFFER_WRITE */

diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c
index 7bf7bb5a5e5490309e68fbfe1567ebc0b411bfc9..fcb8cbbe735caf24f07e576103ea7b91097dbb29 100644 (file)
--- a/board/esd/cpciiser4/cpciiser4.c
+++ b/board/esd/cpciiser4/cpciiser4.c
@@ -26,6 +26,8 @@
 #include <asm/processor.h>
 #include <command.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*cmd_boot.c*/
 
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
@@ -55,8 +57,6 @@ const unsigned char fpgadata[] = {
 
 int board_early_init_f (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int index, len, i;
        volatile unsigned char dummy;
        int status;

diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c
index fd51f7f343e8fcd5af4356608201b63565b4a4a1..240ab78aa796e71f3b352543ec1ac846297087cb 100644 (file)
--- a/board/esd/dp405/dp405.c
+++ b/board/esd/dp405/dp405.c
@@ -26,6 +26,7 @@
 #include <command.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 /* fpga configuration data - not compressed, generated by bin2c */
 const unsigned char fpgadata[] =
@@ -84,8 +85,6 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* adjust flash start and offset */
        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
        gd->bd->bi_flashoffset = 0;

diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c
index 26e834196bd923f2b2051d8fc9c0e12a8b981b02..a019ce4215093b4b160259723d0850e86917e4b1 100644 (file)
--- a/board/esd/du405/du405.c
+++ b/board/esd/du405/du405.c
@@ -28,6 +28,8 @@
 #include <405gp_i2c.h>
 #include <command.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*cmd_boot.c*/
 
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
@@ -55,8 +57,6 @@ const unsigned char fpgadata[] = {
 
 int board_early_init_f (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int index, len, i;
        int status;
 

diff --git a/board/esd/hh405/fpgadata.c b/board/esd/hh405/fpgadata.c
index 58ee3a846fcf00e11c1b354decc641ef035a4875..64bca46085c067b34de1de399066ee77e0299e0f 100644 (file)
--- a/board/esd/hh405/fpgadata.c
+++ b/board/esd/hh405/fpgadata.c
@@ -1,2520 +1,2517 @@
-  0x1f,0x8b,0x08,0x08,0x9c,0xc4,0xe8,0x42,0x00,0x03,0x68,0x68,0x34,0x30,0x35,0x5f,
-  0x31,0x5f,0x30,0x35,0x2e,0x62,0x69,0x74,0x00,0xec,0xfd,0x0f,0x78,0x14,0xd7,0x91,
-  0x2f,0x0c,0x57,0x9f,0x6e,0x89,0xa3,0xe9,0x91,0xa6,0x91,0x84,0x57,0xb6,0x31,0x6e,
-  0x8d,0x04,0x1e,0x94,0x91,0x18,0x46,0x58,0xc8,0x42,0x8c,0x5a,0x23,0xd9,0x19,0x1b,
-  0x6c,0x26,0x8e,0x93,0x65,0x77,0xfd,0xe5,0x0e,0x84,0x64,0x95,0xbc,0xc4,0x2b,0x3b,
-  0xb9,0x7b,0x49,0xd6,0xeb,0x1c,0x8d,0x04,0x8c,0x90,0x0c,0x03,0x28,0x31,0x4e,0x58,
-  0x6f,0x23,0x64,0x5b,0x38,0x24,0x3b,0x08,0x0c,0x02,0x1c,0xdc,0xc2,0xb2,0x2d,0xfe,
-  0x18,0x2b,0x0e,0xeb,0xe0,0x3f,0x71,0x06,0x47,0x26,0xb2,0x23,0xdb,0x32,0xc6,0x8e,
-  0x04,0x02,0xde,0x3a,0x3d,0x92,0xa6,0x47,0x64,0xf7,0xe6,0xbe,0xf7,0xf9,0xde,0x6f,
-  0x9f,0xe7,0xbb,0xf2,0xf3,0xec,0x9e,0xb4,0x8e,0x9a,0xee,0xd3,0xe7,0x54,0xfd,0xaa,
-  0xea,0x57,0x55,0x90,0xe1,0x18,0x4e,0xfc,0x07,0x20,0xac,0x00,0x47,0x5d,0xdd,0x02,
-  0xcf,0xad,0xff,0x6d,0xfe,0x7f,0xf3,0xdc,0x5a,0xf2,0xc0,0xd7,0x57,0xc1,0x4a,0x90,
-  0xbd,0xdf,0xbd,0xd5,0xf3,0x8d,0xef,0x3d,0x38,0x7f,0xc1,0x02,0xf8,0x3a,0xfe,0x2f,
-  0x8f,0xe7,0xd6,0x79,0x9e,0x85,0xf3,0xbc,0xe5,0xb0,0x0a,0x32,0xe6,0x97,0x56,0x2c,
-  0xf0,0x56,0x78,0x3d,0xf0,0x0d,0x10,0x4a,0x3b,0xae,0xe2,0xcf,0x33,0x8f,0x7f,0xe5,
-  0x9b,0x1e,0x60,0x02,0x00,0x4c,0xf3,0x08,0x21,0xfe,0xff,0x65,0x8f,0xa0,0x0a,0xc0,
-  0xaa,0x8a,0x3d,0x60,0xf0,0xff,0x0d,0xe3,0xbf,0xcf,0xf0,0x80,0x6a,0xfd,0xdf,0x82,
-  0x07,0x34,0x08,0x82,0xd6,0xca,0xb2,0xe1,0x2f,0xf8,0xa1,0x12,0x9b,0x18,0xfe,0x45,
-  0xf3,0x61,0x72,0xfe,0xd5,0xe3,0xec,0x3f,0x9c,0x94,0xfc,0xa9,0x3a,0xaf,0x8f,0x8f,
-  0x18,0xf1,0xfc,0xcf,0xa7,0x0b,0x01,0x98,0xb8,0xeb,0x0f,0xdf,0xfc,0x4b,0xee,0xbf,
-  0xf0,0xf3,0x89,0xfb,0xff,0xaf,0xce,0x07,0xe5,0x2f,0x98,0x8e,0xef,0x3b,0x31,0xf8,
-  0xa1,0x22,0x68,0xb0,0x1c,0xd2,0x41,0x60,0x10,0x82,0xbc,0xff,0x60,0xb0,0xb0,0x77,
-  0x62,0xfe,0xd1,0xb4,0x31,0xef,0x29,0x71,0x61,0x7e,0xd6,0xe7,0x62,0x25,0xbc,0x0a,
-  0x0b,0x8c,0xcc,0x11,0xf1,0x0a,0x8c,0x42,0x45,0x9f,0x3d,0x2e,0x8e,0xc1,0xc7,0x50,
-  0x05,0x77,0xb3,0x1c,0x0f,0xd4,0x8f,0xcf,0x37,0xf2,0x9e,0x57,0x8e,0xab,0x5e,0x95,
-  0x7e,0x4e,0x7e,0x01,0x2d,0xe0,0x8c,0xdb,0xbb,0xc9,0x47,0xd0,0xad,0x16,0xbc,0x69,
-  0xef,0xc4,0xc1,0x06,0x56,0xa2,0xd2,0x08,0x89,0x49,0x13,0xab,0xd8,0x27,0xed,0x86,
-  0x2d,0xb6,0x39,0xb0,0x61,0x01,0x91,0x60,0xab,0x50,0x62,0xe4,0x79,0xc8,0x49,0x38,
-  0x2c,0xbb,0x5e,0xa4,0x1e,0x32,0x04,0x3b,0xc1,0x0d,0x54,0x99,0xe3,0x15,0x26,0xef,
-  0x8f,0xf3,0x7f,0x02,0x4e,0x0f,0x8d,0x39,0x77,0x6b,0x3f,0x65,0x45,0xf1,0xbc,0x18,
-  0x4e,0x3b,0xbc,0x41,0x35,0x32,0x3a,0xc8,0x50,0xd8,0x46,0x4b,0x08,0xdd,0x8c,0xf7,
-  0x0f,0x8d,0xcf,0xaf,0x9e,0x3e,0x04,0xbf,0x82,0x32,0x4f,0x56,0x4c,0x74,0x85,0xdf,
-  0x3a,0xeb,0x1b,0x76,0xc7,0x6a,0x86,0x60,0x94,0x55,0xf4,0xb4,0xea,0xe2,0x71,0xe9,
-  0x8f,0xbf,0xf2,0x45,0xdd,0x11,0x41,0x91,0x26,0xee,0xaf,0x0b,0xcf,0xc1,0xc7,0xb4,
-  0x0a,0x1c,0x9e,0x1b,0xfb,0xc8,0x7b,0xb0,0xd0,0x98,0x36,0x2c,0x8e,0x09,0x97,0x33,
-  0x9e,0x37,0xb2,0x7a,0xc4,0x0f,0xe0,0xa2,0xe4,0x63,0x0e,0x2a,0x0e,0xc2,0xc4,0xfd,
-  0xfb,0x95,0xdd,0xf4,0x7d,0xcd,0x0b,0xfc,0xfe,0xd2,0x1f,0x7b,0x7c,0x41,0x7b,0xac,
-  0x60,0x08,0x2e,0x41,0x99,0x61,0x67,0xe2,0xfb,0xf0,0x47,0xcd,0x13,0xb5,0x47,0x65,
-  0x8f,0xa4,0x4e,0xbc,0x6f,0x9a,0x8f,0xb6,0xc4,0x43,0x0b,0xe4,0x61,0xb1,0x4e,0x6a,
-  0x31,0xd4,0xb7,0x6d,0x31,0x71,0x37,0xec,0x85,0x02,0x83,0x32,0x32,0xc8,0x36,0x80,
-  0x93,0xd1,0x28,0x29,0xc3,0xdd,0x3f,0xf1,0xbe,0xab,0xb5,0xf6,0x3b,0x74,0xdd,0xe6,
-  0x21,0x76,0xd8,0xa9,0xba,0xe2,0x19,0x7c,0x7d,0x76,0x42,0xa1,0xe1,0x82,0xf4,0x8d,
-  0x64,0x07,0xa8,0x1a,0x55,0xc9,0x08,0x9e,0x95,0xc4,0xcf,0x88,0xf2,0xb5,0x8c,0x8d,
-  0xb1,0xfc,0x8e,0x1b,0xbf,0x4f,0xbe,0x46,0xd7,0xeb,0x73,0x87,0xe4,0x35,0xe4,0x09,
-  0xa8,0xea,0x56,0xe3,0x74,0x0d,0x79,0x27,0xf3,0x49,0x96,0x1f,0xa2,0xdf,0x82,0x2b,
-  0x93,0xf7,0x0f,0xd0,0xa5,0xf0,0x6e,0xbb,0x1a,0xce,0xf2,0x88,0x76,0xf8,0xa3,0x5e,
-  0x39,0x96,0xe9,0x11,0x4f,0xc2,0xa7,0xd1,0x05,0x71,0x3b,0x1f,0x9c,0x85,0x98,0xe6,
-  0xae,0xa8,0x79,0x8d,0x4c,0xec,0x07,0x2d,0xad,0x55,0xfd,0x47,0xa5,0x8a,0x39,0x86,
-  0xc5,0x21,0xed,0x8a,0xb2,0xb0,0x37,0x0b,0xd7,0x07,0x3e,0x85,0xaa,0x97,0x1c,0x31,
-  0x1c,0xfc,0x7f,0x94,0xaa,0x5a,0xc7,0x48,0x8e,0x92,0x3e,0xb1,0x3e,0x54,0xfa,0x79,
-  0xb8,0x07,0x4f,0x75,0xd6,0x01,0x71,0x35,0x9c,0x80,0x32,0x96,0x19,0x13,0x87,0x70,
-  0x7e,0x59,0x9f,0x3d,0x8a,0x83,0x13,0xcc,0x1b,0xb7,0xbb,0xe4,0xa2,0xc9,0xfd,0xd3,
-  0x97,0xb7,0x5d,0x5d,0x0f,0x3b,0x80,0x7e,0x57,0x9c,0x49,0x70,0xc0,0xdc,0xf5,0xe4,
-  0x6d,0x38,0x00,0xfa,0xc9,0x40,0x30,0xfb,0x6d,0xfc,0x43,0xd5,0xa0,0x21,0x9b,0x77,
-  0xf2,0xfb,0xaa,0xb0,0x91,0xb5,0x1a,0x05,0xaa,0xad,0xdc,0xb6,0x0c,0x1e,0x63,0xea,
-  0xd9,0xeb,0xf1,0x35,0xe1,0x79,0x96,0x1f,0x2f,0x5f,0xee,0x3f,0x05,0xeb,0x71,0x80,
-  0x2f,0xae,0xc2,0xc4,0xfa,0xd7,0x49,0xad,0xb0,0x35,0xa4,0xd6,0xe3,0xee,0xca,0xc4,
-  0x8d,0xa4,0x0e,0x2f,0xe7,0xeb,0xb9,0x97,0xdf,0x36,0x37,0xdc,0xab,0xed,0x8d,0xaa,
-  0x03,0xb8,0x03,0xb3,0x27,0xf7,0xe7,0xe0,0x8c,0x41,0x38,0x65,0x94,0x36,0x67,0xe9,
-  0x05,0x7f,0x0b,0xef,0xb4,0xef,0xed,0xcc,0xd4,0xf1,0xeb,0x7f,0x0e,0x5e,0x66,0xff,
-  0x40,0xfc,0x23,0x1c,0x87,0x2e,0xe6,0xd6,0xc5,0x8a,0xc9,0xe7,0x09,0x08,0x02,0x0c,
-  0xfa,0x7d,0xd4,0x01,0x62,0x9c,0x0d,0x42,0x05,0xcd,0x62,0x62,0x1c,0x46,0x58,0x05,
-  0x38,0x98,0xf8,0x2e,0x0c,0x82,0x0f,0x1c,0x86,0xf8,0x1a,0x4c,0xdc,0x9f,0x2a,0x4f,
-  0x91,0x1e,0xf6,0x94,0x96,0x19,0x15,0x3b,0xd2,0x8f,0x41,0xf8,0x76,0x1c,0x0c,0xc0,
-  0x28,0xe9,0xd2,0xec,0x8a,0x28,0xc1,0xfb,0xe0,0xd3,0x1c,0x51,0xf1,0xe8,0xe4,0xf3,
-  0x30,0x58,0xd5,0xd3,0xdc,0xaf,0x06,0x6d,0xd1,0x9c,0x55,0xb0,0x0b,0xd4,0x3a,0x7b,
-  0x94,0x0c,0xc0,0x41,0xcd,0xa9,0x45,0xa2,0xa4,0x10,0x9a,0xa1,0x44,0x93,0xa3,0x24,
-  0x3e,0x29,0x16,0xca,0xd3,0x0a,0xd3,0x5a,0xb4,0x5f,0x04,0x68,0x34,0x7d,0x00,0x32,
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+  0x30,0x65,0xcd,0x5b,0xaf,0x22,0x7e,0xbc,0x47,0x9c,0xe6,0xfd,0xe1,0xe3,0xf6,0x07,
+  0x86,0xc9,0x7e,0xdd,0x5e,0x81,0x2b,0xe0,0x9a,0x33,0x75,0xe3,0xcb,0x3f,0x98,0x59,
+  0x7b,0x69,0xa2,0x18,0x2e,0x22,0x3d,0xf6,0xd0,0x04,0x0d,0x6f,0x87,0x4b,0x0c,0x2c,
+  0x8b,0xe1,0x24,0x33,0x94,0x9b,0xb3,0xbe,0xf9,0xc9,0x29,0xa5,0xc1,0xd4,0x7e,0x5c,
+  0xdf,0xc3,0x4a,0xe9,0x4c,0xca,0x1c,0x8e,0xeb,0x37,0x9b,0x86,0xf9,0x11,0x7c,0xc8,
+  0x2e,0x46,0xf2,0x8b,0x85,0xec,0x8a,0x70,0xc3,0xe5,0xc3,0x86,0x4b,0x85,0x94,0x14,
+  0x2c,0xc1,0x87,0x36,0xa7,0x41,0x34,0x3e,0x2c,0x64,0x66,0x26,0x97,0x6e,0xcc,0x3f,
+  0xd6,0xf6,0xf6,0xb6,0x68,0x3e,0xa7,0x25,0xf7,0x32,0x3e,0xcc,0x63,0xc6,0xb1,0xb8,
+  0xe1,0xf9,0x07,0xcd,0x20,0x1a,0x5f,0xfc,0xf0,0x48,0x0c,0xb9,0x29,0x50,0x9b,0x8c,
+  0x18,0xa4,0xc0,0x62,0x6a,0x92,0x5f,0x3b,0xd9,0x26,0x0c,0xf8,0x84,0x10,0xe8,0x40,
+  0x15,0xba,0xa1,0x09,0xf8,0xed,0xf2,0xc2,0xf8,0xf9,0xb0,0xbb,0x21,0xff,0x8c,0x87,
+  0x1f,0xa3,0x95,0x0b,0xe9,0xf5,0xf6,0xf8,0xaa,0x56,0xfa,0x0d,0x1a,0x75,0x3c,0xd4,
+  0x4a,0x2f,0x5e,0xe8,0x5d,0x9f,0x18,0x0f,0x85,0xb9,0x89,0xfb,0xc6,0x43,0x0a,0x15,
+  0xdc,0xf4,0xa7,0x70,0xf7,0x3f,0xcf,0xf8,0x10,0x5c,0xc3,0x79,0xe0,0x3b,0xd7,0x24,
+  0x1d,0xdf,0x78,0x38,0x16,0x32,0x3e,0x5c,0x3a,0x3a,0xea,0xe7,0xc3,0xf7,0xeb,0x7c,
+  0xb8,0xb7,0x91,0x0f,0x39,0x7d,0x31,0x3e,0xdc,0x78,0x68,0x8b,0x9f,0x0f,0xaf,0xdf,
+  0x25,0x3e,0xe4,0x58,0xf8,0xdb,0x54,0x6d,0x61,0xe0,0x4f,0x01,0x8a,0x07,0xbb,0xde,
+  0x65,0x58,0x38,0xf5,0xd6,0xc2,0xea,0x9a,0x6b,0xfc,0xed,0xf9,0xd9,0xff,0xb8,0x8a,
+  0xed,0xff,0x12,0xa0,0xb8,0xb0,0xf1,0x10,0xc3,0xc2,0xab,0xd7,0x16,0x36,0xd6,0x5c,
+  0xd3,0xd0,0xbe,0xd3,0xe5,0xc3,0x4c,0xe7,0xe6,0x5f,0xa6,0x7b,0x90,0x0f,0x33,0x2f,
+  0x6f,0x3e,0xc7,0x09,0x33,0xc3,0x51,0xb3,0x72,0xed,0x3f,0x8c,0xdf,0x04,0x83,0xb0,
+  0xdb,0x33,0x4c,0xc8,0xc5,0xef,0xbc,0x17,0x29,0x29,0x29,0x29,0x29,0x29,0x29,0x29,
+  0x29,0x29,0xa9,0xff,0xbb,0x78,0xed,0xa0,0xc8,0xda,0x41,0x4a,0x4a,0x4a,0x4a,0x4a,
+  0x4a,0x4a,0x4a,0x4a,0x4a,0xea,0xd6,0xe2,0xb5,0x43,0x54,0xd6,0x0e,0x52,0x52,0x52,
+  0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0xb7,0x16,0xaf,0x1d,0x54,0x5e,0x3b,0xe0,
+  0x5f,0x91,0xbe,0x27,0x77,0xd3,0x81,0xfe,0x97,0x76,0x07,0x74,0xb6,0xee,0x73,0xf0,
+  0x00,0xcd,0x58,0xd0,0x70,0x13,0xda,0x5d,0x94,0xd2,0xf4,0xcc,0x31,0x7b,0x69,0xdb,
+  0x97,0x85,0x60,0xba,0x87,0x81,0x39,0x36,0x7e,0x0a,0x03,0x4e,0x30,0xfd,0x2b,0xc6,
+  0xcc,0x09,0x67,0xe5,0xc5,0xd7,0x5f,0x09,0xa6,0x7b,0x30,0xe7,0xcc,0xdf,0x69,0x66,
+  0xbf,0x63,0x3a,0xc1,0xf4,0x9f,0x78,0xf8,0xe0,0x11,0xa7,0xe3,0x93,0xa7,0xb7,0x04,
+  0xd3,0x3d,0xce,0xbf,0x18,0x7f,0x50,0xf3,0x1f,0x5f,0x73,0xdc,0x86,0x47,0x57,0x54,
+  0x83,0x9b,0xff,0x65,0x18,0x3f,0x5b,0x20,0xa8,0xf9,0x6f,0xce,0x9e,0x9e,0x87,0x7b,
+  0x76,0x7c,0xbe,0x29,0x98,0xee,0x71,0xfe,0xc5,0xf8,0x03,0x8b,0xff,0xb5,0x6d,0x1f,
+  0xd3,0xa5,0xcf,0xcf,0xa8,0xb7,0x6f,0x7a,0x47,0x32,0xe7,0x06,0x30,0x7e,0x0e,0x05,
+  0x17,0xff,0x1a,0xd9,0x00,0xab,0x63,0xf7,0x06,0x17,0xff,0x62,0xfc,0x41,0xcd,0x7f,
+  0x22,0x6d,0x0d,0xc3,0xba,0xeb,0xd9,0xa0,0xe2,0xc7,0xac,0x39,0x2c,0x7f,0x9a,0xf3,
+  0x4e,0x30,0xfd,0x2b,0xea,0x81,0x37,0x9d,0x0d,0x9f,0xce,0x04,0x96,0xff,0xdd,0xf1,
+  0xdf,0xfc,0xcb,0x04,0x77,0x47,0x4a,0x66,0xe6,0x94,0x93,0x59,0x31,0x1d,0x58,0xfe,
+  0xa9,0xcd,0xb3,0xfc,0x39,0x1f,0xd4,0xfc,0x2f,0xeb,0xff,0xf5,0x9a,0xd3,0xfb,0xe3,
+  0xe3,0x73,0xc1,0x74,0x8f,0xf3,0x2f,0xc6,0x1f,0xd8,0xfc,0xf7,0xbf,0xf6,0x8e,0xfd,
+  0xd0,0x8a,0x93,0xb1,0xdb,0x37,0xbd,0x23,0x99,0xb5,0x39,0x96,0x3f,0x03,0x8b,0xff,
+  0x68,0xe7,0xa9,0x67,0xed,0xec,0x57,0x3f,0x59,0xc1,0x74,0x8f,0xf3,0x2f,0xc6,0x1f,
+  0xd8,0xfc,0xaf,0xde,0xf1,0x05,0x18,0x6d,0x6f,0x07,0x97,0x7f,0x6a,0x2c,0x7f,0x06,
+  0x17,0xff,0x2b,0x23,0x69,0xda,0x7f,0x32,0xf1,0x7d,0x30,0xdd,0xb3,0x1f,0x39,0xe1,
+  0xe3,0x0f,0x66,0xfe,0x4d,0xf6,0x7c,0x1c,0xbc,0xd8,0x6a,0x82,0xcd,0x9e,0x5a,0x09,
+  0x9b,0x40,0xff,0xf5,0xff,0x13,0xdc,0xf7,0x46,0x4c,0xa8,0x12,0xaf,0xcf,0x2b,0x7b,
+  0x6e,0x6c,0xf7,0x37,0xea,0xe7,0xba,0x8f,0xf0,0x33,0x01,0x00,

diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c
index 3158803f0c7c3cb126d4dd6b2a642f8201549e2e..ea344c0f26dd2a7054932f62c0f3c15879113447 100644 (file)
--- a/board/esd/hh405/hh405.c
+++ b/board/esd/hh405/hh405.c
@@ -5,6 +5,9 @@
  * (C) Copyright 2005
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
+ * (C) Copyright 2006
+ * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -31,6 +34,7 @@
 #include <pci.h>
 #include <sm501.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_VIDEO_SM501
 
@@ -66,10 +70,12 @@ static const SMI_REGS init_regs_800x600 [] =
        {0x00040, SWAP32(0x00021807)},
        {0x00044, SWAP32(0x221a0a01)},
        {0x00054, SWAP32(0x00000000)},
+       /* GPIO */
+       {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
        /* panel control regs... */
        {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
        {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
-       {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+       {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
        {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
        {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
        {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
@@ -100,10 +106,12 @@ static const SMI_REGS init_regs_1024x768 [] =
        {0x00040, SWAP32(0x00021807)},
        {0x00044, SWAP32(0x011a0a01)},
        {0x00054, SWAP32(0x00000000)},
+       /* GPIO */
+       {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
        /* panel control regs... */
        {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
        {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
-       {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+       {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
        {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
        {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
        {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
@@ -144,10 +152,12 @@ static const SMI_REGS init_regs_800x600 [] =
        {0x00040, SWAP32(0x00021807)},
        {0x00044, SWAP32(0x221a0a01)},
        {0x00054, SWAP32(0x00000000)},
+       /* GPIO */
+       {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
        /* panel control regs... */
        {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
        {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
-       {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+       {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
        {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
        {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
        {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
@@ -178,10 +188,12 @@ static const SMI_REGS init_regs_1024x768 [] =
        {0x00040, SWAP32(0x00021807)},
        {0x00044, SWAP32(0x011a0a01)},
        {0x00054, SWAP32(0x00000000)},
+       /* GPIO */
+       {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
        /* panel control regs... */
        {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
        {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
-       {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+       {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
        {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
        {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
        {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
@@ -272,6 +284,9 @@ au_image_t au_image[] = {
 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
 
 
+/*
+ * Get version of HH405 board from GPIO's
+ */
 int board_revision(void)
 {
        unsigned long osrh_reg;
@@ -279,10 +294,6 @@ int board_revision(void)
        unsigned long tcr_reg;
        unsigned long value;
 
-       /*
-        * Get version of HH405 board from GPIO's
-        */
-
        /*
         * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
         */
@@ -305,15 +316,13 @@ int board_revision(void)
 
        if (value & 0x80000000) {
                /* Revision 1.0 or 1.1 detected */
-               return 0x0101;
+               return 1;
        } else {
                if (value & 0x00400000) {
                        /* unused */
-                       return 0x0103;
+                       return 3;
                } else {
-                       /* Revision >= 2.0 detected */
-                       /* rev. 2.x uses four SM501 GPIOs for revision coding */
-                       return 0x0200;
+                       return 2;
                }
        }
 }
@@ -349,11 +358,39 @@ int board_early_init_f (void)
        return 0;
 }
 
+int cf_enable(void)
+{
+       int i;
+
+       volatile unsigned short *fpga_ctrl =
+               (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+       volatile unsigned short *fpga_status =
+               (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
+
+       if (gd->board_type >= 2) {
+               if (*fpga_status & CFG_FPGA_STATUS_CF_DETECT) {
+                       if (!(*fpga_ctrl & CFG_FPGA_CTRL_CF_BUS_EN)) {
+                               *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_PWRN;
+
+                               for (i=0; i<300; i++)
+                                       udelay(1000);
+
+                               *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
+
+                               for (i=0; i<20; i++)
+                                       udelay(1000);
+                       }
+               } else {
+                       *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_BUS_EN;
+                       *fpga_ctrl |= CFG_FPGA_CTRL_CF_PWRN;
+               }
+       }
+
+       return 0;
+}
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile unsigned short *fpga_ctrl =
                (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
        volatile unsigned short *lcd_contrast =
@@ -433,9 +470,6 @@ int misc_init_r (void)
         * Write Board revision into FPGA
         */
        *fpga_ctrl |= gd->board_type & 0x0003;
-       if (gd->board_type >= 0x0200) {
-               *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
-       }
 
        /*
         * Setup and enable EEPROM write protection
@@ -471,7 +505,7 @@ int misc_init_r (void)
                contrast0 = simple_strtol(str, NULL, 16);
                if (contrast0 > 255) {
                        printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0);
-                       contrast0 = 0;
+                       contrast0 = 0xffffffff;
                }
        }
 
@@ -544,9 +578,9 @@ int misc_init_r (void)
                 */
                *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
                /*
-                * Set lcd clock (small epson)
+                * Set lcd clock (small epson), enable 1-wire interface
                 */
-               *fpga_ctrl |= LCD_CLK_08330;
+               *fpga_ctrl |= LCD_CLK_08330 | CFG_FPGA_CTRL_OW_ENABLE;
 
                lcd_setup(0, 1);
                lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
@@ -565,8 +599,10 @@ int misc_init_r (void)
                        puts("VGA:   SM501 with 8 MB ");
                        if (strcmp(str, "ppc221") == 0) {
                                printf("(800*600, %dbpp)\n", BPP);
+                               *lcd_backlight = 0x002d; /* max. allowed brightness */
                        } else if (strcmp(str, "ppc231") == 0) {
                                printf("(1024*768, %dbpp)\n", BPP);
+                               *lcd_backlight = 0x0000;
                        } else {
                                printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
                                return 0;
@@ -578,6 +614,8 @@ int misc_init_r (void)
 #endif /* CONFIG_VIDEO_SM501 */
        }
 
+       cf_enable();
+
        return (0);
 }
 
@@ -588,9 +626,7 @@ int misc_init_r (void)
 
 int checkboard (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
-       unsigned char str[64];
+       char str[64];
        int i = getenv_r ("serial#", str, sizeof(str));
 
        puts ("Board: ");
@@ -608,14 +644,7 @@ int checkboard (void)
        }
 
        gd->board_type = board_revision();
-       printf(", Rev %ld.%ld)\n",
-              (gd->board_type >> 8) & 0xff,
-              gd->board_type & 0xff);
-
-       /*
-        * Disable sleep mode in LXT971
-        */
-       lxt971_no_sleep();
+       printf(", Rev %ld.x)\n", gd->board_type);
 
        return 0;
 }
@@ -637,35 +666,32 @@ long int initdram (int board_type)
 }
 
 
-int testdram (void)
-{
-       /* TODO: XXX XXX XXX */
-       printf ("test: 16 MB - ok\n");
-
-       return (0);
-}
-
-
 #ifdef CONFIG_IDE_RESET
 void ide_set_reset(int on)
 {
        volatile unsigned short *fpga_mode =
                (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+       volatile unsigned short *fpga_status =
+               (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
 
-       /*
-        * Assert or deassert CompactFlash Reset Pin
-        */
-       if (on) {               /* assert RESET */
-               *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
-       } else {                /* release RESET */
-               *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+       if (((gd->board_type >= 2) && (*fpga_status & CFG_FPGA_STATUS_CF_DETECT)) ||
+           (gd->board_type < 2)) {
+               /*
+                * Assert or deassert CompactFlash Reset Pin
+                */
+               if (on) {               /* assert RESET */
+                       cf_enable();
+                       *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+               } else {                /* release RESET */
+                       *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+               }
        }
 }
 #endif /* CONFIG_IDE_RESET */
 
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 
 void nand_init(void)
@@ -756,8 +782,6 @@ U_BOOT_CMD(eepwren, 2,      0,      do_eep_wren,
  */
 void video_get_info_str (int line_number, char *info)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        char str[64];
        char str2[64];
        int i = getenv_r("serial#", str2, sizeof(str));
@@ -778,8 +802,7 @@ void video_get_info_str (int line_number, char *info)
                        strcat(str, " (Missing bd_type!");
                }
 
-               sprintf(str2, ", Rev %ld.%ld)",
-                      (gd->board_type >> 8) & 0xff, gd->board_type & 0xff);
+               sprintf(str2, ", Rev %ld.x)", gd->board_type);
                strcat(str, str2);
                strcpy(info, str);
        } else {
@@ -822,7 +845,11 @@ unsigned int board_video_get_fb (void)
        devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
        if (devbusfn != -1) {
                pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
-               return (addr & 0xfffffffe);
+               addr &= 0xfffffffe;
+#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
+               addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
+#endif
+               return addr;
        }
 
        return 0;
@@ -875,3 +902,15 @@ int board_get_height (void)
 }
 
 #endif /* CONFIG_VIDEO_SM501 */
+
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+       /*
+        * Disable sleep mode in LXT971
+        */
+       lxt971_no_sleep();
+#endif
+}

diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c
index e77dba8a869c1ac9d4961fcafec20fe8f6c1e696..1e0accbe0e515a3a26b3775561bf56d6aaf8b33c 100644 (file)
--- a/board/esd/hub405/hub405.c
+++ b/board/esd/hub405/hub405.c
@@ -26,10 +26,10 @@
 #include <command.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 extern void lxt971_no_sleep(void);
 
-
 int board_revision(void)
 {
        unsigned long osrl_reg;
@@ -110,8 +110,6 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
        volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
        volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
@@ -208,8 +206,6 @@ int misc_init_r (void)
  */
 int checkboard (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        char str[64];
        int i = getenv_r ("serial#", str, sizeof(str));
 
@@ -265,7 +261,7 @@ int testdram (void)
 
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 
 void nand_init(void)

diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
index 4be4d7e7d9eb352b97ea4e0a05fe37cbee7546c7..e5d2273f07f478e3a9c826c98792906e6b10a98f 100644 (file)
--- a/board/esd/pci405/pci405.c
+++ b/board/esd/pci405/pci405.c
@@ -30,6 +30,7 @@
 
 #include "pci405.h"
 
+DECLARE_GLOBAL_DATA_PTR;
 
 /* Prototypes */
 int gunzip(void *, int, unsigned char *, unsigned long *);
@@ -111,8 +112,6 @@ int board_revision(void)
 
 unsigned long fpga_done_state(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (gd->board_type < 2) {
                return FPGA_DONE_STATE_V11;
        } else {
@@ -123,8 +122,6 @@ unsigned long fpga_done_state(void)
 
 unsigned long fpga_init_state(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (gd->board_type < 2) {
                return FPGA_INIT_STATE_V11;
        } else {
@@ -320,8 +317,6 @@ int misc_init_r (void)
 
 int checkboard (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        char str[64];
        int i = getenv_r ("serial#", str, sizeof(str));
 

diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
index 5b9d0631f8e782140e4fd0a9e5f0c5d68f0a0cb5..37b92fb65a8dd482a433e0a592c9e5ba33a4ed6a 100644 (file)
--- a/board/esd/plu405/plu405.c
+++ b/board/esd/plu405/plu405.c
@@ -269,7 +269,7 @@ void ide_set_reset(int on)
 
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 
 void nand_init(void)

diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile
index 1281be70bec71a99422013958c6f98b0681770ac..741e4aacdcd4ede64069113dce79a5b480649118 100644 (file)
--- a/board/esd/pmc405/Makefile
+++ b/board/esd/pmc405/Makefile
@@ -30,7 +30,7 @@ CPLD    = ../common/xilinx_jtag/lenval.o \
          ../common/xilinx_jtag/micro.o \
          ../common/xilinx_jtag/ports.o
 
-OBJS   = $(BOARD).o ../common/misc.o $(CPLD)
+OBJS   = $(BOARD).o ../common/misc.o ../common/cmd_loadpci.o $(CPLD)
 
 $(LIB):        $(OBJS) $(SOBJS)
        $(AR) crv $@ $(OBJS)

diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
index 33b5f774d572385d584cd856159be6a0227fc03d..7499671aaf5d031c81994df148aa40a9a94a7dc8 100644 (file)
--- a/board/esd/pmc405/pmc405.c
+++ b/board/esd/pmc405/pmc405.c
@@ -1,6 +1,9 @@
 /*
  * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -26,10 +29,10 @@
 #include <command.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 extern void lxt971_no_sleep(void);
 
-
 /* fpga configuration data - not compressed, generated by bin2c */
 const unsigned char fpgadata[] =
 {
@@ -66,16 +69,27 @@ int board_early_init_f (void)
        mtebc (epcr, 0xa8400000);
 
        /*
-        * Setup GPIO pins (CS6+CS7 as GPIO)
+        * Setup GPIO pins
         */
-       mtdcr(cntrl0, mfdcr(cntrl0) | 0x00300000);
 
-       /*
-        * Configure GPIO pins
+       mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_FPGA_INIT | \
+                                       CFG_FPGA_DONE | \
+                                       CFG_XEREADY | \
+                                       CFG_NONMONARCH | \
+                                       CFG_REV1_2) << 5));
+
+       if (!(in32(GPIO0_IR) & CFG_REV1_2)) {
+               /* rev 1.2 boards */
+               mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_INTA_FAKE | \
+                                               CFG_SELF_RST) << 5));
+       }
+
+       out32(GPIO0_OR, 0);
+       out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA | CFG_XEREADY); /* setup for output */
+
+       /* - check if rev1_2 is low, then:
+        * - set/reset CFG_INTA_FAKE/CFG_SELF_RST in TCR to assert INTA# or SELFRST#
         */
-       out32(GPIO0_ODR, 0x00000000);                                /* no open drain pins */
-       out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA); /* setup for output */
-       out32(GPIO0_OR, 0);                                            /* outputs -> low   */
 
        return 0;
 }
@@ -83,30 +97,37 @@ int board_early_init_f (void)
 
 /* ------------------------------------------------------------------------- */
 
-int misc_init_f (void)
-{
-       return 0;  /* dummy implementation */
-}
-
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* adjust flash start and offset */
        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
        gd->bd->bi_flashoffset = 0;
 
+       out32(GPIO0_OR, in32(GPIO0_OR) | CFG_XEREADY); /* deassert EREADY# */
        return (0);
 }
 
+ushort pmc405_pci_subsys_deviceid(void)
+{
+       ulong val;
+       val = in32(GPIO0_IR);
+       if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
+               if (val & CFG_NONMONARCH) { /* monarch# signal */
+                       return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
+               }
+               return CFG_PCI_SUBSYS_DEVICEID_MONARCH;
+       }
+       return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
+}
 
 /*
  * Check Board Identity:
  */
-
 int checkboard (void)
 {
+       ulong val;
+
        char str[64];
        int i = getenv_r ("serial#", str, sizeof(str));
 
@@ -118,12 +139,18 @@ int checkboard (void)
                puts(str);
        }
 
-       putc ('\n');
+       val = in32(GPIO0_IR);
+       if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
+               puts(" rev1.2 (");
+               if (val & CFG_NONMONARCH) { /* monarch# signal */
+                       puts("non-");
+               }
+               puts("monarch)");
+       } else {
+               puts(" <=rev1.1");
+       }
 
-       /*
-        * Disable sleep mode in LXT971
-        */
-       lxt971_no_sleep();
+       putc ('\n');
 
        return 0;
 }
@@ -145,17 +172,19 @@ long int initdram (int board_type)
        return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
 
-/* ------------------------------------------------------------------------- */
 
-int testdram (void)
+/* ------------------------------------------------------------------------- */
+void reset_phy(void)
 {
-       /* TODO: XXX XXX XXX */
-       printf ("test: 16 MB - ok\n");
+#ifdef CONFIG_LXT971_NO_SLEEP
 
-       return (0);
+       /*
+        * Disable sleep mode in LXT971
+        */
+       lxt971_no_sleep();
+#endif
 }
 
-/* ------------------------------------------------------------------------- */
 
 int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {

diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c
index eda3fd9d9d8639d503a332281a1801d98a8e8c4b..22995b50209db6bb4d7fa1ae3e480bc599030311 100644 (file)
--- a/board/esd/voh405/voh405.c
+++ b/board/esd/voh405/voh405.c
@@ -343,7 +343,7 @@ void ide_set_reset(int on)
 
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 
 void nand_init(void)

diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c
index 445b8fc57662bb4d36292e069cead0eadd6e859b..8be552e2ea2511e3c2ae750db8b654670d022221 100644 (file)
--- a/board/esd/vom405/vom405.c
+++ b/board/esd/vom405/vom405.c
@@ -26,10 +26,10 @@
 #include <command.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 extern void lxt971_no_sleep(void);
 
-
 /* fpga configuration data - not compressed, generated by bin2c */
 const unsigned char fpgadata[] =
 {
@@ -81,8 +81,6 @@ int board_early_init_f (void)
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* adjust flash start and offset */
        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
        gd->bd->bi_flashoffset = 0;
@@ -97,7 +95,7 @@ int misc_init_r (void)
 
 int checkboard (void)
 {
-       unsigned char str[64];
+       char str[64];
        int i = getenv_r ("serial#", str, sizeof(str));
        int flashcnt;
        int delay;

diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c
index db24122c5ea7efb2860e4f35002cc55906226322..5a1a3f3e8ee68fe38e07384fb72ba2f9b45a8b76 100644 (file)
--- a/board/esd/wuh405/wuh405.c
+++ b/board/esd/wuh405/wuh405.c
@@ -239,7 +239,7 @@ int testdram (void)
 /* ------------------------------------------------------------------------- */
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 
 void nand_init(void)

diff --git a/board/etin/debris/debris.c b/board/etin/debris/debris.c
index 93c502c9de8fac2de5011d40ac0cd5a678daf540..08ed635f346032ce9d3e33733b4374bf4886d958 100644 (file)
--- a/board/etin/debris/debris.c
+++ b/board/etin/debris/debris.c
@@ -26,6 +26,8 @@
 #include <pci.h>
 #include <i2c.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard (void)
 {
        /*TODO: Check processor type */
@@ -170,8 +172,6 @@ void nvram_write(long dest, const void *src, size_t count)
 
 int misc_init_r(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Write ethernet addr in NVRAM for VxWorks */
        nvram_write(CFG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS,
                        (char*)&gd->bd->bi_enetaddr[0], 6);

diff --git a/board/etx094/etx094.c b/board/etx094/etx094.c
index dba3c1181e641d231b1be6d9467485b70fc40bac..eb58b5d52989641f0cfc408e5fa38a676e154120 100644 (file)
--- a/board/etx094/etx094.c
+++ b/board/etx094/etx094.c
@@ -24,6 +24,8 @@
 #include <common.h>
 #include <mpc8xx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 static long int dram_size (long int, long int *, long int);
@@ -90,8 +92,6 @@ const uint sdram_table[] = {
 
 int checkboard (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        char *s = getenv ("serial#");
        char *e;
 

diff --git a/board/evb4510/evb4510.c b/board/evb4510/evb4510.c
index 0008e5a000e32f1b3a337377eb01a47fd09f3fea..13abbb70136ad9f4e1eff95bfb5468dc0e7e30b2 100644 (file)
--- a/board/evb4510/evb4510.c
+++ b/board/evb4510/evb4510.c
@@ -25,6 +25,8 @@
 #include <asm/hardware.h>
 #include <command.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_EVB4510
 
 /* ------------------------------------------------------------------------- */
@@ -35,8 +37,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        icache_enable();
 
        /* address for the kernel command line */
@@ -52,7 +52,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
 #if CONFIG_NR_DRAM_BANKS == 2

diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c
index 6a9d1645694ebab6b3eace8289d5919f2fbaf739..ab599410b27f1a17d521e15b09684cf4c5553ffd 100644 (file)
--- a/board/evb64260/evb64260.c
+++ b/board/evb64260/evb64260.c
@@ -37,6 +37,9 @@
 #include "mpsc.h"
 #include "i2c.h"
 #include "64260.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_ZUMA_V2
 extern void zuma_mbox_init(void);
 #endif
@@ -323,8 +326,6 @@ int misc_init_r (void)
 void
 after_reloc(ulong dest_addr)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* check to see if we booted from the sram.  If so, move things
         * back to the way they should be. (we're running from main
         * memory at this point now */

diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c
index ee623ca569275e4976f08b1dc855705008f94864..98ac7f63df9917c8b2d47f46f64618fc684b3a63 100644 (file)
--- a/board/evb64260/mpsc.c
+++ b/board/evb64260/mpsc.c
@@ -32,6 +32,8 @@
 #include <malloc.h>
 #include "mpsc.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int (*mpsc_putchar)(char ch) = mpsc_putchar_early;
 
 static volatile unsigned int *rx_desc_base=NULL;
@@ -115,7 +117,6 @@ struct _tag_mirror_hack {
 int
 mpsc_putchar_early(char ch)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int mpsc=CHANNEL;
        int temp=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
        galmpsc_set_tcschar(mpsc,ch);
@@ -177,79 +178,82 @@ mpsc_putchar_sdma(char ch)
        return 0;
 }
 
-char
-mpsc_getchar(void)
+char mpsc_getchar (void)
 {
-    DECLARE_GLOBAL_DATA_PTR;
-    static unsigned int done = 0;
-    volatile char ch;
-    unsigned int len=0, idx=0, temp;
-
-    volatile unsigned int *p;
-
-
-    do {
-       p=&rx_desc_base[rx_desc_index*8];
-
-       INVALIDATE_DCACHE(&p[0], &p[1]);
-       /* Wait for character */
-       while (p[1] & DESC_OWNER){
-           udelay(100);
-           INVALIDATE_DCACHE(&p[0], &p[1]);
-       }
-
-       /* Handle error case */
-       if (p[1] & (1<<15)) {
-               printf("oops, error: %08x\n", p[1]);
-
-               temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,CHANNEL,GALMPSC_REG_GAP);
-               temp |= (1 << 23);
-               GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2, CHANNEL,GALMPSC_REG_GAP, temp);
-
-               /* Can't poll on abort bit, so we just wait. */
-               udelay(100);
+       static unsigned int done = 0;
+       volatile char ch;
+       unsigned int len = 0, idx = 0, temp;
 
-               galsdma_enable_rx();
-       }
-
-       /* Number of bytes left in this descriptor */
-       len = p[0] & 0xffff;
-
-       if (len) {
-           /* Where to look */
-           idx = 5;
-           if (done > 3) idx = 4;
-           if (done > 7) idx = 7;
-           if (done > 11) idx = 6;
-
-           INVALIDATE_DCACHE(&p[idx], &p[idx+1]);
-           ch = p[idx] & 0xff;
-           done++;
-       }
+       volatile unsigned int *p;
 
-       if (done < len) {
-               /* this descriptor has more bytes still
-                * shift down the char we just read, and leave the
-                * buffer in place for the next time around
-                */
-               p[idx] =  p[idx] >> 8;
-               FLUSH_DCACHE(&p[idx], &p[idx+1]);
-       }
 
-       if (done == len) {
-               /* nothing left in this descriptor.
-                * go to next one
-                */
-               p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST;
-               p[0] = 0x00100000;
-               FLUSH_DCACHE(&p[0], &p[1]);
-               /* Next descriptor */
-               rx_desc_index = (rx_desc_index + 1) % RX_DESC;
-               done = 0;
-       }
-    } while (len==0);  /* galileo bug.. len might be zero */
-
-    return ch;
+       do {
+               p = &rx_desc_base[rx_desc_index * 8];
+
+               INVALIDATE_DCACHE (&p[0], &p[1]);
+               /* Wait for character */
+               while (p[1] & DESC_OWNER) {
+                       udelay (100);
+                       INVALIDATE_DCACHE (&p[0], &p[1]);
+               }
+
+               /* Handle error case */
+               if (p[1] & (1 << 15)) {
+                       printf ("oops, error: %08x\n", p[1]);
+
+                       temp = GTREGREAD_MIRROR (GALMPSC_CHANNELREG_2,
+                                                CHANNEL, GALMPSC_REG_GAP);
+                       temp |= (1 << 23);
+                       GT_REG_WRITE_MIRROR (GALMPSC_CHANNELREG_2, CHANNEL,
+                                            GALMPSC_REG_GAP, temp);
+
+                       /* Can't poll on abort bit, so we just wait. */
+                       udelay (100);
+
+                       galsdma_enable_rx ();
+               }
+
+               /* Number of bytes left in this descriptor */
+               len = p[0] & 0xffff;
+
+               if (len) {
+                       /* Where to look */
+                       idx = 5;
+                       if (done > 3)
+                               idx = 4;
+                       if (done > 7)
+                               idx = 7;
+                       if (done > 11)
+                               idx = 6;
+
+                       INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
+                       ch = p[idx] & 0xff;
+                       done++;
+               }
+
+               if (done < len) {
+                       /* this descriptor has more bytes still
+                        * shift down the char we just read, and leave the
+                        * buffer in place for the next time around
+                        */
+                       p[idx] = p[idx] >> 8;
+                       FLUSH_DCACHE (&p[idx], &p[idx + 1]);
+               }
+
+               if (done == len) {
+                       /* nothing left in this descriptor.
+                        * go to next one
+                        */
+                       p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST;
+                       p[0] = 0x00100000;
+                       FLUSH_DCACHE (&p[0], &p[1]);
+                       /* Next descriptor */
+                       rx_desc_index = (rx_desc_index + 1) % RX_DESC;
+                       done = 0;
+               }
+       } while (len == 0);     /* galileo bug.. len might be zero */
+
+       return ch;
 }
 
 int
@@ -266,8 +270,6 @@ mpsc_test_char(void)
 int
 mpsc_init(int baud)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        memset(MIRROR_HACK, 0, sizeof(struct _tag_mirror_hack));
        MIRROR_HACK->GALMPSC_ROUTING_REGISTER_M=0x3fffffff;
 
@@ -382,7 +384,6 @@ mpsc_init2(void)
 int
 galbrg_set_baudrate(int channel, int rate)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int clock;
 
        galbrg_disable(channel);
@@ -410,7 +411,6 @@ galbrg_set_baudrate(int channel, int rate)
 static int
 galbrg_set_CDV(int channel, int value)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int temp;
 
        temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
@@ -424,7 +424,6 @@ galbrg_set_CDV(int channel, int value)
 static int
 galbrg_enable(int channel)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int temp;
 
        temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
@@ -437,7 +436,6 @@ galbrg_enable(int channel)
 static int
 galbrg_disable(int channel)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int temp;
 
        temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
@@ -450,7 +448,6 @@ galbrg_disable(int channel)
 static int
 galbrg_set_clksrc(int channel, int value)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int temp;
 
        temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP);
@@ -583,7 +580,6 @@ galsdma_set_burstsize(int channel, unsigned int value)
 static int
 galmpsc_connect(int channel, int connect)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int temp;
 
        temp = GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER);
@@ -629,7 +625,6 @@ galmpsc_route_serial(int channel, int connect)
 static int
 galmpsc_route_rx_clock(int channel, int brg)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int temp;
 
        temp = GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE);
@@ -647,7 +642,6 @@ galmpsc_route_rx_clock(int channel, int brg)
 static int
 galmpsc_route_tx_clock(int channel, int brg)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int temp;
 
        temp = GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE);
@@ -688,7 +682,6 @@ galmpsc_write_config_regs(int mpsc, int mode)
 static int
 galmpsc_config_channel_regs(int mpsc)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, 0);
        GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, 0);
        GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 1);
@@ -709,7 +702,6 @@ galmpsc_config_channel_regs(int mpsc)
 static int
 galmpsc_set_brkcnt(int mpsc, int value)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int temp;
 
        temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
@@ -723,7 +715,6 @@ galmpsc_set_brkcnt(int mpsc, int value)
 static int
 galmpsc_set_tcschar(int mpsc, int value)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int temp;
 
        temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
@@ -737,7 +728,6 @@ galmpsc_set_tcschar(int mpsc, int value)
 static int
 galmpsc_set_char_length(int mpsc, int value)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int temp;
 
        temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
@@ -751,7 +741,6 @@ galmpsc_set_char_length(int mpsc, int value)
 static int
 galmpsc_set_stop_bit_length(int mpsc, int value)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int temp;
 
        temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
@@ -764,7 +753,6 @@ galmpsc_set_stop_bit_length(int mpsc, int value)
 static int
 galmpsc_set_parity(int mpsc, int value)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int temp;
 
        temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
@@ -784,7 +772,6 @@ galmpsc_set_parity(int mpsc, int value)
 static int
 galmpsc_enter_hunt(int mpsc)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int temp;
 
        temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
@@ -802,7 +789,6 @@ galmpsc_enter_hunt(int mpsc)
 static int
 galmpsc_shutdown(int mpsc)
 {
-       DECLARE_GLOBAL_DATA_PTR;
 #if 0
        unsigned int temp;
 

diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c
index 8d63c6fa2ab03f169f1af180b60859ed60ab9965..fae6d1090dfdc7bb295deffb355f408cb657132f 100644 (file)
--- a/board/evb64260/sdram_init.c
+++ b/board/evb64260/sdram_init.c
@@ -35,6 +35,8 @@
 #include "i2c.h"
 #include "64260.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* #define     DEBUG */
 #define        MAP_PCI
 
@@ -199,7 +201,6 @@ static int check_dimm (uchar slot, sdram_info_t * info)
  * the array which is passed in with the relevant information */
 static int check_dimm (uchar slot, sdram_info_t * info)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
        int ret;
        uchar rows, cols, sdram_banks, supp_cal, width, cal_val;

diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c
index d9c7a157c10abd616c24048408cf67433a2571b7..191445c691c4f0d9978f624f703d79af90f88717 100644 (file)
--- a/board/evb64260/serial.c
+++ b/board/evb64260/serial.c
@@ -39,6 +39,8 @@
 
 #include "mpsc.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
 const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1,
                                (NS16550_t) CFG_NS16550_COM2 };
@@ -48,8 +50,6 @@ const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1,
 
 int serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
 #if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
        int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
 #endif
@@ -90,8 +90,6 @@ serial_tstc(void)
 void
 serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate);
 }
 
@@ -99,8 +97,6 @@ serial_setbrg (void)
 
 int serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
 
 #ifdef CFG_INIT_CHAN1
@@ -137,8 +133,6 @@ serial_tstc(void)
 void
 serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
 
 #ifdef CFG_INIT_CHAN1

diff --git a/board/ezkit533/Makefile b/board/ezkit533/Makefile
new file mode 100644 (file)
index 0000000..c9b3c92
--- /dev/null
+++ b/board/ezkit533/Makefile
@@ -0,0 +1,44 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   = $(BOARD).o flash.o ezkit533.o
+
+$(LIB):        .depend $(OBJS)
+       $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

diff --git a/board/ezkit533/config.mk b/board/ezkit533/config.mk
new file mode 100644 (file)
index 0000000..36c9f99
--- /dev/null
+++ b/board/ezkit533/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x01FC0000
+PLATFORM_CPPFLAGS += -I$(TOPDIR)

diff --git a/board/ezkit533/ezkit533.c b/board/ezkit533/ezkit533.c
new file mode 100644 (file)
index 0000000..8d6c8de
--- /dev/null
+++ b/board/ezkit533/ezkit533.c
@@ -0,0 +1,72 @@
+/*
+ * U-boot - ezkit533.c
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_MISC_INIT_R)
+#include "psd4256.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+       printf("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
+       printf("Board: ADI BF533 EZ-Kit Lite board\n");
+       printf("       Support: http://blackfin.uclinux.org/\n");
+       printf("       Richard Klingler <richard@uclinux.net>\n");
+       return 0;
+}
+
+long int initdram(int board_type)
+{
+#ifdef DEBUG
+       int brate;
+       char *tmp = getenv("baudrate");
+       brate = simple_strtoul(tmp, NULL, 16);
+       printf("Serial Port initialized with Baud rate = %x\n",brate);
+       printf("SDRAM attributes:\n");
+       printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
+              "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
+              3, 3, 6, 2, 3);
+       printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+       printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
+#endif
+       gd->bd->bi_memstart = CFG_SDRAM_BASE;
+       gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+       return CFG_MAX_RAM_SIZE;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+       /* Set direction bits for Video en/decoder reset as output      */
+       *(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST;
+       /* Deactivate Video en/decoder reset lines                      */
+       *(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST;
+}
+#endif

diff --git a/board/ezkit533/flash-defines.h b/board/ezkit533/flash-defines.h
new file mode 100644 (file)
index 0000000..8f9dff5
--- /dev/null
+++ b/board/ezkit533/flash-defines.h
@@ -0,0 +1,130 @@
+/*
+ * U-boot - flash-defines.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLASHDEFINES_H__
+#define __FLASHDEFINES_H__
+
+#include <common.h>
+
+#define V_ULONG(a)             (*(volatile unsigned long *)( a ))
+#define V_BYTE(a)              (*(volatile unsigned char *)( a ))
+#define TRUE                   0x1
+#define FALSE                  0x0
+#define BUFFER_SIZE            0x80000
+#define NO_COMMAND             0
+#define GET_CODES              1
+#define RESET                  2
+#define WRITE                  3
+#define FILL                   4
+#define ERASE_ALL              5
+#define ERASE_SECT             6
+#define READ                   7
+#define GET_SECTNUM            8
+#define FLASH_START_L          0x0000
+#define FLASH_START_H          0x2000
+#define FLASH_TOT_SECT         40
+#define FLASH_SIZE             0x220000
+#define FLASH_MAN_ST           2
+#define CFG_FLASH0_BASE                0x20000000
+#define RESET_VAL              0xF0
+
+
+asm("#define FLASH_START_L 0x0000");
+asm("#define FLASH_START_H 0x2000");
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+int get_codes(void);
+int poll_toggle_bit(long lOffset);
+void reset_flash(void);
+int erase_flash(void);
+int erase_block_flash(int,unsigned long);
+void unlock_flash(long lOffset);
+int write_data(long lStart, long lCount, long lStride, int *pnData);
+int FillData(long lStart, long lCount, long lStride, int *pnData);
+int read_data(long lStart, long lCount, long lStride, int *pnData);
+int read_flash(long nOffset, int *pnValue);
+int write_flash(long nOffset, int nValue);
+void get_sector_number(long lOffset, int *pnSector);
+int GetSectorProtectionStatus(flash_info_t * info, int nSector);
+int GetOffset(int nBlock);
+int AFP_NumSectors = 40;
+long AFP_SectorSize1 = 0x10000;
+int AFP_SectorSize2 = 0x4000;
+
+#define WRITESEQ1              0x0AAA
+#define WRITESEQ2              0x0554
+#define WRITESEQ3              0x0AAA
+#define WRITESEQ4              0x0AAA
+#define WRITESEQ5              0x0554
+#define WRITESEQ6              0x0AAA
+#define WRITEDATA1             0xaa
+#define WRITEDATA2             0x55
+#define WRITEDATA3             0x80
+#define WRITEDATA4             0xaa
+#define WRITEDATA5             0x55
+#define WRITEDATA6             0x10
+#define PriFlashABegin         0
+#define SecFlashABegin         32
+#define SecFlashBBegin         36
+#define PriFlashAOff           0x0
+#define PriFlashBOff           0x100000
+#define SecFlashAOff           0x200000
+#define SecFlashBOff           0x280000
+#define INVALIDLOCNSTART       0x20270000
+#define INVALIDLOCNEND         0x20280000
+#define BlockEraseVal          0x30
+#define UNLOCKDATA1            0xaa
+#define UNLOCKDATA2            0x55
+#define UNLOCKDATA3            0xa0
+#define GETCODEDATA1           0xaa
+#define GETCODEDATA2           0x55
+#define GETCODEDATA3           0x90
+#define SecFlashASec1Off       0x200000
+#define SecFlashASec2Off       0x204000
+#define SecFlashASec3Off       0x206000
+#define SecFlashASec4Off       0x208000
+#define SecFlashAEndOff                0x210000
+#define SecFlashBSec1Off       0x280000
+#define SecFlashBSec2Off       0x284000
+#define SecFlashBSec3Off       0x286000
+#define SecFlashBSec4Off       0x288000
+#define SecFlashBEndOff                0x290000
+
+#define SECT32                 32
+#define SECT33                 33
+#define SECT34                 34
+#define SECT35                 35
+#define SECT36                 36
+#define SECT37                 37
+#define SECT38                 38
+#define SECT39                 39
+
+#define FLASH_SUCCESS  0
+#define FLASH_FAIL     -1
+
+#endif

diff --git a/board/ezkit533/flash.c b/board/ezkit533/flash.c
new file mode 100644 (file)
index 0000000..b0a0796
--- /dev/null
+++ b/board/ezkit533/flash.c
@@ -0,0 +1,476 @@
+/*
+ * U-boot - flash.c Flash driver for PSD4256GV
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "flash-defines.h"
+
+void flash_reset(void)
+{
+       reset_flash();
+}
+
+unsigned long flash_get_size(ulong baseaddr, flash_info_t * info,
+                            int bank_flag)
+{
+       int id = 0, i = 0;
+       static int FlagDev = 1;
+
+       id = get_codes();
+       if(FlagDev)     {
+#ifdef DEBUG
+               printf("Device ID of the Flash is %x\n", id);
+#endif
+               FlagDev = 0;
+       }
+       info->flash_id = id;
+
+       switch (bank_flag) {
+       case 0:
+               for (i = PriFlashABegin; i < SecFlashABegin; i++)
+                       info->start[i] = (baseaddr + (i * AFP_SectorSize1));
+               info->size = 0x200000;
+               info->sector_count = 32;
+               break;
+       case 1:
+               info->start[0] = baseaddr + SecFlashASec1Off;
+               info->start[1] = baseaddr + SecFlashASec2Off;
+               info->start[2] = baseaddr + SecFlashASec3Off;
+               info->start[3] = baseaddr + SecFlashASec4Off;
+               info->size = 0x10000;
+               info->sector_count = 4;
+               break;
+       case 2:
+               info->start[0] = baseaddr + SecFlashBSec1Off;
+               info->start[1] = baseaddr + SecFlashBSec2Off;
+               info->start[2] = baseaddr + SecFlashBSec3Off;
+               info->start[3] = baseaddr + SecFlashBSec4Off;
+               info->size = 0x10000;
+               info->sector_count = 4;
+               break;
+       }
+       return (info->size);
+}
+
+unsigned long flash_init(void)
+{
+       unsigned long size_b0, size_b1, size_b2;
+       int i;
+
+       size_b0 = size_b1 = size_b2 = 0;
+#ifdef DEBUG
+       printf("Flash Memory Start 0x%x\n", CFG_FLASH_BASE);
+       printf("Memory Map for the Flash\n");
+       printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n");
+       printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n");
+       printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n");
+       printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n");
+       printf("Please type command flinfo for information on Sectors \n");
+#endif
+       for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+               flash_info[i].flash_id = FLASH_UNKNOWN;
+       }
+
+       size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0], 0);
+       size_b1 = flash_get_size(CFG_FLASH0_BASE, &flash_info[1], 1);
+       size_b2 = flash_get_size(CFG_FLASH0_BASE, &flash_info[2], 2);
+
+       if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+               printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+                       size_b0, size_b0 >> 20);
+       }
+
+       (void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH0_BASE,(flash_info[0].start[2] - 1),&flash_info[0]);
+
+       return (size_b0 + size_b1 + size_b2);
+}
+
+void flash_print_info(flash_info_t * info)
+{
+       int i;
+
+       if (info->flash_id == FLASH_UNKNOWN) {
+               printf("missing or unknown FLASH type\n");
+               return;
+       }
+
+       switch (info->flash_id) {
+       case FLASH_PSD4256GV:
+               printf("ST Microelectronics ");
+               break;
+       default:
+               printf("Unknown Vendor ");
+               break;
+       }
+       for (i = 0; i < info->sector_count; ++i) {
+               if ((i % 5) == 0)
+                       printf("\n   ");
+               printf(" %08lX%s",
+                       info->start[i],
+                       info->protect[i] ? " (RO)" : "     ");
+       }
+       printf("\n");
+       return;
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+       int cnt = 0,i;
+       int prot,sect;
+
+       prot = 0;
+       for (sect = s_first; sect <= s_last; ++sect) {
+               if (info->protect[sect])
+                       prot++;
+       }
+
+       if (prot)
+               printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+       else
+               printf ("\n");
+
+       cnt = s_last - s_first + 1;
+
+       if (cnt == FLASH_TOT_SECT) {
+               printf("Erasing flash, Please Wait \n");
+               if(erase_flash() < 0) {
+                       printf("Erasing flash failed \n");
+                       return FLASH_FAIL;
+               }
+       } else {
+               printf("Erasing Flash locations, Please Wait\n");
+               for (i = s_first; i <= s_last; i++) {
+                       if (info->protect[i] == 0) {    /* not protected */
+                               if(erase_block_flash(i, info->start[i]) < 0) {
+                                       printf("Error Sector erasing \n");
+                                       return FLASH_FAIL;
+                               }
+                       }
+               }
+       }
+       return FLASH_SUCCESS;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+       int ret;
+
+       ret = write_data(addr, cnt, 1, (int *) src);
+       if(ret == FLASH_FAIL)
+               return ERR_NOT_ERASED;
+       return FLASH_SUCCESS;
+}
+
+
+int write_data(long lStart, long lCount, long lStride, int *pnData)
+{
+       long i = 0;
+       int j = 0;
+       unsigned long ulOffset = lStart - CFG_FLASH_BASE;
+       int d;
+       int iShift = 0;
+       int iNumWords = 2;
+       int nLeftover = lCount % 4;
+       int nSector = 0;
+
+       for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
+               for (iShift = 0, j = 0; (j < iNumWords);
+                       j++, ulOffset += (lStride * 2)) {
+                       if ((ulOffset >= INVALIDLOCNSTART)
+                       && (ulOffset < INVALIDLOCNEND)) {
+                               printf("Invalid locations, Try writing to another location \n");
+                               return FLASH_FAIL;
+                       }
+                       get_sector_number(ulOffset, &nSector);
+                       read_flash(ulOffset,&d);
+                       if(d != 0xffff) {
+                               printf("Flash not erased at offset 0x%x Please erase to reprogram \n",ulOffset);
+                               return FLASH_FAIL;
+                       }
+                       unlock_flash(ulOffset);
+                       if(write_flash(ulOffset, (pnData[i] >> iShift)) < 0) {
+                               printf("Error programming the flash \n");
+                               return FLASH_FAIL;
+                       }
+                       iShift += 16;
+               }
+       }
+       if (nLeftover > 0) {
+               if ((ulOffset >= INVALIDLOCNSTART)
+                       && (ulOffset < INVALIDLOCNEND))
+                               return FLASH_FAIL;
+               get_sector_number(ulOffset, &nSector);
+               read_flash(ulOffset,&d);
+               if(d != 0xffff) {
+                       printf("Flash already programmed. Please erase to reprogram \n");
+                       printf("uloffset = 0x%x \t d = 0x%x\n",ulOffset,d);
+                       return FLASH_FAIL;
+               }
+               unlock_flash(ulOffset);
+               if(write_flash(ulOffset, pnData[i]) < 0) {
+                       printf("Error programming the flash \n");
+                       return FLASH_FAIL;
+               }
+       }
+       return FLASH_SUCCESS;
+}
+
+int read_data(long ulStart, long lCount, long lStride, int *pnData)
+{
+       long i = 0;
+       int j = 0;
+       long ulOffset = ulStart;
+       int iShift = 0;
+       int iNumWords = 2;
+       int nLeftover = lCount % 4;
+       int nHi, nLow;
+       int nSector = 0;
+
+       for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
+               for (iShift = 0, j = 0; j < iNumWords; j += 2) {
+                       if ((ulOffset >= INVALIDLOCNSTART)
+                               && (ulOffset < INVALIDLOCNEND))
+                                       return FLASH_FAIL;
+
+                       get_sector_number(ulOffset, &nSector);
+                       read_flash(ulOffset, &nLow);
+                       ulOffset += (lStride * 2);
+                       read_flash(ulOffset, &nHi);
+                       ulOffset += (lStride * 2);
+                       pnData[i] = (nHi << 16) | nLow;
+               }
+       }
+       if (nLeftover > 0) {
+               if ((ulOffset >= INVALIDLOCNSTART)
+                       && (ulOffset < INVALIDLOCNEND))
+                               return FLASH_FAIL;
+
+               get_sector_number(ulOffset, &nSector);
+               read_flash(ulOffset, &pnData[i]);
+       }
+       return FLASH_SUCCESS;
+}
+
+int write_flash(long nOffset, int nValue)
+{
+       long addr;
+
+       addr = (CFG_FLASH_BASE + nOffset);
+       asm("ssync;");
+       *(unsigned volatile short *) addr = nValue;
+       asm("ssync;");
+       if(poll_toggle_bit(nOffset) < 0)
+               return FLASH_FAIL;
+       return FLASH_SUCCESS;
+}
+
+int read_flash(long nOffset, int *pnValue)
+{
+       int nValue = 0x0;
+       long addr = (CFG_FLASH_BASE + nOffset);
+
+       if (nOffset != 0x2)
+               reset_flash();
+       asm("ssync;");
+       nValue = *(volatile unsigned short *) addr;
+       asm("ssync;");
+       *pnValue = nValue;
+       return TRUE;
+}
+
+int poll_toggle_bit(long lOffset)
+{
+       unsigned int u1,u2;
+       unsigned long timeout = 0xFFFFFFFF;
+       volatile unsigned long *FB = (volatile unsigned long *)(0x20000000 + lOffset);
+       while(1) {
+               if(timeout < 0)
+                       break;
+               u1 = *(volatile unsigned short *)FB;
+               u2 = *(volatile unsigned short *)FB;
+               if((u1 & 0x0040) == (u2 & 0x0040))
+                       return FLASH_SUCCESS;
+               if((u2 & 0x0020) == 0x0000)
+                       continue;
+               u1 = *(volatile unsigned short *)FB;
+               if((u2 & 0x0040) == (u1 & 0x0040))
+                       return FLASH_SUCCESS;
+               else {
+                       reset_flash();
+                       return FLASH_FAIL;
+               }
+               timeout--;
+       }
+       printf("Time out occured \n");
+       if(timeout <0)  return FLASH_FAIL;
+}
+
+void reset_flash(void)
+{
+       write_flash(WRITESEQ1, RESET_VAL);
+       /* Wait for 10 micro seconds */
+       udelay(10);
+}
+
+int erase_flash(void)
+{
+       write_flash(WRITESEQ1, WRITEDATA1);
+       write_flash(WRITESEQ2, WRITEDATA2);
+       write_flash(WRITESEQ3, WRITEDATA3);
+       write_flash(WRITESEQ4, WRITEDATA4);
+       write_flash(WRITESEQ5, WRITEDATA5);
+       write_flash(WRITESEQ6, WRITEDATA6);
+
+       if(poll_toggle_bit(0x0000) < 0)
+               return FLASH_FAIL;
+
+       write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1);
+       write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2);
+       write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3);
+       write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4);
+       write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5);
+       write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6);
+
+       if(poll_toggle_bit(SecFlashASec1Off) < 0)
+               return FLASH_FAIL;
+
+       write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1);
+       write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2);
+       write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3);
+       write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4);
+       write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5);
+       write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6);
+
+       if(poll_toggle_bit(PriFlashBOff) <0)
+               return FLASH_FAIL;
+
+       write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1);
+       write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2);
+       write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3);
+       write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4);
+       write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5);
+       write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6);
+
+       if(poll_toggle_bit(SecFlashBOff) < 0)
+               return FLASH_FAIL;
+
+       return FLASH_SUCCESS;
+}
+
+int erase_block_flash(int nBlock, unsigned long address)
+{
+       long ulSectorOff = 0x0;
+
+       if ((nBlock < 0) || (nBlock > AFP_NumSectors))
+               return FALSE;
+
+       ulSectorOff = (address - CFG_FLASH_BASE);
+
+       write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
+       write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
+       write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
+       write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
+       write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
+
+       write_flash(ulSectorOff, BlockEraseVal);
+
+       if(poll_toggle_bit(ulSectorOff) < 0)
+               return FLASH_FAIL;
+
+       return FLASH_SUCCESS;
+}
+
+void unlock_flash(long ulOffset)
+{
+       unsigned long ulOffsetAddr = ulOffset;
+       ulOffsetAddr &= 0xFFFF0000;
+
+       write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
+       write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
+       write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
+}
+
+int get_codes()
+{
+       int dev_id = 0;
+
+       write_flash(WRITESEQ1, GETCODEDATA1);
+       write_flash(WRITESEQ2, GETCODEDATA2);
+       write_flash(WRITESEQ3, GETCODEDATA3);
+
+       read_flash(0x0002, &dev_id);
+       dev_id &= 0x00FF;
+
+       reset_flash();
+
+       return dev_id;
+}
+
+void get_sector_number(long ulOffset, int *pnSector)
+{
+       int nSector = 0;
+
+       if (ulOffset >= SecFlashAOff) {
+               if ((ulOffset < SecFlashASec1Off)
+                       && (ulOffset < SecFlashASec2Off)) {
+                               nSector = SECT32;
+               } else if ((ulOffset >= SecFlashASec2Off)
+                       && (ulOffset < SecFlashASec3Off)) {
+                               nSector = SECT33;
+               } else if ((ulOffset >= SecFlashASec3Off)
+                       && (ulOffset < SecFlashASec4Off)) {
+                               nSector = SECT34;
+               } else if ((ulOffset >= SecFlashASec4Off)
+                       && (ulOffset < SecFlashAEndOff)) {
+                               nSector = SECT35;
+               }
+       } else if (ulOffset >= SecFlashBOff) {
+               if ((ulOffset < SecFlashBSec1Off)
+                       && (ulOffset < SecFlashBSec2Off)) {
+                               nSector = SECT36;
+               }
+               if ((ulOffset < SecFlashBSec2Off)
+                       && (ulOffset < SecFlashBSec3Off)) {
+                               nSector = SECT37;
+               }
+               if ((ulOffset < SecFlashBSec3Off)
+                       && (ulOffset < SecFlashBSec4Off)) {
+                               nSector = SECT38;
+               }
+               if ((ulOffset < SecFlashBSec4Off)
+                       && (ulOffset < SecFlashBEndOff)) {
+                               nSector = SECT39;
+               }
+       } else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) {
+               nSector = ulOffset & 0xffff0000;
+               nSector = ulOffset >> 16;
+               nSector = nSector & 0x000ff;
+       }
+
+       if ((nSector >= 0) && (nSector < AFP_NumSectors)) {
+               *pnSector = nSector;
+       }
+}

diff --git a/board/ezkit533/psd4256.h b/board/ezkit533/psd4256.h
new file mode 100644 (file)
index 0000000..01f6566
--- /dev/null
+++ b/board/ezkit533/psd4256.h
@@ -0,0 +1,67 @@
+/*
+ * U-boot - psd4256.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Flash A/B Port A configuration registers.
+ * Addresses are offset values to CFG_FLASH1_BASE
+ * for Flash A and CFG_FLASH2_BASE for Flash B.
+ */
+
+#define        PSD_PORTA_DIN   0x070000
+#define        PSD_PORTA_DOUT  0x070004
+#define        PSD_PORTA_DIR   0x070006
+
+/*
+ * Flash A/B Port B configuration registers
+ * Addresses are offset values to CFG_FLASH1_BASE
+ * for Flash A and CFG_FLASH2_BASE for Flash B.
+ */
+
+#define        PSD_PORTB_DIN   0x070001
+#define        PSD_PORTB_DOUT  0x070005
+#define        PSD_PORTB_DIR   0x070007
+
+/*
+ * Flash A Port A Bit definitions
+ */
+
+#define        PSDA_PPICLK1    0x20            /* PPI Clock select bit 1               */
+#define        PSDA_PPICLK0    0x10            /* PPI Clock select bit 0               */
+#define        PSDA_VDEC_RST   0x08            /* Video decoder reset, 0 = RESET       */
+#define        PSDA_VENC_RST   0x04            /* Video encoder reset, 0 = RESET       */
+#define        PSDA_CODEC_RST  0x01            /* Codec reset, 0 = RESET               */
+
+/*
+ * Flash A Port B Bit definitions
+ */
+
+#define        PSDA_LED9       0x20            /* LED 9, 1 = LED ON                    */
+#define        PSDA_LED8       0x10            /* LED 8, 1 = LED ON                    */
+#define        PSDA_LED7       0x08            /* LED 7, 1 = LED ON                    */
+#define        PSDA_LED6       0x04            /* LED 6, 1 = LED ON                    */
+#define        PSDA_LED5       0x02            /* LED 5, 1 = LED ON                    */
+#define        PSDA_LED4       0x01            /* LED 4, 1 = LED ON                    */

diff --git a/board/ezkit533/u-boot.lds b/board/ezkit533/u-boot.lds
new file mode 100644 (file)
index 0000000..10203ff
--- /dev/null
+++ b/board/ezkit533/u-boot.lds
@@ -0,0 +1,148 @@
+/*
+ * U-boot - u-boot.lds
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(bfin)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)      }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)      }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)       }
+  .rela.got      : { *(.rela.got)      }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)       }
+  .rela.bss      : { *(.rela.bss)      }
+  .rel.plt       : { *(.rel.plt)       }
+  .rela.plt      : { *(.rela.plt)      }
+  .init          : { *(.init)          }
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within */
+    /* the sector before the environment sector. If it throws  */
+    /* an error during compilation remove an object here to get        */
+    /* it linked after the configuration sector.               */
+
+    cpu/bf533/start.o          (.text)
+    cpu/bf533/start1.o         (.text)
+    cpu/bf533/traps.o          (.text)
+    cpu/bf533/interrupt.o      (.text)
+    cpu/bf533/serial.o         (.text)
+    common/dlmalloc.o          (.text)
+    lib_generic/vsprintf.o     (.text)
+    lib_generic/crc32.o                (.text)
+    lib_generic/zlib.o         (.text)
+    board/ezkit533/ezkit533.o          (.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o       (.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

diff --git a/board/fads/fads.c b/board/fads/fads.c
index 013b3cb15506545cb1e430b6e655127b9020b9d3..7b04af56c9f7afa9afb6192be1f47bcf956624a5 100644 (file)
--- a/board/fads/fads.c
+++ b/board/fads/fads.c
@@ -726,24 +726,23 @@ static void checkdboard(void)
 
 int checkboard (void)
 {
-       /* get revision from BCSR 3 */
+#if   defined(CONFIG_MPC86xADS)
+       puts ("Board: MPC86xADS\n");
+#elif defined(CONFIG_MPC885ADS)
+       puts ("Board: MPC885ADS\n");
+#else /* Only old ADS/FADS have got revision ID in BCSR3 */
        uint r =  (((*((uint *) BCSR3) >> 23) & 1) << 3)
                | (((*((uint *) BCSR3) >> 19) & 1) << 2)
                | (((*((uint *) BCSR3) >> 16) & 3));
 
        puts ("Board: ");
-
-#if defined(CONFIG_MPC86xADS)
-       puts ("MPC86xADS");
-#elif defined(CONFIG_MPC885ADS)
-       puts ("MPC885ADS");
-       r = 0; /* I've got NR (No Revision) board */
-#elif defined(CONFIG_FADS)
+#if defined(CONFIG_FADS)
        puts ("FADS");
        checkdboard ();
 #else
        puts ("ADS");
 #endif
+
        puts (" rev ");
 
        switch (r) {
@@ -758,13 +757,9 @@ int checkboard (void)
                puts ("A - warning, read errata \n");
                break;
        case 0x03:
-               puts ("B \n");
+               puts ("B\n");
                break;
-#elif defined(CONFIG_MPC885ADS)
-       case 0x00:
-               puts ("NR\n");
-               break;
-#else  /* FADS and newer */
+#else  /* FADS */
        case 0x00:
                puts ("ENG\n");
                break;
@@ -776,6 +771,7 @@ int checkboard (void)
                printf ("unknown (0x%x)\n", r);
                return -1;
        }
+#endif /* CONFIG_MPC86xADS */
 
        return 0;
 }
@@ -848,7 +844,7 @@ int pcmcia_init(void)
        switch ((pcmp->pcmc_pipr >> 14) & 3)
 #endif
        {
-       case 0x00 :
+       case 0x03 :
                printf("5V");
                v = 5;
                break;
@@ -860,7 +856,7 @@ int pcmcia_init(void)
                v = 5;
 #endif
                break;
-       case 0x03 :
+       case 0x00 :
                printf("5V, 3V and x.xV");
 #ifdef CONFIG_FADS
                v = 3; /* User lower voltage if supported! */

diff --git a/board/fads/fads.h b/board/fads/fads.h
index 1127c7ff726f43330af519ad489a0f020d198647..e981be03b5a59cc2c12067ad38f1de4598a9c593 100644 (file)
--- a/board/fads/fads.h
+++ b/board/fads/fads.h
@@ -55,18 +55,26 @@
 #define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
 #endif
 
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND                                                     \
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NFSBOOTCOMMAND                                                  \
     "dhcp;"                                                                    \
-    "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "                \
-    "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"       \
+    "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath "                      \
+    "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"             \
     "bootm"
 
+#define CONFIG_BOOTCOMMAND                                                     \
+    "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
+    "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"             \
+    "bootm fe080000"
+
+#undef CONFIG_BOOTARGS
+
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 
 /*
- * New MPC86xADS and Duet provide two Ethernet connectivity options:
+ * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
  * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
  * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
  * got FEC so FEC is the default.
@@ -89,7 +97,9 @@
 
 #ifndef CONFIG_COMMANDS
 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL   \
+                        | CFG_CMD_ASKENV \
                         | CFG_CMD_DHCP   \
+                        | CFG_CMD_ECHO   \
                         | CFG_CMD_IMMAP  \
                         | CFG_CMD_JFFS2  \
                         | CFG_CMD_MII    \
@@ -104,16 +114,18 @@
 /*
  * Miscellaneous configurable options
  */
-#undef CFG_LONGHELP                    /* undef to save memory         */
-#define        CFG_PROMPT              "=>"    /* Monitor Command Prompt       */
+#define        CFG_PROMPT              "=>"            /* Monitor Command Prompt       */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2    "> "
+#define        CFG_LONGHELP                            /* #undef to save memory        */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define        CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
+#define        CFG_CBSIZE              1024            /* Console I/O Buffer Size      */
 #else
-#define        CFG_CBSIZE      256             /* Console I/O Buffer Size      */
+#define        CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 #endif
-#define        CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define        CFG_MAXARGS     16              /* max number of command args   */
-#define CFG_BARGSIZE   CFG_CBSIZE      /* Boot Argument Buffer Size    */
+#define        CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size  */
+#define        CFG_MAXARGS             16              /* max number of command args   */
+#define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size    */
 
 #define CFG_LOAD_ADDR          0x00100000
 
@@ -126,6 +138,7 @@
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
  */
+
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
@@ -148,6 +161,14 @@
 #define        CFG_SDRAM_BASE          0x00000000
 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
 #define        CFG_SDRAM_SIZE          0x00800000              /* 8 Mbyte */
+/*
+ * 2048        SDRAM rows
+ * 1000        factor s -> ms
+ * 64  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4   Number of refresh cycles per period
+ * 64  Refresh cycle in ms per number of rows
+ */
+#define CFG_PTA_PER_CLK                ((2048 * 64 * 1000) / (4 * 64))
 #elif defined(CONFIG_FADS)                             /* Old/new FADS */
 #define        CFG_SDRAM_SIZE          0x00400000              /* 4 Mbyte */
 #else                                                  /* Old ADS */
@@ -223,9 +244,7 @@
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE     16      /* For all MPC8xx CPUs                  */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    4       /* log base 2 of the above value        */
-#endif
 
 /*-----------------------------------------------------------------------
  * I2C configuration
@@ -277,31 +296,21 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK      SCCR_EBDF11
-#define CFG_SCCR       (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+#define CFG_SCCR       SCCR_TBS
 
 /*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register         14-22
+ * DER - Debug Enable Register
  *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control
- */
-#ifndef CFG_PLPRCR
-#define CFG_PLPRCR     PLPRCR_TEXPS
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
+ * Set to zero to prevent the processor from entering debug mode
  */
 #define CFG_DER                 0
 
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently.  Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register.  For CS0, you must write the base register
-* first, followed by the option register.
-*/
+/* Because of the way the 860 starts up and assigns CS0 the entire
+ * address space, we have to set the memory controller differently.
+ * Normally, you write the option register first, and then enable the
+ * chip select by writing the base register.  For CS0, you must write
+ * the base register first, followed by the option register.
+ */
 
 /*
  * Init Memory Controller:
@@ -335,9 +344,6 @@
 
 /* values according to the manual */
 
-#define PCMCIA_MEM_ADDR                ((uint)0xFF020000)
-#define PCMCIA_MEM_SIZE                ((uint)(64 * 1024))
-
 #define        BCSR0                   ((uint) (BCSR_ADDR + 0x00))
 #define        BCSR1                   ((uint) (BCSR_ADDR + 0x04))
 #define        BCSR2                   ((uint) (BCSR_ADDR + 0x08))
@@ -396,59 +402,28 @@
 #define BCSR4_TFPLDL             ((uint)0x40000000)
 #define BCSR4_TPSQEL             ((uint)0x20000000)
 #define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
-#define BCSR4_FETH_EN            ((uint)0x08000000)
-#define BCSR4_FETHCFG0           ((uint)0x04000000)
-#define BCSR4_FETHFDE            ((uint)0x02000000)
-#define BCSR4_FETHCFG1           ((uint)0x00400000)
-#define BCSR4_FETHRST            ((uint)0x00200000)
-
-#ifdef CONFIG_MPC823
+#if defined(CONFIG_MPC823)
 #define BCSR4_USB_EN             ((uint)0x08000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860SAR
-#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
-#endif /* CONFIG_MPC860SAR */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETH_EN            ((uint)0x08000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
 #define BCSR4_USB_SPEED          ((uint)0x04000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHCFG0           ((uint)0x04000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
 #define BCSR4_VCCO               ((uint)0x02000000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHFDE            ((uint)0x02000000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
 #define BCSR4_VIDEO_ON           ((uint)0x00800000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC823
 #define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHCFG1           ((uint)0x00400000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
 #define BCSR4_VIDEO_RST          ((uint)0x00200000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETHRST            ((uint)0x00200000)
-#endif /* CONFIG_MPC860T */
-#ifdef CONFIG_MPC823
 #define BCSR4_MODEM_EN           ((uint)0x00100000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC823
 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
-#endif /* CONFIG_MPC823 */
-#ifdef CONFIG_MPC850
+#elif defined(CONFIG_MPC850)
 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
-#endif /* CONFIG_MPC850 */
+#elif defined(CONFIG_MPC860SAR)
+#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
+#else /* MPC860T and other chips with FEC */
+#define BCSR4_FETH_EN            ((uint)0x08000000)
+#define BCSR4_FETHCFG0           ((uint)0x04000000)
+#define BCSR4_FETHFDE            ((uint)0x02000000)
+#define BCSR4_FETHCFG1           ((uint)0x00400000)
+#define BCSR4_FETHRST            ((uint)0x00200000)
+#endif
 
-/* BSCR5 exists on MPC86xADS and Duet ADS only */
+/* BSCR5 exists on MPC86xADS and MPC885ADS only */
 
 #define CFG_PHYDEV_ADDR                (BCSR_ADDR + 0x20000)
 
@@ -511,4 +486,4 @@
 #define CFG_ATA_ALT_OFFSET     0x0000
 
 #define CONFIG_DISK_SPINUP_TIME 1000000
-#undef CONFIG_DISK_SPINUP_TIME /* usin´ Compact Flash */
+/* #undef CONFIG_DISK_SPINUP_TIME */   /* usin  Compact Flash */

diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c
index 3f7875334defc0b6a7ec69eb13ab241ad63e3f36..39b5c701e02c34f3ed12f0ac94961fa33570aa72 100644 (file)
--- a/board/g2000/g2000.c
+++ b/board/g2000/g2000.c
@@ -185,7 +185,7 @@ int testdram (void)
 
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 
 void nand_init(void)

diff --git a/board/gcplus/gcplus.c b/board/gcplus/gcplus.c
index 261e894f46f6e68c39dac61e7c11632ac1b6c698..829b5975976fd250e9379943880fb8b023fa8e7b 100644 (file)
--- a/board/gcplus/gcplus.c
+++ b/board/gcplus/gcplus.c
@@ -26,7 +26,8 @@
 
 #include <common.h>
 #include <SA-1100.h>
-/* ------------------------------------------------------------------------- */
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -35,8 +36,6 @@
 int
 board_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_arch_number = MACH_TYPE_GRAPHICSCLIENT;
 
        gd->bd->bi_boot_params = 0xc000003c; /* Weird address? */
@@ -62,8 +61,6 @@ board_init(void)
 int
 dram_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c
index 37788d5396a86af3b4ed1fd717ebca74bf35b906..2ba7e0e4207b92a8997b5b463fead7ff4f7fa62b 100644 (file)
--- a/board/gen860t/fpga.c
+++ b/board/gen860t/fpga.c
@@ -32,6 +32,8 @@
 #include <command.h>
 #include "fpga.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if (CONFIG_FPGA)
 
 #if 0
@@ -189,8 +191,6 @@ void fpga_selectmap_init (void)
  */
 int gen860t_init_fpga (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int i;
 
        PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);

diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c
index b7a1b56437aba5e19c6b13d71803c6962e5f0260..eb732210053ada257bf28b0cc97e75b0f2f80769 100644 (file)
--- a/board/gen860t/gen860t.c
+++ b/board/gen860t/gen860t.c
@@ -30,6 +30,8 @@
 #include "fpga.h"
 #include "ioport.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
 #endif
@@ -126,8 +128,6 @@ const uint selectmap_upm_table[] = {
  */
 int checkboard (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        char *s;
        char buf[64];
        int i;
@@ -305,5 +305,3 @@ int post_hotkeys_pressed (void)
        return 0;               /* No hotkeys supported */
 }
 #endif
-
-/* vim: set ts=4 sw=4 tw=78 : */

diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c
index e95d9ee3324d76c0773177617939f0b8a3a885a7..a523db1a487d92a94d6298ed5ac8d63b3f25dbe8 100644 (file)
--- a/board/hermes/hermes.c
+++ b/board/hermes/hermes.c
@@ -32,6 +32,8 @@
 # define SHOW_BOOT_PROGRESS(arg)
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 static long int dram_size (long int, long int *, long int);
@@ -105,8 +107,6 @@ const uint sdram_table[] = {
 
 int checkboard (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        char *s = getenv ("serial#");
        char *e;
 

diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c
index 0596fa4aadeb5d7fd80f45a15e139ba1bebd17c1..6868f260c2094699772505fa06cfda896d593c8d 100644 (file)
--- a/board/hymod/bsp.c
+++ b/board/hymod/bsp.c
@@ -28,6 +28,8 @@
 #include <net.h>
 #include <asm/iopin_8260.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*-----------------------------------------------------------------------
  * Board Special Commands: FPGA load/store, EEPROM erase
  */
@@ -75,8 +77,6 @@
 int
 fpga_load (int mezz, uchar *addr, ulong size)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
        xlx_info_t *fp;
        xlx_iopins_t *fpgaio;

diff --git a/board/hymod/env.c b/board/hymod/env.c
index f9e14213ceb91b4826d3df3ec5ffd2fb6fcb983f..062553bfad087504856c92e86abaab6f33037a3c 100644 (file)
--- a/board/hymod/env.c
+++ b/board/hymod/env.c
@@ -23,6 +23,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* imports from fetch.c */
 extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *));
 
@@ -32,8 +34,6 @@ static char *def_global_env_path = "/hymod/global_env";
 static int
 env_callback (uchar *name, uchar *value)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
        char ov[CFG_CBSIZE], nv[CFG_CBSIZE], *p, *q, *nn, c, *curver, *newver;
        int override = 1, append = 0, remove = 0, nnl, ovl, nvl;

diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c
index dea0a70a23a410aa68772a9226500080c64e5043..5e98e9edb7f171a0e0e7ff66181959e1296dbfea 100644 (file)
--- a/board/hymod/hymod.c
+++ b/board/hymod/hymod.c
@@ -30,6 +30,8 @@
 #include <i2c.h>
 #include <asm/iopin_8260.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 /* imports from eeprom.c */
@@ -424,8 +426,6 @@ initdram (int board_type)
 int
 last_stage_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
        int rc;
 

diff --git a/board/icecube/flash.c b/board/icecube/flash.c
index 713011c972aa22fb299a7aa3b3813198a55261f7..15e86d34f394446925b786a05ea8f10c43cd9288 100644 (file)
--- a/board/icecube/flash.c
+++ b/board/icecube/flash.c
@@ -23,6 +23,7 @@
 
 #include <common.h>
 
+#ifndef CFG_FLASH_CFI_DRIVER
 flash_info_t   flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips        */
 
 /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
@@ -489,3 +490,4 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
 
        return (res);
 }
+#endif /*CFG_FLASH_CFI_DRIVER*/

diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index 1f1a74ce33978a52451fc5a73b3bae87d9ab639d..4f056b2fa44e4d985c1a70bfe589bab7c522c9b0 100644 (file)
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -27,13 +27,17 @@
 #include <common.h>
 #include <mpc5xxx.h>
 #include <pci.h>
+#include <asm/processor.h>
 
-#if defined(CONFIG_MPC5200_DDR)
-#include "mt46v16m16-75.h"
+#if defined(CONFIG_LITE5200B)
+#include "mt46v32m16.h"
 #else
+# if defined(CONFIG_MPC5200_DDR)
+#  include "mt46v16m16-75.h"
+# else
 #include "mt48lc16m16a2-75.h"
+# endif
 #endif
-
 #ifndef CFG_RAMBOOT
 static void sdram_start (int hi_addr)
 {
@@ -86,6 +90,8 @@ long int initdram (int board_type)
 {
        ulong dramsize = 0;
        ulong dramsize2 = 0;
+       uint svr, pvr;
+
 #ifndef CFG_RAMBOOT
        ulong test1, test2;
 
@@ -180,6 +186,24 @@ long int initdram (int board_type)
 
 #endif /* CFG_RAMBOOT */
 
+       /*
+        * On MPC5200B we need to set the special configuration delay in the
+        * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+        * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+        *
+        * "The SDelay should be written to a value of 0x00000004. It is
+        * required to account for changes caused by normal wafer processing
+        * parameters."
+        */
+       svr = get_svr();
+       pvr = get_pvr();
+       if ((SVR_MJREV(svr) >= 2) &&
+           (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+               *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+               __asm__ volatile ("sync");
+       }
+
        return dramsize + dramsize2;
 }
 
@@ -236,7 +260,9 @@ long int initdram (int board_type)
 
 int checkboard (void)
 {
-#if defined(CONFIG_MPC5200)
+#if defined (CONFIG_LITE5200B)
+       puts ("Board: Freescale Lite5200B\n");
+#elif defined(CONFIG_MPC5200)
        puts ("Board: Motorola MPC5200 (IceCube)\n");
 #elif defined(CONFIG_MGT5100)
        puts ("Board: Motorola MGT5100 (IceCube)\n");

diff --git a/board/icecube/mt46v32m16.h b/board/icecube/mt46v32m16.h
new file mode 100644 (file)
index 0000000..de2b48b
--- /dev/null
+++ b/board/icecube/mt46v32m16.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR      1               /* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE     0x018D0000
+#define SDRAM_EMODE    0x40090000
+#define SDRAM_CONTROL  0x704f0f00
+#define SDRAM_CONFIG1  0x73722930
+#define SDRAM_CONFIG2  0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif

diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c
index 081ef658e0d92322ec8d359e031b21cc1cba587e..7b9a83d0f954b195830391a02977ee2d3f78cecd 100644 (file)
--- a/board/ids8247/ids8247.c
+++ b/board/ids8247/ids8247.c
@@ -25,6 +25,8 @@
 #include <ioports.h>
 #include <mpc8260.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * I/O Port configuration table
  *
@@ -295,8 +297,6 @@ long int initdram (int board_type)
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_flashstart = 0xff800000;
 }
 

diff --git a/board/impa7/impa7.c b/board/impa7/impa7.c
index e49692328246eb6050920b16d17325fa82e19dda..3230dd48f0767622b1d295cb5c42227befdbc303 100644 (file)
--- a/board/impa7/impa7.c
+++ b/board/impa7/impa7.c
@@ -25,6 +25,8 @@
 #include <common.h>
 #include <clps7111.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 
@@ -34,8 +36,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Activate LED flasher */
        IO_LEDFLSH = 0x40;
 
@@ -50,8 +50,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c
index ae5402e8431c9698a0fad0d1250aa1b830ff459a..7f8f47c3a2ef7338acf9d60fc70a50d9bf61523a 100644 (file)
--- a/board/innokom/innokom.c
+++ b/board/innokom/innokom.c
@@ -27,6 +27,8 @@
 #include <asm/arch/pxa-regs.h>
 #include <asm/mach-types.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 # define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
 #else
@@ -95,8 +97,6 @@ int misc_init_r(void)
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* memory and cpu-speed are setup before relocation */
        /* so we do _nothing_ here */
 
@@ -116,8 +116,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/integratorap/integratorap.c b/board/integratorap/integratorap.c
index d4f61d6403d530f7139196c6ee523d367f5cb79d..e659907567ba748bab17e0b18ccb601dd0e6e295 100644 (file)
--- a/board/integratorap/integratorap.c
+++ b/board/integratorap/integratorap.c
@@ -39,6 +39,8 @@
 #include <pci.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void flash__init (void);
 void ether__init (void);
 void peripheral_power_enable (void);
@@ -65,8 +67,6 @@ static inline void delay (unsigned long loops)
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* arch number of Integrator Board */
        gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
 
@@ -480,8 +480,6 @@ void ether__init (void)
 ******************************/
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/integratorcp/integratorcp.c b/board/integratorcp/integratorcp.c
index 216876b469db2bc18dad073f52dd0f160279b182..d6d6e13d5a475f20290bb86277affe17365522b8 100644 (file)
--- a/board/integratorcp/integratorcp.c
+++ b/board/integratorcp/integratorcp.c
@@ -35,6 +35,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void flash__init (void);
 void ether__init (void);
 void peripheral_power_enable (void);
@@ -54,8 +56,6 @@ void show_boot_progress(int progress)
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* arch number of Integrator Board */
        gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
 
@@ -105,8 +105,6 @@ void ether__init (void)
 ******************************/
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/ixdp425/ixdp425.c b/board/ixdp425/ixdp425.c
index c04626a34650ac64ca91b9576a9d5881aede3e9d..aa965914507ae59e9c79eede6152089c02a710f7 100644 (file)
--- a/board/ixdp425/ixdp425.c
+++ b/board/ixdp425/ixdp425.c
@@ -28,11 +28,7 @@
 #include <asm/arch/ixp425.h>
 #include <common.h>
 
-/* ------------------------------------------------------------------------- */
-
-
-/* local prototypes */
-
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -49,8 +45,6 @@ int board_post_init (void)
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* arch number of IXDP */
        gd->bd->bi_arch_number = MACH_TYPE_IXDP425;
 
@@ -64,8 +58,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/kb9202/kb9202.c b/board/kb9202/kb9202.c
index 4a7cf77ba5212389e340017ec4a8d21a20221edb..ec51dca914901c1a0bc8e2bde92f61be66d44a0a 100644 (file)
--- a/board/kb9202/kb9202.c
+++ b/board/kb9202/kb9202.c
@@ -31,7 +31,8 @@
 #include <at91rm9200_net.h>
 #include <lxt971a.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Miscelaneous platform dependent initialisations
  */
@@ -42,8 +43,6 @@ void lowlevel_init(void) {
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Enable Ctrlc */
        console_init_f ();
 
@@ -60,8 +59,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
        return 0;

diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c
index e621c436ffd25837d4cd8332a7ea5c597cd13d22..4e377a142bb5dadb795f87a6db068ecee288499f 100644 (file)
--- a/board/kup/kup4k/kup4k.c
+++ b/board/kup/kup4k/kup4k.c
@@ -29,6 +29,8 @@
    #include "s1d13706.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef DEBUG
 #ifdef  DEBUG
 # define debugk(fmt,args...)    printf(fmt ,##args)
@@ -44,10 +46,6 @@ typedef struct {
 
 /* ------------------------------------------------------------------------- */
 
-#if 0
-static long int dram_size (long int, long int *, long int);
-#endif
-
 #ifdef CONFIG_KUP4K_LOGO
 void lcd_logo(bd_t *bd);
 #endif
@@ -235,62 +233,8 @@ long int initdram (int board_type)
 
 /* ------------------------------------------------------------------------- */
 
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-#if 0
-static long int dram_size (long int mamr_value, long int *base,
-                                                  long int maxsize)
-{
-       volatile immap_t *immap = (immap_t *) CFG_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-       volatile long int *addr;
-       ulong cnt, val;
-       ulong save[32];                         /* to make test non-destructive */
-       unsigned char i = 0;
-
-       memctl->memc_mamr = mamr_value;
-
-       for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
-               addr = base + cnt;              /* pointer arith! */
-
-               save[i++] = *addr;
-               *addr = ~cnt;
-       }
-
-       /* write 0 to base address */
-       addr = base;
-       save[i] = *addr;
-       *addr = 0;
-
-       /* check at base address */
-       if ((val = *addr) != 0) {
-               *addr = save[i];
-               return (0);
-       }
-
-       for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
-               addr = base + cnt;              /* pointer arith! */
-
-               val = *addr;
-               *addr = save[--i];
-
-               if (val != (~cnt)) {
-                       return (cnt * sizeof (long));
-               }
-       }
-       return (maxsize);
-}
-#endif
-
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
 #ifdef CONFIG_STATUS_LED
        volatile immap_t *immap = (immap_t *) CFG_IMMR;
 #endif

diff --git a/board/lart/flash.c b/board/lart/flash.c
index 5232ed258614153ffd750a410d325f7df627bbb9..28c4531c0232f3818ed3baa7a3732731e0c26091 100644 (file)
--- a/board/lart/flash.c
+++ b/board/lart/flash.c
@@ -348,7 +348,7 @@ outahere:
  * Copy memory to flash
  */
 
-volatile static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word (flash_info_t *info, ulong dest, ulong data)
 {
     vu_long *addr = (vu_long *)dest;
     ulong result;

diff --git a/board/lart/lart.c b/board/lart/lart.c
index 66b730dba7fe68a46f136ed3d04899d5932da050..8d534c8e6738fd8af533c69b3522b9e42cd4049a 100644 (file)
--- a/board/lart/lart.c
+++ b/board/lart/lart.c
@@ -24,6 +24,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 
@@ -33,8 +35,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* memory and cpu-speed are setup before relocation */
        /* so we do _nothing_ here */
 
@@ -49,7 +49,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        bd_t *bd = gd->bd;
 
        bd->bi_dram[0].start = PHYS_SDRAM_1;

diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c
index 95634ac0044cd00434b10a90598cfb86589458d0..14fd28f56fc37ab4d4ad604f56fe7456c365d0ff 100644 (file)
--- a/board/logodl/logodl.c
+++ b/board/logodl/logodl.c
@@ -25,6 +25,8 @@
 #include <common.h>
 #include <asm/arch/pxa-regs.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /**
  * board_init: - setup some data structures
  *
@@ -33,8 +35,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* memory and cpu-speed are setup before relocation */
        /* so we do _nothing_ here */
 
@@ -57,8 +57,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c
index 2dfe37656fc1c112041488f6def5cc3a699ff9ed..d18720e5b20d2a6c6b81f57b54cbee41e2dd4dd4 100644 (file)
--- a/board/lpd7a40x/flash.c
+++ b/board/lpd7a40x/flash.c
@@ -351,8 +351,7 @@ outahere:
  * Copy memory to flash
  */
 
-volatile static int write_word (flash_info_t * info, ulong dest,
-                                                               ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
        vu_long *addr = (vu_long *) dest;
        ulong result;

diff --git a/board/lpd7a40x/lpd7a40x.c b/board/lpd7a40x/lpd7a40x.c
index 4c373eead51a987e40c81d7166d72b7f002bede9..e12bbf04fb2f508a86bd05e814652803aa60e176 100644 (file)
--- a/board/lpd7a40x/lpd7a40x.c
+++ b/board/lpd7a40x/lpd7a40x.c
@@ -37,14 +37,14 @@
 
 #include <lpd7a400_cpld.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Miscellaneous platform dependent initialisations
  */
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* set up the I/O ports */
 
        /* enable flash programming */
@@ -74,8 +74,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c
index e618ab96a1d4cc24d244c803c586126060e909bc..58291706c0d91b044cdaaee362f92a7a206e035e 100644 (file)
--- a/board/lubbock/lubbock.c
+++ b/board/lubbock/lubbock.c
@@ -27,8 +27,7 @@
 
 #include <common.h>
 
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -36,8 +35,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* memory and cpu-speed are setup before relocation */
        /* so we do _nothing_ here */
 
@@ -60,8 +57,6 @@ int board_late_init(void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c
index a174b57b70edf09f81a1c3d710f6f3a607a8387d..9e8ea2db194b91260188638b825bd927e07a0e6e 100644 (file)
--- a/board/lwmon/lwmon.c
+++ b/board/lwmon/lwmon.c
@@ -45,6 +45,8 @@ V* Verification:  dzu@denx.de
 #include <linux/types.h>
 #include <linux/string.h>      /* for strdup */
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*------------------------ Local prototypes ---------------------------*/
 static long int dram_size (long int, long int *, long int);
 static void kbd_init (void);
@@ -455,8 +457,6 @@ Z*               for the lwmon board.
  ***********************************************************************/
 int board_postclk_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        kbd_init();
 
 #ifdef CONFIG_MODEM_SUPPORT
@@ -471,15 +471,11 @@ int board_postclk_init (void)
 
 struct serial_device * default_serial_console (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        return gd->do_mdm_init ? &serial_scc_device : &serial_smc_device;
 }
 
 static void kbd_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        uchar kbd_data[KEYBD_DATALEN];
        uchar tmp_data[KEYBD_DATALEN];
        uchar val, errcd;
@@ -571,8 +567,6 @@ V* Verification: dzu@denx.de
  ***********************************************************************/
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        uchar kbd_data[KEYBD_DATALEN];
        char keybd_env[2 * KEYBD_DATALEN + 1];
        uchar kbd_init_status = gd->kbd_status >> 8;

diff --git a/board/m5272c3/flash.c b/board/m5272c3/flash.c
index fb918435c81a4f305d770b0ea606ecbb1792a05b..f156342291a832490ac59639a4d0aec5a3b68569 100644 (file)
--- a/board/m5272c3/flash.c
+++ b/board/m5272c3/flash.c
@@ -256,8 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
        return rc;
 }
 
-
-volatile static int write_word (flash_info_t * info, ulong dest, ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
        volatile u16 *addr = (volatile u16 *) dest;
        ulong result;

diff --git a/board/m5282evb/flash.c b/board/m5282evb/flash.c
index ff70783bda167ab153040fb6fa42fbe19619f108..95f35ad84f9b71a3fac76439e718785ca6b5a6c6 100644 (file)
--- a/board/m5282evb/flash.c
+++ b/board/m5282evb/flash.c
@@ -256,8 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
        return rc;
 }
 
-
-volatile static int write_word (flash_info_t * info, ulong dest, ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
        volatile u16 *addr = (volatile u16 *) dest;
        ulong result;

diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile
new file mode 100644 (file)
index 0000000..7fdc088
--- /dev/null
+++ b/board/mcc200/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   := $(BOARD).o
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

diff --git a/board/mcc200/config.mk b/board/mcc200/config.mk
new file mode 100644 (file)
index 0000000..fa55673
--- /dev/null
+++ b/board/mcc200/config.mk
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MCC200 board:
+#
+#      Valid values for TEXT_BASE are:
+#
+#      0xFFF00000   boot high (standard configuration)
+#      0xFE000000   boot low
+#      0x00100000   boot from RAM (for testing only)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
new file mode 100644 (file)
index 0000000..5fe239f
--- /dev/null
+++ b/board/mcc200/mcc200.c
@@ -0,0 +1,286 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#include "mt48lc8m32b2-6-7.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[];      /* FLASH chips info */
+
+ulong flash_get_size (ulong base, int banknum);
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+       long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+       /* unlock mode register */
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+       __asm__ volatile ("sync");
+
+       /* precharge all banks */
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+       __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+       /* set mode register: extended mode */
+       *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+       __asm__ volatile ("sync");
+
+       /* set mode register: reset DLL */
+       *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+       __asm__ volatile ("sync");
+#endif
+
+       /* precharge all banks */
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+       __asm__ volatile ("sync");
+
+       /* auto refresh */
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+       __asm__ volatile ("sync");
+
+       /* set mode register */
+       *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+       __asm__ volatile ("sync");
+
+       /* normal operation */
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+       __asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+long int initdram (int board_type)
+{
+       ulong dramsize = 0;
+       ulong dramsize2 = 0;
+#ifndef CFG_RAMBOOT
+       ulong test1, test2;
+
+       /* setup SDRAM chip selects */
+       *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+       *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+       __asm__ volatile ("sync");
+
+       /* setup config registers */
+       *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+       *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+       __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+       /* set tap delay */
+       *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+       __asm__ volatile ("sync");
+#endif
+
+       /* find RAM size using SDRAM CS0 only */
+       sdram_start(0);
+       test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+       sdram_start(1);
+       test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+       if (test1 > test2) {
+               sdram_start(0);
+               dramsize = test1;
+       } else {
+               dramsize = test2;
+       }
+
+       /* memory smaller than 1MB is impossible */
+       if (dramsize < (1 << 20)) {
+               dramsize = 0;
+       }
+
+       /* set SDRAM CS0 size according to the amount of RAM found */
+       if (dramsize > 0) {
+               *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+       } else {
+               *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+       }
+
+       /* let SDRAM CS1 start right after CS0 */
+       *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+       /* find RAM size using SDRAM CS1 only */
+       if (!dramsize)
+               sdram_start(0);
+       test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+       if (!dramsize) {
+               sdram_start(1);
+               test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+       }
+       if (test1 > test2) {
+               sdram_start(0);
+               dramsize2 = test1;
+       } else {
+               dramsize2 = test2;
+       }
+
+       /* memory smaller than 1MB is impossible */
+       if (dramsize2 < (1 << 20)) {
+               dramsize2 = 0;
+       }
+
+       /* set SDRAM CS1 size according to the amount of RAM found */
+       if (dramsize2 > 0) {
+               *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+                       | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+       } else {
+               *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+       }
+
+#else /* CFG_RAMBOOT */
+
+       /* retrieve size of memory connected to SDRAM CS0 */
+       dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+       if (dramsize >= 0x13) {
+               dramsize = (1 << (dramsize - 0x13)) << 20;
+       } else {
+               dramsize = 0;
+       }
+
+       /* retrieve size of memory connected to SDRAM CS1 */
+       dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+       if (dramsize2 >= 0x13) {
+               dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+       } else {
+               dramsize2 = 0;
+       }
+
+#endif /* CFG_RAMBOOT */
+
+       return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+       puts ("Board: MCC200\n");
+       return 0;
+}
+
+int misc_init_r (void)
+{
+       /*
+        * Adjust flash start and offset to detected values
+        */
+       gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+       gd->bd->bi_flashoffset = 0;
+
+       /*
+        * Check if boot FLASH isn't max size
+        */
+       if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) {
+               /* adjust mapping */
+               *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+                       START_REG(gd->bd->bi_flashstart);
+               *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+                       STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
+
+               /*
+                * Re-check to get correct base address
+                */
+               flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
+
+               /*
+                * Re-do flash protection upon new addresses
+                */
+               flash_protect (FLAG_PROTECT_CLEAR,
+                              gd->bd->bi_flashstart, 0xffffffff,
+                              &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+               /* Monitor protection ON by default */
+               flash_protect (FLAG_PROTECT_SET,
+                              CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
+                              &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+               /* Environment protection ON by default */
+               flash_protect (FLAG_PROTECT_SET,
+                              CFG_ENV_ADDR,
+                              CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+                              &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+               /* Redundant environment protection ON by default */
+               flash_protect (FLAG_PROTECT_SET,
+                              CFG_ENV_ADDR_REDUND,
+                              CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+                              &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+       }
+
+       if (gd->bd->bi_flashsize > (32 << 20)) {
+               /* Unprotect the upper bank of the Flash */
+               *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
+               flash_protect (FLAG_PROTECT_CLEAR,
+                              flash_info[0].start[0],
+                              (flash_info[0].start[0] + flash_info[0].size) / 2 - 1,
+                              &flash_info[0]);
+               *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
+       }
+
+       return (0);
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+       pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+       debug ("init_ide_reset\n");
+
+}
+
+void ide_set_reset (int idereset)
+{
+       debug ("ide_reset(%d)\n", idereset);
+
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe (ulong physadr);
+void doc_init (void)
+{
+       doc_probe (CFG_DOC_BASE);
+}
+#endif

diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h
new file mode 100644 (file)
index 0000000..f650faa
--- /dev/null
+++ b/board/mcc200/mt46v16m16-75.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR      1               /* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE     0x018D0000
+#define SDRAM_EMODE    0x40090000
+#define SDRAM_CONTROL  0x714f0f00
+#define SDRAM_CONFIG1  0x73722930
+#define SDRAM_CONFIG2  0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif

diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h
new file mode 100644 (file)
index 0000000..ffdf039
--- /dev/null
+++ b/board/mcc200/mt48lc16m16a2-75.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR      0               /* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE     0x00CD0000
+#define SDRAM_CONTROL  0x504F0000
+#define SDRAM_CONFIG1  0xD2322800
+#define SDRAM_CONFIG2  0x8AD70000
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE     0x008D0000
+#define SDRAM_CONTROL  0x504F0000
+#define SDRAM_CONFIG1  0xC2222600
+#define SDRAM_CONFIG2  0x88B70004
+#define SDRAM_ADDRSEL  0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif

diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h
new file mode 100644 (file)
index 0000000..13aebbd
--- /dev/null
+++ b/board/mcc200/mt48lc8m32b2-6-7.h
@@ -0,0 +1,12 @@
+/*
+ * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform
+ */
+
+#define SDRAM_DDR      0               /* is SDR */
+
+/* Settings for XLB = 132 MHz */
+
+#define SDRAM_MODE     0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */
+#define SDRAM_CONTROL  0x504f0000 /* Control Register MBAR + 0x0104 */
+#define SDRAM_CONFIG1  0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */
+#define SDRAM_CONFIG2  0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */

diff --git a/board/mcc200/u-boot.lds b/board/mcc200/u-boot.lds
new file mode 100644 (file)
index 0000000..4fdea6b
--- /dev/null
+++ b/board/mcc200/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)              }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)              }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)               }
+  .rela.got      : { *(.rela.got)              }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)               }
+  .rela.bss      : { *(.rela.bss)              }
+  .rel.plt       : { *(.rel.plt)               }
+  .rela.plt      : { *(.rela.plt)              }
+  .init          : { *(.init)  }
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o        (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

diff --git a/board/ml2/serial.c b/board/ml2/serial.c
index 92baba927598a914ba308d9e45eccab1979bd31e..74687f12c63ba69c20ebcf42d2384dc1aa2ac058 100644 (file)
--- a/board/ml2/serial.c
+++ b/board/ml2/serial.c
@@ -29,70 +29,59 @@
 #include <ns16550.h>
 #endif
 
-#if 0
-#include "serial.h"
-#endif
+DECLARE_GLOBAL_DATA_PTR;
 
 #if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
 const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1,
-                               (NS16550_t) CFG_NS16550_COM2 };
+       (NS16550_t) CFG_NS16550_COM2
+};
 #endif
 
-int
-serial_init (void)
+int serial_init (void)
 {
-               DECLARE_GLOBAL_DATA_PTR;
-
-           int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+       int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
 
 #ifdef CFG_INIT_CHAN1
-           (void)NS16550_init(COM_PORTS[0], clock_divisor);
+       (void) NS16550_init (COM_PORTS[0], clock_divisor);
 #endif
 #ifdef CFG_INIT_CHAN2
-           (void)NS16550_init(COM_PORTS[1], clock_divisor);
+       (void) NS16550_init (COM_PORTS[1], clock_divisor);
 #endif
-               return 0;
+       return 0;
 
 }
 
-void
-serial_putc(const char c)
+void serial_putc (const char c)
 {
-    if (c == '\n')
-       NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r');
+       if (c == '\n')
+               NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
 
-    NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c);
+       NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
 }
 
-int
-serial_getc(void)
+int serial_getc (void)
 {
-    return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]);
+       return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
 }
 
-int
-serial_tstc(void)
+int serial_tstc (void)
 {
-    return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]);
+       return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
 }
 
-void
-serial_setbrg (void)
+void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
-    int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+       int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
 
 #ifdef CFG_INIT_CHAN1
-    NS16550_reinit(COM_PORTS[0], clock_divisor);
+       NS16550_reinit (COM_PORTS[0], clock_divisor);
 #endif
 #ifdef CFG_INIT_CHAN2
-    NS16550_reinit(COM_PORTS[1], clock_divisor);
+       NS16550_reinit (COM_PORTS[1], clock_divisor);
 #endif
 }
 
-void
-serial_puts (const char *s)
+void serial_puts (const char *s)
 {
        while (*s) {
                serial_putc (*s++);
@@ -100,32 +89,27 @@ serial_puts (const char *s)
 }
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-void
-kgdb_serial_init(void)
+void kgdb_serial_init (void)
 {
 }
 
-void
-putDebugChar (int c)
+void putDebugChar (int c)
 {
        serial_putc (c);
 }
 
-void
-putDebugStr (const char *str)
+void putDebugStr (const char *str)
 {
        serial_puts (str);
 }
 
-int
-getDebugChar (void)
+int getDebugChar (void)
 {
-       return serial_getc();
+       return serial_getc ();
 }
 
-void
-kgdb_interruptible (int yes)
+void kgdb_interruptible (int yes)
 {
        return;
 }
-#endif /* CFG_CMD_KGDB */
+#endif /* CFG_CMD_KGDB */

diff --git a/board/modnet50/modnet50.c b/board/modnet50/modnet50.c
index 448c6233e9cf9338e27fc915b3cae72d4ff899e4..4544069c2ff4030ed1c25bdd9672ee6333884103 100644 (file)
--- a/board/modnet50/modnet50.c
+++ b/board/modnet50/modnet50.c
@@ -24,8 +24,7 @@
 
 #include <common.h>
 
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -33,7 +32,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        /* address for the kernel command line */
        gd->bd->bi_boot_params = 0x800;
        return 0;
@@ -41,7 +39,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
        if (CONFIG_NR_DRAM_BANKS == 2) {

diff --git a/board/mp2usb/mp2usb.c b/board/mp2usb/mp2usb.c
index e75be1e3aa86fd3b9c80a9d3a8c097600d2df5e7..486d44c202f1523f97ac0ec88625ad4ef943a8ae 100644 (file)
--- a/board/mp2usb/mp2usb.c
+++ b/board/mp2usb/mp2usb.c
@@ -31,15 +31,14 @@
 #include <dm9161.h>
 #include <asm/mach-types.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Miscelaneous platform dependent initialisations
  */
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Enable Ctrlc */
        console_init_f ();
 
@@ -56,8 +55,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
        return 0;

diff --git a/board/mpc8349ads/Makefile b/board/mpc8349ads/Makefile
index 4327b0d3ef3f89c1972e149e2f6a6227ea17f6f8..f865f9c83bd785513c65e1b150b84b564f09f508 100644 (file)
--- a/board/mpc8349ads/Makefile
+++ b/board/mpc8349ads/Makefile
@@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = lib$(BOARD).a
 
-OBJS   := $(BOARD).o
+OBJS   := $(BOARD).o pci.o
 
 $(LIB):        $(OBJS) $(SOBJS)
        $(AR) crv $@ $(OBJS)

diff --git a/board/mpc8349ads/mpc8349ads.c b/board/mpc8349ads/mpc8349ads.c
index da8d3d7e81384691da1c7f086bc57211d39bfed7..9841298d6e6ebd6c48b3d1f7e870851854584d4b 100644 (file)
--- a/board/mpc8349ads/mpc8349ads.c
+++ b/board/mpc8349ads/mpc8349ads.c
@@ -64,7 +64,7 @@ long int initdram (int board_type)
        /* DDR SDRAM - Main SODIMM */
        im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
 #if defined(CONFIG_SPD_EEPROM)
-       msize = spd_sdram(NULL);
+       msize = spd_sdram();
 #else
        msize = fixed_sdram();
 #endif
@@ -147,47 +147,6 @@ int checkboard (void)
        return 0;
 }
 
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc83xxads_config_table[] = {
-       {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
-       pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
-                                   PCI_ENET0_MEMADDR,
-                                   PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
-       } },
-       {}
-}
-#endif
-
-
-volatile static struct pci_controller hose[] = {
-       {
-#ifndef CONFIG_PCI_PNP
-       config_table:pci_mpc83xxads_config_table,
-#endif
-       },
-       {
-#ifndef CONFIG_PCI_PNP
-       config_table:pci_mpc83xxads_config_table,
-#endif
-       }
-};
-#endif /* CONFIG_PCI */
-
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
-       extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
-
-       pci_mpc83xx_init(hose);
-#endif /* CONFIG_PCI */
-}
-
 /*
  * if MPC8349ADS is soldered with SDRAM
  */

diff --git a/board/mpc8349ads/pci.c b/board/mpc8349ads/pci.c
new file mode 100644 (file)
index 0000000..319e35c
--- /dev/null
+++ b/board/mpc8349ads/pci.c
@@ -0,0 +1,381 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/mmu.h>
+#include <common.h>
+#include <asm/global_data.h>
+#include <pci.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_PCI
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS        CFG_SDRAM_BASE
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc83xxads_config_table[] = {
+       {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+        PCI_IDSEL_NUMBER, PCI_ANY_ID,
+        pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+                                    PCI_ENET0_MEMADDR,
+                                    PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+               }
+       },
+       {}
+};
+#endif
+
+static struct pci_controller pci_hose[] = {
+       {
+#ifndef CONFIG_PCI_PNP
+       config_table:pci_mpc83xxads_config_table,
+#endif
+       },
+       {
+#ifndef CONFIG_PCI_PNP
+       config_table:pci_mpc83xxads_config_table,
+#endif
+       }
+};
+
+/**************************************************************************
+ *
+ * pib_init() -- initialize the PCA9555PW IO expander on the PIB board
+ *
+ */
+void
+pib_init(void)
+{
+       u8 val8;
+       /*
+        * Assign PIB PMC slot to desired PCI bus
+        */
+       mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
+       i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+       val8 = 0;
+       i2c_write(0x23, 0x6, 1, &val8, 1);
+       i2c_write(0x23, 0x7, 1, &val8, 1);
+       val8 = 0xff;
+       i2c_write(0x23, 0x2, 1, &val8, 1);
+       i2c_write(0x23, 0x3, 1, &val8, 1);
+
+       val8 = 0;
+       i2c_write(0x26, 0x6, 1, &val8, 1);
+       val8 = 0x34;
+       i2c_write(0x26, 0x7, 1, &val8, 1);
+#if defined(PCI_64BIT)
+       val8 = 0xf4;    /* PMC2:PCI1/64-bit */
+#elif defined(PCI_ALL_PCI1)
+       val8 = 0xf3;    /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
+#elif defined(PCI_ONE_PCI1)
+       val8 = 0xf9;    /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
+#else
+       val8 = 0xf5;    /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
+#endif
+       i2c_write(0x26, 0x2, 1, &val8, 1);
+       val8 = 0xff;
+       i2c_write(0x26, 0x3, 1, &val8, 1);
+       val8 = 0;
+       i2c_write(0x27, 0x6, 1, &val8, 1);
+       i2c_write(0x27, 0x7, 1, &val8, 1);
+       val8 = 0xff;
+       i2c_write(0x27, 0x2, 1, &val8, 1);
+       val8 = 0xef;
+       i2c_write(0x27, 0x3, 1, &val8, 1);
+       asm("eieio");
+
+#if defined(PCI_64BIT)
+       printf("PCI1: 64-bit on PMC2\n");
+#elif defined(PCI_ALL_PCI1)
+       printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
+#elif defined(PCI_ONE_PCI1)
+       printf("PCI1: 32-bit on PMC1\n");
+       printf("PCI2: 32-bit on PMC2, PMC3\n");
+#else
+       printf("PCI1: 32-bit on PMC1, PMC2\n");
+       printf("PCI2: 32-bit on PMC3\n");
+#endif
+}
+
+/**************************************************************************
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not currently supported
+ *
+ */
+void
+pci_init_board(void)
+{
+       volatile immap_t *      immr;
+       volatile clk8349_t *    clk;
+       volatile law8349_t *    pci_law;
+       volatile pot8349_t *    pci_pot;
+       volatile pcictrl8349_t *        pci_ctrl;
+       volatile pciconf8349_t *        pci_conf;
+       u16 reg16;
+       u32 reg32;
+       u32 dev;
+       struct  pci_controller * hose;
+
+       immr = (immap_t *)CFG_IMMRBAR;
+       clk = (clk8349_t *)&immr->clk;
+       pci_law = immr->sysconf.pcilaw;
+       pci_pot = immr->ios.pot;
+       pci_ctrl = immr->pci_ctrl;
+       pci_conf = immr->pci_conf;
+
+       hose = &pci_hose[0];
+
+       pib_init();
+
+       /*
+        * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
+        */
+
+       reg32 = clk->occr;
+       udelay(2000);
+       clk->occr = 0xff000000;
+       udelay(2000);
+
+       /*
+        * Release PCI RST Output signal
+        */
+       pci_ctrl[0].gcr = 0;
+       udelay(2000);
+       pci_ctrl[0].gcr = 1;
+
+#ifdef CONFIG_MPC83XX_PCI2
+       pci_ctrl[1].gcr = 0;
+       udelay(2000);
+       pci_ctrl[1].gcr = 1;
+#endif
+
+       /* We need to wait at least a 1sec based on PCI specs */
+       {
+               int i;
+
+               for (i = 0; i < 1000; ++i)
+                       udelay (1000);
+       }
+
+       /*
+        * Configure PCI Local Access Windows
+        */
+       pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+       pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+       pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+       pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
+
+       /*
+        * Configure PCI Outbound Translation Windows
+        */
+
+       /* PCI1 mem space - prefetch */
+       pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
+       pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
+       pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+       /* PCI1 IO space */
+       pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
+       pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
+       pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
+
+       /* PCI1 mmio - non-prefetch mem space */
+       pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
+       pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+       pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+       /*
+        * Configure PCI Inbound Translation Windows
+        */
+
+       /* we need RAM mapped to PCI space for the devices to
+        * access main memory */
+       pci_ctrl[0].pitar1 = 0x0;
+       pci_ctrl[0].pibar1 = 0x0;
+       pci_ctrl[0].piebar1 = 0x0;
+       pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+       hose->first_busno = 0;
+       hose->last_busno = 0xff;
+
+       /* PCI memory prefetch space */
+       pci_set_region(hose->regions + 0,
+                      CFG_PCI1_MEM_BASE,
+                      CFG_PCI1_MEM_PHYS,
+                      CFG_PCI1_MEM_SIZE,
+                      PCI_REGION_MEM|PCI_REGION_PREFETCH);
+
+       /* PCI memory space */
+       pci_set_region(hose->regions + 1,
+                      CFG_PCI1_MMIO_BASE,
+                      CFG_PCI1_MMIO_PHYS,
+                      CFG_PCI1_MMIO_SIZE,
+                      PCI_REGION_MEM);
+
+       /* PCI IO space */
+       pci_set_region(hose->regions + 2,
+                      CFG_PCI1_IO_BASE,
+                      CFG_PCI1_IO_PHYS,
+                      CFG_PCI1_IO_SIZE,
+                      PCI_REGION_IO);
+
+       /* System memory space */
+       pci_set_region(hose->regions + 3,
+                      CONFIG_PCI_SYS_MEM_BUS,
+                      CONFIG_PCI_SYS_MEM_PHYS,
+                      gd->ram_size,
+                      PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+       hose->region_count = 4;
+
+       pci_setup_indirect(hose,
+                          (CFG_IMMRBAR+0x8300),
+                          (CFG_IMMRBAR+0x8304));
+
+       pci_register_hose(hose);
+
+       /*
+        * Write to Command register
+        */
+       reg16 = 0xff;
+       dev = PCI_BDF(hose->first_busno, 0, 0);
+       pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
+       reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+       pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+       /*
+        * Clear non-reserved bits in status register.
+        */
+       pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+       pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+       pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+       printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+       /*
+        * Hose scan.
+        */
+       hose->last_busno = pci_hose_scan(hose);
+
+#ifdef CONFIG_MPC83XX_PCI2
+       hose = &pci_hose[1];
+
+       /*
+        * Configure PCI Outbound Translation Windows
+        */
+
+       /* PCI2 mem space - prefetch */
+       pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
+       pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
+       pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+       /* PCI2 IO space */
+       pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
+       pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
+       pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
+
+       /* PCI2 mmio - non-prefetch mem space */
+       pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
+       pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+       pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
+
+       /*
+        * Configure PCI Inbound Translation Windows
+        */
+
+       /* we need RAM mapped to PCI space for the devices to
+        * access main memory */
+       pci_ctrl[1].pitar1 = 0x0;
+       pci_ctrl[1].pibar1 = 0x0;
+       pci_ctrl[1].piebar1 = 0x0;
+       pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+       hose->first_busno = pci_hose[0].last_busno + 1;
+       hose->last_busno = 0xff;
+
+       /* PCI memory prefetch space */
+       pci_set_region(hose->regions + 0,
+                      CFG_PCI2_MEM_BASE,
+                      CFG_PCI2_MEM_PHYS,
+                      CFG_PCI2_MEM_SIZE,
+                      PCI_REGION_MEM|PCI_REGION_PREFETCH);
+
+       /* PCI memory space */
+       pci_set_region(hose->regions + 1,
+                      CFG_PCI2_MMIO_BASE,
+                      CFG_PCI2_MMIO_PHYS,
+                      CFG_PCI2_MMIO_SIZE,
+                      PCI_REGION_MEM);
+
+       /* PCI IO space */
+       pci_set_region(hose->regions + 2,
+                      CFG_PCI2_IO_BASE,
+                      CFG_PCI2_IO_PHYS,
+                      CFG_PCI2_IO_SIZE,
+                      PCI_REGION_IO);
+
+       /* System memory space */
+       pci_set_region(hose->regions + 3,
+                      CONFIG_PCI_SYS_MEM_BUS,
+                      CONFIG_PCI_SYS_MEM_PHYS,
+                      gd->ram_size,
+                      PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+       hose->region_count = 4;
+
+       pci_setup_indirect(hose,
+                          (CFG_IMMRBAR+0x8380),
+                          (CFG_IMMRBAR+0x8384));
+
+       pci_register_hose(hose);
+
+       /*
+        * Write to Command register
+        */
+       reg16 = 0xff;
+       dev = PCI_BDF(hose->first_busno, 0, 0);
+       pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
+       reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+       pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+       /*
+        * Clear non-reserved bits in status register.
+        */
+       pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+       pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+       pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+       /*
+        * Hose scan.
+        */
+       hose->last_busno = pci_hose_scan(hose);
+#endif
+
+}
+#endif /* CONFIG_PCI */

diff --git a/board/mpc8349emds/Makefile b/board/mpc8349emds/Makefile
new file mode 100644 (file)
index 0000000..38bbb67
--- /dev/null
+++ b/board/mpc8349emds/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   := $(BOARD).o
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

diff --git a/board/mpc8349emds/config.mk b/board/mpc8349emds/config.mk
new file mode 100644 (file)
index 0000000..edf64d1
--- /dev/null
+++ b/board/mpc8349emds/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MPC8349EMDS
+#
+
+TEXT_BASE  =   0xFE000000

diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c
new file mode 100644 (file)
index 0000000..7ece7db
--- /dev/null
+++ b/board/mpc8349emds/mpc8349emds.c
@@ -0,0 +1,602 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <command.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#if defined(CONFIG_SPD_EEPROM)
+#include <spd_sdram.h>
+#endif
+int fixed_sdram(void);
+void sdram_init(void);
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+int board_early_init_f (void)
+{
+       volatile u8* bcsr = (volatile u8*)CFG_BCSR;
+
+       /* Enable flash write */
+       bcsr[1] &= ~0x01;
+
+       return 0;
+}
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
+
+long int initdram (int board_type)
+{
+       volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+       u32 msize = 0;
+
+       if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+               return -1;
+
+       puts("Initializing\n");
+
+       /* DDR SDRAM - Main SODIMM */
+       im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+       msize = spd_sdram();
+#else
+       msize = fixed_sdram();
+#endif
+       /*
+        * Initialize SDRAM if it is on local bus.
+        */
+       sdram_init();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+       /*
+        * Initialize and enable DDR ECC.
+        */
+       ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+       puts("   DDR RAM: ");
+       /* return total bus SDRAM size(bytes)  -- DDR */
+       return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+       volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+       u32 msize = 0;
+       u32 ddr_size;
+       u32 ddr_size_log2;
+
+       msize = CFG_DDR_SIZE;
+       for (ddr_size = msize << 20, ddr_size_log2 = 0;
+            (ddr_size > 1);
+            ddr_size = ddr_size>>1, ddr_size_log2++) {
+               if (ddr_size & 1) {
+                       return -1;
+               }
+       }
+       im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+       im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+
+#if (CFG_DDR_SIZE != 256)
+#warning Currenly any ddr size other than 256 is not supported
+#endif
+       im->ddr.csbnds[2].csbnds = 0x0000000f;
+       im->ddr.cs_config[2] = CFG_DDR_CONFIG;
+
+       /* currently we use only one CS, so disable the other banks */
+       im->ddr.cs_config[0] = 0;
+       im->ddr.cs_config[1] = 0;
+       im->ddr.cs_config[3] = 0;
+
+       im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+       im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+
+       im->ddr.sdram_cfg =
+               SDRAM_CFG_SREN
+#if defined(CONFIG_DDR_2T_TIMING)
+               | SDRAM_CFG_2T_EN
+#endif
+               | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
+#if defined (CONFIG_DDR_32BIT)
+       /* for 32-bit mode burst length is 8 */
+       im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
+#endif
+       im->ddr.sdram_mode = CFG_DDR_MODE;
+
+       im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+       udelay(200);
+
+       /* enable DDR controller */
+       im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+       return msize;
+}
+#endif/*!CFG_SPD_EEPROM*/
+
+
+int checkboard (void)
+{
+       puts("Board: Freescale MPC8349EMDS\n");
+       return 0;
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc8349emds_config_table[] = {
+       {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
+       pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+                                   PCI_ENET0_MEMADDR,
+                                   PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
+       } },
+       {}
+}
+#endif
+
+volatile static struct pci_controller hose[] = {
+       {
+#ifndef CONFIG_PCI_PNP
+       config_table:pci_mpc8349emds_config_table,
+#endif
+       },
+       {
+#ifndef CONFIG_PCI_PNP
+       config_table:pci_mpc8349emds_config_table,
+#endif
+       }
+};
+#endif /* CONFIG_PCI */
+
+void pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+       extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
+
+       pci_mpc83xx_init(hose);
+#endif /* CONFIG_PCI */
+}
+
+/*
+ * if MPC8349EMDS is soldered with SDRAM
+ */
+#if defined(CFG_BR2_PRELIM)  \
+       && defined(CFG_OR2_PRELIM) \
+       && defined(CFG_LBLAWBAR2_PRELIM) \
+       && defined(CFG_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void sdram_init(void)
+{
+       volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+       volatile lbus8349_t *lbc= &immap->lbus;
+       uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+       puts("\n   SDRAM on Local Bus: ");
+       print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+       /*
+        * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+        */
+
+       /* setup mtrpt, lsrt and lbcr for LB bus */
+       lbc->lbcr = CFG_LBC_LBCR;
+       lbc->mrtpr = CFG_LBC_MRTPR;
+       lbc->lsrt = CFG_LBC_LSRT;
+       asm("sync");
+
+       /*
+        * Configure the SDRAM controller Machine Mode Register.
+        */
+       lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+
+       lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+       asm("sync");
+       *sdram_addr = 0xff;
+       udelay(100);
+
+       lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+       asm("sync");
+       /*1 times*/
+       *sdram_addr = 0xff;
+       udelay(100);
+       /*2 times*/
+       *sdram_addr = 0xff;
+       udelay(100);
+       /*3 times*/
+       *sdram_addr = 0xff;
+       udelay(100);
+       /*4 times*/
+       *sdram_addr = 0xff;
+       udelay(100);
+       /*5 times*/
+       *sdram_addr = 0xff;
+       udelay(100);
+       /*6 times*/
+       *sdram_addr = 0xff;
+       udelay(100);
+       /*7 times*/
+       *sdram_addr = 0xff;
+       udelay(100);
+       /*8 times*/
+       *sdram_addr = 0xff;
+       udelay(100);
+
+       /* 0x58636733; mode register write operation */
+       lbc->lsdmr = CFG_LBC_LSDMR_4;
+       asm("sync");
+       *sdram_addr = 0xff;
+       udelay(100);
+
+       lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+       asm("sync");
+       *sdram_addr = 0xff;
+       udelay(100);
+}
+#else
+void sdram_init(void)
+{
+       put("SDRAM on Local Bus is NOT available!\n");
+}
+#endif
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
+/*
+ * ECC user commands
+ */
+void ecc_print_status(void)
+{
+       volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+       volatile ddr8349_t *ddr = &immap->ddr;
+
+       printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
+
+       /* Interrupts */
+       printf("Memory Error Interrupt Enable:\n");
+       printf("  Multiple-Bit Error Interrupt Enable: %d\n",
+                       (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
+       printf("  Single-Bit Error Interrupt Enable: %d\n",
+                       (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
+       printf("  Memory Select Error Interrupt Enable: %d\n\n",
+                       (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
+
+       /* Error disable */
+       printf("Memory Error Disable:\n");
+       printf("  Multiple-Bit Error Disable: %d\n",
+                       (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
+       printf("  Sinle-Bit Error Disable: %d\n",
+                       (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
+       printf("  Memory Select Error Disable: %d\n\n",
+                       (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
+
+       /* Error injection */
+       printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
+                       ddr->data_err_inject_hi, ddr->data_err_inject_lo);
+
+       printf("Memory Data Path Error Injection Mask ECC:\n");
+       printf("  ECC Mirror Byte: %d\n",
+                       (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
+       printf("  ECC Injection Enable: %d\n",
+                       (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
+       printf("  ECC Error Injection Mask: 0x%02x\n\n",
+                       ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
+
+       /* SBE counter/threshold */
+       printf("Memory Single-Bit Error Management (0..255):\n");
+       printf("  Single-Bit Error Threshold: %d\n",
+                       (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
+       printf("  Single-Bit Error Counter: %d\n\n",
+                       (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
+
+       /* Error detect */
+       printf("Memory Error Detect:\n");
+       printf("  Multiple Memory Errors: %d\n",
+                       (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
+       printf("  Multiple-Bit Error: %d\n",
+                       (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
+       printf("  Single-Bit Error: %d\n",
+                       (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
+       printf("  Memory Select Error: %d\n\n",
+                       (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
+
+       /* Capture data */
+       printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
+       printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
+                       ddr->capture_data_hi, ddr->capture_data_lo);
+       printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
+               ddr->capture_ecc & CAPTURE_ECC_ECE);
+
+       printf("Memory Error Attributes Capture:\n");
+       printf("  Data Beat Number: %d\n",
+                       (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
+       printf("  Transaction Size: %d\n",
+                       (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
+       printf("  Transaction Source: %d\n",
+                       (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
+       printf("  Transaction Type: %d\n",
+                       (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
+       printf("  Error Information Valid: %d\n\n",
+                       ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
+}
+
+int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+       volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+       volatile ddr8349_t *ddr = &immap->ddr;
+       volatile u32 val;
+       u64 *addr, count, val64;
+       register u64 *i;
+
+       if (argc > 4) {
+               printf ("Usage:\n%s\n", cmdtp->usage);
+               return 1;
+       }
+
+       if (argc == 2) {
+               if (strcmp(argv[1], "status") == 0) {
+                       ecc_print_status();
+                       return 0;
+               } else if (strcmp(argv[1], "captureclear") == 0) {
+                       ddr->capture_address = 0;
+                       ddr->capture_data_hi = 0;
+                       ddr->capture_data_lo = 0;
+                       ddr->capture_ecc = 0;
+                       ddr->capture_attributes = 0;
+                       return 0;
+               }
+       }
+
+       if (argc == 3) {
+               if (strcmp(argv[1], "sbecnt") == 0) {
+                       val = simple_strtoul(argv[2], NULL, 10);
+                       if (val > 255) {
+                               printf("Incorrect Counter value, should be 0..255\n");
+                               return 1;
+                       }
+
+                       val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
+                       val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
+
+                       ddr->err_sbe = val;
+                       return 0;
+               } else if (strcmp(argv[1], "sbethr") == 0) {
+                       val = simple_strtoul(argv[2], NULL, 10);
+                       if (val > 255) {
+                               printf("Incorrect Counter value, should be 0..255\n");
+                               return 1;
+                       }
+
+                       val = (val << ECC_ERROR_MAN_SBET_SHIFT);
+                       val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
+
+                       ddr->err_sbe = val;
+                       return 0;
+               } else if (strcmp(argv[1], "errdisable") == 0) {
+                       val = ddr->err_disable;
+
+                       if (strcmp(argv[2], "+sbe") == 0) {
+                               val |= ECC_ERROR_DISABLE_SBED;
+                       } else if (strcmp(argv[2], "+mbe") == 0) {
+                               val |= ECC_ERROR_DISABLE_MBED;
+                       } else if (strcmp(argv[2], "+mse") == 0) {
+                               val |= ECC_ERROR_DISABLE_MSED;
+                       } else if (strcmp(argv[2], "+all") == 0) {
+                               val |= (ECC_ERROR_DISABLE_SBED |
+                                       ECC_ERROR_DISABLE_MBED |
+                                       ECC_ERROR_DISABLE_MSED);
+                       } else if (strcmp(argv[2], "-sbe") == 0) {
+                               val &= ~ECC_ERROR_DISABLE_SBED;
+                       } else if (strcmp(argv[2], "-mbe") == 0) {
+                               val &= ~ECC_ERROR_DISABLE_MBED;
+                       } else if (strcmp(argv[2], "-mse") == 0) {
+                               val &= ~ECC_ERROR_DISABLE_MSED;
+                       } else if (strcmp(argv[2], "-all") == 0) {
+                               val &= ~(ECC_ERROR_DISABLE_SBED |
+                                       ECC_ERROR_DISABLE_MBED |
+                                       ECC_ERROR_DISABLE_MSED);
+                       } else {
+                               printf("Incorrect err_disable field\n");
+                               return 1;
+                       }
+
+                       ddr->err_disable = val;
+                       __asm__ __volatile__ ("sync");
+                       __asm__ __volatile__ ("isync");
+                       return 0;
+               } else if (strcmp(argv[1], "errdetectclr") == 0) {
+                       val = ddr->err_detect;
+
+                       if (strcmp(argv[2], "mme") == 0) {
+                               val |= ECC_ERROR_DETECT_MME;
+                       } else if (strcmp(argv[2], "sbe") == 0) {
+                               val |= ECC_ERROR_DETECT_SBE;
+                       } else if (strcmp(argv[2], "mbe") == 0) {
+                               val |= ECC_ERROR_DETECT_MBE;
+                       } else if (strcmp(argv[2], "mse") == 0) {
+                               val |= ECC_ERROR_DETECT_MSE;
+                       } else if (strcmp(argv[2], "all") == 0) {
+                               val |= (ECC_ERROR_DETECT_MME |
+                                       ECC_ERROR_DETECT_MBE |
+                                       ECC_ERROR_DETECT_SBE |
+                                       ECC_ERROR_DETECT_MSE);
+                       } else {
+                               printf("Incorrect err_detect field\n");
+                               return 1;
+                       }
+
+                       ddr->err_detect = val;
+                       return 0;
+               } else if (strcmp(argv[1], "injectdatahi") == 0) {
+                       val = simple_strtoul(argv[2], NULL, 16);
+
+                       ddr->data_err_inject_hi = val;
+                       return 0;
+               } else if (strcmp(argv[1], "injectdatalo") == 0) {
+                       val = simple_strtoul(argv[2], NULL, 16);
+
+                       ddr->data_err_inject_lo = val;
+                       return 0;
+               } else if (strcmp(argv[1], "injectecc") == 0) {
+                       val = simple_strtoul(argv[2], NULL, 16);
+                       if (val > 0xff) {
+                               printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
+                               return 1;
+                       }
+                       val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
+
+                       ddr->ecc_err_inject = val;
+                       return 0;
+               } else if (strcmp(argv[1], "inject") == 0) {
+                       val = ddr->ecc_err_inject;
+
+                       if (strcmp(argv[2], "en") == 0)
+                               val |= ECC_ERR_INJECT_EIEN;
+                       else if (strcmp(argv[2], "dis") == 0)
+                               val &= ~ECC_ERR_INJECT_EIEN;
+                       else
+                               printf("Incorrect command\n");
+
+                       ddr->ecc_err_inject = val;
+                       __asm__ __volatile__ ("sync");
+                       __asm__ __volatile__ ("isync");
+                       return 0;
+               } else if (strcmp(argv[1], "mirror") == 0) {
+                       val = ddr->ecc_err_inject;
+
+                       if (strcmp(argv[2], "en") == 0)
+                               val |= ECC_ERR_INJECT_EMB;
+                       else if (strcmp(argv[2], "dis") == 0)
+                               val &= ~ECC_ERR_INJECT_EMB;
+                       else
+                               printf("Incorrect command\n");
+
+                       ddr->ecc_err_inject = val;
+                       return 0;
+               }
+       }
+
+       if (argc == 4) {
+               if (strcmp(argv[1], "test") == 0) {
+                       addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
+                       count = simple_strtoul(argv[3], NULL, 16);
+
+                       if ((u32)addr % 8) {
+                               printf("Address not alligned on double word boundary\n");
+                               return 1;
+                       }
+
+                       disable_interrupts();
+                       icache_disable();
+
+                       for (i = addr; i < addr + count; i++) {
+                               /* enable injects */
+                               ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
+                               __asm__ __volatile__ ("sync");
+                               __asm__ __volatile__ ("isync");
+
+                               /* write memory location injecting errors */
+                               *i = 0x1122334455667788ULL;
+                               __asm__ __volatile__ ("sync");
+
+                               /* disable injects */
+                               ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
+                               __asm__ __volatile__ ("sync");
+                               __asm__ __volatile__ ("isync");
+
+                               /* read data, this generates ECC error */
+                               val64 = *i;
+                               __asm__ __volatile__ ("sync");
+
+                               /* disable errors for ECC */
+                               ddr->err_disable |= ~ECC_ERROR_ENABLE;
+                               __asm__ __volatile__ ("sync");
+                               __asm__ __volatile__ ("isync");
+
+                               /* re-initialize memory, write the location again
+                                * NOT injecting errors this time */
+                               *i = 0xcafecafecafecafeULL;
+                               __asm__ __volatile__ ("sync");
+
+                               /* enable errors for ECC */
+                               ddr->err_disable &= ECC_ERROR_ENABLE;
+                               __asm__ __volatile__ ("sync");
+                               __asm__ __volatile__ ("isync");
+                       }
+
+                       icache_enable();
+                       enable_interrupts();
+
+                       return 0;
+               }
+       }
+
+       printf ("Usage:\n%s\n", cmdtp->usage);
+       return 1;
+}
+
+U_BOOT_CMD(
+       ecc,     4,     0,      do_ecc,
+       "ecc     - support for DDR ECC features\n",
+       "status              - print out status info\n"
+       "ecc captureclear        - clear capture regs data\n"
+       "ecc sbecnt <val>        - set Single-Bit Error counter\n"
+       "ecc sbethr <val>        - set Single-Bit Threshold\n"
+       "ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
+       "  [-|+]sbe - Single-Bit Error\n"
+       "  [-|+]mbe - Multiple-Bit Error\n"
+       "  [-|+]mse - Memory Select Error\n"
+       "  [-|+]all - all errors\n"
+       "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
+       "  mme - Multiple Memory Errors\n"
+       "  sbe - Single-Bit Error\n"
+       "  mbe - Multiple-Bit Error\n"
+       "  mse - Memory Select Error\n"
+       "  all - all errors\n"
+       "ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
+       "ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
+       "ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
+       "ecc inject <en|dis>    - enable/disable error injection\n"
+       "ecc mirror <en|dis>    - enable/disable mirror byte\n"
+       "ecc test <addr> <cnt>  - test mem region:\n"
+       "  - enables injects\n"
+       "  - writes pattern injecting errors\n"
+       "  - disables injects\n"
+       "  - reads pattern back, generates error\n"
+       "  - re-inits memory"
+);
+#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */

diff --git a/board/mpc8349emds/u-boot.lds b/board/mpc8349emds/u-boot.lds
new file mode 100644 (file)
index 0000000..937c87a
--- /dev/null
+++ b/board/mpc8349emds/u-boot.lds
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)              }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)              }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)               }
+  .rela.got      : { *(.rela.got)              }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)               }
+  .rela.bss      : { *(.rela.bss)              }
+  .rel.plt       : { *(.rel.plt)               }
+  .rela.plt      : { *(.rela.plt)              }
+  .init          : { *(.init)  }
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc83xx/start.o        (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)

diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
index b331d6ec474234b1cedf7674e5d43e4cfa429d17..06d021a026a04abc22dc225e75ebd704322454d8 100644 (file)
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -42,6 +42,9 @@
 #include "../mip405/mip405.h"
 #include <405gp_pci.h>
 #endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_PATI)
 #define FIRM_START 0xFFF00000
 #endif
@@ -584,7 +587,6 @@ extern int get_boot_mode(void);
 void video_get_info_str (int line_number, char *info)
 {
        /* init video info strings for graphic console */
-       DECLARE_GLOBAL_DATA_PTR;
        PPC405_SYS_INFO sys_info;
        char rev;
        int i,boot;

diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c
index 2c77d375ea00a5a2d2420fa2af69ed788ec48c5b..ff1190ab21294cc24533d8a30693f26c72f933aa 100644 (file)
--- a/board/mpl/common/memtst.c
+++ b/board/mpl/common/memtst.c
@@ -50,13 +50,15 @@ int testdram (void)
 #include <asm/processor.h>
 #include <405gp_i2c.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define FALSE           0
 #define TRUE            1
 
-#define TEST_QUIET                     8
+#define TEST_QUIET     8
 #define TEST_SHOW_PROG         4
 #define TEST_SHOW_ERR  2
-#define TEST_SHOW_ALL          1
+#define TEST_SHOW_ALL  1
 
 #define TESTPAT1 0xAA55AA55
 #define TESTPAT2 0x55AA55AA
@@ -468,7 +470,6 @@ static RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = {
 
 void mem_test_reloc(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned long addr;
        int i;
        for (i=0; i< TEST_STAGES; i++) {

diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c
index 692930b41639d5e55f800cf0d8199fd8c39112f2..bde14beeb168f3d9f33ec7c8dda4e7007c5f48d1 100644 (file)
--- a/board/mpl/common/pci.c
+++ b/board/mpl/common/pci.c
@@ -32,7 +32,7 @@
 #ifdef CONFIG_405GP
 #ifdef CONFIG_PCI
 
-#undef DEBUG
+DECLARE_GLOBAL_DATA_PTR;
 
 #include "piix4_pci.h"
 #include "pci_parts.h"
@@ -94,7 +94,6 @@ static struct pci_controller hose = {
 
 static void reloc_pci_cfg_table(struct pci_config_table *table)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned long addr;
 
        for (; table && table->vendor; table++) {

diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index 9c469b09ac964d2a652c257d0529b9a02ada4ba2..34f328999d1d27b7ac8df257a791e3cd3be20964 100644 (file)
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -70,6 +70,9 @@
 #include "../common/common_util.h"
 #include <i2c.h>
 #include <rtc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
 extern block_dev_desc_t * scsi_get_dev(int dev);
 extern block_dev_desc_t * ide_get_dev(int dev);
 
@@ -189,8 +192,6 @@ const sdram_t sdram_table[] = {
 void SDRAM_err (const char *s)
 {
 #ifndef SDRAM_DEBUG
-       DECLARE_GLOBAL_DATA_PTR;
-
        (void) get_clocks ();
        gd->baudrate = 9600;
        serial_init ();
@@ -241,8 +242,6 @@ void write_4hex (unsigned long val)
 
 int init_sdram (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long   tmp, baseaddr;
        unsigned short  i;
        unsigned char   trp_clocks,
@@ -681,7 +680,6 @@ extern flash_info_t flash_info[];   /* info for FLASH chips */
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        /* adjust flash start and size as well as the offset */
        gd->bd->bi_flashstart=0-flash_info[0].size;
        gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;

diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index a398362f96aef4fad6eab5f3f77e22681ba831f0..38286081ae79bb62af6fd1a37295d0de39f94fbd 100644 (file)
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -31,6 +31,8 @@
 #include "../common/isa.h"
 #include "../common/common_util.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef SDRAM_DEBUG
 
 #define FALSE           0
@@ -134,8 +136,6 @@ unsigned short NSto10PS (unsigned char spd_byte)
 void SDRAM_err (const char *s)
 {
 #ifndef SDRAM_DEBUG
-       DECLARE_GLOBAL_DATA_PTR;
-
        (void) get_clocks ();
        gd->baudrate = 9600;
        serial_init ();
@@ -191,9 +191,6 @@ int board_early_init_f (void)
                        trc_clocks, tctp_clocks;
        unsigned char cal_index, cal_val, spd_version, spd_chksum;
        unsigned char buf[8];
-#ifdef SDRAM_DEBUG
-       DECLARE_GLOBAL_DATA_PTR;
-#endif
        /* set up the config port */
        mtdcr (ebccfga, pb7ap);
        mtdcr (ebccfgd, CONFIG_PORT_AP);
@@ -613,8 +610,6 @@ static int test_dram (unsigned long ramsize);
 
 long int initdram (int board_type)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long bank_reg[4], tmp, bank_size;
        int i, ds;
        unsigned long TotalSize;
@@ -666,7 +661,6 @@ extern flash_info_t flash_info[];   /* info for FLASH chips */
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        /* adjust flash start and size as well as the offset */
        gd->bd->bi_flashstart=0-flash_info[0].size;
        gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;

diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
index ffdba5d990da9dee8f671b334d15a2f59819c614..0d2003d2fc3ae89822d6b1915df9ef6223310ebc 100644 (file)
--- a/board/mpl/vcma9/vcma9.c
+++ b/board/mpl/vcma9/vcma9.c
@@ -32,7 +32,7 @@
 #include "vcma9.h"
 #include "../common/common_util.h"
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
 
 #define FCLK_SPEED 1
 
@@ -71,7 +71,6 @@ static inline void delay(unsigned long loops)
 
 int board_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 
@@ -275,8 +274,6 @@ static void Show_VCMA9_Info(char *board_name, char *serial)
 
 int dram_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr();
 

diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c
index 20a551dfa5a3e8d64dc30eca40fa97183415330b..ee8f3e3015f865e1d0484e1997f80eeaaafae990 100644 (file)
--- a/board/mvblue/mvblue.c
+++ b/board/mvblue/mvblue.c
@@ -14,6 +14,8 @@
 #include <pci.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 u32 get_BoardType (void);
 
 #define PCI_CONFIG(b,d,f,r)    cpu_to_le32(0x80000000 | ((b&0xff)<<16) \
@@ -50,7 +52,6 @@ void hw_watchdog_reset (void)
 }
 int checkboard (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        ulong busfreq = get_bus_freq (0);
        char buf[32];
        u32 BoardType = get_BoardType ();

diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c
index 5c33ba3c0ea8354122425cc4c54bde63dbd3cbe6..abf2fd51e9bf3bd641682cc7606e4ce7362e7374 100644 (file)
--- a/board/mx1ads/mx1ads.c
+++ b/board/mx1ads/mx1ads.c
@@ -27,7 +27,7 @@
 /*#include <mc9328.h>*/
 #include <asm/arch/imx-regs.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
 
 #define FCLK_SPEED 1
 
@@ -55,10 +55,11 @@
 
 #if 0
 
-static inline void delay (unsigned long loops) {
+static inline void delay (unsigned long loops)
+{
        __asm__ volatile ("1:\n"
-         "subs %0, %1, #1\n"
-         "bne 1b":"=r" (loops):"0" (loops));
+                         "subs %0, %1, #1\n"
+                         "bne 1b":"=r" (loops):"0" (loops));
 }
 
 #endif
@@ -67,62 +68,58 @@ static inline void delay (unsigned long loops) {
  * Miscellaneous platform dependent initialisations
  */
 
-void SetAsynchMode(void) {
-       __asm__ (
-               "mrc p15,0,r0,c1,c0,0 \n"
-               "mov r2, #0xC0000000 \n"
-               "orr r0,r2,r0 \n"
-               "mcr p15,0,r0,c1,c0,0 \n"
-       );
+void SetAsynchMode (void)
+{
+       __asm__ ("mrc p15,0,r0,c1,c0,0 \n"
+                "mov r2, #0xC0000000 \n"
+                "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n");
 }
 
 static u32 mc9328sid;
 
-int board_init (void) {
+int board_init (void)
+{
+       volatile unsigned int tmp;
 
-       DECLARE_GLOBAL_DATA_PTR;
+       mc9328sid = SIDR;
 
-       volatile unsigned int  tmp;
+       GPCR = 0x000003AB;      /* I/O pad driving strength     */
 
-       mc9328sid       = SIDR;
-
-       GPCR            = 0x000003AB;           /* I/O pad driving strength     */
-
-/*     MX1_CS1U        = 0x00000A00;   */      /* SRAM initialization          */
+       /*      MX1_CS1U        = 0x00000A00;   */ /* SRAM initialization          */
 /*     MX1_CS1L        = 0x11110601;   */
 
-       MPCTL0          = 0x04632410;   /* setting for 150 MHz MCU PLL CLK      */
+       MPCTL0 = 0x04632410;    /* setting for 150 MHz MCU PLL CLK      */
 
 /* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
  * BCLK divider to 2 (i.e. BCLK to 48 MHz)
  */
-       CSCR    = 0xAF000403;
+       CSCR = 0xAF000403;
 
-       CSCR    |= 0x00200000;          /* Trigger the restart bit(bit 21)      */
-       CSCR    &= 0xFFFF7FFF;          /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
+       CSCR |= 0x00200000;     /* Trigger the restart bit(bit 21)      */
+       CSCR &= 0xFFFF7FFF;     /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
 
 /* setup cs4 for cs8900 ethernet */
 
-       CS4U    = 0x00000F00;   /* Initialize CS4 for CS8900 ethernet   */
-       CS4L    = 0x00001501;
+       CS4U = 0x00000F00;      /* Initialize CS4 for CS8900 ethernet   */
+       CS4L = 0x00001501;
 
-       GIUS(0) &= 0xFF3FFFFF;
-       GPR(0)  &= 0xFF3FFFFF;
+       GIUS (0) &= 0xFF3FFFFF;
+       GPR (0) &= 0xFF3FFFFF;
 
-       tmp = *(unsigned int *)(0x1500000C);
-       tmp = *(unsigned int *)(0x1500000C);
+       tmp = *(unsigned int *) (0x1500000C);
+       tmp = *(unsigned int *) (0x1500000C);
 
-       SetAsynchMode();
+       SetAsynchMode ();
 
        gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
 
-       gd->bd->bi_boot_params = 0x08000100;    /* adress of boot parameters    */
+       gd->bd->bi_boot_params = 0x08000100;    /* adress of boot parameters    */
 
-       icache_enable();
-       dcache_enable();
+       icache_enable ();
+       dcache_enable ();
 
 /* set PERCLKs                         */
-       PCDR = 0x00000055;      /* set PERCLKS                          */
+       PCDR = 0x00000055;      /* set PERCLKS                          */
 
 /* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
  * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
@@ -135,34 +132,38 @@ int board_init (void) {
        return 0;
 }
 
-int board_late_init(void) {
-
-       setenv("stdout", "serial");
-       setenv("stderr", "serial");
-
-       switch  (mc9328sid) {
-               case 0x0005901d :
-                       printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid);
-                       break;
-               case 0x04d4c01d :
-                       printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid);
-                       break;
-               case 0x00d4c01d :
-                       printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid);
-                       break;
-
-               default :
-                       printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
-                       break;
+int board_late_init (void)
+{
+
+       setenv ("stdout", "serial");
+       setenv ("stderr", "serial");
+
+       switch (mc9328sid) {
+       case 0x0005901d:
+               printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",
+                       mc9328sid);
+               break;
+       case 0x04d4c01d:
+               printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",
+                       mc9328sid);
+               break;
+       case 0x00d4c01d:
+               printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",
+                       mc9328sid);
+               break;
+
+       default:
+               printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",
+                       mc9328sid);
+               break;
        }
        return 0;
 }
 
-int dram_init (void) {
-       DECLARE_GLOBAL_DATA_PTR;
-
+int dram_init (void)
+{
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-       gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 
        return 0;
 }

diff --git a/board/mx1fs2/mx1fs2.c b/board/mx1fs2/mx1fs2.c
index 9e7a06c0df7c41fc46d802c678188ae20e41699a..1c026f0f7ace635f1d81008f7ce6c7d4baa1a2fd 100644 (file)
--- a/board/mx1fs2/mx1fs2.c
+++ b/board/mx1fs2/mx1fs2.c
@@ -19,9 +19,10 @@
  */
 
 #include <common.h>
-
 #include <asm/arch/imx-regs.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
 
 extern void imx_gpio_mode(int gpio_mode);
@@ -79,8 +80,6 @@ static void logo_init(void)
 int
 board_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_arch_number = MACH_TYPE_MX1FS2;
        gd->bd->bi_boot_params = 0x08000100;
 serial_init();
@@ -91,8 +90,6 @@ serial_init();
 int
 dram_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
 #if ( CONFIG_NR_DRAM_BANKS > 0 )
        gd->bd->bi_dram[0].start = MX1FS2_SDRAM_1;
        gd->bd->bi_dram[0].size = MX1FS2_SDRAM_1_SIZE;

diff --git a/board/nc650/Makefile b/board/nc650/Makefile
index a4dd85f508d567fef18ca894027f56a90da00d6c..8dc4934f79487def30ae1c2b8f41f5fb521d9e4e 100644 (file)
--- a/board/nc650/Makefile
+++ b/board/nc650/Makefile
@@ -1,4 +1,5 @@
 #
+# (C) Copyright 2006 Detlev Zundel, dzu@denx.de
 # (C) Copyright 2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
@@ -25,7 +26,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = lib$(BOARD).a
 
-OBJS   = $(BOARD).o flash.o
+OBJS   = $(BOARD).o nand.o flash.o
 
 $(LIB):        .depend $(OBJS)
        $(AR) crv $@ $(OBJS)

diff --git a/board/nc650/config.mk b/board/nc650/config.mk
index fa8ba3186ca574fa859b692a1116feb61609a597..5b2284aec4d5d7a3342499bedf21bbc5b6dfa112 100644 (file)
--- a/board/nc650/config.mk
+++ b/board/nc650/config.mk
@@ -1,4 +1,5 @@
 #
+# (C) Copyright 2006 Detlev Zundel, dzu@denx.de
 # (C) Copyright 2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
@@ -26,3 +27,4 @@
 #
 
 TEXT_BASE = 0x40700000
+BOARDLIBS = drivers/nand/libnand.a

diff --git a/board/nc650/flash.c b/board/nc650/flash.c
index ce2f83bc794527cdc5d8f026baf8cd00320a3ec2..8d7c1726577b85dc6220ae1558c074f1321499b8 100644 (file)
--- a/board/nc650/flash.c
+++ b/board/nc650/flash.c
@@ -32,6 +32,8 @@
 #include <common.h>
 #include <mpc8xx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
 #define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
                                      OR_SCY_2_CLK | OR_EHTR | OR_BI)
@@ -95,8 +97,6 @@ unsigned long flash_init (void)
 #ifdef CFG_OR_TIMING_FLASH_AT_50MHZ
        int scy, trlx, flash_or_timing, clk_diff;
 
-       DECLARE_GLOBAL_DATA_PTR;
-
        scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
        if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
                trlx = OR_TRLX;

diff --git a/board/nc650/nand.c b/board/nc650/nand.c
new file mode 100644 (file)
index 0000000..f27e536
--- /dev/null
+++ b/board/nc650/nand.c
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+
+#if defined(CONFIG_IDS852_REV1)
+/*
+ *     hardware specific access to control-lines
+ */
+static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+       struct nand_chip *this = mtd->priv;
+
+       switch(cmd) {
+               case NAND_CTL_SETCLE:
+                       this->IO_ADDR_W += 2;
+                       break;
+               case NAND_CTL_CLRCLE:
+                       this->IO_ADDR_W -= 2;
+                       break;
+               case NAND_CTL_SETALE:
+                       this->IO_ADDR_W += 1;
+                       break;
+               case NAND_CTL_CLRALE:
+                       this->IO_ADDR_W -= 1;
+                       break;
+               case NAND_CTL_SETNCE:
+               case NAND_CTL_CLRNCE:
+                       /* nop */
+                       break;
+       }
+}
+#elif defined(CONFIG_IDS852_REV2)
+/*
+ *     hardware specific access to control-lines
+ */
+static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+       struct nand_chip *this = mtd->priv;
+
+       switch(cmd) {
+               case NAND_CTL_SETCLE:
+                       *(((volatile __u8 *) this->IO_ADDR_W) + 0xa) = 0; 
+                       break;
+               case NAND_CTL_CLRCLE:
+                       *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; 
+                       break;
+               case NAND_CTL_SETALE:
+                       *(((volatile __u8 *) this->IO_ADDR_W) + 0x9) = 0; 
+                       break;
+               case NAND_CTL_CLRALE:
+                       *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; 
+                       break;
+               case NAND_CTL_SETNCE:
+                       *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0; 
+                       break;
+               case NAND_CTL_CLRNCE:
+                       *(((volatile __u8 *) this->IO_ADDR_W) + 0xc) = 0; 
+                       break;
+       }
+}
+#else
+#error Unknown IDS852 module revision
+#endif
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for  accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
+ *   only be provided if a hardware ECC is available
+ * - eccmode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ *   read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ *   nand_scan about special functionality. See the defines for further
+ *   explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+void board_nand_init(struct nand_chip *nand)
+{
+
+       nand->hwcontrol = nc650_hwcontrol;
+       nand->eccmode = NAND_ECC_SOFT;
+       nand->chip_delay = 12;
+/*     nand->options = NAND_SAMSUNG_LP_OPTIONS;*/
+}
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */

diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c
index fe96b93816f5932068b4fcb6412deefbdd574569..c90ac9c955b5b42f41ab14a2a629b695888bd3d6 100644 (file)
--- a/board/nc650/nc650.c
+++ b/board/nc650/nc650.c
@@ -1,4 +1,5 @@
 /*
+ * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
  * (C) Copyright 2001
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
@@ -108,7 +109,16 @@ const uint nand_flash_table[] = {
 
 int checkboard (void)
 {
-       puts ("Board: NC650\n");
+#if !defined(CONFIG_CP850)
+       puts ("Board: NC650");
+#else
+       puts ("Board: CP850");
+#endif
+#if defined(CONFIG_IDS852_REV1)
+       puts (" with IDS852 rev 1 module\n");
+#elif defined(CONFIG_IDS852_REV2)
+       puts (" with IDS852 rev 2 module\n");
+#endif
        return 0;
 }
 
@@ -241,13 +251,61 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
        return (get_ram_size(base, maxsize));
 }
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-void nand_init(void)
-{
-       extern unsigned long nand_probe(unsigned long physadr);
 
-       unsigned long totlen = nand_probe(CFG_NAND_BASE);
+#if defined(CONFIG_CP850)
+
+#define DPRAM_VARNAME           "KP850DIP"
+#define PARAM_ADDR              0x7C0
+#define NAME_ADDR               0x7F8
+#define BOARD_NAME              "KP01"
+#define DEFAULT_LB              "241111"
 
-       printf ("%4lu MB\n", totlen >> 20);
+int misc_init_r(void)
+{
+       int             iCompatMode = 0;
+       char            *pParam = NULL;
+       char            *envlb;
+       
+       /* 
+          First byte in CPLD read address space signals compatibility mode
+          0 - cp850
+          1 - kp852
+       */
+       pParam = (char*)(CFG_CPLD_BASE);
+       if( *pParam != 0)
+               iCompatMode = 1;
+       
+       if ( iCompatMode != 0) {
+               /* 
+                  In KP852 compatibility mode we have to write to
+                  DPRAM as early as possible the binary coded
+                  line config and board name.
+                  The line config is derived from the environment
+                  variable DPRAM_VARNAME by converting from ASCII
+                  to binary per character.
+               */
+               if ( (envlb = getenv ( DPRAM_VARNAME )) == 0) {
+                       setenv( DPRAM_VARNAME, DEFAULT_LB);
+                       envlb = DEFAULT_LB;
+               }
+               
+               /* Status string */
+               printf("Mode:  KP852(LB=%s)\n", envlb);
+
+               /* copy appl init */
+               pParam = (char*)(DPRAM_BASE_ADDR + PARAM_ADDR);
+               while (*envlb) {
+                       *(pParam++) = *(envlb++) - '0';
+               }
+               *pParam = '\0';
+
+               /* copy board id */
+               pParam = (char*)(DPRAM_BASE_ADDR + NAME_ADDR);
+               strcpy( pParam, BOARD_NAME);
+       } else {
+               puts("Mode:  CP850\n");
+       }
+       
+       return 0;
 }
 #endif

diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c
index dd03e4bd5bdd490a8b0c5e8af9d669d418c5e90b..297de97a554ed25eae725acb6566f2ddcb3a6e71 100644 (file)
--- a/board/netphone/netphone.c
+++ b/board/netphone/netphone.c
@@ -599,7 +599,7 @@ int board_early_init_f(void)
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 
 extern ulong nand_probe(ulong physadr);
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

diff --git a/board/netstar/Makefile b/board/netstar/Makefile
new file mode 100644 (file)
index 0000000..3a20501
--- /dev/null
+++ b/board/netstar/Makefile
@@ -0,0 +1,85 @@
+#
+# (C) Copyright 2005
+# Ladislav Michl, 2N Telekomunikace, michl@2n.cz
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   := netstar.o flash.o nand.o
+SOBJS  := setup.o crcek.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all:   $(LIB) eeprom.srec eeprom.bin crcek.srec crcek.bin crcit
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $^
+
+eeprom.srec:   eeprom.o eeprom_start.o
+       $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
+               -o $(<:.o=) -e $(<:.o=) $^ \
+               -L../../examples -lstubs \
+               -L../../lib_generic -lgeneric \
+               -L$(gcclibdir) -lgcc
+       $(OBJCOPY) -O srec $(<:.o=) $@
+
+eeprom.bin:    eeprom.srec
+       $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
+
+crcek.srec:    crcek.o
+       $(LD) -g -Ttext 0x00000000 \
+               -o $(<:.o=) -e $(<:.o=) $^
+       $(OBJCOPY) -O srec $(<:.o=) $@
+
+crcek.bin:     crcek.srec
+       $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
+
+crcit:         crcit.o crc32.o
+       $(HOSTCC) $(HOST_CFLAGS) -o $@ $^
+
+crcit.o:       crcit.c
+       $(HOSTCC) $(HOST_CFLAGS) -c $<
+
+crc32.o:       $(TOPDIR)/tools/crc32.c
+       $(HOSTCC) $(HOST_CFLAGS) -DUSE_HOSTCC -c $<
+
+clean:
+       rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin \
+               crcek crcek.srec crcek.bin
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

diff --git a/board/netstar/config.mk b/board/netstar/config.mk
new file mode 100644 (file)
index 0000000..8b73e97
--- /dev/null
+++ b/board/netstar/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x13FC0000

diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S
new file mode 100644 (file)
index 0000000..6ca4d11
--- /dev/null
+++ b/board/netstar/crcek.S
@@ -0,0 +1,177 @@
+/**
+ * (C) Copyright 2005
+ * 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2.
+ *
+ * Image layout looks like following:
+ *     u32 - size
+ *     u32 - version
+ *     ... - data
+ *     u32 - crc32
+ */
+
+#include "crcek.h"
+
+/**
+ * do_crc32 - calculate CRC32 of given buffer
+ * r0 - crc
+ * r1 - pointer to buffer
+ * r2 - buffer len
+ */
+       .macro  do_crc32
+       ldr     r5, FFFFFFFF
+       eor     r0, r0, r5
+       adr     r3, CRC32_TABLE
+1:
+       ldrb    r4, [r1], #1
+       eor     r4, r4, r0
+       and     r4, r4, #0xff
+       ldr     r4, [r3, r4, lsl#2]
+       eor     r0, r4, r0, lsr#8
+       subs    r2, r2, #0x1
+       bne     1b
+       eor     r0, r0, r5
+       .endm
+
+       .macro crcuj, offset, size
+       mov     r0, #0
+       ldr     r1, \offset
+       ldr     r2, [r1]
+       cmp     r2, r0          @ no data, no problem
+       beq     2f
+       tst     r2, #3          @ unaligned size
+       bne     2f
+       ldr     r3, \size
+       cmp     r2, r3          @ bogus size
+       bhi     2f
+       add     r1, r1, #4
+       do_crc32
+       ldr     r1, [r1]
+2:
+       cmp     r0, r1
+       .endm
+
+       .macro wait, reg
+       mov     \reg, #0x1000
+3:
+       subs    \reg, \reg, #0x1
+       bne     3b
+
+       .endm
+.text
+.globl crcek
+crcek:
+       b       crc2_bad
+       mov     r6, #0
+       crcuj   _LOADER1_OFFSET, _LOADER_SIZE
+       bne     crc1_bad
+       orr     r6, r6, #1
+crc1_bad:
+       crcuj   _LOADER2_OFFSET, _LOADER_SIZE
+       bne     crc2_bad
+       orr     r6, r6, #2
+crc2_bad:
+       ldr     r3, _LOADER1_OFFSET
+       ldr     r4, _LOADER2_OFFSET
+       b       boot_2nd
+       tst     r6, #3
+       beq     one_is_bad      @ one of them (or both) has bad crc
+       ldr     r1, [r3, #4]
+       ldr     r2, [r4, #4]
+       cmp     r1, r2          @ boot 2nd loader if versions differ
+       beq     boot_1st
+       b       boot_2nd
+one_is_bad:
+       tst     r6, #1
+       bne     boot_1st
+       tst     r6, #2
+       bne     boot_2nd
+@ We are doomed, so let user know.
+       ldr     r0, GPIO_BASE   @ configure GPIO pins
+       ldr     r1, GPIO_DIRECTION
+       strh    r1, [r0, #0x08]
+blink_loop:
+       mov     r1, #0x08
+       strh    r1, [r0, #0x04]
+       wait    r3
+       mov     r1, #0x10
+       strh    r1, [r0, #0x04]
+       wait    r3
+       b blink_loop
+boot_1st:
+       add     pc, r3, #8
+boot_2nd:
+       add     pc, r4, #8
+
+_LOADER_SIZE:
+       .word LOADER_SIZE - 8   @ minus size and crc32
+_LOADER1_OFFSET:
+       .word LOADER1_OFFSET
+_LOADER2_OFFSET:
+       .word LOADER2_OFFSET
+
+FFFFFFFF:
+       .word 0xffffffff
+CRC32_TABLE:
+       .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419
+       .word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4
+       .word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07
+       .word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de
+       .word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856
+       .word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9
+       .word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4
+       .word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b
+       .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3
+       .word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a
+       .word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599
+       .word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924
+       .word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190
+       .word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f
+       .word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e
+       .word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01
+       .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed
+       .word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950
+       .word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3
+       .word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2
+       .word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a
+       .word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5
+       .word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010
+       .word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f
+       .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17
+       .word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6
+       .word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615
+       .word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8
+       .word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344
+       .word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb
+       .word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a
+       .word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5
+       .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1
+       .word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c
+       .word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef
+       .word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236
+       .word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe
+       .word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31
+       .word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c
+       .word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713
+       .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b
+       .word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242
+       .word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1
+       .word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c
+       .word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278
+       .word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7
+       .word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66
+       .word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9
+       .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605
+       .word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8
+       .word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b
+       .word 0x2d02ef8d
+
+GPIO_BASE:
+       .word 0xfffce000
+GPIO_DIRECTION:
+       .word 0x0000ffe7
+
+.end

diff --git a/board/netstar/crcek.h b/board/netstar/crcek.h
new file mode 100644 (file)
index 0000000..30c0860
--- /dev/null
+++ b/board/netstar/crcek.h
@@ -0,0 +1,3 @@
+#define LOADER_SIZE    (448 * 1024)
+#define LOADER1_OFFSET (128 * 1024)
+#define LOADER2_OFFSET (LOADER1_OFFSET + LOADER_SIZE)

diff --git a/board/netstar/crcit b/board/netstar/crcit
new file mode 100755 (executable)
index 0000000..98ae42e
Binary files /dev/null and b/board/netstar/crcit differ

diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c
new file mode 100644 (file)
index 0000000..f6d3066
--- /dev/null
+++ b/board/netstar/crcit.c
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2005
+ * 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <fcntl.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include "crcek.h"
+
+extern unsigned long crc32(unsigned long, const unsigned char *, unsigned int);
+
+uint32_t data[LOADER_SIZE/4 + 3];
+
+int doit(char *path, unsigned version)
+{
+       uint32_t *p;
+       ssize_t size;
+       int fd;
+
+       fd = open(path, O_RDONLY);
+       if (fd == -1) {
+               perror("Error opening file");
+               return EXIT_FAILURE;
+       }
+       p = data + 2;
+       size = read(fd, p, LOADER_SIZE + 4);
+       if (size == -1) {
+               perror("Error reading file");
+               return EXIT_FAILURE;
+       }
+       if (size > LOADER_SIZE) {
+               fprintf(stderr, "File too large\n");
+               return EXIT_FAILURE;
+       }
+       size = (((size - 1) >> 2) + 1) << 2;
+       data[0] = size + 4;     /* add size of version field */
+       data[1] = version;
+       data[(size >> 2) + 2] = crc32(0, (unsigned char *)(data + 1), data[0]);
+       close(fd);
+
+       if (write(STDOUT_FILENO, data, size + 3*4) == -1) {
+               perror("Error writing file");
+               return EXIT_FAILURE;
+       }
+
+       return EXIT_SUCCESS;
+}
+
+int main(int argc, char **argv)
+{
+       if (argc == 2) {
+               return doit(argv[1], 0);
+       } else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) {
+               char *endptr, *nptr = argv[2];
+               unsigned ver = strtoul(nptr, &endptr, 0);
+               if (nptr != '\0' && endptr == '\0')
+                       return doit(argv[3], ver);
+       }
+       fprintf(stderr, "Usage: crcit [-v version] <image>\n");
+
+       return EXIT_FAILURE;
+}

diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c
new file mode 100644 (file)
index 0000000..fef3822
--- /dev/null
+++ b/board/netstar/eeprom.c
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2005
+ * Ladislav Michl, 2N Telekomunikace, michl@2n.cz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Some code shamelessly stolen back from Robin Getz.
+ */
+
+#define DEBUG
+
+#include <common.h>
+#include <exports.h>
+#include "../drivers/smc91111.h"
+
+#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
+
+static u16 read_eeprom_reg(u16 reg)
+{
+       int timeout;
+
+       SMC_SELECT_BANK(2);
+       SMC_outw(reg, PTR_REG);
+
+       SMC_SELECT_BANK(1);
+       SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
+                CTL_REG);
+       timeout = 100;
+       while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout)
+               udelay(100);
+       if (timeout == 0) {
+               printf("Timeout Reading EEPROM register %02x\n", reg);
+               return 0;
+       }
+
+       return SMC_inw (GP_REG);
+}
+
+static int write_eeprom_reg(u16 value, u16 reg)
+{
+       int timeout;
+
+       SMC_SELECT_BANK(2);
+       SMC_outw(reg, PTR_REG);
+
+       SMC_SELECT_BANK(1);
+       SMC_outw(value, GP_REG);
+       SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
+       timeout = 100;
+       while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout)
+               udelay (100);
+       if (timeout == 0) {
+               printf("Timeout Writing EEPROM register %02x\n", reg);
+               return 0;
+       }
+
+       return 1;
+}
+
+static int write_data(u16 *buf, int len)
+{
+       u16 reg = 0x23;
+
+       while (len--)
+               write_eeprom_reg(*buf++, reg++);
+
+       return 0;
+}
+
+static int verify_macaddr(char *s)
+{
+       u16 reg;
+       int i, err = 0;
+
+       printf("MAC Address: ");
+       err = i = 0;
+       for (i = 0; i < 3; i++) {
+               reg = read_eeprom_reg(0x20 + i);
+               printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
+               if (s)
+                       err |= reg != ((u16 *)s)[i];
+       }
+
+       return err ? 0 : 1;
+}
+
+static int set_mac(char *s)
+{
+       int i;
+       char *e, eaddr[6];
+
+       /* turn string into mac value */
+       for (i = 0; i < 6; i++) {
+               eaddr[i] = simple_strtoul(s, &e, 16);
+               s = (*e) ? e+1 : e;
+       }
+
+       for (i = 0; i < 3; i++)
+               write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
+
+       return 0;
+}
+
+static int parse_element(char *s, unsigned char *buf, int len)
+{
+       int cnt;
+       char *p, num[3];
+       unsigned char id;
+
+       id = simple_strtoul(s, &p, 16);
+       if (*p++ != ':')
+               return -1;
+       cnt = 2;
+       num[2] = 0;
+       for (; *p; p += 2) {
+               if (p[1] == 0)
+                       return -2;
+               if (cnt + 3 > len)
+                       return -3;
+               num[0] = p[0];
+               num[1] = p[1];
+               buf[cnt++] = simple_strtoul(num, NULL, 16);
+       }
+       buf[0] = id;
+       buf[1] = cnt - 2;
+
+       return cnt;
+}
+
+extern int crcek(void);
+
+int eeprom(int argc, char *argv[])
+{
+       int i, len, ret;
+       unsigned char buf[58], *p;
+
+       app_startup(argv);
+       if (get_version() != XF_VERSION) {
+               printf("Wrong XF_VERSION.\n");
+               printf("Application expects ABI version %d\n", XF_VERSION);
+               printf("Actual U-Boot ABI version %d\n", (int)get_version());
+               return 1;
+       }
+
+       return crcek();
+
+       if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
+               printf("SMSC91111 not found.\n");
+               return 2;
+       }
+
+       /* Called without parameters - print MAC address */
+       if (argc < 2) {
+               verify_macaddr(NULL);
+               return 0;
+       }
+
+       /* Print help message */
+       if (argv[1][1] == 'h') {
+               printf("VoiceBlue EEPROM writer\n");
+               printf("Built: %s at %s\n", __DATE__ , __TIME__ );
+               printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
+               return 0;
+       }
+
+       /* Try to parse information elements */
+       len = sizeof(buf);
+       p = buf;
+       for (i = 2; i < argc; i++) {
+               ret = parse_element(argv[i], p, len);
+               switch (ret) {
+               case -1:
+                       printf("Element %d: malformed\n", i - 1);
+                       return 3;
+               case -2:
+                       printf("Element %d: odd character count\n", i - 1);
+                       return 3;
+               case -3:
+                       printf("Out of EEPROM memory\n");
+                       return 3;
+               default:
+                       p += ret;
+                       len -= ret;
+               }
+       }
+
+       /* First argument (MAC) is mandatory */
+       set_mac(argv[1]);
+       if (verify_macaddr(argv[1])) {
+               printf("*** MAC address does not match! ***\n");
+               return 4;
+       }
+
+       while (len--)
+               *p++ = 0;
+
+       write_data((u16 *)buf, sizeof(buf) >> 1);
+
+       return 0;
+}

diff --git a/board/netstar/eeprom.lds b/board/netstar/eeprom.lds
new file mode 100644 (file)
index 0000000..317550d
--- /dev/null
+++ b/board/netstar/eeprom.lds
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ * (C) Copyright 2005
+ * Ladislav Michl, 2N Telekomunikace, <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = ALIGN(4);
+       .text      :
+       {
+         eeprom_start.o        (.text)
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data : { *(.data) }
+
+       . = ALIGN(4);
+       .got : { *(.got) }
+
+       . = ALIGN(4);
+       __bss_start = .;
+       .bss : { *(.bss) }
+       _end = .;
+}

diff --git a/board/netstar/eeprom_start.S b/board/netstar/eeprom_start.S
new file mode 100644 (file)
index 0000000..75d9f05
--- /dev/null
+++ b/board/netstar/eeprom_start.S
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2005  2N Telekomunikace
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+.globl _start
+_start:        b       eeprom
+
+#include "crcek.h"
+
+/**
+ * do_crc32 - calculate CRC32 of given buffer
+ * r0 - crc
+ * r1 - pointer to buffer
+ * r2 - buffer len
+ */
+       .macro  do_crc32
+       ldr     r5, FFFFFFFF
+       eor     r0, r0, r5
+       adr     r3, CRC32_TABLE
+1:
+       ldrb    r4, [r1], #1
+       eor     r4, r4, r0
+       and     r4, r4, #0xff
+       ldr     r4, [r3, r4, lsl#2]
+       eor     r0, r4, r0, lsr#8
+       subs    r2, r2, #0x1
+       bne     1b
+       eor     r0, r0, r5
+       .endm
+
+       .macro crcuj, offset, size
+       ldr     r1, \offset
+       ldr     r2, [r1]
+       cmp     r2, #0          @ no data, no problem
+       beq     2f
+       mov     r7, #1
+       tst     r2, #3          @ unaligned size
+       bne     2f
+       mov     r7, #2
+       ldr     r0, \size
+       cmp     r2, r0          @ bogus size
+       bhi     2f
+       mov     r7, #3
+       add     r1, r1, #4
+       mov     r0, #0
+       do_crc32
+       ldr     r1, [r1]
+2:
+       cmp     r0, r1
+       .endm
+
+       .macro wait, reg
+       mov     \reg, #0x1000
+3:
+       subs    \reg, \reg, #0x1
+       bne     3b
+
+       .endm
+.text
+.globl crcek
+crcek:
+       mov     r6, #0
+@      crcuj   _LOADER1_OFFSET, _LOADER_SIZE
+@      bne     crc1_bad
+@      orr     r6, r6, #1
+crc1_bad:
+       crcuj   _LOADER2_OFFSET, _LOADER_SIZE
+       bne     crc2_bad
+       orr     r6, r6, #2
+crc2_bad:
+@      mov     r0, r6
+       mov     pc, lr
+       ldr     r3, _LOADER1_OFFSET
+       ldr     r4, _LOADER2_OFFSET
+       tst     r6, #3
+       beq     one_is_bad      @ one of them (or both) has bad crc
+       ldr     r1, [r3, #4]
+       ldr     r2, [r4, #4]
+       cmp     r1, r2          @ boot 2nd loader if versions differ
+       beq     boot_1st
+       b       boot_2nd
+one_is_bad:
+       tst     r6, #1
+       bne     boot_1st
+       tst     r6, #2
+       bne     boot_2nd
+@ We are doomed, so let user know.
+       ldr     r0, GPIO_BASE   @ configure GPIO pins
+       ldr     r1, GPIO_DIRECTION
+       strh    r1, [r0, #0x08]
+blink_loop:
+       mov     r1, #0x08
+       strh    r1, [r0, #0x04]
+       wait    r3
+       mov     r1, #0x10
+       strh    r1, [r0, #0x04]
+       wait    r3
+       b blink_loop
+boot_1st:
+       add     pc, r3, #8
+boot_2nd:
+       add     pc, r4, #8
+
+_LOADER_SIZE:
+       .word LOADER_SIZE - 8   @ minus size and crc32
+_LOADER1_OFFSET:
+       .word LOADER1_OFFSET
+_LOADER2_OFFSET:
+       .word LOADER2_OFFSET
+
+FFFFFFFF:
+       .word 0xffffffff
+CRC32_TABLE:
+       .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419
+       .word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4
+       .word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07
+       .word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de
+       .word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856
+       .word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9
+       .word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4
+       .word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b
+       .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3
+       .word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a
+       .word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599
+       .word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924
+       .word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190
+       .word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f
+       .word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e
+       .word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01
+       .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed
+       .word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950
+       .word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3
+       .word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2
+       .word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a
+       .word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5
+       .word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010
+       .word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f
+       .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17
+       .word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6
+       .word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615
+       .word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8
+       .word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344
+       .word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb
+       .word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a
+       .word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5
+       .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1
+       .word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c
+       .word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef
+       .word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236
+       .word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe
+       .word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31
+       .word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c
+       .word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713
+       .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b
+       .word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242
+       .word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1
+       .word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c
+       .word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278
+       .word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7
+       .word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66
+       .word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9
+       .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605
+       .word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8
+       .word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b
+       .word 0x2d02ef8d
+
+GPIO_BASE:
+       .word 0xfffce000
+GPIO_DIRECTION:
+       .word 0x0000ffe7
+
+.end

diff --git a/board/netstar/flash.c b/board/netstar/flash.c
new file mode 100644 (file)
index 0000000..692c416
--- /dev/null
+++ b/board/netstar/flash.c
@@ -0,0 +1,343 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2005
+ * 2N Telekomunikace, a.s. <www.2n.cz>
+ * Ladislav Michl <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*#if 0 */
+#if (PHYS_SDRAM_1_SIZE != SZ_32M)
+
+#include "crcek.h"
+
+#if (CFG_MAX_FLASH_BANKS > 1)
+#error There is always only _one_ flash chip
+#endif
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+#define CMD_READ_ARRAY         0x000000f0
+#define CMD_UNLOCK1            0x000000aa
+#define CMD_UNLOCK2            0x00000055
+#define CMD_ERASE_SETUP                0x00000080
+#define CMD_ERASE_CONFIRM      0x00000030
+#define CMD_PROGRAM            0x000000a0
+#define CMD_UNLOCK_BYPASS      0x00000020
+
+#define MEM_FLASH_ADDR1                (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2                (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002aa << 1)))
+
+#define BIT_ERASE_DONE         0x00000080
+#define BIT_RDY_MASK           0x00000080
+#define BIT_PROGRAM_ERROR      0x00000020
+#define BIT_TIMEOUT            0x80000000      /* our flag */
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init(void)
+{
+       int i;
+
+       flash_info[0].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) |
+                                (AMD_ID_LV800B & FLASH_TYPEMASK);
+       flash_info[0].size = PHYS_FLASH_1_SIZE;
+       flash_info[0].sector_count = CFG_MAX_FLASH_SECT;
+       memset(flash_info[0].protect, 0, CFG_MAX_FLASH_SECT);
+
+       for (i = 0; i < flash_info[0].sector_count; i++) {
+               switch (i) {
+               case 0: /* 16kB */
+                       flash_info[0].start[0] = CFG_FLASH_BASE;
+                       break;
+               case 1: /* 8kB */
+                       flash_info[0].start[1] = CFG_FLASH_BASE + 0x4000;
+                       break;
+               case 2: /* 8kB */
+                       flash_info[0].start[2] = CFG_FLASH_BASE + 0x4000 +
+                                                0x2000;
+                       break;
+               case 3: /* 32 KB */
+                       flash_info[0].start[3] = CFG_FLASH_BASE + 0x4000 +
+                                                2 * 0x2000;
+                       break;
+               case 4:
+                       flash_info[0].start[4] = CFG_FLASH_BASE + 0x4000 +
+                                                2 * 0x2000 + 0x8000;
+                       break;
+               default: /* 64kB */
+                       flash_info[0].start[i] = flash_info[0].start[i-1] +
+                                                0x10000;
+                       break;
+               }
+       }
+
+       /* U-Boot */
+       flash_protect(FLAG_PROTECT_SET,
+                     LOADER1_OFFSET,
+                     LOADER1_OFFSET + LOADER_SIZE - 1, flash_info);
+       /* Protect crcek, env and r_env as well */
+       flash_protect(FLAG_PROTECT_SET, 0, 0x8000 - 1, flash_info);
+
+       return flash_info[0].size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t *info)
+{
+       int i;
+
+       switch (info->flash_id & FLASH_VENDMASK) {
+       case (AMD_MANUFACT & FLASH_VENDMASK):
+               puts("AMD: ");
+               break;
+       default:
+               puts("Unknown vendor ");
+               break;
+       }
+
+       switch (info->flash_id & FLASH_TYPEMASK) {
+       case (AMD_ID_LV800B & FLASH_TYPEMASK):
+               puts("AM29LV800BB (8Mb)\n");
+               break;
+       default:
+               puts("Unknown chip type\n");
+               return;
+       }
+
+       printf("  Size: %ld MB in %d sectors\n",
+              info->size >> 20, info->sector_count);
+
+       puts("  Sector start addresses:");
+       for (i = 0; i < info->sector_count; i++) {
+               if ((i % 5) == 0)
+                       puts("\n   ");
+
+               printf(" %08lX%s", info->start[i],
+                      info->protect[i] ? " (RO)" : "     ");
+       }
+       puts("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+       ushort result;
+       int prot, sect;
+       int rc = ERR_OK;
+
+       /* first look for protection bits */
+
+       if (info->flash_id == FLASH_UNKNOWN)
+               return ERR_UNKNOWN_FLASH_TYPE;
+
+       if ((s_first < 0) || (s_first > s_last))
+               return ERR_INVAL;
+
+       if ((info->flash_id & FLASH_VENDMASK) !=
+           (AMD_MANUFACT & FLASH_VENDMASK))
+               return ERR_UNKNOWN_FLASH_VENDOR;
+
+       prot = 0;
+       for (sect = s_first; sect <= s_last; ++sect)
+               if (info->protect[sect])
+                       prot++;
+
+       if (prot)
+               printf("- Warning: %d protected sectors will not be erased!\n",
+                      prot);
+       else
+               putc('\n');
+
+       /* Start erase on unprotected sectors */
+       for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+               if (info->protect[sect] == 0) { /* not protected */
+                       vu_short *addr = (vu_short *) (info->start[sect]);
+
+                       /* arm simple, non interrupt dependent timer */
+                       reset_timer_masked();
+
+                       MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+                       MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+                       MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+                       MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+                       MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+                       *addr = CMD_ERASE_CONFIRM;
+
+                       /* wait until flash is ready */
+                       while (1) {
+                               result = *addr;
+
+                               /* check timeout */
+                               if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+                                       MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+                                       rc = ERR_TIMOUT;
+                                       break;
+                               }
+
+                               if ((result & 0xfff) & BIT_ERASE_DONE)
+                                       break;
+
+                               if ((result & 0xffff) & BIT_PROGRAM_ERROR) {
+                                       rc = ERR_PROG_ERROR;
+                                       break;
+                               }
+                       }
+
+                       MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+                       if (rc != ERR_OK)
+                               goto out;
+
+                       putc('.');
+               }
+       }
+out:
+       /* allow flash to settle - wait 10 ms */
+       udelay_masked(10000);
+
+       return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_hword(flash_info_t *info, ulong dest, ushort data)
+{
+       vu_short *addr = (vu_short *) dest;
+       ushort result;
+       int rc = ERR_OK;
+
+       /* check if flash is (sufficiently) erased */
+       result = *addr;
+       if ((result & data) != data)
+               return ERR_NOT_ERASED;
+
+       MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+       MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+       MEM_FLASH_ADDR1 = CMD_PROGRAM;
+       *addr = data;
+
+       /* arm simple, non interrupt dependent timer */
+       reset_timer_masked();
+
+       /* wait until flash is ready */
+       while (1) {
+               result = *addr;
+
+               /* check timeout */
+               if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+                       rc = ERR_TIMOUT;
+                       break;
+               }
+
+               if ((result & 0x80) == (data & 0x80))
+                       break;
+
+               if ((result & 0xffff) & BIT_PROGRAM_ERROR) {
+                       result = *addr;
+
+                       if ((result & 0x80) != (data & 0x80))
+                               rc = ERR_PROG_ERROR;
+               }
+       }
+
+       *addr = CMD_READ_ARRAY;
+
+       if (*addr != data)
+               rc = ERR_PROG_ERROR;
+
+       return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+       ulong cp, wp;
+       int l;
+       int i, rc;
+       ushort data;
+
+       wp = (addr & ~1);       /* get lower word aligned address */
+
+       /*
+        * handle unaligned start bytes
+        */
+       if ((l = addr - wp) != 0) {
+               data = 0;
+               for (i = 0, cp = wp; i < l; ++i, ++cp)
+                       data = (data >> 8) | (*(uchar *) cp << 8);
+               for (; i < 2 && cnt > 0; ++i) {
+                       data = (data >> 8) | (*src++ << 8);
+                       --cnt;
+                       ++cp;
+               }
+               for (; cnt == 0 && i < 2; ++i, ++cp)
+                       data = (data >> 8) | (*(uchar *) cp << 8);
+
+               if ((rc = write_hword(info, wp, data)) != 0)
+                       return (rc);
+               wp += 2;
+       }
+
+       /*
+        * handle word aligned part
+        */
+       while (cnt >= 2) {
+               data = *((vu_short *) src);
+               if ((rc = write_hword(info, wp, data)) != 0)
+                       return (rc);
+               src += 2;
+               wp += 2;
+               cnt -= 2;
+       }
+
+       if (cnt == 0)
+               return ERR_OK;
+
+       /*
+        * handle unaligned tail bytes
+        */
+       data = 0;
+       for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+               data = (data >> 8) | (*src++ << 8);
+               --cnt;
+       }
+       for (; i < 2; ++i, ++cp)
+               data = (data >> 8) | (*(uchar *) cp << 8);
+
+       return write_hword(info, wp, data);
+}
+
+#endif

diff --git a/board/netstar/nand.c b/board/netstar/nand.c
new file mode 100644 (file)
index 0000000..f470c1a
--- /dev/null
+++ b/board/netstar/nand.c
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+
+/*
+ *     hardware specific access to control-lines
+ */
+#define        MASK_CLE        0x02
+#define        MASK_ALE        0x04
+
+static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+       struct nand_chip *this = mtd->priv;
+       ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+       IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
+       switch (cmd) {
+               case NAND_CTL_SETCLE: IO_ADDR_W |= MASK_CLE; break;
+               case NAND_CTL_SETALE: IO_ADDR_W |= MASK_ALE; break;
+       }
+       this->IO_ADDR_W = (void *) IO_ADDR_W;
+}
+
+/*
+ *     chip R/B detection
+ */
+/***
+static int netstar_nand_ready(struct mtd_info *mtd)
+{
+       return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02;
+}
+***/
+
+void board_nand_init(struct nand_chip *nand)
+{
+       nand->options = NAND_SAMSUNG_LP_OPTIONS;
+       nand->eccmode = NAND_ECC_SOFT;
+       nand->hwcontrol = netstar_nand_hwcontrol;
+/*     nand->dev_ready = netstar_nand_ready; */
+       nand->chip_delay = 18;
+}
+#endif

diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c
new file mode 100644 (file)
index 0000000..4b7eba1
--- /dev/null
+++ b/board/netstar/netstar.c
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+       /* arch number of NetStar board */
+       /* TODO: use define from asm/mach-types.h */
+       gd->bd->bi_arch_number = 692;
+
+       /* adress of boot parameters */
+       gd->bd->bi_boot_params = 0x10000100;
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+       /* Take the Ethernet controller out of reset and wait
+        * for the EEPROM load to complete. */
+       *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80;
+       udelay(10);     /* doesn't work before interrupt_init call */
+       *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80;
+       udelay(500);
+
+       return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+       return 0;
+}
+
+extern void nand_init(void);
+
+int board_late_init(void)
+{
+       return 0;
+}

diff --git a/board/netstar/setup.S b/board/netstar/setup.S
new file mode 100644 (file)
index 0000000..f67786d
--- /dev/null
+++ b/board/netstar/setup.S
@@ -0,0 +1,287 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004 Ales Jindra <jindra@2n.cz>
+ * (C) Copyright 2005 Ladislav Michl <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+_TEXT_BASE:
+       .word   TEXT_BASE       /* SDRAM load addr from config.mk */
+
+OMAP5910_LPG1_BASE:            .word 0xfffbd000
+OMAP5910_TIPB_SWITCHES_BASE:   .word 0xfffbc800
+OMAP5910_MPU_TC_BASE:          .word 0xfffecc00
+OMAP5910_MPU_CLKM_BASE:                .word 0xfffece00
+OMAP5910_ULPD_PWR_MNG_BASE:    .word 0xfffe0800
+OMAP5910_DPLL1_BASE:           .word 0xfffecf00
+OMAP5910_GPIO_BASE:            .word 0xfffce000
+OMAP5910_MPU_WD_TIMER_BASE:    .word 0xfffec800
+OMAP5910_MPUI_BASE:            .word 0xfffec900
+
+_OMAP5910_ARM_CKCTL:           .word OMAP5910_ARM_CKCTL
+_OMAP5910_ARM_EN_CLK:          .word OMAP5910_ARM_EN_CLK
+
+OMAP5910_MPUI_CTRL:            .word 0x0000ff1b
+
+VAL_EMIFS_CS0_CONFIG:          .word 0x00009090
+VAL_EMIFS_CS1_CONFIG:          .word 0x00003031
+VAL_EMIFS_CS2_CONFIG:          .word 0x0000a0a1
+VAL_EMIFS_CS3_CONFIG:          .word 0x0000c0c0
+VAL_EMIFS_DYN_WAIT:            .word 0x00000000
+/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */
+                               /*     SLRF       SD_RET     ARE        SDRAM_TYPE   ARCV           SDRAM_FREQUENCY PWD     CLK */
+
+#if (PHYS_SDRAM_1_SIZE == SZ_32M)
+VAL_EMIFF_SDRAM_CONFIG:                .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
+#else
+VAL_EMIFF_SDRAM_CONFIG:                .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
+#endif
+
+VAL_EMIFF_SDRAM_CONFIG2:       .word 0x00000003
+VAL_EMIFF_MRS:                 .word 0x00000037
+
+/*
+ * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator)
+ * GPIO07 - LAN91C111 reset
+ */
+GPIO_DIRECTION:
+       .word 0x0000ff6f
+/*
+ * Disable everything (green LED is connected via invertor)
+ */
+GPIO_OUTPUT:
+       .word 0x00000010
+
+MUX_CONFIG_BASE:
+       .word 0xfffe1000
+
+MUX_CONFIG_VALUES:
+       .align 4
+       .word 0x00000000        @ FUNC_MUX_CTRL_0
+       .word 0x00000000        @ FUNC_MUX_CTRL_1
+       .word 0x00000000        @ FUNC_MUX_CTRL_2
+       .word 0x00000000        @ FUNC_MUX_CTRL_3
+       .word 0x00000000        @ FUNC_MUX_CTRL_4
+       .word 0x02080480        @ FUNC_MUX_CTRL_5
+       .word 0x0100001c        @ FUNC_MUX_CTRL_6
+       .word 0x0004800b        @ FUNC_MUX_CTRL_7
+       .word 0x10001200        @ FUNC_MUX_CTRL_8
+       .word 0x01201012        @ FUNC_MUX_CTRL_9
+       .word 0x02082248        @ FUNC_MUX_CTRL_A
+       .word 0x00000248        @ FUNC_MUX_CTRL_B
+       .word 0x12240000        @ FUNC_MUX_CTRL_C
+       .word 0x00002000        @ FUNC_MUX_CTRL_D
+       .word 0x00000000        @ PULL_DWN_CTRL_0
+       .word 0x00000800        @ PULL_DWN_CTRL_1
+       .word 0x01801000        @ PULL_DWN_CTRL_2
+       .word 0x00000000        @ PULL_DWN_CTRL_3
+       .word 0x00000000        @ GATE_INH_CTRL_0
+       .word 0x00000000        @ VOLTAGE_CTRL_0
+       .word 0x00000000        @ TEST_DBG_CTRL_0
+       .word 0x00000006        @ MOD_CONF_CTRL_0
+       .word 0x0000eaef        @ COMP_MODE_CTRL_0
+
+MUX_CONFIG_OFFSETS:
+       .align 1
+       .byte 0x00              @ FUNC_MUX_CTRL_0
+       .byte 0x04              @ FUNC_MUX_CTRL_1
+       .byte 0x08              @ FUNC_MUX_CTRL_2
+       .byte 0x10              @ FUNC_MUX_CTRL_3
+       .byte 0x14              @ FUNC_MUX_CTRL_4
+       .byte 0x18              @ FUNC_MUX_CTRL_5
+       .byte 0x1c              @ FUNC_MUX_CTRL_6
+       .byte 0x20              @ FUNC_MUX_CTRL_7
+       .byte 0x24              @ FUNC_MUX_CTRL_8
+       .byte 0x28              @ FUNC_MUX_CTRL_9
+       .byte 0x2c              @ FUNC_MUX_CTRL_A
+       .byte 0x30              @ FUNC_MUX_CTRL_B
+       .byte 0x34              @ FUNC_MUX_CTRL_C
+       .byte 0x38              @ FUNC_MUX_CTRL_D
+       .byte 0x40              @ PULL_DWN_CTRL_0
+       .byte 0x44              @ PULL_DWN_CTRL_1
+       .byte 0x48              @ PULL_DWN_CTRL_2
+       .byte 0x4c              @ PULL_DWN_CTRL_3
+       .byte 0x50              @ GATE_INH_CTRL_0
+       .byte 0x60              @ VOLTAGE_CTRL_0
+       .byte 0x70              @ TEST_DBG_CTRL_0
+       .byte 0x80              @ MOD_CONF_CTRL_0
+       .byte 0x0c              @ COMP_MODE_CTRL_0
+       .byte 0xff
+
+.globl lowlevel_init
+lowlevel_init:
+       /* Improve performance a bit... */
+       mrc     p15, 0, r1, c0, c0, 0           @ read C15 ID register
+       mrc     p15, 0, r1, c0, c0, 1           @ read C15 Cache information register
+       mrc     p15, 0, r1, c1, c0, 0           @ read C15 Control register
+       orr     r1, r1, #0x1000                 @ enable I-cache, map interrupt vector 0xffff0000
+       mcr     p15, 0, r1, c1, c0, 0           @ write C15 Control register
+       mov     r1, #0x00
+       mcr     p15, 0, r1, c7, c5, 0           @ Flush I-cache
+       nop
+       nop
+       nop
+       nop
+
+       /* Setup clocking mode */
+       ldr     r0, OMAP5910_MPU_CLKM_BASE      @ prepare base of CLOCK unit
+       ldrh    r1, [r0, #0x18]                 @ get reset status
+       bic     r1, r1, #(7 << 11)              @ clear clock select
+       orr     r1, r1, #(2 << 11)              @ set synchronous scalable
+       mov     r2, #0                          @ set wait counter to 100 clock cycles
+
+icache_loop:
+       cmp     r2, #0x01
+       streqh  r1, [r0, #0x18]
+       add     r2, r2, #0x01
+       cmp     r2, #0x10
+       bne     icache_loop
+       nop
+
+       /* Setup clock divisors */
+       ldr     r0, OMAP5910_MPU_CLKM_BASE      @ base of CLOCK unit
+       ldr     r1, _OMAP5910_ARM_CKCTL
+       orr     r1, r1, #0x2000                 @ enable DSP clock
+       strh    r1, [r0, #0x00]                 @ setup clock divisors
+
+       /* Setup DPLL to generate requested freq */
+       ldr     r0, OMAP5910_DPLL1_BASE         @ base of DPLL1 register
+       mov     r1, #0x0010                     @ set PLL_ENABLE
+       orr     r1, r1, #0x2000                 @ set IOB to new locking
+       orr     r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
+       orr     r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
+       strh    r1, [r0]                        @ write
+
+locking:
+       ldrh    r1, [r0]                        @ get DPLL value
+       tst     r1, #0x01
+       beq     locking                         @ while LOCK not set
+
+       /* Enable clock */
+       ldr     r0, OMAP5910_MPU_CLKM_BASE      @ base of CLOCK unit
+       mov     r1, #(1 << 10)                  @ disable idle mode do not check
+                                               @ nWAKEUP pin, other remain active
+       strh    r1, [r0, #0x04]
+       ldr     r1, _OMAP5910_ARM_EN_CLK
+       strh    r1, [r0, #0x08]
+       mov     r1, #0x003f                     @ FLASH.RP not enabled in idle and
+                                               @ max delayed ( 32 x CLKIN )
+       strh    r1, [r0, #0x0c]
+
+       /* Configure 5910 pins functions to match our board. */
+       ldr     r0, MUX_CONFIG_BASE
+       adr     r1, MUX_CONFIG_VALUES
+       adr     r2, MUX_CONFIG_OFFSETS
+next_mux_cfg:
+       ldrb    r3, [r2], #1
+       ldr     r4, [r1], #4
+       cmp     r3, #0xff
+       strne   r4, [r0, r3]
+       bne     next_mux_cfg
+
+       /* Configure GPIO pins (also disables Green LED) */
+       ldr     r0, OMAP5910_GPIO_BASE
+       ldr     r1, GPIO_OUTPUT
+       strh    r1, [r0, #0x04]
+       ldr     r1, GPIO_DIRECTION
+       strh    r1, [r0, #0x08]
+
+       /* EnablePeripherals */
+       ldr     r0, OMAP5910_MPU_CLKM_BASE      @ CLOCK unit
+       mov     r1, #0x0001                     @ Peripheral enable
+       strh    r1, [r0, #0x14]
+
+       /* Program LED Pulse Generator */
+       ldr     r0, OMAP5910_LPG1_BASE          @ 1st LED Pulse Generator
+       mov     r1, #0x7F                       @ Set obscure frequency in
+       strb    r1, [r0, #0x00]                 @ LCR
+       mov     r1, #0x01                       @ Enable clock (CLK_EN) in
+       strb    r1, [r0, #0x04]                 @ PMR
+
+       /* TIPB Lock UART1 */
+       ldr     r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches
+       mov     r1, #1                          @ ARM allocated
+       strh    r1, [r0,#0x04]                  @ clear IRQ line and status bits
+       strh    r1, [r0,#0x00]
+       ldrh    r1, [r0,#0x04]
+
+       /* Disable watchdog */
+       ldr     r0, OMAP5910_MPU_WD_TIMER_BASE
+       mov     r1, #0xf5
+       strh    r1, [r0, #0x8]
+       mov     r1, #0xa0
+       strh    r1, [r0, #0x8]
+
+       /* Enable MCLK */
+       ldr     r0, OMAP5910_ULPD_PWR_MNG_BASE
+       mov     r1, #0x6
+       strh    r1, [r0, #0x34]
+       strh    r1, [r0, #0x34]
+
+       /* Setup clock divisors */
+       ldr     r0, OMAP5910_ULPD_PWR_MNG_BASE  @ base of ULDPL DPLL1 register
+
+       mov     r1, #0x0010                     @ set PLL_ENABLE
+       orr     r1, r1, #0x2000                 @ set IOB to new locking
+       strh    r1, [r0]                        @ write
+
+ulocking:
+       ldrh    r1, [r0]                        @ get DPLL value
+       tst     r1, #1
+       beq     ulocking                        @ while LOCK not set
+
+       /* EMIF init */
+       ldr     r0, OMAP5910_MPU_TC_BASE
+       ldrh    r1, [r0, #0x0c]                 @ EMIFS_CONFIG_REG
+       bic     r1, r1, #0x0c                   @ pwr down disabled, flash WP
+       orr     r1, r1, #0x01
+       str     r1, [r0, #0x0c]
+
+       ldr     r1, VAL_EMIFS_CS0_CONFIG
+       str     r1, [r0, #0x10]                 @ EMIFS_CS0_CONFIG
+       ldr     r1, VAL_EMIFS_CS1_CONFIG
+       str     r1, [r0, #0x14]                 @ EMIFS_CS1_CONFIG
+       ldr     r1, VAL_EMIFS_CS2_CONFIG
+       str     r1, [r0, #0x18]                 @ EMIFS_CS2_CONFIG
+       ldr     r1, VAL_EMIFS_CS3_CONFIG
+       str     r1, [r0, #0x1c]                 @ EMIFS_CS3_CONFIG
+       ldr     r1, VAL_EMIFS_DYN_WAIT
+       str     r1, [r0, #0x40]                 @ EMIFS_CFG_DYN_WAIT
+
+       /* Setup SDRAM */
+       ldr     r1, VAL_EMIFF_SDRAM_CONFIG
+       str     r1, [r0, #0x20]                 @ EMIFF_SDRAM_CONFIG
+       ldr     r1, VAL_EMIFF_SDRAM_CONFIG2
+       str     r1, [r0, #0x3c]                 @ EMIFF_SDRAM_CONFIG2
+       ldr     r1, VAL_EMIFF_MRS
+       str     r1, [r0, #0x24]                 @ EMIFF_MRS
+       /* SDRAM needs 100us to stabilize */
+       mov     r0, #0x4000
+sdelay:
+       subs    r0, r0, #0x1
+       bne     sdelay
+
+       /* back to arch calling code */
+       mov     pc, lr
+.end

diff --git a/board/netstar/u-boot.lds b/board/netstar/u-boot.lds
new file mode 100644 (file)
index 0000000..8317f72
--- /dev/null
+++ b/board/netstar/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text      :
+       {
+         cpu/arm925t/start.o   (.text)
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data : { *(.data) }
+
+       . = ALIGN(4);
+       .got : { *(.got) }
+
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       __bss_start = .;
+       .bss : { *(.bss) }
+       _end = .;
+}

diff --git a/board/netta/netta.c b/board/netta/netta.c
index 9194bfb9de37dd3e92de4e04b1746351068bbeac..4923e3addafbfce87b9e7a41e4c606d1bec4cd03 100644 (file)
--- a/board/netta/netta.c
+++ b/board/netta/netta.c
@@ -555,9 +555,9 @@ int board_early_init_f(void)
        return 0;
 }
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
 
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 
 extern ulong nand_probe(ulong physadr);
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c
index c9b405145e5918d919a3f2f62d2680a68c7be76b..3ca7bd3c8677e86321d68a417a2e56ea2b17ee02 100644 (file)
--- a/board/netta2/netta2.c
+++ b/board/netta2/netta2.c
@@ -597,7 +597,7 @@ int board_early_init_f(void)
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 
 extern ulong nand_probe(ulong physadr);
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c
index fb7f7700cffc98ce9e75d4e16f0e8c80179120d3..3e6c61663f202deb232cb831a32f56cd6f51c0d5 100644 (file)
--- a/board/netvia/netvia.c
+++ b/board/netvia/netvia.c
@@ -418,7 +418,7 @@ int board_early_init_f(void)
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 
 extern ulong nand_probe(ulong physadr);
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

diff --git a/board/ns9750dev/ns9750dev.c b/board/ns9750dev/ns9750dev.c
index ea00d5af2593683d0c8174504cd2092a4d295e09..1dd348a0c3045eb89fefeb5f53757f46138f2e26 100644 (file)
--- a/board/ns9750dev/ns9750dev.c
+++ b/board/ns9750dev/ns9750dev.c
@@ -41,6 +41,8 @@
 # include <./ns9750_bbus.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void flash__init( void );
 void ether__init( void );
 
@@ -60,8 +62,6 @@ static inline void delay( unsigned long loops )
 
 int board_init( void )
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Active BBUS modules */
        *get_bbus_reg_addr( NS9750_BBUS_MASTER_RESET ) = 0;
 
@@ -114,8 +114,6 @@ void ether__init (void)
 ******************************/
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c
index 65d45c197f0053cc6ad9c4c1d4ca036a818f9167..4a426ec4980326ed96df67b9811df5963fb9a91d 100644 (file)
--- a/board/nx823/nx823.c
+++ b/board/nx823/nx823.c
@@ -28,12 +28,10 @@
 #include <malloc.h>
 #include <mpc8xx.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
 
 static long int dram_size (long int, long int *, long int);
 
-/* ------------------------------------------------------------------------- */
-
 #define        _NOT_USED_      0xFFFFFFFF
 
 const uint sdram_table[] = {
@@ -366,8 +364,6 @@ u_long *my_sernum;
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        char tmp[50];
        u_char *e = gd->bd->bi_enetaddr;
 
@@ -387,8 +383,6 @@ int misc_init_r (void)
 
 void load_sernum_ethaddr (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int i;
        bd_t *bd = gd->bd;
 

diff --git a/board/omap1510inn/omap1510innovator.c b/board/omap1510inn/omap1510innovator.c
index f037f42d4198a1bc7549d80b5941f8351feb5c05..894120951021397f61f8813d5d0f6698b1f0eb13 100644 (file)
--- a/board/omap1510inn/omap1510innovator.c
+++ b/board/omap1510inn/omap1510innovator.c
@@ -31,6 +31,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static void flash__init (void);
 static void ether__init (void);
 
@@ -47,8 +49,6 @@ static inline void delay (unsigned long loops)
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* arch number of OMAP 1510-Board */
        gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
 
@@ -122,8 +122,6 @@ static void ether__init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/omap1610inn/omap1610innovator.c b/board/omap1610inn/omap1610innovator.c
index 78425181e894f7d0c21d1492f5bf21068bb70f03..8dbe686a8913214bfc0d7b9fa8602d0f51b72b6e 100644 (file)
--- a/board/omap1610inn/omap1610innovator.c
+++ b/board/omap1610inn/omap1610innovator.c
@@ -36,6 +36,8 @@
 #include <./configs/omap1510.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_CS_AUTOBOOT
 unsigned long omap_flash_base;
 #endif
@@ -60,8 +62,6 @@ static inline void delay (unsigned long loops)
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (machine_is_omap_h2())
                gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2;
        else if (machine_is_omap_innovator())
@@ -153,8 +153,6 @@ void ether__init (void)
 ******************************/
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c
index 6ae1a490a500424ba1d198104028b3cdc91c612f..f7f75e0fe1a2a3162f1a98ff4d8274572553efbb 100644 (file)
--- a/board/omap2420h4/omap2420h4.c
+++ b/board/omap2420h4/omap2420h4.c
@@ -32,11 +32,13 @@
 #include <i2c.h>
 #include <asm/mach-types.h>
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 #endif
 
- void wait_for_command_complete(unsigned int wd_base);
+DECLARE_GLOBAL_DATA_PTR;
+
+void wait_for_command_complete(unsigned int wd_base);
 
 /*******************************************************
  * Routine: delay
@@ -54,8 +56,6 @@ static inline void delay (unsigned long loops)
  *****************************************/
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gpmc_init(); /* in SRAM or SDRM, finish GPMC */
 
        gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4;             /* board id for linux */
@@ -195,7 +195,6 @@ void ether_init (void)
  **********************************************/
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned int size0=0,size1=0;
        u32 mtype, btype, rev, cpu;
        u8 chg_on = 0x5; /* enable charge of back up battery */

diff --git a/board/omap5912osk/omap5912osk.c b/board/omap5912osk/omap5912osk.c
index 1faa084f94ef84bb50b7f73231cbfcab434f7842..e9e6b0e794dc54c8f5b924677f3982782c1334ce 100644 (file)
--- a/board/omap5912osk/omap5912osk.c
+++ b/board/omap5912osk/omap5912osk.c
@@ -38,6 +38,8 @@
 #include <./configs/omap1510.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void flash__init (void);
 void ether__init (void);
 void set_muxconf_regs (void);
@@ -58,8 +60,6 @@ static inline void delay (unsigned long loops)
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_arch_number = MACH_TYPE_OMAP_OSK;
 
        /* adress of boot parameters */
@@ -136,8 +136,6 @@ void ether__init (void)
 ******************************/
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/omap730p2/omap730p2.c b/board/omap730p2/omap730p2.c
index 256c6a665d8eb41a2c36b9c16f9b21f75696778d..309d667585abfd3cadc0559b6d0d0ca8a79f9aa1 100644 (file)
--- a/board/omap730p2/omap730p2.c
+++ b/board/omap730p2/omap730p2.c
@@ -34,6 +34,8 @@
 #include <./configs/omap730.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int test_boot_mode(void);
 void spin_up_leds(void);
 void flash__init (void);
@@ -84,8 +86,6 @@ void toggle_backup_led(void)
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* arch number of OMAP 730 P2 Board - Same as the Innovator! */
        gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2;
 
@@ -180,8 +180,6 @@ void ether__init (void)
 ******************************/
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/oxc/oxc.c b/board/oxc/oxc.c
index fa7ff0215c01bb7a2fdaa14ecb8a6e8e019cb3ce..6cc3cc5a3e48e7e45da7404541a150b82d1598db 100644 (file)
--- a/board/oxc/oxc.c
+++ b/board/oxc/oxc.c
@@ -26,6 +26,8 @@
 #include <pci.h>
 #include <i2c.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard (void)
 {
        puts (  "Board: OXC8240\n" );
@@ -184,8 +186,6 @@ int misc_init_r (void)
 
 #ifdef CFG_OXC_GENERATE_IP
        {
-               DECLARE_GLOBAL_DATA_PTR;
-
                char str[32];
                unsigned long ip = CFG_OXC_IPMASK;
                bd_t *bd = gd->bd;

diff --git a/board/pcippc2/fpga_serial.c b/board/pcippc2/fpga_serial.c
index 579bfc702744978cf5af2b80772bcbe741c2d1d9..5f89d9b125e105d71aa2e968cba8459cc28f2983 100644 (file)
--- a/board/pcippc2/fpga_serial.c
+++ b/board/pcippc2/fpga_serial.c
@@ -29,6 +29,8 @@
 #include "hardware.h"
 #include "pcippc2.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
   /* 8 data, 1 stop, no parity
    */
 #define LCRVAL         0x03
@@ -92,8 +94,6 @@ int fpga_serial_tstc (void)
 
 void fpga_serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int clock_divisor = 115200 / gd->baudrate;
 
        fpga_serial_wait ();

diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c
index 231b50576b38c9e7d6888e9528028d65d7339357..a216c55bc6ad149be937e92d0fb4a9a92b0933e3 100644 (file)
--- a/board/pcippc2/pcippc2.c
+++ b/board/pcippc2/pcippc2.c
@@ -34,6 +34,8 @@
 #include "sconsole.h"
 #include "fpga_serial.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_WATCHDOG)
 
 static int pcippc2_wdt_init_done = 0;
@@ -108,8 +110,6 @@ int board_early_init_f (void)
 
 void after_reloc (ulong dest_addr)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Jump to the main U-Boot board init code
         */
        board_init_r ((gd_t *)gd, dest_addr);

diff --git a/board/pcippc2/sconsole.c b/board/pcippc2/sconsole.c
index a9f2b298116a8d68f9fbda2ac6f85e0c427d10de..3b190699f08557a9f79c40a658fb7969ec1b7a92 100644 (file)
--- a/board/pcippc2/sconsole.c
+++ b/board/pcippc2/sconsole.c
@@ -26,6 +26,8 @@
 
 #include "sconsole.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void   (*sconsole_putc) (char) = 0;
 void   (*sconsole_puts) (const char *) = 0;
 int    (*sconsole_getc) (void) = 0;
@@ -34,8 +36,6 @@ void  (*sconsole_setbrg) (void) = 0;
 
 int serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        sconsole_buffer_t *sb = SCONSOLE_BUFFER;
 
        sb->pos  = 0;
@@ -104,8 +104,6 @@ int serial_tstc (void)
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (sconsole_setbrg) {
                (*sconsole_setbrg) ();
        } else {

diff --git a/board/pleb2/pleb2.c b/board/pleb2/pleb2.c
index ce9245cd4e31744459a28b4b660ea9887f507a57..dc6fac46d344defa18eaaecef29fd7c7c297bc1b 100644 (file)
--- a/board/pleb2/pleb2.c
+++ b/board/pleb2/pleb2.c
@@ -28,8 +28,7 @@
 #include <common.h>
 #include <asm-arm/mach-types.h>
 
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -37,8 +36,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* memory and cpu-speed are setup before relocation */
        /* so we do _nothing_ here */
 
@@ -61,8 +58,6 @@ int board_late_init(void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c
index d4cc5cb56170131aa137a8b300c6bda3b71d597d..65c529192a649782bd9f3715476a9ba1ec670b1c 100644 (file)
--- a/board/pm520/pm520.c
+++ b/board/pm520/pm520.c
@@ -34,6 +34,8 @@
 #include "mt48lc16m16a2-75.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CFG_RAMBOOT
 static void sdram_start (int hi_addr)
 {
@@ -281,7 +283,6 @@ extern flash_info_t flash_info[];   /* info for FLASH chips */
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        /* adjust flash start */
        gd->bd->bi_flashstart = flash_info[0].start[0];
        return (0);

diff --git a/board/pn62/pn62.c b/board/pn62/pn62.c
index 377aaa8bca3a48dda99a4a98413ba35931e1df66..b2f348d4d6d5b24d101d831a1f279c0a34bb5c22 100644 (file)
--- a/board/pn62/pn62.c
+++ b/board/pn62/pn62.c
@@ -26,6 +26,7 @@
 
 #include "pn62.h"
 
+DECLARE_GLOBAL_DATA_PTR;
 
 static int get_serial_number (char *string, int size);
 static int get_mac_address (int id, u8 * mac, char *string, int size);
@@ -122,8 +123,6 @@ void pci_init_board (void)
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        char str[20];
        u8 mac[6];
 

diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
index d42a643c2f0d2de21a0a9123c88a40b9bdde8b19..2f28e9d87a3477f3f8b9b2d716b4a575dff8da42 100644 (file)
--- a/board/prodrive/p3p440/p3p440.c
+++ b/board/prodrive/p3p440/p3p440.c
@@ -29,6 +29,8 @@
 
 #include "p3p440.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void set_led(int color)
 {
        switch (color) {
@@ -141,8 +143,6 @@ int checkboard(void)
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /*
         * Adjust flash start and offset to detected values
         */
@@ -206,8 +206,6 @@ int pci_pre_init(struct pci_controller *hose)
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/

diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
index d5b993ae5518341bad1a1e8f2ba6e0eba3853cc0..5765c5532a4d59cb2958bce95ecc888efdae3b0a 100644 (file)
--- a/board/pxa255_idp/pxa_idp.c
+++ b/board/pxa255_idp/pxa_idp.c
@@ -33,8 +33,7 @@
 #include <common.h>
 #include <command.h>
 
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -42,8 +41,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* memory and cpu-speed are setup before relocation */
        /* so we do _nothing_ here */
 
@@ -86,8 +83,6 @@ int board_late_init(void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

diff --git a/board/quantum/quantum.c b/board/quantum/quantum.c
index 2861bc3b166325274d121054e561e6e78ac28d11..afa6e113d828f771780159949b3f78ed623f145c 100644 (file)
--- a/board/quantum/quantum.c
+++ b/board/quantum/quantum.c
@@ -170,14 +170,14 @@ static long int dram_size (long int mamr_value, long int *base,
        memctl->memc_mamr = mamr_value;
 
        for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
-               addr = base + cnt;      /* pointer arith! */
+               addr = (volatile ulong *)(base + cnt);  /* pointer arith! */
 
                save[i++] = *addr;
                *addr = ~cnt;
        }
 
        /* write 0 to base address */
-       addr = base;
+       addr = (volatile ulong *)base;
        save[i] = *addr;
        *addr = 0;
 
@@ -194,7 +194,7 @@ static long int dram_size (long int mamr_value, long int *base,
        }
 
        for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
-               addr = base + cnt;      /* pointer arith! */
+               addr = (volatile ulong *)(base + cnt);  /* pointer arith! */
 
                val = *addr;
                *addr = save[--i];

diff --git a/board/rbc823/kbd.c b/board/rbc823/kbd.c
index c27929dcd3c93f59aef9299f890b5339b1af44f5..6d530f6b431cf9d16fc023e2365ba23a74244e06 100644 (file)
--- a/board/rbc823/kbd.c
+++ b/board/rbc823/kbd.c
@@ -33,6 +33,8 @@
 #include <devices.h>
 #include <lcd.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define        SMC_INDEX       0
 #define PROFF_SMC      PROFF_SMC1
 #define CPM_CR_CH_SMC  CPM_CR_CH_SMC1
@@ -46,8 +48,6 @@
 
 void smc1_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *im = (immap_t *)CFG_IMMR;
        volatile cpm8xx_t *cp = &(im->im_cpm);
 

diff --git a/board/sacsng/clkinit.c b/board/sacsng/clkinit.c
index ea4c65d6b34fb007b7a6a42c7611b4cea0f95eea..edb775df2ea057ea30a4726bfd396b66d80ea778 100644 (file)
--- a/board/sacsng/clkinit.c
+++ b/board/sacsng/clkinit.c
@@ -30,6 +30,8 @@
 
 #include "clkinit.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int Daq64xSampling = 0;
 
 
@@ -257,7 +259,6 @@ void Daq_BRG_Set_ExtClk(uint brg, uint extc)
 
 uint Daq_BRG_Rate(uint brg)
 {
-     DECLARE_GLOBAL_DATA_PTR;
      volatile immap_t *immr = (immap_t *)CFG_IMMR;
      uint *brg_ptr;
      uint brg_cnt;
@@ -295,7 +296,6 @@ uint Daq_Get_SampleRate(void)
 
 void Daq_Init_Clocks(int sample_rate, int sample_64x)
 {
-    DECLARE_GLOBAL_DATA_PTR;
     volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
     uint mclk_divisor; /* MCLK divisor */
     int  flag;         /* Interrupt state */

diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c
index 353041667f2333be6eaaedc2a535077247b9fa12..781647251683d574e6f4b17c1692c76e03eacea1 100644 (file)
--- a/board/sandburst/common/sb_common.c
+++ b/board/sandburst/common/sb_common.c
@@ -29,6 +29,8 @@
 #include "ppc440gx_i2c.h"
 #include "sb_common.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 long int fixed_sdram (void);
 
 /*************************************************************************
@@ -203,7 +205,7 @@ long int initdram (int board_type)
        long dram_size = 0;
 
 #if defined(CONFIG_SPD_EEPROM)
-       dram_size = spd_sdram (0);
+       dram_size = spd_sdram ();
 #else
        dram_size = fixed_sdram ();
 #endif
@@ -341,8 +343,6 @@ int pci_pre_init(struct pci_controller * hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/

diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c
index cad58731d3e812ee02495c1a767c7b9fedfb049c..0ae6d0ba4558a175379887d2165d821e065d6d57 100644 (file)
--- a/board/sbc405/sbc405.c
+++ b/board/sbc405/sbc405.c
@@ -98,7 +98,7 @@ int checkboard (void)
 
 long int initdram (int board_type)
 {
-       return  spd_sdram (0);
+       return  spd_sdram ();
 }
 
 /* ------------------------------------------------------------------------- */

diff --git a/board/sbc8240/sbc8240.c b/board/sbc8240/sbc8240.c
index a6d3babe92942ec87dfaf625c80327c15d75726d..8a52f67418090a4899f53de22ede19966386cb41 100644 (file)
--- a/board/sbc8240/sbc8240.c
+++ b/board/sbc8240/sbc8240.c
@@ -29,12 +29,12 @@
 #include <asm/processor.h>
 #include <pci.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define BOARD_REV_REG 0xFE80002B
 
 int checkboard (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        char  revision = *(volatile char *)(BOARD_REV_REG);
        char  buf[32];
 

diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c
index cd523248268556ef0f7bbbea46cac1d91a89c846..b6add59bb482dd14363eea6f3030c325854bdb1b 100644 (file)
--- a/board/sc520_cdp/sc520_cdp.c
+++ b/board/sc520_cdp/sc520_cdp.c
@@ -30,6 +30,8 @@
 #include <asm/ic/ali512x.h>
 #include <spi.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef SC520_CDP_DEBUG
 
 #ifdef SC520_CDP_DEBUG
@@ -481,8 +483,6 @@ int pci_enable_legacy_video_ports(struct pci_controller *hose)
 
 int board_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        init_sc520();
        bus_init();
        irq_init();

diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c
index e7a7d5188cfdc7fb079de7ce06906a49ce5effaa..ed226fd6423ee68d7deb1a14ef844cd2f7a948bb 100644 (file)
--- a/board/sc520_spunk/sc520_spunk.c
+++ b/board/sc520_spunk/sc520_spunk.c
@@ -29,9 +29,7 @@
 #include <asm/pci.h>
 #include <asm/ic/sc520.h>
 
-
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Theory:
@@ -483,8 +481,6 @@ int pci_enable_legacy_video_ports(struct pci_controller *hose)
 
 int board_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        init_sc520();
        bus_init();
        irq_init();

diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c
index 3ed8753e210e8851dab89af06aad92a57ee30cb7..3f6831be5e50ab8b4062150c791b59e075dd6dc2 100644 (file)
--- a/board/scb9328/scb9328.c
+++ b/board/scb9328/scb9328.c
@@ -20,42 +20,41 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 # define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
 #else
 # define SHOW_BOOT_PROGRESS(arg)
 #endif
 
-int board_init( void ){
-  DECLARE_GLOBAL_DATA_PTR;
-
-  gd->bd->bi_arch_number = MACH_TYPE_SCB9328;
-  gd->bd->bi_boot_params = 0x08000100;
+int board_init (void)
+{
+       gd->bd->bi_arch_number = MACH_TYPE_SCB9328;
+       gd->bd->bi_boot_params = 0x08000100;
 
-  return 0;
+       return 0;
 }
 
-int dram_init( void ){
-  DECLARE_GLOBAL_DATA_PTR;
-
+int dram_init (void)
+{
 #if ( CONFIG_NR_DRAM_BANKS > 0 )
-  gd->bd->bi_dram[0].start = SCB9328_SDRAM_1;
-  gd->bd->bi_dram[0].size  = SCB9328_SDRAM_1_SIZE;
+       gd->bd->bi_dram[0].start = SCB9328_SDRAM_1;
+       gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE;
 #endif
 #if ( CONFIG_NR_DRAM_BANKS > 1 )
-  gd->bd->bi_dram[1].start = SCB9328_SDRAM_2;
-  gd->bd->bi_dram[1].size  = SCB9328_SDRAM_2_SIZE;
+       gd->bd->bi_dram[1].start = SCB9328_SDRAM_2;
+       gd->bd->bi_dram[1].size = SCB9328_SDRAM_2_SIZE;
 #endif
 #if ( CONFIG_NR_DRAM_BANKS > 2 )
-  gd->bd->bi_dram[2].start = SCB9328_SDRAM_3;
-  gd->bd->bi_dram[2].size  = SCB9328_SDRAM_3_SIZE;
+       gd->bd->bi_dram[2].start = SCB9328_SDRAM_3;
+       gd->bd->bi_dram[2].size = SCB9328_SDRAM_3_SIZE;
 #endif
 #if ( CONFIG_NR_DRAM_BANKS > 3 )
-  gd->bd->bi_dram[3].start = SCB9328_SDRAM_4;
-  gd->bd->bi_dram[3].size  = SCB9328_SDRAM_4_SIZE;
+       gd->bd->bi_dram[3].start = SCB9328_SDRAM_4;
+       gd->bd->bi_dram[3].size = SCB9328_SDRAM_4_SIZE;
 #endif
-
-  return 0;
+       return 0;
 }
 
 /**

diff --git a/board/shannon/flash.c b/board/shannon/flash.c
index 13c01d8351af6d16306cbef04cb9dd5c9b653f56..475b76b30bdcafee719199c02c917e712f8cbcb8 100644 (file)
--- a/board/shannon/flash.c
+++ b/board/shannon/flash.c
@@ -315,7 +315,7 @@ outahere:
  * Copy memory to flash
  */
 
-volatile static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word (flash_info_t *info, ulong dest, ulong data)
 {
     vu_long *addr = (vu_long *)dest;
     ulong result;

diff --git a/board/shannon/shannon.c b/board/shannon/shannon.c
index 0d9f146d5224ffe59a080d6a585266bb5a03ea79..8cd1fc34c63b5f235ed34cfc25948aa039ee38ae 100644 (file)
--- a/board/shannon/shannon.c
+++ b/board/shannon/shannon.c
@@ -24,8 +24,7 @@
 
 #include <common.h>
 
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -33,8 +32,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* memory and cpu-speed are setup before relocation */
        /* but if we use InfernoLoader, we must do some inits here */
 
@@ -75,7 +72,6 @@ int dram_init (void)
 {
 #if defined(PHYS_SDRAM_1) || defined(PHYS_SDRAM_2) || \
     defined(PHYS_SDRAM_3) || defined(PHYS_SDRAM_4)
-       DECLARE_GLOBAL_DATA_PTR;
        bd_t *bd = gd->bd;
 #endif
 

diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c
index d20688d5687133d8677c784f0e95070eebb96a92..8783aafe9a124a16797f4275747572409f97f974 100644 (file)
--- a/board/siemens/SCM/scm.c
+++ b/board/siemens/SCM/scm.c
@@ -27,6 +27,8 @@
 
 #include "scm.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static void config_scoh_cs(void);
 extern int  fpga_init(void);
 
@@ -300,8 +302,6 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
  */
 int power_on_reset (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Test Reset Status Register */
        return gd->reset_status & RSR_CSRS ? 0 : 1;
 }

diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c
index 867589f918e36da26cd8bd7b81ac89d1689e744c..a4cb4dcf09772230823daa27fa798362f5db3a5a 100644 (file)
--- a/board/sixnet/sixnet.c
+++ b/board/sixnet/sixnet.c
@@ -34,10 +34,12 @@
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define ORMASK(size) ((-size) & OR_AM_MSK)
 
 static long ram_size(ulong *, long);
@@ -256,8 +258,6 @@ int board_postclk_init (void)
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t     *immap = (immap_t *)CFG_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
        char* s;

diff --git a/board/smdk2400/flash.c b/board/smdk2400/flash.c
index a108af7c7296864a1e3bf23ff0928886a694e4c0..fd9992d366ad8be73fef38cece2741da35f414cb 100644 (file)
--- a/board/smdk2400/flash.c
+++ b/board/smdk2400/flash.c
@@ -353,8 +353,7 @@ outahere:
  * Copy memory to flash
  */
 
-volatile static int write_word (flash_info_t * info, ulong dest,
-                                                               ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
        vu_long *addr = (vu_long *) dest;
        ulong result;

diff --git a/board/smdk2400/smdk2400.c b/board/smdk2400/smdk2400.c
index cb70218434be15a05a4340a31660d5ef10516d6a..4d1f1a63cd3a711833bc79d9e795ca4095260ea2 100644 (file)
--- a/board/smdk2400/smdk2400.c
+++ b/board/smdk2400/smdk2400.c
@@ -28,7 +28,7 @@
 #include <common.h>
 #include <s3c2400.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_MODEM_SUPPORT
 static int key_pressed(void);
@@ -45,7 +45,6 @@ extern int do_mdm_init; /* defined in common/main.c */
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 
@@ -94,8 +93,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/smdk2410/smdk2410.c b/board/smdk2410/smdk2410.c
index 9623aeff32b8881929f3ceee7c98bad103a71bd1..802348d23693f8ef25a4fe1299f3908848eb2df3 100644 (file)
--- a/board/smdk2410/smdk2410.c
+++ b/board/smdk2410/smdk2410.c
@@ -28,7 +28,7 @@
 #include <common.h>
 #include <s3c2410.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
 
 #define FCLK_SPEED 1
 
@@ -67,7 +67,6 @@ static inline void delay (unsigned long loops)
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 
@@ -117,8 +116,6 @@ int board_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/stamp/Makefile b/board/stamp/Makefile
new file mode 100644 (file)
index 0000000..ab97e1b
--- /dev/null
+++ b/board/stamp/Makefile
@@ -0,0 +1,68 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   = $(BOARD).o stamp.o
+SOBJS  =
+
+$(LIB):        .depend $(OBJS)
+       $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

diff --git a/board/stamp/config.mk b/board/stamp/config.mk
new file mode 100644 (file)
index 0000000..0d00730
--- /dev/null
+++ b/board/stamp/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x07FC0000
+PLATFORM_CPPFLAGS += -I$(TOPDIR)

diff --git a/board/stamp/stamp.c b/board/stamp/stamp.c
new file mode 100644 (file)
index 0000000..7e3af20
--- /dev/null
+++ b/board/stamp/stamp.c
@@ -0,0 +1,276 @@
+/*
+ * U-boot - stamp.c STAMP board specific routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mem_init.h>
+#include "stamp.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define STATUS_LED_OFF 0
+#define STATUS_LED_ON  1
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# define SHOW_BOOT_PROGRESS(arg)       show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+int checkboard (void)
+{
+       printf ("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
+       printf ("Board: ADI BF533 Stamp board\n");
+       printf ("       Support: http://blackfin.uclinux.org/\n");
+       printf ("       Richard Klingler <richard@uclinux.net>\n");
+       return 0;
+}
+
+long int initdram (int board_type)
+{
+#ifdef DEBUG
+       printf ("SDRAM attributes:\n");
+       printf ("  tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
+               "CAS Latency:%d cycles\n",
+               (SDRAM_tRCD >> 15),
+               (SDRAM_tRP >> 11),
+               (SDRAM_tRAS >> 6),
+               (SDRAM_tWR >> 19),
+               (SDRAM_CL >> 2));
+       printf ("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+       printf ("Bank size = %d MB\n", 128);
+#endif
+       gd->bd->bi_memstart = CFG_SDRAM_BASE;
+       gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+       return (gd->bd->bi_memsize);
+}
+
+void swap_to (int device_id)
+{
+
+       if (device_id == ETHERNET) {
+               *pFIO_DIR = PF0;
+               asm ("ssync;");
+               *pFIO_FLAG_S = PF0;
+               asm ("ssync;");
+       } else if (device_id == FLASH) {
+               *pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
+               *pFIO_FLAG_S = (PF4 | PF3 | PF2);
+               *pFIO_MASKA_D = (PF8 | PF6 | PF5);
+               *pFIO_MASKB_D = (PF7);
+               *pFIO_POLAR = (PF8 | PF6 | PF5);
+               *pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
+               *pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
+               *pFIO_FLAG_D = (PF4 | PF3 | PF2);
+               asm ("ssync;");
+       } else {
+               printf ("Unknown bank to switch\n");
+       }
+
+       return;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r (void)
+{
+       int i;
+       int cf_stat = 0;
+
+       /* Check whether CF card is inserted */
+       *pFIO_EDGE = FIO_EDGE_CF_BITS;
+       *pFIO_POLAR = FIO_POLAR_CF_BITS;
+       for (i = 0; i < 0x300; i++)
+               asm ("nop;");
+
+       if ((*pFIO_FLAG_S) & CF_STAT_BITS) {
+               cf_stat = 0;
+       } else {
+               cf_stat = 1;
+       }
+
+       *pFIO_EDGE = FIO_EDGE_BITS;
+       *pFIO_POLAR = FIO_POLAR_BITS;
+
+
+       if (cf_stat) {
+               printf ("Booting from COMPACT flash\n");
+
+               /* Set cycle time for CF */
+               *(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL;
+
+               for (i = 0; i < 0x1000; i++)
+                       asm ("nop;");
+               for (i = 0; i < 0x1000; i++)
+                       asm ("nop;");
+               for (i = 0; i < 0x1000; i++)
+                       asm ("nop;");
+
+               serial_setbrg ();
+               ide_init ();
+
+               setenv ("bootargs", "");
+               setenv ("bootcmd",
+                       "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
+       } else {
+               printf ("Booting from FLASH\n");
+       }
+
+       return 1;
+}
+#endif
+
+#ifdef CONFIG_STAMP_CF
+
+void cf_outb (unsigned char val, volatile unsigned char *addr)
+{
+       /*
+        * Set PF1 PF0 respectively to 0 1 to divert address
+        * to the expansion memory banks
+        */
+       *pFIO_FLAG_S = CF_PF0;
+       *pFIO_FLAG_C = CF_PF1;
+       asm ("ssync;");
+
+       *(addr) = val;
+       asm ("ssync;");
+
+       /* Setback PF1 PF0 to 0 0 to address external
+        * memory banks  */
+       *(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0;
+       asm ("ssync;");
+}
+
+unsigned char cf_inb (volatile unsigned char *addr)
+{
+       volatile unsigned char c;
+
+       *pFIO_FLAG_S = CF_PF0;
+       *pFIO_FLAG_C = CF_PF1;
+       asm ("ssync;");
+
+       c = *(addr);
+       asm ("ssync;");
+
+       *pFIO_FLAG_C = CF_PF1_PF0;
+       asm ("ssync;");
+
+       return c;
+}
+
+void cf_insw (unsigned short *sect_buf, unsigned short *addr, int words)
+{
+       int i;
+
+       *pFIO_FLAG_S = CF_PF0;
+       *pFIO_FLAG_C = CF_PF1;
+       asm ("ssync;");
+
+       for (i = 0; i < words; i++) {
+               *(sect_buf + i) = *(addr);
+               asm ("ssync;");
+       }
+
+       *pFIO_FLAG_C = CF_PF1_PF0;
+       asm ("ssync;");
+}
+
+void cf_outsw (unsigned short *addr, unsigned short *sect_buf, int words)
+{
+       int i;
+
+       *pFIO_FLAG_S = CF_PF0;
+       *pFIO_FLAG_C = CF_PF1;
+       asm ("ssync;");
+
+       for (i = 0; i < words; i++) {
+               *(addr) = *(sect_buf + i);
+               asm ("ssync;");
+       }
+
+       *pFIO_FLAG_C = CF_PF1_PF0;
+       asm ("ssync;");
+}
+#endif
+
+void stamp_led_set (int LED1, int LED2, int LED3)
+{
+       *pFIO_INEN &= ~(PF2 | PF3 | PF4);
+       *pFIO_DIR |= (PF2 | PF3 | PF4);
+
+       if (LED1 == STATUS_LED_OFF)
+               *pFIO_FLAG_S = PF2;
+       else
+               *pFIO_FLAG_C = PF2;
+       if (LED2 == STATUS_LED_OFF)
+               *pFIO_FLAG_S = PF3;
+       else
+               *pFIO_FLAG_C = PF3;
+       if (LED3 == STATUS_LED_OFF)
+               *pFIO_FLAG_S = PF4;
+       else
+               *pFIO_FLAG_C = PF4;
+       asm ("ssync;");
+}
+
+void show_boot_progress (int status)
+{
+       switch (status) {
+       case 1:
+               stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
+               break;
+       case 2:
+               stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
+               break;
+       case 3:
+               stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
+               break;
+       case 4:
+               stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
+               break;
+       case 5:
+       case 6:
+               stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
+               break;
+       case 7:
+       case 8:
+               stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
+               break;
+       case 9:
+       case 10:
+       case 11:
+       case 12:
+       case 13:
+       case 14:
+       case 15:
+               stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF,
+                              STATUS_LED_OFF);
+               break;
+       default:
+               stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
+               break;
+       }
+}

diff --git a/board/stamp/stamp.h b/board/stamp/stamp.h
new file mode 100644 (file)
index 0000000..7bc33b4
--- /dev/null
+++ b/board/stamp/stamp.h
@@ -0,0 +1,57 @@
+/*
+ * U-boot - stamp.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __STAMP_H__
+#define __STAMP_H__
+
+extern void init_Flags(void);
+
+extern volatile unsigned long *ambctl0;
+extern volatile unsigned long *ambctl1;
+extern volatile unsigned long *amgctl;
+
+extern unsigned long pll_div_fact;
+extern void serial_setbrg(void);
+extern void pll_set(int vco, int crystal_frq, int pll_div);
+
+/* Definitions used in  Compact Flash Boot support */
+#define FIO_EDGE_CF_BITS       0x0000
+#define FIO_POLAR_CF_BITS      0x0000
+#define        FIO_EDGE_BITS           0x1E0
+#define        FIO_POLAR_BITS          0x160
+
+/* Compact flash status bits in status register */
+#define CF_STAT_BITS           0x00000060
+
+/* CF Flags used to switch between expansion and external
+ * memory banks
+ */
+#define CF_PF0                 0x0001
+#define CF_PF1                 0x0002
+#define CF_PF1_PF0             0x0003
+
+#endif

diff --git a/board/stamp/u-boot.lds b/board/stamp/u-boot.lds
new file mode 100644 (file)
index 0000000..9a22e50
--- /dev/null
+++ b/board/stamp/u-boot.lds
@@ -0,0 +1,147 @@
+/*
+ * U-boot - u-boot.lds
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(bfin)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)      }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)      }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)       }
+  .rela.got      : { *(.rela.got)      }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)       }
+  .rela.bss      : { *(.rela.bss)      }
+  .rel.plt       : { *(.rel.plt)       }
+  .rela.plt      : { *(.rela.plt)      }
+  .init          : { *(.init)          }
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within */
+    /* the sector before the environment sector. If it throws  */
+    /* an error during compilation remove an object here to get        */
+    /* it linked after the configuration sector.               */
+
+    cpu/bf533/start.o          (.text)
+    cpu/bf533/start1.o         (.text)
+    cpu/bf533/traps.o          (.text)
+    cpu/bf533/interrupt.o      (.text)
+    cpu/bf533/serial.o         (.text)
+    common/dlmalloc.o          (.text)
+    lib_generic/vsprintf.o     (.text)
+    lib_generic/crc32.o                (.text)
+    lib_generic/zlib.o         (.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o       (.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c
index aa3d129f9c930cd34b5b85040a2c85e909c362cc..7caf06a0862d5af851b570464b6a8d3b5fc0b131 100644 (file)
--- a/board/stxxtc/stxxtc.c
+++ b/board/stxxtc/stxxtc.c
@@ -576,7 +576,7 @@ int board_early_init_f(void)
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 
 extern ulong nand_probe(ulong physadr);
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

diff --git a/board/sx1/sx1.c b/board/sx1/sx1.c
index e45f6ae4f3466eb7e273fa65b83efa8c0dc04874..aaef76e713decc903155aa4c558f256fe111b9a1 100644 (file)
--- a/board/sx1/sx1.c
+++ b/board/sx1/sx1.c
@@ -27,6 +27,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static void flash__init (void);
 static void ether__init (void);
 
@@ -43,8 +45,6 @@ static inline void delay (unsigned long loops)
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* arch number of SX1 Board */
        gd->bd->bi_arch_number = MACH_TYPE_SX1;
 
@@ -116,8 +116,6 @@ static void ether__init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
index dada6739b6ca7e433eee80f866b9c4fdc9a2b397..b5c12e3e240edbcc20b628fdf3ca77202e65e896 100644 (file)
--- a/board/tqm834x/tqm834x.c
+++ b/board/tqm834x/tqm834x.c
@@ -32,6 +32,8 @@
 #include <asm-ppc/mmu.h>
 #include <pci.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define IOSYNC                 asm("eieio")
 #define ISYNC                  asm("isync")
 #define SYNC                   asm("sync")
@@ -142,7 +144,6 @@ int checkboard (void)
        puts("Board: TQM834x\n");
 
 #ifdef CONFIG_PCI
-       DECLARE_GLOBAL_DATA_PTR;
        volatile immap_t * immr;
        u32 w, f;
 

diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c
index 13ea6f48ddebf624d133d6c76ff354b5609bc202..69b91017fee339f14497bc37a7a84dfa2847a735 100644 (file)
--- a/board/tqm85xx/tqm85xx.c
+++ b/board/tqm85xx/tqm85xx.c
@@ -36,6 +36,8 @@
 #include <spd.h>
 #include <flash.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern flash_info_t flash_info[];      /* FLASH chips info */
 
 void local_bus_init (void);
@@ -257,7 +259,6 @@ int checkboard (void)
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        volatile immap_t    *immap = (immap_t *)CFG_IMMR;
        volatile ccsr_lbc_t *memctl = &immap->im_lbc;
 
@@ -296,7 +297,7 @@ int misc_init_r (void)
 
                /* Monitor protection ON by default */
                flash_protect (FLAG_PROTECT_SET,
-                              CFG_MONITOR_BASE, 0xffffffff,
+                              CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
                               &flash_info[CFG_MAX_FLASH_BANKS - 1]);
 
                /* Environment protection ON by default */

diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c
index 97bb5c3ee499ad9647a35331b73b7be060da9ddb..ab57ee5c6196b0932d4bf9c972d25cabb8d42350 100644 (file)
--- a/board/tqm8xx/flash.c
+++ b/board/tqm8xx/flash.c
@@ -31,6 +31,8 @@
 
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
 # ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
 #  define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
@@ -63,8 +65,6 @@ unsigned long flash_init (void)
 #ifdef CFG_OR_TIMING_FLASH_AT_50MHZ
        int scy, trlx, flash_or_timing, clk_diff;
 
-       DECLARE_GLOBAL_DATA_PTR;
-
        scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
        if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
                trlx = OR_TRLX;

diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c
index 017bdf9442a8871ebfa737ff0faa9445c33c5e74..520bea873fdf74b1fce470d8a0abaef58bf1ae8d 100644 (file)
--- a/board/tqm8xx/tqm8xx.c
+++ b/board/tqm8xx/tqm8xx.c
@@ -31,12 +31,10 @@
 #include <ps2mult.h>
 #endif
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
 
 static long int dram_size (long int, long int *, long int);
 
-/* ------------------------------------------------------------------------- */
-
 #define        _NOT_USED_      0xFFFFFFFF
 
 const uint sdram_table[] =
@@ -104,8 +102,6 @@ const uint sdram_table[] =
 
 int checkboard (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        char *s = getenv ("serial#");
 
        puts ("Board: ");

diff --git a/board/trab/Makefile b/board/trab/Makefile
index ced9bc5bc8fd5fe02009536225ad04181392ed3d..159404b269aa63c57ae38e659144abdd63de310a 100644 (file)
--- a/board/trab/Makefile
+++ b/board/trab/Makefile
@@ -47,7 +47,7 @@ trab_fkt.srec:        trab_fkt.o rs485.o tsc2000.o $(LIB)
        $(OBJCOPY) -O srec $(<:.o=) $@
 
 trab_fkt.bin:  trab_fkt.srec
-       $(OBJCOPY) -O binary $< $@ 2>/dev/null
+       $(OBJCOPY) -I srec -O binary $< $@
 
 clean:
        rm -f $(SOBJS) $(OBJS)

diff --git a/board/trab/flash.c b/board/trab/flash.c
index b4435e390f42040e51252057828f6cb25ad58be1..8cdd82400bba2b49b2314d14489fa328f97e4c9f 100644 (file)
--- a/board/trab/flash.c
+++ b/board/trab/flash.c
@@ -308,8 +308,7 @@ outahere:
  * Copy memory to flash
  */
 
-volatile static int write_word (flash_info_t * info, ulong dest,
-                                                               ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
        vu_long *addr = (vu_long *) dest;
        ulong result;

diff --git a/board/trab/memory.c b/board/trab/memory.c
index 91044130988475c42ec0705b77481fbbeeed0fbc..4097892b9efbdff1df8d6865bebf0bff44f62a6d 100644 (file)
--- a/board/trab/memory.c
+++ b/board/trab/memory.c
@@ -454,10 +454,11 @@ int memory_post_tests (unsigned long start, unsigned long size)
 }
 
 #if 0
+DECLARE_GLOBAL_DATA_PTR;
+
 int memory_post_test (int flags)
 {
        int ret = 0;
-       DECLARE_GLOBAL_DATA_PTR;
        bd_t *bd = gd->bd;
        unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
                                 256 << 20 : bd->bi_memsize) - (1 << 20);

diff --git a/board/trab/trab.c b/board/trab/trab.c
index e8dfd2ceb0b1476dbff743506865e03b885bc664..868a899ee90e0002f204b68a306a26407837a222 100644 (file)
--- a/board/trab/trab.c
+++ b/board/trab/trab.c
@@ -28,7 +28,7 @@
 #include <s3c2400.h>
 #include <command.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CFG_BRIGHTNESS
 static void spi_init(void);
@@ -52,8 +52,6 @@ extern int do_mdm_init; /* defined in common/main.c */
 #define KBD_MDELAY     5000
 static void udelay_no_timer (int usec)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int i;
        int delay = usec * 3;
 
@@ -70,7 +68,6 @@ int board_init ()
 #if defined(CONFIG_VFD)
        extern int vfd_init_clocks(void);
 #endif
-       DECLARE_GLOBAL_DATA_PTR;
        S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 
@@ -141,8 +138,6 @@ int board_init ()
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
        return 0;

diff --git a/board/trab/vfd.c b/board/trab/vfd.c
index f510ee55b07d169acfef2d68e370a2cc7513c376..cea8b0b665ee318133773a6a403a66e8df289265 100644 (file)
--- a/board/trab/vfd.c
+++ b/board/trab/vfd.c
@@ -39,6 +39,8 @@
 #include <devices.h>
 #include <s3c2400.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_VFD
 
 /************************************************************************/
@@ -86,7 +88,6 @@ unsigned char bit_vfd_table[112][18][2][4][2];
  */
 void init_grid_ctrl(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        ulong adr, grid_cycle;
        unsigned int bit, display;
        unsigned char temp, bit_nr;
@@ -172,7 +173,6 @@ void init_grid_ctrl(void)
  */
 void create_vfd_table(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned long vfd_table[112][18][2][4][2];
        unsigned int x, y, color, display, entry, pixel;
        unsigned int x_abcdef = 0;
@@ -280,7 +280,6 @@ void set_vfd_pixel(unsigned char x, unsigned char y,
                   unsigned char color, unsigned char display,
                   unsigned char value)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        ulong adr;
        unsigned char bit_nr, temp;
 
@@ -435,8 +434,6 @@ int drv_vfd_init(void)
        static int vfd_init_done = 0;
        int vfd_inv_data = 0;
 
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (vfd_init_done != 0)
                return (0);
        vfd_init_done = 1;

diff --git a/board/versatile/split_by_variant.sh b/board/versatile/split_by_variant.sh
index 35c663e6a555dffa34e82bbb13f012a977f781df..576f238adef2f8c895ebe5e7b3aacb6b6ecd39cb 100755 (executable)
--- a/board/versatile/split_by_variant.sh
+++ b/board/versatile/split_by_variant.sh
@@ -36,5 +36,5 @@ fi
 # ---------------------------------------------------------
 # Complete the configuration
 # ---------------------------------------------------------
-./mkconfig -a versatile arm arm926ejs versatile
+./mkconfig -a versatile arm arm926ejs versatile NULL versatile
 echo "Variant:: $variant"

diff --git a/board/versatile/versatile.c b/board/versatile/versatile.c
index 0274027096fda0951ddfe38599baecee089a0d35..9d1a25ec8a09ec11a5a9c8c029d1816d00d352ba 100644 (file)
--- a/board/versatile/versatile.c
+++ b/board/versatile/versatile.c
@@ -35,6 +35,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void flash__init (void);
 void ether__init (void);
 void peripheral_power_enable (void);
@@ -61,9 +63,6 @@ static inline void delay (unsigned long loops)
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
-
        /*
         * set clock frequency:
         *      VERSATILE_REFCLK is 32KHz

diff --git a/board/voiceblue/voiceblue.c b/board/voiceblue/voiceblue.c
index 7a2d243ef88f3855b40debc1cec2f9cae3102a0b..04093d172c6bf83f3294e1245fd6cdc95bdfa1e7 100644 (file)
--- a/board/voiceblue/voiceblue.c
+++ b/board/voiceblue/voiceblue.c
@@ -21,10 +21,10 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int board_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        *((volatile unsigned char *) VOICEBLUE_LED_REG) = 0xaa;
 
        /* arch number of VoiceBlue board */
@@ -39,8 +39,6 @@ int board_init(void)
 
 int dram_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        *((volatile unsigned short *) VOICEBLUE_LED_REG) = 0xff;
 
        /* Take the Ethernet controller out of reset and wait

diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c
index 56cb855af0190e05474efd32493f043abf8bea72..fe4b6a91d20797bc48a7ef5e5da07a5153e43024 100644 (file)
--- a/board/wepep250/wepep250.c
+++ b/board/wepep250/wepep250.c
@@ -23,45 +23,45 @@
 #include <common.h>
 #include <asm/arch/pxa-regs.h>
 
-int board_init( void ){
-  DECLARE_GLOBAL_DATA_PTR;
+DECLARE_GLOBAL_DATA_PTR;
 
-  gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250;
-  gd->bd->bi_boot_params = 0xa0000000;
+int board_init (void)
+{
+       gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250;
+       gd->bd->bi_boot_params = 0xa0000000;
 /*
  * Setup GPIO stuff to get serial working
  */
 #if defined( CONFIG_FFUART )
-  GPDR1   = 0x80;
-  GAFR1_L = 0x8010;
+       GPDR1 = 0x80;
+       GAFR1_L = 0x8010;
 #elif defined( CONFIG_BTUART )
-  GPDR1   = 0x800;
-  GAFR1_L = 0x900000;
+       GPDR1 = 0x800;
+       GAFR1_L = 0x900000;
 #endif
-  PSSR    = 0x20;
+       PSSR = 0x20;
 
-  return 0;
+       return 0;
 }
 
-int dram_init( void ){
-  DECLARE_GLOBAL_DATA_PTR;
-
+int dram_init (void)
+{
 #if ( CONFIG_NR_DRAM_BANKS > 0 )
-  gd->bd->bi_dram[0].start = WEP_SDRAM_1;
-  gd->bd->bi_dram[0].size  = WEP_SDRAM_1_SIZE;
+       gd->bd->bi_dram[0].start = WEP_SDRAM_1;
+       gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE;
 #endif
 #if ( CONFIG_NR_DRAM_BANKS > 1 )
-  gd->bd->bi_dram[1].start = WEP_SDRAM_2;
-  gd->bd->bi_dram[1].size  = WEP_SDRAM_2_SIZE;
+       gd->bd->bi_dram[1].start = WEP_SDRAM_2;
+       gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE;
 #endif
 #if ( CONFIG_NR_DRAM_BANKS > 2 )
-  gd->bd->bi_dram[2].start = WEP_SDRAM_3;
-  gd->bd->bi_dram[2].size  = WEP_SDRAM_3_SIZE;
+       gd->bd->bi_dram[2].start = WEP_SDRAM_3;
+       gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE;
 #endif
 #if ( CONFIG_NR_DRAM_BANKS > 3 )
-  gd->bd->bi_dram[3].start = WEP_SDRAM_4;
-  gd->bd->bi_dram[3].size  = WEP_SDRAM_4_SIZE;
+       gd->bd->bi_dram[3].start = WEP_SDRAM_4;
+       gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE;
 #endif
 
-  return 0;
+       return 0;
 }

diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c
index 26fb312fd0a5c7ab77e7df1b6eeac01fda02b94e..9baa457c046f52dae5e22abedfd08ac45cd990d8 100644 (file)
--- a/board/xaeniax/xaeniax.c
+++ b/board/xaeniax/xaeniax.c
@@ -30,8 +30,7 @@
 
 #include <common.h>
 
-/* ------------------------------------------------------------------------- */
-
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -39,8 +38,6 @@
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* memory and cpu-speed are setup before relocation */
        /* so we do _nothing_ here */
 
@@ -63,8 +60,6 @@ int board_late_init(void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
        /*      gd->bd->bi_dram[1].start = PHYS_SDRAM_2;*/

diff --git a/board/xilinx/ml300/serial.c b/board/xilinx/ml300/serial.c
index 19bcc6ff33400f284ed56fd367fd9c37de694319..c204b88e415bae025f8829025b4af8e642355624 100644 (file)
--- a/board/xilinx/ml300/serial.c
+++ b/board/xilinx/ml300/serial.c
@@ -43,6 +43,8 @@
 #include <configs/ml300.h>
 #include "xparameters.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define USE_CHAN1 \
        ((defined XPAR_UARTNS550_0_BASEADDR) && (defined CFG_INIT_CHAN1))
 #define USE_CHAN2 \
@@ -64,7 +66,6 @@ int
 serial_init(void)
 {
 #if USE_CHAN1
-       DECLARE_GLOBAL_DATA_PTR;
        int clock_divisor;
 
        clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate;
@@ -103,7 +104,6 @@ void
 serial_setbrg(void)
 {
 #if USE_CHAN1
-       DECLARE_GLOBAL_DATA_PTR;
        int clock_divisor;
 
        clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate;

diff --git a/board/xilinx/xilinx_enet/emac_adapter.c b/board/xilinx/xilinx_enet/emac_adapter.c
index 1076345752f3e2f5ae91b7bf01c4e9213ed87ff7..b30e8976692211c55242938ed70296f90a5ab38d 100644 (file)
--- a/board/xilinx/xilinx_enet/emac_adapter.c
+++ b/board/xilinx/xilinx_enet/emac_adapter.c
@@ -39,7 +39,6 @@
 
 #include <common.h>
 #include <net.h>
-#include <configs/ml300.h>
 #include "xparameters.h"
 #include "xemac.h"
 
@@ -148,7 +147,7 @@ eth_rx(void)
        RecvFrameLength = PKTSIZE;
        Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength);
        if (Result == XST_SUCCESS) {
-               NetReceive((uchar)etherrxbuff, RecvFrameLength);
+               NetReceive((uchar *)etherrxbuff, RecvFrameLength);
                return (1);
        } else {
                return (0);

diff --git a/board/xilinx/xilinx_iic/iic_adapter.c b/board/xilinx/xilinx_iic/iic_adapter.c
index f3ecba72dc88095ba9837f7fe01e14544cc6efdf..163fe1511dba17b4c08ec4ac119c15648e6b1ad6 100644 (file)
--- a/board/xilinx/xilinx_iic/iic_adapter.c
+++ b/board/xilinx/xilinx_iic/iic_adapter.c
@@ -40,7 +40,6 @@
 #include <common.h>
 #include <environment.h>
 #include <net.h>
-#include <configs/ml300.h>
 #include "xparameters.h"
 
 #ifdef CFG_ENV_IS_IN_EEPROM

diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c
index ef5e9da0e3e8c12acfb810dc0c19f9050ebe4b8b..528d3239ce4306ca05f29825d2d231301679e1ee 100644 (file)
--- a/board/xm250/xm250.c
+++ b/board/xm250/xm250.c
@@ -28,6 +28,8 @@
 #include <asm/arch/pxa-regs.h>
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 /* local prototypes */
@@ -61,7 +63,6 @@ int
 board_init (void)
 /**********************************************************/
 {
-       DECLARE_GLOBAL_DATA_PTR;
        /* arch number of MicroSys XM250 */
        gd->bd->bi_arch_number = MACH_TYPE_XM250;
 
@@ -76,8 +77,6 @@ int
 dram_init (void)
 /**********************************************************/
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c
index bb36c965236344f42c44ef65f2f62043059f6d77..a569b534727a87a7e2eb055962061cc1530f5540 100644 (file)
--- a/board/xpedite1k/xpedite1k.c
+++ b/board/xpedite1k/xpedite1k.c
@@ -26,6 +26,8 @@
 #include <spd_sdram.h>
 #include <i2c.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define BOOT_SMALL_FLASH       32      /* 00100000 */
 #define FLASH_ONBD_N           2       /* 00000010 */
 #define FLASH_SRAM_SEL         1       /* 00000001 */
@@ -107,7 +109,7 @@ long int initdram (int board_type)
        long dram_size = 0;
 
 #if defined(CONFIG_SPD_EEPROM)
-       dram_size = spd_sdram (0);
+       dram_size = spd_sdram ();
 #else
        dram_size = fixed_sdram ();
 #endif
@@ -238,8 +240,6 @@ int pci_pre_init(struct pci_controller * hose )
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /*--------------------------------------------------------------------------+
         * Disable everything
         *--------------------------------------------------------------------------*/

diff --git a/board/xsengine/xsengine.c b/board/xsengine/xsengine.c
index a9919dbaa651b6ccdea677c6d06344e6262bff0b..23d56c43ac90377fc5408dea25b07cb8ac253a7b 100644 (file)
--- a/board/xsengine/xsengine.c
+++ b/board/xsengine/xsengine.c
@@ -27,14 +27,14 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Miscelaneous platform dependent initialisations
  */
 
 int board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* memory and cpu-speed are setup before relocation */
        /* so we do _nothing_ here */
 
@@ -56,8 +56,6 @@ int board_post_init (void)
 
 int dram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 

diff --git a/board/zpc1900/config.mk b/board/zpc1900/config.mk
index 1072dc7905e84b7ede5549ec0d16f159d56b4b72..3e53b2be050f4daf2f248cd71c69b33f0cbf941d 100644 (file)
--- a/board/zpc1900/config.mk
+++ b/board/zpc1900/config.mk
@@ -27,4 +27,4 @@
 # ZPC.1900 board
 #
 
-TEXT_BASE = 0xFFE00000
+TEXT_BASE = 0xFE000000

diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c
index 6d16a0d19286b665e227a7ed31762ebbfd9d033b..7db535e8a479220e6fc96d04776007d81f45679a 100644 (file)
--- a/board/zpc1900/zpc1900.c
+++ b/board/zpc1900/zpc1900.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2001-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2003 Arabella Software Ltd.
+ * (C) Copyright 2003-2005 Arabella Software Ltd.
  * Yuli Barcohen <yuli@arabellasw.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,9 +27,6 @@
 #include <common.h>
 #include <ioports.h>
 #include <mpc8260.h>
-#include <asm/m8260_pci.h>
-#include <i2c.h>
-#include <spd.h>
 #include <miiphy.h>
 
 /*
@@ -167,8 +164,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
        /* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
        /* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
        /* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
-       /* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
-       /* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+       /* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+       /* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
        /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
        /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
        /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
@@ -231,11 +228,10 @@ long int initdram(int board_type)
        vu_char *ramaddr;
        uchar c = 0xFF;
        long int msize = CFG_SDRAM_SIZE;
-       uint psdmr = CFG_PSDMR;
        int i;
 
        if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
-               immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
+               immap->im_clkrst.car_sccr |= SCCR_PCI_MODE;
                immap->im_siu_conf.sc_siumcr =
                        (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
                        | SIUMCR_LBPC01;
@@ -255,10 +251,10 @@ long int initdram(int board_type)
        */
        if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
                memctl->memc_lsrt  = CFG_LSRT;
-               memctl->memc_or4   = 0xFFC01480;
-               memctl->memc_br4   = CFG_LSDRAM_BASE | 0x00001861;
-               memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
+               memctl->memc_or4   = CFG_LSDRAM_OR;
+               memctl->memc_br4   = CFG_LSDRAM_BR;
                ramaddr = (vu_char *)CFG_LSDRAM_BASE;
+               memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
                *ramaddr = c;
                memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR;
                for (i = 0; i < 8; i++)
@@ -271,8 +267,8 @@ long int initdram(int board_type)
 
        /* Initialise 60x bus SDRAM */
        memctl->memc_psrt = CFG_PSRT;
-       memctl->memc_or2  = 0xFC0028C0;
-       memctl->memc_br2  = CFG_SDRAM_BASE | 0x00000041;
+       memctl->memc_or2  = CFG_PSDRAM_OR;
+       memctl->memc_br2  = CFG_PSDRAM_BR;
        /*
         * The mode data for Mode Register Write command must appear on
         * the address lines during a mode-set cycle. It is driven by
@@ -283,15 +279,15 @@ long int initdram(int board_type)
         * length must be 4.
         */
        ramaddr = (vu_char *)(CFG_SDRAM_BASE |
-                             ((psdmr & PSDMR_CL_MSK) << 7) | 0x10);
-       memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+                             ((CFG_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
+       memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
        *ramaddr = c;
-       memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+       memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
        for (i = 0; i < 8; i++)
                *ramaddr = c;
-       memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
+       memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_MRW;  /* Mode Register write */
        *ramaddr = c;
-       memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
+       memctl->memc_psdmr = CFG_PSDMR | PSDMR_RFEN;    /* Refresh enable */
        *ramaddr = c;
 #endif /* CFG_RAMBOOT */
 

diff --git a/board/zylonite/Makefile b/board/zylonite/Makefile
new file mode 100644 (file)
index 0000000..999647f
--- /dev/null
+++ b/board/zylonite/Makefile
@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   := zylonite.o flash.o
+SOBJS  := lowlevel_init.o
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

diff --git a/board/zylonite/config.mk b/board/zylonite/config.mk
new file mode 100644 (file)
index 0000000..09b0f71
--- /dev/null
+++ b/board/zylonite/config.mk
@@ -0,0 +1,4 @@
+#TEXT_BASE = 0x0
+#TEXT_BASE = 0xa1700000
+#TEXT_BASE = 0xa3080000
+TEXT_BASE = 0xa3008000

diff --git a/board/zylonite/flash.c b/board/zylonite/flash.c
new file mode 100644 (file)
index 0000000..883c1ba
--- /dev/null
+++ b/board/zylonite/flash.c
@@ -0,0 +1,434 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];  /* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH               ushort
+#define FLASH_PORT_WIDTHV              vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH               ulong
+#define FLASH_PORT_WIDTHV              vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+#define FPW       FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#if 0
+       int i;
+       ulong size = 0;
+
+       for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+               switch (i) {
+               case 0:
+                       flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+                       flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+                       break;
+               case 1:
+                       flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+                       flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+                       break;
+               default:
+                       panic ("configured too many flash banks!\n");
+                       break;
+               }
+               size += flash_info[i].size;
+       }
+
+       /* Protect monitor and environment sectors
+        */
+       flash_protect ( FLAG_PROTECT_SET,
+                       CFG_FLASH_BASE,
+                       CFG_FLASH_BASE + monitor_flash_len - 1,
+                       &flash_info[0] );
+
+       flash_protect ( FLAG_PROTECT_SET,
+                       CFG_ENV_ADDR,
+                       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+       return size;
+#endif
+       return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+       int i;
+
+       if (info->flash_id == FLASH_UNKNOWN) {
+               return;
+       }
+
+       if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+               for (i = 0; i < info->sector_count; i++) {
+                       info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+                       info->protect[i] = 0;
+               }
+       }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+       int i;
+
+       if (info->flash_id == FLASH_UNKNOWN) {
+               printf ("missing or unknown FLASH type\n");
+               return;
+       }
+
+       switch (info->flash_id & FLASH_VENDMASK) {
+       case FLASH_MAN_INTEL:
+               printf ("INTEL ");
+               break;
+       default:
+               printf ("Unknown Vendor ");
+               break;
+       }
+
+       switch (info->flash_id & FLASH_TYPEMASK) {
+       case FLASH_28F128J3A:
+               printf ("28F128J3A\n");
+               break;
+       default:
+               printf ("Unknown Chip Type\n");
+               break;
+       }
+
+       printf ("  Size: %ld MB in %d Sectors\n",
+                       info->size >> 20, info->sector_count);
+
+       printf ("  Sector Start Addresses:");
+       for (i = 0; i < info->sector_count; ++i) {
+               if ((i % 5) == 0)
+                       printf ("\n   ");
+               printf (" %08lX%s",
+                       info->start[i],
+                       info->protect[i] ? " (RO)" : "     ");
+       }
+       printf ("\n");
+       return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+       volatile FPW value;
+
+       /* Write auto select command: read Manufacturer ID */
+       addr[0x5555] = (FPW) 0x00AA00AA;
+       addr[0x2AAA] = (FPW) 0x00550055;
+       addr[0x5555] = (FPW) 0x00900090;
+
+       mb ();
+       value = addr[0];
+
+       switch (value) {
+
+       case (FPW) INTEL_MANUFACT:
+               info->flash_id = FLASH_MAN_INTEL;
+               break;
+
+       default:
+               info->flash_id = FLASH_UNKNOWN;
+               info->sector_count = 0;
+               info->size = 0;
+               addr[0] = (FPW) 0x00FF00FF;     /* restore read mode */
+               return (0);                     /* no or unknown flash  */
+       }
+
+       mb ();
+       value = addr[1];                        /* device ID        */
+
+       switch (value) {
+
+       case (FPW) INTEL_ID_28F128J3A:
+               info->flash_id += FLASH_28F128J3A;
+               info->sector_count = 128;
+               info->size = 0x02000000;
+               break;                          /* => 16 MB     */
+
+       default:
+               info->flash_id = FLASH_UNKNOWN;
+               break;
+       }
+
+       if (info->sector_count > CFG_MAX_FLASH_SECT) {
+               printf ("** ERROR: sector count %d > max (%d) **\n",
+                       info->sector_count, CFG_MAX_FLASH_SECT);
+               info->sector_count = CFG_MAX_FLASH_SECT;
+       }
+
+       addr[0] = (FPW) 0x00FF00FF;             /* restore read mode */
+
+       return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+       int flag, prot, sect;
+       ulong type, start, last;
+       int rcode = 0;
+
+       if ((s_first < 0) || (s_first > s_last)) {
+               if (info->flash_id == FLASH_UNKNOWN) {
+                       printf ("- missing\n");
+               } else {
+                       printf ("- no sectors to erase\n");
+               }
+               return 1;
+       }
+
+       type = (info->flash_id & FLASH_VENDMASK);
+       if ((type != FLASH_MAN_INTEL)) {
+               printf ("Can't erase unknown flash type %08lx - aborted\n",
+                       info->flash_id);
+               return 1;
+       }
+
+       prot = 0;
+       for (sect = s_first; sect <= s_last; ++sect) {
+               if (info->protect[sect]) {
+                       prot++;
+               }
+       }
+
+       if (prot) {
+               printf ("- Warning: %d protected sectors will not be erased!\n",
+                       prot);
+       } else {
+               printf ("\n");
+       }
+
+       start = get_timer (0);
+       last = start;
+
+       /* Disable interrupts which might cause a timeout here */
+       flag = disable_interrupts ();
+
+       /* Start erase on unprotected sectors */
+       for (sect = s_first; sect <= s_last; sect++) {
+               if (info->protect[sect] == 0) { /* not protected */
+                       FPWV *addr = (FPWV *) (info->start[sect]);
+                       FPW status;
+
+                       printf ("Erasing sector %2d ... ", sect);
+
+                       /* arm simple, non interrupt dependent timer */
+                       reset_timer_masked ();
+
+                       *addr = (FPW) 0x00500050;       /* clear status register */
+                       *addr = (FPW) 0x00200020;       /* erase setup */
+                       *addr = (FPW) 0x00D000D0;       /* erase confirm */
+
+                       while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+                               if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+                                       printf ("Timeout\n");
+                                       *addr = (FPW) 0x00B000B0;       /* suspend erase     */
+                                       *addr = (FPW) 0x00FF00FF;       /* reset to read mode */
+                                       rcode = 1;
+                                       break;
+                               }
+                       }
+
+                       *addr = 0x00500050;     /* clear status register cmd.   */
+                       *addr = 0x00FF00FF;     /* resest to read mode          */
+
+                       printf (" done\n");
+               }
+       }
+       return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+       ulong cp, wp;
+       FPW data;
+       int count, i, l, rc, port_width;
+
+       if (info->flash_id == FLASH_UNKNOWN) {
+               return 4;
+       }
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+       wp = (addr & ~1);
+       port_width = 2;
+#else
+       wp = (addr & ~3);
+       port_width = 4;
+#endif
+
+       /*
+        * handle unaligned start bytes
+        */
+       if ((l = addr - wp) != 0) {
+               data = 0;
+               for (i = 0, cp = wp; i < l; ++i, ++cp) {
+                       data = (data << 8) | (*(uchar *) cp);
+               }
+               for (; i < port_width && cnt > 0; ++i) {
+                       data = (data << 8) | *src++;
+                       --cnt;
+                       ++cp;
+               }
+               for (; cnt == 0 && i < port_width; ++i, ++cp) {
+                       data = (data << 8) | (*(uchar *) cp);
+               }
+
+               if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+                       return (rc);
+               }
+               wp += port_width;
+       }
+
+       /*
+        * handle word aligned part
+        */
+       count = 0;
+       while (cnt >= port_width) {
+               data = 0;
+               for (i = 0; i < port_width; ++i) {
+                       data = (data << 8) | *src++;
+               }
+               if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+                       return (rc);
+               }
+               wp += port_width;
+               cnt -= port_width;
+               if (count++ > 0x800) {
+                       spin_wheel ();
+                       count = 0;
+               }
+       }
+
+       if (cnt == 0) {
+               return (0);
+       }
+
+       /*
+        * handle unaligned tail bytes
+        */
+       data = 0;
+       for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+               data = (data << 8) | *src++;
+               --cnt;
+       }
+       for (; i < port_width; ++i, ++cp) {
+               data = (data << 8) | (*(uchar *) cp);
+       }
+
+       return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+       FPWV *addr = (FPWV *) dest;
+       ulong status;
+       int flag;
+
+       /* Check if Flash is (sufficiently) erased */
+       if ((*addr & data) != data) {
+               printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+               return (2);
+       }
+       /* Disable interrupts which might cause a timeout here */
+       flag = disable_interrupts ();
+
+       *addr = (FPW) 0x00400040;       /* write setup */
+       *addr = data;
+
+       /* arm simple, non interrupt dependent timer */
+       reset_timer_masked ();
+
+       /* wait while polling the status register */
+       while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+               if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+                       *addr = (FPW) 0x00FF00FF;       /* restore read mode */
+                       return (1);
+               }
+       }
+
+       *addr = (FPW) 0x00FF00FF;       /* restore read mode */
+
+       return (0);
+}
+
+void inline spin_wheel (void)
+{
+       static int p = 0;
+       static char w[] = "\\/-";
+
+       printf ("\010%c", w[p]);
+       (++p == 3) ? (p = 0) : 0;
+}

diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S
new file mode 100644 (file)
index 0000000..c3bb4eb
--- /dev/null
+++ b/board/zylonite/lowlevel_init.S
@@ -0,0 +1,371 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+.macro CPWAIT reg
+       mrc     p15,0,\reg,c2,c0,0
+       mov     \reg,\reg
+       sub     pc,pc,#4
+.endm
+
+
+.macro wait time
+       ldr             r2, =OSCR
+       mov             r3, #0
+       str             r3, [r2]
+0:
+       ldr             r3, [r2]
+       cmp             r3, \time
+       bls             0b
+.endm
+
+/*
+ *     Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+       /* Set up GPIO pins first ----------------------------------------- */
+       mov      r10, lr
+
+       /*  Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */
+       ldr             r0, =0x40E10438 @ GPIO41 FFRXD
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       ldr             r0, =0x40E1043C @ GPIO42 FFTXD
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       ldr             r0, =0x40E10440 @ GPIO43 FFCTS
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       ldr             r0, =0x40E10444 @ GPIO 44 FFDCD
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       ldr             r0, =0x40E10448 @ GPIO 45 FFDSR
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       ldr             r0, =0x40E1044C @ GPIO 46 FFRI
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       ldr             r0, =0x40E10450 @ GPIO 47 FFDTR
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       ldr             r0, =0x40E10454 @ GPIO 48
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       /* tebrandt - ASCR, clear the RDH bit */
+       ldr             r0, =ASCR
+       ldr             r1, [r0]
+       bic             r1, r1, #0x80000000
+       str             r1, [r0]
+
+       /* ---------------------------------------------------------------- */
+       /* Enable memory interface                                          */
+       /*                                                                  */
+       /* The sequence below is based on the recommended init steps        */
+       /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+       /* Chapter 10.                                                      */
+       /* ---------------------------------------------------------------- */
+
+       /* ---------------------------------------------------------------- */
+       /* Step 1: Wait for at least 200 microsedonds to allow internal     */
+       /*         clocks to settle. Only necessary after hard reset...     */
+       /*         FIXME: can be optimized later                            */
+       /* ---------------------------------------------------------------- */
+
+       /* mk:   replaced with wait macro */
+/*     ldr r3, =OSCR                   /\* reset the OS Timer Count to zero *\/ */
+/*     mov r2, #0 */
+/*     str r2, [r3] */
+/*     ldr r4, =0x300                  /\* really 0x2E1 is about 200usec,   *\/ */
+/*                                     /\* so 0x300 should be plenty        *\/ */
+/* 1: */
+/*     ldr r2, [r3] */
+/*     cmp r4, r2 */
+/*     bgt 1b */
+       wait #300
+
+mem_init:
+
+       /* configure the MEMCLKCFG register */
+       ldr             r1, =MEMCLKCFG
+       ldr             r2, =0x00010001
+       str             r2, [r1]             @ WRITE
+       ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
+
+       /* set CSADRCFG[0] to data flash SRAM mode */
+       ldr             r1, =CSADRCFG0
+       ldr             r2, =0x00320809
+       str             r2, [r1]             @ WRITE
+       ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
+
+       /* set CSADRCFG[1] to data flash SRAM mode */
+       ldr             r1, =CSADRCFG1
+       ldr             r2, =0x00320809
+       str             r2, [r1]             @ WRITE
+       ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
+
+       /* set MSC 0 register for SRAM memory */
+       ldr             r1, =MSC0
+       ldr             r2, =0x11191119
+       str             r2, [r1]             @ WRITE
+       ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
+
+       /* set CSADRCFG[2] to data flash SRAM mode */
+       ldr             r1, =CSADRCFG2
+       ldr             r2, =0x00320809
+       str             r2, [r1]             @ WRITE
+       ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
+
+       /* set CSADRCFG[3] to VLIO mode */
+       ldr             r1, =CSADRCFG3
+       ldr             r2, =0x0032080B
+       str             r2, [r1]             @ WRITE
+       ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
+
+       /* set MSC 1 register for VLIO memory */
+       ldr             r1, =MSC1
+       ldr             r2, =0x123C1119
+       str             r2, [r1]             @ WRITE
+       ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
+
+#if 0
+       /* This does not work in Zylonite. -SC */
+       ldr             r0, =0x15fffff0
+       ldr             r1, =0xb10b
+       str             r1, [r0]
+       str             r1, [r0, #4]
+#endif
+
+       /* Configure ACCR Register */
+       ldr             r0, =ACCR               @ ACCR
+       ldr             r1, =0x0180b108
+       str             r1, [r0]
+       ldr             r1, [r0]
+
+       /* Configure MDCNFG Register */
+       ldr             r0, =MDCNFG             @ MDCNFG
+       ldr             r1, =0x403
+       str             r1, [r0]
+       ldr             r1, [r0]
+
+       /* Perform Resistive Compensation by configuring RCOMP register */
+       ldr             r1, =RCOMP              @ RCOMP
+       ldr             r2, =0x000000ff
+       str             r2, [r1]
+       ldr             r2, [r1]
+
+       /* Configure MDMRS Register for SDCS0 */
+       ldr             r1, =MDMRS              @ MDMRS
+       ldr             r2, =0x60000023
+       ldr             r3, [r1]
+       orr             r2, r2, r3
+       str             r2, [r1]
+       ldr             r2, [r1]
+
+       /* Configure MDMRS Register for SDCS1 */
+       ldr             r1, =MDMRS              @ MDMRS
+       ldr             r2, =0xa0000023
+       ldr             r3, [r1]
+       orr             r2, r2, r3
+       str             r2, [r1]
+       ldr             r2, [r1]
+
+       /* Configure MDREFR */
+       ldr             r1, =MDREFR             @ MDREFR
+       ldr             r2, =0x00000006
+       str             r2, [r1]
+       ldr             r2, [r1]
+
+       /* Configure EMPI */
+       ldr             r1, =EMPI               @ EMPI
+       ldr             r2, =0x80000000
+       str             r2, [r1]
+       ldr             r2, [r1]
+
+       /* Hardware DDR Read-Strobe Delay Calibration */
+       ldr             r0, =DDR_HCAL           @ DDR_HCAL
+       ldr             r1, =0x803ffc07     @ the offset is correct? -SC
+       str             r1, [r0]
+       wait            #5
+       ldr             r1, [r0]
+
+       /* Here we assume the hardware calibration alwasy be successful. -SC */
+       /* Set DMCEN bit in MDCNFG Register */
+       ldr             r0, =MDCNFG             @ MDCNFG
+       ldr             r1, [r0]
+       orr             r1, r1, #0x40000000     @ enable SDRAM for Normal Access
+       str             r1, [r0]
+
+       /* scrub/init SDRAM if enabled/present */
+/*     ldr     r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
+/*     ldr     r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
+/*     mov     r8,r12           /\* save DRAM size (mk: why???) *\/ */
+       ldr     r8, =0xa0000000  /* base address of SDRAM (CFG_DRAM_BASE) */
+       ldr     r9, =0x04000000  /* size of memory to scrub (CFG_DRAM_SIZE) */
+       mov     r0, #0           /* scrub with 0x0000:0000 */
+       mov     r1, #0
+       mov     r2, #0
+       mov     r3, #0
+       mov     r4, #0
+       mov     r5, #0
+       mov     r6, #0
+       mov     r7, #0
+10:    /* fastScrubLoop */
+       subs    r9, r9, #32     /* 32 bytes/line */
+       stmia   r8!, {r0-r7}
+       beq     15f
+       b       10b
+
+15:
+       /* Mask all interrupts */
+       mov     r1, #0
+       mcr     p6, 0, r1, c1, c0, 0    @ ICMR
+
+       /* Disable software and data breakpoints */
+       mov     r0, #0
+       mcr     p15,0,r0,c14,c8,0  /* ibcr0 */
+       mcr     p15,0,r0,c14,c9,0  /* ibcr1 */
+       mcr     p15,0,r0,c14,c4,0  /* dbcon */
+
+       /* Enable all debug functionality */
+       mov     r0,#0x80000000
+       mcr     p14,0,r0,c10,c0,0  /* dcsr */
+
+       /* We are finished with Intel's memory controller initialisation    */
+
+       /* ---------------------------------------------------------------- */
+       /* End lowlevel_init                                                     */
+       /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+       mov     pc, lr
+
+/*
+@********************************************************************************
+@ DDR calibration
+@
+@  This function is used to calibrate DQS delay lines.
+@ Monahans supports three ways to do it. One is software
+@ calibration. Two is hardware calibration. Three is hybrid
+@ calibration.
+@
+@ TBD
+@ -SC
+ddr_calibration:
+
+       @ Case 1:       Write the correct delay value once
+       @ Configure DDR_SCAL Register
+       ldr     r0, =DDR_SCAL           @ DDR_SCAL
+q      ldr     r1, =0xaf2f2f2f
+       str     r1, [r0]
+       ldr     r1, [r0]
+*/
+/*     @ Case 2:       Software Calibration
+       @ Write test pattern to memory
+       ldr     r5, =0x0faf0faf         @ Data Pattern
+       ldr     r4, =0xa0000000         @ DDR ram
+       str     r5, [r4]
+
+       mov     r1, =0x0                @ delay count
+       mov     r6, =0x0
+       mov     r7, =0x0
+ddr_loop1:
+       add     r1, r1, =0x1
+       cmp     r1, =0xf
+       ble     end_loop
+       mov     r3, r1
+       mov     r0, r1, lsl #30
+       orr     r3, r3, r0
+       mov     r0, r1, lsl #22
+       orr     r3, r3, r0
+       mov     r0, r1, lsl #14
+       orr     r3, r3, r0
+       orr     r3, r3, =0x80000000
+       ldr     r2, =DDR_SCAL
+       str     r3, [r2]
+
+       ldr     r2, [r4]
+       cmp     r2, r5
+       bne     ddr_loop1
+       mov     r6, r1
+ddr_loop2:
+       add     r1, r1, =0x1
+       cmp     r1, =0xf
+       ble     end_loop
+       mov     r3, r1
+       mov     r0, r1, lsl #30
+       orr     r3, r3, r0
+       mov     r0, r1, lsl #22
+       orr     r3, r3, r0
+       mov     r0, r1, lsl #14
+       orr     r3, r3, r0
+       orr     r3, r3, =0x80000000
+       ldr     r2, =DDR_SCAL
+       str     r3, [r2]
+
+       ldr     r2, [r4]
+       cmp     r2, r5
+       be      ddr_loop2
+       mov     r7, r2
+
+       add     r3, r6, r7
+       lsr     r3, r3, =0x1
+       mov     r0, r1, lsl #30
+       orr     r3, r3, r0
+       mov     r0, r1, lsl #22
+       orr     r3, r3, r0
+       mov     r0, r1, lsl #14
+       orr     r3, r3, r0
+       orr     r3, r3, =0x80000000
+       ldr     r2, =DDR_SCAL
+
+end_loop:
+
+       @ Case 3:       Hardware Calibratoin
+       ldr     r0, =DDR_HCAL           @ DDR_HCAL
+       ldr     r1, =0x803ffc07     @ the offset is correct? -SC
+       str     r1, [r0]
+       wait    #5
+       ldr     r1, [r0]
+       mov     pc, lr
+*/

diff --git a/board/zylonite/u-boot.lds b/board/zylonite/u-boot.lds
new file mode 100644 (file)
index 0000000..f010239
--- /dev/null
+++ b/board/zylonite/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text      :
+       {
+         cpu/pxa/start.o       (.text)
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data : { *(.data) }
+
+       . = ALIGN(4);
+       .got : { *(.got) }
+
+       . = .;
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       __bss_start = .;
+       .bss : { *(.bss) }
+       _end = .;
+}

diff --git a/board/zylonite/zylonite.c b/board/zylonite/zylonite.c
new file mode 100644 (file)
index 0000000..5829170
--- /dev/null
+++ b/board/zylonite/zylonite.c
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+       /* memory and cpu-speed are setup before relocation */
+       /* so we do _nothing_ here */
+
+       /* arch number of Lubbock-Board */
+       gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
+
+       /* adress of boot parameters */
+       gd->bd->bi_boot_params = 0xa0000100;
+
+       return 0;
+}
+
+int board_late_init(void)
+{
+       setenv("stdout", "serial");
+       setenv("stderr", "serial");
+       return 0;
+}
+
+
+int dram_init (void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+       gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+       gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+       gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+       gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+       gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+       return 0;
+}

diff --git a/common/Makefile b/common/Makefile
index 7dbf84a555ea9d3b54742f96785e8cf900056a83..eb0b5dadfec12fb62680336f8f440929c2fdaf91 100644 (file)
--- a/common/Makefile
+++ b/common/Makefile
@@ -51,7 +51,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \
          memsize.o miiphybb.o miiphyutil.o \
          s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
          usb.o usb_kbd.o usb_storage.o \
-         virtex2.o xilinx.o
+         virtex2.o xilinx.o crc16.o xyzModem.o
 
 OBJS   = $(AOBJS) $(COBJS)
 

diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 40e28dd9d23b4e14774b536bdd854e671f431ffd..04fa4facae1bacd6c4d733574aad56072f1962c6 100644 (file)
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -28,6 +28,7 @@
 #include <command.h>
 #include <net.h>               /* for print_IPaddr */
 
+DECLARE_GLOBAL_DATA_PTR;
 
 #if (CONFIG_COMMANDS & CFG_CMD_BDI)
 static void print_num(const char *, ulong);
@@ -39,8 +40,6 @@ static void print_str(const char *, const char *);
 
 int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int i;
        bd_t *bd = gd->bd;
        char buf[32];
@@ -127,8 +126,6 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int i;
        bd_t *bd = gd->bd;
 
@@ -153,8 +150,6 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int i;
        bd_t *bd = gd->bd;
 
@@ -187,8 +182,6 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int i;
        bd_t *bd = gd->bd;
 
@@ -215,8 +208,6 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int i;
        bd_t *bd = gd->bd;
 

diff --git a/common/cmd_bedbug.c b/common/cmd_bedbug.c
index cdb379de21656afa8f4011d9df4a397fe906fdda..48086a62809d34ba4e6aaf824b95b48e0c26a2af 100644 (file)
--- a/common/cmd_bedbug.c
+++ b/common/cmd_bedbug.c
@@ -11,187 +11,183 @@
 #include <bedbug/regs.h>
 #include <bedbug/ppc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
 
 #ifndef MAX
 #define MAX(a,b) ((a) > (b) ? (a) : (b))
 #endif
 
-extern void show_regs __P((struct pt_regs*));
-extern int  run_command __P((const char*, int));
+extern void show_regs __P ((struct pt_regs *));
+extern int run_command __P ((const char *, int));
 extern char console_buffer[];
 
-ulong        dis_last_addr = 0;        /* Last address disassembled   */
-ulong        dis_last_len = 20;        /* Default disassembler length */
-CPU_DEBUG_CTX bug_ctx;                  /* Bedbug context structure    */
-
+ulong dis_last_addr = 0;       /* Last address disassembled   */
+ulong dis_last_len = 20;       /* Default disassembler length */
+CPU_DEBUG_CTX bug_ctx;         /* Bedbug context structure    */
 \f
+
 /* ======================================================================
  * U-Boot's puts function does not append a newline, so the bedbug stuff
  * will use this for the output of the dis/assembler.
  * ====================================================================== */
 
-int bedbug_puts(const char *str)
+int bedbug_puts (const char *str)
 {
-  /* -------------------------------------------------- */
+       /* -------------------------------------------------- */
 
-  printf( "%s\r\n", str );
-  return 0;
-} /* bedbug_puts */
+       printf ("%s\r\n", str);
+       return 0;
+}                              /* bedbug_puts */
+\f
 
 
-\f
 /* ======================================================================
  * Initialize the bug_ctx structure used by the bedbug debugger.  This is
  * specific to the CPU since each has different debug registers and
  * settings.
  * ====================================================================== */
 
-void bedbug_init( void )
+void bedbug_init (void)
 {
-  /* -------------------------------------------------- */
+       /* -------------------------------------------------- */
 
 #if defined(CONFIG_4xx)
-  void bedbug405_init( void );
-  bedbug405_init();
+       void bedbug405_init (void);
+
+       bedbug405_init ();
 #elif defined(CONFIG_8xx)
-  void bedbug860_init( void );
-  bedbug860_init();
+       void bedbug860_init (void);
+
+       bedbug860_init ();
 #endif
 
 #if defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260)
-  /* Processors that are 603e core based */
-  void bedbug603e_init( void );
+       /* Processors that are 603e core based */
+       void bedbug603e_init (void);
 
-  bedbug603e_init();
+       bedbug603e_init ();
 #endif
 
-  return;
-} /* bedbug_init */
+       return;
+}                              /* bedbug_init */
+\f
 
 
-\f
 /* ======================================================================
  * Entry point from the interpreter to the disassembler.  Repeated calls
  * will resume from the last disassembled address.
  * ====================================================================== */
-int do_bedbug_dis (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_bedbug_dis (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-  ulong        addr;   /* Address to start disassembly from    */
-  ulong        len;    /* # of instructions to disassemble     */
-  /* -------------------------------------------------- */
-
-  /* Setup to go from the last address if none is given */
-  addr = dis_last_addr;
-  len  = dis_last_len;
-
-  if (argc < 2)
-  {
-    printf ("Usage:\n%s\n", cmdtp->usage);
-    return 1;
-  }
-
-  if(( flag & CMD_FLAG_REPEAT ) == 0 )
-  {
-    /* New command */
-    addr = simple_strtoul( argv[1], NULL, 16 );
-
-    /* If an extra param is given then it is the length */
-    if( argc > 2 )
-      len = simple_strtoul( argv[2], NULL, 16 );
-  }
-
-  /* Run the disassembler */
-  disppc( (unsigned char *)addr, 0, len, bedbug_puts, F_RADHEX );
-
-  dis_last_addr = addr + (len * 4);
-  dis_last_len = len;
-  return 0;
-} /* do_bedbug_dis */
-U_BOOT_CMD(
-       ds,      3,      1,      do_bedbug_dis,
-       "ds      - disassemble memory\n",
-       "ds <address> [# instructions]\n"
-);
+       ulong addr;             /* Address to start disassembly from    */
+       ulong len;              /* # of instructions to disassemble     */
+
+       /* -------------------------------------------------- */
+
+       /* Setup to go from the last address if none is given */
+       addr = dis_last_addr;
+       len = dis_last_len;
+
+       if (argc < 2) {
+               printf ("Usage:\n%s\n", cmdtp->usage);
+               return 1;
+       }
+
+       if ((flag & CMD_FLAG_REPEAT) == 0) {
+               /* New command */
+               addr = simple_strtoul (argv[1], NULL, 16);
+
+               /* If an extra param is given then it is the length */
+               if (argc > 2)
+                       len = simple_strtoul (argv[2], NULL, 16);
+       }
+
+       /* Run the disassembler */
+       disppc ((unsigned char *) addr, 0, len, bedbug_puts, F_RADHEX);
+
+       dis_last_addr = addr + (len * 4);
+       dis_last_len = len;
+       return 0;
+}                              /* do_bedbug_dis */
+
+U_BOOT_CMD (ds, 3, 1, do_bedbug_dis,
+           "ds      - disassemble memory\n",
+           "ds <address> [# instructions]\n");
 \f
 /* ======================================================================
  * Entry point from the interpreter to the assembler.  Assembles
  * instructions in consecutive memory locations until a '.' (period) is
  * entered on a line by itself.
  * ====================================================================== */
-int do_bedbug_asm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_bedbug_asm (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-  long         mem_addr;               /* Address to assemble into     */
-  unsigned long instr;                  /* Machine code for text        */
-  char         prompt[ 15 ];           /* Prompt string for user input */
-  int          asm_err;                /* Error code from the assembler*/
-  /* -------------------------------------------------- */
-   int          rcode = 0;
-
-  if (argc < 2)
-  {
-    printf ("Usage:\n%s\n", cmdtp->usage);
-    return 1;
-  }
-
-  printf( "\nEnter '.' when done\n" );
-  mem_addr = simple_strtoul( argv[ 1 ], NULL, 16 );
-
-  while( 1 )
-  {
-    putc( '\n' );
-    disppc( (unsigned char *)mem_addr, 0, 1, bedbug_puts, F_RADHEX );
-
-    sprintf( prompt, "%08lx:    ", mem_addr );
-    readline( prompt );
-
-    if( console_buffer[ 0 ] && strcmp( console_buffer, "." ))
-    {
-      if(( instr = asmppc( mem_addr, console_buffer, &asm_err )) != 0 )
-      {
-       *(unsigned long *)mem_addr = instr;
-       mem_addr += 4;
-      }
-      else
-      {
-       printf( "*** Error: %s ***\n", asm_error_str( asm_err ));
-       rcode = 1;
-      }
-    }
-    else
-    {
-      break;
-    }
-  }
-  return rcode;
-} /* do_bedbug_asm */
-U_BOOT_CMD(
-       as,      2,      0,      do_bedbug_asm,
-       "as      - assemble memory\n",
-       "as <address>\n"
-);
+       long mem_addr;          /* Address to assemble into     */
+       unsigned long instr;    /* Machine code for text        */
+       char prompt[15];        /* Prompt string for user input */
+       int asm_err;            /* Error code from the assembler */
+
+       /* -------------------------------------------------- */
+       int rcode = 0;
+
+       if (argc < 2) {
+               printf ("Usage:\n%s\n", cmdtp->usage);
+               return 1;
+       }
+
+       printf ("\nEnter '.' when done\n");
+       mem_addr = simple_strtoul (argv[1], NULL, 16);
+
+       while (1) {
+               putc ('\n');
+               disppc ((unsigned char *) mem_addr, 0, 1, bedbug_puts,
+                       F_RADHEX);
+
+               sprintf (prompt, "%08lx:    ", mem_addr);
+               readline (prompt);
+
+               if (console_buffer[0] && strcmp (console_buffer, ".")) {
+                       if ((instr =
+                            asmppc (mem_addr, console_buffer,
+                                    &asm_err)) != 0) {
+                               *(unsigned long *) mem_addr = instr;
+                               mem_addr += 4;
+                       } else {
+                               printf ("*** Error: %s ***\n",
+                                       asm_error_str (asm_err));
+                               rcode = 1;
+                       }
+               } else {
+                       break;
+               }
+       }
+       return rcode;
+}                              /* do_bedbug_asm */
+
+U_BOOT_CMD (as, 2, 0, do_bedbug_asm,
+           "as      - assemble memory\n", "as <address>\n");
 \f
 /* ======================================================================
  * Used to set a break point from the interpreter.  Simply calls into the
  * CPU-specific break point set routine.
  * ====================================================================== */
 
-int do_bedbug_break (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_bedbug_break (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-  /* -------------------------------------------------- */
-  if( bug_ctx.do_break )
-    (*bug_ctx.do_break)( cmdtp, flag, argc, argv );
-    return 0;
-
-} /* do_bedbug_break */
-U_BOOT_CMD(
-       break,      3,      0,      do_bedbug_break,
-       "break   - set or clear a breakpoint\n",
-       " - Set or clear a breakpoint\n"
-       "break <address> - Break at an address\n"
-       "break off <bp#> - Disable breakpoint.\n"
-       "break show      - List breakpoints.\n"
-);
+       /* -------------------------------------------------- */
+       if (bug_ctx.do_break)
+               (*bug_ctx.do_break) (cmdtp, flag, argc, argv);
+       return 0;
+
+}                              /* do_bedbug_break */
+
+U_BOOT_CMD (break, 3, 0, do_bedbug_break,
+           "break   - set or clear a breakpoint\n",
+           " - Set or clear a breakpoint\n"
+           "break <address> - Break at an address\n"
+           "break off <bp#> - Disable breakpoint.\n"
+           "break show      - List breakpoints.\n");
 \f
 /* ======================================================================
  * Called from the debug interrupt routine.  Simply calls the CPU-specific
@@ -200,16 +196,16 @@ U_BOOT_CMD(
 
 void do_bedbug_breakpoint (struct pt_regs *regs)
 {
-  /* -------------------------------------------------- */
+       /* -------------------------------------------------- */
 
-  if( bug_ctx.break_isr )
-    (*bug_ctx.break_isr)( regs );
+       if (bug_ctx.break_isr)
+               (*bug_ctx.break_isr) (regs);
 
-  return;
-} /* do_bedbug_breakpoint */
+       return;
+}                              /* do_bedbug_breakpoint */
+\f
 
 
-\f
 /* ======================================================================
  * Called from the CPU-specific breakpoint handling routine.  Enter a
  * mini main loop until the stopped flag is cleared from the breakpoint
@@ -218,81 +214,77 @@ void do_bedbug_breakpoint (struct pt_regs *regs)
  * This handles the parts of the debugger that are common to all CPU's.
  * ====================================================================== */
 
-void bedbug_main_loop( unsigned long addr, struct pt_regs *regs )
+void bedbug_main_loop (unsigned long addr, struct pt_regs *regs)
 {
-  int          len;                    /* Length of command line */
-  int           flag;                   /* Command flags          */
-  int           rc = 0;                 /* Result from run_command*/
-  char          prompt_str[ 20 ];       /* Prompt string          */
-  static char   lastcommand[ CFG_CBSIZE ] = {0}; /* previous command */
-  /* -------------------------------------------------- */
+       int len;                /* Length of command line */
+       int flag;               /* Command flags          */
+       int rc = 0;             /* Result from run_command */
+       char prompt_str[20];    /* Prompt string          */
+       static char lastcommand[CFG_CBSIZE] = { 0 };    /* previous command */
+       /* -------------------------------------------------- */
 
-  if( bug_ctx.clear )
-    (*bug_ctx.clear)( bug_ctx.current_bp );
+       if (bug_ctx.clear)
+               (*bug_ctx.clear) (bug_ctx.current_bp);
 
-  printf( "Breakpoint %d: ", bug_ctx.current_bp );
-  disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX );
+       printf ("Breakpoint %d: ", bug_ctx.current_bp);
+       disppc ((unsigned char *) addr, 0, 1, bedbug_puts, F_RADHEX);
 
-  bug_ctx.stopped = 1;
-  bug_ctx.regs = regs;
+       bug_ctx.stopped = 1;
+       bug_ctx.regs = regs;
 
-  sprintf( prompt_str, "BEDBUG.%d =>", bug_ctx.current_bp );
+       sprintf (prompt_str, "BEDBUG.%d =>", bug_ctx.current_bp);
 
-  /* A miniature main loop */
-  while( bug_ctx.stopped )
-  {
-    len = readline( prompt_str );
+       /* A miniature main loop */
+       while (bug_ctx.stopped) {
+               len = readline (prompt_str);
 
-    flag = 0;  /* assume no special flags for now */
+               flag = 0;       /* assume no special flags for now */
 
-    if (len > 0)
-      strcpy( lastcommand, console_buffer );
-    else if( len == 0 )
-      flag |= CMD_FLAG_REPEAT;
+               if (len > 0)
+                       strcpy (lastcommand, console_buffer);
+               else if (len == 0)
+                       flag |= CMD_FLAG_REPEAT;
 
-    if (len == -1)
-      printf ("<INTERRUPT>\n");
-    else
-      rc = run_command( lastcommand, flag );
+               if (len == -1)
+                       printf ("<INTERRUPT>\n");
+               else
+                       rc = run_command (lastcommand, flag);
 
-    if (rc <= 0) {
-      /* invalid command or not repeatable, forget it */
-      lastcommand[0] = 0;
-    }
-  }
+               if (rc <= 0) {
+                       /* invalid command or not repeatable, forget it */
+                       lastcommand[0] = 0;
+               }
+       }
 
-  bug_ctx.regs = NULL;
-  bug_ctx.current_bp = 0;
+       bug_ctx.regs = NULL;
+       bug_ctx.current_bp = 0;
 
-  return;
-} /* bedbug_main_loop */
+       return;
+}                              /* bedbug_main_loop */
+\f
 
 
-\f
 /* ======================================================================
  * Interpreter command to continue from a breakpoint.  Just clears the
  * stopped flag in the context so that the breakpoint routine will
  * return.
  * ====================================================================== */
-int do_bedbug_continue (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-
+int do_bedbug_continue (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-  /* -------------------------------------------------- */
-
-  if( ! bug_ctx.stopped )
-  {
-    printf( "Not at a breakpoint\n" );
-    return 1;
-  }
-
-  bug_ctx.stopped = 0;
-  return 0;
-} /* do_bedbug_continue */
-U_BOOT_CMD(
-       continue,      1,      0,      do_bedbug_continue,
-       "continue- continue from a breakpoint\n",
-       " - continue from a breakpoint.\n"
-);
+       /* -------------------------------------------------- */
+
+       if (!bug_ctx.stopped) {
+               printf ("Not at a breakpoint\n");
+               return 1;
+       }
+
+       bug_ctx.stopped = 0;
+       return 0;
+}                              /* do_bedbug_continue */
+
+U_BOOT_CMD (continue, 1, 0, do_bedbug_continue,
+           "continue- continue from a breakpoint\n",
+           " - continue from a breakpoint.\n");
 \f
 /* ======================================================================
  * Interpreter command to continue to the next instruction, stepping into
@@ -300,31 +292,30 @@ U_BOOT_CMD(
  * the address passes control to the CPU-specific set breakpoint routine
  * for the current breakpoint number.
  * ====================================================================== */
-int do_bedbug_step (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_bedbug_step (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-  unsigned long addr;   /* Address to stop at */
-  /* -------------------------------------------------- */
-
-  if( ! bug_ctx.stopped )
-  {
-    printf( "Not at a breakpoint\n" );
-    return 1;
-  }
-
-  if( !find_next_address( (unsigned char *)&addr, FALSE, bug_ctx.regs ))
-    return 1;
-
-  if( bug_ctx.set )
-    (*bug_ctx.set)( bug_ctx.current_bp, addr );
-
-  bug_ctx.stopped = 0;
-  return 0;
-} /* do_bedbug_step */
-U_BOOT_CMD(
-       step,      1,      1,      do_bedbug_step,
-       "step    - single step execution.\n",
-       " - single step execution.\n"
-);
+       unsigned long addr;     /* Address to stop at */
+
+       /* -------------------------------------------------- */
+
+       if (!bug_ctx.stopped) {
+               printf ("Not at a breakpoint\n");
+               return 1;
+       }
+
+       if (!find_next_address ((unsigned char *) &addr, FALSE, bug_ctx.regs))
+               return 1;
+
+       if (bug_ctx.set)
+               (*bug_ctx.set) (bug_ctx.current_bp, addr);
+
+       bug_ctx.stopped = 0;
+       return 0;
+}                              /* do_bedbug_step */
+
+U_BOOT_CMD (step, 1, 1, do_bedbug_step,
+           "step    - single step execution.\n",
+           " - single step execution.\n");
 \f
 /* ======================================================================
  * Interpreter command to continue to the next instruction, stepping over
@@ -332,105 +323,97 @@ U_BOOT_CMD(
  * the address passes control to the CPU-specific set breakpoint routine
  * for the current breakpoint number.
  * ====================================================================== */
-int do_bedbug_next (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_bedbug_next (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-  unsigned long addr;   /* Address to stop at */
-  /* -------------------------------------------------- */
-
-  if( ! bug_ctx.stopped )
-  {
-    printf( "Not at a breakpoint\n" );
-    return 1;
-  }
-
-  if( !find_next_address( (unsigned char *)&addr, TRUE, bug_ctx.regs ))
-    return 1;
-
-  if( bug_ctx.set )
-    (*bug_ctx.set)( bug_ctx.current_bp, addr );
-
-  bug_ctx.stopped = 0;
-  return 0;
-} /* do_bedbug_next */
-U_BOOT_CMD(
-       next,      1,      1,      do_bedbug_next,
-       "next    - single step execution, stepping over subroutines.\n",
-       " - single step execution, stepping over subroutines.\n"
-);
+       unsigned long addr;     /* Address to stop at */
+
+       /* -------------------------------------------------- */
+
+       if (!bug_ctx.stopped) {
+               printf ("Not at a breakpoint\n");
+               return 1;
+       }
+
+       if (!find_next_address ((unsigned char *) &addr, TRUE, bug_ctx.regs))
+               return 1;
+
+       if (bug_ctx.set)
+               (*bug_ctx.set) (bug_ctx.current_bp, addr);
+
+       bug_ctx.stopped = 0;
+       return 0;
+}                              /* do_bedbug_next */
+
+U_BOOT_CMD (next, 1, 1, do_bedbug_next,
+           "next    - single step execution, stepping over subroutines.\n",
+           " - single step execution, stepping over subroutines.\n");
 \f
 /* ======================================================================
  * Interpreter command to print the current stack.  This assumes an EABI
  * architecture, so it starts with GPR R1 and works back up the stack.
  * ====================================================================== */
-int do_bedbug_stack (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_bedbug_stack (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
-  unsigned long sp;             /* Stack pointer                */
-  unsigned long func;           /* LR from stack                */
-  int           depth;          /* Stack iteration level        */
-  int           skip = 1;       /* Flag to skip the first entry */
-  unsigned long top;            /* Top of memory address        */
-  /* -------------------------------------------------- */
-
-  if( ! bug_ctx.stopped )
-  {
-    printf( "Not at a breakpoint\n" );
-    return 1;
-  }
-
-  top = gd->bd->bi_memstart + gd->bd->bi_memsize;
-  depth = 0;
-
-  printf( "Depth     PC\n" );
-  printf( "-----  --------\n" );
-  printf( "%5d  %08lx\n", depth++, bug_ctx.regs->nip );
-
-  sp = bug_ctx.regs->gpr[ 1 ];
-  func = *(unsigned long *)(sp+4);
-
-  while(( func < top ) && ( sp < top ))
-  {
-    if( !skip )
-      printf( "%5d  %08lx\n", depth++, func );
-    else
-      --skip;
-
-    sp = *(unsigned long *)sp;
-    func = *(unsigned long *)(sp+4);
-  }
-  return 0;
-} /* do_bedbug_stack */
-U_BOOT_CMD(
-       where,     1,      1,      do_bedbug_stack,
-       "where   - Print the running stack.\n",
-       " - Print the running stack.\n"
-);
+       unsigned long sp;       /* Stack pointer                */
+       unsigned long func;     /* LR from stack                */
+       int depth;              /* Stack iteration level        */
+       int skip = 1;           /* Flag to skip the first entry */
+       unsigned long top;      /* Top of memory address        */
+
+       /* -------------------------------------------------- */
+
+       if (!bug_ctx.stopped) {
+               printf ("Not at a breakpoint\n");
+               return 1;
+       }
+
+       top = gd->bd->bi_memstart + gd->bd->bi_memsize;
+       depth = 0;
+
+       printf ("Depth     PC\n");
+       printf ("-----  --------\n");
+       printf ("%5d  %08lx\n", depth++, bug_ctx.regs->nip);
+
+       sp = bug_ctx.regs->gpr[1];
+       func = *(unsigned long *) (sp + 4);
+
+       while ((func < top) && (sp < top)) {
+               if (!skip)
+                       printf ("%5d  %08lx\n", depth++, func);
+               else
+                       --skip;
+
+               sp = *(unsigned long *) sp;
+               func = *(unsigned long *) (sp + 4);
+       }
+       return 0;
+}                              /* do_bedbug_stack */
+
+U_BOOT_CMD (where, 1, 1, do_bedbug_stack,
+           "where   - Print the running stack.\n",
+           " - Print the running stack.\n");
 \f
 /* ======================================================================
  * Interpreter command to dump the registers.  Calls the CPU-specific
  * show registers routine.
  * ====================================================================== */
-int do_bedbug_rdump (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_bedbug_rdump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-  /* -------------------------------------------------- */
-
-  if( ! bug_ctx.stopped )
-  {
-    printf( "Not at a breakpoint\n" );
-    return 1;
-  }
-
-  show_regs( bug_ctx.regs );
-  return 0;
-} /* do_bedbug_rdump */
-U_BOOT_CMD(
-       rdump,     1,      1,      do_bedbug_rdump,
-       "rdump   - Show registers.\n",
-       " - Show registers.\n"
-);
+       /* -------------------------------------------------- */
+
+       if (!bug_ctx.stopped) {
+               printf ("Not at a breakpoint\n");
+               return 1;
+       }
+
+       show_regs (bug_ctx.regs);
+       return 0;
+}                              /* do_bedbug_rdump */
+
+U_BOOT_CMD (rdump, 1, 1, do_bedbug_rdump,
+           "rdump   - Show registers.\n", " - Show registers.\n");
 /* ====================================================================== */
-#endif /* CFG_CMD_BEDBUG */
+#endif /* CFG_CMD_BEDBUG */
 
 
 /*

diff --git a/common/cmd_boot.c b/common/cmd_boot.c
index 5b58d4e2f1ff1528ba397a10b068f805b0d37e79..e68f16f9da022aa805d5e5f79fec0fa7f9f229d2 100644 (file)
--- a/common/cmd_boot.c
+++ b/common/cmd_boot.c
@@ -28,14 +28,12 @@
 #include <command.h>
 #include <net.h>
 
-
-/* -------------------------------------------------------------------- */
+#if defined(CONFIG_I386)
+DECLARE_GLOBAL_DATA_PTR;
+#endif
 
 int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-#if defined(CONFIG_I386)
-       DECLARE_GLOBAL_DATA_PTR;
-#endif
        ulong   addr, rc;
        int     rcode = 0;
 

diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 8599a49d057b954f11d0cb73deb2f8124c2eeb78..fdf7180a19a87d4974b3b1a4cc131dba4ba432ba 100644 (file)
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -38,6 +38,8 @@
 #include <ft_build.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
  /*cmd_boot.c*/
  extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
@@ -140,6 +142,10 @@ static boot_os_Fcn do_bootm_lynxkdi;
 extern void lynxkdi_boot( image_header_t * );
 #endif
 
+#ifndef CFG_BOOTM_LEN
+#define CFG_BOOTM_LEN  0x800000        /* use 8MByte as default max gunzip size */
+#endif
+
 image_header_t header;
 
 ulong load_addr = CFG_LOAD_ADDR;               /* Default Load Address */
@@ -150,7 +156,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        ulong   addr;
        ulong   data, len, checksum;
        ulong  *len_ptr;
-       uint    unc_len = 0x400000;
+       uint    unc_len = CFG_BOOTM_LEN;
        int     i, verify;
        char    *name, *s;
        int     (*appl)(int, char *[]);
@@ -252,6 +258,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        if (hdr->ih_arch != IH_CPU_MICROBLAZE)
 #elif defined(__nios2__)
        if (hdr->ih_arch != IH_CPU_NIOS2)
+#elif defined(__blackfin__)
+       if (hdr->ih_arch != IH_CPU_BLACKFIN)
 #else
 # error Unknown CPU type
 #endif
@@ -463,7 +471,6 @@ U_BOOT_CMD(
 static void
 fixup_silent_linux ()
 {
-       DECLARE_GLOBAL_DATA_PTR;
        char buf[256], *start, *end;
        char *cmdline = getenv ("bootargs");
 
@@ -506,8 +513,6 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
                ulong   *len_ptr,
                int     verify)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong   sp;
        ulong   len, checksum;
        ulong   initrd_start, initrd_end;
@@ -606,7 +611,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 #endif /* CONFIG_MPC5xxx */
        }
 
-       kernel = (void (*)(bd_t *, ulong, ulong, ulong, ulong))hdr->ih_ep;
+       kernel = (void (*)(bd_t *, ulong, ulong, ulong, ulong)) ntohl(hdr->ih_ep);
 
        /*
         * Check if there is an initrd image
@@ -621,7 +626,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
                /* Copy header so we can blank CRC field for re-calculation */
                memmove (&header, (char *)addr, sizeof(image_header_t));
 
-               if (hdr->ih_magic  != IH_MAGIC) {
+               if (ntohl(hdr->ih_magic)  != IH_MAGIC) {
                        puts ("Bad Magic Number\n");
                        SHOW_BOOT_PROGRESS (-10);
                        do_reset (cmdtp, flag, argc, argv);
@@ -630,7 +635,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
                data = (ulong)&header;
                len  = sizeof(image_header_t);
 
-               checksum = hdr->ih_hcrc;
+               checksum = ntohl(hdr->ih_hcrc);
                hdr->ih_hcrc = 0;
 
                if (crc32 (0, (uchar *)data, len) != checksum) {
@@ -644,7 +649,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
                print_image_hdr (hdr);
 
                data = addr + sizeof(image_header_t);
-               len  = hdr->ih_size;
+               len  = ntohl(hdr->ih_size);
 
                if (verify) {
                        ulong csum = 0;
@@ -670,7 +675,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
                        csum = crc32 (0, (uchar *)data, len);
 #endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
 
-                       if (csum != hdr->ih_dcrc) {
+                       if (csum != ntohl(hdr->ih_dcrc)) {
                                puts ("Bad Data CRC\n");
                                SHOW_BOOT_PROGRESS (-12);
                                do_reset (cmdtp, flag, argc, argv);
@@ -819,7 +824,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
        (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
 
 #else
-       ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd);
+       ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd, initrd_start, initrd_end);
        /* ft_dump_blob(of_flat_tree); */
 
 #if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
@@ -828,12 +833,16 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
        /*
         * Linux Kernel Parameters:
         *   r3: ptr to OF flat tree, followed by the board info data
-        *   r4: initrd_start or 0 if no initrd
-        *   r5: initrd_end - unused if r4 is 0
-        *   r6: Start of command line string
-        *   r7: End   of command line string
+        *   r4: physical pointer to the kernel itself
+        *   r5: NULL
+        *   r6: NULL
+        *   r7: NULL
         */
-       (*kernel) ((bd_t *)of_flat_tree, initrd_start, initrd_end, cmd_start, cmd_end);
+       if (getenv("disable_of") != NULL)
+               (*kernel) ((bd_t *)of_flat_tree, initrd_start, initrd_end,
+                       cmd_start, cmd_end);
+       else
+               (*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0);
 
 #endif
 }
@@ -846,8 +855,6 @@ do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag,
                ulong   *len_ptr,
                int     verify)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        image_header_t *hdr = &header;
 
        void    (*loader)(bd_t *, image_header_t *, char *, char *);
@@ -902,7 +909,7 @@ do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag,
                cmdline = "";
        }
 
-       loader = (void (*)(bd_t *, image_header_t *, char *, char *)) hdr->ih_ep;
+       loader = (void (*)(bd_t *, image_header_t *, char *, char *)) ntohl(hdr->ih_ep);
 
        printf ("## Transferring control to NetBSD stage-2 loader (at address %08lx) ...\n",
                (ulong)loader);
@@ -931,7 +938,6 @@ do_bootm_artos (cmd_tbl_t *cmdtp, int flag,
                ulong   *len_ptr,
                int     verify)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        ulong top;
        char *s, *cmdline;
        char **fwenv, **ss;
@@ -1360,11 +1366,10 @@ static void
 do_bootm_rtems (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
                ulong addr, ulong *len_ptr, int verify)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        image_header_t *hdr = &header;
        void    (*entry_point)(bd_t *);
 
-       entry_point = (void (*)(bd_t *)) hdr->ih_ep;
+       entry_point = (void (*)(bd_t *)) ntohl(hdr->ih_ep);
 
        printf ("## Transferring control to RTEMS (at address %08lx) ...\n",
                (ulong)entry_point);
@@ -1387,7 +1392,7 @@ do_bootm_vxworks (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
        image_header_t *hdr = &header;
        char str[80];
 
-       sprintf(str, "%x", hdr->ih_ep); /* write entry-point into string */
+       sprintf(str, "%x", ntohl(hdr->ih_ep)); /* write entry-point into string */
        setenv("loadaddr", str);
        do_bootvx(cmdtp, 0, 0, NULL);
 }
@@ -1400,7 +1405,7 @@ do_bootm_qnxelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
        char *local_args[2];
        char str[16];
 
-       sprintf(str, "%x", hdr->ih_ep); /* write entry-point into string */
+       sprintf(str, "%x", ntohl(hdr->ih_ep)); /* write entry-point into string */
        local_args[0] = argv[0];
        local_args[1] = str;    /* and provide it via the arguments */
        do_bootelf(cmdtp, 0, 2, local_args);

diff --git a/common/cmd_date.c b/common/cmd_date.c
index a569d78cadc3f911e9ebd4cf5714f3565d8b0736..84932f75680893512e4cdf84d94b298ab0a8af25 100644 (file)
--- a/common/cmd_date.c
+++ b/common/cmd_date.c
@@ -28,6 +28,8 @@
 #include <command.h>
 #include <rtc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if (CONFIG_COMMANDS & CFG_CMD_DATE)
 
 const char *weekdays[] = {
@@ -40,7 +42,6 @@ int mk_date (char *, struct rtc_time *);
 
 int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-       DECLARE_GLOBAL_DATA_PTR;
        struct rtc_time tm;
        int rcode = 0;
 

diff --git a/common/cmd_doc.c b/common/cmd_doc.c
index 5e9bea30450683eea1d22c91d920676c3e5fe4e6..ab37516953195f1048d8817664cdb9ccd0e46f12 100644 (file)
--- a/common/cmd_doc.c
+++ b/common/cmd_doc.c
@@ -22,10 +22,7 @@
 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
 
 #include <linux/mtd/nftl.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ids.h>
 #include <linux/mtd/doc2000.h>
-#include <linux/mtd/nftl.h>
 
 #ifdef CFG_DOC_SUPPORT_2000
 #define DoC_is_2000(doc) (doc->ChipID == DOC_ChipID_Doc2k)
@@ -68,6 +65,32 @@ static struct DiskOnChip doc_dev_desc[CFG_MAX_DOC_DEVICE];
 /* Current DOC Device  */
 static int curr_device = -1;
 
+/* Supported NAND flash devices */
+static struct nand_flash_dev nand_flash_ids[] = {
+       {"Toshiba TC5816BDC",     NAND_MFR_TOSHIBA, 0x64, 21, 1, 2, 0x1000, 0},
+       {"Toshiba TC5832DC",      NAND_MFR_TOSHIBA, 0x6b, 22, 0, 2, 0x2000, 0},
+       {"Toshiba TH58V128DC",    NAND_MFR_TOSHIBA, 0x73, 24, 0, 2, 0x4000, 0},
+       {"Toshiba TC58256FT/DC",  NAND_MFR_TOSHIBA, 0x75, 25, 0, 2, 0x4000, 0},
+       {"Toshiba TH58512FT",     NAND_MFR_TOSHIBA, 0x76, 26, 0, 3, 0x4000, 0},
+       {"Toshiba TC58V32DC",     NAND_MFR_TOSHIBA, 0xe5, 22, 0, 2, 0x2000, 0},
+       {"Toshiba TC58V64AFT/DC", NAND_MFR_TOSHIBA, 0xe6, 23, 0, 2, 0x2000, 0},
+       {"Toshiba TC58V16BDC",    NAND_MFR_TOSHIBA, 0xea, 21, 1, 2, 0x1000, 0},
+       {"Toshiba TH58100FT",     NAND_MFR_TOSHIBA, 0x79, 27, 0, 3, 0x4000, 0},
+       {"Samsung KM29N16000",    NAND_MFR_SAMSUNG, 0x64, 21, 1, 2, 0x1000, 0},
+       {"Samsung unknown 4Mb",   NAND_MFR_SAMSUNG, 0x6b, 22, 0, 2, 0x2000, 0},
+       {"Samsung KM29U128T",     NAND_MFR_SAMSUNG, 0x73, 24, 0, 2, 0x4000, 0},
+       {"Samsung KM29U256T",     NAND_MFR_SAMSUNG, 0x75, 25, 0, 2, 0x4000, 0},
+       {"Samsung unknown 64Mb",  NAND_MFR_SAMSUNG, 0x76, 26, 0, 3, 0x4000, 0},
+       {"Samsung KM29W32000",    NAND_MFR_SAMSUNG, 0xe3, 22, 0, 2, 0x2000, 0},
+       {"Samsung unknown 4Mb",   NAND_MFR_SAMSUNG, 0xe5, 22, 0, 2, 0x2000, 0},
+       {"Samsung KM29U64000",    NAND_MFR_SAMSUNG, 0xe6, 23, 0, 2, 0x2000, 0},
+       {"Samsung KM29W16000",    NAND_MFR_SAMSUNG, 0xea, 21, 1, 2, 0x1000, 0},
+       {"Samsung K9F5616Q0C",    NAND_MFR_SAMSUNG, 0x45, 25, 0, 2, 0x4000, 1},
+       {"Samsung K9K1216Q0C",    NAND_MFR_SAMSUNG, 0x46, 26, 0, 3, 0x4000, 1},
+       {"Samsung K9F1G08U0M",    NAND_MFR_SAMSUNG, 0xf1, 27, 0, 2, 0, 0},
+       {NULL,}
+};
+
 /* ------------------------------------------------------------------------- */
 
 int do_doc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -249,7 +272,7 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
                print_image_hdr (hdr);
 
-               cnt = (hdr->ih_size + sizeof(image_header_t));
+               cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t));
                cnt -= SECTORSIZE;
        } else {
                puts ("\n** Bad Magic Number **\n");

diff --git a/common/cmd_elf.c b/common/cmd_elf.c
index eccf2e9e7b1aaf45ed3bb9393335c758a124e8c2..1d92bb37d3f9b4c1b435faa5b2651abcc7d88fb9 100644 (file)
--- a/common/cmd_elf.c
+++ b/common/cmd_elf.c
@@ -19,6 +19,9 @@
 #include <net.h>
 #include <elf.h>
 
+#if defined(CONFIG_WALNUT) || defined(CFG_VXWORKS_MAC_PTR)
+DECLARE_GLOBAL_DATA_PTR;
+#endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_ELF)
 
@@ -78,11 +81,6 @@ int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  * ====================================================================== */
 int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-#if defined(CONFIG_WALNUT)     || \
-    defined(CFG_VXWORKS_MAC_PTR)
-       DECLARE_GLOBAL_DATA_PTR;
-#endif
-
        unsigned long addr;             /* Address of image            */
        unsigned long bootaddr;         /* Address to put the bootline */
        char *bootline;                 /* Text of the bootline        */

diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c
index 02dffa38e5287c3d783fd887c183383dca17f420..03f4ce6d34c918d295091c8ac384161f0b42b234 100644 (file)
--- a/common/cmd_fdc.c
+++ b/common/cmd_fdc.c
@@ -836,13 +836,13 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
                return 1;
        }
        hdr = (image_header_t *)addr;
-       if (hdr->ih_magic  != IH_MAGIC) {
+       if (ntohl(hdr->ih_magic)  != IH_MAGIC) {
                printf ("Bad Magic Number\n");
                return 1;
        }
        print_image_hdr(hdr);
 
-       imsize= hdr->ih_size+sizeof(image_header_t);
+       imsize= ntohl(hdr->ih_size)+sizeof(image_header_t);
        nrofblk=imsize/512;
        if((imsize%512)>0)
                nrofblk++;

diff --git a/common/cmd_flash.c b/common/cmd_flash.c
index 0aa478306b8bd1988f4e66fc2e33111375128b0e..cb1c5bb432be9fb231078ad2175b27e9de8ae646 100644 (file)
--- a/common/cmd_flash.c
+++ b/common/cmd_flash.c
@@ -125,13 +125,16 @@ abbrev_spec (char *str, flash_info_t ** pinfo, int *psf, int *psl)
 static int
 addr_spec(char *arg1, char *arg2, ulong *addr_first, ulong *addr_last)
 {
-       char len_used = 0; /* indicates if the "start +length" form used */
        char *ep;
+       char len_used; /* indicates if the "start +length" form used */
+       char found;
+       ulong bank;
 
        *addr_first = simple_strtoul(arg1, &ep, 16);
        if (ep == arg1 || *ep != '\0')
                return -1;
 
+       len_used = 0;
        if (arg2 && *arg2 == '+'){
                len_used = 1;
                ++arg2;
@@ -142,9 +145,6 @@ addr_spec(char *arg1, char *arg2, ulong *addr_first, ulong *addr_last)
                return -1;
 
        if (len_used){
-               char found = 0;
-               ulong bank;
-
                /*
                 * *addr_last has the length, compute correct *addr_last
                 * XXX watch out for the integer overflow! Right now it is
@@ -159,6 +159,7 @@ addr_spec(char *arg1, char *arg2, ulong *addr_first, ulong *addr_last)
                 */
 
                /* find the end addr of the sector where the *addr_last is */
+               found = 0;
                for (bank = 0; bank < CFG_MAX_FLASH_BANKS && !found; ++bank){
                        int i;
                        flash_info_t *info = &flash_info[bank];
@@ -455,6 +456,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #ifdef CONFIG_HAS_DATAFLASH
        int status;
 #endif
+
        if (argc < 3) {
                printf ("Usage:\n%s\n", cmdtp->usage);
                return 1;
@@ -505,12 +507,10 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
                                info->protect[i] = p;
 #endif /* CFG_FLASH_PROTECTION */
                        }
-               }
-
 #if defined(CFG_FLASH_PROTECTION)
-               if (!rcode) puts (" done\n");
+                       if (!rcode) puts (" done\n");
 #endif /* CFG_FLASH_PROTECTION */
-
+               }
                return rcode;
        }
 
@@ -655,10 +655,10 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
 #endif /* CFG_FLASH_PROTECTION */
                                }
                        }
+               }
 #if defined(CFG_FLASH_PROTECTION)
-                       if (!rcode) putc ('\n');
+               puts (" done\n");
 #endif /* CFG_FLASH_PROTECTION */
-               }
 
                printf ("%sProtected %d sectors\n",
                        p ? "" : "Un-", protected);

diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index b67d35a5a4e89191f5c41aedbdccedf81706bf4c..41621ba982b029564a8e1311997e5a78a5400145 100644 (file)
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -60,6 +60,10 @@ unsigned long mips_io_port_base = 0;
 # define SHOW_BOOT_PROGRESS(arg)
 #endif
 
+#ifdef CONFIG_IDE_8xx_DIRECT
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 #ifdef __PPC__
 # define EIEIO         __asm__ volatile ("eieio")
 # define SYNC          __asm__ volatile ("sync")
@@ -498,7 +502,6 @@ void ide_init (void)
 {
 
 #ifdef CONFIG_IDE_8xx_DIRECT
-       DECLARE_GLOBAL_DATA_PTR;
        volatile immap_t *immr = (immap_t *)CFG_IMMR;
        volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
 #endif

diff --git a/common/cmd_immap.c b/common/cmd_immap.c
index 559d7b4c300dacfd2826f146c0a33447203f6387..fa79b45a3cc6182e5dbaf21185c07712691b72bf 100644 (file)
--- a/common/cmd_immap.c
+++ b/common/cmd_immap.c
@@ -41,6 +41,10 @@
 #include <asm/iopin_8260.h>
 #endif
 
+#if defined(CONFIG_8xx) || defined(CONFIG_8260)
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 static void
 unimplemented ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -450,10 +454,8 @@ static void prbrg (int n, uint val)
        uint div16 = (val & CPM_BRG_DIV16) != 0;
 
 #if defined(CONFIG_8xx)
-       DECLARE_GLOBAL_DATA_PTR;
        ulong clock = gd->cpu_clk;
 #elif defined(CONFIG_8260)
-       DECLARE_GLOBAL_DATA_PTR;
        ulong clock = gd->brg_clk;
 #endif
 

diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c
index 34920b1abd36a5fba91c5d49b092611599f2f46a..201c3c1553c3451c7f4402c7ad3a0127ad38bf9b 100644 (file)
--- a/common/cmd_jffs2.c
+++ b/common/cmd_jffs2.c
@@ -91,7 +91,6 @@
 #include <command.h>
 #include <malloc.h>
 #include <jffs2/jffs2.h>
-#include <linux/mtd/nand.h>
 #include <linux/list.h>
 #include <linux/ctype.h>
 
@@ -99,11 +98,19 @@
 
 #include <cramfs/cramfs_fs.h>
 
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#ifdef CFG_NAND_LEGACY
+#include <linux/mtd/nand_legacy.h>
+#else /* !CFG_NAND_LEGACY */
+#include <linux/mtd/nand.h>
+#include <nand.h>
+#endif /* !CFG_NAND_LEGACY */
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
 /* enable/disable debugging messages */
-#define        DEBUG
-#undef DEBUG
+#define        DEBUG_JFFS
+#undef DEBUG_JFFS
 
-#ifdef  DEBUG
+#ifdef  DEBUG_JFFS
 # define DEBUGF(fmt, args...)  printf(fmt ,##args)
 #else
 # define DEBUGF(fmt, args...)
@@ -123,7 +130,7 @@
 
 /* this flag needs to be set in part_info struct mask_flags
  * field for read-only partitions */
-#define MTD_WRITEABLE          1
+#define MTD_WRITEABLE_CMD              1
 
 #ifdef CONFIG_JFFS2_CMDLINE
 /* default values for mtdids and mtdparts variables */
@@ -365,10 +372,9 @@ static int part_validate_nand(struct mtdids *id, struct part_info *part)
 {
 #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
        /* info for NAND chips */
-       extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-       struct nand_chip *nand;
+       nand_info_t *nand;
 
-       nand = &nand_dev_desc[id->num];
+       nand = &nand_info[id->num];
 
        if ((unsigned long)(part->offset) % nand->erasesize) {
                printf("%s%d: partition (%s) start offset alignment incorrect\n",
@@ -464,7 +470,9 @@ static int part_del(struct mtd_device *dev, struct part_info *part)
                }
        }
 
+#ifdef CFG_NAND_LEGACY
        jffs2_free_cache(part);
+#endif
        list_del(&part->link);
        free(part);
        dev->num_parts--;
@@ -491,7 +499,9 @@ static void part_delall(struct list_head *head)
        list_for_each_safe(entry, n, head) {
                part_tmp = list_entry(entry, struct part_info, link);
 
+#ifdef CFG_NAND_LEGACY
                jffs2_free_cache(part_tmp);
+#endif
                list_del(entry);
                free(part_tmp);
        }
@@ -646,7 +656,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i
        /* test for options */
        mask_flags = 0;
        if (strncmp(p, "ro", 2) == 0) {
-               mask_flags |= MTD_WRITEABLE;
+               mask_flags |= MTD_WRITEABLE_CMD;
                p += 2;
        }
 
@@ -713,6 +723,7 @@ static int device_validate(u8 type, u8 num, u32 *size)
                if (num < CFG_MAX_FLASH_BANKS) {
                        extern flash_info_t flash_info[];
                        *size = flash_info[num].size;
+
                        return 0;
                }
 
@@ -724,8 +735,12 @@ static int device_validate(u8 type, u8 num, u32 *size)
        } else if (type == MTD_DEV_TYPE_NAND) {
 #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
                if (num < CFG_MAX_NAND_DEVICE) {
+#ifndef CFG_NAND_LEGACY
+                       *size = nand_info[num].size;
+#else
                        extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
                        *size = nand_dev_desc[num].totlen;
+#endif
                        return 0;
                }
 
@@ -1169,7 +1184,7 @@ static int generate_mtdparts(char *buf, u32 buflen)
                        }
 
                        /* ro mask flag */
-                       if (part->mask_flags && MTD_WRITEABLE) {
+                       if (part->mask_flags && MTD_WRITEABLE_CMD) {
                                len = 2;
                                if (len > maxlen)
                                        goto cleanup;

diff --git a/common/cmd_load.c b/common/cmd_load.c
index 749849711a007fcfc6817ddca3144e2e0c0dcfb2..2432ee20567ce8b014d6fb10a5b0d6e6c1692c29 100644 (file)
--- a/common/cmd_load.c
+++ b/common/cmd_load.c
@@ -29,10 +29,13 @@
 #include <s_record.h>
 #include <net.h>
 #include <exports.h>
+#include <xyzModem.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 #if (CONFIG_COMMANDS & CFG_CMD_LOADS)
 static ulong load_serial (ulong offset);
+static ulong load_serial_ymodem (ulong offset);
 static int read_record (char *buf, ulong len);
 # if (CONFIG_COMMANDS & CFG_CMD_SAVES)
 static int save_serial (ulong offset, ulong size);
@@ -53,7 +56,6 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        char *env_echo;
        int rcode = 0;
 #ifdef CFG_LOADS_BAUD_CHANGE
-       DECLARE_GLOBAL_DATA_PTR;
        int load_baudrate, current_baudrate;
 
        load_baudrate = current_baudrate = gd->baudrate;
@@ -213,7 +215,6 @@ load_serial (ulong offset)
 static int
 read_record (char *buf, ulong len)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        char *p;
        char c;
 
@@ -256,7 +257,6 @@ int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        ulong offset = 0;
        ulong size   = 0;
 #ifdef CFG_LOADS_BAUD_CHANGE
-       DECLARE_GLOBAL_DATA_PTR;
        int save_baudrate, current_baudrate;
 
        save_baudrate = current_baudrate = gd->baudrate;
@@ -433,8 +433,6 @@ char his_quote;      /* quote chars he'll use */
 
 int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong offset = 0;
        ulong addr;
        int load_baudrate, current_baudrate;
@@ -475,21 +473,31 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
                }
        }
 
-       printf ("## Ready for binary (kermit) download "
-               "to 0x%08lX at %d bps...\n",
-               offset,
-               load_baudrate);
-       addr = load_serial_bin (offset);
+       if (strcmp(argv[0],"loady")==0) {
+               printf ("## Ready for binary (ymodem) download "
+                       "to 0x%08lX at %d bps...\n",
+                       offset,
+                       load_baudrate);
+
+               addr = load_serial_ymodem (offset);
 
-       if (addr == ~0) {
-               load_addr = 0;
-               printf ("## Binary (kermit) download aborted\n");
-               rcode = 1;
        } else {
-               printf ("## Start Addr      = 0x%08lX\n", addr);
-               load_addr = addr;
-       }
 
+               printf ("## Ready for binary (kermit) download "
+                       "to 0x%08lX at %d bps...\n",
+                       offset,
+                       load_baudrate);
+               addr = load_serial_bin (offset);
+
+               if (addr == ~0) {
+                       load_addr = 0;
+                       printf ("## Binary (kermit) download aborted\n");
+                       rcode = 1;
+               } else {
+                       printf ("## Start Addr      = 0x%08lX\n", addr);
+                       load_addr = addr;
+               }
+       }
        if (load_baudrate != current_baudrate) {
                printf ("## Switch baudrate to %d bps and press ESC ...\n",
                        current_baudrate);
@@ -963,6 +971,68 @@ START:
        }
        return ((ulong) os_data_addr - (ulong) bin_start_address);
 }
+
+static int getcxmodem(void) {
+       if (tstc())
+               return (getc());
+       return -1;
+}
+static ulong load_serial_ymodem (ulong offset)
+{
+       int size;
+       char buf[32];
+       int err;
+       int res;
+       connection_info_t info;
+       char ymodemBuf[1024];
+       ulong store_addr = ~0;
+       ulong addr = 0;
+
+       size = 0;
+       info.mode = xyzModem_ymodem;
+       res = xyzModem_stream_open (&info, &err);
+       if (!res) {
+
+               while ((res =
+                       xyzModem_stream_read (ymodemBuf, 1024, &err)) > 0) {
+                       store_addr = addr + offset;
+                       size += res;
+                       addr += res;
+#ifndef CFG_NO_FLASH
+                       if (addr2info (store_addr)) {
+                               int rc;
+
+                               rc = flash_write ((char *) ymodemBuf,
+                                                 store_addr, res);
+                               if (rc != 0) {
+                                       flash_perror (rc);
+                                       return (~0);
+                               }
+                       } else
+#endif
+                       {
+                               memcpy ((char *) (store_addr), ymodemBuf,
+                                       res);
+                       }
+
+               }
+       } else {
+               printf ("%s\n", xyzModem_error (err));
+       }
+
+       xyzModem_stream_close (&err);
+       xyzModem_stream_terminate (false, &getcxmodem);
+
+
+       flush_cache (offset, size);
+
+       printf ("## Total Size      = 0x%08x = %d Bytes\n", size, size);
+       sprintf (buf, "%X", size);
+       setenv ("filesize", buf);
+
+       return offset;
+}
+
 #endif /* CFG_CMD_LOADB */
 
 /* -------------------------------------------------------------------- */
@@ -1022,6 +1092,14 @@ U_BOOT_CMD(
        " with offset 'off' and baudrate 'baud'\n"
 );
 
+U_BOOT_CMD(
+       loady, 3, 0,    do_load_serial_bin,
+       "loady   - load binary file over serial line (ymodem mode)\n",
+       "[ off ] [ baud ]\n"
+       "    - load binary file over serial line"
+       " with offset 'off' and baudrate 'baud'\n"
+);
+
 #endif /* CFG_CMD_LOADB */
 
 /* -------------------------------------------------------------------- */

diff --git a/common/cmd_log.c b/common/cmd_log.c
index efc9689c298b55675bde676c5708bb66917c9b3d..042a403026f00fa04b5cadd571ee3246b301d522 100644 (file)
--- a/common/cmd_log.c
+++ b/common/cmd_log.c
@@ -46,6 +46,8 @@
 #include <post.h>
 #include <logbuff.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_LOGBUFFER)
 
 /* Local prototypes */
@@ -73,7 +75,6 @@ static unsigned long *ext_logged_chars;
    in linux/kernel/printk */
 void logbuff_init_ptrs (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned long *ext_tag;
        unsigned long post_word;
        char *s;
@@ -139,8 +140,6 @@ static void logbuff_puts (const char *s)
 
 void logbuff_log(char *msg)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if ((gd->post_log_word & LOGBUFF_INITIALIZED)) {
                logbuff_printk (msg);
        } else {

diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index b0c01d1205aa50e45ea0e78964a5a3a0f3fd9b1f..21adb1b47868a42d51f58bf80bf346754e9deb05 100644 (file)
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -9,6 +9,387 @@
  */
 
 #include <common.h>
+
+
+#ifndef CFG_NAND_LEGACY
+/*
+ *
+ * New NAND support
+ *
+ */
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <command.h>
+#include <watchdog.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+# define SHOW_BOOT_PROGRESS(arg)       show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+#include <jffs2/jffs2.h>
+#include <nand.h>
+
+extern nand_info_t nand_info[];       /* info for NAND chips */
+
+static int nand_dump_oob(nand_info_t *nand, ulong off)
+{
+       return 0;
+}
+
+static int nand_dump(nand_info_t *nand, ulong off)
+{
+       int i;
+       u_char *buf, *p;
+
+       buf = malloc(nand->oobblock + nand->oobsize);
+       if (!buf) {
+               puts("No memory for page buffer\n");
+               return 1;
+       }
+       off &= ~(nand->oobblock - 1);
+       i = nand_read_raw(nand, buf, off, nand->oobblock, nand->oobsize);
+       if (i < 0) {
+               printf("Error (%d) reading page %08x\n", i, off);
+               free(buf);
+               return 1;
+       }
+       printf("Page %08x dump:\n", off);
+       i = nand->oobblock >> 4; p = buf;
+       while (i--) {
+               printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x"
+                       "  %02x %02x %02x %02x %02x %02x %02x %02x\n",
+                       p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
+                       p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]);
+               p += 16;
+       }
+       puts("OOB:\n");
+       i = nand->oobsize >> 3;
+       while (i--) {
+               printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
+                       p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+               p += 8;
+       }
+       free(buf);
+
+       return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void
+arg_off_size(int argc, char *argv[], ulong *off, ulong *size, ulong totsize)
+{
+       *off = 0;
+       *size = 0;
+
+#if defined(CONFIG_JFFS2_NAND) && defined(CFG_JFFS_CUSTOM_PART)
+       if (argc >= 1 && strcmp(argv[0], "partition") == 0) {
+               int part_num;
+               struct part_info *part;
+               const char *partstr;
+
+               if (argc >= 2)
+                       partstr = argv[1];
+               else
+                       partstr = getenv("partition");
+
+               if (partstr)
+                       part_num = (int)simple_strtoul(partstr, NULL, 10);
+               else
+                       part_num = 0;
+
+               part = jffs2_part_info(part_num);
+               if (part == NULL) {
+                       printf("\nInvalid partition %d\n", part_num);
+                       return;
+               }
+               *size = part->size;
+               *off = (ulong)part->offset;
+       } else
+#endif
+       {
+               if (argc >= 1)
+                       *off = (ulong)simple_strtoul(argv[0], NULL, 16);
+               else
+                       *off = 0;
+
+               if (argc >= 2)
+                       *size = (ulong)simple_strtoul(argv[1], NULL, 16);
+               else
+                       *size = totsize - *off;
+
+       }
+
+}
+
+int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+       int i, dev, ret;
+       ulong addr, off, size;
+       char *cmd, *s;
+       nand_info_t *nand;
+
+       /* at least two arguments please */
+       if (argc < 2)
+               goto usage;
+
+       cmd = argv[1];
+
+       if (strcmp(cmd, "info") == 0) {
+
+               putc('\n');
+               for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
+                       if (nand_info[i].name)
+                               printf("Device %d: %s, sector size %lu KiB\n",
+                                       i, nand_info[i].name,
+                                       nand_info[i].erasesize >> 10);
+               }
+               return 0;
+       }
+
+       if (strcmp(cmd, "device") == 0) {
+
+               if (argc < 3) {
+                       if ((nand_curr_device < 0) ||
+                           (nand_curr_device >= CFG_MAX_NAND_DEVICE))
+                               puts("\nno devices available\n");
+                       else
+                               printf("\nDevice %d: %s\n", nand_curr_device,
+                                       nand_info[nand_curr_device].name);
+                       return 0;
+               }
+               dev = (int)simple_strtoul(argv[2], NULL, 10);
+               if (dev < 0 || dev >= CFG_MAX_NAND_DEVICE || !nand_info[dev].name) {
+                       puts("No such device\n");
+                       return 1;
+               }
+               printf("Device %d: %s", dev, nand_info[dev].name);
+               puts("... is now current device\n");
+               nand_curr_device = dev;
+               return 0;
+       }
+
+       if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 &&
+           strncmp(cmd, "dump", 4) != 0 &&
+           strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0)
+               goto usage;
+
+       /* the following commands operate on the current device */
+       if (nand_curr_device < 0 || nand_curr_device >= CFG_MAX_NAND_DEVICE ||
+           !nand_info[nand_curr_device].name) {
+               puts("\nno devices available\n");
+               return 1;
+       }
+       nand = &nand_info[nand_curr_device];
+
+       if (strcmp(cmd, "bad") == 0) {
+               printf("\nDevice %d bad blocks:\n", nand_curr_device);
+               for (off = 0; off < nand->size; off += nand->erasesize)
+                       if (nand_block_isbad(nand, off))
+                               printf("  %08x\n", off);
+               return 0;
+       }
+
+       if (strcmp(cmd, "erase") == 0) {
+               arg_off_size(argc - 2, argv + 2, &off, &size, nand->size);
+               if (off == 0 && size == 0)
+                       return 1;
+
+               printf("\nNAND erase: device %d offset 0x%x, size 0x%x ",
+                      nand_curr_device, off, size);
+               ret = nand_erase(nand, off, size);
+               printf("%s\n", ret ? "ERROR" : "OK");
+
+               return ret == 0 ? 0 : 1;
+       }
+
+       if (strncmp(cmd, "dump", 4) == 0) {
+               if (argc < 3)
+                       goto usage;
+
+               s = strchr(cmd, '.');
+               off = (int)simple_strtoul(argv[2], NULL, 16);
+
+               if (s != NULL && strcmp(s, ".oob") == 0)
+                       ret = nand_dump_oob(nand, off);
+               else
+                       ret = nand_dump(nand, off);
+
+               return ret == 0 ? 1 : 0;
+
+       }
+
+       /* read write */
+       if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) {
+               if (argc < 4)
+                       goto usage;
+/*
+               s = strchr(cmd, '.');
+               clean = CLEAN_NONE;
+               if (s != NULL) {
+                       if (strcmp(s, ".jffs2") == 0 || strcmp(s, ".e") == 0
+                           || strcmp(s, ".i"))
+                               clean = CLEAN_JFFS2;
+               }
+*/
+               addr = (ulong)simple_strtoul(argv[2], NULL, 16);
+
+               arg_off_size(argc - 3, argv + 3, &off, &size, nand->size);
+               if (off == 0 && size == 0)
+                       return 1;
+
+               i = strncmp(cmd, "read", 4) == 0;       /* 1 = read, 0 = write */
+               printf("\nNAND %s: device %d offset %u, size %u ... ",
+                      i ? "read" : "write", nand_curr_device, off, size);
+
+               if (i)
+                       ret = nand_read(nand, off, &size, (u_char *)addr);
+               else
+                       ret = nand_write(nand, off, &size, (u_char *)addr);
+
+               printf(" %d bytes %s: %s\n", size,
+                      i ? "read" : "written", ret ? "ERROR" : "OK");
+
+               return ret == 0 ? 0 : 1;
+       }
+usage:
+       printf("Usage:\n%s\n", cmdtp->usage);
+       return 1;
+}
+
+U_BOOT_CMD(nand, 5, 1, do_nand,
+       "nand    - NAND sub-system\n",
+       "info                  - show available NAND devices\n"
+       "nand device [dev]     - show or set current device\n"
+       "nand read[.jffs2]     - addr off size\n"
+       "nand write[.jffs2]    - addr off size - read/write `size' bytes starting\n"
+       "    at offset `off' to/from memory address `addr'\n"
+       "nand erase [clean] [off size] - erase `size' bytes from\n"
+       "    offset `off' (entire device if not specified)\n"
+       "nand bad - show bad blocks\n"
+       "nand dump[.oob] off - dump page\n"
+       "nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n"
+       "nand markbad off - mark bad block at offset (UNSAFE)\n"
+       "nand biterr off - make a bit error at offset (UNSAFE)\n");
+
+int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+       char *boot_device = NULL;
+       char *ep;
+       int dev;
+       int r;
+       ulong addr, cnt, offset = 0;
+       image_header_t *hdr;
+       nand_info_t *nand;
+
+       switch (argc) {
+       case 1:
+               addr = CFG_LOAD_ADDR;
+               boot_device = getenv("bootdevice");
+               break;
+       case 2:
+               addr = simple_strtoul(argv[1], NULL, 16);
+               boot_device = getenv("bootdevice");
+               break;
+       case 3:
+               addr = simple_strtoul(argv[1], NULL, 16);
+               boot_device = argv[2];
+               break;
+       case 4:
+               addr = simple_strtoul(argv[1], NULL, 16);
+               boot_device = argv[2];
+               offset = simple_strtoul(argv[3], NULL, 16);
+               break;
+       default:
+               printf("Usage:\n%s\n", cmdtp->usage);
+               SHOW_BOOT_PROGRESS(-1);
+               return 1;
+       }
+
+       if (!boot_device) {
+               puts("\n** No boot device **\n");
+               SHOW_BOOT_PROGRESS(-1);
+               return 1;
+       }
+
+       dev = simple_strtoul(boot_device, &ep, 16);
+
+       if (dev < 0 || dev >= CFG_MAX_NAND_DEVICE || !nand_info[dev].name) {
+               printf("\n** Device %d not available\n", dev);
+               SHOW_BOOT_PROGRESS(-1);
+               return 1;
+       }
+
+       nand = &nand_info[dev];
+       printf("\nLoading from device %d: %s (offset 0x%lx)\n",
+              dev, nand->name, offset);
+
+       cnt = nand->oobblock;
+       r = nand_read(nand, offset, &cnt, (u_char *) addr);
+       if (r) {
+               printf("** Read error on %d\n", dev);
+               SHOW_BOOT_PROGRESS(-1);
+               return 1;
+       }
+
+       hdr = (image_header_t *) addr;
+
+       if (ntohl(hdr->ih_magic) != IH_MAGIC) {
+               printf("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
+               SHOW_BOOT_PROGRESS(-1);
+               return 1;
+       }
+
+       print_image_hdr(hdr);
+
+       cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t));
+
+       r = nand_read(nand, offset, &cnt, (u_char *) addr);
+       if (r) {
+               printf("** Read error on %d\n", dev);
+               SHOW_BOOT_PROGRESS(-1);
+               return 1;
+       }
+
+       /* Loading ok, update default load address */
+
+       load_addr = addr;
+
+       /* Check if we should attempt an auto-start */
+       if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) {
+               char *local_args[2];
+               extern int do_bootm(cmd_tbl_t *, int, int, char *[]);
+
+               local_args[0] = argv[0];
+               local_args[1] = NULL;
+
+               printf("Automatic boot of image at addr 0x%08lx ...\n", addr);
+
+               do_bootm(cmdtp, 0, 1, local_args);
+               return 1;
+       }
+       return 0;
+}
+
+U_BOOT_CMD(nboot, 4, 1, do_nandboot,
+       "nboot   - boot from NAND device\n", "loadAddr dev\n");
+
+
+#endif                         /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
+
+#else /* CFG_NAND_LEGACY */
+/*
+ *
+ * Legacy NAND support - to be phased out
+ *
+ */
 #include <command.h>
 #include <malloc.h>
 #include <asm/io.h>
@@ -22,10 +403,11 @@
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
-
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
+#if 0
 #include <linux/mtd/nand_ids.h>
 #include <jffs2/jffs2.h>
+#endif
 
 #ifdef CONFIG_OMAP1510
 void archflashwp(void *archdata, int wp);
@@ -33,15 +415,6 @@ void archflashwp(void *archdata, int wp);
 
 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
 
-/*
- * Definition of the out of band configuration structure
- */
-struct nand_oob_config {
-       int ecc_pos[6];         /* position of ECC bytes inside oob */
-       int badblock_pos;       /* position of bad block flag inside oob -1 = inactive */
-       int eccvalid_pos;       /* position of ECC valid flag inside oob -1 = inactive */
-} oob_config = { {0}, 0, 0};
-
 #undef NAND_DEBUG
 #undef PSYCHO_DEBUG
 
@@ -63,41 +436,28 @@ struct nand_oob_config {
 #define CONFIG_MTD_NAND_ECC  /* enable ECC */
 #define CONFIG_MTD_NAND_ECC_JFFS2
 
-/* bits for nand_rw() `cmd'; or together as needed */
+/* bits for nand_legacy_rw() `cmd'; or together as needed */
 #define NANDRW_READ    0x01
 #define NANDRW_WRITE   0x00
 #define NANDRW_JFFS2   0x02
 #define NANDRW_JFFS2_SKIP      0x04
 
 /*
- * Function Prototypes
+ * Imports from nand_legacy.c
  */
-static void nand_print(struct nand_chip *nand);
-int nand_rw (struct nand_chip* nand, int cmd,
-           size_t start, size_t len,
-           size_t * retlen, u_char * buf);
-int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean);
-static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
-                size_t * retlen, u_char *buf, u_char *ecc_code);
-static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
-                          size_t * retlen, const u_char * buf, u_char * ecc_code);
-static void nand_print_bad(struct nand_chip *nand);
-static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
-                size_t * retlen, u_char * buf);
-static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
-                size_t * retlen, const u_char * buf);
-static int NanD_WaitReady(struct nand_chip *nand, int ale_wait);
-#ifdef CONFIG_MTD_NAND_ECC
-static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc);
-static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code);
-#endif
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+extern int curr_device;
+extern int nand_legacy_erase(struct nand_chip *nand, size_t ofs,
+                           size_t len, int clean);
+extern int nand_legacy_rw(struct nand_chip *nand, int cmd, size_t start,
+                        size_t len, size_t *retlen, u_char *buf);
+extern void nand_print(struct nand_chip *nand);
+extern void nand_print_bad(struct nand_chip *nand);
+extern int nand_read_oob(struct nand_chip *nand, size_t ofs,
+                              size_t len, size_t *retlen, u_char *buf);
+extern int nand_write_oob(struct nand_chip *nand, size_t ofs,
+                               size_t len, size_t *retlen, const u_char *buf);
 
-struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}};
-
-/* Current NAND Device */
-static int curr_device = -1;
-
-/* ------------------------------------------------------------------------- */
 
 int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -174,7 +534,7 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
                printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
                        curr_device, off, size);
 
-               ret = nand_erase (nand, off, size, 1);
+               ret = nand_legacy_erase (nand, off, size, 1);
 
                printf("%s\n", ret ? "ERROR" : "OK");
 
@@ -240,7 +600,7 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
                        (cmd & NANDRW_READ) ? "read" : "write",
                        curr_device, off, size);
 
-               ret = nand_rw(nand_dev_desc + curr_device, cmd, off, size,
+               ret = nand_legacy_rw(nand_dev_desc + curr_device, cmd, off, size,
                             (size_t *)&total, (u_char*)addr);
 
                printf (" %d bytes %s: %s\n", total,
@@ -258,7 +618,8 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
                printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
                        curr_device, off, size);
 
-               ret = nand_erase (nand_dev_desc + curr_device, off, size, clean);
+               ret = nand_legacy_erase (nand_dev_desc + curr_device,
+                                       off, size, clean);
 
                printf("%s\n", ret ? "ERROR" : "OK");
 
@@ -340,8 +701,8 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
                dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR,
                offset);
 
-       if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset,
-                   SECTORSIZE, NULL, (u_char *)addr)) {
+       if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset,
+                       SECTORSIZE, NULL, (u_char *)addr)) {
                printf ("** Read error on %d\n", dev);
                SHOW_BOOT_PROGRESS (-1);
                return 1;
@@ -356,13 +717,14 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
                cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t));
                cnt -= SECTORSIZE;
        } else {
-               printf ("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
+               printf ("\n** Bad Magic Number 0x%x **\n", ntohl(hdr->ih_magic));
                SHOW_BOOT_PROGRESS (-1);
                return 1;
        }
 
-       if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset + SECTORSIZE, cnt,
-                   NULL, (u_char *)(addr+SECTORSIZE))) {
+       if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ,
+                       offset + SECTORSIZE, cnt, NULL,
+                       (u_char *)(addr+SECTORSIZE))) {
                printf ("** Read error on %d\n", dev);
                SHOW_BOOT_PROGRESS (-1);
                return 1;
@@ -394,1505 +756,6 @@ U_BOOT_CMD(
        "loadAddr dev\n"
 );
 
-/* returns 0 if block containing pos is OK:
- *             valid erase block and
- *             not marked bad, or no bad mark position is specified
- * returns 1 if marked bad or otherwise invalid
- */
-int check_block (struct nand_chip *nand, unsigned long pos)
-{
-       size_t retlen;
-       uint8_t oob_data;
-       uint16_t oob_data16[6];
-       int page0 = pos & (-nand->erasesize);
-       int page1 = page0 + nand->oobblock;
-       int badpos = oob_config.badblock_pos;
-
-       if (pos >= nand->totlen)
-               return 1;
-
-       if (badpos < 0)
-               return 0;       /* no way to check, assume OK */
-
-       if (nand->bus16) {
-               if (nand_read_oob(nand, (page0 + 0), 12, &retlen, (uint8_t *)oob_data16)
-                   || (oob_data16[2] & 0xff00) != 0xff00)
-                       return 1;
-               if (nand_read_oob(nand, (page1 + 0), 12, &retlen, (uint8_t *)oob_data16)
-                   || (oob_data16[2] & 0xff00) != 0xff00)
-                       return 1;
-       } else {
-               /* Note - bad block marker can be on first or second page */
-               if (nand_read_oob(nand, page0 + badpos, 1, &retlen, (unsigned char *)&oob_data)
-                   || oob_data != 0xff
-                   || nand_read_oob (nand, page1 + badpos, 1, &retlen, (unsigned char *)&oob_data)
-                   || oob_data != 0xff)
-                       return 1;
-       }
-
-       return 0;
-}
-
-/* print bad blocks in NAND flash */
-static void nand_print_bad(struct nand_chip* nand)
-{
-       unsigned long pos;
-
-       for (pos = 0; pos < nand->totlen; pos += nand->erasesize) {
-               if (check_block(nand, pos))
-                       printf(" 0x%8.8lx\n", pos);
-       }
-       puts("\n");
-}
-
-/* cmd: 0: NANDRW_WRITE                        write, fail on bad block
- *     1: NANDRW_READ                  read, fail on bad block
- *     2: NANDRW_WRITE | NANDRW_JFFS2  write, skip bad blocks
- *     3: NANDRW_READ | NANDRW_JFFS2   read, data all 0xff for bad blocks
- *      7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks
- */
-int nand_rw (struct nand_chip* nand, int cmd,
-           size_t start, size_t len,
-           size_t * retlen, u_char * buf)
-{
-       int ret = 0, n, total = 0;
-       char eccbuf[6];
-       /* eblk (once set) is the start of the erase block containing the
-        * data being processed.
-        */
-       unsigned long eblk = ~0;        /* force mismatch on first pass */
-       unsigned long erasesize = nand->erasesize;
-
-       while (len) {
-               if ((start & (-erasesize)) != eblk) {
-                       /* have crossed into new erase block, deal with
-                        * it if it is sure marked bad.
-                        */
-                       eblk = start & (-erasesize); /* start of block */
-                       if (check_block(nand, eblk)) {
-                               if (cmd == (NANDRW_READ | NANDRW_JFFS2)) {
-                                       while (len > 0 &&
-                                              start - eblk < erasesize) {
-                                               *(buf++) = 0xff;
-                                               ++start;
-                                               ++total;
-                                               --len;
-                                       }
-                                       continue;
-                               } else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) {
-                                       start += erasesize;
-                                       continue;
-                               } else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) {
-                                       /* skip bad block */
-                                       start += erasesize;
-                                       continue;
-                               } else {
-                                       ret = 1;
-                                       break;
-                               }
-                       }
-               }
-               /* The ECC will not be calculated correctly if
-                  less than 512 is written or read */
-               /* Is request at least 512 bytes AND it starts on a proper boundry */
-               if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200))
-                       printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n");
-
-               if (cmd & NANDRW_READ) {
-                       ret = nand_read_ecc(nand, start,
-                                          min(len, eblk + erasesize - start),
-                                          (size_t *)&n, (u_char*)buf, (u_char *)eccbuf);
-               } else {
-                       ret = nand_write_ecc(nand, start,
-                                           min(len, eblk + erasesize - start),
-                                           (size_t *)&n, (u_char*)buf, (u_char *)eccbuf);
-               }
-
-               if (ret)
-                       break;
-
-               start  += n;
-               buf   += n;
-               total += n;
-               len   -= n;
-       }
-       if (retlen)
-               *retlen = total;
-
-       return ret;
-}
-
-static void nand_print(struct nand_chip *nand)
-{
-       if (nand->numchips > 1) {
-               printf("%s at 0x%lx,\n"
-                      "\t  %d chips %s, size %d MB, \n"
-                      "\t  total size %ld MB, sector size %ld kB\n",
-                      nand->name, nand->IO_ADDR, nand->numchips,
-                      nand->chips_name, 1 << (nand->chipshift - 20),
-                      nand->totlen >> 20, nand->erasesize >> 10);
-       }
-       else {
-               printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR);
-               print_size(nand->totlen, ", ");
-               print_size(nand->erasesize, " sector)\n");
-       }
-}
-
-/* ------------------------------------------------------------------------- */
-
-static int NanD_WaitReady(struct nand_chip *nand, int ale_wait)
-{
-       /* This is inline, to optimise the common case, where it's ready instantly */
-       int ret = 0;
-
-#ifdef NAND_NO_RB      /* in config file, shorter delays currently wrap accesses */
-       if(ale_wait)
-               NAND_WAIT_READY(nand);  /* do the worst case 25us wait */
-       else
-               udelay(10);
-#else  /* has functional r/b signal */
-       NAND_WAIT_READY(nand);
-#endif
-       return ret;
-}
-
-/* NanD_Command: Send a flash command to the flash chip */
-
-static inline int NanD_Command(struct nand_chip *nand, unsigned char command)
-{
-       unsigned long nandptr = nand->IO_ADDR;
-
-       /* Assert the CLE (Command Latch Enable) line to the flash chip */
-       NAND_CTL_SETCLE(nandptr);
-
-       /* Send the command */
-       WRITE_NAND_COMMAND(command, nandptr);
-
-       /* Lower the CLE line */
-       NAND_CTL_CLRCLE(nandptr);
-
-#ifdef NAND_NO_RB
-       if(command == NAND_CMD_RESET){
-               u_char ret_val;
-               NanD_Command(nand, NAND_CMD_STATUS);
-               do {
-                       ret_val = READ_NAND(nandptr);/* wait till ready */
-               } while((ret_val & 0x40) != 0x40);
-       }
-#endif
-       return NanD_WaitReady(nand, 0);
-}
-
-/* NanD_Address: Set the current address for the flash chip */
-
-static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs)
-{
-       unsigned long nandptr;
-       int i;
-
-       nandptr = nand->IO_ADDR;
-
-       /* Assert the ALE (Address Latch Enable) line to the flash chip */
-       NAND_CTL_SETALE(nandptr);
-
-       /* Send the address */
-       /* Devices with 256-byte page are addressed as:
-        * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31)
-        * there is no device on the market with page256
-        * and more than 24 bits.
-        * Devices with 512-byte page are addressed as:
-        * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31)
-        * 25-31 is sent only if the chip support it.
-        * bit 8 changes the read command to be sent
-        * (NAND_CMD_READ0 or NAND_CMD_READ1).
-        */
-
-       if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE)
-               WRITE_NAND_ADDRESS(ofs, nandptr);
-
-       ofs = ofs >> nand->page_shift;
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
 
-       if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) {
-               for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8) {
-                       WRITE_NAND_ADDRESS(ofs, nandptr);
-               }
-       }
-
-       /* Lower the ALE line */
-       NAND_CTL_CLRALE(nandptr);
-
-       /* Wait for the chip to respond */
-       return NanD_WaitReady(nand, 1);
-}
-
-/* NanD_SelectChip: Select a given flash chip within the current floor */
-
-static inline int NanD_SelectChip(struct nand_chip *nand, int chip)
-{
-       /* Wait for it to be ready */
-       return NanD_WaitReady(nand, 0);
-}
-
-/* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */
-
-static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip)
-{
-       int mfr, id, i;
-
-       NAND_ENABLE_CE(nand);  /* set pin low */
-       /* Reset the chip */
-       if (NanD_Command(nand, NAND_CMD_RESET)) {
-#ifdef NAND_DEBUG
-               printf("NanD_Command (reset) for %d,%d returned true\n",
-                      floor, chip);
-#endif
-               NAND_DISABLE_CE(nand);  /* set pin high */
-               return 0;
-       }
-
-       /* Read the NAND chip ID: 1. Send ReadID command */
-       if (NanD_Command(nand, NAND_CMD_READID)) {
-#ifdef NAND_DEBUG
-               printf("NanD_Command (ReadID) for %d,%d returned true\n",
-                      floor, chip);
-#endif
-               NAND_DISABLE_CE(nand);  /* set pin high */
-               return 0;
-       }
-
-       /* Read the NAND chip ID: 2. Send address byte zero */
-       NanD_Address(nand, ADDR_COLUMN, 0);
-
-       /* Read the manufacturer and device id codes from the device */
-
-       mfr = READ_NAND(nand->IO_ADDR);
-
-       id = READ_NAND(nand->IO_ADDR);
-
-       NAND_DISABLE_CE(nand);  /* set pin high */
-
-#ifdef NAND_DEBUG
-       printf("NanD_Command (ReadID) got %x %x\n", mfr, id);
-#endif
-       if (mfr == 0xff || mfr == 0) {
-               /* No response - return failure */
-               return 0;
-       }
-
-       /* Check it's the same as the first chip we identified.
-        * M-Systems say that any given nand_chip device should only
-        * contain _one_ type of flash part, although that's not a
-        * hardware restriction. */
-       if (nand->mfr) {
-               if (nand->mfr == mfr && nand->id == id) {
-                       return 1;       /* This is another the same the first */
-               } else {
-                       printf("Flash chip at floor %d, chip %d is different:\n",
-                              floor, chip);
-               }
-       }
-
-       /* Print and store the manufacturer and ID codes. */
-       for (i = 0; nand_flash_ids[i].name != NULL; i++) {
-               if (mfr == nand_flash_ids[i].manufacture_id &&
-                   id == nand_flash_ids[i].model_id) {
-#ifdef NAND_DEBUG
-                       printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, "
-                              "Chip ID: 0x%2.2X (%s)\n", mfr, id,
-                              nand_flash_ids[i].name);
-#endif
-                       if (!nand->mfr) {
-                               nand->mfr = mfr;
-                               nand->id = id;
-                               nand->chipshift =
-                                   nand_flash_ids[i].chipshift;
-                               nand->page256 = nand_flash_ids[i].page256;
-                               nand->eccsize = 256;
-                               if (nand->page256) {
-                                       nand->oobblock = 256;
-                                       nand->oobsize = 8;
-                                       nand->page_shift = 8;
-                               } else {
-                                       nand->oobblock = 512;
-                                       nand->oobsize = 16;
-                                       nand->page_shift = 9;
-                               }
-                               nand->pageadrlen = nand_flash_ids[i].pageadrlen;
-                               nand->erasesize  = nand_flash_ids[i].erasesize;
-                               nand->chips_name = nand_flash_ids[i].name;
-                               nand->bus16      = nand_flash_ids[i].bus16;
-                               return 1;
-                       }
-                       return 0;
-               }
-       }
-
-
-#ifdef NAND_DEBUG
-       /* We haven't fully identified the chip. Print as much as we know. */
-       printf("Unknown flash chip found: %2.2X %2.2X\n",
-              id, mfr);
-#endif
-
-       return 0;
-}
-
-/* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */
-
-static void NanD_ScanChips(struct nand_chip *nand)
-{
-       int floor, chip;
-       int numchips[NAND_MAX_FLOORS];
-       int maxchips = NAND_MAX_CHIPS;
-       int ret = 1;
-
-       nand->numchips = 0;
-       nand->mfr = 0;
-       nand->id = 0;
-
-
-       /* For each floor, find the number of valid chips it contains */
-       for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
-               ret = 1;
-               numchips[floor] = 0;
-               for (chip = 0; chip < maxchips && ret != 0; chip++) {
-
-                       ret = NanD_IdentChip(nand, floor, chip);
-                       if (ret) {
-                               numchips[floor]++;
-                               nand->numchips++;
-                       }
-               }
-       }
-
-       /* If there are none at all that we recognise, bail */
-       if (!nand->numchips) {
-#ifdef NAND_DEBUG
-               puts ("No NAND flash chips recognised.\n");
-#endif
-               return;
-       }
-
-       /* Allocate an array to hold the information for each chip */
-       nand->chips = malloc(sizeof(struct Nand) * nand->numchips);
-       if (!nand->chips) {
-               puts ("No memory for allocating chip info structures\n");
-               return;
-       }
-
-       ret = 0;
-
-       /* Fill out the chip array with {floor, chipno} for each
-        * detected chip in the device. */
-       for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
-               for (chip = 0; chip < numchips[floor]; chip++) {
-                       nand->chips[ret].floor = floor;
-                       nand->chips[ret].chip = chip;
-                       nand->chips[ret].curadr = 0;
-                       nand->chips[ret].curmode = 0x50;
-                       ret++;
-               }
-       }
-
-       /* Calculate and print the total size of the device */
-       nand->totlen = nand->numchips * (1 << nand->chipshift);
-
-#ifdef NAND_DEBUG
-       printf("%d flash chips found. Total nand_chip size: %ld MB\n",
-              nand->numchips, nand->totlen >> 20);
-#endif
-}
-
-/* we need to be fast here, 1 us per read translates to 1 second per meg */
-static void NanD_ReadBuf (struct nand_chip *nand, u_char * data_buf, int cntr)
-{
-       unsigned long nandptr = nand->IO_ADDR;
-
-       NanD_Command (nand, NAND_CMD_READ0);
-
-       if (nand->bus16) {
-               u16 val;
-
-               while (cntr >= 16) {
-                       val = READ_NAND (nandptr);
-                       *data_buf++ = val & 0xff;
-                       *data_buf++ = val >> 8;
-                       val = READ_NAND (nandptr);
-                       *data_buf++ = val & 0xff;
-                       *data_buf++ = val >> 8;
-                       val = READ_NAND (nandptr);
-                       *data_buf++ = val & 0xff;
-                       *data_buf++ = val >> 8;
-                       val = READ_NAND (nandptr);
-                       *data_buf++ = val & 0xff;
-                       *data_buf++ = val >> 8;
-                       val = READ_NAND (nandptr);
-                       *data_buf++ = val & 0xff;
-                       *data_buf++ = val >> 8;
-                       val = READ_NAND (nandptr);
-                       *data_buf++ = val & 0xff;
-                       *data_buf++ = val >> 8;
-                       val = READ_NAND (nandptr);
-                       *data_buf++ = val & 0xff;
-                       *data_buf++ = val >> 8;
-                       val = READ_NAND (nandptr);
-                       *data_buf++ = val & 0xff;
-                       *data_buf++ = val >> 8;
-                       cntr -= 16;
-               }
-
-               while (cntr > 0) {
-                       val = READ_NAND (nandptr);
-                       *data_buf++ = val & 0xff;
-                       *data_buf++ = val >> 8;
-                       cntr -= 2;
-               }
-       } else {
-               while (cntr >= 16) {
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       *data_buf++ = READ_NAND (nandptr);
-                       cntr -= 16;
-               }
-
-               while (cntr > 0) {
-                       *data_buf++ = READ_NAND (nandptr);
-                       cntr--;
-               }
-       }
-}
-
-/*
- * NAND read with ECC
- */
-static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
-                size_t * retlen, u_char *buf, u_char *ecc_code)
-{
-       int col, page;
-       int ecc_status = 0;
-#ifdef CONFIG_MTD_NAND_ECC
-       int j;
-       int ecc_failed = 0;
-       u_char *data_poi;
-       u_char ecc_calc[6];
-#endif
-
-       /* Do not allow reads past end of device */
-       if ((start + len) > nand->totlen) {
-               printf ("%s: Attempt read beyond end of device %x %x %x\n",
-                       __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen);
-               *retlen = 0;
-               return -1;
-       }
-
-       /* First we calculate the starting page */
-       /*page = shr(start, nand->page_shift);*/
-       page = start >> nand->page_shift;
-
-       /* Get raw starting column */
-       col = start & (nand->oobblock - 1);
-
-       /* Initialize return value */
-       *retlen = 0;
-
-       /* Select the NAND device */
-       NAND_ENABLE_CE(nand);  /* set pin low */
-
-       /* Loop until all data read */
-       while (*retlen < len) {
-
-#ifdef CONFIG_MTD_NAND_ECC
-               /* Do we have this page in cache ? */
-               if (nand->cache_page == page)
-                       goto readdata;
-               /* Send the read command */
-               NanD_Command(nand, NAND_CMD_READ0);
-               if (nand->bus16) {
-                       NanD_Address(nand, ADDR_COLUMN_PAGE,
-                                    (page << nand->page_shift) + (col >> 1));
-               } else {
-                       NanD_Address(nand, ADDR_COLUMN_PAGE,
-                                    (page << nand->page_shift) + col);
-               }
-
-               /* Read in a page + oob data */
-               NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize);
-
-               /* copy data into cache, for read out of cache and if ecc fails */
-               if (nand->data_cache) {
-                       memcpy (nand->data_cache, nand->data_buf,
-                               nand->oobblock + nand->oobsize);
-               }
-
-               /* Pick the ECC bytes out of the oob data */
-               for (j = 0; j < 6; j++) {
-                       ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])];
-               }
-
-               /* Calculate the ECC and verify it */
-               /* If block was not written with ECC, skip ECC */
-               if (oob_config.eccvalid_pos != -1 &&
-                   (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) {
-
-                       nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]);
-                       switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) {
-                       case -1:
-                               printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
-                               ecc_failed++;
-                               break;
-                       case 1:
-                       case 2: /* transfer ECC corrected data to cache */
-                               if (nand->data_cache)
-                                       memcpy (nand->data_cache, nand->data_buf, 256);
-                               break;
-                       }
-               }
-
-               if (oob_config.eccvalid_pos != -1 &&
-                   nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) {
-
-                       nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]);
-                       switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) {
-                       case -1:
-                               printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
-                               ecc_failed++;
-                               break;
-                       case 1:
-                       case 2: /* transfer ECC corrected data to cache */
-                               if (nand->data_cache)
-                                       memcpy (&nand->data_cache[256], &nand->data_buf[256], 256);
-                               break;
-                       }
-               }
-readdata:
-               /* Read the data from ECC data buffer into return buffer */
-               data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf;
-               data_poi += col;
-               if ((*retlen + (nand->oobblock - col)) >= len) {
-                       memcpy (buf + *retlen, data_poi, len - *retlen);
-                       *retlen = len;
-               } else {
-                       memcpy (buf + *retlen, data_poi,  nand->oobblock - col);
-                       *retlen += nand->oobblock - col;
-               }
-               /* Set cache page address, invalidate, if ecc_failed */
-               nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1;
-
-               ecc_status += ecc_failed;
-               ecc_failed = 0;
-
-#else
-               /* Send the read command */
-               NanD_Command(nand, NAND_CMD_READ0);
-               if (nand->bus16) {
-                       NanD_Address(nand, ADDR_COLUMN_PAGE,
-                                    (page << nand->page_shift) + (col >> 1));
-               } else {
-                       NanD_Address(nand, ADDR_COLUMN_PAGE,
-                                    (page << nand->page_shift) + col);
-               }
-
-               /* Read the data directly into the return buffer */
-               if ((*retlen + (nand->oobblock - col)) >= len) {
-                       NanD_ReadBuf(nand, buf + *retlen, len - *retlen);
-                       *retlen = len;
-                       /* We're done */
-                       continue;
-               } else {
-                       NanD_ReadBuf(nand, buf + *retlen, nand->oobblock - col);
-                       *retlen += nand->oobblock - col;
-                       }
-#endif
-               /* For subsequent reads align to page boundary. */
-               col = 0;
-               /* Increment page address */
-               page++;
-       }
-
-       /* De-select the NAND device */
-       NAND_DISABLE_CE(nand);  /* set pin high */
-
-       /*
-        * Return success, if no ECC failures, else -EIO
-        * fs driver will take care of that, because
-        * retlen == desired len and result == -EIO
-        */
-       return ecc_status ? -1 : 0;
-}
-
-/*
- *     Nand_page_program function is used for write and writev !
- */
-static int nand_write_page (struct nand_chip *nand,
-                           int page, int col, int last, u_char * ecc_code)
-{
-
-       int i;
-       unsigned long nandptr = nand->IO_ADDR;
-
-#ifdef CONFIG_MTD_NAND_ECC
-#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
-       int ecc_bytes = (nand->oobblock == 512) ? 6 : 3;
-#endif
-#endif
-       /* pad oob area */
-       for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++)
-               nand->data_buf[i] = 0xff;
-
-#ifdef CONFIG_MTD_NAND_ECC
-       /* Zero out the ECC array */
-       for (i = 0; i < 6; i++)
-               ecc_code[i] = 0x00;
-
-       /* Read back previous written data, if col > 0 */
-       if (col) {
-               NanD_Command (nand, NAND_CMD_READ0);
-               if (nand->bus16) {
-                       NanD_Address (nand, ADDR_COLUMN_PAGE,
-                                     (page << nand->page_shift) + (col >> 1));
-               } else {
-                       NanD_Address (nand, ADDR_COLUMN_PAGE,
-                                     (page << nand->page_shift) + col);
-               }
-
-               if (nand->bus16) {
-                       u16 val;
-
-                       for (i = 0; i < col; i += 2) {
-                               val = READ_NAND (nandptr);
-                               nand->data_buf[i] = val & 0xff;
-                               nand->data_buf[i + 1] = val >> 8;
-                       }
-               } else {
-                       for (i = 0; i < col; i++)
-                               nand->data_buf[i] = READ_NAND (nandptr);
-               }
-       }
-
-       /* Calculate and write the ECC if we have enough data */
-       if ((col < nand->eccsize) && (last >= nand->eccsize)) {
-               nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0]));
-               for (i = 0; i < 3; i++) {
-                       nand->data_buf[(nand->oobblock +
-                                       oob_config.ecc_pos[i])] = ecc_code[i];
-               }
-               if (oob_config.eccvalid_pos != -1) {
-                       nand->data_buf[nand->oobblock +
-                                      oob_config.eccvalid_pos] = 0xf0;
-               }
-       }
-
-       /* Calculate and write the second ECC if we have enough data */
-       if ((nand->oobblock == 512) && (last == nand->oobblock)) {
-               nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3]));
-               for (i = 3; i < 6; i++) {
-                       nand->data_buf[(nand->oobblock +
-                                       oob_config.ecc_pos[i])] = ecc_code[i];
-               }
-               if (oob_config.eccvalid_pos != -1) {
-                       nand->data_buf[nand->oobblock +
-                                      oob_config.eccvalid_pos] &= 0x0f;
-               }
-       }
-#endif
-       /* Prepad for partial page programming !!! */
-       for (i = 0; i < col; i++)
-               nand->data_buf[i] = 0xff;
-
-       /* Postpad for partial page programming !!! oob is already padded */
-       for (i = last; i < nand->oobblock; i++)
-               nand->data_buf[i] = 0xff;
-
-       /* Send command to begin auto page programming */
-       NanD_Command (nand, NAND_CMD_READ0);
-       NanD_Command (nand, NAND_CMD_SEQIN);
-       if (nand->bus16) {
-               NanD_Address (nand, ADDR_COLUMN_PAGE,
-                             (page << nand->page_shift) + (col >> 1));
-       } else {
-               NanD_Address (nand, ADDR_COLUMN_PAGE,
-                             (page << nand->page_shift) + col);
-       }
-
-       /* Write out complete page of data */
-       if (nand->bus16) {
-               for (i = 0; i < (nand->oobblock + nand->oobsize); i += 2) {
-                       WRITE_NAND (nand->data_buf[i] +
-                                   (nand->data_buf[i + 1] << 8),
-                                   nand->IO_ADDR);
-               }
-       } else {
-               for (i = 0; i < (nand->oobblock + nand->oobsize); i++)
-                       WRITE_NAND (nand->data_buf[i], nand->IO_ADDR);
-       }
-
-       /* Send command to actually program the data */
-       NanD_Command (nand, NAND_CMD_PAGEPROG);
-       NanD_Command (nand, NAND_CMD_STATUS);
-#ifdef NAND_NO_RB
-       {
-               u_char ret_val;
-
-               do {
-                       ret_val = READ_NAND (nandptr);  /* wait till ready */
-               } while ((ret_val & 0x40) != 0x40);
-       }
-#endif
-       /* See if device thinks it succeeded */
-       if (READ_NAND (nand->IO_ADDR) & 0x01) {
-               printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__,
-                       page);
-               return -1;
-       }
-#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
-       /*
-        * The NAND device assumes that it is always writing to
-        * a cleanly erased page. Hence, it performs its internal
-        * write verification only on bits that transitioned from
-        * 1 to 0. The device does NOT verify the whole page on a
-        * byte by byte basis. It is possible that the page was
-        * not completely erased or the page is becoming unusable
-        * due to wear. The read with ECC would catch the error
-        * later when the ECC page check fails, but we would rather
-        * catch it early in the page write stage. Better to write
-        * no data than invalid data.
-        */
-
-       /* Send command to read back the page */
-       if (col < nand->eccsize)
-               NanD_Command (nand, NAND_CMD_READ0);
-       else
-               NanD_Command (nand, NAND_CMD_READ1);
-       if (nand->bus16) {
-               NanD_Address (nand, ADDR_COLUMN_PAGE,
-                             (page << nand->page_shift) + (col >> 1));
-       } else {
-               NanD_Address (nand, ADDR_COLUMN_PAGE,
-                             (page << nand->page_shift) + col);
-       }
-
-       /* Loop through and verify the data */
-       if (nand->bus16) {
-               for (i = col; i < last; i = +2) {
-                       if ((nand->data_buf[i] +
-                            (nand->data_buf[i + 1] << 8)) != READ_NAND (nand->IO_ADDR)) {
-                               printf ("%s: Failed write verify, page 0x%08x ",
-                                       __FUNCTION__, page);
-                               return -1;
-                       }
-               }
-       } else {
-               for (i = col; i < last; i++) {
-                       if (nand->data_buf[i] != READ_NAND (nand->IO_ADDR)) {
-                               printf ("%s: Failed write verify, page 0x%08x ",
-                                       __FUNCTION__, page);
-                               return -1;
-                       }
-               }
-       }
-
-#ifdef CONFIG_MTD_NAND_ECC
-       /*
-        * We also want to check that the ECC bytes wrote
-        * correctly for the same reasons stated above.
-        */
-       NanD_Command (nand, NAND_CMD_READOOB);
-       if (nand->bus16) {
-               NanD_Address (nand, ADDR_COLUMN_PAGE,
-                             (page << nand->page_shift) + (col >> 1));
-       } else {
-               NanD_Address (nand, ADDR_COLUMN_PAGE,
-                             (page << nand->page_shift) + col);
-       }
-       if (nand->bus16) {
-               for (i = 0; i < nand->oobsize; i += 2) {
-                       u16 val;
-
-                       val = READ_NAND (nand->IO_ADDR);
-                       nand->data_buf[i] = val & 0xff;
-                       nand->data_buf[i + 1] = val >> 8;
-               }
-       } else {
-               for (i = 0; i < nand->oobsize; i++) {
-                       nand->data_buf[i] = READ_NAND (nand->IO_ADDR);
-               }
-       }
-       for (i = 0; i < ecc_bytes; i++) {
-               if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) {
-                       printf ("%s: Failed ECC write "
-                               "verify, page 0x%08x, "
-                               "%6i bytes were succesful\n",
-                               __FUNCTION__, page, i);
-                       return -1;
-               }
-       }
-#endif /* CONFIG_MTD_NAND_ECC */
-#endif /* CONFIG_MTD_NAND_VERIFY_WRITE */
-       return 0;
-}
-
-static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
-                          size_t * retlen, const u_char * buf, u_char * ecc_code)
-{
-       int i, page, col, cnt, ret = 0;
-
-       /* Do not allow write past end of device */
-       if ((to + len) > nand->totlen) {
-               printf ("%s: Attempt to write past end of page\n", __FUNCTION__);
-               return -1;
-       }
-
-       /* Shift to get page */
-       page = ((int) to) >> nand->page_shift;
-
-       /* Get the starting column */
-       col = to & (nand->oobblock - 1);
-
-       /* Initialize return length value */
-       *retlen = 0;
-
-       /* Select the NAND device */
-#ifdef CONFIG_OMAP1510
-       archflashwp(0,0);
-#endif
-#ifdef CFG_NAND_WP
-       NAND_WP_OFF();
-#endif
-
-       NAND_ENABLE_CE(nand);  /* set pin low */
-
-       /* Check the WP bit */
-       NanD_Command(nand, NAND_CMD_STATUS);
-       if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
-               printf ("%s: Device is write protected!!!\n", __FUNCTION__);
-               ret = -1;
-               goto out;
-       }
-
-       /* Loop until all data is written */
-       while (*retlen < len) {
-               /* Invalidate cache, if we write to this page */
-               if (nand->cache_page == page)
-                       nand->cache_page = -1;
-
-               /* Write data into buffer */
-               if ((col + len) >= nand->oobblock) {
-                       for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++) {
-                               nand->data_buf[i] = buf[(*retlen + cnt)];
-                       }
-               } else {
-                       for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++) {
-                               nand->data_buf[i] = buf[(*retlen + cnt)];
-                       }
-               }
-               /* We use the same function for write and writev !) */
-               ret = nand_write_page (nand, page, col, i, ecc_code);
-               if (ret)
-                       goto out;
-
-               /* Next data start at page boundary */
-               col = 0;
-
-               /* Update written bytes count */
-               *retlen += cnt;
-
-               /* Increment page address */
-               page++;
-       }
-
-       /* Return happy */
-       *retlen = len;
-
-out:
-       /* De-select the NAND device */
-       NAND_DISABLE_CE(nand);  /* set pin high */
-#ifdef CONFIG_OMAP1510
-       archflashwp(0,1);
-#endif
-#ifdef CFG_NAND_WP
-       NAND_WP_ON();
-#endif
-
-       return ret;
-}
-
-/* read from the 16 bytes of oob data that correspond to a 512 byte
- * page or 2 256-byte pages.
- */
-static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
-                        size_t * retlen, u_char * buf)
-{
-       int len256 = 0;
-       struct Nand *mychip;
-       int ret = 0;
-
-       mychip = &nand->chips[ofs >> nand->chipshift];
-
-       /* update address for 2M x 8bit devices. OOB starts on the second */
-       /* page to maintain compatibility with nand_read_ecc. */
-       if (nand->page256) {
-               if (!(ofs & 0x8))
-                       ofs += 0x100;
-               else
-                       ofs -= 0x8;
-       }
-
-       NAND_ENABLE_CE(nand);  /* set pin low */
-       NanD_Command(nand, NAND_CMD_READOOB);
-       if (nand->bus16) {
-               NanD_Address(nand, ADDR_COLUMN_PAGE,
-                            ((ofs >> nand->page_shift) << nand->page_shift) +
-                               ((ofs & (nand->oobblock - 1)) >> 1));
-       } else {
-               NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
-       }
-
-       /* treat crossing 8-byte OOB data for 2M x 8bit devices */
-       /* Note: datasheet says it should automaticaly wrap to the */
-       /*       next OOB block, but it didn't work here. mf.      */
-       if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
-               len256 = (ofs | 0x7) + 1 - ofs;
-               NanD_ReadBuf(nand, buf, len256);
-
-               NanD_Command(nand, NAND_CMD_READOOB);
-               NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
-       }
-
-       NanD_ReadBuf(nand, &buf[len256], len - len256);
-
-       *retlen = len;
-       /* Reading the full OOB data drops us off of the end of the page,
-        * causing the flash device to go into busy mode, so we need
-        * to wait until ready 11.4.1 and Toshiba TC58256FT nands */
-
-       ret = NanD_WaitReady(nand, 1);
-       NAND_DISABLE_CE(nand);  /* set pin high */
-
-       return ret;
-
-}
-
-/* write to the 16 bytes of oob data that correspond to a 512 byte
- * page or 2 256-byte pages.
- */
-static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
-                 size_t * retlen, const u_char * buf)
-{
-       int len256 = 0;
-       int i;
-       unsigned long nandptr = nand->IO_ADDR;
-
-#ifdef PSYCHO_DEBUG
-       printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n",
-              (long)ofs, len, buf[0], buf[1], buf[2], buf[3],
-              buf[8], buf[9], buf[14],buf[15]);
-#endif
-
-       NAND_ENABLE_CE(nand);  /* set pin low to enable chip */
-
-       /* Reset the chip */
-       NanD_Command(nand, NAND_CMD_RESET);
-
-       /* issue the Read2 command to set the pointer to the Spare Data Area. */
-       NanD_Command(nand, NAND_CMD_READOOB);
-       if (nand->bus16) {
-               NanD_Address(nand, ADDR_COLUMN_PAGE,
-                            ((ofs >> nand->page_shift) << nand->page_shift) +
-                               ((ofs & (nand->oobblock - 1)) >> 1));
-       } else {
-               NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
-       }
-
-       /* update address for 2M x 8bit devices. OOB starts on the second */
-       /* page to maintain compatibility with nand_read_ecc. */
-       if (nand->page256) {
-               if (!(ofs & 0x8))
-                       ofs += 0x100;
-               else
-                       ofs -= 0x8;
-       }
-
-       /* issue the Serial Data In command to initial the Page Program process */
-       NanD_Command(nand, NAND_CMD_SEQIN);
-       if (nand->bus16) {
-               NanD_Address(nand, ADDR_COLUMN_PAGE,
-                            ((ofs >> nand->page_shift) << nand->page_shift) +
-                               ((ofs & (nand->oobblock - 1)) >> 1));
-       } else {
-               NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
-       }
-
-       /* treat crossing 8-byte OOB data for 2M x 8bit devices */
-       /* Note: datasheet says it should automaticaly wrap to the */
-       /*       next OOB block, but it didn't work here. mf.      */
-       if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
-               len256 = (ofs | 0x7) + 1 - ofs;
-               for (i = 0; i < len256; i++)
-                       WRITE_NAND(buf[i], nandptr);
-
-               NanD_Command(nand, NAND_CMD_PAGEPROG);
-               NanD_Command(nand, NAND_CMD_STATUS);
-#ifdef NAND_NO_RB
-               { u_char ret_val;
-                       do {
-                               ret_val = READ_NAND(nandptr); /* wait till ready */
-                       } while ((ret_val & 0x40) != 0x40);
-               }
-#endif
-               if (READ_NAND(nandptr) & 1) {
-                       puts ("Error programming oob data\n");
-                       /* There was an error */
-                       NAND_DISABLE_CE(nand);  /* set pin high */
-                       *retlen = 0;
-                       return -1;
-               }
-               NanD_Command(nand, NAND_CMD_SEQIN);
-               NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
-       }
-
-       if (nand->bus16) {
-               for (i = len256; i < len; i += 2) {
-                       WRITE_NAND(buf[i] + (buf[i+1] << 8), nandptr);
-               }
-       } else {
-               for (i = len256; i < len; i++)
-                       WRITE_NAND(buf[i], nandptr);
-       }
-
-       NanD_Command(nand, NAND_CMD_PAGEPROG);
-       NanD_Command(nand, NAND_CMD_STATUS);
-#ifdef NAND_NO_RB
-       {       u_char ret_val;
-               do {
-                       ret_val = READ_NAND(nandptr); /* wait till ready */
-               } while ((ret_val & 0x40) != 0x40);
-       }
-#endif
-       if (READ_NAND(nandptr) & 1) {
-               puts ("Error programming oob data\n");
-               /* There was an error */
-               NAND_DISABLE_CE(nand);  /* set pin high */
-               *retlen = 0;
-               return -1;
-       }
-
-       NAND_DISABLE_CE(nand);  /* set pin high */
-       *retlen = len;
-       return 0;
-
-}
-
-int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean)
-{
-       /* This is defined as a structure so it will work on any system
-        * using native endian jffs2 (the default).
-        */
-       static struct jffs2_unknown_node clean_marker = {
-               JFFS2_MAGIC_BITMASK,
-               JFFS2_NODETYPE_CLEANMARKER,
-               8               /* 8 bytes in this node */
-       };
-       unsigned long nandptr;
-       struct Nand *mychip;
-       int ret = 0;
-
-       if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) {
-               printf ("Offset and size must be sector aligned, erasesize = %d\n",
-                       (int) nand->erasesize);
-               return -1;
-       }
-
-       nandptr = nand->IO_ADDR;
-
-       /* Select the NAND device */
-#ifdef CONFIG_OMAP1510
-       archflashwp(0,0);
-#endif
-#ifdef CFG_NAND_WP
-       NAND_WP_OFF();
-#endif
-    NAND_ENABLE_CE(nand);  /* set pin low */
-
-       /* Check the WP bit */
-       NanD_Command(nand, NAND_CMD_STATUS);
-       if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
-               printf ("nand_write_ecc: Device is write protected!!!\n");
-               ret = -1;
-               goto out;
-       }
-
-       /* Check the WP bit */
-       NanD_Command(nand, NAND_CMD_STATUS);
-       if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
-               printf ("%s: Device is write protected!!!\n", __FUNCTION__);
-               ret = -1;
-               goto out;
-       }
-
-       /* FIXME: Do nand in the background. Use timers or schedule_task() */
-       while(len) {
-               /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/
-               mychip = &nand->chips[ofs >> nand->chipshift];
-
-               /* always check for bad block first, genuine bad blocks
-                * should _never_  be erased.
-                */
-               if (ALLOW_ERASE_BAD_DEBUG || !check_block(nand, ofs)) {
-                       /* Select the NAND device */
-                       NAND_ENABLE_CE(nand);  /* set pin low */
-
-                       NanD_Command(nand, NAND_CMD_ERASE1);
-                       NanD_Address(nand, ADDR_PAGE, ofs);
-                       NanD_Command(nand, NAND_CMD_ERASE2);
-
-                       NanD_Command(nand, NAND_CMD_STATUS);
-
-#ifdef NAND_NO_RB
-                       {       u_char ret_val;
-                               do {
-                                       ret_val = READ_NAND(nandptr); /* wait till ready */
-                               } while ((ret_val & 0x40) != 0x40);
-                       }
-#endif
-                       if (READ_NAND(nandptr) & 1) {
-                               printf ("%s: Error erasing at 0x%lx\n",
-                                       __FUNCTION__, (long)ofs);
-                               /* There was an error */
-                               ret = -1;
-                               goto out;
-                       }
-                       if (clean) {
-                               int n;  /* return value not used */
-                               int p, l;
-
-                               /* clean marker position and size depend
-                                * on the page size, since 256 byte pages
-                                * only have 8 bytes of oob data
-                                */
-                               if (nand->page256) {
-                                       p = NAND_JFFS2_OOB8_FSDAPOS;
-                                       l = NAND_JFFS2_OOB8_FSDALEN;
-                               } else {
-                                       p = NAND_JFFS2_OOB16_FSDAPOS;
-                                       l = NAND_JFFS2_OOB16_FSDALEN;
-                               }
-
-                               ret = nand_write_oob(nand, ofs + p, l, (size_t *)&n,
-                                                    (u_char *)&clean_marker);
-                               /* quit here if write failed */
-                               if (ret)
-                                       goto out;
-                       }
-               }
-               ofs += nand->erasesize;
-               len -= nand->erasesize;
-       }
-
-out:
-       /* De-select the NAND device */
-       NAND_DISABLE_CE(nand);  /* set pin high */
-#ifdef CONFIG_OMAP1510
-       archflashwp(0,1);
-#endif
-#ifdef CFG_NAND_WP
-       NAND_WP_ON();
-#endif
-
-       return ret;
-}
-
-static inline int nandcheck(unsigned long potential, unsigned long physadr)
-{
-       return 0;
-}
-
-unsigned long nand_probe(unsigned long physadr)
-{
-       struct nand_chip *nand = NULL;
-       int i = 0, ChipID = 1;
-
-#ifdef CONFIG_MTD_NAND_ECC_JFFS2
-       oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0;
-       oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1;
-       oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2;
-       oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3;
-       oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4;
-       oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5;
-       oob_config.eccvalid_pos = 4;
-#else
-       oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0;
-       oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1;
-       oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2;
-       oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3;
-       oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4;
-       oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5;
-       oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS;
-#endif
-       oob_config.badblock_pos = 5;
-
-       for (i=0; i<CFG_MAX_NAND_DEVICE; i++) {
-               if (nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) {
-                       nand = &nand_dev_desc[i];
-                       break;
-               }
-       }
-       if (!nand)
-               return (0);
-
-       memset((char *)nand, 0, sizeof(struct nand_chip));
-
-       nand->IO_ADDR = physadr;
-       nand->cache_page = -1;  /* init the cache page */
-       NanD_ScanChips(nand);
-
-       if (nand->totlen == 0) {
-               /* no chips found, clean up and quit */
-               memset((char *)nand, 0, sizeof(struct nand_chip));
-               nand->ChipID = NAND_ChipID_UNKNOWN;
-               return (0);
-       }
-
-       nand->ChipID = ChipID;
-       if (curr_device == -1)
-               curr_device = i;
-
-       nand->data_buf = malloc (nand->oobblock + nand->oobsize);
-       if (!nand->data_buf) {
-               puts ("Cannot allocate memory for data structures.\n");
-               return (0);
-       }
-
-       return (nand->totlen);
-}
-
-#ifdef CONFIG_MTD_NAND_ECC
-/*
- * Pre-calculated 256-way 1 byte column parity
- */
-static const u_char nand_ecc_precalc_table[] = {
-       0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a,
-       0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
-       0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f,
-       0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
-       0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c,
-       0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
-       0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59,
-       0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
-       0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33,
-       0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
-       0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56,
-       0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
-       0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55,
-       0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
-       0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30,
-       0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
-       0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30,
-       0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
-       0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55,
-       0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
-       0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56,
-       0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
-       0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33,
-       0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
-       0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59,
-       0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
-       0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c,
-       0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
-       0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f,
-       0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
-       0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a,
-       0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
-};
-
-
-/*
- * Creates non-inverted ECC code from line parity
- */
-static void nand_trans_result(u_char reg2, u_char reg3,
-       u_char *ecc_code)
-{
-       u_char a, b, i, tmp1, tmp2;
-
-       /* Initialize variables */
-       a = b = 0x80;
-       tmp1 = tmp2 = 0;
-
-       /* Calculate first ECC byte */
-       for (i = 0; i < 4; i++) {
-               if (reg3 & a)           /* LP15,13,11,9 --> ecc_code[0] */
-                       tmp1 |= b;
-               b >>= 1;
-               if (reg2 & a)           /* LP14,12,10,8 --> ecc_code[0] */
-                       tmp1 |= b;
-               b >>= 1;
-               a >>= 1;
-       }
-
-       /* Calculate second ECC byte */
-       b = 0x80;
-       for (i = 0; i < 4; i++) {
-               if (reg3 & a)           /* LP7,5,3,1 --> ecc_code[1] */
-                       tmp2 |= b;
-               b >>= 1;
-               if (reg2 & a)           /* LP6,4,2,0 --> ecc_code[1] */
-                       tmp2 |= b;
-               b >>= 1;
-               a >>= 1;
-       }
-
-       /* Store two of the ECC bytes */
-       ecc_code[0] = tmp1;
-       ecc_code[1] = tmp2;
-}
-
-/*
- * Calculate 3 byte ECC code for 256 byte block
- */
-static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code)
-{
-       u_char idx, reg1, reg3;
-       int j;
-
-       /* Initialize variables */
-       reg1 = reg3 = 0;
-       ecc_code[0] = ecc_code[1] = ecc_code[2] = 0;
-
-       /* Build up column parity */
-       for(j = 0; j < 256; j++) {
-
-               /* Get CP0 - CP5 from table */
-               idx = nand_ecc_precalc_table[dat[j]];
-               reg1 ^= idx;
-
-               /* All bit XOR = 1 ? */
-               if (idx & 0x40) {
-                       reg3 ^= (u_char) j;
-               }
-       }
-
-       /* Create non-inverted ECC code from line parity */
-       nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code);
-
-       /* Calculate final ECC code */
-       ecc_code[0] = ~ecc_code[0];
-       ecc_code[1] = ~ecc_code[1];
-       ecc_code[2] = ((~reg1) << 2) | 0x03;
-}
-
-/*
- * Detect and correct a 1 bit error for 256 byte block
- */
-static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc)
-{
-       u_char a, b, c, d1, d2, d3, add, bit, i;
-
-       /* Do error detection */
-       d1 = calc_ecc[0] ^ read_ecc[0];
-       d2 = calc_ecc[1] ^ read_ecc[1];
-       d3 = calc_ecc[2] ^ read_ecc[2];
-
-       if ((d1 | d2 | d3) == 0) {
-               /* No errors */
-               return 0;
-       } else {
-               a = (d1 ^ (d1 >> 1)) & 0x55;
-               b = (d2 ^ (d2 >> 1)) & 0x55;
-               c = (d3 ^ (d3 >> 1)) & 0x54;
-
-               /* Found and will correct single bit error in the data */
-               if ((a == 0x55) && (b == 0x55) && (c == 0x54)) {
-                       c = 0x80;
-                       add = 0;
-                       a = 0x80;
-                       for (i=0; i<4; i++) {
-                               if (d1 & c)
-                                       add |= a;
-                               c >>= 2;
-                               a >>= 1;
-                       }
-                       c = 0x80;
-                       for (i=0; i<4; i++) {
-                               if (d2 & c)
-                                       add |= a;
-                               c >>= 2;
-                               a >>= 1;
-                       }
-                       bit = 0;
-                       b = 0x04;
-                       c = 0x80;
-                       for (i=0; i<3; i++) {
-                               if (d3 & c)
-                                       bit |= b;
-                               c >>= 2;
-                               b >>= 1;
-                       }
-                       b = 0x01;
-                       a = dat[add];
-                       a ^= (b << bit);
-                       dat[add] = a;
-                       return 1;
-               }
-               else {
-                       i = 0;
-                       while (d1) {
-                               if (d1 & 0x01)
-                                       ++i;
-                               d1 >>= 1;
-                       }
-                       while (d2) {
-                               if (d2 & 0x01)
-                                       ++i;
-                               d2 >>= 1;
-                       }
-                       while (d3) {
-                               if (d3 & 0x01)
-                                       ++i;
-                               d3 >>= 1;
-                       }
-                       if (i == 1) {
-                               /* ECC Code Error Correction */
-                               read_ecc[0] = calc_ecc[0];
-                               read_ecc[1] = calc_ecc[1];
-                               read_ecc[2] = calc_ecc[2];
-                               return 2;
-                       }
-                       else {
-                               /* Uncorrectable Error */
-                               return -1;
-                       }
-               }
-       }
-
-       /* Should never happen */
-       return -1;
-}
-
-#endif
-
-#ifdef CONFIG_JFFS2_NAND
-
-int read_jffs2_nand(size_t start, size_t len,
-                   size_t * retlen, u_char * buf, int nanddev)
-{
-       return nand_rw(nand_dev_desc + nanddev, NANDRW_READ | NANDRW_JFFS2,
-                      start, len, retlen, buf);
-}
-
-#endif /* CONFIG_JFFS2_NAND */
-
-
-#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
+#endif /* CFG_NAND_LEGACY */

diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index 1babffec2e0a8fc322b2ac462635e41bef4eb57a..6257fbd23e6d0703213bcc59b14a487bf52f4707 100644 (file)
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -50,6 +50,8 @@
 #include <net.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if !defined(CFG_ENV_IS_IN_NVRAM)      && \
     !defined(CFG_ENV_IS_IN_EEPROM)     && \
     !defined(CFG_ENV_IS_IN_FLASH)      && \
@@ -152,8 +154,6 @@ int do_printenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 int _do_setenv (int flag, int argc, char *argv[])
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int   i, len, oldval;
        int   console = -1;
        uchar *env, *nxt = NULL;
@@ -532,7 +532,9 @@ int getenv_r (char *name, char *buf, unsigned len)
 
 #if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \
     ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \
-      (CFG_CMD_ENV|CFG_CMD_FLASH))
+      (CFG_CMD_ENV|CFG_CMD_FLASH)) || \
+    ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_NAND)) == \
+      (CFG_CMD_ENV|CFG_CMD_NAND))
 int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
        extern char * env_name_spec;
@@ -588,7 +590,9 @@ U_BOOT_CMD(
 
 #if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \
     ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \
-      (CFG_CMD_ENV|CFG_CMD_FLASH))
+      (CFG_CMD_ENV|CFG_CMD_FLASH)) || \
+    ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_NAND)) == \
+      (CFG_CMD_ENV|CFG_CMD_NAND))
 U_BOOT_CMD(
        saveenv, 1, 0,  do_saveenv,
        "saveenv - save environment variables to persistent storage\n",

diff --git a/common/command.c b/common/command.c
index 2b4c5547b31af616f5599e475790935823d04344..e917975a7331d21f6cf02efad21660ac2e060c77 100644 (file)
--- a/common/command.c
+++ b/common/command.c
@@ -42,6 +42,8 @@ U_BOOT_CMD(
        NULL
 );
 
+#if (CONFIG_COMMANDS & CFG_CMD_ECHO)
+
 int
 do_echo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -74,6 +76,8 @@ U_BOOT_CMD(
        "    - echo args to console; \\c suppresses newline\n"
 );
 
+#endif /*  CFG_CMD_ECHO */
+
 #ifdef CFG_HUSH_PARSER
 
 int

diff --git a/common/console.c b/common/console.c
index 3c535d23d6d5ea592d982e57b41303c019a470f2..e9f23bec1820f178e3f4a67e3241182a0c65dc9d 100644 (file)
--- a/common/console.c
+++ b/common/console.c
@@ -27,6 +27,8 @@
 #include <console.h>
 #include <exports.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_AMIGAONEG3SE
 int console_changed = 0;
 #endif
@@ -48,7 +50,6 @@ extern int overwrite_console (void);
 
 static int console_setfile (int file, device_t * dev)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int error = 0;
 
        if (dev == NULL)
@@ -161,8 +162,6 @@ void fprintf (int file, const char *fmt, ...)
 
 int getc (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (gd->flags & GD_FLG_DEVINIT) {
                /* Get from the standard input */
                return fgetc (stdin);
@@ -174,8 +173,6 @@ int getc (void)
 
 int tstc (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (gd->flags & GD_FLG_DEVINIT) {
                /* Test the standard input */
                return ftstc (stdin);
@@ -187,8 +184,6 @@ int tstc (void)
 
 void putc (const char c)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
 #ifdef CONFIG_SILENT_CONSOLE
        if (gd->flags & GD_FLG_SILENT)
                return;
@@ -205,8 +200,6 @@ void putc (const char c)
 
 void puts (const char *s)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
 #ifdef CONFIG_SILENT_CONSOLE
        if (gd->flags & GD_FLG_SILENT)
                return;
@@ -258,8 +251,6 @@ static int ctrlc_disabled = 0;      /* see disable_ctrl() */
 static int ctrlc_was_pressed = 0;
 int ctrlc (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (!ctrlc_disabled && gd->have_console) {
                if (tstc ()) {
                        switch (getc ()) {
@@ -370,8 +361,6 @@ int console_assign (int file, char *devname)
 /* Called before relocation - use serial functions */
 int console_init_f (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->have_console = 1;
 
 #ifdef CONFIG_SILENT_CONSOLE
@@ -407,7 +396,6 @@ device_t *search_device (int flags, char *name)
 /* Called after the relocation - use desired console functions */
 int console_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        char *stdinname, *stdoutname, *stderrname;
        device_t *inputdev = NULL, *outputdev = NULL, *errdev = NULL;
 #ifdef CFG_CONSOLE_ENV_OVERWRITE
@@ -499,8 +487,6 @@ int console_init_r (void)
 /* Called after the relocation - use desired console functions */
 int console_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        device_t *inputdev = NULL, *outputdev = NULL;
        int i, items = ListNumItems (devlist);
 

diff --git a/common/crc16.c b/common/crc16.c
new file mode 100644 (file)
index 0000000..3cef106
--- /dev/null
+++ b/common/crc16.c
@@ -0,0 +1,107 @@
+/*
+ *==========================================================================
+ *
+ *      crc16.c
+ *
+ *      16 bit CRC with polynomial x^16+x^12+x^5+1
+ *
+ *==========================================================================
+ *####ECOSGPLCOPYRIGHTBEGIN####
+ * -------------------------------------------
+ * This file is part of eCos, the Embedded Configurable Operating System.
+ * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+ * Copyright (C) 2002 Gary Thomas
+ *
+ * eCos is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 or (at your option) any later version.
+ *
+ * eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+ * WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with eCos; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * As a special exception, if other files instantiate templates or use macros
+ * or inline functions from this file, or you compile this file and link it
+ * with other works to produce a work based on this file, this file does not
+ * by itself cause the resulting work to be covered by the GNU General Public
+ * License. However the source code for this file must still be made available
+ * in accordance with section (3) of the GNU General Public License.
+ *
+ * This exception does not invalidate any other reasons why a work based on
+ * this file might be covered by the GNU General Public License.
+ *
+ * Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+ * at http: *sources.redhat.com/ecos/ecos-license/
+ * -------------------------------------------
+ *####ECOSGPLCOPYRIGHTEND####
+ *==========================================================================
+ *#####DESCRIPTIONBEGIN####
+ *
+ * Author(s):    gthomas
+ * Contributors: gthomas,asl
+ * Date:         2001-01-31
+ * Purpose:
+ * Description:
+ *
+ * This code is part of eCos (tm).
+ *
+ *####DESCRIPTIONEND####
+ *
+ *==========================================================================
+ */
+
+#include "crc.h"
+
+/* Table of CRC constants - implements x^16+x^12+x^5+1 */
+static const uint16_t crc16_tab[] = {
+    0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
+    0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
+    0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
+    0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
+    0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
+    0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
+    0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
+    0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
+    0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
+    0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
+    0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
+    0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
+    0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
+    0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
+    0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
+    0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
+    0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
+    0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
+    0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
+    0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
+    0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
+    0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
+    0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
+    0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
+    0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
+    0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
+    0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
+    0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
+    0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
+    0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
+    0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
+    0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0,
+};
+
+uint16_t
+cyg_crc16(unsigned char *buf, int len)
+{
+    int i;
+    uint16_t cksum;
+
+    cksum = 0;
+    for (i = 0;  i < len;  i++) {
+        cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xFF] ^ (cksum << 8);
+    }
+    return cksum;
+}

diff --git a/common/devices.c b/common/devices.c
index bd4dfa024a94460415f5948cc6947215367e54b3..ddf8f8ee2d9f8d9c220cb73198ee93a0b5335c87 100644 (file)
--- a/common/devices.c
+++ b/common/devices.c
@@ -34,6 +34,8 @@
 #include <i2c.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 list_t devlist = 0;
 device_t *stdio_devices[] = { NULL, NULL, NULL };
 char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" };
@@ -160,8 +162,6 @@ int device_deregister(char *devname)
 int devices_init (void)
 {
 #ifndef CONFIG_ARM     /* already relocated for current ARM implementation */
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong relocation_offset = gd->reloc_off;
        int i;
 

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 0c0487228e500aaadb021352ad8eb9027949e897..20c206913c63d2fcd1588fc0f0ae3baaae10940a 100644 (file)
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -949,6 +949,8 @@ void malloc_stats();
 #endif /* 0 */                 /* Moved to malloc.h */
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
   Emulation of sbrk for WIN32
   All code within the ifdef WIN32 is untested by me.
@@ -1493,8 +1495,6 @@ static mbinptr av_[NAV * 2 + 2] = {
 
 void malloc_bin_reloc (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long *p = (unsigned long *)(&av_[2]);
        int i;
        for (i=2; i<(sizeof(av_)/sizeof(mbinptr)); ++i) {

diff --git a/common/env_common.c b/common/env_common.c
index 3201135ea2eddbe7b46c427c7f1deef21d9d7d32..eb33422af4b9c664da8928c1e2d61d986067d338 100644 (file)
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -37,6 +37,8 @@
 # define SHOW_BOOT_PROGRESS(arg)
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_AMIGAONEG3SE
        extern void enable_nvram(void);
        extern void disable_nvram(void);
@@ -150,7 +152,6 @@ void env_crc_update (void)
 
 static uchar env_get_char_init (int index)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        uchar c;
 
        /* if crc was bad, use the default environment */
@@ -167,7 +168,6 @@ static uchar env_get_char_init (int index)
 #ifdef CONFIG_AMIGAONEG3SE
 uchar env_get_char_memory (int index)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        uchar retval;
        enable_nvram();
        if (gd->env_valid) {
@@ -181,8 +181,6 @@ uchar env_get_char_memory (int index)
 #else
 uchar env_get_char_memory (int index)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (gd->env_valid) {
                return ( *((uchar *)(gd->env_addr + index)) );
        } else {
@@ -193,8 +191,6 @@ uchar env_get_char_memory (int index)
 
 uchar *env_get_addr (int index)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (gd->env_valid) {
                return ( ((uchar *)(gd->env_addr + index)) );
        } else {
@@ -204,8 +200,6 @@ uchar *env_get_addr (int index)
 
 void env_relocate (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        DEBUGF ("%s[%d] offset = 0x%lx\n", __FUNCTION__,__LINE__,
                gd->reloc_off);
 

diff --git a/common/env_dataflash.c b/common/env_dataflash.c
index 8834da032bdd82f5b78acf51d772e9972057a1a4..93fff29b05a4a6dda262fddbee115467495eae0a 100644 (file)
--- a/common/env_dataflash.c
+++ b/common/env_dataflash.c
@@ -26,6 +26,8 @@
 #include <linux/stddef.h>
 #include <dataflash.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 env_t *env_ptr = NULL;
 
 char * env_name_spec = "dataflash";
@@ -68,8 +70,6 @@ int i;
  */
 int env_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong crc, len, new;
        unsigned off;
        uchar buf[64];

diff --git a/common/env_eeprom.c b/common/env_eeprom.c
index 50c623e37e32b89b4bbe9f4bab1ba95f3017b059..2adc129c67799cee1ecbf7124862d4b4a1d9a1d0 100644 (file)
--- a/common/env_eeprom.c
+++ b/common/env_eeprom.c
@@ -32,6 +32,8 @@
 #include <environment.h>
 #include <linux/stddef.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 env_t *env_ptr = NULL;
 
 char * env_name_spec = "EEPROM";
@@ -75,8 +77,6 @@ int saveenv(void)
  */
 int env_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong crc, len, new;
        unsigned off;
        uchar buf[64];

diff --git a/common/env_flash.c b/common/env_flash.c
index a2ea9c41406842d7acbc404aef25538f19d75df7..1674b30e118d57c60d1a44684138555417fe34b6 100644 (file)
--- a/common/env_flash.c
+++ b/common/env_flash.c
@@ -35,6 +35,8 @@
 #include <linux/stddef.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
 #define CMD_SAVEENV
 #elif defined(CFG_ENV_ADDR_REDUND)
@@ -89,8 +91,6 @@ extern int default_environment_size;
 
 uchar env_get_char_spec (int index)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        return ( *((uchar *)(gd->env_addr + index)) );
 }
 
@@ -98,7 +98,6 @@ uchar env_get_char_spec (int index)
 
 int  env_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int crc1_ok = 0, crc2_ok = 0;
 
        uchar flag1 = flash_addr->flags;
@@ -260,7 +259,6 @@ Done:
 
 int  env_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_OMAP2420H4
        int flash_probe(void);
 
@@ -358,8 +356,6 @@ void env_relocate_spec (void)
 {
 #if !defined(ENV_IS_EMBEDDED) || defined(CFG_ENV_ADDR_REDUND)
 #ifdef CFG_ENV_ADDR_REDUND
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (gd->env_addr != (ulong)&(flash_addr->data)) {
                env_t * etmp = flash_addr;
                ulong ltmp = end_addr;

diff --git a/common/env_nand.c b/common/env_nand.c
index 60aba1e7e667ee8137b2ce61611c2e038fd92c8e..0a05b09a7a8515622edee793710b16a7f323e536 100644 (file)
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -36,35 +36,29 @@
 #include <command.h>
 #include <environment.h>
 #include <linux/stddef.h>
-#include <linux/mtd/nand.h>
+#include <malloc.h>
+#include <nand.h>
 
 #if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_NAND)) == (CFG_CMD_ENV|CFG_CMD_NAND))
 #define CMD_SAVEENV
+#elif defined(CFG_ENV_OFFSET_REDUND)
+#error Cannot use CFG_ENV_OFFSET_REDUND without CFG_CMD_ENV & CFG_CMD_NAND
 #endif
 
-#if defined(CFG_ENV_SIZE_REDUND)
-#error CFG_ENV_SIZE_REDUND  not supported yet
+#if defined(CFG_ENV_SIZE_REDUND) && (CFG_ENV_SIZE_REDUND != CFG_ENV_SIZE)
+#error CFG_ENV_SIZE_REDUND should be the same as CFG_ENV_SIZE
 #endif
 
-#if defined(CFG_ENV_ADDR_REDUND)
-#error CFG_ENV_ADDR_REDUND and CFG_ENV_IS_IN_NAND not supported yet
-#endif
-
-
 #ifdef CONFIG_INFERNO
 #error CONFIG_INFERNO not supported yet
 #endif
 
-/* references to names in cmd_nand.c */
-#define NANDRW_READ            0x01
-#define NANDRW_WRITE   0x00
-#define NANDRW_JFFS2   0x02
-extern struct nand_chip nand_dev_desc[];
-int nand_rw (struct nand_chip* nand, int cmd,
+int nand_legacy_rw (struct nand_chip* nand, int cmd,
            size_t start, size_t len,
            size_t * retlen, u_char * buf);
-int nand_erase(struct nand_chip* nand, size_t ofs,
-                               size_t len, int clean);
+
+/* info for NAND chips, defined in drivers/nand/nand.c */
+extern nand_info_t nand_info[];
 
 /* references to names in env_common.c */
 extern uchar default_environment[];
@@ -84,11 +78,10 @@ env_t *env_ptr = 0;
 /* local functions */
 static void use_default(void);
 
+DECLARE_GLOBAL_DATA_PTR;
 
 uchar env_get_char_spec (int index)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        return ( *((uchar *)(gd->env_addr + index)) );
 }
 
@@ -101,59 +94,153 @@ uchar env_get_char_spec (int index)
  */
 int env_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
-       gd->env_addr  = (ulong)&default_environment[0];
+       gd->env_addr  = (ulong)&default_environment[0];
        gd->env_valid = 1;
 
        return (0);
 }
 
 #ifdef CMD_SAVEENV
+/*
+ * The legacy NAND code saved the environment in the first NAND device i.e.,
+ * nand_dev_desc + 0. This is also the behaviour using the new NAND code.
+ */
+#ifdef CFG_ENV_OFFSET_REDUND
 int saveenv(void)
 {
-       int     total, ret = 0;
-       puts ("Erasing Nand...");
-       if (nand_erase(nand_dev_desc + 0, CFG_ENV_OFFSET, CFG_ENV_SIZE, 0))
-               return 1;
+       ulong total;
+       int ret = 0;
+
+       env_ptr->flags++;
+       total = CFG_ENV_SIZE;
+
+       if(gd->env_valid == 1) {
+               puts ("Erasing redundant Nand...");
+               if (nand_erase(&nand_info[0],
+                              CFG_ENV_OFFSET_REDUND, CFG_ENV_SIZE))
+                       return 1;
+               puts ("Writing to redundant Nand... ");
+               ret = nand_write(&nand_info[0], CFG_ENV_OFFSET_REDUND, &total,
+                                (u_char*) env_ptr);
+       } else {
+               puts ("Erasing Nand...");
+               if (nand_erase(&nand_info[0],
+                              CFG_ENV_OFFSET, CFG_ENV_SIZE))
+                       return 1;
+
+               puts ("Writing to Nand... ");
+               ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total,
+                                (u_char*) env_ptr);
+       }
+       if (ret || total != CFG_ENV_SIZE)
+               return 1;
+
+       puts ("done\n");
+       gd->env_valid = (gd->env_valid == 2 ? 1 : 2);
+       return ret;
+}
+#else /* ! CFG_ENV_OFFSET_REDUND */
+int saveenv(void)
+{
+       ulong total;
+       int ret = 0;
+
+       puts ("Erasing Nand...");
+       if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_SIZE))
+               return 1;
 
        puts ("Writing to Nand... ");
-       ret = nand_rw(nand_dev_desc + 0,
-                                 NANDRW_WRITE | NANDRW_JFFS2, CFG_ENV_OFFSET, CFG_ENV_SIZE,
-                             &total, (u_char*)env_ptr);
-       if (ret || total != CFG_ENV_SIZE)
+       total = CFG_ENV_SIZE;
+       ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr);
+       if (ret || total != CFG_ENV_SIZE)
                return 1;
 
-       puts ("done\n");
-       return ret;
+       puts ("done\n");
+       return ret;
 }
+#endif /* CFG_ENV_OFFSET_REDUND */
 #endif /* CMD_SAVEENV */
 
+#ifdef CFG_ENV_OFFSET_REDUND
+void env_relocate_spec (void)
+{
+#if !defined(ENV_IS_EMBEDDED)
+       ulong total;
+       int crc1_ok = 0, crc2_ok = 0;
+       env_t *tmp_env1, *tmp_env2;
+
+       total = CFG_ENV_SIZE;
+
+       tmp_env1 = (env_t *) malloc(CFG_ENV_SIZE);
+       tmp_env2 = (env_t *) malloc(CFG_ENV_SIZE);
+
+       nand_read(&nand_info[0], CFG_ENV_OFFSET, &total,
+                 (u_char*) tmp_env1);
+       nand_read(&nand_info[0], CFG_ENV_OFFSET_REDUND, &total,
+                 (u_char*) tmp_env2);
+
+       crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc);
+       crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc);
+
+       if(!crc1_ok && !crc2_ok)
+               return use_default();
+       else if(crc1_ok && !crc2_ok)
+               gd->env_valid = 1;
+       else if(!crc1_ok && crc2_ok)
+               gd->env_valid = 2;
+       else {
+               /* both ok - check serial */
+               if(tmp_env1->flags == 255 && tmp_env2->flags == 0)
+                       gd->env_valid = 2;
+               else if(tmp_env2->flags == 255 && tmp_env1->flags == 0)
+                       gd->env_valid = 1;
+               else if(tmp_env1->flags > tmp_env2->flags)
+                       gd->env_valid = 1;
+               else if(tmp_env2->flags > tmp_env1->flags)
+                       gd->env_valid = 2;
+               else /* flags are equal - almost impossible */
+                       gd->env_valid = 1;
+
+       }
 
+       free(env_ptr);
+       if(gd->env_valid == 1) {
+               env_ptr = tmp_env1;
+               free(tmp_env2);
+       } else {
+               env_ptr = tmp_env2;
+               free(tmp_env1);
+       }
+
+#endif /* ! ENV_IS_EMBEDDED */
+}
+#else /* ! CFG_ENV_OFFSET_REDUND */
+/*
+ * The legacy NAND code saved the environment in the first NAND device i.e.,
+ * nand_dev_desc + 0. This is also the behaviour using the new NAND code.
+ */
 void env_relocate_spec (void)
 {
 #if !defined(ENV_IS_EMBEDDED)
-       int ret, total;
+       ulong total;
+       int ret;
 
-       ret = nand_rw(nand_dev_desc + 0,
-                                 NANDRW_READ | NANDRW_JFFS2, CFG_ENV_OFFSET, CFG_ENV_SIZE,
-                             &total, (u_char*)env_ptr);
+       total = CFG_ENV_SIZE;
+       ret = nand_read(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr);
        if (ret || total != CFG_ENV_SIZE)
                return use_default();
 
        if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc)
                return use_default();
 #endif /* ! ENV_IS_EMBEDDED */
-
 }
+#endif /* CFG_ENV_OFFSET_REDUND */
 
 static void use_default()
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        puts ("*** Warning - bad CRC or NAND, using default environment\n\n");
 
-       if (default_environment_size > CFG_ENV_SIZE){
+       if (default_environment_size > CFG_ENV_SIZE){
                puts ("*** Error - default environment is too large\n\n");
                return;
        }
@@ -163,7 +250,7 @@ static void use_default()
                        default_environment,
                        default_environment_size);
        env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
-       gd->env_valid = 1;
+       gd->env_valid = 1;
 
 }
 

diff --git a/common/env_nowhere.c b/common/env_nowhere.c
index ee4237c7e906889fe6833baab2d8425a04b6d79d..17ecc775ff9bf0686a74b9926ee6c6438956dda8 100644 (file)
--- a/common/env_nowhere.c
+++ b/common/env_nowhere.c
@@ -32,6 +32,8 @@
 #include <environment.h>
 #include <linux/stddef.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 env_t *env_ptr = NULL;
 
 extern uchar default_environment[];
@@ -44,8 +46,6 @@ void env_relocate_spec (void)
 
 uchar env_get_char_spec (int index)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        return ( *((uchar *)(gd->env_addr + index)) );
 }
 
@@ -56,8 +56,6 @@ uchar env_get_char_spec (int index)
  */
 int  env_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->env_addr  = (ulong)&default_environment[0];
        gd->env_valid = 0;
 

diff --git a/common/env_nvram.c b/common/env_nvram.c
index a406e427a24e871f9ace82901483b434afd58272..7c18896cb04fa88b42ec92275547eacfa1d18406 100644 (file)
--- a/common/env_nvram.c
+++ b/common/env_nvram.c
@@ -42,6 +42,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */
 
 #include <command.h>
@@ -74,7 +76,6 @@ uchar env_get_char_spec (int index)
 
        return c;
 #else
-       DECLARE_GLOBAL_DATA_PTR;
        uchar retval;
        enable_nvram();
        retval = *((uchar *)(gd->env_addr + index));
@@ -92,8 +93,6 @@ uchar env_get_char_spec (int index)
 
        return c;
 #else
-       DECLARE_GLOBAL_DATA_PTR;
-
        return *((uchar *)(gd->env_addr + index));
 #endif
 }
@@ -135,7 +134,6 @@ int saveenv (void)
  */
 int env_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_AMIGAONEG3SE
        enable_nvram();
 #endif

diff --git a/common/exports.c b/common/exports.c
index 9858217ae0c3db1b0e28df5be9b41a995b39f52a..ef253381697bad29490770936869e62e082fb237 100644 (file)
--- a/common/exports.c
+++ b/common/exports.c
@@ -1,6 +1,8 @@
 #include <common.h>
 #include <exports.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static void dummy(void)
 {
 }
@@ -12,7 +14,6 @@ unsigned long get_version(void)
 
 void jumptable_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int i;
 
        gd->jt = (void **) malloc (XF_MAX * sizeof (void *));

diff --git a/common/ft_build.c b/common/ft_build.c
index 65a274f84087eea80f94d76b4f9987a081845617..9e9c906fc1f9cb27c0d6078d1967fa1a6e6e1b03 100644 (file)
--- a/common/ft_build.c
+++ b/common/ft_build.c
@@ -163,7 +163,7 @@ void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size)
        ((u64 *) cxt->pres)[0] = cpu_to_be64(physaddr); /* phys = 0, size = 0, terminate */
        ((u64 *) cxt->pres)[1] = cpu_to_be64(size);
 
-       cxt->pres += 18;        /* advance */
+       cxt->pres += 16;        /* advance */
 
        ((u64 *) cxt->pres)[0] = 0;     /* phys = 0, size = 0, terminate */
        ((u64 *) cxt->pres)[1] = 0;
@@ -529,6 +529,7 @@ extern uchar(*env_get_char) (int);
 
 #define BDM(x) {       .name = #x, .offset = offsetof(bd_t, bi_ ##x ) }
 
+#ifdef CONFIG_OF_HAS_BD_T
 static const struct {
        const char *name;
        int offset;
@@ -574,19 +575,24 @@ static const struct {
 #endif
        BDM(baudrate),
 };
+#endif
 
-void ft_setup(void *blob, int size, bd_t * bd)
+void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-       u8 *end;
        u32 *p;
        int len;
        struct ft_cxt cxt;
-       int i, k, nxt;
-       static char tmpenv[256];
-       char *s, *lval, *rval;
        ulong clock;
-       uint32_t v;
+#if defined(CONFIG_OF_HAS_UBOOT_ENV)
+       int k, nxt;
+#endif
+#if defined(CONFIG_OF_HAS_BD_T)
+       u8 *end;
+#endif
+#if defined(CONFIG_OF_HAS_UBOOT_ENV) || defined(CONFIG_OF_HAS_BD_T)
+       int i;
+       static char tmpenv[256];
+#endif
 
        /* disable OF tree; booting old kernel */
        if (getenv("disable_of") != NULL) {
@@ -596,7 +602,8 @@ void ft_setup(void *blob, int size, bd_t * bd)
 
        ft_begin(&cxt, blob, size);
 
-       /* fs_add_rsvmap not used */
+       if (initrd_start && initrd_end)
+               ft_add_rsvmap(&cxt, initrd_start, initrd_end - initrd_start + 1);
 
        ft_begin_tree(&cxt);
 
@@ -610,9 +617,12 @@ void ft_setup(void *blob, int size, bd_t * bd)
        /* back into root */
        ft_backtrack_node(&cxt);
 
+#ifdef CONFIG_OF_HAS_UBOOT_ENV
        ft_begin_node(&cxt, "u-boot-env");
 
        for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
+               char *s, *lval, *rval;
+
                for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) ;
                s = tmpenv;
                for (k = i; k < nxt && s < &tmpenv[sizeof(tmpenv) - 1]; ++k)
@@ -629,12 +639,20 @@ void ft_setup(void *blob, int size, bd_t * bd)
        }
 
        ft_end_node(&cxt);
+#endif
 
        ft_begin_node(&cxt, "chosen");
 
        ft_prop_str(&cxt, "name", "chosen");
        ft_prop_str(&cxt, "bootargs", getenv("bootargs"));
        ft_prop_int(&cxt, "linux,platform", 0x600);     /* what is this? */
+       if (initrd_start && initrd_end) {
+               ft_prop_int(&cxt, "linux,initrd-start", initrd_start);
+               ft_prop_int(&cxt, "linux,initrd-end", initrd_end);
+       }
+#ifdef OF_STDOUT_PATH
+       ft_prop_str(&cxt, "linux,stdout-path", OF_STDOUT_PATH);
+#endif
 
        ft_end_node(&cxt);
 
@@ -647,14 +665,19 @@ void ft_setup(void *blob, int size, bd_t * bd)
           ft_dump_blob(blob);
         */
 
+#ifdef CONFIG_OF_HAS_BD_T
        /* paste the bd_t at the end of the flat tree */
        end = (char *)blob +
            be32_to_cpu(((struct boot_param_header *)blob)->totalsize);
        memcpy(end, bd, sizeof(*bd));
+#endif
 
 #ifdef CONFIG_PPC
 
+#ifdef CONFIG_OF_HAS_BD_T
        for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) {
+               uint32_t v;
+
                sprintf(tmpenv, "/bd_t/%s", bd_map[i].name);
                v = *(uint32_t *)((char *)bd + bd_map[i].offset);
 
@@ -670,6 +693,7 @@ void ft_setup(void *blob, int size, bd_t * bd)
        p = ft_get_prop(blob, "/bd_t/ethspeed", &len);
        if (p != NULL)
                *p = cpu_to_be32((uint32_t) bd->bi_ethspeed);
+#endif
 
        clock = bd->bi_intfreq;
        p = ft_get_prop(blob, "/cpus/" OF_CPU "/clock-frequency", &len);
@@ -680,11 +704,14 @@ void ft_setup(void *blob, int size, bd_t * bd)
        clock = OF_TBCLK;
        p = ft_get_prop(blob, "/cpus/" OF_CPU "/timebase-frequency", &len);
        if (p != NULL)
-               *p = cpu_to_be32(OF_TBCLK);
+               *p = cpu_to_be32(clock);
 #endif
-
 #endif                         /* __powerpc__ */
 
+#ifdef CONFIG_OF_BOARD_SETUP
+       ft_board_setup(blob, bd);
+#endif
+
        /*
           printf("final OF-tree\n");
           ft_dump_blob(blob);

diff --git a/common/hush.c b/common/hush.c
index bb5041a08d872d93b04077fab9edadbd02fca12c..feb5627ff2eef282b16312cbccca13b208b7ed96 100644 (file)
--- a/common/hush.c
+++ b/common/hush.c
@@ -138,6 +138,8 @@ extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);      /
 #endif
 
 #ifdef __U_BOOT__
+DECLARE_GLOBAL_DATA_PTR;
+
 #define EXIT_SUCCESS 0
 #define EOF -1
 #define syntax() syntax_err()
@@ -3272,7 +3274,6 @@ int parse_file_outer(void)
 #ifdef __U_BOOT__
 static void u_boot_hush_reloc(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned long addr;
        struct reserved_combo *r;
 

diff --git a/common/lcd.c b/common/lcd.c
index e64972fd813a6e10ade52623140df65fa234249c..0be1912a359e56dfb1b1f63139e8633764793902 100644 (file)
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -50,7 +50,6 @@
 #include <lcdvideo.h>
 #endif
 
-
 #ifdef CONFIG_LCD
 
 /************************************************************************/
@@ -68,6 +67,8 @@
 # endif
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 ulong lcd_setmem (ulong addr);
 
 static void lcd_drawchars (ushort x, ushort y, uchar *str, int count);
@@ -339,8 +340,6 @@ static void test_pattern (void)
 
 int drv_lcd_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        device_t lcddev;
        int rc;
 
@@ -682,8 +681,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 static void *lcd_logo (void)
 {
 #ifdef CONFIG_LCD_INFO
-       DECLARE_GLOBAL_DATA_PTR;
-
        char info[80];
        char temp[32];
 #endif /* CONFIG_LCD_INFO */

diff --git a/common/lynxkdi.c b/common/lynxkdi.c
index 797d8cc880d35594213ed55a8147eaee410e0c4d..76a271b966d76a82140572c5108dcb726631a117 100644 (file)
--- a/common/lynxkdi.c
+++ b/common/lynxkdi.c
@@ -20,14 +20,15 @@
 #if defined(CONFIG_LYNXKDI)
 #include <lynxkdi.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_MPC8260) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 void lynxkdi_boot ( image_header_t *hdr )
 {
-       void (*lynxkdi)(void) = (void(*)(void))hdr->ih_ep;
+       void (*lynxkdi)(void) = (void(*)(void)) ntohl(hdr->ih_ep);
        lynxos_bootparms_t *parms = (lynxos_bootparms_t *)0x0020;
        bd_t *kbd;
-       DECLARE_GLOBAL_DATA_PTR;
-       u32 *psz = (u32 *)(hdr->ih_load + 0x0204);
+       u32 *psz = (u32 *)(ntohl(hdr->ih_load) + 0x0204);
 
        memset( parms, 0, sizeof(*parms));
        kbd = gd->bd;
@@ -39,9 +40,9 @@ void lynxkdi_boot ( image_header_t *hdr )
        /* Do a simple check for Bluecat so we can pass the
         * kernel command line parameters.
         */
-       if( le32_to_cpu(*psz) == hdr->ih_size ){
+       if( le32_to_cpu(*psz) == ntohl(hdr->ih_size) ){ /* FIXME: NOT SURE HERE ! */
            char *args;
-           char *cmdline = (char *)(hdr->ih_load + 0x020c);
+           char *cmdline = (char *)(ntohl(hdr->ih_load) + 0x020c);
            int len;
 
            printf("Booting Bluecat KDI ...\n");

diff --git a/common/main.c b/common/main.c
index f042f3a636fd6171ce2f96c6f8a15b49fb33169b..758ef8d32b2ba15d025bbf311d539c0b82e4fd6a 100644 (file)
--- a/common/main.c
+++ b/common/main.c
@@ -36,6 +36,10 @@
 
 #include <post.h>
 
+#ifdef CONFIG_SILENT_CONSOLE
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 #if defined(CONFIG_BOOT_RETRY_TIME) && defined(CONFIG_RESET_TO_RETRY)
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);              /* for do_reset() prototype */
 #endif
@@ -105,14 +109,10 @@ static __inline__ int abortboot(int bootdelay)
        u_int i;
 
 #ifdef CONFIG_SILENT_CONSOLE
-       {
-               DECLARE_GLOBAL_DATA_PTR;
-
-               if (gd->flags & GD_FLG_SILENT) {
-                       /* Restore serial console */
-                       console_assign (stdout, "serial");
-                       console_assign (stderr, "serial");
-               }
+       if (gd->flags & GD_FLG_SILENT) {
+               /* Restore serial console */
+               console_assign (stdout, "serial");
+               console_assign (stderr, "serial");
        }
 #endif
 
@@ -195,17 +195,13 @@ static __inline__ int abortboot(int bootdelay)
 #  endif
 
 #ifdef CONFIG_SILENT_CONSOLE
-       {
-               DECLARE_GLOBAL_DATA_PTR;
-
-               if (abort) {
-                       /* permanently enable normal console output */
-                       gd->flags &= ~(GD_FLG_SILENT);
-               } else if (gd->flags & GD_FLG_SILENT) {
-                       /* Restore silent console */
-                       console_assign (stdout, "nulldev");
-                       console_assign (stderr, "nulldev");
-               }
+       if (abort) {
+               /* permanently enable normal console output */
+               gd->flags &= ~(GD_FLG_SILENT);
+       } else if (gd->flags & GD_FLG_SILENT) {
+               /* Restore silent console */
+               console_assign (stdout, "nulldev");
+               console_assign (stderr, "nulldev");
        }
 #endif
 
@@ -223,14 +219,10 @@ static __inline__ int abortboot(int bootdelay)
        int abort = 0;
 
 #ifdef CONFIG_SILENT_CONSOLE
-       {
-               DECLARE_GLOBAL_DATA_PTR;
-
-               if (gd->flags & GD_FLG_SILENT) {
-                       /* Restore serial console */
-                       console_assign (stdout, "serial");
-                       console_assign (stderr, "serial");
-               }
+       if (gd->flags & GD_FLG_SILENT) {
+               /* Restore serial console */
+               console_assign (stdout, "serial");
+               console_assign (stderr, "serial");
        }
 #endif
 
@@ -279,17 +271,13 @@ static __inline__ int abortboot(int bootdelay)
        putc ('\n');
 
 #ifdef CONFIG_SILENT_CONSOLE
-       {
-               DECLARE_GLOBAL_DATA_PTR;
-
-               if (abort) {
-                       /* permanently enable normal console output */
-                       gd->flags &= ~(GD_FLG_SILENT);
-               } else if (gd->flags & GD_FLG_SILENT) {
-                       /* Restore silent console */
-                       console_assign (stdout, "nulldev");
-                       console_assign (stderr, "nulldev");
-               }
+       if (abort) {
+               /* permanently enable normal console output */
+               gd->flags &= ~(GD_FLG_SILENT);
+       } else if (gd->flags & GD_FLG_SILENT) {
+               /* Restore silent console */
+               console_assign (stdout, "nulldev");
+               console_assign (stderr, "nulldev");
        }
 #endif
 
@@ -919,7 +907,10 @@ int run_command (const char *cmd, int flag)
                process_macros (token, finaltoken);
 
                /* Extract arguments */
-               argc = parse_line (finaltoken, argv);
+               if ((argc = parse_line (finaltoken, argv)) == 0) {
+                       rc = -1;        /* no command at all */
+                       continue;
+               }
 
                /* Look up command in command table */
                if ((cmdtp = find_cmd(argv[0])) == NULL) {
@@ -945,9 +936,9 @@ int run_command (const char *cmd, int flag)
                                puts ("'bootd' recursion detected\n");
                                rc = -1;
                                continue;
-                       }
-                       else
+                       } else {
                                flag |= CMD_FLAG_BOOTD;
+                       }
                }
 #endif /* CFG_CMD_BOOTD */
 

diff --git a/common/serial.c b/common/serial.c
index 22d8fd0584febae96c2083a7bc6dc6d489488d4c..2acbd08b16d2c09c4f70c63e9894867ed0feba9c 100644 (file)
--- a/common/serial.c
+++ b/common/serial.c
@@ -25,6 +25,8 @@
 #include <serial.h>
 #include <devices.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_SERIAL_MULTI)
 
 static struct serial_device *serial_devices = NULL;
@@ -49,8 +51,6 @@ struct serial_device *default_serial_console (void)
 
 static int serial_register (struct serial_device *dev)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        dev->init += gd->reloc_off;
        dev->setbrg += gd->reloc_off;
        dev->getc += gd->reloc_off;
@@ -131,8 +131,6 @@ void serial_reinit_all (void)
 
 int serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
                struct serial_device *dev = default_serial_console ();
 
@@ -144,8 +142,6 @@ int serial_init (void)
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
                struct serial_device *dev = default_serial_console ();
 
@@ -158,8 +154,6 @@ void serial_setbrg (void)
 
 int serial_getc (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
                struct serial_device *dev = default_serial_console ();
 
@@ -171,8 +165,6 @@ int serial_getc (void)
 
 int serial_tstc (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
                struct serial_device *dev = default_serial_console ();
 
@@ -184,8 +176,6 @@ int serial_tstc (void)
 
 void serial_putc (const char c)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
                struct serial_device *dev = default_serial_console ();
 
@@ -198,8 +188,6 @@ void serial_putc (const char c)
 
 void serial_puts (const char *s)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
                struct serial_device *dev = default_serial_console ();
 

diff --git a/common/soft_i2c.c b/common/soft_i2c.c
index 3d0e08c6ff3866f295913bd576b80bb230992ff2..bffcd4405ec5bbe5d550ec471f6e5f4657bd33fa 100644 (file)
--- a/common/soft_i2c.c
+++ b/common/soft_i2c.c
@@ -39,6 +39,10 @@
 
 /* #define     DEBUG_I2C       */
 
+#ifdef DEBUG_I2C
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 
 /*-----------------------------------------------------------------------
  * Definitions
@@ -53,7 +57,6 @@
 
 #ifdef DEBUG_I2C
 #define PRINTD(fmt,args...)    do {    \
-       DECLARE_GLOBAL_DATA_PTR;        \
        if (gd->have_console)           \
                printf (fmt ,##args);   \
        } while (0)
@@ -164,13 +167,10 @@ static void send_ack(int ack)
        volatile immap_t *immr = (immap_t *)CFG_IMMR;
 #endif
 
-       I2C_ACTIVE;
        I2C_SCL(0);
        I2C_DELAY;
-
-       I2C_SDA(ack);
-
        I2C_ACTIVE;
+       I2C_SDA(ack);
        I2C_DELAY;
        I2C_SCL(1);
        I2C_DELAY;
@@ -288,7 +288,10 @@ int i2c_probe(uchar addr)
 {
        int rc;
 
-       /* perform 1 byte read transaction */
+       /*
+        * perform 1 byte write transaction with just address byte
+        * (fake write)
+        */
        send_start();
        rc = write_byte ((addr << 1) | 0);
        send_stop();

diff --git a/common/xyzModem.c b/common/xyzModem.c
new file mode 100644 (file)
index 0000000..4a137bf
--- /dev/null
+++ b/common/xyzModem.c
@@ -0,0 +1,743 @@
+/*
+ *==========================================================================
+ *
+ *      xyzModem.c
+ *
+ *      RedBoot stream handler for xyzModem protocol
+ *
+ *==========================================================================
+ *####ECOSGPLCOPYRIGHTBEGIN####
+ * -------------------------------------------
+ * This file is part of eCos, the Embedded Configurable Operating System.
+ * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+ * Copyright (C) 2002 Gary Thomas
+ *
+ * eCos is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 or (at your option) any later version.
+ *
+ * eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+ * WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with eCos; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * As a special exception, if other files instantiate templates or use macros
+ * or inline functions from this file, or you compile this file and link it
+ * with other works to produce a work based on this file, this file does not
+ * by itself cause the resulting work to be covered by the GNU General Public
+ * License. However the source code for this file must still be made available
+ * in accordance with section (3) of the GNU General Public License.
+ *
+ * This exception does not invalidate any other reasons why a work based on
+ * this file might be covered by the GNU General Public License.
+ *
+ * Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+ * at http: *sources.redhat.com/ecos/ecos-license/
+ * -------------------------------------------
+ *####ECOSGPLCOPYRIGHTEND####
+ *==========================================================================
+ *#####DESCRIPTIONBEGIN####
+ *
+ * Author(s):    gthomas
+ * Contributors: gthomas, tsmith, Yoshinori Sato
+ * Date:         2000-07-14
+ * Purpose:
+ * Description:
+ *
+ * This code is part of RedBoot (tm).
+ *
+ *####DESCRIPTIONEND####
+ *
+ *==========================================================================
+ */
+#include <common.h>
+#include <xyzModem.h>
+#include <stdarg.h>
+#include <crc.h>
+
+/* Assumption - run xyzModem protocol over the console port */
+
+/* Values magic to the protocol */
+#define SOH 0x01
+#define STX 0x02
+#define EOT 0x04
+#define ACK 0x06
+#define BSP 0x08
+#define NAK 0x15
+#define CAN 0x18
+#define EOF 0x1A  /* ^Z for DOS officionados */
+
+#define USE_YMODEM_LENGTH
+
+/* Data & state local to the protocol */
+static struct {
+#ifdef REDBOOT
+    hal_virtual_comm_table_t* __chan;
+#else
+    int *__chan;
+#endif
+    unsigned char pkt[1024], *bufp;
+    unsigned char blk,cblk,crc1,crc2;
+    unsigned char next_blk;  /* Expected block */
+    int len, mode, total_retries;
+    int total_SOH, total_STX, total_CAN;
+    bool crc_mode, at_eof, tx_ack;
+#ifdef USE_YMODEM_LENGTH
+    unsigned long file_length, read_length;
+#endif
+} xyz;
+
+#define xyzModem_CHAR_TIMEOUT            2000  /* 2 seconds */
+#define xyzModem_MAX_RETRIES             20
+#define xyzModem_MAX_RETRIES_WITH_CRC    10
+#define xyzModem_CAN_COUNT                3    /* Wait for 3 CAN before quitting */
+
+
+#ifndef REDBOOT  /*SB */
+typedef int cyg_int32;
+int CYGACC_COMM_IF_GETC_TIMEOUT (char chan,char *c) {
+#define DELAY 20
+       unsigned long counter=0;
+       while (!tstc() && (counter < xyzModem_CHAR_TIMEOUT*1000/DELAY)) {
+               udelay(DELAY);
+               counter++;
+       }
+       if (tstc()) {
+               *c=getc();
+               return 1;
+       }
+       return 0;
+}
+
+void CYGACC_COMM_IF_PUTC(char x,char y) {
+       putc(y);
+}
+
+/* Validate a hex character */
+__inline__ static bool
+_is_hex(char c)
+{
+    return (((c >= '0') && (c <= '9')) ||
+            ((c >= 'A') && (c <= 'F')) ||
+            ((c >= 'a') && (c <= 'f')));
+}
+
+/* Convert a single hex nibble */
+__inline__ static int
+_from_hex(char c)
+{
+    int ret = 0;
+
+    if ((c >= '0') && (c <= '9')) {
+        ret = (c - '0');
+    } else if ((c >= 'a') && (c <= 'f')) {
+        ret = (c - 'a' + 0x0a);
+    } else if ((c >= 'A') && (c <= 'F')) {
+        ret = (c - 'A' + 0x0A);
+    }
+    return ret;
+}
+
+/* Convert a character to lower case */
+__inline__ static char
+_tolower(char c)
+{
+    if ((c >= 'A') && (c <= 'Z')) {
+        c = (c - 'A') + 'a';
+    }
+    return c;
+}
+
+/* Parse (scan) a number */
+bool
+parse_num(char *s, unsigned long *val, char **es, char *delim)
+{
+    bool first = true;
+    int radix = 10;
+    char c;
+    unsigned long result = 0;
+    int digit;
+
+    while (*s == ' ') s++;
+    while (*s) {
+        if (first && (s[0] == '0') && (_tolower(s[1]) == 'x')) {
+            radix = 16;
+            s += 2;
+        }
+        first = false;
+        c = *s++;
+        if (_is_hex(c) && ((digit = _from_hex(c)) < radix)) {
+            /* Valid digit */
+#ifdef CYGPKG_HAL_MIPS
+            /* FIXME: tx49 compiler generates 0x2539018 for MUL which */
+            /* isn't any good. */
+            if (16 == radix)
+                result = result << 4;
+            else
+                result = 10 * result;
+            result += digit;
+#else
+            result = (result * radix) + digit;
+#endif
+        } else {
+            if (delim != (char *)0) {
+                /* See if this character is one of the delimiters */
+                char *dp = delim;
+                while (*dp && (c != *dp)) dp++;
+                if (*dp) break;  /* Found a good delimiter */
+            }
+            return false;  /* Malformatted number */
+        }
+    }
+    *val = result;
+    if (es != (char **)0) {
+        *es = s;
+    }
+    return true;
+}
+
+#endif
+
+#define USE_SPRINTF
+#ifdef DEBUG
+#ifndef USE_SPRINTF
+/*
+ * Note: this debug setup only works if the target platform has two serial ports
+ * available so that the other one (currently only port 1) can be used for debug
+ * messages.
+ */
+static int
+zm_dprintf(char *fmt, ...)
+{
+    int cur_console;
+    va_list args;
+
+    va_start(args, fmt);
+#ifdef REDBOOT
+    cur_console = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
+#endif
+    diag_vprintf(fmt, args);
+#ifdef REDBOOT
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur_console);
+#endif
+}
+
+static void
+zm_flush(void)
+{
+}
+
+#else
+/*
+ * Note: this debug setup works by storing the strings in a fixed buffer
+ */
+#define FINAL
+#ifdef FINAL
+static char *zm_out = (char *)0x00380000;
+static char *zm_out_start = (char *)0x00380000;
+#else
+static char zm_buf[8192];
+static char *zm_out=zm_buf;
+static char *zm_out_start = zm_buf;
+
+#endif
+static int
+zm_dprintf(char *fmt, ...)
+{
+    int len;
+    va_list args;
+
+    va_start(args, fmt);
+    len = diag_vsprintf(zm_out, fmt, args);
+    zm_out += len;
+    return len;
+}
+
+static void
+zm_flush(void)
+{
+    char *p = zm_out_start;
+#ifdef REDBOOT
+    while (*p) mon_write_char(*p++);
+#endif
+    zm_out = zm_out_start;
+}
+#endif
+
+static void
+zm_dump_buf(void *buf, int len)
+{
+#ifdef REDBOOT
+    diag_vdump_buf_with_offset(zm_dprintf, buf, len, 0);
+#else
+
+#endif
+}
+
+static unsigned char zm_buf[2048];
+static unsigned char *zm_bp;
+
+static void
+zm_new(void)
+{
+    zm_bp = zm_buf;
+}
+
+static void
+zm_save(unsigned char c)
+{
+    *zm_bp++ = c;
+}
+
+static void
+zm_dump(int line)
+{
+    zm_dprintf("Packet at line: %d\n", line);
+    zm_dump_buf(zm_buf, zm_bp-zm_buf);
+}
+
+#define ZM_DEBUG(x) x
+#else
+#define ZM_DEBUG(x)
+#endif
+
+/* Wait for the line to go idle */
+static void
+xyzModem_flush(void)
+{
+    int res;
+    char c;
+    while (true) {
+        res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c);
+        if (!res) return;
+    }
+}
+
+static int
+xyzModem_get_hdr(void)
+{
+    char c;
+    int res;
+    bool hdr_found = false;
+    int i, can_total, hdr_chars;
+    unsigned short cksum;
+
+    ZM_DEBUG(zm_new());
+    /* Find the start of a header */
+    can_total = 0;
+    hdr_chars = 0;
+
+    if (xyz.tx_ack) {
+        CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
+        xyz.tx_ack = false;
+    }
+    while (!hdr_found) {
+        res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c);
+        ZM_DEBUG(zm_save(c));
+        if (res) {
+            hdr_chars++;
+            switch (c) {
+            case SOH:
+                xyz.total_SOH++;
+            case STX:
+                if (c == STX) xyz.total_STX++;
+                hdr_found = true;
+                break;
+            case CAN:
+                xyz.total_CAN++;
+                ZM_DEBUG(zm_dump(__LINE__));
+                if (++can_total == xyzModem_CAN_COUNT) {
+                    return xyzModem_cancel;
+                } else {
+                    /* Wait for multiple CAN to avoid early quits */
+                    break;
+                }
+            case EOT:
+                /* EOT only supported if no noise */
+                if (hdr_chars == 1) {
+                    CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
+                    ZM_DEBUG(zm_dprintf("ACK on EOT #%d\n", __LINE__));
+                    ZM_DEBUG(zm_dump(__LINE__));
+                    return xyzModem_eof;
+                }
+            default:
+                /* Ignore, waiting for start of header */
+                ;
+            }
+        } else {
+            /* Data stream timed out */
+            xyzModem_flush();  /* Toss any current input */
+            ZM_DEBUG(zm_dump(__LINE__));
+            CYGACC_CALL_IF_DELAY_US((cyg_int32)250000);
+            return xyzModem_timeout;
+        }
+    }
+
+    /* Header found, now read the data */
+    res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &xyz.blk);
+    ZM_DEBUG(zm_save(xyz.blk));
+    if (!res) {
+        ZM_DEBUG(zm_dump(__LINE__));
+        return xyzModem_timeout;
+    }
+    res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &xyz.cblk);
+    ZM_DEBUG(zm_save(xyz.cblk));
+    if (!res) {
+        ZM_DEBUG(zm_dump(__LINE__));
+        return xyzModem_timeout;
+    }
+    xyz.len = (c == SOH) ? 128 : 1024;
+    xyz.bufp = xyz.pkt;
+    for (i = 0;  i < xyz.len;  i++) {
+        res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c);
+        ZM_DEBUG(zm_save(c));
+        if (res) {
+            xyz.pkt[i] = c;
+        } else {
+            ZM_DEBUG(zm_dump(__LINE__));
+            return xyzModem_timeout;
+        }
+    }
+    res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &xyz.crc1);
+    ZM_DEBUG(zm_save(xyz.crc1));
+    if (!res) {
+        ZM_DEBUG(zm_dump(__LINE__));
+        return xyzModem_timeout;
+    }
+    if (xyz.crc_mode) {
+        res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &xyz.crc2);
+        ZM_DEBUG(zm_save(xyz.crc2));
+        if (!res) {
+            ZM_DEBUG(zm_dump(__LINE__));
+            return xyzModem_timeout;
+        }
+    }
+    ZM_DEBUG(zm_dump(__LINE__));
+    /* Validate the message */
+    if ((xyz.blk ^ xyz.cblk) != (unsigned char)0xFF) {
+        ZM_DEBUG(zm_dprintf("Framing error - blk: %x/%x/%x\n", xyz.blk, xyz.cblk, (xyz.blk ^ xyz.cblk)));
+        ZM_DEBUG(zm_dump_buf(xyz.pkt, xyz.len));
+        xyzModem_flush();
+        return xyzModem_frame;
+    }
+    /* Verify checksum/CRC */
+    if (xyz.crc_mode) {
+        cksum = cyg_crc16(xyz.pkt, xyz.len);
+        if (cksum != ((xyz.crc1 << 8) | xyz.crc2)) {
+            ZM_DEBUG(zm_dprintf("CRC error - recvd: %02x%02x, computed: %x\n",
+                                xyz.crc1, xyz.crc2, cksum & 0xFFFF));
+            return xyzModem_cksum;
+        }
+    } else {
+        cksum = 0;
+        for (i = 0;  i < xyz.len;  i++) {
+            cksum += xyz.pkt[i];
+        }
+        if (xyz.crc1 != (cksum & 0xFF)) {
+            ZM_DEBUG(zm_dprintf("Checksum error - recvd: %x, computed: %x\n", xyz.crc1, cksum & 0xFF));
+            return xyzModem_cksum;
+        }
+    }
+    /* If we get here, the message passes [structural] muster */
+    return 0;
+}
+
+int
+xyzModem_stream_open(connection_info_t *info, int *err)
+{
+    int console_chan, stat=0;
+    int retries = xyzModem_MAX_RETRIES;
+    int crc_retries = xyzModem_MAX_RETRIES_WITH_CRC;
+
+/*    ZM_DEBUG(zm_out = zm_out_start); */
+#ifdef xyzModem_zmodem
+    if (info->mode == xyzModem_zmodem) {
+        *err = xyzModem_noZmodem;
+        return -1;
+    }
+#endif
+
+#ifdef REDBOOT
+    /* Set up the I/O channel.  Note: this allows for using a different port in the future */
+    console_chan = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+    if (info->chan >= 0) {
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(info->chan);
+    } else {
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(console_chan);
+    }
+    xyz.__chan = CYGACC_CALL_IF_CONSOLE_PROCS();
+
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(console_chan);
+    CYGACC_COMM_IF_CONTROL(*xyz.__chan, __COMMCTL_SET_TIMEOUT, xyzModem_CHAR_TIMEOUT);
+#else
+/* TODO: CHECK ! */
+    int dummy;
+    xyz.__chan=&dummy;
+#endif
+    xyz.len = 0;
+    xyz.crc_mode = true;
+    xyz.at_eof = false;
+    xyz.tx_ack = false;
+    xyz.mode = info->mode;
+    xyz.total_retries = 0;
+    xyz.total_SOH = 0;
+    xyz.total_STX = 0;
+    xyz.total_CAN = 0;
+#ifdef USE_YMODEM_LENGTH
+    xyz.read_length = 0;
+    xyz.file_length = 0;
+#endif
+
+    CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
+
+    if (xyz.mode == xyzModem_xmodem) {
+           /* X-modem doesn't have an information header - exit here */
+            xyz.next_blk = 1;
+            return 0;
+    }
+
+    while (retries-- > 0) {
+        stat = xyzModem_get_hdr();
+        if (stat == 0) {
+            /* Y-modem file information header */
+            if (xyz.blk == 0) {
+#ifdef USE_YMODEM_LENGTH
+                /* skip filename */
+                while (*xyz.bufp++);
+                /* get the length */
+                parse_num(xyz.bufp, &xyz.file_length, NULL, " ");
+#endif
+                /* The rest of the file name data block quietly discarded */
+                xyz.tx_ack = true;
+            }
+            xyz.next_blk = 1;
+            xyz.len = 0;
+            return 0;
+        } else
+        if (stat == xyzModem_timeout) {
+            if (--crc_retries <= 0) xyz.crc_mode = false;
+            CYGACC_CALL_IF_DELAY_US(5*100000);   /* Extra delay for startup */
+            CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
+            xyz.total_retries++;
+            ZM_DEBUG(zm_dprintf("NAK (%d)\n", __LINE__));
+        }
+        if (stat == xyzModem_cancel) {
+            break;
+        }
+    }
+    *err = stat;
+    ZM_DEBUG(zm_flush());
+    return -1;
+}
+
+int
+xyzModem_stream_read(char *buf, int size, int *err)
+{
+    int stat, total, len;
+    int retries;
+
+    total = 0;
+    stat = xyzModem_cancel;
+    /* Try and get 'size' bytes into the buffer */
+    while (!xyz.at_eof && (size > 0)) {
+        if (xyz.len == 0) {
+            retries = xyzModem_MAX_RETRIES;
+            while (retries-- > 0) {
+                stat = xyzModem_get_hdr();
+                if (stat == 0) {
+                    if (xyz.blk == xyz.next_blk) {
+                        xyz.tx_ack = true;
+                        ZM_DEBUG(zm_dprintf("ACK block %d (%d)\n", xyz.blk, __LINE__));
+                        xyz.next_blk = (xyz.next_blk + 1) & 0xFF;
+
+#if defined(xyzModem_zmodem) || defined(USE_YMODEM_LENGTH)
+                        if (xyz.mode == xyzModem_xmodem || xyz.file_length == 0) {
+#else
+                        if (1) {
+#endif
+                            /* Data blocks can be padded with ^Z (EOF) characters */
+                            /* This code tries to detect and remove them */
+                            if ((xyz.bufp[xyz.len-1] == EOF) &&
+                                (xyz.bufp[xyz.len-2] == EOF) &&
+                                (xyz.bufp[xyz.len-3] == EOF)) {
+                                while (xyz.len && (xyz.bufp[xyz.len-1] == EOF)) {
+                                    xyz.len--;
+                                }
+                            }
+                        }
+
+#ifdef USE_YMODEM_LENGTH
+                       /*
+                         * See if accumulated length exceeds that of the file.
+                         * If so, reduce size (i.e., cut out pad bytes)
+                         * Only do this for Y-modem (and Z-modem should it ever
+                         * be supported since it can fall back to Y-modem mode).
+                        */
+                        if (xyz.mode != xyzModem_xmodem && 0 != xyz.file_length) {
+                            xyz.read_length += xyz.len;
+                            if (xyz.read_length > xyz.file_length) {
+                                xyz.len -= (xyz.read_length - xyz.file_length);
+                            }
+                        }
+#endif
+                        break;
+                    } else if (xyz.blk == ((xyz.next_blk - 1) & 0xFF)) {
+                        /* Just re-ACK this so sender will get on with it */
+                        CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
+                        continue;  /* Need new header */
+                    } else {
+                        stat = xyzModem_sequence;
+                    }
+                }
+                if (stat == xyzModem_cancel) {
+                    break;
+                }
+                if (stat == xyzModem_eof) {
+                    CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
+                    ZM_DEBUG(zm_dprintf("ACK (%d)\n", __LINE__));
+                    if (xyz.mode == xyzModem_ymodem) {
+                        CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
+                        xyz.total_retries++;
+                        ZM_DEBUG(zm_dprintf("Reading Final Header\n"));
+                        stat = xyzModem_get_hdr();
+                        CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
+                        ZM_DEBUG(zm_dprintf("FINAL ACK (%d)\n", __LINE__));
+                    }
+                    xyz.at_eof = true;
+                    break;
+                }
+                CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
+                xyz.total_retries++;
+                ZM_DEBUG(zm_dprintf("NAK (%d)\n", __LINE__));
+            }
+            if (stat < 0) {
+                *err = stat;
+                xyz.len = -1;
+                return total;
+            }
+        }
+        /* Don't "read" data from the EOF protocol package */
+        if (!xyz.at_eof) {
+            len = xyz.len;
+            if (size < len) len = size;
+            memcpy(buf, xyz.bufp, len);
+            size -= len;
+            buf += len;
+            total += len;
+            xyz.len -= len;
+            xyz.bufp += len;
+        }
+    }
+    return total;
+}
+
+void
+xyzModem_stream_close(int *err)
+{
+    diag_printf("xyzModem - %s mode, %d(SOH)/%d(STX)/%d(CAN) packets, %d retries\n",
+                xyz.crc_mode ? "CRC" : "Cksum",
+                xyz.total_SOH, xyz.total_STX, xyz.total_CAN,
+                xyz.total_retries);
+    ZM_DEBUG(zm_flush());
+}
+
+/* Need to be able to clean out the input buffer, so have to take the */
+/* getc */
+void xyzModem_stream_terminate(bool abort, int (*getc)(void))
+{
+  int c;
+
+  if (abort) {
+      ZM_DEBUG(zm_dprintf("!!!! TRANSFER ABORT !!!!\n"));
+      switch (xyz.mode) {
+       case xyzModem_xmodem:
+       case xyzModem_ymodem:
+         /* The X/YMODEM Spec seems to suggest that multiple CAN followed by an equal */
+         /* number of Backspaces is a friendly way to get the other end to abort. */
+         CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN);
+         CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN);
+         CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN);
+         CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN);
+         CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP);
+         CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP);
+         CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP);
+         CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP);
+         /* Now consume the rest of what's waiting on the line. */
+         ZM_DEBUG(zm_dprintf("Flushing serial line.\n"));
+         xyzModem_flush();
+          xyz.at_eof = true;
+       break;
+#ifdef xyzModem_zmodem
+       case xyzModem_zmodem:
+         /* Might support it some day I suppose. */
+#endif
+       break;
+      }
+  } else {
+      ZM_DEBUG(zm_dprintf("Engaging cleanup mode...\n"));
+      /*
+       * Consume any trailing crap left in the inbuffer from
+       * previous recieved blocks. Since very few files are an exact multiple
+       * of the transfer block size, there will almost always be some gunk here.
+       * If we don't eat it now, RedBoot will think the user typed it.
+       */
+      ZM_DEBUG(zm_dprintf("Trailing gunk:\n"));
+      while ((c = (*getc)()) > -1) ;
+      ZM_DEBUG(zm_dprintf("\n"));
+      /*
+       * Make a small delay to give terminal programs like minicom
+       * time to get control again after their file transfer program
+       * exits.
+       */
+      CYGACC_CALL_IF_DELAY_US((cyg_int32)250000);
+  }
+}
+
+char *
+xyzModem_error(int err)
+{
+    switch (err) {
+    case xyzModem_access:
+        return "Can't access file";
+        break;
+    case xyzModem_noZmodem:
+        return "Sorry, zModem not available yet";
+        break;
+    case xyzModem_timeout:
+        return "Timed out";
+        break;
+    case xyzModem_eof:
+        return "End of file";
+        break;
+    case xyzModem_cancel:
+        return "Cancelled";
+        break;
+    case xyzModem_frame:
+        return "Invalid framing";
+        break;
+    case xyzModem_cksum:
+        return "CRC/checksum error";
+        break;
+    case xyzModem_sequence:
+        return "Block sequence error";
+        break;
+    default:
+        return "Unknown error";
+        break;
+    }
+}
+
+/*
+ * RedBoot interface
+ */
+#if 0 /* SB */
+GETC_IO_FUNCS(xyzModem_io, xyzModem_stream_open, xyzModem_stream_close,
+              xyzModem_stream_terminate, xyzModem_stream_read, xyzModem_error);
+RedBoot_load(xmodem, xyzModem_io, false, false, xyzModem_xmodem);
+RedBoot_load(ymodem, xyzModem_io, false, false, xyzModem_ymodem);
+#endif

diff --git a/config.mk b/config.mk
index d85ac36b5e602c3e80c67c8c5cb1d767f6f49680..dfbb1b7c6f220f4f12f467e66fb76c7d979e5ae4 100644 (file)
--- a/config.mk
+++ b/config.mk
@@ -53,6 +53,10 @@ PLATFORM_CPPFLAGS+= -D__ARM__
 endif
 endif
 
+ifeq ($(ARCH),blackfin)
+PLATFORM_CPPFLAGS+= -D__BLACKFIN__ -mno-underscore
+endif
+
 ifdef  ARCH
 sinclude $(TOPDIR)/$(ARCH)_config.mk   # include architecture dependend rules
 endif

diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c
index 629ed66b07ec8769c2b96242475f75ec6c3d9994..706c880db1ea3a19f9edeada2ad14fe9a8269c09 100644 (file)
--- a/cpu/74xx_7xx/cpu.c
+++ b/cpu/74xx_7xx/cpu.c
@@ -49,6 +49,8 @@
 #include "../board/MAI/AmigaOneG3SE/memio.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 cpu_t
 get_cpu_type(void)
 {
@@ -111,8 +113,6 @@ get_cpu_type(void)
 #if !defined(CONFIG_BAB7xx)
 int checkcpu (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        uint type   = get_cpu_type();
        uint pvr    = get_pvr();
        ulong clock = gd->cpu_clk;
@@ -258,8 +258,6 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #ifdef CONFIG_AMIGAONEG3SE
 unsigned long get_tbclk(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        return (gd->bus_clk / 4);
 }
 #else  /* ! CONFIG_AMIGAONEG3SE */

diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c
index f94ff78711a089f201055c59c580f874db97407e..2dc510746d69e2c678b45c6536143623138a8901 100644 (file)
--- a/cpu/74xx_7xx/speed.c
+++ b/cpu/74xx_7xx/speed.c
@@ -29,6 +29,8 @@
 #include "../board/MAI/AmigaOneG3SE/via686.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static const int hid1_multipliers_x_10[] = {
        25,     /* 0000 - 2.5x */
        75,     /* 0001 - 7.5x */
@@ -85,7 +87,6 @@ static const int hid1_fx_multipliers_x_10[] = {
 
 int get_clocks (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        ulong clock = 0;
 
        /* calculate the clock frequency based upon the CPU type */

diff --git a/cpu/74xx_7xx/traps.c b/cpu/74xx_7xx/traps.c
index ac5f8bfeb50df7d20593ccd472ab7fb57792d51d..50c5eeb4835802635bf1e0eec0fe880e2bfe0171 100644 (file)
--- a/cpu/74xx_7xx/traps.c
+++ b/cpu/74xx_7xx/traps.c
@@ -36,6 +36,10 @@
 #include <command.h>
 #include <asm/processor.h>
 
+#ifdef CONFIG_AMIGAONEG3SE
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 int (*debugger_exception_handler)(struct pt_regs *) = 0;
 #endif
@@ -58,9 +62,6 @@ extern unsigned long search_exception_table(unsigned long);
 void
 print_backtrace(unsigned long *sp)
 {
-#ifdef CONFIG_AMIGAONEG3SE
-       DECLARE_GLOBAL_DATA_PTR;
-#endif
        int cnt = 0;
        unsigned long i;
 

diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c
index 85a48491b35b7f68b9e09ec866989dd810bf3eb7..fa78eaa7f06816373982b6577ef935a306a28e4e 100644 (file)
--- a/cpu/arm1136/cpu.c
+++ b/cpu/arm1136/cpu.c
@@ -37,6 +37,10 @@
 #include <asm/arch/omap2420.h>
 #endif
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1 (void)
 {
@@ -88,8 +92,6 @@ int cpu_init (void)
         * setup up stacks if necessary
         */
 #ifdef CONFIG_USE_IRQ
-       DECLARE_GLOBAL_DATA_PTR;
-
        IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
        FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif

diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c
index 0f9997950875551e445faacf1a49da1bcdaa410f..054bab98112f194c62da23741887e0e1b9bfd502 100644 (file)
--- a/cpu/arm720t/serial.c
+++ b/cpu/arm720t/serial.c
@@ -34,10 +34,10 @@
 
 #include <clps7111.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned int reg = 0;
 
        switch (gd->baudrate) {

diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c
index 5ad98f06fdb8c0b29bdf6d4c8fcf988aa6df94f6..bc6bf30b69e920e2aac5d47b3c8e8282efbfac42 100644 (file)
--- a/cpu/arm720t/serial_netarm.c
+++ b/cpu/arm720t/serial_netarm.c
@@ -34,6 +34,8 @@
 
 #include <asm/hardware.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PORTA  (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA))
 #if !defined(CONFIG_NETARM_NS7520)
 #define PORTB  (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB))
@@ -67,9 +69,6 @@ extern void _netarm_led_FAIL1(void);
  */
 void serial_setbrg (void)
 {
-       /* get the gd pointer */
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* set 0 ... make sure pins are configured for serial */
 #if !defined(CONFIG_NETARM_NS7520)
        PORTA = PORTB =

diff --git a/cpu/arm920t/at91rm9200/i2c.c b/cpu/arm920t/at91rm9200/i2c.c
index 2565998e484d7ed0f70a1ad2ee7ce762220990dd..826cea8e2641a7a6dc832bc955943cc403b3558f 100644 (file)
--- a/cpu/arm920t/at91rm9200/i2c.c
+++ b/cpu/arm920t/at91rm9200/i2c.c
@@ -111,7 +111,7 @@ at91_xfer(unsigned char chip, unsigned int addr, int alen,
 int
 i2c_probe(unsigned char chip)
 {
-       char buffer[1];
+       unsigned char buffer[1];
 
        return at91_xfer(chip, 0, 0, buffer, 1, 1);
 }
@@ -191,7 +191,7 @@ i2c_init(int speed, int slaveaddr)
 
 uchar i2c_reg_read(uchar i2c_addr, uchar reg)
 {
-       char buf;
+       unsigned char buf;
 
        i2c_read(i2c_addr, reg, 1, &buf, 1);
 

diff --git a/cpu/arm920t/at91rm9200/serial.c b/cpu/arm920t/at91rm9200/serial.c
index a281932b77d05500358cb20172e5539c6d88d93d..d5634454927591eb4b3e52a4d9499b8988fff7ec 100644 (file)
--- a/cpu/arm920t/at91rm9200/serial.c
+++ b/cpu/arm920t/at91rm9200/serial.c
@@ -33,6 +33,8 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
 #error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
 #endif
@@ -50,7 +52,6 @@ AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US1;
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int baudrate;
 
        if ((baudrate = gd->baudrate) <= 0)

diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c
index 2f7963dcf6640ccc275d92d9784fda91c20eed52..f93bf57e2b47fe6a79be27372e039d726e0ed5ef 100644 (file)
--- a/cpu/arm920t/cpu.c
+++ b/cpu/arm920t/cpu.c
@@ -33,6 +33,10 @@
 #include <command.h>
 #include <arm920t.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1 (void)
 {
@@ -91,8 +95,6 @@ int cpu_init (void)
         * setup up stacks if necessary
         */
 #ifdef CONFIG_USE_IRQ
-       DECLARE_GLOBAL_DATA_PTR;
-
        IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
        FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif

diff --git a/cpu/arm920t/ks8695/serial.c b/cpu/arm920t/ks8695/serial.c
index 0dd91e7dd0eed14a31cd4bfa317f1727e6f3897e..aacd1be630b1800303f1b4cae793bd0bb9b58ef8 100644 (file)
--- a/cpu/arm920t/ks8695/serial.c
+++ b/cpu/arm920t/ks8695/serial.c
@@ -25,6 +25,8 @@
 #error "Bad: you didn't configure serial ..."
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  *     Define the UART hardware register access structure.
  */
@@ -54,7 +56,6 @@ int serial_console = 1;
 
 void serial_setbrg(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
 
        /* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/

diff --git a/cpu/arm920t/s3c24x0/serial.c b/cpu/arm920t/s3c24x0/serial.c
index 83274432e4b1c72e4e553786be2328b098e94d9f..36851ad5ca86dcb95833ceb509b24d56bfebc4e5 100644 (file)
--- a/cpu/arm920t/s3c24x0/serial.c
+++ b/cpu/arm920t/s3c24x0/serial.c
@@ -27,6 +27,8 @@
 #include <s3c2410.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_SERIAL1
 #define UART_NR        S3C24X0_UART0
 
@@ -48,7 +50,6 @@
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
        int i;
        unsigned int reg = 0;

diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c
index b4cc74476b0e4999ebd06b828bfc537e0b933621..869ca79d032dcbf97e6561836306d483662d0f2e 100644 (file)
--- a/cpu/arm920t/s3c24x0/usb_ohci.c
+++ b/cpu/arm920t/s3c24x0/usb_ohci.c
@@ -1647,7 +1647,8 @@ int usb_lowlevel_init(void)
        }
 
        /* FIXME this is a second HC reset; why?? */
-       writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
+       gohci.hc_control = OHCI_USB_RESET;
+       writel (gohci.hc_control, &gohci.regs->control);
        wait_ms (10);
 
        if (hc_start (&gohci) < 0) {

diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index 4603cf573376fdfaa5b7b88933c6b1190591976a..346f0d09ea77a18b2c9a7b2a3d08a078a9aa4741 100644 (file)
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -237,6 +237,7 @@ _start_armboot:     .word start_armboot
  */
 
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
        /*
         * flush v4 I/D caches
@@ -264,7 +265,7 @@ cpu_init_crit:
        bl      lowlevel_init
        mov     lr, ip
        mov     pc, lr
-
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 
 /*
  *************************************************************************

diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c
index c1c6b03e4245dfe872b024cf82487435fbd7fcab..d85b7fad39ed378cb73fc71edfe90d7eab282af6 100644 (file)
--- a/cpu/arm925t/cpu.c
+++ b/cpu/arm925t/cpu.c
@@ -33,6 +33,10 @@
 #include <command.h>
 #include <arm925t.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1 (void)
 {
@@ -91,8 +95,6 @@ int cpu_init (void)
         * setup up stacks if necessary
         */
 #ifdef CONFIG_USE_IRQ
-       DECLARE_GLOBAL_DATA_PTR;
-
        IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
        FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif

diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index f57c5a5d89513098a39a86044cf2ab987388bbae..722732e589b4d225a3e38aaae3514de4aec3753e 100644 (file)
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -33,6 +33,10 @@
 #include <command.h>
 #include <arm926ejs.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1 (void)
 {
@@ -91,8 +95,6 @@ int cpu_init (void)
         * setup up stacks if necessary
         */
 #ifdef CONFIG_USE_IRQ
-       DECLARE_GLOBAL_DATA_PTR;
-
        IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
        FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif

diff --git a/cpu/arm926ejs/interrupts.c b/cpu/arm926ejs/interrupts.c
index 0457bff96457e24836b1aeb6acd871348cf555fc..9cac969f64abd775e359b94dfb73ac4528469b35 100644 (file)
--- a/cpu/arm926ejs/interrupts.c
+++ b/cpu/arm926ejs/interrupts.c
@@ -39,16 +39,6 @@
 #include <arm926ejs.h>
 #include <asm/proc-armv/ptrace.h>
 
-#define TIMER_LOAD_VAL 0xffffffff
-
-/* macro to read the 32 bit timer */
-#ifdef CONFIG_OMAP
-#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
-#endif
-#ifdef CONFIG_VERSATILE
-#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
-#endif
-
 #ifdef CONFIG_USE_IRQ
 /* enable IRQ interrupts */
 void enable_interrupts (void)
@@ -188,146 +178,14 @@ void do_irq (struct pt_regs *pt_regs)
 
 #else
 
-static ulong timestamp;
-static ulong lastdec;
-
 /* nothing really to do with interrupts, just starts up a counter. */
 int interrupt_init (void)
 {
-#ifdef CONFIG_OMAP
-       int32_t val;
-
-       /* Start the decrementer ticking down from 0xffffffff */
-       *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
-       val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
-       *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
-#endif /* CONFIG_OMAP */
-
-#ifdef CONFIG_VERSATILE
-       *(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD;      /* TimerLoad */
-       *(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD;      /* TimerValue */
-       *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C;
-#endif /* CONFIG_VERSATILE */
-
-       /* init the timestamp and lastdec value */
-       reset_timer_masked();
-
-       return (0);
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-       reset_timer_masked ();
-}
+       extern void timer_init(void);
 
-ulong get_timer (ulong base)
-{
-       return get_timer_masked () - base;
-}
+       timer_init();
 
-void set_timer (ulong t)
-{
-       timestamp = t;
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-void udelay (unsigned long usec)
-{
-       ulong tmo, tmp;
-
-       if(usec >= 1000){               /* if "big" number, spread normalization to seconds */
-               tmo = usec / 1000;      /* start to normalize for usec to ticks per sec */
-               tmo *= CFG_HZ;          /* find number of "ticks" to wait to achieve target */
-               tmo /= 1000;            /* finish normalize. */
-       }else{                          /* else small number, don't kill it prior to HZ multiply */
-               tmo = usec * CFG_HZ;
-               tmo /= (1000*1000);
-       }
-
-       tmp = get_timer (0);            /* get current timestamp */
-       if( (tmo + tmp + 1) < tmp )     /* if setting this fordward will roll time stamp */
-               reset_timer_masked ();  /* reset "advancing" timestamp to 0, set lastdec value */
-       else
-               tmo += tmp;             /* else, set advancing stamp wake up time */
-
-       while (get_timer_masked () < tmo)/* loop till event */
-               /*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
-       /* reset time */
-       lastdec = READ_TIMER;  /* capure current decrementer value time */
-       timestamp = 0;         /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked (void)
-{
-       ulong now = READ_TIMER;         /* current tick value */
-
-       if (lastdec >= now) {           /* normal mode (non roll) */
-               /* normal mode */
-               timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
-       } else {                        /* we have overflow of the count down timer */
-               /* nts = ts + ld + (TLV - now)
-                * ts=old stamp, ld=time that passed before passing through -1
-                * (TLV-now) amount of time after passing though -1
-                * nts = new "advancing time stamp"...it could also roll and cause problems.
-                */
-               timestamp += lastdec + TIMER_LOAD_VAL - now;
-       }
-       lastdec = now;
-
-       return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
-       ulong tmo;
-       ulong endtime;
-       signed long diff;
-
-       if (usec >= 1000) {             /* if "big" number, spread normalization to seconds */
-               tmo = usec / 1000;      /* start to normalize for usec to ticks per sec */
-               tmo *= CFG_HZ;          /* find number of "ticks" to wait to achieve target */
-               tmo /= 1000;            /* finish normalize. */
-       } else {                        /* else small number, don't kill it prior to HZ multiply */
-               tmo = usec * CFG_HZ;
-               tmo /= (1000*1000);
-       }
-
-       endtime = get_timer_masked () + tmo;
-
-       do {
-               ulong now = get_timer_masked ();
-               diff = endtime - now;
-       } while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-       return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-       ulong tbclk;
-
-       tbclk = CFG_HZ;
-       return tbclk;
+       return 0;
 }
 
 #endif /* CONFIG_INTEGRATOR */

diff --git a/cpu/arm926ejs/omap/Makefile b/cpu/arm926ejs/omap/Makefile
new file mode 100644 (file)
index 0000000..f9d3378
--- /dev/null
+++ b/cpu/arm926ejs/omap/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(SOC).a
+
+OBJS   = timer.o
+SOBJS  = reset.o
+
+all:   .depend $(LIB)
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:       Makefile $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

diff --git a/cpu/arm926ejs/omap/reset.S b/cpu/arm926ejs/omap/reset.S
new file mode 100644 (file)
index 0000000..e898902
--- /dev/null
+++ b/cpu/arm926ejs/omap/reset.S
@@ -0,0 +1,45 @@
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
+ *  Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+       .align  5
+.globl reset_cpu
+reset_cpu:
+       ldr     r1, rstctl1     /* get clkm1 reset ctl */
+       mov     r3, #0x0
+       strh    r3, [r1]        /* clear it */
+       mov     r3, #0x8
+       strh    r3, [r1]        /* force dsp+arm reset */
+_loop_forever:
+       b       _loop_forever
+
+rstctl1:
+       .word   0xfffece10

diff --git a/cpu/arm926ejs/omap/timer.c b/cpu/arm926ejs/omap/timer.c
new file mode 100644 (file)
index 0000000..a2a9133
--- /dev/null
+++ b/cpu/arm926ejs/omap/timer.c
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <arm926ejs.h>
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init (void)
+{
+       int32_t val;
+
+       /* Start the decrementer ticking down from 0xffffffff */
+       *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
+       val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
+       *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
+
+       /* init the timestamp and lastdec value */
+       reset_timer_masked();
+
+       return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+       reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+       return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+       timestamp = t;
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay (unsigned long usec)
+{
+       ulong tmo, tmp;
+
+       if(usec >= 1000){               /* if "big" number, spread normalization to seconds */
+               tmo = usec / 1000;      /* start to normalize for usec to ticks per sec */
+               tmo *= CFG_HZ;          /* find number of "ticks" to wait to achieve target */
+               tmo /= 1000;            /* finish normalize. */
+       }else{                          /* else small number, don't kill it prior to HZ multiply */
+               tmo = usec * CFG_HZ;
+               tmo /= (1000*1000);
+       }
+
+       tmp = get_timer (0);            /* get current timestamp */
+       if( (tmo + tmp + 1) < tmp )     /* if setting this fordward will roll time stamp */
+               reset_timer_masked ();  /* reset "advancing" timestamp to 0, set lastdec value */
+       else
+               tmo += tmp;             /* else, set advancing stamp wake up time */
+
+       while (get_timer_masked () < tmo)/* loop till event */
+               /*NOP*/;
+}
+
+void reset_timer_masked (void)
+{
+       /* reset time */
+       lastdec = READ_TIMER;  /* capure current decrementer value time */
+       timestamp = 0;         /* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked (void)
+{
+       ulong now = READ_TIMER;         /* current tick value */
+
+       if (lastdec >= now) {           /* normal mode (non roll) */
+               /* normal mode */
+               timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
+       } else {                        /* we have overflow of the count down timer */
+               /* nts = ts + ld + (TLV - now)
+                * ts=old stamp, ld=time that passed before passing through -1
+                * (TLV-now) amount of time after passing though -1
+                * nts = new "advancing time stamp"...it could also roll and cause problems.
+                */
+               timestamp += lastdec + TIMER_LOAD_VAL - now;
+       }
+       lastdec = now;
+
+       return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+       ulong tmo;
+       ulong endtime;
+       signed long diff;
+
+       if (usec >= 1000) {             /* if "big" number, spread normalization to seconds */
+               tmo = usec / 1000;      /* start to normalize for usec to ticks per sec */
+               tmo *= CFG_HZ;          /* find number of "ticks" to wait to achieve target */
+               tmo /= 1000;            /* finish normalize. */
+       } else {                        /* else small number, don't kill it prior to HZ multiply */
+               tmo = usec * CFG_HZ;
+               tmo /= (1000*1000);
+       }
+
+       endtime = get_timer_masked () + tmo;
+
+       do {
+               ulong now = get_timer_masked ();
+               diff = endtime - now;
+       } while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+       return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+       ulong tbclk;
+
+       tbclk = CFG_HZ;
+       return tbclk;
+}

diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S
index fc6b20b21e3f1c4d8a631238ea6883e3c8578438..725c6639a1e506054d74a7642291d5c058b5277f 100644 (file)
--- a/cpu/arm926ejs/start.S
+++ b/cpu/arm926ejs/start.S
@@ -392,25 +392,3 @@ fiq:
        bl      do_fiq
 
 #endif
-
-# ifdef CONFIG_INTEGRATOR
-
-       /* Satisfied by Integrator routine (AP or CP) */
-
-#else
-
-       .align  5
-.globl reset_cpu
-reset_cpu:
-       ldr     r1, rstctl1     /* get clkm1 reset ctl */
-       mov     r3, #0x0
-       strh    r3, [r1]        /* clear it */
-       mov     r3, #0x8
-       strh    r3, [r1]        /* force dsp+arm reset */
-_loop_forever:
-       b       _loop_forever
-
-rstctl1:
-       .word   0xfffece10
-
-#endif /* #ifdef CONFIG_INTEGRATOR */

diff --git a/cpu/arm926ejs/versatile/Makefile b/cpu/arm926ejs/versatile/Makefile
new file mode 100644 (file)
index 0000000..f9d3378
--- /dev/null
+++ b/cpu/arm926ejs/versatile/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(SOC).a
+
+OBJS   = timer.o
+SOBJS  = reset.o
+
+all:   .depend $(LIB)
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:       Makefile $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

diff --git a/cpu/arm926ejs/versatile/reset.S b/cpu/arm926ejs/versatile/reset.S
new file mode 100644 (file)
index 0000000..e898902
--- /dev/null
+++ b/cpu/arm926ejs/versatile/reset.S
@@ -0,0 +1,45 @@
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
+ *  Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+       .align  5
+.globl reset_cpu
+reset_cpu:
+       ldr     r1, rstctl1     /* get clkm1 reset ctl */
+       mov     r3, #0x0
+       strh    r3, [r1]        /* clear it */
+       mov     r3, #0x8
+       strh    r3, [r1]        /* force dsp+arm reset */
+_loop_forever:
+       b       _loop_forever
+
+rstctl1:
+       .word   0xfffece10

diff --git a/cpu/arm926ejs/versatile/timer.c b/cpu/arm926ejs/versatile/timer.c
new file mode 100644 (file)
index 0000000..32872d2
--- /dev/null
+++ b/cpu/arm926ejs/versatile/timer.c
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <arm926ejs.h>
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
+
+static ulong timestamp;
+static ulong lastdec;
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int timer_init (void)
+{
+       *(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD;      /* TimerLoad */
+       *(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD;      /* TimerValue */
+       *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C;
+
+       /* init the timestamp and lastdec value */
+       reset_timer_masked();
+
+       return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+       reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+       return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+       timestamp = t;
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay (unsigned long usec)
+{
+       ulong tmo, tmp;
+
+       if(usec >= 1000){               /* if "big" number, spread normalization to seconds */
+               tmo = usec / 1000;      /* start to normalize for usec to ticks per sec */
+               tmo *= CFG_HZ;          /* find number of "ticks" to wait to achieve target */
+               tmo /= 1000;            /* finish normalize. */
+       }else{                          /* else small number, don't kill it prior to HZ multiply */
+               tmo = usec * CFG_HZ;
+               tmo /= (1000*1000);
+       }
+
+       tmp = get_timer (0);            /* get current timestamp */
+       if( (tmo + tmp + 1) < tmp )     /* if setting this fordward will roll time stamp */
+               reset_timer_masked ();  /* reset "advancing" timestamp to 0, set lastdec value */
+       else
+               tmo += tmp;             /* else, set advancing stamp wake up time */
+
+       while (get_timer_masked () < tmo)/* loop till event */
+               /*NOP*/;
+}
+
+void reset_timer_masked (void)
+{
+       /* reset time */
+       lastdec = READ_TIMER;  /* capure current decrementer value time */
+       timestamp = 0;         /* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked (void)
+{
+       ulong now = READ_TIMER;         /* current tick value */
+
+       if (lastdec >= now) {           /* normal mode (non roll) */
+               /* normal mode */
+               timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
+       } else {                        /* we have overflow of the count down timer */
+               /* nts = ts + ld + (TLV - now)
+                * ts=old stamp, ld=time that passed before passing through -1
+                * (TLV-now) amount of time after passing though -1
+                * nts = new "advancing time stamp"...it could also roll and cause problems.
+                */
+               timestamp += lastdec + TIMER_LOAD_VAL - now;
+       }
+       lastdec = now;
+
+       return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+       ulong tmo;
+       ulong endtime;
+       signed long diff;
+
+       if (usec >= 1000) {             /* if "big" number, spread normalization to seconds */
+               tmo = usec / 1000;      /* start to normalize for usec to ticks per sec */
+               tmo *= CFG_HZ;          /* find number of "ticks" to wait to achieve target */
+               tmo /= 1000;            /* finish normalize. */
+       } else {                        /* else small number, don't kill it prior to HZ multiply */
+               tmo = usec * CFG_HZ;
+               tmo /= (1000*1000);
+       }
+
+       endtime = get_timer_masked () + tmo;
+
+       do {
+               ulong now = get_timer_masked ();
+               diff = endtime - now;
+       } while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+       return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+       ulong tbclk;
+
+       tbclk = CFG_HZ;
+       return tbclk;
+}

diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c
index ba0a4e496e2e194c1b43d7b83ac0982416f2393f..4c63a8dd87fefd0d77edc50f460a550d43bc0d0f 100644 (file)
--- a/cpu/arm946es/cpu.c
+++ b/cpu/arm946es/cpu.c
@@ -33,6 +33,10 @@
 #include <command.h>
 #include <arm946es.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1 (void)
 {
@@ -91,8 +95,6 @@ int cpu_init (void)
         * setup up stacks if necessary
         */
 #ifdef CONFIG_USE_IRQ
-       DECLARE_GLOBAL_DATA_PTR;
-
        IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
        FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif

diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c
index d03b09dad81fb0f57ec0b3cf66a9661794cd8001..e2309f8898babbf28d874e0acf4f0ff65f8bd0af 100644 (file)
--- a/cpu/arm_intcm/cpu.c
+++ b/cpu/arm_intcm/cpu.c
@@ -33,14 +33,16 @@
 #include <common.h>
 #include <command.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 int cpu_init (void)
 {
        /*
         * setup up stacks if necessary
         */
 #ifdef CONFIG_USE_IRQ
-       DECLARE_GLOBAL_DATA_PTR;
-
        IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
        FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif

diff --git a/cpu/bf533/Makefile b/cpu/bf533/Makefile
new file mode 100644 (file)
index 0000000..c63a8f6
--- /dev/null
+++ b/cpu/bf533/Makefile
@@ -0,0 +1,46 @@
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(CPU).a
+
+START  = start.o start1.o interrupt.o cache.o cplbhdlr.o cplbmgr.o flush.o
+OBJS   = cpu.o traps.o ints.o serial.o interrupts.o
+
+all:   .depend $(START) $(LIB)
+
+$(LIB):        $(OBJS)
+       $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:       Makefile $(START:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h
new file mode 100644 (file)
index 0000000..d430e6c
--- /dev/null
+++ b/cpu/bf533/bf533_serial.h
@@ -0,0 +1,78 @@
+/*
+ * U-boot - bf533_serial.h Serial Driver defines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
+ * Copyright (C) 2003  Bas Vermeulen <bas@buyways.nl>
+ *                     BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on:
+ * blkfinserial.h: Definitions for the BlackFin DSP serial driver.
+ *
+ * Copyright (C) 2001  Tony Z. Kou     tonyko@arcturusnetworks.com
+ * Copyright (C) 2001   Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328serial.c which was:
+ * Copyright (C) 1995       David S. Miller    <davem@caip.rutgers.edu>
+ * Copyright (C) 1998       Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne     <jeff@uclinux.org>
+ * Copyright (C) 1999       Vladimir Gurevich  <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _Bf533_SERIAL_H
+#define _Bf533_SERIAL_H
+
+#include <linux/config.h>
+#include <asm/blackfin.h>
+
+#define SYNC_ALL       __asm__ __volatile__ ("ssync;\n")
+#define ACCESS_LATCH   *pUART_LCR |= UART_LCR_DLAB;
+#define ACCESS_PORT_IER        *pUART_LCR &= (~UART_LCR_DLAB);
+
+void serial_setbrg(void);
+static void local_put_char(char ch);
+void calc_baud(void);
+void serial_setbrg(void);
+int serial_init(void);
+void serial_putc(const char c);
+int serial_tstc(void);
+int serial_getc(void);
+void serial_puts(const char *s);
+static void local_put_char(char ch);
+
+extern int get_clock(void);
+int baud_table[5] = {9600, 19200, 38400, 57600, 115200};
+
+struct {
+       unsigned char dl_high;
+       unsigned char dl_low;
+} hw_baud_table[5];
+
+#ifdef CONFIG_STAMP
+extern unsigned long pll_div_fact;
+#endif
+
+#endif

diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S
new file mode 100644 (file)
index 0000000..8fac402
--- /dev/null
+++ b/cpu/bf533/cache.S
@@ -0,0 +1,125 @@
+
+
+#define ASSEMBLY
+#include <asm/linkage.h>
+#include <asm/cpu/def_LPBlackfin.h>
+
+.text
+.align 2
+ENTRY(blackfin_icache_flush_range)
+       R2 = -32;
+       R2 = R0 & R2;
+       P0 = R2;
+       P1 = R1;
+       CSYNC;
+1:
+       IFLUSH[P0++];
+       CC = P0 < P1(iu);
+       IF CC JUMP 1b(bp);
+       IFLUSH[P0];
+       SSYNC;
+       RTS;
+
+ENTRY(blackfin_dcache_flush_range)
+       R2 = -32;
+       R2 = R0 & R2;
+       P0 = R2;
+       P1 = R1;
+       CSYNC;
+1:
+       FLUSH[P0++];
+       CC = P0 < P1(iu);
+       IF CC JUMP 1b(bp);
+       FLUSH[P0];
+       SSYNC;
+       RTS;
+
+ENTRY(_icache_invalidate)
+ENTRY(invalidate_entire_icache)
+       [--SP] = ( R7:5);
+
+       P0.L = (IMEM_CONTROL & 0xFFFF);
+       P0.H = (IMEM_CONTROL >> 16);
+       R7 = [P0];
+
+       /* Clear the IMC bit , All valid bits in the instruction
+        * cache are set to the invalid state
+        */
+       BITCLR(R7,IMC_P);
+       CLI R6;
+       SSYNC;          /* SSYNC required before invalidating cache. */
+       .align 8;
+       [P0] = R7;
+       SSYNC;
+       STI R6;
+
+       /* Configures the instruction cache agian */
+       R6 = (IMC | ENICPLB);
+       R7 = R7 | R6;
+
+       CLI R6;
+       SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
+       .align 8;
+       [P0] = R7;
+       SSYNC;
+       STI R6;
+
+       ( R7:5) = [SP++];
+       RTS;
+
+/* Invalidate the Entire Data cache by
+ * clearing DMC[1:0] bits
+ */
+ENTRY(invalidate_entire_dcache)
+ENTRY(_dcache_invalidate)
+       [--SP] = ( R7:6);
+
+       P0.L = (DMEM_CONTROL & 0xFFFF);
+       P0.H = (DMEM_CONTROL >> 16);
+       R7 = [P0];
+
+       /* Clear the DMC[1:0] bits, All valid bits in the data
+        * cache are set to the invalid state
+        */
+       BITCLR(R7,DMC0_P);
+       BITCLR(R7,DMC1_P);
+       CLI R6;
+       SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
+       .align 8;
+       [P0] = R7;
+       SSYNC;
+       STI R6;
+
+       /* Configures the data cache again */
+
+       R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+       R7 = R7 | R6;
+
+       CLI R6;
+       SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
+       .align 8;
+       [P0] = R7;
+       SSYNC;
+       STI R6;
+
+       ( R7:6) = [SP++];
+       RTS;
+
+ENTRY(blackfin_dcache_invalidate_range)
+       R2 = -32;
+       R2 = R0 & R2;
+       P0 = R2;
+       P1 = R1;
+       CSYNC;
+1:
+       FLUSHINV[P0++];
+       CC = P0 < P1 (iu);
+       IF CC JUMP 1b (bp);
+
+       /* If the data crosses a cache line, then we'll be pointing to
+       ** the last cache line, but won't have flushed/invalidated it yet, so do
+       ** one more.
+       */
+       FLUSHINV[P0];
+       SSYNC;
+       RTS;

diff --git a/cpu/bf533/config.mk b/cpu/bf533/config.mk
new file mode 100644 (file)
index 0000000..a9d529e
--- /dev/null
+++ b/cpu/bf533/config.mk
@@ -0,0 +1,27 @@
+# U-boot - config.mk
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -ffixed-P5

diff --git a/cpu/bf533/cplbhdlr.S b/cpu/bf533/cplbhdlr.S
new file mode 100644 (file)
index 0000000..61be5bb
--- /dev/null
+++ b/cpu/bf533/cplbhdlr.S
@@ -0,0 +1,193 @@
+/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ */
+
+
+/* Include an exception handler to invoke the CPLB manager
+ */
+
+#include <asm-blackfin/linkage.h>
+#include <asm/cplb.h>
+#include <asm/entry.h>
+
+
+.text
+
+.globl _cplb_hdr;
+.type _cplb_hdr, STT_FUNC;
+.extern _cplb_mgr;
+.type _cplb_mgr, STT_FUNC;
+.extern __unknown_exception_occurred;
+.type __unknown_exception_occurred, STT_FUNC;
+.extern __cplb_miss_all_locked;
+.type __cplb_miss_all_locked, STT_FUNC;
+.extern __cplb_miss_without_replacement;
+.type __cplb_miss_without_replacement, STT_FUNC;
+.extern __cplb_protection_violation;
+.type __cplb_protection_violation, STT_FUNC;
+.extern panic_pv;
+
+.align 2;
+
+ENTRY(_cplb_hdr)
+       SSYNC;
+       [--SP] = ( R7:0, P5:0 );
+       [--SP] = ASTAT;
+       [--SP] = SEQSTAT;
+       [--SP] = I0;
+       [--SP] = I1;
+       [--SP] = I2;
+       [--SP] = I3;
+       [--SP] = LT0;
+       [--SP] = LB0;
+       [--SP] = LC0;
+       [--SP] = LT1;
+       [--SP] = LB1;
+       [--SP] = LC1;
+       R2 = SEQSTAT;
+
+       /*Mask the contents of SEQSTAT and leave only EXCAUSE in R2*/
+       R2 <<= 26;
+       R2 >>= 26;
+
+       R1 = 0x23; /* Data access CPLB protection violation */
+       CC = R2 == R1;
+       IF !CC JUMP not_data_write;
+       R0 = 2;         /* is a write to data space*/
+       JUMP is_icplb_miss;
+
+not_data_write:
+       R1 = 0x2C; /* CPLB miss on an instruction fetch */
+       CC = R2 == R1;
+       R0 = 0;         /* is_data_miss == False*/
+       IF CC JUMP is_icplb_miss;
+
+       R1 = 0x26;
+       CC = R2 == R1;
+       IF !CC JUMP unknown;
+
+       R0 = 1;         /* is_data_miss == True*/
+
+is_icplb_miss:
+
+#if ( defined (CONFIG_BLKFIN_CACHE) || defined (CONFIG_BLKFIN_DCACHE))
+#if ( defined (CONFIG_BLKFIN_CACHE) && !defined (CONFIG_BLKFIN_DCACHE))
+       R1 = CPLB_ENABLE_ICACHE;
+#endif
+#if ( !defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
+       R1 = CPLB_ENABLE_DCACHE;
+#endif
+#if ( defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
+       R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE;
+#endif
+#else
+       R1 = 0;
+#endif
+
+       [--SP] = RETS;
+       CALL _cplb_mgr;
+       RETS = [SP++];
+       CC = R0 == 0;
+       IF !CC JUMP not_replaced;
+       LC1 = [SP++];
+       LB1 = [SP++];
+       LT1 = [SP++];
+       LC0 = [SP++];
+       LB0 = [SP++];
+       LT0 = [SP++];
+       I3 = [SP++];
+       I2 = [SP++];
+       I1 = [SP++];
+       I0 = [SP++];
+       SEQSTAT = [SP++];
+       ASTAT = [SP++];
+       ( R7:0, P5:0 ) = [SP++];
+       RTS;
+
+unknown:
+       [--SP] = RETS;
+       CALL __unknown_exception_occurred;
+       RETS = [SP++];
+       JUMP unknown;
+not_replaced:
+       CC = R0 == CPLB_NO_UNLOCKED;
+       IF !CC JUMP next_check;
+       [--SP] = RETS;
+       CALL __cplb_miss_all_locked;
+       RETS = [SP++];
+next_check:
+       CC = R0 == CPLB_NO_ADDR_MATCH;
+       IF !CC JUMP next_check2;
+       [--SP] = RETS;
+       CALL __cplb_miss_without_replacement;
+       RETS = [SP++];
+       JUMP not_replaced;
+next_check2:
+       CC = R0 == CPLB_PROT_VIOL;
+       IF !CC JUMP strange_return_from_cplb_mgr;
+       [--SP] = RETS;
+       CALL __cplb_protection_violation;
+       RETS = [SP++];
+       JUMP not_replaced;
+strange_return_from_cplb_mgr:
+       IDLE;
+       CSYNC;
+       JUMP strange_return_from_cplb_mgr;
+
+/************************************
+ * Diagnostic exception handlers
+ */
+
+__cplb_miss_all_locked:
+       sp += -12;
+       R0 = CPLB_NO_UNLOCKED;
+       call panic_bfin;
+       SP += 12;
+       RTS;
+
+ __cplb_miss_without_replacement:
+       sp += -12;
+       R0 = CPLB_NO_ADDR_MATCH;
+       call panic_bfin;
+       SP += 12;
+       RTS;
+
+__cplb_protection_violation:
+       sp += -12;
+       R0 = CPLB_PROT_VIOL;
+       call panic_bfin;
+       SP += 12;
+       RTS;
+
+__unknown_exception_occurred:
+
+       /* This function is invoked by the default exception
+        * handler, if it does not recognise the kind of
+        * exception that has occurred. In other words, the
+        * default handler only handles some of the system's
+        * exception types, and it does not expect any others
+        * to occur. If your application is going to be using
+        * other kinds of exceptions, you must replace the
+        * default handler with your own, that handles all the
+        * exceptions you will use.
+        *
+        * Since there's nothing we can do, we just loop here
+        * at what we hope is a suitably informative label.
+        */
+
+       IDLE;
+do_not_know_what_to_do:
+       CSYNC;
+       JUMP __unknown_exception_occurred;
+
+       RTS;
+.__unknown_exception_occurred.end:
+.global __unknown_exception_occurred;
+.type __unknown_exception_occurred, STT_FUNC;
+
+panic_bfin:
+       RTS;

diff --git a/cpu/bf533/cplbmgr.S b/cpu/bf533/cplbmgr.S
new file mode 100644 (file)
index 0000000..7a0b048
--- /dev/null
+++ b/cpu/bf533/cplbmgr.S
@@ -0,0 +1,601 @@
+/*This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ * Modification: Dec 07 2004
+ *     1. Correction in icheck_lock.  Valid lock entries were
+ *        geting victimized, for instruction cplb replacement.
+ *     2. Setup loop's are modified as now toolchain support's P Indexed
+ *        addressing
+ *        :LG Soft India
+ *
+ */
+
+/* Usage: int _cplb_mgr(is_data_miss,int enable_cache)
+ * is_data_miss==2 => Mark as Dirty, write to the clean data page
+ * is_data_miss==1 => Replace a data CPLB.
+ * is_data_miss==0 => Replace an instruction CPLB.
+ *
+ * Returns:
+ * CPLB_RELOADED       => Successfully updated CPLB table.
+ * CPLB_NO_UNLOCKED    => All CPLBs are locked, so cannot be evicted.This indicates
+ *                             that the CPLBs in the configuration tablei are badly
+ *                             configured, as this should never occur.
+ * CPLB_NO_ADDR_MATCH  => The address being accessed, that triggered the exception,
+ *                             is not covered by any of the CPLBs in the configuration
+ *                             table. The application isi presumably misbehaving.
+ * CPLB_PROT_VIOL      => The address being accessed, that triggered thei exception,
+ *                             was not a first-write to a clean Write Back Data page,
+ *                             and so presumably is a genuine violation of the page's
+ *                             protection attributes. The application is misbehaving.
+ */
+#define ASSEMBLY
+
+#include <asm-blackfin/linkage.h>
+#include <asm-blackfin/blackfin.h>
+#include <asm-blackfin/cplbtab.h>
+#include <asm-blackfin/cplb.h>
+
+.text
+
+.align 2;
+ENTRY(_cplb_mgr)
+
+       [--SP]=( R7:0,P5:0 );
+
+       CC = R0 == 2;
+       IF CC JUMP dcplb_write;
+
+       CC = R0 == 0;
+       IF !CC JUMP dcplb_miss_compare;
+
+       /* ICPLB Miss Exception. We need to choose one of the
+       * currently-installed CPLBs, and replace it with one
+       * from the configuration table.
+       */
+
+       P4.L = (ICPLB_FAULT_ADDR & 0xFFFF);
+       P4.H = (ICPLB_FAULT_ADDR >> 16);
+
+       P1 = 16;
+       P5.L = page_size_table;
+       P5.H = page_size_table;
+
+       P0.L = (ICPLB_DATA0 & 0xFFFF);
+       P0.H = (ICPLB_DATA0 >> 16);
+       R4 = [P4];              /* Get faulting address*/
+       R6 = 64;                /* Advance past the fault address, which*/
+       R6 = R6 + R4;           /* we'll use if we find a match*/
+       R3 = ((16 << 8) | 2);   /* Extract mask, bits 16 and 17.*/
+
+       R5 = 0;
+isearch:
+
+       R1 = [P0-0x100];        /* Address for this CPLB */
+
+       R0 = [P0++];            /* Info for this CPLB*/
+       CC = BITTST(R0,0);      /* Is the CPLB valid?*/
+       IF !CC JUMP nomatch;    /* Skip it, if not.*/
+       CC = R4 < R1(IU);       /* If fault address less than page start*/
+       IF CC JUMP nomatch;     /* then skip this one.*/
+       R2 = EXTRACT(R0,R3.L) (Z);      /* Get page size*/
+       P1 = R2;
+       P1 = P5 + (P1<<2);      /* index into page-size table*/
+       R2 = [P1];              /* Get the page size*/
+       R1 = R1 + R2;           /* and add to page start, to get page end*/
+       CC = R4 < R1(IU);       /* and see whether fault addr is in page.*/
+       IF !CC R4 = R6;         /* If so, advance the address and finish loop.*/
+       IF !CC JUMP isearch_done;
+nomatch:
+       /* Go around again*/
+       R5 += 1;
+       CC = BITTST(R5, 4);     /* i.e CC = R5 >= 16*/
+       IF !CC JUMP isearch;
+
+isearch_done:
+       I0 = R4;                /* Fault address we'll search for*/
+
+       /* set up pointers */
+       P0.L = (ICPLB_DATA0 & 0xFFFF);
+       P0.H = (ICPLB_DATA0 >> 16);
+
+       /* The replacement procedure for ICPLBs */
+
+       P4.L = (IMEM_CONTROL & 0xFFFF);
+       P4.H = (IMEM_CONTROL >> 16);
+
+       /* disable cplbs */
+       R5 = [P4];              /* Control Register*/
+       BITCLR(R5,ENICPLB_P);
+       CLI R1;
+       SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
+       .align 8;
+       [P4] = R5;
+       SSYNC;
+       STI R1;
+
+       R1 = -1;                /* end point comparison */
+       R3 = 16;                /* counter */
+
+       /* Search through CPLBs for first non-locked entry */
+       /* Overwrite it by moving everyone else up by 1 */
+icheck_lock:
+       R0 = [P0++];
+       R3 = R3 + R1;
+       CC = R3 == R1;
+       IF CC JUMP all_locked;
+       CC = BITTST(R0, 0);             /* an invalid entry is good */
+       IF !CC JUMP ifound_victim;
+       CC = BITTST(R0,1);              /* but a locked entry isn't */
+       IF CC JUMP icheck_lock;
+
+ifound_victim:
+#ifdef CONFIG_CPLB_INFO
+       R7 = [P0 - 0x104];
+       P2.L = ipdt_table;
+       P2.H = ipdt_table;
+       P3.L = ipdt_swapcount_table;
+       P3.H = ipdt_swapcount_table;
+       P3 += -4;
+icount:
+       R2 = [P2];      /* address from config table */
+       P2 += 8;
+       P3 += 8;
+       CC = R2==-1;
+       IF CC JUMP icount_done;
+       CC = R7==R2;
+       IF !CC JUMP icount;
+       R7 = [P3];
+       R7 += 1;
+       [P3] = R7;
+       CSYNC;
+icount_done:
+#endif
+       LC0=R3;
+       LSETUP(is_move,ie_move) LC0;
+is_move:
+       R0 = [P0];
+       [P0 - 4] = R0;
+       R0 = [P0 - 0x100];
+       [P0-0x104] = R0;
+ie_move:P0+=4;
+
+       /* We've made space in the ICPLB table, so that ICPLB15
+        * is now free to be overwritten. Next, we have to determine
+        * which CPLB we need to install, from the configuration
+        * table. This is a matter of getting the start-of-page
+        * addresses and page-lengths from the config table, and
+        * determining whether the fault address falls within that
+        * range.
+        */
+
+       P2.L = ipdt_table;
+       P2.H = ipdt_table;
+#ifdef CONFIG_CPLB_INFO
+       P3.L = ipdt_swapcount_table;
+       P3.H = ipdt_swapcount_table;
+       P3 += -8;
+#endif
+       P0.L = page_size_table;
+       P0.H = page_size_table;
+
+       /* Retrieve our fault address (which may have been advanced
+        * because the faulting instruction crossed a page boundary).
+        */
+
+       R0 = I0;
+
+       /* An extraction pattern, to get the page-size bits from
+        * the CPLB data entry. Bits 16-17, so two bits at posn 16.
+        */
+
+       R1 = ((16<<8)|2);
+inext: R4 = [P2++];    /* address from config table */
+       R2 = [P2++];    /* data from config table */
+#ifdef CONFIG_CPLB_INFO
+       P3 += 8;
+#endif
+
+       CC = R4 == -1;  /* End of config table*/
+       IF CC JUMP no_page_in_table;
+
+       /* See if failed address > start address */
+       CC = R4 <= R0(IU);
+       IF !CC JUMP inext;
+
+       /* extract page size (17:16)*/
+       R3 = EXTRACT(R2, R1.L) (Z);
+
+       /* add page size to addr to get range */
+
+       P5 = R3;
+       P5 = P0 + (P5 << 2);    /* scaled, for int access*/
+       R3 = [P5];
+       R3 = R3 + R4;
+
+       /* See if failed address < (start address + page size) */
+       CC = R0 < R3(IU);
+       IF !CC JUMP inext;
+
+       /* We've found a CPLB in the config table that covers
+        * the faulting address, so install this CPLB into the
+        * last entry of the table.
+        */
+
+       P1.L = (ICPLB_DATA15 & 0xFFFF);         /*ICPLB_DATA15*/
+       P1.H = (ICPLB_DATA15 >> 16);
+       [P1] = R2;
+       [P1-0x100] = R4;
+#ifdef CONFIG_CPLB_INFO
+       R3 = [P3];
+       R3 += 1;
+       [P3] = R3;
+#endif
+
+       /* P4 points to IMEM_CONTROL, and R5 contains its old
+        * value, after we disabled ICPLBS. Re-enable them.
+        */
+
+       BITSET(R5,ENICPLB_P);
+       CLI R2;
+       SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
+       .align 8;
+       [P4] = R5;
+       SSYNC;
+       STI R2;
+
+       ( R7:0,P5:0 ) = [SP++];
+       R0 = CPLB_RELOADED;
+       RTS;
+
+/* FAILED CASES*/
+no_page_in_table:
+       ( R7:0,P5:0 ) = [SP++];
+       R0 = CPLB_NO_ADDR_MATCH;
+       RTS;
+all_locked:
+       ( R7:0,P5:0 ) = [SP++];
+       R0 = CPLB_NO_UNLOCKED;
+       RTS;
+prot_violation:
+       ( R7:0,P5:0 ) = [SP++];
+       R0 = CPLB_PROT_VIOL;
+       RTS;
+
+dcplb_write:
+
+       /* if a DCPLB is marked as write-back (CPLB_WT==0), and
+        * it is clean (CPLB_DIRTY==0), then a write to the
+        * CPLB's page triggers a protection violation. We have to
+        * mark the CPLB as dirty, to indicate that there are
+        * pending writes associated with the CPLB.
+        */
+
+       P4.L = (DCPLB_STATUS & 0xFFFF);
+       P4.H = (DCPLB_STATUS >> 16);
+       P3.L = (DCPLB_DATA0 & 0xFFFF);
+       P3.H = (DCPLB_DATA0 >> 16);
+       R5 = [P4];
+
+       /* A protection violation can be caused by more than just writes
+        * to a clean WB page, so we have to ensure that:
+        * - It's a write
+        * - to a clean WB page
+        * - and is allowed in the mode the access occurred.
+        */
+
+       CC = BITTST(R5, 16);    /* ensure it was a write*/
+       IF !CC JUMP prot_violation;
+
+       /* to check the rest, we have to retrieve the DCPLB.*/
+
+       /* The low half of DCPLB_STATUS is a bit mask*/
+
+       R2 = R5.L (Z);  /* indicating which CPLB triggered the event.*/
+       R3 = 30;        /* so we can use this to determine the offset*/
+       R2.L = SIGNBITS R2;
+       R2 = R2.L (Z);  /* into the DCPLB table.*/
+       R3 = R3 - R2;
+       P4 = R3;
+       P3 = P3 + (P4<<2);
+       R3 = [P3];      /* Retrieve the CPLB*/
+
+       /* Now we can check whether it's a clean WB page*/
+
+       CC = BITTST(R3, 14);    /* 0==WB, 1==WT*/
+       IF CC JUMP prot_violation;
+       CC = BITTST(R3, 7);     /* 0 == clean, 1 == dirty*/
+       IF CC JUMP prot_violation;
+
+       /* Check whether the write is allowed in the mode that was active.*/
+
+       R2 = 1<<3;              /* checking write in user mode*/
+       CC = BITTST(R5, 17);    /* 0==was user, 1==was super*/
+       R5 = CC;
+       R2 <<= R5;              /* if was super, check write in super mode*/
+       R2 = R3 & R2;
+       CC = R2 == 0;
+       IF CC JUMP prot_violation;
+
+       /* It's a genuine write-to-clean-page.*/
+
+       BITSET(R3, 7);          /* mark as dirty*/
+       [P3] = R3;              /* and write back.*/
+       CSYNC;
+       ( R7:0,P5:0 ) = [SP++];
+       R0 = CPLB_RELOADED;
+       RTS;
+
+dcplb_miss_compare:
+
+       /* Data CPLB Miss event. We need to choose a CPLB to
+        * evict, and then locate a new CPLB to install from the
+        * config table, that covers the faulting address.
+        */
+
+       P1.L = (DCPLB_DATA15 & 0xFFFF);
+       P1.H = (DCPLB_DATA15 >> 16);
+
+       P4.L = (DCPLB_FAULT_ADDR & 0xFFFF);
+       P4.H = (DCPLB_FAULT_ADDR >> 16);
+       R4 = [P4];
+       I0 = R4;
+
+       /* The replacement procedure for DCPLBs*/
+
+       R6 = R1;        /* Save for later*/
+
+       /* Turn off CPLBs while we work.*/
+       P4.L = (DMEM_CONTROL & 0xFFFF);
+       P4.H = (DMEM_CONTROL >> 16);
+       R5 = [P4];
+       BITCLR(R5,ENDCPLB_P);
+       CLI R0;
+       SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
+       .align 8;
+       [P4] = R5;
+       SSYNC;
+       STI R0;
+
+       /* Start looking for a CPLB to evict. Our order of preference
+        * is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs
+        * are no good.
+        */
+
+       I1.L = (DCPLB_DATA0 & 0xFFFF);
+       I1.H = (DCPLB_DATA0 >> 16);
+       P1 = 3;
+       P2 = 16;
+       I2.L = dcplb_preference;
+       I2.H = dcplb_preference;
+       LSETUP(sdsearch1, edsearch1) LC0 = P1;
+sdsearch1:
+       R0 = [I2++];            /* Get the bits we're interested in*/
+       P0 = I1;                /* Go back to start of table*/
+       LSETUP (sdsearch2, edsearch2) LC1 = P2;
+sdsearch2:
+       R1 = [P0++];            /* Fetch each installed CPLB in turn*/
+       R2 = R1 & R0;           /* and test for interesting bits.*/
+       CC = R2 == 0;           /* If none are set, it'll do.*/
+       IF !CC JUMP skip_stack_check;
+
+       R2 = [P0 - 0x104];      /* R2 - PageStart */
+       P3.L = page_size_table; /* retrive end address */
+       P3.H = page_size_table; /* retrive end address */
+       R3 = 0x2;               /* 0th - position, 2 bits -length */
+       nop;                    /*Anamoly 05000209*/
+       R7 = EXTRACT(R1,R3.l);
+       R7 = R7 << 2;           /* Page size index offset */
+       P5 = R7;
+       P3 = P3 + P5;
+       R7 = [P3];              /* page size in 1K bytes */
+
+       R7 = R7 << 0xA;         /* in bytes * 1024*/
+       R7 = R2 + R7;           /* R7 - PageEnd */
+       R4 = SP;                /* Test SP is in range */
+
+       CC = R7 < R4;           /* if PageEnd < SP */
+       IF CC JUMP dfound_victim;
+       R3 = 0x284;             /* stack length from start of trap till the point */
+                               /* 20 stack locations for future modifications */
+       R4 = R4 + R3;
+       CC = R4 < R2;           /* if SP + stacklen < PageStart */
+       IF CC JUMP dfound_victim;
+skip_stack_check:
+
+edsearch2: NOP;
+edsearch1: NOP;
+
+       /* If we got here, we didn't find a DCPLB we considered
+        * replacable, which means all of them were locked.
+        */
+
+       JUMP all_locked;
+dfound_victim:
+
+#ifdef CONFIG_CPLB_INFO
+       R1 = [P0 - 0x104];
+       P2.L = dpdt_table;
+       P2.H = dpdt_table;
+       P3.L = dpdt_swapcount_table;
+       P3.H = dpdt_swapcount_table;
+       P3 += -4;
+dicount:
+       R2 = [P2];
+       P2 += 8;
+       P3 += 8;
+       CC = R2==-1;
+       IF CC JUMP dicount_done;
+       CC = R1==R2;
+       IF !CC JUMP dicount;
+       R1 = [P3];
+       R1 += 1;
+       [P3] = R1;
+       CSYNC;
+dicount_done:
+#endif
+
+       /* Clean down the hardware loops*/
+       R2 = 0;
+       LC1 = R2;
+       LC0 = R2;
+
+       /* There's a suitable victim in [P0-4] (because we've
+        * advanced already). If it's a valid dirty write-back
+        * CPLB, we need to flush the pending writes first.
+        */
+
+       CC = BITTST(R1, 0);     /* Is it valid?*/
+       IF !CC JUMP Ddoverwrite;/* nope.*/
+       CC = BITTST(R1, 7);     /* Is it dirty?*/
+       IF !CC JUMP Ddoverwrite (BP);   /* Nope.*/
+       CC = BITTST(R1, 14);    /* Is it Write-Through?*/
+       IF CC JUMP Ddoverwrite; /* Yep*/
+
+       /* This is a dirty page, so we need to flush all writes
+        * that are pending on the page.
+        */
+
+       /* Retrieve the page start address*/
+       R0 = [P0 - 0x104];
+       [--sp] = rets;
+       CALL dcplb_flush;       /* R0==CPLB addr, R1==CPLB data*/
+       rets = [sp++];
+Ddoverwrite:
+
+       /* [P0-4] is a suitable victim CPLB, so we want to
+        * overwrite it by moving all the following CPLBs
+        * one space closer to the start.
+        */
+
+       R1.L = ((DCPLB_DATA15+4) & 0xFFFF);             /*DCPLB_DATA15+4*/
+       R1.H = ((DCPLB_DATA15+4) >> 16);
+       R0 = P0;
+
+       /* If the victim happens to be in DCPLB15,
+        * we don't need to move anything.
+        */
+
+       CC = R1 == R0;
+       IF CC JUMP de_moved;
+       R1 = R1 - R0;
+       R1 >>= 2;
+       P1 = R1;
+       LSETUP(ds_move, de_move) LC0=P1;
+ds_move:
+        R0 = [P0++];   /* move data */
+       [P0 - 8] = R0;
+       R0 = [P0-0x104] /* move address */
+de_move: [P0-0x108] = R0;
+
+       /* We've now made space in DCPLB15 for the new CPLB to be
+        * installed. The next stage is to locate a CPLB in the
+        * config table that covers the faulting address.
+        */
+
+de_moved:NOP;
+       R0 = I0;                /* Our faulting address */
+
+       P2.L = dpdt_table;
+       P2.H = dpdt_table;
+#ifdef CONFIG_CPLB_INFO
+       P3.L = dpdt_swapcount_table;
+       P3.H = dpdt_swapcount_table;
+       P3 += -8;
+#endif
+
+       P1.L = page_size_table;
+       P1.H = page_size_table;
+
+       /* An extraction pattern, to retrieve bits 17:16.*/
+
+       R1 = (16<<8)|2;
+dnext: R4 = [P2++];    /* address */
+       R2 = [P2++];    /* data */
+#ifdef CONFIG_CPLB_INFO
+       P3 += 8;
+#endif
+
+       CC = R4 == -1;
+       IF CC JUMP no_page_in_table;
+
+       /* See if failed address > start address */
+       CC = R4 <= R0(IU);
+       IF !CC JUMP dnext;
+
+       /* extract page size (17:16)*/
+       R3 = EXTRACT(R2, R1.L) (Z);
+
+       /* add page size to addr to get range */
+
+       P5 = R3;
+       P5 = P1 + (P5 << 2);
+       R3 = [P5];
+       R3 = R3 + R4;
+
+       /* See if failed address < (start address + page size) */
+       CC = R0 < R3(IU);
+       IF !CC JUMP dnext;
+
+       /* We've found the CPLB that should be installed, so
+        * write it into CPLB15, masking off any caching bits
+        * if necessary.
+        */
+
+       P1.L = (DCPLB_DATA15 & 0xFFFF);
+       P1.H = (DCPLB_DATA15 >> 16);
+
+       /* If the DCPLB has cache bits set, but caching hasn't
+        * been enabled, then we want to mask off the cache-in-L1
+        * bit before installing. Moreover, if caching is off, we
+        * also want to ensure that the DCPLB has WT mode set, rather
+        * than WB, since WB pages still trigger first-write exceptions
+        * even when not caching is off, and the page isn't marked as
+        * cachable. Finally, we could mark the page as clean, not dirty,
+        * but we choose to leave that decision to the user; if the user
+        * chooses to have a CPLB pre-defined as dirty, then they always
+        * pay the cost of flushing during eviction, but don't pay the
+        * cost of first-write exceptions to mark the page as dirty.
+        */
+
+#ifdef CONFIG_BLKFIN_WT
+       BITSET(R6, 14);         /* Set WT*/
+#endif
+
+       [P1] = R2;
+       [P1-0x100] = R4;
+#ifdef CONFIG_CPLB_INFO
+       R3 = [P3];
+       R3 += 1;
+       [P3] = R3;
+#endif
+
+       /* We've installed the CPLB, so re-enable CPLBs. P4
+        * points to DMEM_CONTROL, and R5 is the value we
+        * last wrote to it, when we were disabling CPLBs.
+        */
+
+       BITSET(R5,ENDCPLB_P);
+       CLI R2;
+       .align 8;
+       [P4] = R5;
+       SSYNC;
+       STI R2;
+
+       ( R7:0,P5:0 ) = [SP++];
+       R0 = CPLB_RELOADED;
+       RTS;
+
+.data
+.align 4;
+page_size_table:
+.byte4 0x00000400;     /* 1K */
+.byte4 0x00001000;     /* 4K */
+.byte4 0x00100000;     /* 1M */
+.byte4 0x00400000;     /* 4M */
+
+.align 4;
+dcplb_preference:
+.byte4 0x00000001;     /* valid bit */
+.byte4 0x00000082;     /* dirty+lock bits */
+.byte4 0x00000002;     /* lock bit */

diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c
new file mode 100644 (file)
index 0000000..78e2b96
--- /dev/null
+++ b/cpu/bf533/cpu.c
@@ -0,0 +1,189 @@
+/*
+ * U-boot - cpu.c CPU specific functions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <command.h>
+#include <asm/entry.h>
+
+#define SSYNC() asm("ssync;")
+#define CACHE_ON 1
+#define CACHE_OFF 0
+
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC         (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY             (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL                (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+#define ANOMALY_05000158               0x200
+#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY              (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+
+static unsigned int icplb_table[16][2]={
+                       {0xFFA00000, L1_IMEMORY},
+                       {0x00000000, SDRAM_IKERNEL},    /*SDRAM_Page1*/
+                       {0x00400000, SDRAM_IKERNEL},    /*SDRAM_Page1*/
+                       {0x07C00000, SDRAM_IKERNEL},    /*SDRAM_Page14*/
+                       {0x00800000, SDRAM_IGENERIC},   /*SDRAM_Page2*/
+                       {0x00C00000, SDRAM_IGENERIC},   /*SDRAM_Page2*/
+                       {0x01000000, SDRAM_IGENERIC},   /*SDRAM_Page4*/
+                       {0x01400000, SDRAM_IGENERIC},   /*SDRAM_Page5*/
+                       {0x01800000, SDRAM_IGENERIC},   /*SDRAM_Page6*/
+                       {0x01C00000, SDRAM_IGENERIC},   /*SDRAM_Page7*/
+                       {0x02000000, SDRAM_IGENERIC},   /*SDRAM_Page8*/
+                       {0x02400000, SDRAM_IGENERIC},   /*SDRAM_Page9*/
+                       {0x02800000, SDRAM_IGENERIC},   /*SDRAM_Page10*/
+                       {0x02C00000, SDRAM_IGENERIC},   /*SDRAM_Page11*/
+                       {0x03000000, SDRAM_IGENERIC},   /*SDRAM_Page12*/
+                       {0x03400000, SDRAM_IGENERIC},   /*SDRAM_Page13*/
+};
+
+static unsigned int dcplb_table[16][2]={
+                       {0xFFA00000,L1_DMEMORY},
+                       {0x00000000,SDRAM_DKERNEL},     /*SDRAM_Page1*/
+                       {0x00400000,SDRAM_DKERNEL},     /*SDRAM_Page1*/
+                       {0x07C00000,SDRAM_DKERNEL},     /*SDRAM_Page15*/
+                       {0x00800000,SDRAM_DGENERIC},    /*SDRAM_Page2*/
+                       {0x00C00000,SDRAM_DGENERIC},    /*SDRAM_Page3*/
+                       {0x01000000,SDRAM_DGENERIC},    /*SDRAM_Page4*/
+                       {0x01400000,SDRAM_DGENERIC},    /*SDRAM_Page5*/
+                       {0x01800000,SDRAM_DGENERIC},    /*SDRAM_Page6*/
+                       {0x01C00000,SDRAM_DGENERIC},    /*SDRAM_Page7*/
+                       {0x02000000,SDRAM_DGENERIC},    /*SDRAM_Page8*/
+                       {0x02400000,SDRAM_DGENERIC},    /*SDRAM_Page9*/
+                       {0x02800000,SDRAM_DGENERIC},    /*SDRAM_Page10*/
+                       {0x02C00000,SDRAM_DGENERIC},    /*SDRAM_Page11*/
+                       {0x03000000,SDRAM_DGENERIC},    /*SDRAM_Page12*/
+                       {0x20000000,SDRAM_EBIU},        /*For Network */
+};
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+       __asm__ __volatile__
+       ("cli r3;"
+       "P0 = %0;"
+       "JUMP (P0);"
+       :
+       : "r" (L1_ISRAM)
+       );
+
+       return 0;
+}
+
+/* These functions are just used to satisfy the linker */
+int cpu_init(void)
+{
+       return 0;
+}
+
+int cleanup_before_linux(void)
+{
+       return 0;
+}
+
+void icache_enable(void)
+{
+       unsigned int *I0,*I1;
+       int i;
+
+       I0 = (unsigned int *)ICPLB_ADDR0;
+       I1 = (unsigned int *)ICPLB_DATA0;
+
+       for(i=0;i<16;i++){
+               *I0++ = icplb_table[i][0];
+               *I1++ = icplb_table[i][1];
+               }
+       cli();
+       SSYNC();
+       *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
+       SSYNC();
+       sti();
+}
+
+void icache_disable(void)
+{
+       cli();
+       SSYNC();
+       *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
+       SSYNC();
+       sti();
+}
+
+int icache_status(void)
+{
+       unsigned int value;
+       value = *(unsigned int *)IMEM_CONTROL;
+
+       if( value & (IMC|ENICPLB) )
+               return CACHE_ON;
+       else
+               return CACHE_OFF;
+}
+
+void dcache_enable(void)
+{
+       unsigned int *I0,*I1;
+       unsigned int temp;
+       int i;
+       I0 = (unsigned int *)DCPLB_ADDR0;
+       I1 = (unsigned int *)DCPLB_DATA0;
+
+       for(i=0;i<16;i++){
+               *I0++ = dcplb_table[i][0];
+               *I1++ = dcplb_table[i][1];
+               }
+       cli();
+       temp = *(unsigned int *)DMEM_CONTROL;
+       SSYNC();
+       *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE |ENDCPLB |PORT_PREF0|temp;
+       SSYNC();
+       sti();
+}
+
+void dcache_disable(void)
+{
+       cli();
+       SSYNC();
+       *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE |ENDCPLB |PORT_PREF0);
+       SSYNC();
+       sti();
+}
+
+int dcache_status(void)
+{
+       unsigned int value;
+       value = *(unsigned int *)DMEM_CONTROL;
+       if( value & (ENDCPLB))
+               return CACHE_ON;
+       else
+               return CACHE_OFF;
+}

diff --git a/cpu/bf533/cpu.h b/cpu/bf533/cpu.h
new file mode 100644 (file)
index 0000000..7ec3387
--- /dev/null
+++ b/cpu/bf533/cpu.h
@@ -0,0 +1,65 @@
+/*
+ *  U-boot - cpu.h
+ *
+ *  Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CPU_H_
+#define _CPU_H_
+
+#include <command.h>
+
+#define INTERNAL_IRQS (32)
+#define NUM_IRQ_NODES 16
+#define DEF_INTERRUPT_FLAGS 1
+#define MAX_TIM_LOAD   0xFFFFFFFF
+
+void blackfin_irq_panic(int reason, struct pt_regs * reg);
+extern void dump(struct pt_regs * regs);
+void display_excp(void);
+asmlinkage void evt_nmi(void);
+asmlinkage void evt_exception(void);
+asmlinkage void trap(void);
+asmlinkage void evt_ivhw(void);
+asmlinkage void evt_rst(void);
+asmlinkage void evt_timer(void);
+asmlinkage void evt_evt7(void);
+asmlinkage void evt_evt8(void);
+asmlinkage void evt_evt9(void);
+asmlinkage void evt_evt10(void);
+asmlinkage void evt_evt11(void);
+asmlinkage void evt_evt12(void);
+asmlinkage void evt_evt13(void);
+asmlinkage void evt_soft_int1(void);
+asmlinkage void evt_system_call(void);
+void blackfin_irq_panic(int reason, struct pt_regs * regs);
+void blackfin_free_irq(unsigned int irq, void *dev_id);
+void call_isr(int irq, struct pt_regs * fp);
+void blackfin_do_irq(int vec, struct pt_regs *fp);
+void blackfin_init_IRQ(void);
+void blackfin_enable_irq(unsigned int irq);
+void blackfin_disable_irq(unsigned int irq);
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int blackfin_request_irq(unsigned int irq,
+                    void (*handler)(int, void *, struct pt_regs *),
+                    unsigned long flags,const char *devname,void *dev_id);
+void timer_init(void);
+#endif

diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S
new file mode 100644 (file)
index 0000000..9fbdefc
--- /dev/null
+++ b/cpu/bf533/flush.S
@@ -0,0 +1,402 @@
+/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
+ * Copyright (C) 2004 LG SOft India. All Rights Reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ */
+#define ASSEMBLY
+
+#include <asm/linkage.h>
+#include <asm/cplb.h>
+#include <asm/blackfin.h>
+
+.text
+
+/* This is an external function being called by the user
+ * application through __flush_cache_all. Currently this function
+ * serves the purpose of flushing all the pending writes in
+ * in the instruction cache.
+ */
+
+ENTRY(flush_instruction_cache)
+       [--SP] = ( R7:6, P5:4 );
+       LINK 12;
+       SP += -12;
+       P5.H = (ICPLB_ADDR0 >> 16);
+       P5.L = (ICPLB_ADDR0 & 0xFFFF);
+       P4.H = (ICPLB_DATA0 >> 16);
+       P4.L = (ICPLB_DATA0 & 0xFFFF);
+       R7 = CPLB_VALID | CPLB_L1_CHBL;
+       R6 = 16;
+inext: R0 = [P5++];
+       R1 = [P4++];
+       [--SP] =  RETS;
+       CALL icplb_flush;       /* R0 = page, R1 = data*/
+       RETS = [SP++];
+iskip: R6 += -1;
+       CC = R6;
+       IF CC JUMP inext;
+       SSYNC;
+       SP += 12;
+       UNLINK;
+       ( R7:6, P5:4 ) = [SP++];
+       RTS;
+
+/* This is an internal function to flush all pending
+ * writes in the cache associated with a particular ICPLB.
+ *
+ * R0 -  page's start address
+ * R1 -  CPLB's data field.
+ */
+
+.align 2
+ENTRY(icplb_flush)
+       [--SP] = ( R7:0, P5:0 );
+       [--SP] = LC0;
+       [--SP] = LT0;
+       [--SP] = LB0;
+       [--SP] = LC1;
+       [--SP] = LT1;
+       [--SP] = LB1;
+
+       /* If it's a 1K or 4K page, then it's quickest to
+        * just systematically flush all the addresses in
+        * the page, regardless of whether they're in the
+        * cache, or dirty. If it's a 1M or 4M page, there
+        * are too many addresses, and we have to search the
+        * cache for lines corresponding to the page.
+        */
+
+       CC = BITTST(R1, 17);    /* 1MB or 4MB */
+       IF !CC JUMP iflush_whole_page;
+
+       /* We're only interested in the page's size, so extract
+        * this from the CPLB (bits 17:16), and scale to give an
+        * offset into the page_size and page_prefix tables.
+        */
+
+       R1 <<= 14;
+       R1 >>= 30;
+       R1 <<= 2;
+
+       /* We can also determine the sub-bank used, because this is
+        * taken from bits 13:12 of the address.
+        */
+
+       R3 = ((12<<8)|2);               /* Extraction pattern */
+       nop;                            /*Anamoly 05000209*/
+       R4 = EXTRACT(R0, R3.L) (Z);     /* Extract bits*/
+       R3.H = R4.L << 0 ;              /* Save in extraction pattern for later deposit.*/
+
+
+       /* So:
+        * R0 = Page start
+        * R1 = Page length (actually, offset into size/prefix tables)
+        * R3 = sub-bank deposit values
+        *
+        * The cache has 2 Ways, and 64 sets, so we iterate through
+        * the sets, accessing the tag for each Way, for our Bank and
+        * sub-bank, looking for dirty, valid tags that match our
+        * address prefix.
+        */
+
+       P5.L = (ITEST_COMMAND & 0xFFFF);
+       P5.H = (ITEST_COMMAND >> 16);
+       P4.L = (ITEST_DATA0 & 0xFFFF);
+       P4.H = (ITEST_DATA0 >> 16);
+
+       P0.L = page_prefix_table;
+       P0.H = page_prefix_table;
+       P1 = R1;
+       R5 = 0;                 /* Set counter*/
+       P0 = P1 + P0;
+       R4 = [P0];              /* This is the address prefix*/
+
+       /* We're reading (bit 1==0) the tag (bit 2==0), and we
+        * don't care about which double-word, since we're only
+        * fetching tags, so we only have to set Set, Bank,
+        * Sub-bank and Way.
+        */
+
+       P2 = 4;
+       LSETUP (ifs1, ife1) LC1 = P2;
+ifs1:  P0 = 32;                /* iterate over all sets*/
+       LSETUP (ifs0, ife0) LC0 = P0;
+ifs0:  R6 = R5 << 5;           /* Combine set*/
+       R6.H = R3.H << 0 ;      /* and sub-bank*/
+       [P5] = R6;              /* Issue Command*/
+       SSYNC;                  /* CSYNC will not work here :(*/
+       R7 = [P4];              /* and read Tag.*/
+       CC = BITTST(R7, 0);     /* Check if valid*/
+       IF !CC JUMP ifskip;     /* and skip if not.*/
+
+       /* Compare against the page address. First, plant bits 13:12
+        * into the tag, since those aren't part of the returned data.
+        */
+
+       R7 = DEPOSIT(R7, R3);   /* set 13:12*/
+       R1 = R7 & R4;           /* Mask off lower bits*/
+       CC = R1 == R0;          /* Compare against page start.*/
+       IF !CC JUMP ifskip;     /* Skip it if it doesn't match.*/
+
+       /* Tag address matches against page, so this is an entry
+        * we must flush.
+        */
+
+       R7 >>= 10;              /* Mask off the non-address bits*/
+       R7 <<= 10;
+       P3 = R7;
+       IFLUSH [P3];            /* And flush the entry*/
+ifskip:
+ife0:  R5 += 1;                /* Advance to next Set*/
+ife1:  NOP;
+
+ifinished:
+       SSYNC;                  /* Ensure the data gets out to mem.*/
+
+       /*Finished. Restore context.*/
+       LB1 = [SP++];
+       LT1 = [SP++];
+       LC1 = [SP++];
+       LB0 = [SP++];
+       LT0 = [SP++];
+       LC0 = [SP++];
+       ( R7:0, P5:0 ) = [SP++];
+       RTS;
+
+iflush_whole_page:
+       /* It's a 1K or 4K page, so quicker to just flush the
+        * entire page.
+        */
+
+       P1 = 32;                /* For 1K pages*/
+       P2 = P1 << 2;           /* For 4K pages*/
+       P0 = R0;                /* Start of page*/
+       CC = BITTST(R1, 16);    /* Whether 1K or 4K*/
+       IF CC P1 = P2;
+       P1 += -1;               /* Unroll one iteration*/
+       SSYNC;
+       IFLUSH [P0++];          /* because CSYNC can't end loops.*/
+       LSETUP (isall, ieall) LC0 = P1;
+isall:IFLUSH [P0++];
+ieall: NOP;
+       SSYNC;
+       JUMP ifinished;
+
+/* This is an external function being called by the user
+ * application through __flush_cache_all. Currently this function
+ * serves the purpose of flushing all the pending writes in
+ * in the data cache.
+ */
+
+ENTRY(flush_data_cache)
+       [--SP] = ( R7:6, P5:4 );
+       LINK 12;
+       SP += -12;
+       P5.H = (DCPLB_ADDR0 >> 16);
+       P5.L = (DCPLB_ADDR0 & 0xFFFF);
+       P4.H = (DCPLB_DATA0 >> 16);
+       P4.L = (DCPLB_DATA0 & 0xFFFF);
+       R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
+       R6 = 16;
+next:  R0 = [P5++];
+       R1 = [P4++];
+       CC = BITTST(R1, 14);    /* Is it write-through?*/
+       IF CC JUMP skip;        /* If so, ignore it.*/
+       R2 = R1 & R7;           /* Is it a dirty, cached page?*/
+       CC = R2;
+       IF !CC JUMP skip;       /* If not, ignore it.*/
+       [--SP] = RETS;
+       CALL dcplb_flush;       /* R0 = page, R1 = data*/
+       RETS = [SP++];
+skip:  R6 += -1;
+       CC = R6;
+       IF CC JUMP next;
+       SSYNC;
+       SP += 12;
+       UNLINK;
+       ( R7:6, P5:4 ) = [SP++];
+       RTS;
+
+/* This is an internal function to flush all pending
+ * writes in the cache associated with a particular DCPLB.
+ *
+ * R0 -  page's start address
+ * R1 -  CPLB's data field.
+ */
+
+.align 2
+ENTRY(dcplb_flush)
+       [--SP] = ( R7:0, P5:0 );
+       [--SP] = LC0;
+       [--SP] = LT0;
+       [--SP] = LB0;
+       [--SP] = LC1;
+       [--SP] = LT1;
+       [--SP] = LB1;
+
+       /* If it's a 1K or 4K page, then it's quickest to
+        * just systematically flush all the addresses in
+        * the page, regardless of whether they're in the
+        * cache, or dirty. If it's a 1M or 4M page, there
+        * are too many addresses, and we have to search the
+        * cache for lines corresponding to the page.
+        */
+
+       CC = BITTST(R1, 17);    /* 1MB or 4MB */
+       IF !CC JUMP dflush_whole_page;
+
+       /* We're only interested in the page's size, so extract
+        * this from the CPLB (bits 17:16), and scale to give an
+        * offset into the page_size and page_prefix tables.
+        */
+
+       R1 <<= 14;
+       R1 >>= 30;
+       R1 <<= 2;
+
+       /* The page could be mapped into Bank A or Bank B, depending
+        * on (a) whether both banks are configured as cache, and
+        * (b) on whether address bit A[x] is set. x is determined
+        * by DCBS in DMEM_CONTROL
+        */
+
+       R2 = 0;                 /* Default to Bank A (Bank B would be 1)*/
+
+       P0.L = (DMEM_CONTROL & 0xFFFF);
+       P0.H = (DMEM_CONTROL >> 16);
+
+       R3 = [P0];              /* If Bank B is not enabled as cache*/
+       CC = BITTST(R3, 2);     /* then Bank A is our only option.*/
+       IF CC JUMP bank_chosen;
+
+       R4 = 1<<14;             /* If DCBS==0, use A[14].*/
+       R5 = R4 << 7;           /* If DCBS==1, use A[23];*/
+       CC = BITTST(R3, 4);
+       IF CC R4 = R5;          /* R4 now has either bit 14 or bit 23 set.*/
+       R5 = R0 & R4;           /* Use it to test the Page address*/
+       CC = R5;                /* and if that bit is set, we use Bank B,*/
+       R2 = CC;                /* else we use Bank A.*/
+       R2 <<= 23;              /* The Bank selection's at posn 23.*/
+
+bank_chosen:
+
+       /* We can also determine the sub-bank used, because this is
+        * taken from bits 13:12 of the address.
+        */
+
+       R3 = ((12<<8)|2);               /* Extraction pattern */
+       nop;                            /*Anamoly 05000209*/
+       R4 = EXTRACT(R0, R3.L) (Z);     /* Extract bits*/
+       R3.H = R4.L << 0 ;              /* Save in extraction pattern for later deposit.*/
+
+       /* So:
+        * R0 = Page start
+        * R1 = Page length (actually, offset into size/prefix tables)
+        * R2 = Bank select mask
+        * R3 = sub-bank deposit values
+        *
+        * The cache has 2 Ways, and 64 sets, so we iterate through
+        * the sets, accessing the tag for each Way, for our Bank and
+        * sub-bank, looking for dirty, valid tags that match our
+        * address prefix.
+        */
+
+       P5.L = (DTEST_COMMAND & 0xFFFF);
+       P5.H = (DTEST_COMMAND >> 16);
+       P4.L = (DTEST_DATA0 & 0xFFFF);
+       P4.H = (DTEST_DATA0 >> 16);
+
+       P0.L = page_prefix_table;
+       P0.H = page_prefix_table;
+       P1 = R1;
+       R5 = 0;                 /* Set counter*/
+       P0 = P1 + P0;
+       R4 = [P0];              /* This is the address prefix*/
+
+
+       /* We're reading (bit 1==0) the tag (bit 2==0), and we
+        * don't care about which double-word, since we're only
+        * fetching tags, so we only have to set Set, Bank,
+        * Sub-bank and Way.
+        */
+
+       P2 = 2;
+       LSETUP (fs1, fe1) LC1 = P2;
+fs1:   P0 = 64;                /* iterate over all sets*/
+       LSETUP (fs0, fe0) LC0 = P0;
+fs0:   R6 = R5 << 5;           /* Combine set*/
+       R6.H = R3.H << 0 ;      /* and sub-bank*/
+       R6 = R6 | R2;           /* and Bank. Leave Way==0 at first.*/
+       BITSET(R6,14);
+       [P5] = R6;              /* Issue Command*/
+       SSYNC;
+       R7 = [P4];              /* and read Tag.*/
+       CC = BITTST(R7, 0);     /* Check if valid*/
+       IF !CC JUMP fskip;      /* and skip if not.*/
+       CC = BITTST(R7, 1);     /* Check if dirty*/
+       IF !CC JUMP fskip;      /* and skip if not.*/
+
+       /* Compare against the page address. First, plant bits 13:12
+        * into the tag, since those aren't part of the returned data.
+        */
+
+       R7 = DEPOSIT(R7, R3);   /* set 13:12*/
+       R1 = R7 & R4;           /* Mask off lower bits*/
+       CC = R1 == R0;          /* Compare against page start.*/
+       IF !CC JUMP fskip;      /* Skip it if it doesn't match.*/
+
+       /* Tag address matches against page, so this is an entry
+        * we must flush.
+        */
+
+       R7 >>= 10;              /* Mask off the non-address bits*/
+       R7 <<= 10;
+       P3 = R7;
+       SSYNC;
+       FLUSHINV [P3];          /* And flush the entry*/
+fskip:
+fe0:   R5 += 1;                /* Advance to next Set*/
+fe1:   BITSET(R2, 26);         /* Go to next Way.*/
+
+dfinished:
+       SSYNC;                  /* Ensure the data gets out to mem.*/
+
+       /*Finished. Restore context.*/
+       LB1 = [SP++];
+       LT1 = [SP++];
+       LC1 = [SP++];
+       LB0 = [SP++];
+       LT0 = [SP++];
+       LC0 = [SP++];
+       ( R7:0, P5:0 ) = [SP++];
+       RTS;
+
+dflush_whole_page:
+
+       /* It's a 1K or 4K page, so quicker to just flush the
+        * entire page.
+        */
+
+       P1 = 32;                /* For 1K pages*/
+       P2 = P1 << 2;           /* For 4K pages*/
+       P0 = R0;                /* Start of page*/
+       CC = BITTST(R1, 16);    /* Whether 1K or 4K*/
+       IF CC P1 = P2;
+       P1 += -1;               /* Unroll one iteration*/
+    SSYNC;
+       FLUSHINV [P0++];        /* because CSYNC can't end loops.*/
+       LSETUP (eall, eall) LC0 = P1;
+eall:  FLUSHINV [P0++];
+       SSYNC;
+       JUMP dfinished;
+
+.align 4;
+page_prefix_table:
+.byte4         0xFFFFFC00;     /* 1K */
+.byte4 0xFFFFF000;     /* 4K */
+.byte4 0xFFF00000;     /* 1M */
+.byte4 0xFFC00000;     /* 4M */
+.page_prefix_table.end:

diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S
new file mode 100644 (file)
index 0000000..e780dc6
--- /dev/null
+++ b/cpu/bf533/interrupt.S
@@ -0,0 +1,391 @@
+/*
+ * U-boot - interrupt.S Processing of interrupts and exception handling
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file is based on interrupt.S
+ *
+ * Copyright (C) 2003  Metrowerks, Inc. <mwaddel@metrowerks.com>
+ * Copyright (C) 2002  Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
+ * Copyright (C) 1998  D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ *                     Kenneth Albanowski <kjahds@kjahds.com>,
+ *                     The Silver Hammer Group, Ltd.
+ *
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * This file is also based on exception.asm
+ * (C) Copyright 2001-2005 - Analog Devices, Inc.  All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define ASSEMBLY
+
+#include <asm/hw_irq.h>
+#include <asm/entry.h>
+#include <asm/blackfin_defs.h>
+#include <asm/cpu/bf533_irq.h>
+
+.global blackfin_irq_panic;
+
+.text
+.align 2
+
+#ifndef CONFIG_KGDB
+.global evt_emulation
+evt_emulation:
+       SAVE_CONTEXT
+       r0 = IRQ_EMU;
+       r1 = seqstat;
+       sp += -12;
+       call blackfin_irq_panic;
+       sp += 12;
+       rte;
+#endif
+
+.global evt_nmi
+evt_nmi:
+       SAVE_CONTEXT
+       r0 = IRQ_NMI;
+       r1 = RETN;
+       sp += -12;
+       call blackfin_irq_panic;
+       sp += 12;
+
+_evt_nmi_exit:
+       rtn;
+
+.global trap
+trap:
+       [--sp] = r0;
+       [--sp] = r1;
+       [--sp] = p0;
+       [--sp] = p1;
+       [--sp] = astat;
+       r0 = seqstat;
+       R0 <<= 26;
+       R0 >>= 26;
+       p0 = r0;
+       p1.l = EVTABLE;
+       p1.h = EVTABLE;
+       p0 = p1 + (p0 << 1);
+       r1 = W[p0] (Z);
+       p1 = r1;
+       jump (pc + p1);
+
+.global _EVENT1
+_EVENT1:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EVENT2
+_EVENT2:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EVENT3
+_EVENT3:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EVENT4
+_EVENT4:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EVENT5
+_EVENT5:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EVENT6
+_EVENT6:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EVENT7
+_EVENT7:
+       RAISE 15;
+       JUMP.S _EXIT;
+
+.global _EVENT8
+_EVENT8:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EVENT9
+_EVENT9:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EVENT10
+_EVENT10:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EVENT11
+_EVENT11:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EVENT12
+_EVENT12:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EVENT13
+_EVENT13:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EVENT14
+_EVENT14:
+/*     RAISE 14;       */
+       CALL    _cplb_hdr;
+       JUMP.S _EXIT;
+
+.global _EVENT19
+_EVENT19:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EVENT20
+_EVENT20:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EVENT21
+_EVENT21:
+       RAISE 14;
+       JUMP.S _EXIT;
+
+.global _EXIT
+_EXIT:
+       ASTAT = [sp++];
+       p1 = [sp++];
+       p0 = [sp++];
+       r1 = [sp++];
+       r0 = [sp++];
+       RTX;
+
+EVTABLE:
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x0000;
+       .byte2 0x003E;
+       .byte2 0x0042;
+       .byte4 0x0000;
+       .byte4 0x0000;
+       .byte4 0x0000;
+       .byte4 0x0000;
+       .byte4 0x0000;
+       .byte4 0x0000;
+       .byte4 0x0000;
+       .byte2 0x0000;
+       .byte2 0x001E;
+       .byte2 0x0022;
+       .byte2 0x0032;
+       .byte2 0x002e;
+       .byte2 0x0002;
+       .byte2 0x0036;
+       .byte2 0x002A;
+       .byte2 0x001A;
+       .byte2 0x0016;
+       .byte2 0x000A;
+       .byte2 0x000E;
+       .byte2 0x0012;
+       .byte2 0x0006;
+       .byte2 0x0026;
+
+.global evt_rst
+evt_rst:
+       SAVE_CONTEXT
+       r0 = IRQ_RST;
+       r1 = RETN;
+       sp += -12;
+       call do_reset;
+       sp += 12;
+
+_evt_rst_exit:
+       rtn;
+
+irq_panic:
+       r0 = IRQ_EVX;
+       r1 =  sp;
+       sp += -12;
+       call blackfin_irq_panic;
+       sp += 12;
+
+.global evt_ivhw
+evt_ivhw:
+       SAVE_CONTEXT
+       RAISE 14;
+
+_evt_ivhw_exit:
+        rti;
+
+.global evt_timer
+evt_timer:
+       SAVE_CONTEXT
+       r0 = IRQ_CORETMR;
+       sp += -12;
+       /* Polling method used now. */
+       /* call timer_int; */
+       sp += 12;
+       RESTORE_CONTEXT
+       rti;
+       nop;
+
+.global evt_evt7
+evt_evt7:
+       SAVE_CONTEXT
+       r0 = 7;
+       sp += -12;
+       call process_int;
+       sp += 12;
+
+evt_evt7_exit:
+       RESTORE_CONTEXT
+       rti;
+
+.global evt_evt8
+evt_evt8:
+       SAVE_CONTEXT
+       r0 = 8;
+       sp += -12;
+       call process_int;
+       sp += 12;
+
+evt_evt8_exit:
+       RESTORE_CONTEXT
+       rti;
+
+.global evt_evt9
+evt_evt9:
+       SAVE_CONTEXT
+       r0 = 9;
+       sp += -12;
+       call process_int;
+       sp += 12;
+
+evt_evt9_exit:
+       RESTORE_CONTEXT
+       rti;
+
+.global evt_evt10
+evt_evt10:
+       SAVE_CONTEXT
+       r0 = 10;
+       sp += -12;
+       call process_int;
+       sp += 12;
+
+evt_evt10_exit:
+       RESTORE_CONTEXT
+       rti;
+
+.global evt_evt11
+evt_evt11:
+       SAVE_CONTEXT
+       r0 = 11;
+       sp += -12;
+       call process_int;
+       sp += 12;
+
+evt_evt11_exit:
+       RESTORE_CONTEXT
+       rti;
+
+.global evt_evt12
+evt_evt12:
+       SAVE_CONTEXT
+       r0 = 12;
+       sp += -12;
+       call process_int;
+       sp += 12;
+evt_evt12_exit:
+        RESTORE_CONTEXT
+        rti;
+
+.global evt_evt13
+evt_evt13:
+       SAVE_CONTEXT
+       r0 = 13;
+       sp += -12;
+       call process_int;
+       sp += 12;
+
+evt_evt13_exit:
+        RESTORE_CONTEXT
+        rti;
+
+.global evt_system_call
+evt_system_call:
+       [--sp] = r0;
+       [--SP] = RETI;
+       r0 = [sp++];
+       r0 += 2;
+       [--sp] = r0;
+       RETI = [SP++];
+       r0 = [SP++];
+       SAVE_CONTEXT
+       sp += -12;
+       call display_excp;
+       sp += 12;
+       RESTORE_CONTEXT
+       RTI;
+
+evt_system_call_exit:
+       rti;
+
+.global evt_soft_int1
+evt_soft_int1:
+       [--sp] = r0;
+       [--SP] = RETI;
+       r0 = [sp++];
+       r0 += 2;
+       [--sp] = r0;
+       RETI = [SP++];
+       r0 = [SP++];
+       SAVE_CONTEXT
+       sp += -12;
+       call display_excp;
+       sp += 12;
+       RESTORE_CONTEXT
+       RTI;
+
+evt_soft_int1_exit:
+       rti;

diff --git a/cpu/bf533/interrupts.c b/cpu/bf533/interrupts.c
new file mode 100644 (file)
index 0000000..df1a25e
--- /dev/null
+++ b/cpu/bf533/interrupts.c
@@ -0,0 +1,165 @@
+/*
+ * U-boot - interrupts.c Interrupt related routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on interrupts.c
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
+ * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
+ * Copyright 2003 Metrowerks/Motorola
+ * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
+ *                     BuyWays B.V. (www.buyways.nl)
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/machdep.h>
+#include <asm/irq.h>
+#include <asm/cpu/defBF533.h>
+#include "cpu.h"
+
+static ulong timestamp;
+static ulong last_time;
+static int int_flag;
+
+int irq_flags; /* needed by asm-blackfin/system.h */
+
+/* Functions just to satisfy the linker */
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On BF533 it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+       return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On BF533 it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+       ulong tbclk;
+
+       tbclk = CFG_HZ;
+       return tbclk;
+}
+
+void enable_interrupts(void)
+{
+       restore_flags(int_flag);
+}
+
+int disable_interrupts(void)
+{
+       save_and_cli(int_flag);
+       return 1;
+}
+
+int interrupt_init(void)
+{
+       return (0);
+}
+
+void udelay(unsigned long usec)
+{
+       unsigned long delay, start, stop;
+       unsigned long cclk;
+       cclk = (CONFIG_CCLK_HZ);
+
+       while ( usec > 1 ) {
+              /*
+               * how many clock ticks to delay?
+               *  - request(in useconds) * clock_ticks(Hz) / useconds/second
+               */
+               if (usec < 1000) {
+                       delay = (usec * (cclk/244)) >> 12 ;
+                       usec = 0;
+               } else {
+                       delay = (1000 * (cclk/244)) >> 12 ;
+                       usec -= 1000;
+               }
+
+               asm volatile (" %0 = CYCLES;": "=g"(start));
+               do {
+                       asm volatile (" %0 = CYCLES; ": "=g"(stop));
+               } while (stop - start < delay);
+       }
+
+       return;
+}
+
+void timer_init(void)
+{
+       *pTCNTL = 0x1;
+       *pTSCALE = 0x0;
+       *pTCOUNT  = MAX_TIM_LOAD;
+       *pTPERIOD = MAX_TIM_LOAD;
+       *pTCNTL = 0x7;
+       asm("CSYNC;");
+
+       timestamp = 0;
+       last_time = 0;
+}
+
+/* Any network command or flash
+ * command is started get_timer shall
+ * be called before TCOUNT gets reset,
+ * to implement the accurate timeouts.
+ *
+ * How ever milliconds doesn't return
+ * the number that has been elapsed from
+ * the last reset.
+ *
+ *  As get_timer is used in the u-boot
+ *  only for timeouts this should be
+ *  sufficient
+ */
+ulong get_timer(ulong base)
+{
+       ulong milisec;
+
+       /* Number of clocks elapsed */
+       ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
+
+       /* Find if the TCOUNT is reset
+       timestamp gives the number of times
+       TCOUNT got reset */
+       if(clocks < last_time)
+               timestamp++;
+       last_time = clocks;
+
+       /* Get the number of milliseconds */
+       milisec = clocks/(CONFIG_CCLK_HZ / 1000);
+
+       /* Find the number of millisonds
+       that got elapsed before this TCOUNT
+       cycle */
+       milisec += timestamp * (MAX_TIM_LOAD/(CONFIG_CCLK_HZ / 1000));
+
+       return (milisec - base);
+}

diff --git a/cpu/bf533/ints.c b/cpu/bf533/ints.c
new file mode 100644 (file)
index 0000000..859f4b2
--- /dev/null
+++ b/cpu/bf533/ints.c
@@ -0,0 +1,107 @@
+/*
+ * U-boot - ints.c Interrupt related routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on ints.c
+ *
+ * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
+ *             drivers
+ *
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
+ * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
+ * Copyright 2003 Metrowerks/Motorola
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/stddef.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/traps.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/machdep.h>
+#include <asm/setup.h>
+#include <asm/blackfin.h>
+#include "cpu.h"
+
+void blackfin_irq_panic(int reason, struct pt_regs *regs)
+{
+       printf("\n\nException: IRQ 0x%x entered\n", reason);
+       printf("code=[0x%x], ", (unsigned int) (regs->seqstat & 0x3f));
+       printf("stack frame=0x%x, ", (unsigned int) regs);
+       printf("bad PC=0x%04x\n", (unsigned int) regs->pc);
+       dump(regs);
+       printf("Unhandled IRQ or exceptions!\n");
+       printf("Please reset the board \n");
+}
+
+void blackfin_init_IRQ(void)
+{
+       *(unsigned volatile long *) (SIC_IMASK) = SIC_UNMASK_ALL;
+       cli();
+#ifndef CONFIG_KGDB
+       *(unsigned volatile long *) (EVT_EMULATION_ADDR) = 0x0;
+#endif
+       *(unsigned volatile long *) (EVT_NMI_ADDR) =
+               (unsigned volatile long) evt_nmi;
+       *(unsigned volatile long *) (EVT_EXCEPTION_ADDR) =
+               (unsigned volatile long) trap;
+       *(unsigned volatile long *) (EVT_HARDWARE_ERROR_ADDR) =
+               (unsigned volatile long) evt_ivhw;
+       *(unsigned volatile long *) (EVT_RESET_ADDR) =
+               (unsigned volatile long) evt_rst;
+       *(unsigned volatile long *) (EVT_TIMER_ADDR) =
+               (unsigned volatile long) evt_timer;
+       *(unsigned volatile long *) (EVT_IVG7_ADDR) =
+               (unsigned volatile long) evt_evt7;
+       *(unsigned volatile long *) (EVT_IVG8_ADDR) =
+               (unsigned volatile long) evt_evt8;
+       *(unsigned volatile long *) (EVT_IVG9_ADDR) =
+               (unsigned volatile long) evt_evt9;
+       *(unsigned volatile long *) (EVT_IVG10_ADDR) =
+               (unsigned volatile long) evt_evt10;
+       *(unsigned volatile long *) (EVT_IVG11_ADDR) =
+               (unsigned volatile long) evt_evt11;
+       *(unsigned volatile long *) (EVT_IVG12_ADDR) =
+               (unsigned volatile long) evt_evt12;
+       *(unsigned volatile long *) (EVT_IVG13_ADDR) =
+               (unsigned volatile long) evt_evt13;
+       *(unsigned volatile long *) (EVT_IVG14_ADDR) =
+               (unsigned volatile long) evt_system_call;
+       *(unsigned volatile long *) (EVT_IVG15_ADDR) =
+               (unsigned volatile long) evt_soft_int1;
+       *(volatile unsigned long *) ILAT = 0;
+       asm("csync;");
+       sti();
+       *(volatile unsigned long *) IMASK = 0xffbf;
+       asm("csync;");
+}
+
+void display_excp(void)
+{
+       printf("Exception!\n");
+}

diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c
new file mode 100644 (file)
index 0000000..7b43ffd
--- /dev/null
+++ b/cpu/bf533/serial.c
@@ -0,0 +1,195 @@
+/*
+ * U-boot - serial.c Serial driver for BF533
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART.
+ * Copyright (c) 2003  Bas Vermeulen <bas@buyways.nl>,
+ *                     BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on blkfinserial.c
+ * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
+ * Copyright(c) 2003   Metrowerks      <mwaddel@metrowerks.com>
+ * Copyright(c)        2001    Tony Z. Kou     <tonyko@arcturusnetworks.com>
+ * Copyright(c)        2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328 version serial driver imlpementation which was:
+ * Copyright (C) 1995       David S. Miller    <davem@caip.rutgers.edu>
+ * Copyright (C) 1998       Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne     <jeff@uclinux.org>
+ * Copyright (C) 1999       Vladimir Gurevich  <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/segment.h>
+#include <asm/bitops.h>
+#include <asm/delay.h>
+#include <asm/uaccess.h>
+#include "bf533_serial.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long pll_div_fact;
+
+void calc_baud(void)
+{
+       unsigned char i;
+       int     temp;
+
+       for(i = 0; i < sizeof(baud_table)/sizeof(int); i++) {
+               temp =  CONFIG_SCLK_HZ/(baud_table[i]*8);
+               if ( temp && 0x1 == 1 ) {
+                       temp++;
+               }
+               temp = temp/2;
+               hw_baud_table[i].dl_high = (temp >> 8)& 0xFF;
+               hw_baud_table[i].dl_low = (temp) & 0xFF;
+       }
+}
+
+void serial_setbrg(void)
+{
+       int i;
+
+       calc_baud();
+
+       for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
+               if (gd->baudrate == baud_table[i])
+                       break;
+       }
+
+       /* Enable UART */
+       *pUART_GCTL |= UART_GCTL_UCEN;
+       asm("ssync;");
+
+       /* Set DLAB in LCR to Access DLL and DLH */
+       ACCESS_LATCH;
+       asm("ssync;");
+
+       *pUART_DLL = hw_baud_table[i].dl_low;
+       asm("ssync;");
+       *pUART_DLH = hw_baud_table[i].dl_high;
+       asm("ssync;");
+
+       /* Clear DLAB in LCR to Access THR RBR IER */
+       ACCESS_PORT_IER;
+       asm("ssync;");
+
+       /* Enable  ERBFI and ELSI interrupts
+       * to poll SIC_ISR register*/
+       *pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
+       asm("ssync;");
+
+       /* Set LCR to Word Lengh 8-bit word select */
+       *pUART_LCR = UART_LCR_WLS8;
+       asm("ssync;");
+
+       return;
+}
+
+int serial_init(void)
+{
+       serial_setbrg();
+       return (0);
+}
+
+void serial_putc(const char c)
+{
+       if ((*pUART_LSR) & UART_LSR_TEMT)
+       {
+               if (c == '\n')
+                       serial_putc('\r');
+
+               local_put_char(c);
+       }
+
+       while (!((*pUART_LSR) & UART_LSR_TEMT))
+               SYNC_ALL;
+
+       return;
+}
+
+int serial_tstc(void)
+{
+       if (*pUART_LSR & UART_LSR_DR)
+               return 1;
+       else
+               return 0;
+}
+
+int serial_getc(void)
+{
+       unsigned short uart_lsr_val, uart_rbr_val;
+       unsigned long isr_val;
+       int ret;
+
+       /* Poll for RX Interrupt */
+       while (!((isr_val = *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT));
+       asm("csync;");
+
+       uart_lsr_val = *pUART_LSR;      /* Clear status bit */
+       uart_rbr_val = *pUART_RBR;      /* getc() */
+
+       if (isr_val & IRQ_UART_ERROR_BIT) {
+               ret =  -1;
+       }
+       else
+       {
+               ret = uart_rbr_val & 0xff;
+       }
+
+       return ret;
+}
+
+void serial_puts(const char *s)
+{
+       while (*s) {
+               serial_putc(*s++);
+       }
+}
+
+static void local_put_char(char ch)
+{
+       int flags = 0;
+       unsigned long isr_val;
+
+       save_and_cli(flags);
+
+       /* Poll for TX Interruput */
+       while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT));
+       asm("csync;");
+
+       *pUART_THR = ch;                        /* putc() */
+
+       if (isr_val & IRQ_UART_ERROR_BIT) {
+               printf("?");
+       }
+
+       restore_flags(flags);
+
+       return ;
+}

diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S
new file mode 100644 (file)
index 0000000..6d58575
--- /dev/null
+++ b/cpu/bf533/start.S
@@ -0,0 +1,435 @@
+/*
+ * U-boot - start.S Startup file of u-boot for BF533
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on head.S
+ * Copyright (c) 2003  Metrowerks/Motorola
+ * Copyright (C) 1998  D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ *                     Kenneth Albanowski <kjahds@kjahds.com>,
+ *                     The Silver Hammer Group, Ltd.
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Note: A change in this file subsequently requires a change in
+ *       board/$(board_name)/config.mk for a valid u-boot.bin
+ */
+
+#define ASSEMBLY
+
+#include <linux/config.h>
+#include <asm/blackfin.h>
+#include <config.h>
+#include <asm/mem_init.h>
+
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
+#endif
+
+.global _stext;
+.global __bss_start;
+.global start;
+.global _start;
+.global _rambase;
+.global _ramstart;
+.global _ramend;
+.global _bf533_data_dest;
+.global _bf533_data_size;
+.global edata;
+.global _initialize;
+.global _exit;
+.global flashdataend;
+
+.text
+_start:
+start:
+_stext:
+
+       R0 = 0x30;
+       SYSCFG = R0;
+       SSYNC;
+
+       /* As per HW reference manual DAG registers,
+        * DATA and Address resgister shall be zero'd
+        * in initialization, after a reset state
+        */
+       r1 = 0; /* Data registers zero'd */
+       r2 = 0;
+       r3 = 0;
+       r4 = 0;
+       r5 = 0;
+       r6 = 0;
+       r7 = 0;
+
+       p0 = 0; /* Address registers zero'd */
+       p1 = 0;
+       p2 = 0;
+       p3 = 0;
+       p4 = 0;
+       p5 = 0;
+
+       i0 = 0; /* DAG Registers zero'd */
+       i1 = 0;
+       i2 = 0;
+       i3 = 0;
+       m0 = 0;
+       m1 = 0;
+       m3 = 0;
+       m3 = 0;
+       l0 = 0;
+       l1 = 0;
+       l2 = 0;
+       l3 = 0;
+       b0 = 0;
+       b1 = 0;
+       b2 = 0;
+       b3 = 0;
+
+       /* Set loop counters to zero, to make sure that
+        * hw loops are disabled.
+        */
+       lc0 = 0;
+       lc1 = 0;
+
+       SSYNC;
+
+       /* Check soft reset status */
+       p0.h = SWRST >> 16;
+       p0.l = SWRST & 0xFFFF;
+       r0.l = w[p0];
+
+       cc = bittst(r0, 15);
+       if !cc jump no_soft_reset;
+
+       /* Clear Soft reset */
+       r0 = 0x0000;
+       w[p0] = r0;
+       ssync;
+
+no_soft_reset:
+       nop;
+
+       /* Clear EVT registers */
+       p0.h = (EVT_EMULATION_ADDR >> 16);
+       p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
+       p0 += 8;
+       p1 = 14;
+       r1 = 0;
+       LSETUP(4,4) lc0 = p1;
+       [ p0 ++ ] = r1;
+
+       /*
+        *  Set PLL_CTL
+        *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+        *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
+        *   - [7]     = output delay (add 200ps of delay to mem signals)
+        *   - [6]     = input delay (add 200ps of input delay to mem signals)
+        *   - [5]     = PDWN      : 1=All Clocks off
+        *   - [3]     = STOPCK    : 1=Core Clock off
+        *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
+        *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+        *   all other bits set to zero
+        */
+
+       r0 = CONFIG_VCO_MULT;   /* Load the VCO multiplier */
+       r0 = r0 << 9;           /* Shift it over */
+       r1 =  CONFIG_CLKIN_HALF;        /* Do we need to divide CLKIN by 2? */
+       r0 = r1 | r0;
+       r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL?                 */
+       r1 = r1 << 8;   /* Shift it over */
+       r0 = r1 | r0;   /* add them all together */
+
+       p0.h = (PLL_CTL >> 16);
+       p0.l = (PLL_CTL & 0xFFFF);      /* Load the address */
+       cli r2;                         /* Disable interrupts */
+       w[p0] = r0;                     /* Set the value */
+       idle;                           /* Wait for the PLL to stablize */
+       sti r2;                         /* Enable interrupts */
+       ssync;
+
+       /*
+        * Turn on the CYCLES COUNTER
+        */
+       r2 = SYSCFG;
+       BITSET (r2,1);
+       SYSCFG = r2;
+
+       /* Configure SCLK & CCLK Dividers */
+       r0 = CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV;
+       p0.h = (PLL_DIV >> 16);
+       p0.l = (PLL_DIV & 0xFFFF);
+       w[p0] = r0;
+       ssync;
+
+wait_for_pll_stab:
+       p0.h = (PLL_STAT >> 16);
+       p0.l = (PLL_STAT & 0xFFFF);
+       r0.l = w[p0];
+       cc = bittst(r0,5);
+       if !cc jump wait_for_pll_stab;
+
+       /* Configure SDRAM if SDRAM is already not enabled */
+       p0.l = (EBIU_SDSTAT & 0xFFFF);
+       p0.h = (EBIU_SDSTAT >> 16);
+       r0.l = w[p0];
+       cc = bittst(r0, 3);
+       if !cc jump skip_sdram_enable;
+
+       /* SDRAM initialization */
+       p0.l = (EBIU_SDGCTL & 0xFFFF);
+       p0.h = (EBIU_SDGCTL >> 16);     /* SDRAM Memory Global Control Register */
+       r0.h = (mem_SDGCTL >> 16);
+       r0.l = (mem_SDGCTL & 0xFFFF);
+       [p0] = r0;
+       ssync;
+
+       p0.l = (EBIU_SDBCTL & 0xFFFF);
+       p0.h = (EBIU_SDBCTL >> 16);     /* SDRAM Memory Bank Control Register */
+       r0 = mem_SDBCTL;
+       w[p0] = r0.l;
+       ssync;
+
+       p0.l = (EBIU_SDRRC & 0xFFFF);
+       p0.h = (EBIU_SDRRC >> 16);      /* SDRAM Refresh Rate Control Register */
+       r0 = mem_SDRRC;
+       w[p0] = r0.l;
+       ssync;
+
+skip_sdram_enable:
+       nop;
+
+#ifndef        CFG_NO_FLASH
+       /* relocate into to RAM */
+       p1.l = (CFG_FLASH_BASE & 0xffff);
+       p1.h = (CFG_FLASH_BASE >> 16);
+       p2.l = (CFG_MONITOR_BASE & 0xffff);
+       p2.h = (CFG_MONITOR_BASE >> 16);
+       r0.l = (CFG_MONITOR_LEN & 0xffff);
+       r0.h = (CFG_MONITOR_LEN >> 16);
+loop1:
+       r1 = [p1];
+       [p2] = r1;
+       p3=0x4;
+       p1=p1+p3;
+       p2=p2+p3;
+       r2=0x4;
+       r0=r0-r2;
+       cc=r0==0x0;
+       if !cc jump loop1;
+#endif
+       /*
+        * configure STACK
+        */
+       r0.h = (CONFIG_STACKBASE >> 16);
+       r0.l = (CONFIG_STACKBASE & 0xFFFF);
+       sp = r0;
+       fp = sp;
+
+       /*
+        * This next section keeps the processor in supervisor mode
+        * during kernel boot.  Switches to user mode at end of boot.
+        * See page 3-9 of Hardware Reference manual for documentation.
+        */
+
+       /* To keep ourselves in the supervisor mode */
+       p0.l = (EVT_IVG15_ADDR & 0xFFFF);
+       p0.h = (EVT_IVG15_ADDR >> 16);
+
+       p1.l = _real_start;
+       p1.h = _real_start;
+       [p0] = p1;
+
+       p0.l = (IMASK & 0xFFFF);
+       p0.h = (IMASK >> 16);
+       r0 = IVG15_POS;
+       [p0] = r0;
+       raise 15;
+       p0.l = WAIT_HERE;
+       p0.h = WAIT_HERE;
+       reti = p0;
+       rti;
+
+WAIT_HERE:
+       jump WAIT_HERE;
+
+.global _real_start;
+_real_start:
+       [ -- sp ] = reti;
+
+#ifdef CONFIG_EZKIT533
+       p0.l = (WDOG_CTL & 0xFFFF);
+       p0.h = (WDOG_CTL >> 16);
+       r0 = WATCHDOG_DISABLE(z);
+       w[p0] = r0;
+#endif
+
+       /* Code for initializing Async mem banks */
+       p2.h = (EBIU_AMBCTL1 >> 16);
+       p2.l = (EBIU_AMBCTL1 & 0xFFFF);
+       r0.h = (AMBCTL1VAL >> 16);
+       r0.l = (AMBCTL1VAL & 0xFFFF);
+       [p2] = r0;
+       ssync;
+
+       p2.h = (EBIU_AMBCTL0 >> 16);
+       p2.l = (EBIU_AMBCTL0 & 0xFFFF);
+       r0.h = (AMBCTL0VAL >> 16);
+       r0.l = (AMBCTL0VAL & 0xFFFF);
+       [p2] = r0;
+       ssync;
+
+       p2.h = (EBIU_AMGCTL >> 16);
+       p2.l = (EBIU_AMGCTL & 0xffff);
+       r0 = AMGCTLVAL;
+       w[p2] = r0;
+       ssync;
+
+       /* DMA reset code to Hi of L1 SRAM */
+copy:
+       P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
+       P1.L = lo(SYSMMR_BASE);
+
+       R0.H = reset_start;     /* Source Address (high) */
+       R0.L = reset_start;     /* Source Address (low) */
+       R1.H = reset_end;
+       R1.L = reset_end;
+       R2 = R1 - R0;           /* Count */
+       R1.H = hi(L1_ISRAM);    /* Destination Address (high) */
+       R1.L = lo(L1_ISRAM);    /* Destination Address (low) */
+       R3.L = DMAEN;           /* Source DMAConfig Value (8-bit words) */
+       R4.L = (DI_EN | WNR | DMAEN);   /* Destination DMAConfig Value (8-bit words) */
+
+DMA:
+       R6 = 0x1 (Z);
+       W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6;   /* Source Modify = 1 */
+       W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6;   /* Destination Modify = 1 */
+
+       [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0;  /* Set Source Base Address */
+       W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2;    /* Set Source Count */
+       /* Set Source  DMAConfig = DMA Enable,
+       Memory Read,  8-Bit Transfers, 1-D DMA, Flow - Stop */
+       W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+
+       [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;  /* Set Destination Base Address */
+       W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2;    /* Set Destination Count */
+       /* Set Destination DMAConfig = DMA Enable,
+       Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
+       W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+
+       IDLE;   /* Wait for DMA to Complete */
+
+       R0 = 0x1;
+       W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
+
+       /* DMA reset code to DATA BANK A which uses this port
+        * to avoid following problem
+        * " Data from a Data Cache fill can be corrupoted after or during
+        *   instruction DMA if certain core stalls exist"
+        */
+
+copy_as_data:
+       R0.H = reset_start;     /* Source Address (high) */
+       R0.L = reset_start;     /* Source Address (low) */
+       R1.H = reset_end;
+       R1.L = reset_end;
+       R2 = R1 - R0;   /* Count */
+       R1.H = hi(DATA_BANKA_SRAM);     /* Destination Address (high) */
+       R1.L = lo(DATA_BANKA_SRAM);     /* Destination Address (low) */
+       R3.L = DMAEN;   /* Source DMAConfig Value (8-bit words) */
+       R4.L = (DI_EN | WNR | DMAEN);   /* Destination DMAConfig Value (8-bit words) */
+
+DMA_DATA:
+       R6 = 0x1 (Z);
+       W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6;   /* Source Modify = 1 */
+       W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6;   /* Destination Modify = 1 */
+
+       [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0;  /* Set Source Base Address */
+       W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2;    /* Set Source Count */
+       /* Set Source      DMAConfig = DMA Enable,
+       Memory Read,  8-Bit Transfers, 1-D DMA, Flow - Stop */
+       W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+
+       [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;  /* Set Destination Base Address */
+       W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2;    /* Set Destination Count */
+       /* Set Destination DMAConfig = DMA Enable,
+       Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
+       W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+
+       IDLE;   /* Wait for DMA to Complete */
+
+       R0 = 0x1;
+       W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
+
+copy_end: nop;
+
+       /* Initialize BSS Section with 0 s */
+       p1.l = __bss_start;
+       p1.h = __bss_start;
+       p2.l = _end;
+       p2.h = _end;
+       r1 = p1;
+       r2 = p2;
+       r3 = r2 - r1;
+       r3 = r3 >> 2;
+       p3 = r3;
+       lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
+       CC = p2<=p1;
+       if CC jump _clear_bss_skip;
+       r0 = 0;
+_clear_bss:
+_clear_bss_end:
+       [p1++] = r0;
+_clear_bss_skip:
+
+       p0.l = _start1;
+       p0.h = _start1;
+       jump (p0);
+
+reset_start:
+       p0.h = WDOG_CNT >> 16;
+       p0.l = WDOG_CNT & 0xffff;
+       r0 = 0x0010;
+       w[p0] = r0;
+       p0.h = WDOG_CTL >> 16;
+       p0.l = WDOG_CTL & 0xffff;
+       r0 = 0x0000;
+       w[p0] = r0;
+reset_wait:
+       jump reset_wait;
+
+reset_end: nop;
+
+_exit:
+       jump.s  _exit;

diff --git a/cpu/bf533/start1.S b/cpu/bf533/start1.S
new file mode 100644 (file)
index 0000000..6f48124
--- /dev/null
+++ b/cpu/bf533/start1.S
@@ -0,0 +1,38 @@
+/*
+ * U-boot - start1.S Code running out of RAM after relocation
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define ASSEMBLY
+#include <linux/config.h>
+#include <asm/blackfin.h>
+#include <config.h>
+
+.global        start1;
+.global        _start1;
+
+.text
+_start1:
+start1:
+       sp += -12;
+       call    board_init_f;
+       sp += 12;

diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c
new file mode 100644 (file)
index 0000000..37470d5
--- /dev/null
+++ b/cpu/bf533/traps.c
@@ -0,0 +1,73 @@
+/*
+ * U-boot - traps.c Routines related to interrupts and exceptions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * No original Copyright holder listed,
+ * Probabily original (C) Roman Zippel (assigned DJD, 1999)
+ *
+ * Copyright 2003 Metrowerks - for Blackfin
+ * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
+ * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/errno.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/traps.h>
+#include <asm/page.h>
+#include <asm/machdep.h>
+#include "cpu.h"
+
+void init_IRQ(void)
+{
+       blackfin_init_IRQ();
+       return;
+}
+
+void process_int(unsigned long vec, struct pt_regs *fp)
+{
+       return;
+}
+
+void dump(struct pt_regs *fp)
+{
+       printf("PC: %08lx\n", fp->pc);
+       printf("SEQSTAT: %08lx    SP: %08lx\n", (long) fp->seqstat,
+               (long) fp);
+       printf("R0: %08lx    R1: %08lx    R2: %08lx    R3: %08lx\n",
+               fp->r0, fp->r1, fp->r2, fp->r3);
+       printf("R4: %08lx    R5: %08lx    R6: %08lx    R7: %08lx\n",
+               fp->r4, fp->r5, fp->r6, fp->r7);
+       printf("P0: %08lx    P1: %08lx    P2: %08lx    P3: %08lx\n",
+               fp->p0, fp->p1, fp->p2, fp->p3);
+       printf("P4: %08lx    P5: %08lx    FP: %08lx\n", fp->p4, fp->p5,
+               fp->fp);
+       printf("A0.w: %08lx    A0.x: %08lx    A1.w: %08lx    A1.x: %08lx\n",
+               fp->a0w, fp->a0x, fp->a1w, fp->a1x);
+       printf("\n");
+}

diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index 689e775c938160a7747d2b51f3d1adb37275ad33..c83f0bb6cf3cfc2cf1e6d6f0f84533c824c15228 100644 (file)
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -36,6 +36,8 @@
 #include <asm/pci.h>
 #include <asm/ic/sc520.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * utility functions for boards based on the AMD sc520
  *
@@ -93,8 +95,6 @@ u32 read_mmcr_long(u16 mmcr)
 
 void init_sc520(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Set the UARTxCTL register at it's slower,
         * baud clock giving us a 1.8432 MHz reference
         */
@@ -139,7 +139,6 @@ void init_sc520(void)
 
 unsigned long init_sc520_dram(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        bd_t *bd = gd->bd;
 
        u32 dram_present=0;

diff --git a/cpu/i386/serial.c b/cpu/i386/serial.c
index db13008ba5b4adf5220576dfde94ee6e97ede36f..e7299a7ebb0ea1d44955edcfa591633690935e6d 100644 (file)
--- a/cpu/i386/serial.c
+++ b/cpu/i386/serial.c
@@ -55,6 +55,8 @@
 #include <malloc.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define UART_RBR    0x00
 #define UART_THR    0x00
 #define UART_IER    0x01
@@ -126,13 +128,9 @@ static int serial_div(int baudrate)
 
 int serial_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile char val;
-
        int bdiv = serial_div(gd->baudrate);
 
-
        outb(0x80, UART0_BASE + UART_LCR);      /* set DLAB bit */
        outb(bdiv, UART0_BASE + UART_DLL);      /* set baudrate divisor */
        outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */
@@ -150,8 +148,6 @@ int serial_init(void)
 
 void serial_setbrg(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned short bdiv;
 
        bdiv = serial_div(gd->baudrate);
@@ -410,8 +406,6 @@ int serial_buffered_tstc(void)
 #if (CONFIG_KGDB_SER_INDEX & 2)
 void kgdb_serial_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile char val;
        bdiv = serial_div (CONFIG_KGDB_BAUDRATE);
 

diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c
index 9383473141a536b2d78a523f7a694d914db36b1d..2a2bd504dc468869ee32a018c4935ff98005a5f7 100644 (file)
--- a/cpu/ixp/cpu.c
+++ b/cpu/ixp/cpu.c
@@ -34,14 +34,16 @@
 #include <command.h>
 #include <asm/arch/ixp425.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 int cpu_init (void)
 {
        /*
         * setup up stacks if necessary
         */
 #ifdef CONFIG_USE_IRQ
-       DECLARE_GLOBAL_DATA_PTR;
-
        IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
        FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif

diff --git a/cpu/ixp/serial.c b/cpu/ixp/serial.c
index aea0cf86966dba31f4ad4bc46a400649bfea255e..2015958571423aa5705e46b8525bcc2309b841c1 100644 (file)
--- a/cpu/ixp/serial.c
+++ b/cpu/ixp/serial.c
@@ -31,10 +31,10 @@
 #include <common.h>
 #include <asm/arch/ixp425.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned int quot = 0;
        int uart = CFG_IXP425_CONSOLE;
 

diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c
index 718f253471d40e30935b994b631eececc4e6e523..578eb73e8e014e74c54ca7c25d8417fe5e7853cc 100644 (file)
--- a/cpu/lh7a40x/cpu.c
+++ b/cpu/lh7a40x/cpu.c
@@ -33,6 +33,10 @@
 #include <command.h>
 #include <arm920t.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1 (void)
 {
@@ -90,8 +94,6 @@ int cpu_init (void)
         * setup up stacks if necessary
         */
 #ifdef CONFIG_USE_IRQ
-       DECLARE_GLOBAL_DATA_PTR;
-
        IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
        FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif

diff --git a/cpu/lh7a40x/serial.c b/cpu/lh7a40x/serial.c
index ff5b2d8c084cc21f9689760ef9b6ea2947e66fce..2132c052a4e1a3b372751a91c1793fa2ba51dc80 100644 (file)
--- a/cpu/lh7a40x/serial.c
+++ b/cpu/lh7a40x/serial.c
@@ -21,6 +21,8 @@
 #include <common.h>
 #include <lh7a40x.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_CONSOLE_UART1)
 # define UART_CONSOLE 1
 #elif defined(CONFIG_CONSOLE_UART2)
@@ -33,7 +35,6 @@
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
        int i;
        unsigned int reg = 0;

diff --git a/cpu/mcf52x2/serial.c b/cpu/mcf52x2/serial.c
index 641f0d9ef954f56acec475d4b2229dd7c07f6a92..8fbfad47bfbe67620871cf012b776d9bf9be8296 100644 (file)
--- a/cpu/mcf52x2/serial.c
+++ b/cpu/mcf52x2/serial.c
@@ -42,6 +42,8 @@
 #include <asm/m5249.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_M5249
 #define DoubleClock(a) ((double)(CFG_CLK/2) / 32.0 / (double)(a))
 #else
@@ -140,12 +142,10 @@ int rs_get_char(void)
 }
 
 void serial_setbrg(void) {
-       DECLARE_GLOBAL_DATA_PTR;
        rs_serial_setbaudrate(0,gd->bd->bi_baudrate);
 }
 
 int serial_init(void) {
-       DECLARE_GLOBAL_DATA_PTR;
        rs_serial_init(0,gd->baudrate);
        return 0;
 }

diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index 519c99258132f97e192c6df8eb4308781ff0dcb6..ac860b2c673c31fce5c6e31631d0b7876ca241e9 100644 (file)
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -24,13 +24,13 @@
 #include <common.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * get_clocks() fills in gd->cpu_clock and gd->bus_clk
  */
 int get_clocks (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->cpu_clk = CFG_CLK;
 #ifdef CONFIG_M5249
        gd->bus_clk = gd->cpu_clk / 2;

diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c
index 9ce9b353978b8c9d26fcc9e2973e166c1135ee85..078e8328b625d4262632f3a2c9803775dfc7dffe 100644 (file)
--- a/cpu/mips/au1x00_eth.c
+++ b/cpu/mips/au1x00_eth.c
@@ -224,10 +224,14 @@ static void au1x00_halt(struct eth_device* dev){
 int au1x00_enet_initialize(bd_t *bis){
        struct eth_device* dev;
 
-       dev = (struct eth_device*) malloc(sizeof *dev);
+       if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
+               puts ("malloc failed\n");
+               return 0;
+       }
+
        memset(dev, 0, sizeof *dev);
 
-       sprintf(dev->name, "Au1X00 ETHERNET");
+       sprintf(dev->name, "Au1X00 ethernet");
        dev->iobase = 0;
        dev->priv   = 0;
        dev->init   = au1x00_init;

diff --git a/cpu/mpc5xx/cpu.c b/cpu/mpc5xx/cpu.c
index 0c22a31f0de433b44d69814c79321a8e2e78c1cc..4bef90c48ad97755ce644736a31d1054df0baf6f 100644 (file)
--- a/cpu/mpc5xx/cpu.c
+++ b/cpu/mpc5xx/cpu.c
@@ -34,6 +34,7 @@
 #include <command.h>
 #include <mpc5xx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 #if (defined(CONFIG_MPC555))
 #  define      ID_STR  "MPC555/556"
@@ -62,8 +63,6 @@ static int check_cpu_version (long clock, uint pvr, uint immr)
  */
 int checkcpu (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong clock = gd->cpu_clk;
        uint immr = get_immr (0);       /* Return full IMMR contents */
        uint pvr = get_pvr ();          /* Retrieve PVR register */
@@ -104,7 +103,6 @@ void reset_5xx_watchdog (volatile immap_t * immr)
  */
 unsigned long get_tbclk (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        volatile immap_t *immr = (volatile immap_t *) CFG_IMMR;
        ulong oscclk, factor;
 

diff --git a/cpu/mpc5xx/serial.c b/cpu/mpc5xx/serial.c
index 48687829e5aaa067e21115f84914c51bd6992c7a..ac5556f05cd5837f86acda0bdf8bf534c34e0dfb 100644 (file)
--- a/cpu/mpc5xx/serial.c
+++ b/cpu/mpc5xx/serial.c
@@ -34,6 +34,7 @@
 #include <command.h>
 #include <mpc5xx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Local function prototypes
@@ -128,7 +129,6 @@ int serial_tstc()
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        volatile immap_t *immr = (immap_t *)CFG_IMMR;
        short scxbr;
 

diff --git a/cpu/mpc5xx/speed.c b/cpu/mpc5xx/speed.c
index f6097f5c1347265dfa0373b21b6f8e46b4a731a9..6a1fa155e298ab24db7322eb605007e54d35213a 100644 (file)
--- a/cpu/mpc5xx/speed.c
+++ b/cpu/mpc5xx/speed.c
@@ -31,12 +31,13 @@
 #include <mpc5xx.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Get cpu and bus clock
  */
 int get_clocks (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        volatile immap_t *immr = (immap_t *) CFG_IMMR;
 
 #ifndef        CONFIG_5xx_GCLK_FREQ

diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c
index 2d695d12eb1025e337d07e96de9219cf0e61632b..6b6f8282cf36e8515b0ab13cdd94ee7544f9b12e 100644 (file)
--- a/cpu/mpc5xxx/cpu.c
+++ b/cpu/mpc5xxx/cpu.c
@@ -31,14 +31,14 @@
 #include <mpc5xxx.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkcpu (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong clock = gd->cpu_clk;
        char buf[32];
 #ifndef CONFIG_MGT5100
-       uint svr;
+       uint svr, pvr;
 #endif
 
        puts ("CPU:   ");
@@ -47,7 +47,8 @@ int checkcpu (void)
        puts   (CPU_ID_STR);
        printf (" (JTAG ID %08lx)", *(vu_long *)MPC5XXX_CDM_JTAGID);
 #else
-       svr = get_svr ();
+       svr = get_svr();
+       pvr = get_pvr();
        switch (SVR_VER (svr)) {
        case SVR_MPC5200:
                printf ("MPC5200");
@@ -57,11 +58,10 @@ int checkcpu (void)
                break;
        }
 
-       printf (" v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr));
+       printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),
+               PVR_MAJ(pvr), PVR_MIN(pvr));
 #endif
-
        printf (" at %s MHz\n", strmhz (buf, clock));
-
        return 0;
 }
 
@@ -94,8 +94,6 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
  */
 unsigned long get_tbclk (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong tbclk;
 
        tbclk = (gd->bus_clk + 3L) / 4L;

diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c
index 3df005009ebca12113549a355db5c983e2d11f91..b7e00b3e244e4147be3811447fa312348419c078 100644 (file)
--- a/cpu/mpc5xxx/cpu_init.c
+++ b/cpu/mpc5xxx/cpu_init.c
@@ -24,6 +24,8 @@
 #include <common.h>
 #include <mpc5xxx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Breath some life into the CPU...
  *
@@ -32,8 +34,6 @@
  */
 void cpu_init_f (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long addecr = (1 << 25); /* Boot_CS */
 #if defined(CFG_RAMBOOT) && defined(CONFIG_MGT5100)
        addecr |= (1 << 22); /* SDRAM enable */
@@ -152,6 +152,10 @@ void cpu_init_f (void)
        /* enable timebase */
        *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13);
 
+       /* Enable snooping for RAM */
+       *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
+       *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d;
+
 # if defined(CFG_IPBSPEED_133)
        /* Motorola reports IPB should better run at 133 MHz. */
        *(vu_long *)MPC5XXX_ADDECR |= 1;

diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index 86c8ce68799b0ee53f91f35f7da3b67404cb1911..19737ce868dd32a84b266ce04416fdd86ced1674 100644 (file)
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -14,6 +14,8 @@
 #include "sdma.h"
 #include "fec.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* #define DEBUG       0x28 */
 
 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
@@ -242,7 +244,6 @@ static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
 /********************************************************************/
 static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
        struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
 
@@ -393,7 +394,6 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 /********************************************************************/
 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
        const uint8 phyAddr = CONFIG_PHY_ADDR;  /* Only one PHY */
 
@@ -880,8 +880,9 @@ int mpc5xxx_fec_initialize(bd_t * bis)
        fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
 #if defined(CONFIG_CANMB)   || defined(CONFIG_HMI1001) || \
     defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
+    defined(CONFIG_MCC200)  || defined(CONFIG_O2DNT)   || \
     defined(CONFIG_PM520)   || defined(CONFIG_TOP5200) || \
-    defined(CONFIG_TQM5200) || defined(CONFIG_O2DNT)
+    defined(CONFIG_TQM5200)
 # ifndef CONFIG_FEC_10MBIT
        fec->xcv_type = MII100;
 # else

diff --git a/cpu/mpc5xxx/i2c.c b/cpu/mpc5xxx/i2c.c
index 044db46f6fb43676627c835ba844871a6e5a89d7..0f02e78a3bd3e25d04459b50c0b36c5d0e79cdc1 100644 (file)
--- a/cpu/mpc5xxx/i2c.c
+++ b/cpu/mpc5xxx/i2c.c
@@ -23,6 +23,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_HARD_I2C
 
 #include <mpc5xxx.h>
@@ -228,7 +230,6 @@ void i2c_init(int speed, int saddr)
 
 static int mpc_get_fdr(int speed)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        static int fdr = -1;
 
        if (fdr == -1) {

diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c
index 1af794c6ecac6ae8bdeb1ee8bbf4d7e688306ca6..29b99f6b15ddada936f3b3226dfdddf0e2d5098d 100644 (file)
--- a/cpu/mpc5xxx/ide.c
+++ b/cpu/mpc5xxx/ide.c
@@ -27,6 +27,8 @@
 #ifdef CFG_CMD_IDE
 #include <mpc5xxx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define CALC_TIMING(t) (t + period - 1) / period
 
 #ifdef CONFIG_IDE_RESET
@@ -35,7 +37,6 @@ extern void init_ide_reset (void);
 
 int ide_preinit (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        long period, t0, t1, t2_8, t2_16, t4, ta;
        vu_long reg;
        struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA;

diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index 1d903459e0a746a39a9535cd3b13c830b61bf8a1..2f01d5ce996279e675a7e3398f4db5d8fac427f7 100644 (file)
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -135,10 +135,6 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
        *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
        *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
 
-       /* Enable snooping for RAM */
-       *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
-       *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS | 0x1d;
-
        /* Park XLB on PCI */
        *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
        *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);

diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c
index 91e1def98cb3c33670126932230839446732680c..cacb9f057335c855145d185dab1e0cf7e3a9811e 100644 (file)
--- a/cpu/mpc5xxx/serial.c
+++ b/cpu/mpc5xxx/serial.c
@@ -33,6 +33,8 @@
 #include <common.h>
 #include <mpc5xxx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_PSC_CONSOLE)
 
 #if CONFIG_PSC_CONSOLE == 1
@@ -55,8 +57,6 @@
 
 int serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
        unsigned long baseclk;
        int div;
@@ -146,8 +146,6 @@ serial_tstc(void)
 void
 serial_setbrg(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
        unsigned long baseclk, div;
 

diff --git a/cpu/mpc5xxx/speed.c b/cpu/mpc5xxx/speed.c
index 4f4e814e94d64b3b18a070a819d4df1c982135b8..7847adcefa40f4258e0e846ff7ed4d1f143b38d6 100644 (file)
--- a/cpu/mpc5xxx/speed.c
+++ b/cpu/mpc5xxx/speed.c
@@ -25,6 +25,8 @@
 #include <mpc5xxx.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 /* Bus-to-Core Multipliers */
@@ -43,8 +45,6 @@ static int bus2core[] = {
 
 int get_clocks (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong val, vco;
 
 #if !defined(CFG_MPC5XXX_CLKIN)
@@ -81,8 +81,6 @@ int get_clocks (void)
 
 int prt_mpc5xxx_clks (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        printf("       Bus %ld MHz, IPB %ld MHz, PCI %ld MHz\n",
                        gd->bus_clk / 1000000, gd->ipb_clk / 1000000,
                        gd->pci_clk / 1000000);

diff --git a/cpu/mpc8220/cpu.c b/cpu/mpc8220/cpu.c
index 0cfe8089b8a8abb101cce2875f396a369a6f2183..be274cde9e0dc31200bb19dad9fbf755fda2a3cb 100644 (file)
--- a/cpu/mpc8220/cpu.c
+++ b/cpu/mpc8220/cpu.c
@@ -31,10 +31,10 @@
 #include <mpc8220.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkcpu (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong clock = gd->cpu_clk;
        char buf[32];
 
@@ -81,8 +81,6 @@ int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
  */
 unsigned long get_tbclk (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong tbclk;
 
        tbclk = (gd->bus_clk + 3L) / 4L;

diff --git a/cpu/mpc8220/cpu_init.c b/cpu/mpc8220/cpu_init.c
index 8c358a870cef1250c39ec8a5487859c71a2af182..3cf5f66a13006554524e95601569d557489a8803 100644 (file)
--- a/cpu/mpc8220/cpu_init.c
+++ b/cpu/mpc8220/cpu_init.c
@@ -24,6 +24,8 @@
 #include <common.h>
 #include <mpc8220.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Breath some life into the CPU...
  *
@@ -32,8 +34,6 @@
  */
 void cpu_init_f (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile flexbus8220_t *flexbus = (volatile flexbus8220_t *) MMAP_FB;
        volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG;
        volatile xlbarb8220_t *xlbarb = (volatile xlbarb8220_t *) MMAP_XLBARB;

diff --git a/cpu/mpc8220/dramSetup.c b/cpu/mpc8220/dramSetup.c
index 1d0d384722e8c0aaea87ee7b4a39ba91f2039ad4..08e3172f2bf2a140e1c36f4672c7265d5f7f95f1 100644 (file)
--- a/cpu/mpc8220/dramSetup.c
+++ b/cpu/mpc8220/dramSetup.c
@@ -32,6 +32,8 @@ characteristics to initialize the dram on MPC8220
 #include "i2cCore.h"
 #include "dramSetup.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define SPD_SIZE       CFG_SDRAM_SPD_SIZE
 #define DRAM_SPD       (CFG_SDRAM_SPD_I2C_ADDR)<<1     /* on Board SPD eeprom */
 #define TOTAL_BANK     CFG_SDRAM_TOTAL_BANKS
@@ -91,8 +93,6 @@ int spd_readbyte (volatile i2c8220_t * pi2c, u8 * readb, int *index)
 
 int readSpdData (u8 * spdData)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile i2c8220_t *pi2cReg;
        volatile pcfg8220_t *pcfg;
        u8 slvAdr = DRAM_SPD;
@@ -403,8 +403,6 @@ u8 checkMuxSetting (u8 rows, u8 columns)
 
 u32 dramSetup (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        draminfo_t DramInfo[TOTAL_BANK];
        draminfo_t *pDramInfo;
        u32 size, temp, cfg_value, mode_value, refresh;

diff --git a/cpu/mpc8220/i2c.c b/cpu/mpc8220/i2c.c
index 62f7c0f5d330df815284ca99031017880c66273c..d67936dc31c2f3b7a11242f506823015d134115b 100644 (file)
--- a/cpu/mpc8220/i2c.c
+++ b/cpu/mpc8220/i2c.c
@@ -23,6 +23,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_HARD_I2C
 
 #include <mpc8220.h>
@@ -235,7 +237,6 @@ void i2c_init (int speed, int saddr)
 
 static int mpc_get_fdr (int speed)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        static int fdr = -1;
 
        if (fdr == -1) {

diff --git a/cpu/mpc8220/speed.c b/cpu/mpc8220/speed.c
index 8346efe12e9f1ac58a7f08814fe13c1e62867f07..200a762711ec25c40a94eca8a1f1ea07835d5121 100644 (file)
--- a/cpu/mpc8220/speed.c
+++ b/cpu/mpc8220/speed.c
@@ -25,6 +25,8 @@
 #include <mpc8220.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 typedef struct pllmultiplier {
        u8 hid1;
        int multi;
@@ -39,8 +41,6 @@ typedef struct pllmultiplier {
 
 int get_clocks (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        pllcfg_t bus2core[] = {
                {0x02, 2, 8},   /* 1 */
                {0x01, 2, 4},
@@ -109,8 +109,6 @@ int get_clocks (void)
 
 int prt_mpc8220_clks (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        printf ("       Bus %ld MHz, CPU %ld MHz, PCI %ld MHz, VCO %ld MHz\n",
                gd->bus_clk / 1000000, gd->cpu_clk / 1000000,
                gd->pci_clk / 1000000, gd->vco_clk / 1000000);

diff --git a/cpu/mpc8220/uart.c b/cpu/mpc8220/uart.c
index 5f54aac16ef3d88c5d4f1d9c50047ac8919e2b67..0c4b536b48e7a09bdce55741abf20ba20b339a5a 100644 (file)
--- a/cpu/mpc8220/uart.c
+++ b/cpu/mpc8220/uart.c
@@ -30,12 +30,13 @@
 #include <common.h>
 #include <mpc8220.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PSC_BASE   MMAP_PSC1
 
 #if defined(CONFIG_PSC_CONSOLE)
 int serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
        u32 counter;
 
@@ -106,8 +107,6 @@ int serial_tstc (void)
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
        u32 counter;
 

diff --git a/cpu/mpc824x/cpu.c b/cpu/mpc824x/cpu.c
index 312dfe22966abf1e7cbf39d25194285494f0c438..0a45cc8419f610544969abd7600d85f033d09c8e 100644 (file)
--- a/cpu/mpc824x/cpu.c
+++ b/cpu/mpc824x/cpu.c
@@ -26,10 +26,10 @@
 #include <common.h>
 #include <command.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkcpu (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned int pvr = get_pvr ();
        unsigned int version = pvr >> 16;
        unsigned char revision;

diff --git a/cpu/mpc824x/speed.c b/cpu/mpc824x/speed.c
index a37a087af12ab2bb1131e8c38ff60470b43c372d..fdcb9723cbd8817675d700e266a8812e50a5b6b9 100644 (file)
--- a/cpu/mpc824x/speed.c
+++ b/cpu/mpc824x/speed.c
@@ -29,6 +29,8 @@
 #include <mpc824x.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 /* NOTE: This describes the proper use of this file.
  *
@@ -107,8 +109,6 @@ short pllratio_to_factor[] = {
 /* compute the CPU and memory bus clock frequencies */
 int get_clocks (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        uint hid1 = mfspr(HID1);
        hid1 = (hid1 >> (32-5)) & 0x1f;
        gd->cpu_clk = (pllratio_to_factor[hid1] * get_bus_freq(0) + 5)

diff --git a/cpu/mpc8260/commproc.c b/cpu/mpc8260/commproc.c
index e5c5fcf27b97df40f76af5cd5496fa645d42ef88..8777e773698c0addaf5681e98f603f22c2e99b13 100644 (file)
--- a/cpu/mpc8260/commproc.c
+++ b/cpu/mpc8260/commproc.c
@@ -20,11 +20,11 @@
 #include <common.h>
 #include <asm/cpm_8260.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void
 m8260_cpm_reset(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *)CFG_IMMR;
        volatile ulong count;
 
@@ -54,8 +54,6 @@ m8260_cpm_reset(void)
 uint
 m8260_cpm_dpalloc(uint size, uint align)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *)CFG_IMMR;
        uint    retloc;
        uint    align_mask, off;
@@ -112,8 +110,6 @@ m8260_cpm_hostalloc(uint size, uint align)
 void
 m8260_cpm_setbrg(uint brg, uint rate)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *)CFG_IMMR;
        volatile uint   *bp;
        uint cd = BRG_UART_CLK / rate;
@@ -137,8 +133,6 @@ m8260_cpm_setbrg(uint brg, uint rate)
 void
 m8260_cpm_fastbrg(uint brg, uint rate, int div16)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *)CFG_IMMR;
        volatile uint   *bp;
 

diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c
index 5d979330a3da7fd9713a0f4166188788e85b2b77..4f23012b729420ba74ce64dc4cb65d24cb73385e 100644 (file)
--- a/cpu/mpc8260/cpu.c
+++ b/cpu/mpc8260/cpu.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2000-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -47,10 +47,10 @@
 #include <asm/processor.h>
 #include <asm/cpm_8260.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkcpu (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immap = (immap_t *) CFG_IMMR;
        ulong clock = gd->cpu_clk;
        uint pvr = get_pvr ();
@@ -264,8 +264,6 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
  */
 unsigned long get_tbclk (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong tbclk;
 
        tbclk = (gd->bus_clk + 3L) / 4L;

diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c
index babcce4e9b104c6604843a3d28e0fc01acd38721..640026be5ac5d3c7aeec413de63f2a6ca87c4f9c 100644 (file)
--- a/cpu/mpc8260/cpu_init.c
+++ b/cpu/mpc8260/cpu_init.c
@@ -26,6 +26,8 @@
 #include <asm/cpm_8260.h>
 #include <ioports.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static void config_8260_ioports (volatile immap_t * immr)
 {
        int portnum;
@@ -97,7 +99,6 @@ static void config_8260_ioports (volatile immap_t * immr)
  */
 void cpu_init_f (volatile immap_t * immr)
 {
-       DECLARE_GLOBAL_DATA_PTR;
 #if !defined(CONFIG_COGENT)            /* done in start.S for the cogent */
        uint sccr;
 #endif
@@ -222,8 +223,6 @@ void cpu_init_f (volatile immap_t * immr)
  */
 int cpu_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base;
 
        immr->im_cpm.cp_rccr = CFG_RCCR;
@@ -236,8 +235,6 @@ int cpu_init_r (void)
  */
 int prt_8260_rsr (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        static struct {
                ulong mask;
                char *desc;

diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c
index ed3515fcf316bde3fd9bba21d398512ff518de9f..584c40f17a174ace235fe4178787013589e98e17 100644 (file)
--- a/cpu/mpc8260/ether_fcc.c
+++ b/cpu/mpc8260/ether_fcc.c
@@ -51,6 +51,8 @@
 #include <miiphy.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
        defined(CONFIG_NET_MULTI)
 
@@ -644,8 +646,6 @@ swap16 (unsigned short x)
 void
 eth_loopback_test (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *)CFG_IMMR;
        volatile cpm8260_t *cp = &(immr->im_cpm);
        int c, nclosed;

diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c
index ea97ab85fbc091944b6c4a7707dfa253778751d5..34bd3897f6d8fe302614dd002426345d37bac081 100644 (file)
--- a/cpu/mpc8260/i2c.c
+++ b/cpu/mpc8260/i2c.c
@@ -34,6 +34,8 @@
 /* define to enable debug messages */
 #undef  DEBUG_I2C
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* uSec to wait between polls of the i2c */
 #define DELAY_US       100
 /* uSec to wait for the CPM to start processing the buffer */
@@ -213,8 +215,6 @@ static int i2c_setrate(int hz, int speed)
 
 void i2c_init(int speed, int slaveadd)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immap = (immap_t *)CFG_IMMR ;
        volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
        volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;

diff --git a/cpu/mpc8260/interrupts.c b/cpu/mpc8260/interrupts.c
index b2e4d839245813d9b8a4759ff70578ed724eb10e..56e9a721373f3245b3409d9ef001575e14e756e2 100644 (file)
--- a/cpu/mpc8260/interrupts.c
+++ b/cpu/mpc8260/interrupts.c
@@ -29,6 +29,8 @@
 #include <mpc8260_irq.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /****************************************************************************/
 
 struct irq_action {
@@ -140,8 +142,6 @@ static int m8260_get_irq (struct pt_regs *regs)
 
 int interrupt_init_cpu (unsigned *decrementer_count)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *) CFG_IMMR;
 
        *decrementer_count = (gd->bus_clk / 4) / CFG_HZ;

diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index 44576deb61d8a8ed84b8271a3640380473210d75..ea5514fb123414df4dea295c41fde13d98b84b45 100644 (file)
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -33,6 +33,11 @@
 #include <mpc8260.h>
 #include <asm/m8260_pci.h>
 #include <asm/io.h>
+
+#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /*
  *   Local->PCI map (from CPU)                            controlled by
  *   MPC826x master window
@@ -234,9 +239,6 @@ static inline void pci_outl (u32 addr, u32 data)
 
 void pci_mpc8250_init (struct pci_controller *hose)
 {
-#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
-       DECLARE_GLOBAL_DATA_PTR;
-#endif
        u16 tempShort;
 
        volatile immap_t *immap = (immap_t *) CFG_IMMR;

diff --git a/cpu/mpc8260/serial_scc.c b/cpu/mpc8260/serial_scc.c
index 32016f2f9108f9c45c0e2aef7b17441124d52720..3a6eaf0a6775647c5334181aa56645acf66883e3 100644 (file)
--- a/cpu/mpc8260/serial_scc.c
+++ b/cpu/mpc8260/serial_scc.c
@@ -32,6 +32,8 @@
 #include <mpc8260.h>
 #include <asm/cpm_8260.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_CONS_ON_SCC)
 
 #if CONFIG_CONS_INDEX == 1     /* Console on SCC1 */
@@ -181,8 +183,6 @@ int serial_init (void)
 void
 serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
 #if defined(CONFIG_CONS_USE_EXTC)
        m8260_cpm_extcbrg(SCC_INDEX, gd->baudrate,
                CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);

diff --git a/cpu/mpc8260/serial_smc.c b/cpu/mpc8260/serial_smc.c
index b486f8385e3cd38d0d1046f261556d78c8d024fd..f3dffeb11993d81c70aeccb0199b841a75d3613a 100644 (file)
--- a/cpu/mpc8260/serial_smc.c
+++ b/cpu/mpc8260/serial_smc.c
@@ -34,6 +34,8 @@
 #include <mpc8260.h>
 #include <asm/cpm_8260.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_CONS_ON_SMC)
 
 #if CONFIG_CONS_INDEX == 1     /* Console on SMC1 */
@@ -170,8 +172,6 @@ int serial_init (void)
 void
 serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
 #if defined(CONFIG_CONS_USE_EXTC)
        m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate,
                CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);

diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c
index a761a178bc12e179fe32fde00af597361a8de839..360404f0cfd444807fe1a98a5c4d23f72fa948d9 100644 (file)
--- a/cpu/mpc8260/speed.c
+++ b/cpu/mpc8260/speed.c
@@ -25,6 +25,8 @@
 #include <mpc8260.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ------------------------------------------------------------------------- */
 
 /* Bus-to-Core Multiplier */
@@ -101,8 +103,6 @@ corecnf_t corecnf_tab[] = {
 
 int get_clocks (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immap = (immap_t *) CFG_IMMR;
        ulong clkin;
        ulong sccr, dfbrg;
@@ -159,11 +159,9 @@ int get_clocks (void)
 
 int prt_8260_clks (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immap = (immap_t *) CFG_IMMR;
        ulong sccr, dfbrg;
-       ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
+       ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf, pcidf;
        corecnf_t *cp;
 
        sccr = immap->im_clkrst.car_sccr;
@@ -175,6 +173,7 @@ int prt_8260_clks (void)
        cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
        plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
        pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
+       pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT;
 
        cp = &corecnf_tab[corecnf];
 
@@ -204,8 +203,9 @@ int prt_8260_clks (void)
                        cp->vco_div, cp->freq_60x, cp->freq_core);
 
        printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
-                       "plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf,
-                       pllmf);
+               "plldf %ld, pllmf %ld, pcidf %ld\n",
+                       dfbrg, corecnf, busdf, cpmdf,
+                       plldf, pllmf, pcidf);
 
        printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
                        gd->vco_out, gd->scc_clk, gd->brg_clk);
@@ -215,9 +215,20 @@ int prt_8260_clks (void)
 
        if (sccr & SCCR_PCI_MODE) {
                uint pci_div;
-
-               pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
-                       ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
+               uint pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT;
+
+               if (sccr & SCCR_PCI_MODCK) {
+                       pci_div = 2;
+                       if (pcidf == 9) {
+                               pci_div *= 5;
+                       } else if (pcidf == 0xB) {
+                               pci_div *= 6;
+                       } else {
+                               pci_div *= (pcidf + 1);
+                       }
+               } else {
+                       pci_div = pcidf + 1;
+               }
 
                printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div);
        }
@@ -225,5 +236,3 @@ int prt_8260_clks (void)
 
        return (0);
 }
-
-/* ------------------------------------------------------------------------- */

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 8c9b515fa5c72aa3346e1c282010f8b2e5c1aa9c..20bba6c66b668995a5ef386e3b6df9ad63de37b0 100644 (file)
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -35,12 +35,14 @@
 #include <watchdog.h>
 #include <command.h>
 #include <mpc83xx.h>
+#include <ft_build.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 
 int checkcpu(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        ulong clock = gd->cpu_clk;
        u32 pvr = get_pvr();
        char buf[32];
@@ -92,6 +94,8 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
        /* enable Reset Control Reg */
        immap->reset.rpr = 0x52535445;
+       __asm__ __volatile__ ("sync");
+       __asm__ __volatile__ ("isync");
 
        /* confirm Reset Control Reg is enabled */
        while(!((immap->reset.rcer) & RCER_CRE));
@@ -135,8 +139,6 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 unsigned long get_tbclk(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong tbclk;
 
        tbclk = (gd->bus_clk + 3L) / 4L;
@@ -151,3 +153,125 @@ void watchdog_reset (void)
        hang();         /* FIXME: implement watchdog_reset()? */
 }
 #endif /* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_OF_FLAT_TREE)
+void
+ft_cpu_setup(void *blob, bd_t *bd)
+{
+       u32 *p;
+       int len;
+       ulong clock;
+
+       clock = bd->bi_busfreq;
+       p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
+       if (p != NULL)
+               *p = cpu_to_be32(clock);
+
+       p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
+       if (p != NULL)
+               *p = cpu_to_be32(clock);
+
+       p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
+       if (p != NULL)
+               *p = cpu_to_be32(clock);
+
+       p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
+       if (p != NULL)
+               *p = cpu_to_be32(clock);
+
+#ifdef CONFIG_MPC83XX_TSEC1
+       p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len);
+               memcpy(p, bd->bi_enetaddr, 6);
+#endif
+
+#ifdef CONFIG_MPC83XX_TSEC2
+       p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len);
+               memcpy(p, bd->bi_enet1addr, 6);
+#endif
+}
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+void dma_init(void)
+{
+       volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+       volatile dma8349_t *dma = &immap->dma;
+       volatile u32 status = swab32(dma->dmasr0);
+       volatile u32 dmamr0 = swab32(dma->dmamr0);
+
+       debug("DMA-init\n");
+
+       /* initialize DMASARn, DMADAR and DMAABCRn */
+       dma->dmadar0 = (u32)0;
+       dma->dmasar0 = (u32)0;
+       dma->dmabcr0 = 0;
+
+       __asm__ __volatile__ ("sync");
+       __asm__ __volatile__ ("isync");
+
+       /* clear CS bit */
+       dmamr0 &= ~DMA_CHANNEL_START;
+       dma->dmamr0 = swab32(dmamr0);
+       __asm__ __volatile__ ("sync");
+       __asm__ __volatile__ ("isync");
+
+       /* while the channel is busy, spin */
+       while(status & DMA_CHANNEL_BUSY) {
+               status = swab32(dma->dmasr0);
+       }
+
+       debug("DMA-init end\n");
+}
+
+uint dma_check(void)
+{
+       volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+       volatile dma8349_t *dma = &immap->dma;
+       volatile u32 status = swab32(dma->dmasr0);
+       volatile u32 byte_count = swab32(dma->dmabcr0);
+
+       /* while the channel is busy, spin */
+       while (status & DMA_CHANNEL_BUSY) {
+               status = swab32(dma->dmasr0);
+       }
+
+       if (status & DMA_CHANNEL_TRANSFER_ERROR) {
+               printf ("DMA Error: status = %x @ %d\n", status, byte_count);
+       }
+
+       return status;
+}
+
+int dma_xfer(void *dest, u32 count, void *src)
+{
+       volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+       volatile dma8349_t *dma = &immap->dma;
+       volatile u32 dmamr0;
+
+       /* initialize DMASARn, DMADAR and DMAABCRn */
+       dma->dmadar0 = swab32((u32)dest);
+       dma->dmasar0 = swab32((u32)src);
+       dma->dmabcr0 = swab32(count);
+
+       __asm__ __volatile__ ("sync");
+       __asm__ __volatile__ ("isync");
+
+       /* init direct transfer, clear CS bit */
+       dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
+                       DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
+                       DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
+
+       dma->dmamr0 = swab32(dmamr0);
+
+       __asm__ __volatile__ ("sync");
+       __asm__ __volatile__ ("isync");
+
+       /* set CS to start DMA transfer */
+       dmamr0 |= DMA_CHANNEL_START;
+       dma->dmamr0 = swab32(dmamr0);
+       __asm__ __volatile__ ("sync");
+       __asm__ __volatile__ ("isync");
+
+       return ((int)dma_check());
+}
+#endif /*CONFIG_DDR_ECC*/

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index dcb34457b1096e0f39752096c56c4d0084262f56..6ed0992c070bf1bb9676bc6602773399d50e73ee 100644 (file)
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -29,6 +29,8 @@
 #include <mpc83xx.h>
 #include <ioports.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Breathe some life into the CPU...
  *
@@ -38,8 +40,6 @@
  */
 void cpu_init_f (volatile immap_t * im)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Pointer is writable since we allocated a register for it */
        gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 
@@ -63,8 +63,12 @@ void cpu_init_f (volatile immap_t * im)
        im->sysconf.spcr |= SPCR_TBEN;
 
        /* System General Purpose Register */
-       im->sysconf.sicrh = SICRH_TSOBI1;
-       im->sysconf.sicrl = SICRL_LDP_A;
+#ifdef CFG_SICRH
+       im->sysconf.sicrh = CFG_SICRH;
+#endif
+#ifdef CFG_SICRL
+       im->sysconf.sicrl = CFG_SICRL;
+#endif
 
        /*
         * Memory Controller:
@@ -87,69 +91,70 @@ void cpu_init_f (volatile immap_t * im)
 #error         CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
 #endif
 
-#if defined(CFG_BR1_PRELIM)  \
-       && defined(CFG_OR1_PRELIM) \
-       && defined(CFG_LBLAWBAR1_PRELIM) \
-       && defined(CFG_LBLAWAR1_PRELIM)
+#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
        im->lbus.bank[1].br = CFG_BR1_PRELIM;
        im->lbus.bank[1].or = CFG_OR1_PRELIM;
+#endif
+#if defined(CFG_LBLAWBAR1_PRELIM) && defined(CFG_LBLAWAR1_PRELIM)
        im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM;
        im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM;
 #endif
-#if defined(CFG_BR2_PRELIM)  \
-       && defined(CFG_OR2_PRELIM) \
-       && defined(CFG_LBLAWBAR2_PRELIM) \
-       && defined(CFG_LBLAWAR2_PRELIM)
+#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
        im->lbus.bank[2].br = CFG_BR2_PRELIM;
        im->lbus.bank[2].or = CFG_OR2_PRELIM;
+#endif
+#if defined(CFG_LBLAWBAR2_PRELIM) && defined(CFG_LBLAWAR2_PRELIM)
        im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM;
        im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM;
 #endif
-#if defined(CFG_BR3_PRELIM)  \
-       && defined(CFG_OR3_PRELIM) \
-       && defined(CFG_LBLAWBAR3_PRELIM) \
-       && defined(CFG_LBLAWAR3_PRELIM)
+#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
        im->lbus.bank[3].br = CFG_BR3_PRELIM;
        im->lbus.bank[3].or = CFG_OR3_PRELIM;
+#endif
+#if defined(CFG_LBLAWBAR3_PRELIM) && defined(CFG_LBLAWAR3_PRELIM)
        im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM;
        im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM;
 #endif
-#if defined(CFG_BR4_PRELIM)  \
-       && defined(CFG_OR4_PRELIM) \
-       && defined(CFG_LBLAWBAR4_PRELIM) \
-       && defined(CFG_LBLAWAR4_PRELIM)
+#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
        im->lbus.bank[4].br = CFG_BR4_PRELIM;
        im->lbus.bank[4].or = CFG_OR4_PRELIM;
+#endif
+#if defined(CFG_LBLAWBAR4_PRELIM) && defined(CFG_LBLAWAR4_PRELIM)
        im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM;
        im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM;
 #endif
-#if defined(CFG_BR5_PRELIM)  \
-       && defined(CFG_OR5_PRELIM) \
-       && defined(CFG_LBLAWBAR5_PRELIM) \
-       && defined(CFG_LBLAWAR5_PRELIM)
+#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
        im->lbus.bank[5].br = CFG_BR5_PRELIM;
        im->lbus.bank[5].or = CFG_OR5_PRELIM;
+#endif
+#if defined(CFG_LBLAWBAR5_PRELIM) && defined(CFG_LBLAWAR5_PRELIM)
        im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM;
        im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM;
 #endif
-#if defined(CFG_BR6_PRELIM)  \
-       && defined(CFG_OR6_PRELIM) \
-       && defined(CFG_LBLAWBAR6_PRELIM) \
-       && defined(CFG_LBLAWAR6_PRELIM)
+#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
        im->lbus.bank[6].br = CFG_BR6_PRELIM;
        im->lbus.bank[6].or = CFG_OR6_PRELIM;
+#endif
+#if defined(CFG_LBLAWBAR6_PRELIM) && defined(CFG_LBLAWAR6_PRELIM)
        im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM;
        im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM;
 #endif
-#if defined(CFG_BR7_PRELIM)  \
-       && defined(CFG_OR7_PRELIM) \
-       && defined(CFG_LBLAWBAR7_PRELIM) \
-       && defined(CFG_LBLAWAR7_PRELIM)
+#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
        im->lbus.bank[7].br = CFG_BR7_PRELIM;
        im->lbus.bank[7].or = CFG_OR7_PRELIM;
+#endif
+#if defined(CFG_LBLAWBAR7_PRELIM) && defined(CFG_LBLAWAR7_PRELIM)
        im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM;
        im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
 #endif
+#ifdef CFG_GPIO1_PRELIM
+       im->pgio[0].dir = CFG_GPIO1_DIR;
+       im->pgio[0].dat = CFG_GPIO1_DAT;
+#endif
+#ifdef CFG_GPIO2_PRELIM
+       im->pgio[1].dir = CFG_GPIO2_DIR;
+       im->pgio[1].dat = CFG_GPIO2_DAT;
+#endif
 }
 
 

diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c
index 53474f60c91f2b159642fa55506cf7056595c802..5a0babfcbb994348087feffad744ceff0dd1a0cd 100644 (file)
--- a/cpu/mpc83xx/interrupts.c
+++ b/cpu/mpc83xx/interrupts.c
@@ -35,6 +35,8 @@
 #include <mpc83xx.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 struct irq_action {
        interrupt_handler_t *handler;
        void *arg;
@@ -43,6 +45,14 @@ struct irq_action {
 
 int interrupt_init_cpu (unsigned *decrementer_count)
 {
+       volatile immap_t *immr = (immap_t *) CFG_IMMRBAR;
+
+       *decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
+
+       /* Enable e300 time base */
+
+       immr->sysconf.spcr |= 0x00400000;
+
        return 0;
 }
 

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 63dcd664be2adf40c3bfc6c32bbc6b0a308338a4..48624feca616cfa2a74e2aa305a083d9689a1594 100644 (file)
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -1,4 +1,7 @@
 /*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
  * Copyright 2004 Freescale Semiconductor.
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao (X.Xiao@motorola.com)
@@ -63,13 +66,42 @@ picos_to_clk(int picos)
        return clks;
 }
 
-unsigned int
-banksize(unsigned char row_dens)
+unsigned int banksize(unsigned char row_dens)
 {
        return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
 }
 
-long int spd_sdram(int(read_spd)(uint addr))
+int read_spd(uint addr)
+{
+       return ((int) addr);
+}
+
+#undef SPD_DEBUG
+#ifdef SPD_DEBUG
+static void spd_debug(spd_eeprom_t *spd)
+{
+       printf ("\nDIMM type:       %-18.18s\n", spd->mpart);
+       printf ("SPD size:        %d\n", spd->info_size);
+       printf ("EEPROM size:     %d\n", 1 << spd->chip_size);
+       printf ("Memory type:     %d\n", spd->mem_type);
+       printf ("Row addr:        %d\n", spd->nrow_addr);
+       printf ("Column addr:     %d\n", spd->ncol_addr);
+       printf ("# of rows:       %d\n", spd->nrows);
+       printf ("Row density:     %d\n", spd->row_dens);
+       printf ("# of banks:      %d\n", spd->nbanks);
+       printf ("Data width:      %d\n",
+                       256 * spd->dataw_msb + spd->dataw_lsb);
+       printf ("Chip width:      %d\n", spd->primw);
+       printf ("Refresh rate:    %02X\n", spd->refresh);
+       printf ("CAS latencies:   %02X\n", spd->cas_lat);
+       printf ("Write latencies: %02X\n", spd->write_lat);
+       printf ("tRP:             %d\n", spd->trp);
+       printf ("tRCD:            %d\n", spd->trcd);
+       printf ("\n");
+}
+#endif /* SPD_DEBUG */
+
+long int spd_sdram()
 {
        volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
        volatile ddr8349_t *ddr = &immap->ddr;
@@ -81,10 +113,10 @@ long int spd_sdram(int(read_spd)(uint addr))
        unsigned char caslat;
        unsigned int trfc, trfc_clk, trfc_low;
 
-#warning Current spd_sdram does not fit its usage... adjust implementation or API...
-
        CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
-
+#ifdef SPD_DEBUG
+       spd_debug(&spd);
+#endif
        if (spd.nrows > 2) {
                puts("DDR:Only two chip selects are supported on ADS.\n");
                return 0;
@@ -219,25 +251,31 @@ long int spd_sdram(int(read_spd)(uint addr))
         * Only DDR I is supported
         * DDR I and II have different mode-register-set definition
         */
-
-       /* burst length is always 4 */
        switch(caslat) {
        case 2:
-               ddr->sdram_mode = 0x52; /* 1.5 */
+               tmp = 0x50; /* 1.5 */
                break;
        case 3:
-               ddr->sdram_mode = 0x22; /* 2.0 */
+               tmp = 0x20; /* 2.0 */
                break;
        case 4:
-               ddr->sdram_mode = 0x62; /* 2.5 */
+               tmp = 0x60; /* 2.5 */
                break;
        case 5:
-               ddr->sdram_mode = 0x32; /* 3.0 */
+               tmp = 0x30; /* 3.0 */
                break;
        default:
                puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
                return 0;
        }
+#if defined (CONFIG_DDR_32BIT)
+       /* set burst length to 8 for 32-bit data path */
+       tmp |= 0x03;
+#else
+       /* set burst length to 4 - default for 64-bit data path */
+       tmp |= 0x02;
+#endif
+       ddr->sdram_mode = tmp;
        debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
 
        switch(spd.refresh) {
@@ -282,8 +320,13 @@ long int spd_sdram(int(read_spd)(uint addr))
         */
 #if defined(CONFIG_DDR_ECC)
        if (spd.config == 0x02) {
-               ddr->err_disable = 0x0000000d;
-               ddr->err_sbe = 0x00ff0000;
+               /* disable error detection */
+               ddr->err_disable = ~ECC_ERROR_ENABLE;
+
+               /* set single bit error threshold to maximum value,
+                * reset counter to zero */
+               ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
+                       (0 << ECC_ERROR_MAN_SBEC_SHIFT);
        }
        debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
        debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
@@ -297,7 +340,8 @@ long int spd_sdram(int(read_spd)(uint addr))
         * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
         * clock cycle after address/command
         */
-       ddr->sdram_clk_cntl = 0x82000000;
+       /*ddr->sdram_clk_cntl = 0x82000000;*/
+       ddr->sdram_clk_cntl = (DDR_SDRAM_CLK_CNTL_SS_EN|DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05);
 
        /*
         * Figure out the settings for the sdram_cfg register.  Build up
@@ -311,6 +355,10 @@ long int spd_sdram(int(read_spd)(uint addr))
         */
        tmp = 0xc2000000;
 
+#if defined (CONFIG_DDR_32BIT)
+       /* in 32-Bit mode burst len is 8 beats */
+       tmp |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
+#endif
        /*
         * sdram_cfg[3] = RD_EN - registered DIMM enable
         *   A value of 0x26 indicates micron registered DIMMS (micron.com)
@@ -324,7 +372,7 @@ long int spd_sdram(int(read_spd)(uint addr))
         * If the user wanted ECC (enabled via sdram_cfg[2])
         */
        if (spd.config == 0x02) {
-               tmp |= 0x20000000;
+               tmp |= SDRAM_CFG_ECC_EN;
        }
 #endif
 
@@ -340,37 +388,94 @@ long int spd_sdram(int(read_spd)(uint addr))
        udelay(500);
 
        debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
-
-       return memsize;/*in MBytes*/
+       return memsize; /*in MBytes*/
 }
 #endif /* CONFIG_SPD_EEPROM */
 
 
 #if defined(CONFIG_DDR_ECC)
 /*
- * Initialize all of memory for ECC, then enable errors.
+ * Use timebase counter, get_timer() is not availabe
+ * at this point of initialization yet.
  */
+static __inline__ unsigned long get_tbms (void)
+{
+       unsigned long tbl;
+       unsigned long tbu1, tbu2;
+       unsigned long ms;
+       unsigned long long tmp;
+
+       ulong tbclk = get_tbclk();
+
+       /* get the timebase ticks */
+       do {
+               asm volatile ("mftbu %0":"=r" (tbu1):);
+               asm volatile ("mftb %0":"=r" (tbl):);
+               asm volatile ("mftbu %0":"=r" (tbu2):);
+       } while (tbu1 != tbu2);
+
+       /* convert ticks to ms */
+       tmp = (unsigned long long)(tbu1);
+       tmp = (tmp << 32);
+       tmp += (unsigned long long)(tbl);
+       ms = tmp/(tbclk/1000);
+
+       return ms;
+}
 
-void
-ddr_enable_ecc(unsigned int dram_size)
+/*
+ * Initialize all of memory for ECC, then enable errors.
+ */
+/* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
+void ddr_enable_ecc(unsigned int dram_size)
 {
-#ifndef FIXME
-       uint *p = 0;
-       uint i = 0;
+       uint *p;
        volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
-       volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+       volatile ddr8349_t *ddr = &immap->ddr;
+       unsigned long t_start, t_end;
+#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+       uint i;
+#endif
+
+       debug("Initialize a Cachline in DRAM\n");
+       icache_enable();
 
+#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+       /* Initialise DMA for direct Transfers */
        dma_init();
+#endif
+
+       t_start = get_tbms();
 
-       for (*p = 0; p < (uint *)(8 * 1024); p++) {
+#if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+       debug("DDR init: Cache flush method\n");
+       for (p = 0; p < (uint *)(dram_size); p++) {
                if (((unsigned int)p & 0x1f) == 0) {
                        ppcDcbz((unsigned long) p);
                }
+
+               /* write pattern to cache and flush */
                *p = (unsigned int)0xdeadbeef;
+
                if (((unsigned int)p & 0x1c) == 0x1c) {
                        ppcDcbf((unsigned long) p);
                }
        }
+#else
+       printf("DDR init: DMA method\n");
+       for (p = 0; p < (uint *)(8 * 1024); p++) {
+               /* zero one data cache line */
+               if (((unsigned int)p & 0x1f) == 0) {
+                       ppcDcbz((unsigned long)p);
+               }
+
+               /* write pattern to it and flush */
+               *p = (unsigned int)0xdeadbeef;
+
+               if (((unsigned int)p & 0x1c) == 0x1c) {
+                       ppcDcbf((unsigned long)p);
+               }
+       }
 
        /* 8K */
        dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
@@ -396,13 +501,31 @@ ddr_enable_ecc(unsigned int dram_size)
        for (i = 1; i < dram_size / 0x800000; i++) {
                dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
        }
-
-       /*
-        * Enable errors for ECC.
-        */
-       ddr->err_disable = 0x00000000;
-       asm("sync;isync");
 #endif
-}
 
+       t_end = get_tbms();
+       icache_disable();
+
+       debug("\nREADY!!\n");
+       debug("ddr init duration: %ld ms\n", t_end - t_start);
+
+       /* Clear All ECC Errors */
+       if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
+               ddr->err_detect |= ECC_ERROR_DETECT_MME;
+       if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
+               ddr->err_detect |= ECC_ERROR_DETECT_MBE;
+       if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
+               ddr->err_detect |= ECC_ERROR_DETECT_SBE;
+       if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
+               ddr->err_detect |= ECC_ERROR_DETECT_MSE;
+
+       /* Disable ECC-Interrupts */
+       ddr->err_int_en &= ECC_ERR_INT_DISABLE;
+
+       /* Enable errors for ECC */
+       ddr->err_disable &= ECC_ERROR_ENABLE;
+
+       __asm__ __volatile__ ("sync");
+       __asm__ __volatile__ ("isync");
+}
 #endif /* CONFIG_DDR_ECC */

diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 1368fc3feaf5be720e5c852aa31d8c502fd6a285..ad6b3f669fb38c77cda40e491c66e3370f0e5c5b 100644 (file)
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -32,6 +32,8 @@
 #include <mpc83xx.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ----------------------------------------------------------------- */
 
 typedef enum {
@@ -92,7 +94,6 @@ corecnf_t corecnf_tab[] = {
  */
 int get_clocks (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
        u32 pci_sync_in;
        u8  spmf;
@@ -342,14 +343,11 @@ int get_clocks (void)
  *********************************************/
 ulong get_bus_freq (ulong dummy)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        return gd->csb_clk;
 }
 
 int print_clock_conf (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        printf("Clock configuration:\n");
        printf("  Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
        printf("  Core:                %4d MHz\n",gd->core_clk/1000000);

diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index fb001a654c5afa6cdd8958b365e3a547d624c91d..6e02cce799d7dd48b833c9b274e751e58cbc3b23 100644 (file)
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -179,10 +179,47 @@ in_flash:
 #endif
 #endif /* CFG_RAMBOOT */
 
-       bl setup_stack_in_data_cache_on_r1
+       /* setup the bats */
+       bl      setup_bats
+       sync
+
+       /*
+        * Cache must be enabled here for stack-in-cache trick.
+        * This means we need to enable the BATS.
+        * This means:
+        *   1) for the EVB, original gt regs need to be mapped
+        *   2) need to have an IBAT for the 0xf region,
+        *      we are running there!
+        * Cache should be turned on after BATs, since by default
+        * everything is write-through.
+        * The init-mem BAT can be reused after reloc. The old
+        * gt-regs BAT can be reused after board_init_f calls
+        * board_early_init_f (EVB only).
+        */
+       /* enable address translation */
+       bl      enable_addr_trans
+       sync
+
+       /* enable and invalidate the data cache */
+       bl      dcache_enable
+       sync
+#ifdef CFG_INIT_RAM_LOCK
+       bl      lock_ram_in_cache
+       sync
+#endif
+
+       /* set up the stack pointer in our newly created
+        * cache-ram (r1) */
+       lis     r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
+       ori     r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
+
+       li      r0, 0           /* Make room for stack frame header and */
+       stwu    r0, -4(r1)      /* clear final stack frame so that      */
+       stwu    r0, -4(r1)      /* stack backtraces terminate cleanly   */
+
 
        /* let the C-code set up the rest                           */
-       /*                                                                                  */
+       /*                                                          */
        /* Be careful to keep code relocatable & stack humble   */
        /*------------------------------------------------------*/
 
@@ -426,8 +463,14 @@ init_e300_core: /* time t 10 */
 #else
        /* Disable Wathcdog  */
        /*-------------------*/
+       lwz r4, SWCRR(r3)
+       /* Check to see if its enabled for disabling
+          once disabled by SW you can't re-enable */
+       andi. r4, r4, 0x4
+       beq 1f
        xor r4, r4, r4
        stw r4, SWCRR(r3)
+1:
 #endif /* CONFIG_WATCHDOG */
 
        /* Initialize the Hardware Implementation-dependent Registers */
@@ -503,6 +546,221 @@ init_e300_core: /* time t 10 */
        /*------------------------------*/
        blr
 
+       .globl  invalidate_bats
+invalidate_bats:
+       /* invalidate BATs */
+       mtspr   IBAT0U, r0
+       mtspr   IBAT1U, r0
+       mtspr   IBAT2U, r0
+       mtspr   IBAT3U, r0
+#if (CFG_HID2 & HID2_HBE)
+       mtspr   IBAT4U, r0
+       mtspr   IBAT5U, r0
+       mtspr   IBAT6U, r0
+       mtspr   IBAT7U, r0
+#endif
+       isync
+       mtspr   DBAT0U, r0
+       mtspr   DBAT1U, r0
+       mtspr   DBAT2U, r0
+       mtspr   DBAT3U, r0
+#if (CFG_HID2 & HID2_HBE)
+       mtspr   DBAT4U, r0
+       mtspr   DBAT5U, r0
+       mtspr   DBAT6U, r0
+       mtspr   DBAT7U, r0
+#endif
+       isync
+       sync
+       blr
+
+       /* setup_bats - set them up to some initial state */
+       .globl  setup_bats
+setup_bats:
+       addis   r0, r0, 0x0000
+
+       /* IBAT 0 */
+       addis   r4, r0, CFG_IBAT0L@h
+       ori     r4, r4, CFG_IBAT0L@l
+       addis   r3, r0, CFG_IBAT0U@h
+       ori     r3, r3, CFG_IBAT0U@l
+       mtspr   IBAT0L, r4
+       mtspr   IBAT0U, r3
+       isync
+
+       /* DBAT 0 */
+       addis   r4, r0, CFG_DBAT0L@h
+       ori     r4, r4, CFG_DBAT0L@l
+       addis   r3, r0, CFG_DBAT0U@h
+       ori     r3, r3, CFG_DBAT0U@l
+       mtspr   DBAT0L, r4
+       mtspr   DBAT0U, r3
+       isync
+
+       /* IBAT 1 */
+       addis   r4, r0, CFG_IBAT1L@h
+       ori     r4, r4, CFG_IBAT1L@l
+       addis   r3, r0, CFG_IBAT1U@h
+       ori     r3, r3, CFG_IBAT1U@l
+       mtspr   IBAT1L, r4
+       mtspr   IBAT1U, r3
+       isync
+
+       /* DBAT 1 */
+       addis   r4, r0, CFG_DBAT1L@h
+       ori     r4, r4, CFG_DBAT1L@l
+       addis   r3, r0, CFG_DBAT1U@h
+       ori     r3, r3, CFG_DBAT1U@l
+       mtspr   DBAT1L, r4
+       mtspr   DBAT1U, r3
+       isync
+
+       /* IBAT 2 */
+       addis   r4, r0, CFG_IBAT2L@h
+       ori     r4, r4, CFG_IBAT2L@l
+       addis   r3, r0, CFG_IBAT2U@h
+       ori     r3, r3, CFG_IBAT2U@l
+       mtspr   IBAT2L, r4
+       mtspr   IBAT2U, r3
+       isync
+
+       /* DBAT 2 */
+       addis   r4, r0, CFG_DBAT2L@h
+       ori     r4, r4, CFG_DBAT2L@l
+       addis   r3, r0, CFG_DBAT2U@h
+       ori     r3, r3, CFG_DBAT2U@l
+       mtspr   DBAT2L, r4
+       mtspr   DBAT2U, r3
+       isync
+
+       /* IBAT 3 */
+       addis   r4, r0, CFG_IBAT3L@h
+       ori     r4, r4, CFG_IBAT3L@l
+       addis   r3, r0, CFG_IBAT3U@h
+       ori     r3, r3, CFG_IBAT3U@l
+       mtspr   IBAT3L, r4
+       mtspr   IBAT3U, r3
+       isync
+
+       /* DBAT 3 */
+       addis   r4, r0, CFG_DBAT3L@h
+       ori     r4, r4, CFG_DBAT3L@l
+       addis   r3, r0, CFG_DBAT3U@h
+       ori     r3, r3, CFG_DBAT3U@l
+       mtspr   DBAT3L, r4
+       mtspr   DBAT3U, r3
+       isync
+
+#if (CFG_HID2 & HID2_HBE)
+       /* IBAT 4 */
+       addis   r4, r0, CFG_IBAT4L@h
+       ori     r4, r4, CFG_IBAT4L@l
+       addis   r3, r0, CFG_IBAT4U@h
+       ori     r3, r3, CFG_IBAT4U@l
+       mtspr   IBAT4L, r4
+       mtspr   IBAT4U, r3
+       isync
+
+       /* DBAT 4 */
+       addis   r4, r0, CFG_DBAT4L@h
+       ori     r4, r4, CFG_DBAT4L@l
+       addis   r3, r0, CFG_DBAT4U@h
+       ori     r3, r3, CFG_DBAT4U@l
+       mtspr   DBAT4L, r4
+       mtspr   DBAT4U, r3
+       isync
+
+       /* IBAT 5 */
+       addis   r4, r0, CFG_IBAT5L@h
+       ori     r4, r4, CFG_IBAT5L@l
+       addis   r3, r0, CFG_IBAT5U@h
+       ori     r3, r3, CFG_IBAT5U@l
+       mtspr   IBAT5L, r4
+       mtspr   IBAT5U, r3
+       isync
+
+       /* DBAT 5 */
+       addis   r4, r0, CFG_DBAT5L@h
+       ori     r4, r4, CFG_DBAT5L@l
+       addis   r3, r0, CFG_DBAT5U@h
+       ori     r3, r3, CFG_DBAT5U@l
+       mtspr   DBAT5L, r4
+       mtspr   DBAT5U, r3
+       isync
+
+       /* IBAT 6 */
+       addis   r4, r0, CFG_IBAT6L@h
+       ori     r4, r4, CFG_IBAT6L@l
+       addis   r3, r0, CFG_IBAT6U@h
+       ori     r3, r3, CFG_IBAT6U@l
+       mtspr   IBAT6L, r4
+       mtspr   IBAT6U, r3
+       isync
+
+       /* DBAT 6 */
+       addis   r4, r0, CFG_DBAT6L@h
+       ori     r4, r4, CFG_DBAT6L@l
+       addis   r3, r0, CFG_DBAT6U@h
+       ori     r3, r3, CFG_DBAT6U@l
+       mtspr   DBAT6L, r4
+       mtspr   DBAT6U, r3
+       isync
+
+       /* IBAT 7 */
+       addis   r4, r0, CFG_IBAT7L@h
+       ori     r4, r4, CFG_IBAT7L@l
+       addis   r3, r0, CFG_IBAT7U@h
+       ori     r3, r3, CFG_IBAT7U@l
+       mtspr   IBAT7L, r4
+       mtspr   IBAT7U, r3
+       isync
+
+       /* DBAT 7 */
+       addis   r4, r0, CFG_DBAT7L@h
+       ori     r4, r4, CFG_DBAT7L@l
+       addis   r3, r0, CFG_DBAT7U@h
+       ori     r3, r3, CFG_DBAT7U@l
+       mtspr   DBAT7L, r4
+       mtspr   DBAT7U, r3
+       isync
+#endif
+
+       /* Invalidate TLBs.
+        * -> for (val = 0; val < 0x20000; val+=0x1000)
+        * ->   tlbie(val);
+        */
+       lis     r3, 0
+       lis     r5, 2
+
+1:
+       tlbie   r3
+       addi    r3, r3, 0x1000
+       cmp     0, 0, r3, r5
+       blt     1b
+
+       blr
+
+       .globl enable_addr_trans
+enable_addr_trans:
+       /* enable address translation */
+       mfmsr   r5
+       ori     r5, r5, (MSR_IR | MSR_DR)
+       mtmsr   r5
+       isync
+       blr
+
+       .globl disable_addr_trans
+disable_addr_trans:
+       /* disable address translation */
+       mflr    r4
+       mfmsr   r3
+       andi.   r0, r3, (MSR_IR | MSR_DR)
+       beqlr
+       andc    r3, r3, r0
+       mtspr   SRR0, r4
+       mtspr   SRR1, r3
+       rfi
+
 /* Cache functions.
  *
  * Note: requires that all cache bits in
@@ -538,32 +796,31 @@ icache_disable:
        .globl  icache_status
 icache_status:
        mfspr   r3, HID0
-       rlwinm  r3, r3, HID0_ICE_SHIFT, 31, 31
+       rlwinm  r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
        blr
 
        .globl  dcache_enable
 dcache_enable:
        mfspr   r3, HID0
-       ori     r3, r3, HID0_ENABLE_DATA_CACHE
-       lis     r4, 0
-       ori     r4, r4, HID0_LOCK_DATA_CACHE
-       andc    r3, r3, r4
-       ori     r4, r3, HID0_LOCK_INSTRUCTION_CACHE
-       sync
-       mtspr   HID0, r4    /* sets enable and invalidate, clears lock */
+       li      r5, HID0_DCFI|HID0_DLOCK
+       andc    r3, r3, r5
+       mtspr   HID0, r3                /* no invalidate, unlock */
+       ori     r3, r3, HID0_DCE
+       ori     r5, r3, HID0_DCFI
+       mtspr   HID0, r5                /* enable + invalidate */
+       mtspr   HID0, r3                /* enable */
        sync
-       mtspr   HID0, r3        /* clears invalidate */
        blr
 
        .globl  dcache_disable
 dcache_disable:
        mfspr   r3, HID0
        lis     r4, 0
-       ori     r4, r4, HID0_ENABLE_DATA_CACHE|HID0_LOCK_DATA_CACHE
+       ori     r4, r4, HID0_DCE|HID0_DLOCK
        andc    r3, r3, r4
-       ori     r4, r3, HID0_INVALIDATE_DATA_CACHE
+       ori     r4, r3, HID0_DCI
        sync
-       mtspr   HID0, r4    /* sets invalidate, clears enable and lock */
+       mtspr   HID0, r4        /* sets invalidate, clears enable and lock */
        sync
        mtspr   HID0, r3        /* clears invalidate */
        blr
@@ -571,7 +828,7 @@ dcache_disable:
        .globl  dcache_status
 dcache_status:
        mfspr   r3, HID0
-       rlwinm  r3, r3, HID0_DCE_SHIFT, 31, 31
+       rlwinm  r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
        blr
 
        .globl get_pvr
@@ -579,6 +836,40 @@ get_pvr:
        mfspr   r3, PVR
        blr
 
+/*------------------------------------------------------------------------------- */
+/* Function:    ppcDcbf */
+/* Description:         Data Cache block flush */
+/* Input:       r3 = effective address */
+/* Output:      none. */
+/*------------------------------------------------------------------------------- */
+       .globl  ppcDcbf
+ppcDcbf:
+       dcbf    r0,r3
+       blr
+
+/*------------------------------------------------------------------------------- */
+/* Function:    ppcDcbi */
+/* Description:         Data Cache block Invalidate */
+/* Input:       r3 = effective address */
+/* Output:      none. */
+/*------------------------------------------------------------------------------- */
+       .globl  ppcDcbi
+ppcDcbi:
+       dcbi    r0,r3
+       blr
+
+/*--------------------------------------------------------------------------
+ * Function:    ppcDcbz
+ * Description:         Data Cache block zero.
+ * Input:       r3 = effective address
+ * Output:      none.
+ *-------------------------------------------------------------------------- */
+
+       .globl  ppcDcbz
+ppcDcbz:
+       dcbz    r0,r3
+       blr
+
 /*-------------------------------------------------------------------*/
 
 /*
@@ -668,46 +959,29 @@ relocate_code:
  * Now flush the cache: note that we must start from a cache aligned
  * address. Otherwise we might miss one cache line.
  */
-4:
-       bl un_setup_stack_in_data_cache
-       mr r7, r3
-       mr r8, r4
-       bl dcache_disable
-       mr r3, r7
-       mr r4, r8
-
-       cmpwi   r6,0
+4:     cmpwi   r6,0
        add     r5,r3,r5
-       beq     7f      /* Always flush prefetch queue in any case */
+       beq     7f              /* Always flush prefetch queue in any case */
        subi    r0,r6,1
        andc    r3,r3,r0
-       mfspr   r7,HID0         /* don't do dcbst if dcache is disabled*/
-       rlwinm  r7,r7,HID0_DCE_SHIFT,31,31
-       cmpwi   r7,0
-       beq     9f
        mr      r4,r3
 5:     dcbst   0,r4
        add     r4,r4,r6
        cmplw   r4,r5
        blt     5b
-       sync            /* Wait for all dcbst to complete on bus */
-9:     mfspr   r7,HID0         /* don't do icbi if icache is disabled */
-       rlwinm  r7,r7,HID0_DCE_SHIFT,31,31
-       cmpwi   r7,0
-       beq     7f
+       sync                    /* Wait for all dcbst to complete on bus */
        mr      r4,r3
 6:     icbi    0,r4
        add     r4,r4,r6
        cmplw   r4,r5
        blt     6b
-7:     sync            /* Wait for all icbi to complete on bus */
+7:     sync                    /* Wait for all icbi to complete on bus */
        isync
 
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
-
        addi    r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
        mtlr    r0
        blr
@@ -865,6 +1139,27 @@ trap_reloc:
        blr
 
 #ifdef CFG_INIT_RAM_LOCK
+lock_ram_in_cache:
+       /* Allocate Initial RAM in data cache.
+        */
+       lis     r3, (CFG_INIT_RAM_ADDR & ~31)@h
+       ori     r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
+       li      r2, ((CFG_INIT_RAM_END & ~31) + \
+                    (CFG_INIT_RAM_ADDR & 31) + 31) / 32
+       mtctr   r2
+1:
+       dcbz    r0, r3
+       addi    r3, r3, 32
+       bdnz    1b
+
+       /* Lock the data cache */
+       mfspr   r0, HID0
+       ori     r0, r0, 0x1000
+       sync
+       mtspr   HID0, r0
+       sync
+       blr
+
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
        /* invalidate the INIT_RAM section */
@@ -878,6 +1173,15 @@ unlock_ram_in_cache:
        bdnz    1b
        sync                    /* Wait for all icbi to complete on bus */
        isync
+
+       /* Unlock the data cache and invalidate it */
+       mfspr   r3, HID0
+       li      r5, HID0_DLOCK|HID0_DCFI
+       andc    r3, r3, r5              /* no invalidate, unlock */
+       ori     r5, r3, HID0_DCFI       /* invalidate, unlock */
+       mtspr   HID0, r5                /* invalidate, unlock */
+       mtspr   HID0, r3                /* no invalidate, unlock */
+       sync
        blr
 #endif
 
@@ -946,148 +1250,3 @@ remap_flash_by_law0:
        stw r4, LBLAWBAR1(r3)
        stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
        blr
-
-setup_stack_in_data_cache_on_r1:
-       lis r3, (CFG_IMMRBAR)@h
-
-       /* setup D-BAT for the D-Cache (with out real memory backup) */
-
-       lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
-       mtspr   DBAT0U, r4
-       ori r4, r4, 0x0002
-       mtspr   DBAT0L, r4
-       isync
-
-#if 0
-       /* Enable MMU */
-       mfmsr r4
-       ori r4, r4, (MSR_DR | MSR_IR)@l
-       mtmsr r4
-#endif
-
-       /* Enable and invalidate data cache. */
-       mfspr   r4, HID0
-       mr      r5, r4
-       ori     r4, r4, HID0_DCE | HID0_DCI
-       ori     r5, r5, HID0_DCE
-       sync
-       mtspr   HID0, r4
-       mtspr   HID0, r5
-       sync
-
-       /* Allocate Initial RAM in data cache.*/
-       li  r0, 0
-       lis     r4, (CFG_INIT_RAM_ADDR)@h
-       ori     r4, r4, (CFG_INIT_RAM_ADDR)@l
-       li      r5, 128*8 /* 128*8*32=32Kb */
-       mtctr   r5
-1:
-       dcbz    r0, r4
-       addi    r4, r4, 32
-       bdnz    1b
-       isync
-
-       /* Lock all the D-cache, basically leaving the reset of the program without dcache */
-       mfspr   r4, HID0
-       ori     r4, r4, (HID0_DLOCK)@l
-       sync
-       mtspr   HID0 , r4
-
-       /* setup the stack pointer in r1 */
-       lis     r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
-       ori     r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
-       li      r0, 0                   /* Make room for stack frame header and */
-
-       stwu    r0, -4(r1)              /* clear final stack frame so that      */
-       stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
-
-       blr
-
-un_setup_stack_in_data_cache:
-       blr
-       mr r14, r4
-       mr r15, r5
-
-
-       lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
-       mtspr   DBAT0U, r4
-       ori r4, r4, 0x0002
-       mtspr   DBAT0L, r4
-       isync
-
-       /* un lock all the D-cache */
-       mfspr   r4, HID0
-       lis r5, (~(HID0_DLOCK))@h
-       ori     r5, r5, (~(HID0_DLOCK))@l
-       and r4, r4, r5
-       sync
-       mtspr   HID0 , r4
-
-       /* Re - Allocate Initial RAM in data cache.*/
-       li  r0, 0
-       lis     r4, (CFG_INIT_RAM_ADDR)@h
-       ori     r4, r4, (CFG_INIT_RAM_ADDR)@l
-       li      r5, 128*8 /* 128*8*32=32Kb */
-       mtctr   r5
-1:
-       dcbz    r0, r4
-       addi    r4, r4, 32
-       bdnz    1b
-       isync
-
-       mflr r16
-       bl dcache_disable
-       mtlr r16
-
-       blr
-
-#if 0
-#define GREEN_LIGHT 0x2B0D4046
-#define RED_LIGHT   0x250D4046
-#define LIB_CNT     0x4FFF
-
-/*
- * Lib Light
- */
-
-       .globl liblight
-liblight:
-       lis     r3, CFG_IMMRBAR@h
-       ori     r3, r3, CFG_IMMRBAR@l
-       li r4, 0x3002
-       mtmsr r4
-       xor r4, r4, r4
-       mtspr   HID0, r4
-       mtspr   HID2, r4
-       lis r4, 0xF8000000@h
-       ori r4, r4, 0xF8000000@l
-       stw r4, LBLAWBAR1(r3)
-       lis r4, 0x8000000E@h
-       ori r4, r4, 0x8000000E@l
-       stw r4, LBLAWAR1(r3)
-       lis r4, 0xF8000801@h
-       ori r4, r4, 0xF8000801@l
-       stw r4, BR1(r3)
-       lis r4, 0xFFFFE8f0@h
-       ori r4, r4, 0xFFFFE8f0@l
-       stw r4, OR1(r3)
-
-       lis r4, 0xF8000000@h
-       ori r4, r4, 0xF8000000@l
-       lis r5, GREEN_LIGHT@h
-       ori r5, r5, GREEN_LIGHT@l
-       lis r6, RED_LIGHT@h
-       ori r6, r6, RED_LIGHT@l
-       lis r7, LIB_CNT@h
-       ori r7, r7, LIB_CNT@l
-
-1:
-       stw r5, 0(r4)
-       mtctr r7
-2:     bdnz 2b
-       stw r6, 0(r4)
-       mtctr r7
-3:     bdnz 3b
-       b 1b
-
-#endif

diff --git a/cpu/mpc83xx/traps.c b/cpu/mpc83xx/traps.c
index c7a56386e8e1e8a8f7658dd58d13c06df65c6bf3..44345afbfaa447aba717f585124aa9ca2cdab075 100644 (file)
--- a/cpu/mpc83xx/traps.c
+++ b/cpu/mpc83xx/traps.c
@@ -40,6 +40,8 @@
 #include <asm/processor.h>
 #include <asm/mpc8349_pci.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Returns 0 if exception not found and fixup otherwise.  */
 extern unsigned long search_exception_table(unsigned long);
 
@@ -52,7 +54,6 @@ extern unsigned long search_exception_table(unsigned long);
 void
 print_backtrace(unsigned long *sp)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int cnt = 0;
        unsigned long i;
 

diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c
index aa8a5a57ba82ce7d1e141e51f47360020427ce9d..3504d50caed847a93224080de67c9b40cecbaa2b 100644 (file)
--- a/cpu/mpc85xx/commproc.c
+++ b/cpu/mpc85xx/commproc.c
@@ -24,6 +24,8 @@
 #include <common.h>
 #include <asm/cpm_85xx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_CPM2)
 /*
  * because we have stack and init data in dual port ram
@@ -35,8 +37,6 @@
 void
 m8560_cpm_reset(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *)CFG_IMMR;
        volatile ulong count;
 
@@ -64,8 +64,6 @@ m8560_cpm_reset(void)
 uint
 m8560_cpm_dpalloc(uint size, uint align)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *)CFG_IMMR;
        uint    retloc;
        uint    align_mask, off;
@@ -122,8 +120,6 @@ m8560_cpm_hostalloc(uint size, uint align)
 void
 m8560_cpm_setbrg(uint brg, uint rate)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *)CFG_IMMR;
        volatile uint   *bp;
 
@@ -146,8 +142,6 @@ m8560_cpm_setbrg(uint brg, uint rate)
 void
 m8560_cpm_fastbrg(uint brg, uint rate, int div16)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *)CFG_IMMR;
        volatile uint   *bp;
 

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index efde9cc31abe40f792672c6da10313fd4cd88679..c12b47b589d8795c657d559dd40dcb7257c25f40 100644 (file)
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -30,6 +30,8 @@
 #include <ioports.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_CPM2
 static void config_8560_ioports (volatile immap_t * immr)
 {
@@ -103,7 +105,6 @@ static void config_8560_ioports (volatile immap_t * immr)
 
 void cpu_init_f (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        volatile immap_t    *immap = (immap_t *)CFG_IMMR;
        volatile ccsr_lbc_t *memctl = &immap->im_lbc;
        extern void m8560_cpm_reset (void);

diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c
index cf060d68901d5186b668f24423ab4f94cd404d4c..4e925f8bea2d6464dc2f60fd16881ec1976ff894 100644 (file)
--- a/cpu/mpc85xx/serial_scc.c
+++ b/cpu/mpc85xx/serial_scc.c
@@ -35,6 +35,8 @@
 #include <common.h>
 #include <asm/cpm_85xx.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_CPM2)
 #if defined(CONFIG_CONS_ON_SCC)
 
@@ -186,8 +188,6 @@ int serial_init (void)
 void
 serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
 #if defined(CONFIG_CONS_USE_EXTC)
        m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
                CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);

diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index d736742f6225749515d13cbe1fb5d507dba7f778..ca81ee73521a695cf19a7ae54fa457f29c288717 100644 (file)
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -29,6 +29,8 @@
 #include <ppc_asm.tmpl>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* --------------------------------------------------------------- */
 
 void get_sys_info (sys_info_t * sysInfo)
@@ -80,7 +82,6 @@ void get_sys_info (sys_info_t * sysInfo)
 
 int get_clocks (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        sys_info_t sys_info;
 #if defined(CONFIG_CPM2)
        volatile immap_t *immap = (immap_t *) CFG_IMMR;

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 7ac65736bc03f697863ea7a058ed151ec8c59fbe..f96a4c3f8b0dcd2d0cf9ef2ebb719b50fbbadb98 100644 (file)
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -715,7 +715,7 @@ icache_disable:
        .globl  icache_status
 icache_status:
        mfspr   r3,L1CSR1
-       srwi    r3, r3, 31      /* >>31 => select bit 0 */
+       andi.   r3,r3,1
        blr
 
        .globl  dcache_enable
@@ -748,7 +748,7 @@ dcache_disable:
        .globl  dcache_status
 dcache_status:
        mfspr   r3,L1CSR0
-       srwi    r3, r3, 31      /* >>31 => select bit 0 */
+       andi.   r3,r3,1
        blr
 
        .globl get_pir

diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c
index a87eed2ad100fb937850196470b326b95f4b99fe..904f0523396d631a0aa8de698da0b4b6d1ba0cfc 100644 (file)
--- a/cpu/mpc85xx/traps.c
+++ b/cpu/mpc85xx/traps.c
@@ -39,6 +39,8 @@
 #include <command.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 int (*debugger_exception_handler)(struct pt_regs *) = 0;
 #endif
@@ -83,7 +85,6 @@ extern void do_bedbug_breakpoint(struct pt_regs *);
 void
 print_backtrace(unsigned long *sp)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int cnt = 0;
        unsigned long i;
 

diff --git a/cpu/mpc8xx/commproc.c b/cpu/mpc8xx/commproc.c
index 75740e07f2bd00ef78071c6d5568bf7e89748f13..07c763cfde9061b76829ef976e902f1c8e4c657b 100644 (file)
--- a/cpu/mpc8xx/commproc.c
+++ b/cpu/mpc8xx/commproc.c
@@ -24,12 +24,12 @@
 #include <common.h>
 #include <commproc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CFG_ALLOC_DPRAM
 
 int dpram_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Reclaim the DP memory for our use. */
        gd->dp_alloc_base = CPM_DATAONLY_BASE;
        gd->dp_alloc_top  = CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE;
@@ -43,7 +43,6 @@ int dpram_init (void)
  */
 uint dpram_alloc (uint size)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        uint addr = gd->dp_alloc_base;
 
        if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top)
@@ -56,8 +55,6 @@ uint dpram_alloc (uint size)
 
 uint dpram_base (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        return gd->dp_alloc_base;
 }
 
@@ -67,8 +64,6 @@ uint dpram_base (void)
  */
 uint dpram_alloc_align (uint size, uint align)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        uint addr, mask = align - 1;
 
        addr = (gd->dp_alloc_base + mask) & ~mask;
@@ -83,8 +78,6 @@ uint dpram_alloc_align (uint size, uint align)
 
 uint dpram_base_align (uint align)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        uint mask = align - 1;
 
        return (gd->dp_alloc_base + mask) & ~mask;

diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c
index 4a32986a2e7c0cc33414acdb9d19f1031b7e96cb..97112f03daf168b7a311d1af7a91a34a05c08ce4 100644 (file)
--- a/cpu/mpc8xx/cpu.c
+++ b/cpu/mpc8xx/cpu.c
@@ -39,6 +39,8 @@
 #include <mpc8xx.h>
 #include <asm/cache.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static char *cpu_warning = "\n         " \
        "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
 
@@ -69,14 +71,15 @@ static int check_CPU (long clock, uint pvr, uint immr)
 
        k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
        m = 0;
+       suf = "";
 
        /*
         * Some boards use sockets so different CPUs can be used.
         * We have to check chip version in run time.
         */
        switch (k) {
-       case 0x00020001: pre = 'P'; suf = ""; break;
-       case 0x00030001: suf = ""; break;
+       case 0x00020001: pre = 'P'; break;
+       case 0x00030001: break;
        case 0x00120003: suf = "A"; break;
        case 0x00130003: suf = "A3"; break;
 
@@ -93,7 +96,11 @@ static int check_CPU (long clock, uint pvr, uint immr)
                /* this value is not documented anywhere */
        case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
                /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
-       case 0x08000003: pre = 'M'; suf = ""; m = 1;
+       case 0x08010004:                /* Rev. A.0 */
+               suf = "A";
+               /* fall through */
+       case 0x08000003:                /* Rev. 0.3 */
+               pre = 'M'; m = 1;
                if (id_str == NULL)
                        id_str =
 # if defined(CONFIG_MPC852T)
@@ -344,8 +351,6 @@ static int check_CPU (long clock, uint pvr, uint immr)
 
 int checkcpu (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong clock = gd->cpu_clk;
        uint immr = get_immr (0);       /* Return full IMMR contents */
        uint pvr = get_pvr ();
@@ -534,8 +539,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  */
 unsigned long get_tbclk (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        uint immr = get_immr (0);       /* Return full IMMR contents */
        volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
        ulong oscclk, factor, pll;

diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c
index b2c59c6f57b6dc857fde02288764a65b37f9cc2c..1a7111fb2a69462a7a340631ff7d3462dc59eb0a 100644 (file)
--- a/cpu/mpc8xx/cpu_init.c
+++ b/cpu/mpc8xx/cpu_init.c
@@ -27,6 +27,10 @@
 #include <mpc8xx.h>
 #include <commproc.h>
 
+#if defined(CFG_RTCSC) || defined(CFG_RMDS)
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 #if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
 void cpm_load_patch (volatile immap_t * immr);
 #endif
@@ -259,8 +263,6 @@ void cpu_init_f (volatile immap_t * immr)
 int cpu_init_r (void)
 {
 #if defined(CFG_RTCSC) || defined(CFG_RMDS)
-       DECLARE_GLOBAL_DATA_PTR;
-
        bd_t *bd = gd->bd;
        volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
 #endif

diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c
index d2f5d888440b215ec67e9709d09d6ac27d38af54..6006478f97ca9926c24e8a2a94ab6e3ab8cc8225 100644 (file)
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@@ -27,6 +27,8 @@
 #include <net.h>
 #include <command.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef ET_DEBUG
 
 #if (CONFIG_COMMANDS & CFG_CMD_NET) && \
@@ -371,7 +373,6 @@ static inline void fec_half_duplex(struct eth_device *dev)
 
 static void fec_pin_init(int fecidx)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        bd_t           *bd = gd->bd;
        volatile immap_t *immr = (immap_t *) CFG_IMMR;
        volatile fec_t *fecp;

diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c
index 682db53edb10d9807e015f03b717682087fe308b..6c59374e3fbbaad843d2d39b41ff8f37418f5637 100644 (file)
--- a/cpu/mpc8xx/i2c.c
+++ b/cpu/mpc8xx/i2c.c
@@ -37,6 +37,8 @@
 #include <watchdog.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* define to enable debug messages */
 #undef DEBUG_I2C
 
@@ -205,8 +207,6 @@ i2c_setrate (int hz, int speed)
 void
 i2c_init(int speed, int slaveaddr)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immap = (immap_t *)CFG_IMMR ;
        volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
        volatile i2c8xx_t *i2c  = (i2c8xx_t *)&immap->im_i2c;
@@ -615,8 +615,6 @@ int i2c_probe(uchar chip)
 
 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        i2c_state_t state;
        uchar xaddr[4];
        int rc;
@@ -671,8 +669,6 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 
 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        i2c_state_t state;
        uchar xaddr[4];
        int rc;

diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c
index fa0405f198da8e69165cc24323e4fcde22f35c74..26a82cc2405399c19bbdd691ac5955f3f02ce4b6 100644 (file)
--- a/cpu/mpc8xx/serial.c
+++ b/cpu/mpc8xx/serial.c
@@ -27,6 +27,8 @@
 #include <serial.h>
 #include <watchdog.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if !defined(CONFIG_8xx_CONS_NONE)     /* No Console at all */
 
 #if defined(CONFIG_8xx_CONS_SMC1)      /* Console on SMC1 */
@@ -65,7 +67,6 @@
 
 static void serial_setdivisor(volatile cpm8xx_t *cp)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
 
        if(divisor/16>0x1000) {
@@ -268,8 +269,6 @@ smc_putc(const char c)
        volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 
 #ifdef CONFIG_MODEM_SUPPORT
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (gd->be_quiet)
                return;
 #endif
@@ -553,8 +552,6 @@ scc_putc(const char c)
        volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 
 #ifdef CONFIG_MODEM_SUPPORT
-       DECLARE_GLOBAL_DATA_PTR;
-
        if (gd->be_quiet)
                return;
 #endif
@@ -649,13 +646,11 @@ struct serial_device serial_scc_device =
 #ifdef CONFIG_MODEM_SUPPORT
 void disable_putc(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        gd->be_quiet = 1;
 }
 
 void enable_putc(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        gd->be_quiet = 0;
 }
 #endif

diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c
index f03831617c1f24e316e49e182498e9c0c466e0ec..57f91c0aa049cee3efbf5459203ea49d2eab3ae2 100644 (file)
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -25,6 +25,8 @@
 #include <mpc8xx.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK) || defined(DEBUG)
 
 #define PITC_SHIFT 16
@@ -181,8 +183,6 @@ unsigned long measure_gclk(void)
  */
 int get_clocks (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        uint immr = get_immr (0);       /* Return full IMMR contents */
        volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
        uint sccr = immap->im_clkrst.car_sccr;
@@ -238,8 +238,6 @@ static long init_pll_866 (long clk);
  */
 int get_clocks_866 (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *) CFG_IMMR;
        char              tmp[64];
        long              cpuclk = 0;
@@ -277,8 +275,6 @@ int get_clocks_866 (void)
  */
 int sdram_adjust_866 (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *) CFG_IMMR;
        long              mamr;
 
@@ -371,8 +367,6 @@ static long init_pll_866 (long clk)
  */
 int adjust_sdram_tbs_8xx (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *) CFG_IMMR;
        long              mamr;
        long              sccr;

diff --git a/cpu/mpc8xx/video.c b/cpu/mpc8xx/video.c
index ee60477ab8f18753450a25c15860dbd763725665..918de6794353b8f6b8de4c6c6a46df2c258f6d49 100644 (file)
--- a/cpu/mpc8xx/video.c
+++ b/cpu/mpc8xx/video.c
@@ -39,6 +39,8 @@
 
 #ifdef CONFIG_VIDEO
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /************************************************************************/
 /* ** DEBUG SETTINGS                                                   */
 /************************************************************************/
@@ -1164,7 +1166,6 @@ static void *video_logo (void)
        u16 *screen = video_fb_address, width = VIDEO_COLS;
 #ifdef VIDEO_INFO
 # ifndef CONFIG_FADS
-       DECLARE_GLOBAL_DATA_PTR;
        char temp[32];
 # endif
        char info[80];
@@ -1282,8 +1283,6 @@ static int video_init (void *videobase)
 
 int drv_video_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int error, devices = 1;
 
        device_t videodev;

diff --git a/cpu/nios/serial.c b/cpu/nios/serial.c
index 4bdda25007aa92f20e506e2f97b709603ad0eb6c..5ecdc6d7ea128ef8e831d8032656518d559496d2 100644 (file)
--- a/cpu/nios/serial.c
+++ b/cpu/nios/serial.c
@@ -26,6 +26,8 @@
 #include <watchdog.h>
 #include <nios-io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*------------------------------------------------------------------
  * JTAG acts as the serial port
  *-----------------------------------------------------------------*/
@@ -83,7 +85,6 @@ int serial_init (void) { return (0);}
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned div;
 
        div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;

diff --git a/cpu/nios2/serial.c b/cpu/nios2/serial.c
index 2d08c93d09f9867530984dcb1107eff73f920238..3d766037a14f9e33447176e339529aa1f10abb55 100644 (file)
--- a/cpu/nios2/serial.c
+++ b/cpu/nios2/serial.c
@@ -27,6 +27,8 @@
 #include <nios2.h>
 #include <nios2-io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*------------------------------------------------------------------
  * JTAG acts as the serial port
  *-----------------------------------------------------------------*/
@@ -93,7 +95,6 @@ int serial_init (void) { return (0);}
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        unsigned div;
 
        div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;

diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 64431ab13a450ca54d1f561085d0ff20728481c7..fad895b3191d0445320584a7b62ce15e164cc0b4 100644 (file)
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -77,10 +77,16 @@
 #include <asm/processor.h>
 #include <pci.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
 
 #ifdef CONFIG_PCI
 
+#if defined(CONFIG_PMC405)
+ushort pmc405_pci_subsys_deviceid(void);
+#endif
+
 /*#define DEBUG*/
 
 /*-----------------------------------------------------------------------------+
@@ -88,21 +94,16 @@
  *-----------------------------------------------------------------------------*/
 void pci_405gp_init(struct pci_controller *hose)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int i, reg_num = 0;
        bd_t *bd = gd->bd;
 
        unsigned short temp_short;
        unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
 #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
-       unsigned long ptmla[2]    = {bd->bi_memstart, bd->bi_flashstart};
-       unsigned long ptmms[2]    = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1};
        char *ptmla_str, *ptmms_str;
-#else
+#endif
        unsigned long ptmla[2]    = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
        unsigned long ptmms[2]    = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
-#endif
 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
        unsigned long pmmla[3]    = {0x80000000, 0xA0000000, 0};
        unsigned long pmmma[3]    = {0xE0000001, 0xE0000001, 0};
@@ -372,7 +373,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
 {
        unsigned int cmdstat = 0;
 
-       pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
+       pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
 
        /* always enable io space on vga boards */
        pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);

diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index a26533c59c7e553e94143138f30cc623f2a6abe0..0cd72b00a18ea9aacb9ff4f2671cdaacb869a473 100644 (file)
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -37,6 +37,10 @@
 #include <asm/cache.h>
 #include <ppc4xx.h>
 
+#if !defined(CONFIG_405)
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 
 #if defined(CONFIG_440)
 #define FREQ_EBC               (sys_info.freqEPB)
@@ -116,7 +120,6 @@ static int do_chip_reset(unsigned long sys0, unsigned long sys1);
 int checkcpu (void)
 {
 #if !defined(CONFIG_405)       /* not used on Xilinx 405 FPGA implementations */
-       DECLARE_GLOBAL_DATA_PTR;
        uint pvr = get_pvr();
        ulong clock = gd->cpu_clk;
        char buf[32];

diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index 79cfba3a4511d1892c967e012ba5b352b5878a55..1a139d739eccee84e937ed6df81004967f8cd3ec 100644 (file)
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -27,6 +27,10 @@
 #include <asm/processor.h>
 #include <ppc4xx.h>
 
+#if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 
 #define mtebc(reg, data)  mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
 
@@ -209,8 +213,6 @@ cpu_init_f (void)
 int cpu_init_r (void)
 {
 #if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
-       DECLARE_GLOBAL_DATA_PTR;
-
        bd_t *bd = gd->bd;
        unsigned long reg;
 #if defined(CONFIG_405GP)

diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c
index be94b571ff20ba2f0ab7586237cd7d5769c58bc7..7db1cd8046b3c29d7fd5693faaa35208c0242072 100644 (file)
--- a/cpu/ppc4xx/i2c.c
+++ b/cpu/ppc4xx/i2c.c
@@ -16,6 +16,8 @@
 
 #ifdef CONFIG_HARD_I2C
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define IIC_OK         0
 #define IIC_NOK                1
 #define IIC_NOK_LA     2               /* Lost arbitration */
@@ -350,7 +352,6 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
 {
        uchar xaddr[4];
        int ret;
-       DECLARE_GLOBAL_DATA_PTR;
 
        if ( alen > 4 ) {
                printf ("I2C read: addr len %d not supported\n", alen);

diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 1d8dc7c221deb4be50465424e94f46cc29a00875..3aae4ce8b997e6be4b0ddd40d7c49f3db89101fc 100644 (file)
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -36,6 +36,8 @@
 #include <commproc.h>
 #include "vecnum.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /****************************************************************************/
 
 /*
@@ -96,8 +98,6 @@ static __inline__ void set_evpr(unsigned long val)
 
 int interrupt_init_cpu (unsigned *decrementer_count)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int vec;
        unsigned long val;
 

diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index e9548cdcf3dff7fb1fbe464b6dd245ef2a3da5ad..e31d59d80ea5c58ea3fb5c8d74789f5bd2391f49 100644 (file)
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -1,7 +1,10 @@
 /*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2006
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
+ * (C) Copyright 2006
+ * DAVE Srl <www.dave-tech.it>
+ *
  * (C) Copyright 2002-2004
  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  *
@@ -15,7 +18,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -27,63 +30,161 @@
 #include <common.h>
 #include <ppc4xx.h>
 #include <asm/processor.h>
+#include "sdram.h"
 
 
 #ifdef CONFIG_SDRAM_BANK0
 
 
-#define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
-
-
-struct sdram_conf_s {
-       unsigned long size;
-       unsigned long reg;
-};
-
-typedef struct sdram_conf_s sdram_conf_t;
-
 #ifndef CFG_SDRAM_TABLE
 sdram_conf_t mb0cf[] = {
-       {(128 << 20), 0x000A4001},      /* (0-128MB) Address Mode 3, 13x10(4) */
-       {(64 << 20),  0x00084001},      /* (0-64MB) Address Mode 3, 13x9(4)   */
-       {(32 << 20),  0x00062001},      /* (0-32MB) Address Mode 2, 12x9(4)   */
-       {(16 << 20),  0x00046001},      /* (0-16MB) Address Mode 4, 12x8(4)   */
-       {(4 << 20),   0x00008001},      /* (0-4MB) Address Mode 5, 11x8(2)    */
+       {(128 << 20), 13, 0x000A4001},      /* (0-128MB) Address Mode 3, 13x10(4) */
+       {(64 << 20),  13, 0x00084001},      /* (0-64MB) Address Mode 3, 13x9(4)   */
+       {(32 << 20),  12, 0x00062001},      /* (0-32MB) Address Mode 2, 12x9(4)   */
+       {(16 << 20),  12, 0x00046001},      /* (0-16MB) Address Mode 4, 12x8(4)   */
+       {(4 << 20),   11, 0x00008001},      /* (0-4MB) Address Mode 5, 11x8(2)    */
 };
 #else
 sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
 #endif
 
-#define        N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
 
 
 #ifndef CONFIG_440
 
-/*
- * Autodetect onboard SDRAM on 405 platforms
- */
-void sdram_init(void)
+#ifdef CFG_SDRAM_CASL
+static ulong ns2clks(ulong ns)
 {
-       ulong sdtr1;
-       ulong rtr;
-       int i;
+       ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10);
 
+       return ((ns * 10) + bus_period_x_10) / bus_period_x_10;
+}
+#endif /* CFG_SDRAM_CASL */
+
+static ulong compute_sdtr1(ulong speed)
+{
+#ifdef CFG_SDRAM_CASL
+       ulong tmp;
+       ulong sdtr1 = 0;
+
+       /* CASL */
+       if (CFG_SDRAM_CASL < 2)
+               sdtr1 |= (1 << SDRAM0_TR_CASL);
+       else
+               if (CFG_SDRAM_CASL > 4)
+                       sdtr1 |= (3 << SDRAM0_TR_CASL);
+               else
+                       sdtr1 |= ((CFG_SDRAM_CASL-1) << SDRAM0_TR_CASL);
+
+       /* PTA */
+       tmp = ns2clks(CFG_SDRAM_PTA);
+       if ((tmp >= 2) && (tmp <= 4))
+               sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA);
+       else
+               sdtr1 |= ((4-1) << SDRAM0_TR_PTA);
+
+       /* CTP */
+       tmp = ns2clks(CFG_SDRAM_CTP);
+       if ((tmp >= 2) && (tmp <= 4))
+               sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP);
+       else
+               sdtr1 |= ((4-1) << SDRAM0_TR_CTP);
+
+       /* LDF */
+       tmp = ns2clks(CFG_SDRAM_LDF);
+       if ((tmp >= 2) && (tmp <= 4))
+               sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF);
+       else
+               sdtr1 |= ((2-1) << SDRAM0_TR_LDF);
+
+       /* RFTA */
+       tmp = ns2clks(CFG_SDRAM_RFTA);
+       if ((tmp >= 4) && (tmp <= 10))
+               sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA);
+       else
+               sdtr1 |= ((10-4) << SDRAM0_TR_RFTA);
+
+       /* RCD */
+       tmp = ns2clks(CFG_SDRAM_RCD);
+       if ((tmp >= 2) && (tmp <= 4))
+               sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD);
+       else
+               sdtr1 |= ((4-1) << SDRAM0_TR_RCD);
+
+       return sdtr1;
+#else /* CFG_SDRAM_CASL */
        /*
-        * Support for 100MHz and 133MHz SDRAM
+        * If no values are configured in the board config file
+        * use the default values, which seem to be ok for most
+        * boards.
+        *
+        * REMARK:
+        * For new board ports we strongly recommend to define the
+        * correct values for the used SDRAM chips in your board
+        * config file (see PPChameleonEVB.h)
         */
-       if (get_bus_freq(0) > 100000000) {
+       if (speed > 100000000) {
                /*
                 * 133 MHz SDRAM
                 */
-               sdtr1 = 0x01074015;
-               rtr = 0x07f00000;
+               return 0x01074015;
        } else {
                /*
                 * default: 100 MHz SDRAM
                 */
-               sdtr1 = 0x0086400d;
-               rtr = 0x05f00000;
+               return 0x0086400d;
        }
+#endif /* CFG_SDRAM_CASL */
+}
+
+/* refresh is expressed in ms */
+static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
+{
+#ifdef CFG_SDRAM_CASL
+       ulong tmp;
+
+       tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000);
+       tmp /= 1000000;
+
+       return ((tmp & 0x00003FF8) << 16);
+#else /* CFG_SDRAM_CASL */
+       if (speed > 100000000) {
+               /*
+                * 133 MHz SDRAM
+                */
+               return 0x07f00000;
+       } else {
+               /*
+                * default: 100 MHz SDRAM
+                */
+               return 0x05f00000;
+       }
+#endif /* CFG_SDRAM_CASL */
+}
+
+/*
+ * Autodetect onboard SDRAM on 405 platforms
+ */
+void sdram_init(void)
+{
+       ulong speed;
+       ulong sdtr1;
+       int i;
+
+       /*
+        * Determine SDRAM speed
+        */
+       speed = get_bus_freq(0); /* parameter not used on ppc4xx */
+
+       /*
+        * sdtr1 (register SDRAM0_TR) must take into account timings listed
+        * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into
+        * account actual SDRAM size. So we can set up sdtr1 according to what
+        * is specified in board configuration file while rtr dependds on SDRAM
+        * size we are assuming before detection.
+        */
+       sdtr1 = compute_sdtr1(speed);
 
        for (i=0; i<N_MB0CF; i++) {
                /*
@@ -96,7 +197,7 @@ void sdram_init(void)
                 */
                mtsdram0(mem_mb0cf, mb0cf[i].reg);
                mtsdram0(mem_sdtr1, sdtr1);
-               mtsdram0(mem_rtr, rtr);
+               mtsdram0(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
 
                udelay(200);
 
@@ -120,16 +221,135 @@ void sdram_init(void)
 
 #else /* CONFIG_440 */
 
+#define NUM_TRIES 64
+#define NUM_READS 10
+
+static void sdram_tr1_set(int ram_address, int* tr1_value)
+{
+       int i;
+       int j, k;
+       volatile unsigned int* ram_pointer = (unsigned int *)ram_address;
+       int first_good = -1, last_bad = 0x1ff;
+
+       unsigned long test[NUM_TRIES] = {
+               0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+               0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+               0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+               0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+               0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+               0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+               0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+               0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+               0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+               0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+               0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+               0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+               0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+               0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+               0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+               0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
+
+       /* go through all possible SDRAM0_TR1[RDCT] values */
+       for (i=0; i<=0x1ff; i++) {
+               /* set the current value for TR1 */
+               mtsdram(mem_tr1, (0x80800800 | i));
+
+               /* write values */
+               for (j=0; j<NUM_TRIES; j++) {
+                       ram_pointer[j] = test[j];
+
+                       /* clear any cache at ram location */
+                       __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+               }
+
+               /* read values back */
+               for (j=0; j<NUM_TRIES; j++) {
+                       for (k=0; k<NUM_READS; k++) {
+                               /* clear any cache at ram location */
+                               __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+
+                               if (ram_pointer[j] != test[j])
+                                       break;
+                       }
+
+                       /* read error */
+                       if (k != NUM_READS)
+                               break;
+               }
+
+               /* we have a SDRAM0_TR1[RDCT] that is part of the window */
+               if (j == NUM_TRIES) {
+                       if (first_good == -1)
+                               first_good = i;         /* found beginning of window */
+               } else { /* bad read */
+                       /* if we have not had a good read then don't care */
+                       if (first_good != -1) {
+                               /* first failure after a good read */
+                               last_bad = i-1;
+                               break;
+                       }
+               }
+       }
+
+       /* return the current value for TR1 */
+       *tr1_value = (first_good + last_bad) / 2;
+}
+
+
+#ifdef CONFIG_SDRAM_ECC
+static void ecc_init(ulong start, ulong size)
+{
+       ulong   current_addr;           /* current byte address */
+       ulong   end_addr;               /* end of memory region */
+       ulong   addr_inc;               /* address skip between writes */
+       ulong   cfg0_reg;               /* for restoring ECC state */
+
+       /*
+        * TODO: Enable dcache before running this test (speedup)
+        */
+
+       mfsdram(mem_cfg0, cfg0_reg);
+       mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_GEN);
+
+       /*
+        * look at geometry of SDRAM (data width) to determine whether we
+        * can skip words when writing
+        */
+       if ((cfg0_reg & SDRAM_CFG0_DRAMWDTH) == SDRAM_CFG0_DRAMWDTH_32)
+               addr_inc = 4;
+       else
+               addr_inc = 8;
+
+       current_addr = start;
+       end_addr = start + size;
+
+       while (current_addr < end_addr) {
+               *((ulong *)current_addr) = 0x00000000;
+               current_addr += addr_inc;
+       }
+
+       /*
+        * TODO: Flush dcache and disable it again
+        */
+
+       /*
+        * Enable ecc checking and parity errors
+        */
+       mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_CHK);
+}
+#endif
+
 /*
  * Autodetect onboard DDR SDRAM on 440 platforms
  *
  * NOTE: Some of the hardcoded values are hardware dependant,
- *       so this should be extended for other future boards
- *       using this routine!
+ *      so this should be extended for other future boards
+ *      using this routine!
  */
 long int initdram(int board_type)
 {
        int i;
+       int tr1_bank1;
 
        for (i=0; i<N_MB0CF; i++) {
                /*
@@ -140,11 +360,11 @@ long int initdram(int board_type)
                /*
                 * Setup some default
                 */
-               mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default)             */
-               mtsdram(mem_slio, 0x00000000);  /* rdre=0 wrre=0 rarw=0         */
+               mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default)             */
+               mtsdram(mem_slio, 0x00000000);  /* rdre=0 wrre=0 rarw=0         */
                mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal)         */
                mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0                */
-               mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0    */
+               mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0    */
 
                /*
                 * Following for CAS Latency = 2.5 @ 133 MHz PLB
@@ -159,10 +379,20 @@ long int initdram(int board_type)
                /*
                 * Enable the controller, then wait for DCEN to complete
                 */
-               mtsdram(mem_cfg0, 0x86000000);  /* DCEN=1, PMUD=1, 64-bit       */
+               mtsdram(mem_cfg0, 0x86000000);  /* DCEN=1, PMUD=1, 64-bit       */
                udelay(10000);
 
                if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
+                       /*
+                        * Optimize TR1 to current hardware environment
+                        */
+                       sdram_tr1_set(0x00000000, &tr1_bank1);
+                       mtsdram(mem_tr1, (tr1_bank1 | 0x80800800));
+
+#ifdef CONFIG_SDRAM_ECC
+                       ecc_init(0, mb0cf[i].size);
+#endif
+
                        /*
                         * OK, size detected -> all done
                         */

diff --git a/cpu/ppc4xx/sdram.h b/cpu/ppc4xx/sdram.h
new file mode 100644 (file)
index 0000000..62b5442
--- /dev/null
+++ b/cpu/ppc4xx/sdram.h
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * DAVE Srl <www.dave-tech.it>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SDRAM_H_
+#define _SDRAM_H_
+
+#include <config.h>
+
+#define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
+
+#define ONE_BILLION    1000000000
+
+struct sdram_conf_s {
+       unsigned long size;
+       int rows;
+       unsigned long reg;
+};
+
+typedef struct sdram_conf_s sdram_conf_t;
+
+/* Bitfields offsets */
+#define SDRAM0_TR_CASL         (31 - 8)
+#define SDRAM0_TR_PTA          (31 - 13)
+#define SDRAM0_TR_CTP          (31 - 15)
+#define SDRAM0_TR_LDF          (31 - 17)
+#define SDRAM0_TR_RFTA         (31 - 29)
+#define SDRAM0_TR_RCD          (31 - 31)
+
+#ifdef CFG_SDRAM_CL
+/* SDRAM timings [ns] according to AMCC/IBM names (see SDRAM_faq.doc) */
+#define CFG_SDRAM_CASL         CFG_SDRAM_CL
+#define CFG_SDRAM_PTA          CFG_SDRAM_tRP
+#define CFG_SDRAM_CTP          (CFG_SDRAM_tRC - CFG_SDRAM_tRCD - CFG_SDRAM_tRP)
+#define CFG_SDRAM_LDF          0
+#ifdef CFG_SDRAM_tRFC
+#define CFG_SDRAM_RFTA         CFG_SDRAM_tRFC
+#else
+#define CFG_SDRAM_RFTA         CFG_SDRAM_tRC
+#endif
+#define CFG_SDRAM_RCD          CFG_SDRAM_tRCD
+#endif /* #ifdef CFG_SDRAM_CL */
+
+/*
+ * Some defines for the 440 DDR controller
+ */
+#define SDRAM_CFG0_DC_EN       0x80000000      /* SDRAM Controller Enable      */
+#define SDRAM_CFG0_MEMCHK      0x30000000      /* Memory data error checking mask*/
+#define SDRAM_CFG0_MEMCHK_NON  0x00000000      /* No ECC generation            */
+#define SDRAM_CFG0_MEMCHK_GEN  0x20000000      /* ECC generation               */
+#define SDRAM_CFG0_MEMCHK_CHK  0x30000000      /* ECC generation and checking  */
+#define SDRAM_CFG0_DRAMWDTH    0x02000000      /* DRAM width mask              */
+#define SDRAM_CFG0_DRAMWDTH_32 0x00000000      /* 32 bits                      */
+#define SDRAM_CFG0_DRAMWDTH_64 0x02000000      /* 64 bits                      */
+
+#endif

diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c
index e7f6bcbe1e8bed440382e9556d272ba3c7eda1c0..83c947998ed51f81370f21558940dcc92e4a7003 100644 (file)
--- a/cpu/ppc4xx/serial.c
+++ b/cpu/ppc4xx/serial.c
@@ -59,6 +59,8 @@
 #include <malloc.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*****************************************************************************/
 #ifdef CONFIG_IOP480
 
@@ -161,8 +163,6 @@
 
 int serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile char val;
        unsigned short br_reg;
 
@@ -185,8 +185,6 @@ int serial_init (void)
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned short br_reg;
 
        br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
@@ -431,8 +429,6 @@ int serial_init_dev (unsigned long dev_base)
 int serial_init(void)
 #endif
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long reg;
        unsigned long udiv;
        unsigned short bdiv;
@@ -520,8 +516,6 @@ int serial_init_dev (unsigned long dev_base)
 int serial_init (void)
 #endif
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long reg;
        unsigned long tmp;
        unsigned long clk;
@@ -597,8 +591,6 @@ void serial_setbrg_dev (unsigned long dev_base)
 void serial_setbrg (void)
 #endif
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long tmp;
        unsigned long clk;
        unsigned long udiv;
@@ -880,8 +872,6 @@ int serial_buffered_tstc (void)
 #if (CONFIG_KGDB_SER_INDEX & 2)
 void kgdb_serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile char val;
        unsigned short br_reg;
 

diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 553c491e245bab4a6527ac8fab12f3ec29b3f2a6..02b43832f24a2b39eddedb3b17fd7b1b1a9c5a5f 100644 (file)
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -26,7 +26,7 @@
 #include <ppc4xx.h>
 #include <asm/processor.h>
 
-/* ------------------------------------------------------------------------- */
+DECLARE_GLOBAL_DATA_PTR;
 
 #define ONE_BILLION        1000000000
 
@@ -522,8 +522,6 @@ ulong get_PCI_freq (void)
 int get_clocks (void)
 {
 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP)
-       DECLARE_GLOBAL_DATA_PTR;
-
        sys_info_t sys_info;
 
        get_sys_info (&sys_info);
@@ -533,8 +531,6 @@ int get_clocks (void)
 #endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
 
 #ifdef CONFIG_IOP480
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->cpu_clk = 66000000;
        gd->bus_clk = 66000000;
 #endif

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 48b430d14d8583042f68dd2741fba99326f8fa9b..948de43d1429b86fd3a943a3d15c4afac6c496c6 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -340,23 +340,6 @@ _start:
        mtspr   tcr,r0                  /* disable all */
        mtspr   esr,r0                  /* clear exception syndrome register */
        mtxer   r0                      /* clear integer exception register */
-#if !defined(CONFIG_440GX)
-       lis     r1,0x0002               /* set CE bit (Critical Exceptions) */
-       ori     r1,r1,0x1000            /* set ME bit (Machine Exceptions) */
-       mtmsr   r1                      /* change MSR */
-#elif !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
-       bl      __440gx_msr_set
-       b       __440gx_msr_continue
-
-__440gx_msr_set:
-       lis     r1, 0x0002              /* set CE bit (Critical Exceptions) */
-       ori     r1,r1,0x1000    /* set ME bit (Machine Exceptions) */
-       mtspr   srr1,r1
-       mflr    r1
-       mtspr   srr0,r1
-       rfi
-__440gx_msr_continue:
-#endif
 
        /*----------------------------------------------------------------*/
        /* Debug setup -- some (not very good) ice's need an event*/
@@ -458,9 +441,6 @@ __440gx_msr_continue:
        mtspr   esr,r0                  /* clear Exception Syndrome Reg */
        mttcr   r0                      /* timer control register */
        mtexier r0                      /* disable all interrupts */
-       addi    r4,r0,0x1000            /* set ME bit (Machine Exceptions) */
-       oris    r4,r4,0x2               /* set CE bit (Critical Exceptions) */
-       mtmsr   r4                      /* change MSR */
        addis   r4,r0,0xFFFF            /* set r4 to 0xFFFFFFFF (status in the */
        ori     r4,r4,0xFFFF            /* dbsr is cleared by setting bits to 1) */
        mtdbsr  r4                      /* clear/reset the dbsr */
@@ -571,9 +551,6 @@ __440gx_msr_continue:
        mttcr   r4                      /* clear Timer Control Reg */
        mtxer   r4                      /* clear Fixed-Point Exception Reg */
        mtevpr  r4                      /* clear Exception Vector Prefix Reg */
-       addi    r4,r0,0x1000            /* set ME bit (Machine Exceptions) */
-       oris    r4,r4,0x0002            /* set CE bit (Critical Exceptions) */
-       mtmsr   r4                      /* change MSR */
        addi    r4,r0,(0xFFFF-0x10000)          /* set r4 to 0xFFFFFFFF (status in the */
                                        /* dbsr is cleared by setting bits to 1) */
        mtdbsr  r4                      /* clear/reset the dbsr */
@@ -1428,6 +1405,24 @@ trap_init:
        cmplw   0, r7, r8
        blt     4b
 
+#if !defined(CONFIG_440_GX)
+       addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
+       oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
+       mtmsr   r7                      /* change MSR */
+#else
+       bl      __440gx_msr_set
+       b       __440gx_msr_continue
+
+__440gx_msr_set:
+       addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
+       oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
+       mtspr   srr1,r7
+       mflr    r7
+       mtspr   srr0,r7
+       rfi
+__440gx_msr_continue:
+#endif
+
        mtlr    r4                      /* restore link register        */
        blr
 

diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c
index d1551ddc386c7d18b88faa406cae83cbc33a0f8f..0ee8180361f5f43e5fcbb066d52d6e87e211a9e1 100644 (file)
--- a/cpu/pxa/cpu.c
+++ b/cpu/pxa/cpu.c
@@ -34,14 +34,16 @@
 #include <command.h>
 #include <asm/arch/pxa-regs.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 int cpu_init (void)
 {
        /*
         * setup up stacks if necessary
         */
 #ifdef CONFIG_USE_IRQ
-       DECLARE_GLOBAL_DATA_PTR;
-
        IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
        FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
@@ -143,6 +145,7 @@ int dcache_status (void)
        return 0;                                       /* always off */
 }
 
+#ifndef CONFIG_CPU_MONAHANS
 void set_GPIO_mode(int gpio_mode)
 {
        int gpio = gpio_mode & GPIO_MD_MASK_NR;
@@ -160,3 +163,4 @@ void set_GPIO_mode(int gpio_mode)
        gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
        GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
 }
+#endif /* CONFIG_CPU_MONAHANS */

diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c
index b6155b137edbdb96634c10e29b29e1dde4762177..722d949473f5a81bc3796bf682306665d48303f9 100644 (file)
--- a/cpu/pxa/i2c.c
+++ b/cpu/pxa/i2c.c
@@ -47,7 +47,13 @@
 
 /*#define      DEBUG_I2C       1       /###* activate local debugging output  */
 #define I2C_PXA_SLAVE_ADDR     0x1     /* slave pxa unit address           */
-#define I2C_ICR_INIT           (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
+
+#if (CFG_I2C_SPEED == 400000)
+#define I2C_ICR_INIT   (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
+#else
+#define I2C_ICR_INIT   (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
+#endif
+
 #define I2C_ISR_INIT           0x7FF
 
 #ifdef DEBUG_I2C
@@ -91,7 +97,11 @@ static void i2c_reset( void )
        ICR |= ICR_UR;                  /* reset the unit */
        udelay(100);
        ICR &= ~ICR_IUE;                /* disable unit */
+#ifdef CONFIG_CPU_MONAHANS
+       CKENB |= (CKENB_4_I2C); /*  | CKENB_1_PWM1 | CKENB_0_PWM0); */
+#else /* CONFIG_CPU_MONAHANS */
        CKEN |= CKEN14_I2C;             /* set the global I2C clock on */
+#endif
        ISAR = I2C_PXA_SLAVE_ADDR;      /* set our slave address */
        ICR = I2C_ICR_INIT;             /* set control register values */
        ISR = I2C_ISR_INIT;             /* set clear interrupt bits */
@@ -104,9 +114,8 @@ static void i2c_reset( void )
  * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
  *                       are set and cleared
  *
- * @return: 0 in case of success, 1 means timeout (no match within 10 ms).
+ * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
  */
-
 static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask )
 {
        int timeout = 10000;
@@ -360,9 +369,9 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
                msg.data      = 0x00;
                if ((ret=i2c_transfer(&msg))) return -1;
 
-               *(buffer++) = msg.data;
-
+               *buffer = msg.data;
                PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer));
+               buffer++;
 
        }
 

diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c
index cedebfe496bc257bffea7f56c781e97be9654802..cb3a4789901a47baaaa57ed54e88f9dfac3e61e5 100644 (file)
--- a/cpu/pxa/serial.c
+++ b/cpu/pxa/serial.c
@@ -32,10 +32,10 @@
 #include <watchdog.h>
 #include <asm/arch/pxa-regs.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned int quot = 0;
 
        if (gd->baudrate == 1200)
@@ -54,7 +54,11 @@ void serial_setbrg (void)
                hang ();
 
 #ifdef CONFIG_FFUART
+#ifdef CONFIG_CPU_MONAHANS
+       CKENA |= CKENA_22_FFUART;
+#else
        CKEN |= CKEN6_FFUART;
+#endif /* CONFIG_CPU_MONAHANS */
 
        FFIER = 0;                                      /* Disable for now */
        FFFCR = 0;                                      /* No fifos enabled */
@@ -68,7 +72,11 @@ void serial_setbrg (void)
        FFIER = IER_UUE;                        /* Enable FFUART */
 
 #elif defined(CONFIG_BTUART)
+#ifdef CONFIG_CPU_MONAHANS
+       CKENA |= CKENA_21_BTUART;
+#else
        CKEN |= CKEN7_BTUART;
+#endif /*  CONFIG_CPU_MONAHANS */
 
        BTIER = 0;
        BTFCR = 0;
@@ -82,7 +90,11 @@ void serial_setbrg (void)
        BTIER = IER_UUE;                        /* Enable BFUART */
 
 #elif defined(CONFIG_STUART)
+#ifdef CONFIG_CPU_MONAHANS
+       CKENA |= CKENA_23_STUART;
+#else
        CKEN |= CKEN5_STUART;
+#endif /* CONFIG_CPU_MONAHANS */
 
        STIER = 0;
        STFCR = 0;

diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S
index a8cc0800b0ca48ad8e7cb7323789c4137c8c2ec0..ffaa30fdc585417e35c6a234ee8e437ff11533ad 100644 (file)
--- a/cpu/pxa/start.S
+++ b/cpu/pxa/start.S
@@ -6,8 +6,8 @@
  *  Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
  *  Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
  *  Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
- *  Copyright (C) 2003  Robert Schwebel <r.schwebel@pengutronix.de>
- *  Copyright (C) 2003  Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
+ *  Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *  Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -30,6 +30,7 @@
 
 #include <config.h>
 #include <version.h>
+#include <asm/arch/pxa-regs.h>
 
 .globl _start
 _start: b      reset
@@ -116,13 +117,13 @@ reset:
 relocate:                              /* relocate U-Boot to RAM           */
        adr     r0, _start              /* r0 <- current position of code   */
        ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
-       cmp     r0, r1                  /* don't reloc during debug         */
-       beq     stack_setup
+       cmp     r0, r1                  /* don't reloc during debug         */
+       beq     stack_setup
 
        ldr     r2, _armboot_start
        ldr     r3, _bss_start
-       sub     r2, r3, r2              /* r2 <- size of armboot            */
-       add     r2, r0, r2              /* r2 <- source end address         */
+       sub     r2, r3, r2              /* r2 <- size of armboot            */
+       add     r2, r0, r2              /* r2 <- source end address         */
 
 copy_loop:
        ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
@@ -134,19 +135,19 @@ copy_loop:
        /* Set up the stack                                                 */
 stack_setup:
        ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
-       sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
-       sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
+       sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
+       sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
 #ifdef CONFIG_USE_IRQ
        sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 #endif
        sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 
 clear_bss:
-       ldr     r0, _bss_start          /* find start of bss segment        */
-       ldr     r1, _bss_end            /* stop here                        */
-       mov     r2, #0x00000000         /* clear                            */
+       ldr     r0, _bss_start          /* find start of bss segment        */
+       ldr     r1, _bss_end            /* stop here                        */
+       mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:str    r2, [r0]                /* clear loop...                    */
        add     r0, r0, #4
        cmp     r0, r1
        ble     clbss_l
@@ -164,8 +165,16 @@ _start_armboot: .word start_armboot
 /* - setup memory timing                                                   */
 /*                                                                         */
 /****************************************************************************/
+/* mk@tbd: Fix this! */
+#ifdef CONFIG_CPU_MONAHANS
+#undef ICMR
+#undef OSMR3
+#undef OSCR
+#undef OWER
+#undef OIER
+#endif
 
-/* Interrupt-Controller base address                                       */
+/* Interrupt-Controller base address                                       */
 IC_BASE:          .word           0x40d00000
 #define ICMR   0x04
 
@@ -180,7 +189,15 @@ OSTIMER_BASE:      .word   0x40a00000
 #define OWER   0x18
 #define OIER   0x1C
 
-/* Clock Manager Registers                                                 */
+/* Clock Manager Registers                                                 */
+#ifdef CONFIG_CPU_MONAHANS
+# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO
+#  error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!"
+# endif
+# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO
+#  define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
+# endif
+#else /* ! CONFIG_CPU_MONAHANS */
 #ifdef CFG_CPUSPEED
 CC_BASE:       .word   0x41300000
 #define CCCR   0x00
@@ -188,26 +205,50 @@ cpuspeed: .word   CFG_CPUSPEED
 #else
 #error "You have to define CFG_CPUSPEED!!"
 #endif
+#endif /* CONFIG_CPU_MONAHANS */
 
-
-       /* RS: ???                                                          */
-       .macro CPWAIT
-       mrc  p15,0,r0,c2,c0,0
-       mov  r0,r0
+       /* takes care the CP15 update has taken place */
+       .macro CPWAIT reg
+       mrc  p15,0,\reg,c2,c0,0
+       mov  \reg,\reg
        sub  pc,pc,#4
        .endm
 
-
 cpu_init_crit:
 
        /* mask all IRQs                                                    */
+#ifndef CONFIG_CPU_MONAHANS
        ldr     r0, IC_BASE
        mov     r1, #0x00
        str     r1, [r0, #ICMR]
-
-#if defined(CFG_CPUSPEED)
+#else
+       /* Step 1 - Enable CP6 permission */
+       mrc     p15, 0, r1, c15, c1, 0  @ read CPAR
+       orr     r1, r1, #0x40
+               mcr     p15, 0, r1, c15, c1, 0
+       CPWAIT  r1
+
+       /* Step 2 - Mask ICMR & ICMR2 */
+       mov     r1, #0
+       mcr     p6, 0, r1, c1, c0, 0    @ ICMR
+       mcr     p6, 0, r1, c7, c0, 0    @ ICMR2
+
+       /* turn off all clocks but the ones we will definitly require */
+       ldr     r1, =CKENA
+       ldr     r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
+       str     r2, [r1]
+       ldr     r1, =CKENB
+       ldr     r2, =(CKENB_6_IRQ)
+       str     r2, [r1]
+#endif
 
        /* set clock speed */
+#ifdef CONFIG_CPU_MONAHANS
+       ldr     r0, =ACCR
+       ldr     r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
+       str     r1, [r0]
+#else /* ! CONFIG_CPU_MONAHANS */
+#ifdef CFG_CPUSPEED
        ldr     r0, CC_BASE
        ldr     r1, cpuspeed
        str     r1, [r0, #CCCR]
@@ -215,7 +256,9 @@ cpu_init_crit:
        mcr     p14, 0, r0, c6, c0, 0
 
 setspeed_done:
-#endif
+
+#endif /* CFG_CPUSPEED */
+#endif /* CONFIG_CPU_MONAHANS */
 
        /*
         * before relocating, we have to setup RAM timing
@@ -227,19 +270,21 @@ setspeed_done:
        mov     lr,     ip
 
        /* Memory interfaces are working. Disable MMU and enable I-cache.   */
+       /* mk: hmm, this is not in the monahans docs, leave it now but
+        *     check here if it doesn't work :-) */
 
        ldr     r0, =0x2001             /* enable access to all coproc.     */
        mcr     p15, 0, r0, c15, c1, 0
-       CPWAIT
+       CPWAIT r0
 
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write & fill buffers   */
-       CPWAIT
+       CPWAIT r0
 
        mcr     p15, 0, r0, c7, c7, 0   /* flush Icache, Dcache and BTB     */
-       CPWAIT
+       CPWAIT r0
 
        mcr     p15, 0, r0, c8, c7, 0   /* flush instuction and data TLBs   */
-       CPWAIT
+       CPWAIT r0
 
        /* Enable the Icache                                                */
 /*
@@ -292,7 +337,7 @@ setspeed_done:
 
        ldr     r2, _armboot_start
        sub     r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
-       sub     r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
+       sub     r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
        ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
        add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 
@@ -419,17 +464,17 @@ fiq:
 #endif
 
 /****************************************************************************/
-/*                                                                          */
+/*                                                                         */
 /* Reset function: the PXA250 doesn't have a reset function, so we have to  */
-/* perform a watchdog timeout for a soft reset.                             */
-/*                                                                          */
+/* perform a watchdog timeout for a soft reset.                                    */
+/*                                                                         */
 /****************************************************************************/
 
        .align  5
 .globl reset_cpu
 
-       /* FIXME: this code is PXA250 specific. How is this handled on      */
-       /*        other XScale processors?                                  */
+       /* FIXME: this code is PXA250 specific. How is this handled on      */
+       /*        other XScale processors?                                  */
 
 reset_cpu:
 
@@ -437,13 +482,13 @@ reset_cpu:
 
        ldr     r0, OSTIMER_BASE
        ldr     r1, [r0, #OWER]
-       orr     r1, r1, #0x0001                 /* bit0: WME                */
+       orr     r1, r1, #0x0001                 /* bit0: WME                */
        str     r1, [r0, #OWER]
 
        /* OS timer does only wrap every 1165 seconds, so we have to set    */
-       /* the match register as well.                                      */
+       /* the match register as well.                                      */
 
-       ldr     r1, [r0, #OSCR]                 /* read OS timer            */
+       ldr     r1, [r0, #OSCR]                 /* read OS timer            */
        add     r1, r1, #0x800                  /* let OSMR3 match after    */
        add     r1, r1, #0x800                  /* 4096*(1/3.6864MHz)=1ms   */
        str     r1, [r0, #OSMR3]

diff --git a/cpu/s3c44b0/serial.c b/cpu/s3c44b0/serial.c
index 70b4ee811c5136e1d393e709acac954268b99952..95d0266c6c675cba1a31f98e8c007d9cae21fa37 100644 (file)
--- a/cpu/s3c44b0/serial.c
+++ b/cpu/s3c44b0/serial.c
@@ -37,6 +37,8 @@
 #include <common.h>
 #include <asm/hardware.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* flush serial input queue. returns 0 on success or negative error
  * number otherwise
  */
@@ -68,8 +70,6 @@ static int serial_flush_output(void)
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        u32 divisor = 0;
 
        /* get correct divisor */

diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c
index 17e5b0d1956888684800661433f60734614be909..f1bd6440933b4bc5edd72f32e08e1312628c4b07 100644 (file)
--- a/cpu/sa1100/cpu.c
+++ b/cpu/sa1100/cpu.c
@@ -33,14 +33,16 @@
 #include <common.h>
 #include <command.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 int cpu_init (void)
 {
        /*
         * setup up stacks if necessary
         */
 #ifdef CONFIG_USE_IRQ
-       DECLARE_GLOBAL_DATA_PTR;
-
        IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
        FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif

diff --git a/cpu/sa1100/serial.c b/cpu/sa1100/serial.c
index a598489df7af6db786b16f1c5039fd11d7b943b3..5d1887580d7f8ed55c75af8c1b994531f33ab9dd 100644 (file)
--- a/cpu/sa1100/serial.c
+++ b/cpu/sa1100/serial.c
@@ -31,10 +31,10 @@
 #include <common.h>
 #include <SA-1100.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned int reg = 0;
 
        if (gd->baudrate == 1200)

diff --git a/doc/README.mpc8349emds.ddrecc b/doc/README.mpc8349emds.ddrecc
new file mode 100644 (file)
index 0000000..eb249c3
--- /dev/null
+++ b/doc/README.mpc8349emds.ddrecc
@@ -0,0 +1,154 @@
+Overview
+========
+
+The overall usage pattern for ECC diagnostic commands is the following:
+
+  * (injecting errors is initially disabled)
+
+  * define inject mask (which tells the DDR controller what type of errors
+    we'll be injecting: single/multiple bit etc.)
+
+  * enable injecting errors - from now on the controller injects errors as
+    indicated in the inject mask
+
+IMPORTANT NOTICE: enabling injecting multiple-bit errors is potentially
+dangerous as such errors are NOT corrected by the controller. Therefore caution
+should be taken when enabling the injection of multiple-bit errors: it is only
+safe when used on a carefully selected memory area and used under control of
+the 'ecc test' command (see example 'Injecting Multiple-Bit Errors' below). In
+particular, when you simply set the multiple-bit errors in inject mask and
+enable injection, U-Boot is very likely to hang quickly as the errors will be
+injected when it accesses its code, data etc.
+
+
+Use cases for DDR 'ecc' command:
+================================
+
+Before executing particular tests reset target board or clear status registers:
+
+=> ecc captureclear
+=> ecc errdetectclr all
+=> ecc sbecnt 0
+
+
+Injecting Single-Bit Errors
+---------------------------
+
+1. Set 1 bit in Data Path Error Inject Mask
+
+=> ecc injectdatahi 1
+
+2. Run test over some memory region
+
+=> ecc test 200000 10
+
+3. Check ECC status
+
+=> ecc status
+...
+Memory Data Path Error Injection Mask High/Low: 00000001 00000000
+...
+Memory Single-Bit Error Management (0..255):
+  Single-Bit Error Threshold: 255
+  Single Bit Error Counter: 16
+...
+Memory Error Detect:
+  Multiple Memory Errors: 0
+  Multiple-Bit Error: 0
+  Single-Bit Error: 0
+...
+
+16 errors were generated, Single-Bit Error flag was not set as Single Bit Error
+Counter did not reach  Single-Bit Error Threshold.
+
+4. Make sure used memory region got re-initialized with 0xcafecafe pattern
+
+=> md 200000
+00200000: cafecafe cafecafe cafecafe cafecafe    ................
+00200010: cafecafe cafecafe cafecafe cafecafe    ................
+00200020: cafecafe cafecafe cafecafe cafecafe    ................
+00200030: cafecafe cafecafe cafecafe cafecafe    ................
+00200040: cafecafe cafecafe cafecafe cafecafe    ................
+00200050: cafecafe cafecafe cafecafe cafecafe    ................
+00200060: cafecafe cafecafe cafecafe cafecafe    ................
+00200070: cafecafe cafecafe cafecafe cafecafe    ................
+00200080: deadbeef deadbeef deadbeef deadbeef    ................
+00200090: deadbeef deadbeef deadbeef deadbeef    ................
+
+
+Injecting Multiple-Bit Errors
+-----------------------------
+
+1. Set more than 1 bit in Data Path Error Inject Mask
+
+=> ecc injectdatahi 5
+
+2. Run test over some memory region
+
+=> ecc test 200000 10
+
+3. Check ECC status
+
+=> ecc status
+...
+Memory Data Path Error Injection Mask High/Low: 00000005 00000000
+...
+Memory Error Detect:
+  Multiple Memory Errors: 1
+  Multiple-Bit Error: 1
+  Single-Bit Error: 0
+...
+
+Observe that both Multiple Memory Errors and Multiple-Bit Error flags are set.
+
+4. Make sure used memory region got re-initialized with 0xcafecafe pattern
+
+=> md 200000
+00200000: cafecafe cafecafe cafecafe cafecafe    ................
+00200010: cafecafe cafecafe cafecafe cafecafe    ................
+00200020: cafecafe cafecafe cafecafe cafecafe    ................
+00200030: cafecafe cafecafe cafecafe cafecafe    ................
+00200040: cafecafe cafecafe cafecafe cafecafe    ................
+00200050: cafecafe cafecafe cafecafe cafecafe    ................
+00200060: cafecafe cafecafe cafecafe cafecafe    ................
+00200070: cafecafe cafecafe cafecafe cafecafe    ................
+00200080: deadbeef deadbeef deadbeef deadbeef    ................
+00200090: deadbeef deadbeef deadbeef deadbeef    ................
+
+
+Test Single-Bit Error Counter and Threshold
+-------------------------------------------
+
+1. Set 1 bit in Data Path Error Inject Mask
+
+=> ecc injectdatahi 1
+
+2. Enable error injection
+
+=> ecc inject en
+
+3. Let u-boot run for a with Single-Bit error injection enabled
+
+4. Disable error injection
+
+=> ecc inject dis
+
+4. Check status
+
+=> ecc status
+
+...
+Memory Single-Bit Error Management (0..255):
+  Single-Bit Error Threshold: 255
+  Single Bit Error Counter: 60
+
+Memory Error Detect:
+  Multiple Memory Errors: 1
+  Multiple-Bit Error: 0
+  Single-Bit Error: 1
+...
+
+Observe that Single-Bit Error is 'on' which means that Single-Bit Error Counter
+reached Single-Bit Error Threshold. Multiple Memory Errors bit is also 'on', that
+is Counter reached Threshold more than one time (it wraps back after reaching
+Threshold).

diff --git a/doc/README.nand b/doc/README.nand
index 0f2bdc5cc49f2adf1a26239422583a4a93a6287f..f2d6a5b1e6599db8caaef92a0eb399a7eaba0652 100644 (file)
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -1,5 +1,9 @@
 NAND FLASH commands and notes
 
+
+See NOTE below!!!
+
+
 # (C) Copyright 2003
 # Dave Ellis, SIXNET, dge@sixnetio.com
 #
@@ -173,3 +177,33 @@ More Definitions:
    #define NAND_ChipID_UNKNOWN 0x00
    #define NAND_MAX_FLOORS 1
    #define NAND_MAX_CHIPS 1
+
+
+NOTE:
+=====
+
+We now use a complete rewrite of the NAND code based on what is in
+2.6.12 Linux kernel.
+
+The old NAND handling code has been re-factored and is now confined
+to only board-specific files and - unfortunately - to the DoC code
+(see below). A new configuration variable has been introduced:
+CFG_NAND_LEGACY, which has to be defined in the board config file if
+that board uses legacy code. If CFG_NAND_LEGACY is defined, the board
+specific config.mk file should also have "BOARDLIBS =
+drivers/nand_legacy/libnand_legacy.a". For boards using the new NAND
+approach (PPChameleon and netstar at the moment) no variable is
+necessary, but the config.mk should have "BOARDLIBS =
+drivers/nand/libnand.a".
+
+The necessary changes have been made to all affected boards, and no
+build breakage has been introduced, except for NETTA and NETTA_ISDN
+targets from MAKEALL. This is due to the fact that these two boards
+use JFFS, which has been adopted to use the new NAND, and at the same
+time use NAND in legacy mode. The breakage will disappear when the
+board-specific code is changed to the new NAND.
+
+As mentioned above, the legacy code is still used by the DoC subsystem.
+The consequence of this is that the legacy NAND can't be removed  from
+the tree until the DoC is ported to use the new NAND support (or boards
+with DoC will break).

diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c
index 4b7a1107a9a5b6fa905d357c438521f495c91923..2e3748081e369c13d0922fec61ac7114f02ccf91 100644 (file)
--- a/drivers/cfi_flash.c
+++ b/drivers/cfi_flash.c
@@ -104,16 +104,20 @@
 #define AMD_CMD_ERASE_SECTOR           0x30
 #define AMD_CMD_UNLOCK_START           0xAA
 #define AMD_CMD_UNLOCK_ACK             0x55
+#define AMD_CMD_WRITE_TO_BUFFER                0x25
+#define AMD_CMD_WRITE_BUFFER_CONFIRM   0x29
 
 #define AMD_STATUS_TOGGLE              0x40
 #define AMD_STATUS_ERROR               0x20
-#define AMD_ADDR_ERASE_START           0x555
-#define AMD_ADDR_START                 0x555
-#define AMD_ADDR_ACK                   0x2AA
+
+#define AMD_ADDR_ERASE_START   ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555)
+#define AMD_ADDR_START         ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555)
+#define AMD_ADDR_ACK           ((info->portwidth == FLASH_CFI_8BIT) ? 0x555 : 0x2AA)
 
 #define FLASH_OFFSET_CFI               0x55
 #define FLASH_OFFSET_CFI_RESP          0x10
 #define FLASH_OFFSET_PRIMARY_VENDOR    0x13
+#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR        0x15    /* extended query table primary addr */
 #define FLASH_OFFSET_WTOUT             0x1F
 #define FLASH_OFFSET_WBTOUT            0x20
 #define FLASH_OFFSET_ETOUT             0x21
@@ -175,6 +179,13 @@ static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
 flash_info_t flash_info[CFG_MAX_FLASH_BANKS];          /* FLASH chips info */
 #endif
 
+/*
+ * Check if chip width is defined. If not, start detecting with 8bit.
+ */
+#ifndef CFG_FLASH_CFI_WIDTH
+#define CFG_FLASH_CFI_WIDTH    FLASH_CFI_8BIT
+#endif
+
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -190,10 +201,10 @@ static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, u
 static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
 static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
 static int flash_detect_cfi (flash_info_t * info);
-ulong flash_get_size (ulong base, int banknum);
 static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
 static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
                                    ulong tout, char *prompt);
+ulong flash_get_size (ulong base, int banknum);
 #if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
 static flash_info_t *flash_get_info(ulong base);
 #endif
@@ -328,6 +339,7 @@ ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
        return retval;
 }
 
+
 /*-----------------------------------------------------------------------
  */
 unsigned long flash_init (void)
@@ -335,6 +347,10 @@ unsigned long flash_init (void)
        unsigned long size = 0;
        int i;
 
+#ifdef CFG_FLASH_PROTECTION
+       char *s = getenv("unlock");
+#endif
+
        /* Init: no FLASHes known */
        for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
                flash_info[i].flash_id = FLASH_UNKNOWN;
@@ -345,6 +361,48 @@ unsigned long flash_init (void)
                                i, flash_info[i].size, flash_info[i].size << 20);
 #endif /* CFG_FLASH_QUIET_TEST */
                }
+#ifdef CFG_FLASH_PROTECTION
+               else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
+                       /*
+                        * Only the U-Boot image and it's environment is protected,
+                        * all other sectors are unprotected (unlocked) if flash
+                        * hardware protection is used (CFG_FLASH_PROTECTION) and
+                        * the environment variable "unlock" is set to "yes".
+                        */
+                       if (flash_info[i].legacy_unlock) {
+                               int k;
+
+                               /*
+                                * Disable legacy_unlock temporarily, since
+                                * flash_real_protect would relock all other sectors
+                                * again otherwise.
+                                */
+                               flash_info[i].legacy_unlock = 0;
+
+                               /*
+                                * Legacy unlocking (e.g. Intel J3) -> unlock only one
+                                * sector. This will unlock all sectors.
+                                */
+                               flash_real_protect (&flash_info[i], 0, 0);
+
+                               flash_info[i].legacy_unlock = 1;
+
+                               /*
+                                * Manually mark other sectors as unlocked (unprotected)
+                                */
+                               for (k = 1; k < flash_info[i].sector_count; k++)
+                                       flash_info[i].protect[k] = 0;
+                       } else {
+                               /*
+                                * No legancy unlocking -> unlock all sectors
+                                */
+                               flash_protect (FLAG_PROTECT_CLEAR,
+                                              flash_info[i].start[0],
+                                              flash_info[i].start[0] + flash_info[i].size - 1,
+                                              &flash_info[i]);
+                       }
+               }
+#endif /* CFG_FLASH_PROTECTION */
        }
 
        /* Monitor protection ON by default */
@@ -565,7 +623,22 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
        buffered_size = (info->portwidth / info->chipwidth);
        buffered_size *= info->buffer_size;
        while (cnt >= info->portwidth) {
-               i = buffered_size > cnt ? cnt : buffered_size;
+               /* prohibit buffer write when buffer_size is 1 */
+               if (info->buffer_size == 1) {
+                       cword.l = 0;
+                       for (i = 0; i < info->portwidth; i++)
+                               flash_add_byte (info, &cword, *src++);
+                       if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
+                               return rc;
+                       wp += info->portwidth;
+                       cnt -= info->portwidth;
+                       continue;
+               }
+
+               /* write buffer until next buffered_size aligned boundary */
+               i = buffered_size - (wp % buffered_size);
+               if (i > cnt)
+                       i = cnt;
                if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
                        return rc;
                i -= i & (info->portwidth - 1);
@@ -624,8 +697,12 @@ int flash_real_protect (flash_info_t * info, long sector, int prot)
                                      prot ? "protect" : "unprotect")) == 0) {
 
                info->protect[sector] = prot;
-               /* Intel's unprotect unprotects all locking */
-               if (prot == 0) {
+
+               /*
+                * On some of Intel's flash chips (marked via legacy_unlock)
+                * unprotect unprotects all locking.
+                */
+               if ((prot == 0) && (info->legacy_unlock)) {
                        flash_sect_t i;
 
                        for (i = 0; i < info->sector_count; i++) {
@@ -702,10 +779,14 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector,
 {
        ulong start;
 
+#if CFG_HZ != 1000
+       tout *= CFG_HZ/1000;
+#endif
+
        /* Wait for command completion */
        start = get_timer (0);
        while (flash_is_busy (info, sector)) {
-               if (get_timer (start) > info->erase_blk_tout * CFG_HZ) {
+               if (get_timer (start) > tout) {
                        printf ("Flash %s timeout at address %lx data %lx\n",
                                prompt, info->start[sector],
                                flash_read_long (info, sector, 0));
@@ -729,7 +810,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
        switch (info->vendor) {
        case CFI_CMDSET_INTEL_EXTENDED:
        case CFI_CMDSET_INTEL_STANDARD:
-               if ((retcode != ERR_OK)
+               if ((retcode == ERR_OK)
                    && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
                        retcode = ERR_INVAL;
                        printf ("Flash %s error at address %lx\n", prompt,
@@ -834,18 +915,27 @@ static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset
                debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
                       cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
                *addr.cp = cword.c;
+#ifdef CONFIG_BLACKFIN
+               asm("ssync;");
+#endif
                break;
        case FLASH_CFI_16BIT:
                debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
                       cmd, cword.w,
                       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
                *addr.wp = cword.w;
+#ifdef CONFIG_BLACKFIN
+               asm("ssync;");
+#endif
                break;
        case FLASH_CFI_32BIT:
                debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
                       cmd, cword.l,
                       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
                *addr.lp = cword.l;
+#ifdef CONFIG_BLACKFIN
+               asm("ssync;");
+#endif
                break;
        case FLASH_CFI_64BIT:
 #ifdef DEBUG
@@ -860,6 +950,9 @@ static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset
                }
 #endif
                *addr.llp = cword.ll;
+#ifdef CONFIG_BLACKFIN
+               asm("ssync;");
+#endif
                break;
        }
 }
@@ -985,7 +1078,7 @@ static int flash_detect_cfi (flash_info_t * info)
 {
        debug ("flash detect cfi\n");
 
-       for (info->portwidth = FLASH_CFI_8BIT;
+       for (info->portwidth = CFG_FLASH_CFI_WIDTH;
             info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
                for (info->chipwidth = FLASH_CFI_BY8;
                     info->chipwidth <= info->portwidth;
@@ -1026,6 +1119,10 @@ ulong flash_get_size (ulong base, int banknum)
        uchar num_erase_regions;
        int erase_region_size;
        int erase_region_count;
+#ifdef CFG_FLASH_PROTECTION
+       int ext_addr;
+       info->legacy_unlock = 0;
+#endif
 
        info->start[0] = base;
 
@@ -1039,6 +1136,13 @@ ulong flash_get_size (ulong base, int banknum)
                case CFI_CMDSET_INTEL_EXTENDED:
                default:
                        info->cmd_reset = FLASH_CMD_RESET;
+#ifdef CFG_FLASH_PROTECTION
+                       /* read legacy lock/unlock bit from intel flash */
+                       ext_addr = flash_read_ushort (info, 0,
+                                                     FLASH_OFFSET_EXT_QUERY_T_P_ADDR);
+                       info->legacy_unlock =
+                               flash_read_uchar (info, ext_addr + 5) & 0x08;
+#endif
                        break;
                case CFI_CMDSET_AMD_STANDARD:
                case CFI_CMDSET_AMD_EXTENDED:
@@ -1104,10 +1208,12 @@ ulong flash_get_size (ulong base, int banknum)
                info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE));
                tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
                info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
-               tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
-               info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
-               tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
-               info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
+               tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT)) *
+                       (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT));
+               info->buffer_write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */
+               tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT)) *
+                     (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT));
+               info->write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */
                info->flash_id = FLASH_MAN_CFI;
                if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) {
                        info->portwidth >>= 1;  /* XXX - Need to test on x8/x16 in parallel. */
@@ -1118,13 +1224,26 @@ ulong flash_get_size (ulong base, int banknum)
        return (info->size);
 }
 
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static flash_sect_t find_sector (flash_info_t * info, ulong addr)
+{
+       flash_sect_t sector;
+
+       for (sector = info->sector_count - 1; sector >= 0; sector--) {
+               if (addr >= info->start[sector])
+                       break;
+       }
+       return sector;
+}
 
 /*-----------------------------------------------------------------------
  */
 static int flash_write_cfiword (flash_info_t * info, ulong dest,
                                cfiword_t cword)
 {
-
        cfiptr_t ctladdr;
        cfiptr_t cptr;
        int flag;
@@ -1188,26 +1307,12 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest,
        if (flag)
                enable_interrupts ();
 
-       return flash_full_status_check (info, 0, info->write_tout, "write");
+       return flash_full_status_check (info, find_sector (info, dest),
+                                       info->write_tout, "write");
 }
 
 #ifdef CFG_FLASH_USE_BUFFER_WRITE
 
-/* loop through the sectors from the highest address
- * when the passed address is greater or equal to the sector address
- * we have a match
- */
-static flash_sect_t find_sector (flash_info_t * info, ulong addr)
-{
-       flash_sect_t sector;
-
-       for (sector = info->sector_count - 1; sector >= 0; sector--) {
-               if (addr >= info->start[sector])
-                       break;
-       }
-       return sector;
-}
-
 static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
                                  int len)
 {
@@ -1216,66 +1321,106 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
        int retcode;
        volatile cfiptr_t src;
        volatile cfiptr_t dst;
-       /* buffered writes in the AMD chip set is not supported yet */
-       if((info->vendor ==  CFI_CMDSET_AMD_STANDARD) ||
-               (info->vendor == CFI_CMDSET_AMD_EXTENDED))
-               return ERR_INVAL;
 
-       src.cp = cp;
-       dst.cp = (uchar *) dest;
-       sector = find_sector (info, dest);
-       flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
-       flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
-       if ((retcode =
-            flash_status_check (info, sector, info->buffer_write_tout,
-                                "write to buffer")) == ERR_OK) {
-               /* reduce the number of loops by the width of the port  */
+       switch (info->vendor) {
+       case CFI_CMDSET_INTEL_STANDARD:
+       case CFI_CMDSET_INTEL_EXTENDED:
+               src.cp = cp;
+               dst.cp = (uchar *) dest;
+               sector = find_sector (info, dest);
+               flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+               flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+               if ((retcode = flash_status_check (info, sector, info->buffer_write_tout,
+                                                  "write to buffer")) == ERR_OK) {
+                       /* reduce the number of loops by the width of the port  */
+                       switch (info->portwidth) {
+                       case FLASH_CFI_8BIT:
+                               cnt = len;
+                               break;
+                       case FLASH_CFI_16BIT:
+                               cnt = len >> 1;
+                               break;
+                       case FLASH_CFI_32BIT:
+                               cnt = len >> 2;
+                               break;
+                       case FLASH_CFI_64BIT:
+                               cnt = len >> 3;
+                               break;
+                       default:
+                               return ERR_INVAL;
+                               break;
+                       }
+                       flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
+                       while (cnt-- > 0) {
+                               switch (info->portwidth) {
+                               case FLASH_CFI_8BIT:
+                                       *dst.cp++ = *src.cp++;
+                                       break;
+                               case FLASH_CFI_16BIT:
+                                       *dst.wp++ = *src.wp++;
+                                       break;
+                               case FLASH_CFI_32BIT:
+                                       *dst.lp++ = *src.lp++;
+                                       break;
+                               case FLASH_CFI_64BIT:
+                                       *dst.llp++ = *src.llp++;
+                                       break;
+                               default:
+                                       return ERR_INVAL;
+                                       break;
+                               }
+                       }
+                       flash_write_cmd (info, sector, 0,
+                                        FLASH_CMD_WRITE_BUFFER_CONFIRM);
+                       retcode = flash_full_status_check (info, sector,
+                                                          info->buffer_write_tout,
+                                                          "buffer write");
+               }
+               return retcode;
+
+       case CFI_CMDSET_AMD_STANDARD:
+       case CFI_CMDSET_AMD_EXTENDED:
+               src.cp = cp;
+               dst.cp = (uchar *) dest;
+               sector = find_sector (info, dest);
+
+               flash_unlock_seq(info,0);
+               flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_TO_BUFFER);
+
                switch (info->portwidth) {
                case FLASH_CFI_8BIT:
                        cnt = len;
+                       flash_write_cmd (info, sector, 0,  (uchar) cnt - 1);
+                       while (cnt-- > 0) *dst.cp++ = *src.cp++;
                        break;
                case FLASH_CFI_16BIT:
                        cnt = len >> 1;
+                       flash_write_cmd (info, sector, 0,  (uchar) cnt - 1);
+                       while (cnt-- > 0) *dst.wp++ = *src.wp++;
                        break;
                case FLASH_CFI_32BIT:
                        cnt = len >> 2;
+                       flash_write_cmd (info, sector, 0,  (uchar) cnt - 1);
+                       while (cnt-- > 0) *dst.lp++ = *src.lp++;
                        break;
                case FLASH_CFI_64BIT:
                        cnt = len >> 3;
+                       flash_write_cmd (info, sector, 0,  (uchar) cnt - 1);
+                       while (cnt-- > 0) *dst.llp++ = *src.llp++;
                        break;
                default:
                        return ERR_INVAL;
-                       break;
                }
-               flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
-               while (cnt-- > 0) {
-                       switch (info->portwidth) {
-                       case FLASH_CFI_8BIT:
-                               *dst.cp++ = *src.cp++;
-                               break;
-                       case FLASH_CFI_16BIT:
-                               *dst.wp++ = *src.wp++;
-                               break;
-                       case FLASH_CFI_32BIT:
-                               *dst.lp++ = *src.lp++;
-                               break;
-                       case FLASH_CFI_64BIT:
-                               *dst.llp++ = *src.llp++;
-                               break;
-                       default:
-                               return ERR_INVAL;
-                               break;
-                       }
-               }
-               flash_write_cmd (info, sector, 0,
-                                FLASH_CMD_WRITE_BUFFER_CONFIRM);
-               retcode =
-                       flash_full_status_check (info, sector,
-                                                info->buffer_write_tout,
-                                                "buffer write");
+
+               flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
+               retcode = flash_full_status_check (info, sector, info->buffer_write_tout,
+                                                  "buffer write");
+               return retcode;
+
+       default:
+               debug ("Unknown Command Set\n");
+               return ERR_INVAL;
        }
-       flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
-       return retcode;
 }
 #endif /* CFG_FLASH_USE_BUFFER_WRITE */
 #endif /* CFG_FLASH_CFI */

diff --git a/drivers/ct69000.c b/drivers/ct69000.c
index 7bcf19f5ddc69ae133a4ed4ca98d388d7f7c6b5a..29d82e4c4351976f8b045b82674de3a4d15aa6a0 100644 (file)
--- a/drivers/ct69000.c
+++ b/drivers/ct69000.c
@@ -272,6 +272,9 @@ struct ctfb_chips_properties {
 
 static const struct ctfb_chips_properties chips[] = {
        {PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220},
+#ifdef CONFIG_USE_CPCIDVI
+       {PCI_DEVICE_ID_CT_69030, 0x400000, 1, 4, -2, 3, 257, 100, 220},
+#endif
        {PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220},  /* NOT TESTED */
        {0, 0, 0, 0, 0, 0, 0, 0, 0}     /* Terminator */
 };
@@ -957,6 +960,9 @@ SetDrawingEngine (int bits_per_pixel)
 */
 static struct pci_device_id supported[] = {
        {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000},
+#ifdef CONFIG_USE_CPCIDVI
+       {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030},
+#endif
        {}
 };
 
@@ -1121,7 +1127,22 @@ video_hw_init (void)
        pGD->cprBase = pci_mem_base;    /* Dummy */
        /* set up Hardware */
 
+#ifdef CONFIG_USE_CPCIDVI
+       if (device_id == PCI_DEVICE_ID_CT_69030) {
+               ctWrite (CT_MSR_W_O, 0x0b);
+               ctWrite (0x3cd, 0x13);
+               ctWrite_i (CT_FP_O, 0x02, 0x00);
+               ctWrite_i (CT_FP_O, 0x05, 0x00);
+               ctWrite_i (CT_FP_O, 0x06, 0x00);
+               ctWrite (0x3c2, 0x0b);
+               ctWrite_i (CT_FP_O, 0x02, 0x10);
+               ctWrite_i (CT_FP_O, 0x01, 0x09);
+       } else {
+               ctWrite (CT_MSR_W_O, 0x01);
+       }
+#else
        ctWrite (CT_MSR_W_O, 0x01);
+#endif
 
        /* set the extended Registers */
        ctLoadRegs (CT_XR_O, xreg);

diff --git a/drivers/dataflash.c b/drivers/dataflash.c
index ded039578a488e6e9d184c34335bcd671c5af78a..17eb8597f8c26838f38b64db7c0a7cc20d1c8172 100644 (file)
--- a/drivers/dataflash.c
+++ b/drivers/dataflash.c
@@ -174,8 +174,7 @@ void dataflash_print_info (void)
 /* Function Name       : AT91F_DataflashSelect                                         */
 /* Object              : Select the correct device                             */
 /*------------------------------------------------------------------------------*/
-AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash pFlash,
-                                                                               unsigned int *addr)
+AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash pFlash, unsigned long *addr)
 {
        char addr_valid = 0;
        int i;
@@ -291,7 +290,7 @@ int i,j, area1, area2, addr_valid = 0;
 /*------------------------------------------------------------------------------*/
 int read_dataflash (unsigned long addr, unsigned long size, char *result)
 {
-       int AddrToRead = addr;
+       unsigned long AddrToRead = addr;
        AT91PS_DataFlash pFlash = &DataFlashInst;
 
        pFlash = AT91F_DataflashSelect (pFlash, &AddrToRead);
@@ -313,7 +312,7 @@ int read_dataflash (unsigned long addr, unsigned long size, char *result)
 int write_dataflash (unsigned long addr_dest, unsigned long addr_src,
                     unsigned long size)
 {
-       int AddrToWrite = addr_dest;
+       unsigned long AddrToWrite = addr_dest;
        AT91PS_DataFlash pFlash = &DataFlashInst;
 
        pFlash = AT91F_DataflashSelect (pFlash, &AddrToWrite);
@@ -330,7 +329,7 @@ int write_dataflash (unsigned long addr_dest, unsigned long addr_src,
        if (AddrToWrite == -1)
                return -1;
 
-       return AT91F_DataFlashWrite (pFlash, (char *) addr_src, AddrToWrite, size);
+       return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src, AddrToWrite, size);
 }
 
 

diff --git a/drivers/i8042.c b/drivers/i8042.c
index e21978dc249a16dbdb06947c418226f0d27f920c..22c2a4e3a02da185783e0a1064ceca2f54f0866d 100644 (file)
--- a/drivers/i8042.c
+++ b/drivers/i8042.c
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -29,6 +29,14 @@
 
 #ifdef CONFIG_I8042_KBD
 
+#ifdef CONFIG_USE_CPCIDVI
+extern u8  gt_cpcidvi_in8(u32 offset);
+extern void gt_cpcidvi_out8(u32 offset, u8 data);
+
+#define in8(a)    gt_cpcidvi_in8(a)
+#define out8(a, b) gt_cpcidvi_out8(a,b)
+#endif
+
 #include <i8042.h>
 
 /* defines */
@@ -41,10 +49,10 @@ static int cursor_state = 0;
 
 /* locals */
 
-static int  kbd_input    = -1;          /* no input yet */
-static int  kbd_mapping  = KBD_US;      /* default US keyboard */
-static int  kbd_flags    = NORMAL;      /* after reset */
-static int  kbd_state    = 0;           /* unshift code */
+static int  kbd_input   = -1;          /* no input yet */
+static int  kbd_mapping         = KBD_US;      /* default US keyboard */
+static int  kbd_flags   = NORMAL;      /* after reset */
+static int  kbd_state   = 0;           /* unshift code */
 
 static void kbd_conv_char (unsigned char scan_code);
 static void kbd_led_set (void);
@@ -60,230 +68,230 @@ static int  kbd_reset (void);
 
 static unsigned char kbd_fct_map [144] =
     { /* kbd_fct_map table for scan code */
-    0,   AS,   AS,   AS,   AS,   AS,   AS,   AS, /* scan  0- 7 */
-   AS,   AS,   AS,   AS,   AS,   AS,   AS,   AS, /* scan  8- F */
-   AS,   AS,   AS,   AS,   AS,   AS,   AS,   AS, /* scan 10-17 */
-   AS,   AS,   AS,   AS,   AS,   CN,   AS,   AS, /* scan 18-1F */
-   AS,   AS,   AS,   AS,   AS,   AS,   AS,   AS, /* scan 20-27 */
-   AS,   AS,   SH,   AS,   AS,   AS,   AS,   AS, /* scan 28-2F */
-   AS,   AS,   AS,   AS,   AS,   AS,   SH,   AS, /* scan 30-37 */
-   AS,   AS,   CP,   0,    0,    0,    0,     0, /* scan 38-3F */
-    0,   0,    0,    0,    0,    NM,   ST,   ES, /* scan 40-47 */
-   ES,   ES,   ES,   ES,   ES,   ES,   ES,   ES, /* scan 48-4F */
-   ES,   ES,   ES,   ES,   0,    0,    AS,    0, /* scan 50-57 */
-    0,   0,    0,    0,    0,    0,    0,     0, /* scan 58-5F */
-    0,   0,    0,    0,    0,    0,    0,     0, /* scan 60-67 */
-    0,   0,    0,    0,    0,    0,    0,     0, /* scan 68-6F */
-   AS,   0,    0,    AS,   0,    0,    AS,    0, /* scan 70-77 */
-    0,   AS,   0,    0,    0,    AS,   0,     0, /* scan 78-7F */
-   AS,   CN,   AS,   AS,   AK,   ST,   EX,   EX, /* enhanced   */
-   AS,   EX,   EX,   AS,   EX,   AS,   EX,   EX  /* enhanced   */
+    0,  AS,   AS,   AS,   AS,   AS,   AS,   AS, /* scan  0- 7 */
+   AS,  AS,   AS,   AS,   AS,   AS,   AS,   AS, /* scan  8- F */
+   AS,  AS,   AS,   AS,   AS,   AS,   AS,   AS, /* scan 10-17 */
+   AS,  AS,   AS,   AS,   AS,   CN,   AS,   AS, /* scan 18-1F */
+   AS,  AS,   AS,   AS,   AS,   AS,   AS,   AS, /* scan 20-27 */
+   AS,  AS,   SH,   AS,   AS,   AS,   AS,   AS, /* scan 28-2F */
+   AS,  AS,   AS,   AS,   AS,   AS,   SH,   AS, /* scan 30-37 */
+   AS,  AS,   CP,   0,    0,    0,    0,     0, /* scan 38-3F */
+    0,  0,    0,    0,    0,    NM,   ST,   ES, /* scan 40-47 */
+   ES,  ES,   ES,   ES,   ES,   ES,   ES,   ES, /* scan 48-4F */
+   ES,  ES,   ES,   ES,   0,    0,    AS,    0, /* scan 50-57 */
+    0,  0,    0,    0,    0,    0,    0,     0, /* scan 58-5F */
+    0,  0,    0,    0,    0,    0,    0,     0, /* scan 60-67 */
+    0,  0,    0,    0,    0,    0,    0,     0, /* scan 68-6F */
+   AS,  0,    0,    AS,   0,    0,    AS,    0, /* scan 70-77 */
+    0,  AS,   0,    0,    0,    AS,   0,     0, /* scan 78-7F */
+   AS,  CN,   AS,   AS,   AK,   ST,   EX,   EX, /* enhanced   */
+   AS,  EX,   EX,   AS,   EX,   AS,   EX,   EX  /* enhanced   */
     };
 
 static unsigned char kbd_key_map [2][5][144] =
     {
     { /* US keyboard */
     { /* unshift code */
-    0,  0x1b,   '1',   '2',   '3',   '4',   '5',   '6',    /* scan  0- 7 */
-  '7',   '8',   '9',   '0',   '-',   '=',  0x08,  '\t',    /* scan  8- F */
-  'q',   'w',   'e',   'r',   't',   'y',   'u',   'i',    /* scan 10-17 */
-  'o',   'p',   '[',   ']',  '\r',   CN,    'a',   's',    /* scan 18-1F */
-  'd',   'f',   'g',   'h',   'j',   'k',   'l',   ';',    /* scan 20-27 */
- '\'',   '`',   SH,   '\\',   'z',   'x',   'c',   'v',    /* scan 28-2F */
-  'b',   'n',   'm',   ',',   '.',   '/',   SH,    '*',    /* scan 30-37 */
-  ' ',   ' ',   CP,      0,     0,     0,     0,     0,    /* scan 38-3F */
-    0,     0,     0,     0,     0,   NM,    ST,    '7',    /* scan 40-47 */
-  '8',   '9',   '-',   '4',   '5',   '6',   '+',   '1',    /* scan 48-4F */
-  '2',   '3',   '0',   '.',     0,     0,     0,     0,    /* scan 50-57 */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 58-5F */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 60-67 */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 68-6F */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 70-77 */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 78-7F */
-  '\r',   CN,   '/',   '*',   ' ',    ST,   'F',   'A',    /* extended */
-    0,   'D',   'C',     0,   'B',     0,    '@',  'P'     /* extended */
+    0, 0x1b,   '1',   '2',   '3',   '4',   '5',   '6',    /* scan  0- 7 */
+  '7',  '8',   '9',   '0',   '-',   '=',  0x08,  '\t',    /* scan  8- F */
+  'q',  'w',   'e',   'r',   't',   'y',   'u',   'i',    /* scan 10-17 */
+  'o',  'p',   '[',   ']',  '\r',   CN,    'a',   's',    /* scan 18-1F */
+  'd',  'f',   'g',   'h',   'j',   'k',   'l',   ';',    /* scan 20-27 */
+ '\'',  '`',   SH,   '\\',   'z',   'x',   'c',   'v',    /* scan 28-2F */
+  'b',  'n',   'm',   ',',   '.',   '/',   SH,    '*',    /* scan 30-37 */
+  ' ',  ' ',   CP,      0,     0,     0,     0,     0,    /* scan 38-3F */
+    0,    0,     0,     0,     0,   NM,    ST,    '7',    /* scan 40-47 */
+  '8',  '9',   '-',   '4',   '5',   '6',   '+',   '1',    /* scan 48-4F */
+  '2',  '3',   '0',   '.',     0,     0,     0,     0,    /* scan 50-57 */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 58-5F */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 60-67 */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 68-6F */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 70-77 */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 78-7F */
+  '\r',          CN,   '/',   '*',   ' ',    ST,   'F',   'A',    /* extended */
+    0,  'D',   'C',     0,   'B',     0,    '@',  'P'     /* extended */
     },
     { /* shift code */
-    0,  0x1b,   '!',   '@',   '#',   '$',   '%',   '^',    /* scan  0- 7 */
-  '&',   '*',   '(',   ')',   '_',   '+',  0x08,  '\t',    /* scan  8- F */
-  'Q',   'W',   'E',   'R',   'T',   'Y',   'U',   'I',    /* scan 10-17 */
-  'O',   'P',   '{',   '}',  '\r',   CN,    'A',   'S',    /* scan 18-1F */
-  'D',   'F',   'G',   'H',   'J',   'K',   'L',   ':',    /* scan 20-27 */
-  '"',   '~',   SH,    '|',   'Z',   'X',   'C',   'V',    /* scan 28-2F */
-  'B',   'N',   'M',   '<',   '>',   '?',   SH,    '*',    /* scan 30-37 */
-  ' ',   ' ',   CP,      0,     0,     0,     0,     0,    /* scan 38-3F */
-    0,     0,     0,     0,     0,   NM,    ST,    '7',    /* scan 40-47 */
-  '8',   '9',   '-',   '4',   '5',   '6',   '+',   '1',    /* scan 48-4F */
-  '2',   '3',   '0',   '.',     0,     0,     0,     0,    /* scan 50-57 */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 58-5F */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 60-67 */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 68-6F */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 70-77 */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 78-7F */
-  '\r',   CN,   '/',   '*',   ' ',    ST,   'F',   'A',    /* extended */
-    0,   'D',   'C',     0,   'B',     0,   '@',   'P'     /* extended */
+    0, 0x1b,   '!',   '@',   '#',   '$',   '%',   '^',    /* scan  0- 7 */
+  '&',  '*',   '(',   ')',   '_',   '+',  0x08,  '\t',    /* scan  8- F */
+  'Q',  'W',   'E',   'R',   'T',   'Y',   'U',   'I',    /* scan 10-17 */
+  'O',  'P',   '{',   '}',  '\r',   CN,    'A',   'S',    /* scan 18-1F */
+  'D',  'F',   'G',   'H',   'J',   'K',   'L',   ':',    /* scan 20-27 */
+  '"',  '~',   SH,    '|',   'Z',   'X',   'C',   'V',    /* scan 28-2F */
+  'B',  'N',   'M',   '<',   '>',   '?',   SH,    '*',    /* scan 30-37 */
+  ' ',  ' ',   CP,      0,     0,     0,     0,     0,    /* scan 38-3F */
+    0,    0,     0,     0,     0,   NM,    ST,    '7',    /* scan 40-47 */
+  '8',  '9',   '-',   '4',   '5',   '6',   '+',   '1',    /* scan 48-4F */
+  '2',  '3',   '0',   '.',     0,     0,     0,     0,    /* scan 50-57 */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 58-5F */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 60-67 */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 68-6F */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 70-77 */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 78-7F */
+  '\r',          CN,   '/',   '*',   ' ',    ST,   'F',   'A',    /* extended */
+    0,  'D',   'C',     0,   'B',     0,   '@',   'P'     /* extended */
     },
     { /* control code */
- 0xff,  0x1b,  0xff,  0x00,  0xff,  0xff,  0xff,  0xff,    /* scan  0- 7 */
- 0x1e,  0xff,  0xff,  0xff,  0x1f,  0xff,  0xff,  '\t',    /* scan  8- F */
- 0x11,  0x17,  0x05,  0x12,  0x14,  0x19,  0x15,  0x09,    /* scan 10-17 */
- 0x0f,  0x10,  0x1b,  0x1d,  '\r',   CN,   0x01,  0x13,    /* scan 18-1F */
- 0x04,  0x06,  0x07,  0x08,  0x0a,  0x0b,  0x0c,  0xff,    /* scan 20-27 */
- 0xff,  0x1c,   SH,   0xff,  0x1a,  0x18,  0x03,  0x16,    /* scan 28-2F */
- 0x02,  0x0e,  0x0d,  0xff,  0xff,  0xff,   SH,   0xff,    /* scan 30-37 */
- 0xff,  0xff,   CP,   0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 38-3F */
- 0xff,  0xff,  0xff,  0xff,  0xff,   NM,    ST,   0xff,    /* scan 40-47 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 48-4F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 50-57 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 58-5F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 60-67 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 68-6F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 70-77 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 78-7F */
-  '\r',   CN,   '/',   '*',   ' ',    ST,  0xff,  0xff,    /* extended */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff     /* extended */
+ 0xff, 0x1b,  0xff,  0x00,  0xff,  0xff,  0xff,  0xff,    /* scan  0- 7 */
+ 0x1e, 0xff,  0xff,  0xff,  0x1f,  0xff,  0xff,  '\t',    /* scan  8- F */
+ 0x11, 0x17,  0x05,  0x12,  0x14,  0x19,  0x15,  0x09,    /* scan 10-17 */
+ 0x0f, 0x10,  0x1b,  0x1d,  '\r',   CN,   0x01,  0x13,    /* scan 18-1F */
+ 0x04, 0x06,  0x07,  0x08,  0x0a,  0x0b,  0x0c,  0xff,    /* scan 20-27 */
+ 0xff, 0x1c,   SH,   0xff,  0x1a,  0x18,  0x03,  0x16,    /* scan 28-2F */
+ 0x02, 0x0e,  0x0d,  0xff,  0xff,  0xff,   SH,   0xff,    /* scan 30-37 */
+ 0xff, 0xff,   CP,   0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 38-3F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,   NM,    ST,   0xff,    /* scan 40-47 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 48-4F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 50-57 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 58-5F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 60-67 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 68-6F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 70-77 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,    /* scan 78-7F */
+  '\r',          CN,   '/',   '*',   ' ',    ST,  0xff,  0xff,    /* extended */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff     /* extended */
     },
     { /* non numeric code */
-    0,  0x1b,   '1',   '2',   '3',   '4',   '5',   '6',    /* scan  0- 7 */
-  '7',   '8',   '9',   '0',   '-',   '=',  0x08,  '\t',    /* scan  8- F */
-  'q',   'w',   'e',   'r',   't',   'y',   'u',   'i',    /* scan 10-17 */
-  'o',   'p',   '[',   ']',  '\r',   CN,    'a',   's',    /* scan 18-1F */
-  'd',   'f',   'g',   'h',   'j',   'k',   'l',   ';',    /* scan 20-27 */
- '\'',   '`',   SH,   '\\',   'z',   'x',   'c',   'v',    /* scan 28-2F */
-  'b',   'n',   'm',   ',',   '.',   '/',   SH,    '*',    /* scan 30-37 */
-  ' ',   ' ',   CP,      0,     0,     0,     0,     0,    /* scan 38-3F */
-    0,     0,     0,     0,     0,   NM,    ST,    'w',    /* scan 40-47 */
-  'x',   'y',   'l',   't',   'u',   'v',   'm',   'q',    /* scan 48-4F */
-  'r',   's',   'p',   'n',     0,     0,     0,     0,    /* scan 50-57 */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 58-5F */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 60-67 */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 68-6F */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 70-77 */
-    0,     0,     0,     0,     0,     0,     0,     0,    /* scan 78-7F */
-  '\r',   CN,   '/',   '*',   ' ',    ST,   'F',   'A',    /* extended */
-    0,   'D',   'C',     0,   'B',     0,    '@',  'P'     /* extended */
+    0, 0x1b,   '1',   '2',   '3',   '4',   '5',   '6',    /* scan  0- 7 */
+  '7',  '8',   '9',   '0',   '-',   '=',  0x08,  '\t',    /* scan  8- F */
+  'q',  'w',   'e',   'r',   't',   'y',   'u',   'i',    /* scan 10-17 */
+  'o',  'p',   '[',   ']',  '\r',   CN,    'a',   's',    /* scan 18-1F */
+  'd',  'f',   'g',   'h',   'j',   'k',   'l',   ';',    /* scan 20-27 */
+ '\'',  '`',   SH,   '\\',   'z',   'x',   'c',   'v',    /* scan 28-2F */
+  'b',  'n',   'm',   ',',   '.',   '/',   SH,    '*',    /* scan 30-37 */
+  ' ',  ' ',   CP,      0,     0,     0,     0,     0,    /* scan 38-3F */
+    0,    0,     0,     0,     0,   NM,    ST,    'w',    /* scan 40-47 */
+  'x',  'y',   'l',   't',   'u',   'v',   'm',   'q',    /* scan 48-4F */
+  'r',  's',   'p',   'n',     0,     0,     0,     0,    /* scan 50-57 */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 58-5F */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 60-67 */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 68-6F */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 70-77 */
+    0,    0,     0,     0,     0,     0,     0,     0,    /* scan 78-7F */
+  '\r',          CN,   '/',   '*',   ' ',    ST,   'F',   'A',    /* extended */
+    0,  'D',   'C',     0,   'B',     0,    '@',  'P'     /* extended */
     },
     { /* right alt mode - not used in US keyboard */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan  0 - 7 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan  8 - F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 10 -17 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 18 -1F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 20 -27 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 28 -2F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 30 -37 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 38 -3F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 40 -47 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 48 -4F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 50 -57 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 58 -5F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 60 -67 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 68 -6F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 70 -77 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 78 -7F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* extended    */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff  /* extended    */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan  0 - 7 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan  8 - F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 10 -17 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 18 -1F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 20 -27 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 28 -2F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 30 -37 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 38 -3F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 40 -47 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 48 -4F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 50 -57 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 58 -5F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 60 -67 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 68 -6F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 70 -77 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 78 -7F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* extended    */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff  /* extended    */
     }
     },
     { /* german keyboard */
     { /* unshift code */
-    0,  0x1b,   '1',   '2',   '3',   '4',   '5',   '6', /* scan  0- 7 */
-  '7',   '8',   '9',   '0',  0xe1,  '\'',  0x08,  '\t', /* scan  8- F */
-  'q',   'w',   'e',   'r',   't',   'z',   'u',   'i', /* scan 10-17 */
-  'o',   'p',  0x81,   '+',  '\r',   CN,    'a',   's', /* scan 18-1F */
-  'd',   'f',   'g',   'h',   'j',   'k',   'l',  0x94, /* scan 20-27 */
- 0x84,   '^',   SH,    '#',   'y',   'x',   'c',   'v', /* scan 28-2F */
-  'b',   'n',   'm',   ',',   '.',   '-',   SH,    '*', /* scan 30-37 */
-  ' ',   ' ',   CP,      0,     0,     0,     0,     0, /* scan 38-3F */
-    0,     0,     0,     0,     0,   NM,    ST,    '7', /* scan 40-47 */
-  '8',   '9',   '-',   '4',   '5',   '6',   '+',   '1', /* scan 48-4F */
-  '2',   '3',   '0',   ',',     0,     0,   '<',     0, /* scan 50-57 */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 58-5F */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 60-67 */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 68-6F */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 70-77 */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 78-7F */
-  '\r',   CN,   '/',   '*',   ' ',    ST,   'F',   'A', /* extended */
-    0,   'D',   'C',     0,   'B',     0,    '@',  'P'  /* extended */
+    0, 0x1b,   '1',   '2',   '3',   '4',   '5',   '6', /* scan  0- 7 */
+  '7',  '8',   '9',   '0',  0xe1,  '\'',  0x08,  '\t', /* scan  8- F */
+  'q',  'w',   'e',   'r',   't',   'z',   'u',   'i', /* scan 10-17 */
+  'o',  'p',  0x81,   '+',  '\r',   CN,    'a',   's', /* scan 18-1F */
+  'd',  'f',   'g',   'h',   'j',   'k',   'l',  0x94, /* scan 20-27 */
+ 0x84,  '^',   SH,    '#',   'y',   'x',   'c',   'v', /* scan 28-2F */
+  'b',  'n',   'm',   ',',   '.',   '-',   SH,    '*', /* scan 30-37 */
+  ' ',  ' ',   CP,      0,     0,     0,     0,     0, /* scan 38-3F */
+    0,    0,     0,     0,     0,   NM,    ST,    '7', /* scan 40-47 */
+  '8',  '9',   '-',   '4',   '5',   '6',   '+',   '1', /* scan 48-4F */
+  '2',  '3',   '0',   ',',     0,     0,   '<',     0, /* scan 50-57 */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 58-5F */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 60-67 */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 68-6F */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 70-77 */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 78-7F */
+  '\r',          CN,   '/',   '*',   ' ',    ST,   'F',   'A', /* extended */
+    0,  'D',   'C',     0,   'B',     0,    '@',  'P'  /* extended */
     },
     { /* shift code */
-    0,  0x1b,   '!',   '"',  0x15,   '$',   '%',   '&', /* scan  0- 7 */
-  '/',   '(',   ')',   '=',   '?',   '`',  0x08,  '\t', /* scan  8- F */
-  'Q',   'W',   'E',   'R',   'T',   'Z',   'U',   'I', /* scan 10-17 */
-  'O',   'P',  0x9a,   '*',  '\r',   CN,    'A',   'S', /* scan 18-1F */
-  'D',   'F',   'G',   'H',   'J',   'K',   'L',  0x99, /* scan 20-27 */
- 0x8e,  0xf8,   SH,   '\'',   'Y',   'X',   'C',   'V', /* scan 28-2F */
-  'B',   'N',   'M',   ';',   ':',   '_',   SH,    '*', /* scan 30-37 */
-  ' ',   ' ',   CP,      0,     0,     0,     0,     0, /* scan 38-3F */
-    0,     0,     0,     0,     0,   NM,    ST,    '7', /* scan 40-47 */
-  '8',   '9',   '-',   '4',   '5',   '6',   '+',   '1', /* scan 48-4F */
-  '2',   '3',   '0',   ',',     0,     0,   '>',     0, /* scan 50-57 */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 58-5F */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 60-67 */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 68-6F */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 70-77 */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 78-7F */
-  '\r',   CN,   '/',   '*',   ' ',    ST,   'F',   'A', /* extended */
-    0,   'D',   'C',     0,   'B',     0,   '@',   'P'  /* extended */
+    0, 0x1b,   '!',   '"',  0x15,   '$',   '%',   '&', /* scan  0- 7 */
+  '/',  '(',   ')',   '=',   '?',   '`',  0x08,  '\t', /* scan  8- F */
+  'Q',  'W',   'E',   'R',   'T',   'Z',   'U',   'I', /* scan 10-17 */
+  'O',  'P',  0x9a,   '*',  '\r',   CN,    'A',   'S', /* scan 18-1F */
+  'D',  'F',   'G',   'H',   'J',   'K',   'L',  0x99, /* scan 20-27 */
+ 0x8e, 0xf8,   SH,   '\'',   'Y',   'X',   'C',   'V', /* scan 28-2F */
+  'B',  'N',   'M',   ';',   ':',   '_',   SH,    '*', /* scan 30-37 */
+  ' ',  ' ',   CP,      0,     0,     0,     0,     0, /* scan 38-3F */
+    0,    0,     0,     0,     0,   NM,    ST,    '7', /* scan 40-47 */
+  '8',  '9',   '-',   '4',   '5',   '6',   '+',   '1', /* scan 48-4F */
+  '2',  '3',   '0',   ',',     0,     0,   '>',     0, /* scan 50-57 */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 58-5F */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 60-67 */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 68-6F */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 70-77 */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 78-7F */
+  '\r',          CN,   '/',   '*',   ' ',    ST,   'F',   'A', /* extended */
+    0,  'D',   'C',     0,   'B',     0,   '@',   'P'  /* extended */
     },
     { /* control code */
- 0xff,  0x1b,  0xff,  0x00,  0xff,  0xff,  0xff,  0xff, /* scan  0- 7 */
- 0x1e,  0xff,  0xff,  0xff,  0x1f,  0xff,  0xff,  '\t', /* scan  8- F */
- 0x11,  0x17,  0x05,  0x12,  0x14,  0x19,  0x15,  0x09, /* scan 10-17 */
- 0x0f,  0x10,  0x1b,  0x1d,  '\r',   CN,   0x01,  0x13, /* scan 18-1F */
- 0x04,  0x06,  0x07,  0x08,  0x0a,  0x0b,  0x0c,  0xff, /* scan 20-27 */
- 0xff,  0x1c,   SH,   0xff,  0x1a,  0x18,  0x03,  0x16, /* scan 28-2F */
- 0x02,  0x0e,  0x0d,  0xff,  0xff,  0xff,   SH,   0xff, /* scan 30-37 */
- 0xff,  0xff,   CP,   0xff,  0xff,  0xff,  0xff,  0xff, /* scan 38-3F */
- 0xff,  0xff,  0xff,  0xff,  0xff,   NM,    ST,   0xff, /* scan 40-47 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 48-4F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 50-57 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 58-5F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 60-67 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 68-6F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 70-77 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 78-7F */
-  '\r',   CN,   '/',   '*',   ' ',    ST,  0xff,  0xff, /* extended */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff  /* extended */
+ 0xff, 0x1b,  0xff,  0x00,  0xff,  0xff,  0xff,  0xff, /* scan  0- 7 */
+ 0x1e, 0xff,  0xff,  0xff,  0x1f,  0xff,  0xff,  '\t', /* scan  8- F */
+ 0x11, 0x17,  0x05,  0x12,  0x14,  0x19,  0x15,  0x09, /* scan 10-17 */
+ 0x0f, 0x10,  0x1b,  0x1d,  '\r',   CN,   0x01,  0x13, /* scan 18-1F */
+ 0x04, 0x06,  0x07,  0x08,  0x0a,  0x0b,  0x0c,  0xff, /* scan 20-27 */
+ 0xff, 0x1c,   SH,   0xff,  0x1a,  0x18,  0x03,  0x16, /* scan 28-2F */
+ 0x02, 0x0e,  0x0d,  0xff,  0xff,  0xff,   SH,   0xff, /* scan 30-37 */
+ 0xff, 0xff,   CP,   0xff,  0xff,  0xff,  0xff,  0xff, /* scan 38-3F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,   NM,    ST,   0xff, /* scan 40-47 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 48-4F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 50-57 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 58-5F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 60-67 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 68-6F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 70-77 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 78-7F */
+  '\r',          CN,   '/',   '*',   ' ',    ST,  0xff,  0xff, /* extended */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff  /* extended */
     },
     { /* non numeric code */
-    0,  0x1b,   '1',   '2',   '3',   '4',   '5',   '6', /* scan  0- 7 */
-  '7',   '8',   '9',   '0',  0xe1,  '\'',  0x08,  '\t', /* scan  8- F */
-  'q',   'w',   'e',   'r',   't',   'z',   'u',   'i', /* scan 10-17 */
-  'o',   'p',  0x81,   '+',  '\r',   CN,    'a',   's', /* scan 18-1F */
-  'd',   'f',   'g',   'h',   'j',   'k',   'l',  0x94, /* scan 20-27 */
- 0x84,   '^',   SH,      0,   'y',   'x',   'c',   'v', /* scan 28-2F */
-  'b',   'n',   'm',   ',',   '.',   '-',   SH,    '*', /* scan 30-37 */
-  ' ',   ' ',   CP,      0,     0,     0,     0,     0, /* scan 38-3F */
-    0,     0,     0,     0,     0,   NM,    ST,    'w', /* scan 40-47 */
-  'x',   'y',   'l',   't',   'u',   'v',   'm',   'q', /* scan 48-4F */
-  'r',   's',   'p',   'n',     0,     0,   '<',     0, /* scan 50-57 */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 58-5F */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 60-67 */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 68-6F */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 70-77 */
-    0,     0,     0,     0,     0,     0,     0,     0, /* scan 78-7F */
-  '\r',   CN,   '/',   '*',   ' ',    ST,   'F',   'A', /* extended */
-    0,   'D',   'C',     0,   'B',     0,    '@',  'P'  /* extended */
+    0, 0x1b,   '1',   '2',   '3',   '4',   '5',   '6', /* scan  0- 7 */
+  '7',  '8',   '9',   '0',  0xe1,  '\'',  0x08,  '\t', /* scan  8- F */
+  'q',  'w',   'e',   'r',   't',   'z',   'u',   'i', /* scan 10-17 */
+  'o',  'p',  0x81,   '+',  '\r',   CN,    'a',   's', /* scan 18-1F */
+  'd',  'f',   'g',   'h',   'j',   'k',   'l',  0x94, /* scan 20-27 */
+ 0x84,  '^',   SH,      0,   'y',   'x',   'c',   'v', /* scan 28-2F */
+  'b',  'n',   'm',   ',',   '.',   '-',   SH,    '*', /* scan 30-37 */
+  ' ',  ' ',   CP,      0,     0,     0,     0,     0, /* scan 38-3F */
+    0,    0,     0,     0,     0,   NM,    ST,    'w', /* scan 40-47 */
+  'x',  'y',   'l',   't',   'u',   'v',   'm',   'q', /* scan 48-4F */
+  'r',  's',   'p',   'n',     0,     0,   '<',     0, /* scan 50-57 */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 58-5F */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 60-67 */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 68-6F */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 70-77 */
+    0,    0,     0,     0,     0,     0,     0,     0, /* scan 78-7F */
+  '\r',          CN,   '/',   '*',   ' ',    ST,   'F',   'A', /* extended */
+    0,  'D',   'C',     0,   'B',     0,    '@',  'P'  /* extended */
     },
     { /* Right alt mode - is used in German keyboard */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan  0 - 7 */
-  '{',   '[',   ']',   '}',  '\\',  0xff,  0xff,  0xff, /* scan  8 - F */
-  '@',  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 10 -17 */
- 0xff,  0xff,  0xff,   '~',  0xff,  0xff,  0xff,  0xff, /* scan 18 -1F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 20 -27 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 28 -2F */
- 0xff,  0xff,  0xe6,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 30 -37 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 38 -3F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 40 -47 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 48 -4F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,   '|',  0xff, /* scan 50 -57 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 58 -5F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 60 -67 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 68 -6F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 70 -77 */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 78 -7F */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* extended    */
- 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff  /* extended    */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan  0 - 7 */
+  '{',  '[',   ']',   '}',  '\\',  0xff,  0xff,  0xff, /* scan  8 - F */
+  '@', 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 10 -17 */
+ 0xff, 0xff,  0xff,   '~',  0xff,  0xff,  0xff,  0xff, /* scan 18 -1F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 20 -27 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 28 -2F */
+ 0xff, 0xff,  0xe6,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 30 -37 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 38 -3F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 40 -47 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 48 -4F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,   '|',  0xff, /* scan 50 -57 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 58 -5F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 60 -67 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 68 -6F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 70 -77 */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* scan 78 -7F */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff, /* extended    */
+ 0xff, 0xff,  0xff,  0xff,  0xff,  0xff,  0xff,  0xff  /* extended    */
     }
     }
     };
@@ -318,6 +326,13 @@ int i8042_kbd_init (void)
     int keymap, try;
     char *penv;
 
+#ifdef CONFIG_USE_CPCIDVI
+    if ((penv = getenv ("console")) != NULL) {
+           if (strncmp (penv, "serial", 7) == 0) {
+                   return -1;
+           }
+    }
+#endif
     /* Init keyboard device (default US layout) */
     keymap = KBD_US;
     if ((penv = getenv ("keymap")) != NULL)
@@ -330,9 +345,9 @@ int i8042_kbd_init (void)
     {
        if (kbd_reset() == 0)
        {
-           kbd_mapping   = keymap;
-           kbd_flags     = NORMAL;
-           kbd_state     = 0;
+           kbd_mapping   = keymap;
+           kbd_flags     = NORMAL;
+           kbd_state     = 0;
            kbd_led_set();
            return 0;
            }
@@ -344,7 +359,7 @@ int i8042_kbd_init (void)
 /*******************************************************************************
  *
  * i8042_tstc - test if keyboard input is available
- *              option: cursor blinking if called in a loop
+ *             option: cursor blinking if called in a loop
  */
 int i8042_tstc (void)
 {
@@ -380,7 +395,7 @@ int i8042_tstc (void)
 /*******************************************************************************
  *
  * i8042_getc - wait till keyboard input is available
- *              option: turn on/off cursor while waiting
+ *             option: turn on/off cursor while waiting
  */
 int i8042_getc (void)
 {
@@ -433,8 +448,8 @@ static void kbd_conv_char (unsigned char scan_code)
     {
        if (scan_code == 0xe1)
        {
-           kbd_flags ^= BRK;     /* reset the break flag */
-           kbd_flags ^= E1;      /* bitwise EXOR with E1 flag */
+           kbd_flags ^= BRK;     /* reset the break flag */
+           kbd_flags ^= E1;      /* bitwise EXOR with E1 flag */
        }
        return;
     }
@@ -545,7 +560,7 @@ static void kbd_caps (unsigned char scan_code)
     if ((kbd_flags & BRK) == NORMAL)
     {
        kbd_flags ^= CAPS;
-       kbd_led_set ();            /* update keyboard LED */
+       kbd_led_set ();           /* update keyboard LED */
     }
 }
 
@@ -558,7 +573,7 @@ static void kbd_num (unsigned char scan_code)
     {
        kbd_flags ^= NUM;
        kbd_state = (kbd_flags & NUM) ? AS : NM;
-       kbd_led_set ();            /* update keyboard LED */
+       kbd_led_set ();           /* update keyboard LED */
     }
 }
 
@@ -570,7 +585,7 @@ static void kbd_scroll (unsigned char scan_code)
     if ((kbd_flags & BRK) == NORMAL)
     {
        kbd_flags ^= STP;
-       kbd_led_set ();            /* update keyboard LED */
+       kbd_led_set ();            /* update keyboard LED */
        if (kbd_flags & STP)
            kbd_input = 0x13;
        else
@@ -600,9 +615,9 @@ static void kbd_alt (unsigned char scan_code)
 static void kbd_led_set (void)
 {
     kbd_input_empty();
-    out8 (I8042_DATA_REG, 0xed);        /* SET LED command */
+    out8 (I8042_DATA_REG, 0xed);       /* SET LED command */
     kbd_input_empty();
-    out8 (I8042_DATA_REG, (kbd_flags & 0x7));    /* LED bits only */
+    out8 (I8042_DATA_REG, (kbd_flags & 0x7));   /* LED bits only */
 }
 
 
@@ -633,7 +648,11 @@ static int kbd_reset (void)
     if (kbd_input_empty() == 0)
        return -1;
 
+#ifdef CONFIG_USE_CPCIDVI
+    out8 (I8042_COMMAND_REG, 0x60);
+#else
     out8 (I8042_DATA_REG, 0x60);
+#endif
 
     if (kbd_input_empty() == 0)
        return -1;

diff --git a/drivers/ks8695eth.c b/drivers/ks8695eth.c
index a4b03aee8c7ca0df0ccd92c4313ddb6357bf11e1..b598dd7f23d2cbd3d79723e1033e16ac6b1994ef 100644 (file)
--- a/drivers/ks8695eth.c
+++ b/drivers/ks8695eth.c
@@ -18,11 +18,11 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#ifdef CONFIG_DRIVER_KS8695ETH
-
 /****************************************************************************/
 
 #include <common.h>
+
+#ifdef CONFIG_DRIVER_KS8695ETH
 #include <malloc.h>
 #include <net.h>
 #include <asm/io.h>
@@ -216,10 +216,10 @@ int eth_send(volatile void *packet, int len)
                packet, len);
 
        dp = &ks8695_tx[next];
-       memcpy((void *) dp->addr, packet, len);
+       memcpy((void *) dp->addr, (void *) packet, len);
 
        if (len < 64) {
-               memset(dp->addr+len, 0, 64-len);
+               memset((void *) (dp->addr + len), 0, 64-len);
                len = 64;
        }
 

diff --git a/drivers/lan91c96.c b/drivers/lan91c96.c
index bb03dae39c40722d0a03cf6001194caef8529d6d..a50c5f0abece39e993eb6454ede10f3363ed07af 100644 (file)
--- a/drivers/lan91c96.c
+++ b/drivers/lan91c96.c
@@ -185,21 +185,21 @@ static int smc_rcv (void);
  . If an EEPROM is present it really should be consulted.
 */
 int smc_get_ethaddr(bd_t *bd);
-int get_rom_mac(char *v_rom_mac);
+int get_rom_mac(unsigned char *v_rom_mac);
 
 /* ------------------------------------------------------------
  * Internal routines
  * ------------------------------------------------------------
  */
 
-static char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c };
+static unsigned char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c };
 
 /*
  * This function must be called before smc_open() if you want to override
  * the default mac address.
  */
 
-void smc_set_mac_addr (const char *addr)
+void smc_set_mac_addr (const unsigned char *addr)
 {
        int i;
 
@@ -883,7 +883,7 @@ int smc_get_ethaddr (bd_t * bd)
        char *s = NULL;
        char *e = NULL;
        char *v_mac, es[] = "11:22:33:44:55:66";
-       uchar s_env_mac[64];
+       char s_env_mac[64];
        uchar v_env_mac[6];
        uchar v_rom_mac[6];
 
@@ -905,7 +905,7 @@ int smc_get_ethaddr (bd_t * bd)
 
        if (!env_present) {     /* if NO env */
                if (rom_valid) {        /* but ROM is valid */
-                       v_mac = v_rom_mac;
+                       v_mac = (char *)v_rom_mac;
                        sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
                                 v_mac[0], v_mac[1], v_mac[2], v_mac[3],
                                 v_mac[4], v_mac[5]);
@@ -915,7 +915,7 @@ int smc_get_ethaddr (bd_t * bd)
                        return (-1);
                }
        } else {                /* good env, don't care ROM */
-               v_mac = v_env_mac;      /* always use a good env over a ROM */
+               v_mac = (char *)v_env_mac;      /* always use a good env over a ROM */
        }
 
        if (env_present && rom_valid) { /* if both env and ROM are good */
@@ -935,7 +935,7 @@ int smc_get_ethaddr (bd_t * bd)
                }
        }
        memcpy (bd->bi_enetaddr, v_mac, 6);     /* update global address to match env (allows env changing) */
-       smc_set_mac_addr (v_mac);       /* use old function to update smc default */
+       smc_set_mac_addr ((unsigned char *)v_mac); /* use old function to update smc default */
        PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1],
                v_mac[2], v_mac[3], v_mac[4], v_mac[5]);
        return (0);
@@ -946,7 +946,7 @@ int smc_get_ethaddr (bd_t * bd)
  * Note, this has omly been tested for the OMAP730 P2.
  */
 
-int get_rom_mac (char *v_rom_mac)
+int get_rom_mac (unsigned char *v_rom_mac)
 {
 #ifdef HARDCODE_MAC    /* used for testing or to supress run time warnings */
        char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };

diff --git a/drivers/lan91c96.h b/drivers/lan91c96.h
index b7d7455b9d083ee415fb2f351e12914b38c9e7cb..7d33a821f3c57a3ee147703c46187a09c3b7098a 100644 (file)
--- a/drivers/lan91c96.h
+++ b/drivers/lan91c96.h
@@ -51,7 +51,7 @@
  * in order to override the default mac address.
  */
 
-void smc_set_mac_addr(const char *addr);
+void smc_set_mac_addr(const unsigned char *addr);
 
 
 /* I want some simple types */

diff --git a/drivers/nand/Makefile b/drivers/nand/Makefile
new file mode 100644 (file)
index 0000000..96f67df
--- /dev/null
+++ b/drivers/nand/Makefile
@@ -0,0 +1,16 @@
+include $(TOPDIR)/config.mk
+
+LIB := libnand.a
+
+OBJS := nand.o nand_base.o nand_ids.o nand_ecc.o nand_bbt.o
+all:   $(LIB)
+
+$(LIB):        $(OBJS)
+       $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:       Makefile $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend

diff --git a/drivers/nand/diskonchip.c b/drivers/nand/diskonchip.c
new file mode 100644 (file)
index 0000000..e17af70
--- /dev/null
+++ b/drivers/nand/diskonchip.c
@@ -0,0 +1,1787 @@
+/*
+ * drivers/mtd/nand/diskonchip.c
+ *
+ * (C) 2003 Red Hat, Inc.
+ * (C) 2004 Dan Brown <dan_brown@ieee.org>
+ * (C) 2004 Kalev Lember <kalev@smartlink.ee>
+ *
+ * Author: David Woodhouse <dwmw2@infradead.org>
+ * Additional Diskonchip 2000 and Millennium support by Dan Brown <dan_brown@ieee.org>
+ * Diskonchip Millennium Plus support by Kalev Lember <kalev@smartlink.ee>
+ *
+ * Error correction code lifted from the old docecc code
+ * Author: Fabrice Bellard (fabrice.bellard@netgem.com)
+ * Copyright (C) 2000 Netgem S.A.
+ * converted to the generic Reed-Solomon library by Thomas Gleixner <tglx@linutronix.de>
+ *
+ * Interface to generic NAND code for M-Systems DiskOnChip devices
+ *
+ * $Id: diskonchip.c,v 1.45 2005/01/05 18:05:14 dwmw2 Exp $
+ */
+
+#include <common.h>
+
+#if !defined(CFG_NAND_LEGACY)
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/rslib.h>
+#include <linux/moduleparam.h>
+#include <asm/io.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/doc2000.h>
+#include <linux/mtd/compatmac.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/inftl.h>
+
+/* Where to look for the devices? */
+#ifndef CONFIG_MTD_DISKONCHIP_PROBE_ADDRESS
+#define CONFIG_MTD_DISKONCHIP_PROBE_ADDRESS 0
+#endif
+
+static unsigned long __initdata doc_locations[] = {
+#if defined (__alpha__) || defined(__i386__) || defined(__x86_64__)
+#ifdef CONFIG_MTD_DISKONCHIP_PROBE_HIGH
+       0xfffc8000, 0xfffca000, 0xfffcc000, 0xfffce000,
+       0xfffd0000, 0xfffd2000, 0xfffd4000, 0xfffd6000,
+       0xfffd8000, 0xfffda000, 0xfffdc000, 0xfffde000,
+       0xfffe0000, 0xfffe2000, 0xfffe4000, 0xfffe6000,
+       0xfffe8000, 0xfffea000, 0xfffec000, 0xfffee000,
+#else /*  CONFIG_MTD_DOCPROBE_HIGH */
+       0xc8000, 0xca000, 0xcc000, 0xce000,
+       0xd0000, 0xd2000, 0xd4000, 0xd6000,
+       0xd8000, 0xda000, 0xdc000, 0xde000,
+       0xe0000, 0xe2000, 0xe4000, 0xe6000,
+       0xe8000, 0xea000, 0xec000, 0xee000,
+#endif /*  CONFIG_MTD_DOCPROBE_HIGH */
+#elif defined(__PPC__)
+       0xe4000000,
+#elif defined(CONFIG_MOMENCO_OCELOT)
+       0x2f000000,
+       0xff000000,
+#elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C)
+       0xff000000,
+##else
+#warning Unknown architecture for DiskOnChip. No default probe locations defined
+#endif
+       0xffffffff };
+
+static struct mtd_info *doclist = NULL;
+
+struct doc_priv {
+       void __iomem *virtadr;
+       unsigned long physadr;
+       u_char ChipID;
+       u_char CDSNControl;
+       int chips_per_floor; /* The number of chips detected on each floor */
+       int curfloor;
+       int curchip;
+       int mh0_page;
+       int mh1_page;
+       struct mtd_info *nextdoc;
+};
+
+/* Max number of eraseblocks to scan (from start of device) for the (I)NFTL
+   MediaHeader.  The spec says to just keep going, I think, but that's just
+   silly. */
+#define MAX_MEDIAHEADER_SCAN 8
+
+/* This is the syndrome computed by the HW ecc generator upon reading an empty
+   page, one with all 0xff for data and stored ecc code. */
+static u_char empty_read_syndrome[6] = { 0x26, 0xff, 0x6d, 0x47, 0x73, 0x7a };
+/* This is the ecc value computed by the HW ecc generator upon writing an empty
+   page, one with all 0xff for data. */
+static u_char empty_write_ecc[6] = { 0x4b, 0x00, 0xe2, 0x0e, 0x93, 0xf7 };
+
+#define INFTL_BBT_RESERVED_BLOCKS 4
+
+#define DoC_is_MillenniumPlus(doc) ((doc)->ChipID == DOC_ChipID_DocMilPlus16 || (doc)->ChipID == DOC_ChipID_DocMilPlus32)
+#define DoC_is_Millennium(doc) ((doc)->ChipID == DOC_ChipID_DocMil)
+#define DoC_is_2000(doc) ((doc)->ChipID == DOC_ChipID_Doc2k)
+
+static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd);
+static void doc200x_select_chip(struct mtd_info *mtd, int chip);
+
+static int debug=0;
+module_param(debug, int, 0);
+
+static int try_dword=1;
+module_param(try_dword, int, 0);
+
+static int no_ecc_failures=0;
+module_param(no_ecc_failures, int, 0);
+
+#ifdef CONFIG_MTD_PARTITIONS
+static int no_autopart=0;
+module_param(no_autopart, int, 0);
+#endif
+
+#ifdef MTD_NAND_DISKONCHIP_BBTWRITE
+static int inftl_bbt_write=1;
+#else
+static int inftl_bbt_write=0;
+#endif
+module_param(inftl_bbt_write, int, 0);
+
+static unsigned long doc_config_location = CONFIG_MTD_DISKONCHIP_PROBE_ADDRESS;
+module_param(doc_config_location, ulong, 0);
+MODULE_PARM_DESC(doc_config_location, "Physical memory address at which to probe for DiskOnChip");
+
+
+/* Sector size for HW ECC */
+#define SECTOR_SIZE 512
+/* The sector bytes are packed into NB_DATA 10 bit words */
+#define NB_DATA (((SECTOR_SIZE + 1) * 8 + 6) / 10)
+/* Number of roots */
+#define NROOTS 4
+/* First consective root */
+#define FCR 510
+/* Number of symbols */
+#define NN 1023
+
+/* the Reed Solomon control structure */
+static struct rs_control *rs_decoder;
+
+/*
+ * The HW decoder in the DoC ASIC's provides us a error syndrome,
+ * which we must convert to a standard syndrom usable by the generic
+ * Reed-Solomon library code.
+ *
+ * Fabrice Bellard figured this out in the old docecc code. I added
+ * some comments, improved a minor bit and converted it to make use
+ * of the generic Reed-Solomon libary. tglx
+ */
+static int doc_ecc_decode (struct rs_control *rs, uint8_t *data, uint8_t *ecc)
+{
+       int i, j, nerr, errpos[8];
+       uint8_t parity;
+       uint16_t ds[4], s[5], tmp, errval[8], syn[4];
+
+       /* Convert the ecc bytes into words */
+       ds[0] = ((ecc[4] & 0xff) >> 0) | ((ecc[5] & 0x03) << 8);
+       ds[1] = ((ecc[5] & 0xfc) >> 2) | ((ecc[2] & 0x0f) << 6);
+       ds[2] = ((ecc[2] & 0xf0) >> 4) | ((ecc[3] & 0x3f) << 4);
+       ds[3] = ((ecc[3] & 0xc0) >> 6) | ((ecc[0] & 0xff) << 2);
+       parity = ecc[1];
+
+       /* Initialize the syndrom buffer */
+       for (i = 0; i < NROOTS; i++)
+               s[i] = ds[0];
+       /*
+        *  Evaluate
+        *  s[i] = ds[3]x^3 + ds[2]x^2 + ds[1]x^1 + ds[0]
+        *  where x = alpha^(FCR + i)
+        */
+       for(j = 1; j < NROOTS; j++) {
+               if(ds[j] == 0)
+                       continue;
+               tmp = rs->index_of[ds[j]];
+               for(i = 0; i < NROOTS; i++)
+                       s[i] ^= rs->alpha_to[rs_modnn(rs, tmp + (FCR + i) * j)];
+       }
+
+       /* Calc s[i] = s[i] / alpha^(v + i) */
+       for (i = 0; i < NROOTS; i++) {
+               if (syn[i])
+                       syn[i] = rs_modnn(rs, rs->index_of[s[i]] + (NN - FCR - i));
+       }
+       /* Call the decoder library */
+       nerr = decode_rs16(rs, NULL, NULL, 1019, syn, 0, errpos, 0, errval);
+
+       /* Incorrectable errors ? */
+       if (nerr < 0)
+               return nerr;
+
+       /*
+        * Correct the errors. The bitpositions are a bit of magic,
+        * but they are given by the design of the de/encoder circuit
+        * in the DoC ASIC's.
+        */
+       for(i = 0;i < nerr; i++) {
+               int index, bitpos, pos = 1015 - errpos[i];
+               uint8_t val;
+               if (pos >= NB_DATA && pos < 1019)
+                       continue;
+               if (pos < NB_DATA) {
+                       /* extract bit position (MSB first) */
+                       pos = 10 * (NB_DATA - 1 - pos) - 6;
+                       /* now correct the following 10 bits. At most two bytes
+                          can be modified since pos is even */
+                       index = (pos >> 3) ^ 1;
+                       bitpos = pos & 7;
+                       if ((index >= 0 && index < SECTOR_SIZE) ||
+                           index == (SECTOR_SIZE + 1)) {
+                               val = (uint8_t) (errval[i] >> (2 + bitpos));
+                               parity ^= val;
+                               if (index < SECTOR_SIZE)
+                                       data[index] ^= val;
+                       }
+                       index = ((pos >> 3) + 1) ^ 1;
+                       bitpos = (bitpos + 10) & 7;
+                       if (bitpos == 0)
+                               bitpos = 8;
+                       if ((index >= 0 && index < SECTOR_SIZE) ||
+                           index == (SECTOR_SIZE + 1)) {
+                               val = (uint8_t)(errval[i] << (8 - bitpos));
+                               parity ^= val;
+                               if (index < SECTOR_SIZE)
+                                       data[index] ^= val;
+                       }
+               }
+       }
+       /* If the parity is wrong, no rescue possible */
+       return parity ? -1 : nerr;
+}
+
+static void DoC_Delay(struct doc_priv *doc, unsigned short cycles)
+{
+       volatile char dummy;
+       int i;
+
+       for (i = 0; i < cycles; i++) {
+               if (DoC_is_Millennium(doc))
+                       dummy = ReadDOC(doc->virtadr, NOP);
+               else if (DoC_is_MillenniumPlus(doc))
+                       dummy = ReadDOC(doc->virtadr, Mplus_NOP);
+               else
+                       dummy = ReadDOC(doc->virtadr, DOCStatus);
+       }
+
+}
+
+#define CDSN_CTRL_FR_B_MASK    (CDSN_CTRL_FR_B0 | CDSN_CTRL_FR_B1)
+
+/* DOC_WaitReady: Wait for RDY line to be asserted by the flash chip */
+static int _DoC_WaitReady(struct doc_priv *doc)
+{
+       void __iomem *docptr = doc->virtadr;
+       unsigned long timeo = jiffies + (HZ * 10);
+
+       if(debug) printk("_DoC_WaitReady...\n");
+       /* Out-of-line routine to wait for chip response */
+       if (DoC_is_MillenniumPlus(doc)) {
+               while ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) {
+                       if (time_after(jiffies, timeo)) {
+                               printk("_DoC_WaitReady timed out.\n");
+                               return -EIO;
+                       }
+                       udelay(1);
+                       cond_resched();
+               }
+       } else {
+               while (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) {
+                       if (time_after(jiffies, timeo)) {
+                               printk("_DoC_WaitReady timed out.\n");
+                               return -EIO;
+                       }
+                       udelay(1);
+                       cond_resched();
+               }
+       }
+
+       return 0;
+}
+
+static inline int DoC_WaitReady(struct doc_priv *doc)
+{
+       void __iomem *docptr = doc->virtadr;
+       int ret = 0;
+
+       if (DoC_is_MillenniumPlus(doc)) {
+               DoC_Delay(doc, 4);
+
+               if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK)
+                       /* Call the out-of-line routine to wait */
+                       ret = _DoC_WaitReady(doc);
+       } else {
+               DoC_Delay(doc, 4);
+
+               if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B))
+                       /* Call the out-of-line routine to wait */
+                       ret = _DoC_WaitReady(doc);
+               DoC_Delay(doc, 2);
+       }
+
+       if(debug) printk("DoC_WaitReady OK\n");
+       return ret;
+}
+
+static void doc2000_write_byte(struct mtd_info *mtd, u_char datum)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+
+       if(debug)printk("write_byte %02x\n", datum);
+       WriteDOC(datum, docptr, CDSNSlowIO);
+       WriteDOC(datum, docptr, 2k_CDSN_IO);
+}
+
+static u_char doc2000_read_byte(struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       u_char ret;
+
+       ReadDOC(docptr, CDSNSlowIO);
+       DoC_Delay(doc, 2);
+       ret = ReadDOC(docptr, 2k_CDSN_IO);
+       if (debug) printk("read_byte returns %02x\n", ret);
+       return ret;
+}
+
+static void doc2000_writebuf(struct mtd_info *mtd,
+                            const u_char *buf, int len)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       int i;
+       if (debug)printk("writebuf of %d bytes: ", len);
+       for (i=0; i < len; i++) {
+               WriteDOC_(buf[i], docptr, DoC_2k_CDSN_IO + i);
+               if (debug && i < 16)
+                       printk("%02x ", buf[i]);
+       }
+       if (debug) printk("\n");
+}
+
+static void doc2000_readbuf(struct mtd_info *mtd,
+                           u_char *buf, int len)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       int i;
+
+       if (debug)printk("readbuf of %d bytes: ", len);
+
+       for (i=0; i < len; i++) {
+               buf[i] = ReadDOC(docptr, 2k_CDSN_IO + i);
+       }
+}
+
+static void doc2000_readbuf_dword(struct mtd_info *mtd,
+                           u_char *buf, int len)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       int i;
+
+       if (debug) printk("readbuf_dword of %d bytes: ", len);
+
+       if (unlikely((((unsigned long)buf)|len) & 3)) {
+               for (i=0; i < len; i++) {
+                       *(uint8_t *)(&buf[i]) = ReadDOC(docptr, 2k_CDSN_IO + i);
+               }
+       } else {
+               for (i=0; i < len; i+=4) {
+                       *(uint32_t*)(&buf[i]) = readl(docptr + DoC_2k_CDSN_IO + i);
+               }
+       }
+}
+
+static int doc2000_verifybuf(struct mtd_info *mtd,
+                             const u_char *buf, int len)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       int i;
+
+       for (i=0; i < len; i++)
+               if (buf[i] != ReadDOC(docptr, 2k_CDSN_IO))
+                       return -EFAULT;
+       return 0;
+}
+
+static uint16_t __init doc200x_ident_chip(struct mtd_info *mtd, int nr)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       uint16_t ret;
+
+       doc200x_select_chip(mtd, nr);
+       doc200x_hwcontrol(mtd, NAND_CTL_SETCLE);
+       this->write_byte(mtd, NAND_CMD_READID);
+       doc200x_hwcontrol(mtd, NAND_CTL_CLRCLE);
+       doc200x_hwcontrol(mtd, NAND_CTL_SETALE);
+       this->write_byte(mtd, 0);
+       doc200x_hwcontrol(mtd, NAND_CTL_CLRALE);
+
+       ret = this->read_byte(mtd) << 8;
+       ret |= this->read_byte(mtd);
+
+       if (doc->ChipID == DOC_ChipID_Doc2k && try_dword && !nr) {
+               /* First chip probe. See if we get same results by 32-bit access */
+               union {
+                       uint32_t dword;
+                       uint8_t byte[4];
+               } ident;
+               void __iomem *docptr = doc->virtadr;
+
+               doc200x_hwcontrol(mtd, NAND_CTL_SETCLE);
+               doc2000_write_byte(mtd, NAND_CMD_READID);
+               doc200x_hwcontrol(mtd, NAND_CTL_CLRCLE);
+               doc200x_hwcontrol(mtd, NAND_CTL_SETALE);
+               doc2000_write_byte(mtd, 0);
+               doc200x_hwcontrol(mtd, NAND_CTL_CLRALE);
+
+               ident.dword = readl(docptr + DoC_2k_CDSN_IO);
+               if (((ident.byte[0] << 8) | ident.byte[1]) == ret) {
+                       printk(KERN_INFO "DiskOnChip 2000 responds to DWORD access\n");
+                       this->read_buf = &doc2000_readbuf_dword;
+               }
+       }
+
+       return ret;
+}
+
+static void __init doc2000_count_chips(struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       uint16_t mfrid;
+       int i;
+
+       /* Max 4 chips per floor on DiskOnChip 2000 */
+       doc->chips_per_floor = 4;
+
+       /* Find out what the first chip is */
+       mfrid = doc200x_ident_chip(mtd, 0);
+
+       /* Find how many chips in each floor. */
+       for (i = 1; i < 4; i++) {
+               if (doc200x_ident_chip(mtd, i) != mfrid)
+                       break;
+       }
+       doc->chips_per_floor = i;
+       printk(KERN_DEBUG "Detected %d chips per floor.\n", i);
+}
+
+static int doc200x_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
+{
+       struct doc_priv *doc = this->priv;
+
+       int status;
+
+       DoC_WaitReady(doc);
+       this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+       DoC_WaitReady(doc);
+       status = (int)this->read_byte(mtd);
+
+       return status;
+}
+
+static void doc2001_write_byte(struct mtd_info *mtd, u_char datum)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+
+       WriteDOC(datum, docptr, CDSNSlowIO);
+       WriteDOC(datum, docptr, Mil_CDSN_IO);
+       WriteDOC(datum, docptr, WritePipeTerm);
+}
+
+static u_char doc2001_read_byte(struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+
+       /*ReadDOC(docptr, CDSNSlowIO); */
+       /* 11.4.5 -- delay twice to allow extended length cycle */
+       DoC_Delay(doc, 2);
+       ReadDOC(docptr, ReadPipeInit);
+       /*return ReadDOC(docptr, Mil_CDSN_IO); */
+       return ReadDOC(docptr, LastDataRead);
+}
+
+static void doc2001_writebuf(struct mtd_info *mtd,
+                            const u_char *buf, int len)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       int i;
+
+       for (i=0; i < len; i++)
+               WriteDOC_(buf[i], docptr, DoC_Mil_CDSN_IO + i);
+       /* Terminate write pipeline */
+       WriteDOC(0x00, docptr, WritePipeTerm);
+}
+
+static void doc2001_readbuf(struct mtd_info *mtd,
+                           u_char *buf, int len)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       int i;
+
+       /* Start read pipeline */
+       ReadDOC(docptr, ReadPipeInit);
+
+       for (i=0; i < len-1; i++)
+               buf[i] = ReadDOC(docptr, Mil_CDSN_IO + (i & 0xff));
+
+       /* Terminate read pipeline */
+       buf[i] = ReadDOC(docptr, LastDataRead);
+}
+
+static int doc2001_verifybuf(struct mtd_info *mtd,
+                            const u_char *buf, int len)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       int i;
+
+       /* Start read pipeline */
+       ReadDOC(docptr, ReadPipeInit);
+
+       for (i=0; i < len-1; i++)
+               if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) {
+                       ReadDOC(docptr, LastDataRead);
+                       return i;
+               }
+       if (buf[i] != ReadDOC(docptr, LastDataRead))
+               return i;
+       return 0;
+}
+
+static u_char doc2001plus_read_byte(struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       u_char ret;
+
+       ReadDOC(docptr, Mplus_ReadPipeInit);
+       ReadDOC(docptr, Mplus_ReadPipeInit);
+       ret = ReadDOC(docptr, Mplus_LastDataRead);
+       if (debug) printk("read_byte returns %02x\n", ret);
+       return ret;
+}
+
+static void doc2001plus_writebuf(struct mtd_info *mtd,
+                            const u_char *buf, int len)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       int i;
+
+       if (debug)printk("writebuf of %d bytes: ", len);
+       for (i=0; i < len; i++) {
+               WriteDOC_(buf[i], docptr, DoC_Mil_CDSN_IO + i);
+               if (debug && i < 16)
+                       printk("%02x ", buf[i]);
+       }
+       if (debug) printk("\n");
+}
+
+static void doc2001plus_readbuf(struct mtd_info *mtd,
+                           u_char *buf, int len)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       int i;
+
+       if (debug)printk("readbuf of %d bytes: ", len);
+
+       /* Start read pipeline */
+       ReadDOC(docptr, Mplus_ReadPipeInit);
+       ReadDOC(docptr, Mplus_ReadPipeInit);
+
+       for (i=0; i < len-2; i++) {
+               buf[i] = ReadDOC(docptr, Mil_CDSN_IO);
+               if (debug && i < 16)
+                       printk("%02x ", buf[i]);
+       }
+
+       /* Terminate read pipeline */
+       buf[len-2] = ReadDOC(docptr, Mplus_LastDataRead);
+       if (debug && i < 16)
+               printk("%02x ", buf[len-2]);
+       buf[len-1] = ReadDOC(docptr, Mplus_LastDataRead);
+       if (debug && i < 16)
+               printk("%02x ", buf[len-1]);
+       if (debug) printk("\n");
+}
+
+static int doc2001plus_verifybuf(struct mtd_info *mtd,
+                            const u_char *buf, int len)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       int i;
+
+       if (debug)printk("verifybuf of %d bytes: ", len);
+
+       /* Start read pipeline */
+       ReadDOC(docptr, Mplus_ReadPipeInit);
+       ReadDOC(docptr, Mplus_ReadPipeInit);
+
+       for (i=0; i < len-2; i++)
+               if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) {
+                       ReadDOC(docptr, Mplus_LastDataRead);
+                       ReadDOC(docptr, Mplus_LastDataRead);
+                       return i;
+               }
+       if (buf[len-2] != ReadDOC(docptr, Mplus_LastDataRead))
+               return len-2;
+       if (buf[len-1] != ReadDOC(docptr, Mplus_LastDataRead))
+               return len-1;
+       return 0;
+}
+
+static void doc2001plus_select_chip(struct mtd_info *mtd, int chip)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       int floor = 0;
+
+       if(debug)printk("select chip (%d)\n", chip);
+
+       if (chip == -1) {
+               /* Disable flash internally */
+               WriteDOC(0, docptr, Mplus_FlashSelect);
+               return;
+       }
+
+       floor = chip / doc->chips_per_floor;
+       chip -= (floor *  doc->chips_per_floor);
+
+       /* Assert ChipEnable and deassert WriteProtect */
+       WriteDOC((DOC_FLASH_CE), docptr, Mplus_FlashSelect);
+       this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+
+       doc->curchip = chip;
+       doc->curfloor = floor;
+}
+
+static void doc200x_select_chip(struct mtd_info *mtd, int chip)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       int floor = 0;
+
+       if(debug)printk("select chip (%d)\n", chip);
+
+       if (chip == -1)
+               return;
+
+       floor = chip / doc->chips_per_floor;
+       chip -= (floor *  doc->chips_per_floor);
+
+       /* 11.4.4 -- deassert CE before changing chip */
+       doc200x_hwcontrol(mtd, NAND_CTL_CLRNCE);
+
+       WriteDOC(floor, docptr, FloorSelect);
+       WriteDOC(chip, docptr, CDSNDeviceSelect);
+
+       doc200x_hwcontrol(mtd, NAND_CTL_SETNCE);
+
+       doc->curchip = chip;
+       doc->curfloor = floor;
+}
+
+static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+
+       switch(cmd) {
+       case NAND_CTL_SETNCE:
+               doc->CDSNControl |= CDSN_CTRL_CE;
+               break;
+       case NAND_CTL_CLRNCE:
+               doc->CDSNControl &= ~CDSN_CTRL_CE;
+               break;
+       case NAND_CTL_SETCLE:
+               doc->CDSNControl |= CDSN_CTRL_CLE;
+               break;
+       case NAND_CTL_CLRCLE:
+               doc->CDSNControl &= ~CDSN_CTRL_CLE;
+               break;
+       case NAND_CTL_SETALE:
+               doc->CDSNControl |= CDSN_CTRL_ALE;
+               break;
+       case NAND_CTL_CLRALE:
+               doc->CDSNControl &= ~CDSN_CTRL_ALE;
+               break;
+       case NAND_CTL_SETWP:
+               doc->CDSNControl |= CDSN_CTRL_WP;
+               break;
+       case NAND_CTL_CLRWP:
+               doc->CDSNControl &= ~CDSN_CTRL_WP;
+               break;
+       }
+       if (debug)printk("hwcontrol(%d): %02x\n", cmd, doc->CDSNControl);
+       WriteDOC(doc->CDSNControl, docptr, CDSNControl);
+       /* 11.4.3 -- 4 NOPs after CSDNControl write */
+       DoC_Delay(doc, 4);
+}
+
+static void doc2001plus_command (struct mtd_info *mtd, unsigned command, int column, int page_addr)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+
+       /*
+        * Must terminate write pipeline before sending any commands
+        * to the device.
+        */
+       if (command == NAND_CMD_PAGEPROG) {
+               WriteDOC(0x00, docptr, Mplus_WritePipeTerm);
+               WriteDOC(0x00, docptr, Mplus_WritePipeTerm);
+       }
+
+       /*
+        * Write out the command to the device.
+        */
+       if (command == NAND_CMD_SEQIN) {
+               int readcmd;
+
+               if (column >= mtd->oobblock) {
+                       /* OOB area */
+                       column -= mtd->oobblock;
+                       readcmd = NAND_CMD_READOOB;
+               } else if (column < 256) {
+                       /* First 256 bytes --> READ0 */
+                       readcmd = NAND_CMD_READ0;
+               } else {
+                       column -= 256;
+                       readcmd = NAND_CMD_READ1;
+               }
+               WriteDOC(readcmd, docptr, Mplus_FlashCmd);
+       }
+       WriteDOC(command, docptr, Mplus_FlashCmd);
+       WriteDOC(0, docptr, Mplus_WritePipeTerm);
+       WriteDOC(0, docptr, Mplus_WritePipeTerm);
+
+       if (column != -1 || page_addr != -1) {
+               /* Serially input address */
+               if (column != -1) {
+                       /* Adjust columns for 16 bit buswidth */
+                       if (this->options & NAND_BUSWIDTH_16)
+                               column >>= 1;
+                       WriteDOC(column, docptr, Mplus_FlashAddress);
+               }
+               if (page_addr != -1) {
+                       WriteDOC((unsigned char) (page_addr & 0xff), docptr, Mplus_FlashAddress);
+                       WriteDOC((unsigned char) ((page_addr >> 8) & 0xff), docptr, Mplus_FlashAddress);
+                       /* One more address cycle for higher density devices */
+                       if (this->chipsize & 0x0c000000) {
+                               WriteDOC((unsigned char) ((page_addr >> 16) & 0x0f), docptr, Mplus_FlashAddress);
+                               printk("high density\n");
+                       }
+               }
+               WriteDOC(0, docptr, Mplus_WritePipeTerm);
+               WriteDOC(0, docptr, Mplus_WritePipeTerm);
+               /* deassert ALE */
+               if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || command == NAND_CMD_READOOB || command == NAND_CMD_READID)
+                       WriteDOC(0, docptr, Mplus_FlashControl);
+       }
+
+       /*
+        * program and erase have their own busy handlers
+        * status and sequential in needs no delay
+       */
+       switch (command) {
+
+       case NAND_CMD_PAGEPROG:
+       case NAND_CMD_ERASE1:
+       case NAND_CMD_ERASE2:
+       case NAND_CMD_SEQIN:
+       case NAND_CMD_STATUS:
+               return;
+
+       case NAND_CMD_RESET:
+               if (this->dev_ready)
+                       break;
+               udelay(this->chip_delay);
+               WriteDOC(NAND_CMD_STATUS, docptr, Mplus_FlashCmd);
+               WriteDOC(0, docptr, Mplus_WritePipeTerm);
+               WriteDOC(0, docptr, Mplus_WritePipeTerm);
+               while ( !(this->read_byte(mtd) & 0x40));
+               return;
+
+       /* This applies to read commands */
+       default:
+               /*
+                * If we don't have access to the busy pin, we apply the given
+                * command delay
+               */
+               if (!this->dev_ready) {
+                       udelay (this->chip_delay);
+                       return;
+               }
+       }
+
+       /* Apply this short delay always to ensure that we do wait tWB in
+        * any case on any machine. */
+       ndelay (100);
+       /* wait until command is processed */
+       while (!this->dev_ready(mtd));
+}
+
+static int doc200x_dev_ready(struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+
+       if (DoC_is_MillenniumPlus(doc)) {
+               /* 11.4.2 -- must NOP four times before checking FR/B# */
+               DoC_Delay(doc, 4);
+               if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) {
+                       if(debug)
+                               printk("not ready\n");
+                       return 0;
+               }
+               if (debug)printk("was ready\n");
+               return 1;
+       } else {
+               /* 11.4.2 -- must NOP four times before checking FR/B# */
+               DoC_Delay(doc, 4);
+               if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) {
+                       if(debug)
+                               printk("not ready\n");
+                       return 0;
+               }
+               /* 11.4.2 -- Must NOP twice if it's ready */
+               DoC_Delay(doc, 2);
+               if (debug)printk("was ready\n");
+               return 1;
+       }
+}
+
+static int doc200x_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+{
+       /* This is our last resort if we couldn't find or create a BBT.  Just
+          pretend all blocks are good. */
+       return 0;
+}
+
+static void doc200x_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+
+       /* Prime the ECC engine */
+       switch(mode) {
+       case NAND_ECC_READ:
+               WriteDOC(DOC_ECC_RESET, docptr, ECCConf);
+               WriteDOC(DOC_ECC_EN, docptr, ECCConf);
+               break;
+       case NAND_ECC_WRITE:
+               WriteDOC(DOC_ECC_RESET, docptr, ECCConf);
+               WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, ECCConf);
+               break;
+       }
+}
+
+static void doc2001plus_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+
+       /* Prime the ECC engine */
+       switch(mode) {
+       case NAND_ECC_READ:
+               WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf);
+               WriteDOC(DOC_ECC_EN, docptr, Mplus_ECCConf);
+               break;
+       case NAND_ECC_WRITE:
+               WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf);
+               WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, Mplus_ECCConf);
+               break;
+       }
+}
+
+/* This code is only called on write */
+static int doc200x_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+                                unsigned char *ecc_code)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       int i;
+       int emptymatch = 1;
+
+       /* flush the pipeline */
+       if (DoC_is_2000(doc)) {
+               WriteDOC(doc->CDSNControl & ~CDSN_CTRL_FLASH_IO, docptr, CDSNControl);
+               WriteDOC(0, docptr, 2k_CDSN_IO);
+               WriteDOC(0, docptr, 2k_CDSN_IO);
+               WriteDOC(0, docptr, 2k_CDSN_IO);
+               WriteDOC(doc->CDSNControl, docptr, CDSNControl);
+       } else if (DoC_is_MillenniumPlus(doc)) {
+               WriteDOC(0, docptr, Mplus_NOP);
+               WriteDOC(0, docptr, Mplus_NOP);
+               WriteDOC(0, docptr, Mplus_NOP);
+       } else {
+               WriteDOC(0, docptr, NOP);
+               WriteDOC(0, docptr, NOP);
+               WriteDOC(0, docptr, NOP);
+       }
+
+       for (i = 0; i < 6; i++) {
+               if (DoC_is_MillenniumPlus(doc))
+                       ecc_code[i] = ReadDOC_(docptr, DoC_Mplus_ECCSyndrome0 + i);
+               else
+                       ecc_code[i] = ReadDOC_(docptr, DoC_ECCSyndrome0 + i);
+               if (ecc_code[i] != empty_write_ecc[i])
+                       emptymatch = 0;
+       }
+       if (DoC_is_MillenniumPlus(doc))
+               WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf);
+       else
+               WriteDOC(DOC_ECC_DIS, docptr, ECCConf);
+#if 0
+       /* If emptymatch=1, we might have an all-0xff data buffer.  Check. */
+       if (emptymatch) {
+               /* Note: this somewhat expensive test should not be triggered
+                  often.  It could be optimized away by examining the data in
+                  the writebuf routine, and remembering the result. */
+               for (i = 0; i < 512; i++) {
+                       if (dat[i] == 0xff) continue;
+                       emptymatch = 0;
+                       break;
+               }
+       }
+       /* If emptymatch still =1, we do have an all-0xff data buffer.
+          Return all-0xff ecc value instead of the computed one, so
+          it'll look just like a freshly-erased page. */
+       if (emptymatch) memset(ecc_code, 0xff, 6);
+#endif
+       return 0;
+}
+
+static int doc200x_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
+{
+       int i, ret = 0;
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       void __iomem *docptr = doc->virtadr;
+       volatile u_char dummy;
+       int emptymatch = 1;
+
+       /* flush the pipeline */
+       if (DoC_is_2000(doc)) {
+               dummy = ReadDOC(docptr, 2k_ECCStatus);
+               dummy = ReadDOC(docptr, 2k_ECCStatus);
+               dummy = ReadDOC(docptr, 2k_ECCStatus);
+       } else if (DoC_is_MillenniumPlus(doc)) {
+               dummy = ReadDOC(docptr, Mplus_ECCConf);
+               dummy = ReadDOC(docptr, Mplus_ECCConf);
+               dummy = ReadDOC(docptr, Mplus_ECCConf);
+       } else {
+               dummy = ReadDOC(docptr, ECCConf);
+               dummy = ReadDOC(docptr, ECCConf);
+               dummy = ReadDOC(docptr, ECCConf);
+       }
+
+       /* Error occured ? */
+       if (dummy & 0x80) {
+               for (i = 0; i < 6; i++) {
+                       if (DoC_is_MillenniumPlus(doc))
+                               calc_ecc[i] = ReadDOC_(docptr, DoC_Mplus_ECCSyndrome0 + i);
+                       else
+                               calc_ecc[i] = ReadDOC_(docptr, DoC_ECCSyndrome0 + i);
+                       if (calc_ecc[i] != empty_read_syndrome[i])
+                               emptymatch = 0;
+               }
+               /* If emptymatch=1, the read syndrome is consistent with an
+                  all-0xff data and stored ecc block.  Check the stored ecc. */
+               if (emptymatch) {
+                       for (i = 0; i < 6; i++) {
+                               if (read_ecc[i] == 0xff) continue;
+                               emptymatch = 0;
+                               break;
+                       }
+               }
+               /* If emptymatch still =1, check the data block. */
+               if (emptymatch) {
+               /* Note: this somewhat expensive test should not be triggered
+                  often.  It could be optimized away by examining the data in
+                  the readbuf routine, and remembering the result. */
+                       for (i = 0; i < 512; i++) {
+                               if (dat[i] == 0xff) continue;
+                               emptymatch = 0;
+                               break;
+                       }
+               }
+               /* If emptymatch still =1, this is almost certainly a freshly-
+                  erased block, in which case the ECC will not come out right.
+                  We'll suppress the error and tell the caller everything's
+                  OK.  Because it is. */
+               if (!emptymatch) ret = doc_ecc_decode (rs_decoder, dat, calc_ecc);
+               if (ret > 0)
+                       printk(KERN_ERR "doc200x_correct_data corrected %d errors\n", ret);
+       }
+       if (DoC_is_MillenniumPlus(doc))
+               WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf);
+       else
+               WriteDOC(DOC_ECC_DIS, docptr, ECCConf);
+       if (no_ecc_failures && (ret == -1)) {
+               printk(KERN_ERR "suppressing ECC failure\n");
+               ret = 0;
+       }
+       return ret;
+}
+
+/*u_char mydatabuf[528]; */
+
+static struct nand_oobinfo doc200x_oobinfo = {
+       .useecc = MTD_NANDECC_AUTOPLACE,
+       .eccbytes = 6,
+       .eccpos = {0, 1, 2, 3, 4, 5},
+       .oobfree = { {8, 8} }
+};
+
+/* Find the (I)NFTL Media Header, and optionally also the mirror media header.
+   On sucessful return, buf will contain a copy of the media header for
+   further processing.  id is the string to scan for, and will presumably be
+   either "ANAND" or "BNAND".  If findmirror=1, also look for the mirror media
+   header.  The page #s of the found media headers are placed in mh0_page and
+   mh1_page in the DOC private structure. */
+static int __init find_media_headers(struct mtd_info *mtd, u_char *buf,
+                                    const char *id, int findmirror)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       unsigned offs, end = (MAX_MEDIAHEADER_SCAN << this->phys_erase_shift);
+       int ret;
+       size_t retlen;
+
+       end = min(end, mtd->size); /* paranoia */
+       for (offs = 0; offs < end; offs += mtd->erasesize) {
+               ret = mtd->read(mtd, offs, mtd->oobblock, &retlen, buf);
+               if (retlen != mtd->oobblock) continue;
+               if (ret) {
+                       printk(KERN_WARNING "ECC error scanning DOC at 0x%x\n",
+                               offs);
+               }
+               if (memcmp(buf, id, 6)) continue;
+               printk(KERN_INFO "Found DiskOnChip %s Media Header at 0x%x\n", id, offs);
+               if (doc->mh0_page == -1) {
+                       doc->mh0_page = offs >> this->page_shift;
+                       if (!findmirror) return 1;
+                       continue;
+               }
+               doc->mh1_page = offs >> this->page_shift;
+               return 2;
+       }
+       if (doc->mh0_page == -1) {
+               printk(KERN_WARNING "DiskOnChip %s Media Header not found.\n", id);
+               return 0;
+       }
+       /* Only one mediaheader was found.  We want buf to contain a
+          mediaheader on return, so we'll have to re-read the one we found. */
+       offs = doc->mh0_page << this->page_shift;
+       ret = mtd->read(mtd, offs, mtd->oobblock, &retlen, buf);
+       if (retlen != mtd->oobblock) {
+               /* Insanity.  Give up. */
+               printk(KERN_ERR "Read DiskOnChip Media Header once, but can't reread it???\n");
+               return 0;
+       }
+       return 1;
+}
+
+static inline int __init nftl_partscan(struct mtd_info *mtd,
+                               struct mtd_partition *parts)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       int ret = 0;
+       u_char *buf;
+       struct NFTLMediaHeader *mh;
+       const unsigned psize = 1 << this->page_shift;
+       unsigned blocks, maxblocks;
+       int offs, numheaders;
+
+       buf = kmalloc(mtd->oobblock, GFP_KERNEL);
+       if (!buf) {
+               printk(KERN_ERR "DiskOnChip mediaheader kmalloc failed!\n");
+               return 0;
+       }
+       if (!(numheaders=find_media_headers(mtd, buf, "ANAND", 1))) goto out;
+       mh = (struct NFTLMediaHeader *) buf;
+
+/*#ifdef CONFIG_MTD_DEBUG_VERBOSE */
+/*     if (CONFIG_MTD_DEBUG_VERBOSE >= 2) */
+       printk(KERN_INFO "    DataOrgID        = %s\n"
+                        "    NumEraseUnits    = %d\n"
+                        "    FirstPhysicalEUN = %d\n"
+                        "    FormattedSize    = %d\n"
+                        "    UnitSizeFactor   = %d\n",
+               mh->DataOrgID, mh->NumEraseUnits,
+               mh->FirstPhysicalEUN, mh->FormattedSize,
+               mh->UnitSizeFactor);
+/*#endif */
+
+       blocks = mtd->size >> this->phys_erase_shift;
+       maxblocks = min(32768U, mtd->erasesize - psize);
+
+       if (mh->UnitSizeFactor == 0x00) {
+               /* Auto-determine UnitSizeFactor.  The constraints are:
+                  - There can be at most 32768 virtual blocks.
+                  - There can be at most (virtual block size - page size)
+                    virtual blocks (because MediaHeader+BBT must fit in 1).
+               */
+               mh->UnitSizeFactor = 0xff;
+               while (blocks > maxblocks) {
+                       blocks >>= 1;
+                       maxblocks = min(32768U, (maxblocks << 1) + psize);
+                       mh->UnitSizeFactor--;
+               }
+               printk(KERN_WARNING "UnitSizeFactor=0x00 detected.  Correct value is assumed to be 0x%02x.\n", mh->UnitSizeFactor);
+       }
+
+       /* NOTE: The lines below modify internal variables of the NAND and MTD
+          layers; variables with have already been configured by nand_scan.
+          Unfortunately, we didn't know before this point what these values
+          should be.  Thus, this code is somewhat dependant on the exact
+          implementation of the NAND layer.  */
+       if (mh->UnitSizeFactor != 0xff) {
+               this->bbt_erase_shift += (0xff - mh->UnitSizeFactor);
+               mtd->erasesize <<= (0xff - mh->UnitSizeFactor);
+               printk(KERN_INFO "Setting virtual erase size to %d\n", mtd->erasesize);
+               blocks = mtd->size >> this->bbt_erase_shift;
+               maxblocks = min(32768U, mtd->erasesize - psize);
+       }
+
+       if (blocks > maxblocks) {
+               printk(KERN_ERR "UnitSizeFactor of 0x%02x is inconsistent with device size.  Aborting.\n", mh->UnitSizeFactor);
+               goto out;
+       }
+
+       /* Skip past the media headers. */
+       offs = max(doc->mh0_page, doc->mh1_page);
+       offs <<= this->page_shift;
+       offs += mtd->erasesize;
+
+       /*parts[0].name = " DiskOnChip Boot / Media Header partition"; */
+       /*parts[0].offset = 0; */
+       /*parts[0].size = offs; */
+
+       parts[0].name = " DiskOnChip BDTL partition";
+       parts[0].offset = offs;
+       parts[0].size = (mh->NumEraseUnits - numheaders) << this->bbt_erase_shift;
+
+       offs += parts[0].size;
+       if (offs < mtd->size) {
+               parts[1].name = " DiskOnChip Remainder partition";
+               parts[1].offset = offs;
+               parts[1].size = mtd->size - offs;
+               ret = 2;
+               goto out;
+       }
+       ret = 1;
+out:
+       kfree(buf);
+       return ret;
+}
+
+/* This is a stripped-down copy of the code in inftlmount.c */
+static inline int __init inftl_partscan(struct mtd_info *mtd,
+                                struct mtd_partition *parts)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       int ret = 0;
+       u_char *buf;
+       struct INFTLMediaHeader *mh;
+       struct INFTLPartition *ip;
+       int numparts = 0;
+       int blocks;
+       int vshift, lastvunit = 0;
+       int i;
+       int end = mtd->size;
+
+       if (inftl_bbt_write)
+               end -= (INFTL_BBT_RESERVED_BLOCKS << this->phys_erase_shift);
+
+       buf = kmalloc(mtd->oobblock, GFP_KERNEL);
+       if (!buf) {
+               printk(KERN_ERR "DiskOnChip mediaheader kmalloc failed!\n");
+               return 0;
+       }
+
+       if (!find_media_headers(mtd, buf, "BNAND", 0)) goto out;
+       doc->mh1_page = doc->mh0_page + (4096 >> this->page_shift);
+       mh = (struct INFTLMediaHeader *) buf;
+
+       mh->NoOfBootImageBlocks = le32_to_cpu(mh->NoOfBootImageBlocks);
+       mh->NoOfBinaryPartitions = le32_to_cpu(mh->NoOfBinaryPartitions);
+       mh->NoOfBDTLPartitions = le32_to_cpu(mh->NoOfBDTLPartitions);
+       mh->BlockMultiplierBits = le32_to_cpu(mh->BlockMultiplierBits);
+       mh->FormatFlags = le32_to_cpu(mh->FormatFlags);
+       mh->PercentUsed = le32_to_cpu(mh->PercentUsed);
+
+/*#ifdef CONFIG_MTD_DEBUG_VERBOSE */
+/*     if (CONFIG_MTD_DEBUG_VERBOSE >= 2) */
+       printk(KERN_INFO "    bootRecordID          = %s\n"
+                        "    NoOfBootImageBlocks   = %d\n"
+                        "    NoOfBinaryPartitions  = %d\n"
+                        "    NoOfBDTLPartitions    = %d\n"
+                        "    BlockMultiplerBits    = %d\n"
+                        "    FormatFlgs            = %d\n"
+                        "    OsakVersion           = %d.%d.%d.%d\n"
+                        "    PercentUsed           = %d\n",
+               mh->bootRecordID, mh->NoOfBootImageBlocks,
+               mh->NoOfBinaryPartitions,
+               mh->NoOfBDTLPartitions,
+               mh->BlockMultiplierBits, mh->FormatFlags,
+               ((unsigned char *) &mh->OsakVersion)[0] & 0xf,
+               ((unsigned char *) &mh->OsakVersion)[1] & 0xf,
+               ((unsigned char *) &mh->OsakVersion)[2] & 0xf,
+               ((unsigned char *) &mh->OsakVersion)[3] & 0xf,
+               mh->PercentUsed);
+/*#endif */
+
+       vshift = this->phys_erase_shift + mh->BlockMultiplierBits;
+
+       blocks = mtd->size >> vshift;
+       if (blocks > 32768) {
+               printk(KERN_ERR "BlockMultiplierBits=%d is inconsistent with device size.  Aborting.\n", mh->BlockMultiplierBits);
+               goto out;
+       }
+
+       blocks = doc->chips_per_floor << (this->chip_shift - this->phys_erase_shift);
+       if (inftl_bbt_write && (blocks > mtd->erasesize)) {
+               printk(KERN_ERR "Writeable BBTs spanning more than one erase block are not yet supported.  FIX ME!\n");
+               goto out;
+       }
+
+       /* Scan the partitions */
+       for (i = 0; (i < 4); i++) {
+               ip = &(mh->Partitions[i]);
+               ip->virtualUnits = le32_to_cpu(ip->virtualUnits);
+               ip->firstUnit = le32_to_cpu(ip->firstUnit);
+               ip->lastUnit = le32_to_cpu(ip->lastUnit);
+               ip->flags = le32_to_cpu(ip->flags);
+               ip->spareUnits = le32_to_cpu(ip->spareUnits);
+               ip->Reserved0 = le32_to_cpu(ip->Reserved0);
+
+/*#ifdef CONFIG_MTD_DEBUG_VERBOSE */
+/*             if (CONFIG_MTD_DEBUG_VERBOSE >= 2) */
+               printk(KERN_INFO        "    PARTITION[%d] ->\n"
+                       "        virtualUnits    = %d\n"
+                       "        firstUnit       = %d\n"
+                       "        lastUnit        = %d\n"
+                       "        flags           = 0x%x\n"
+                       "        spareUnits      = %d\n",
+                       i, ip->virtualUnits, ip->firstUnit,
+                       ip->lastUnit, ip->flags,
+                       ip->spareUnits);
+/*#endif */
+
+/*
+               if ((i == 0) && (ip->firstUnit > 0)) {
+                       parts[0].name = " DiskOnChip IPL / Media Header partition";
+                       parts[0].offset = 0;
+                       parts[0].size = mtd->erasesize * ip->firstUnit;
+                       numparts = 1;
+               }
+*/
+
+               if (ip->flags & INFTL_BINARY)
+                       parts[numparts].name = " DiskOnChip BDK partition";
+               else
+                       parts[numparts].name = " DiskOnChip BDTL partition";
+               parts[numparts].offset = ip->firstUnit << vshift;
+               parts[numparts].size = (1 + ip->lastUnit - ip->firstUnit) << vshift;
+               numparts++;
+               if (ip->lastUnit > lastvunit) lastvunit = ip->lastUnit;
+               if (ip->flags & INFTL_LAST) break;
+       }
+       lastvunit++;
+       if ((lastvunit << vshift) < end) {
+               parts[numparts].name = " DiskOnChip Remainder partition";
+               parts[numparts].offset = lastvunit << vshift;
+               parts[numparts].size = end - parts[numparts].offset;
+               numparts++;
+       }
+       ret = numparts;
+out:
+       kfree(buf);
+       return ret;
+}
+
+static int __init nftl_scan_bbt(struct mtd_info *mtd)
+{
+       int ret, numparts;
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       struct mtd_partition parts[2];
+
+       memset((char *) parts, 0, sizeof(parts));
+       /* On NFTL, we have to find the media headers before we can read the
+          BBTs, since they're stored in the media header eraseblocks. */
+       numparts = nftl_partscan(mtd, parts);
+       if (!numparts) return -EIO;
+       this->bbt_td->options = NAND_BBT_ABSPAGE | NAND_BBT_8BIT |
+                               NAND_BBT_SAVECONTENT | NAND_BBT_WRITE |
+                               NAND_BBT_VERSION;
+       this->bbt_td->veroffs = 7;
+       this->bbt_td->pages[0] = doc->mh0_page + 1;
+       if (doc->mh1_page != -1) {
+               this->bbt_md->options = NAND_BBT_ABSPAGE | NAND_BBT_8BIT |
+                                       NAND_BBT_SAVECONTENT | NAND_BBT_WRITE |
+                                       NAND_BBT_VERSION;
+               this->bbt_md->veroffs = 7;
+               this->bbt_md->pages[0] = doc->mh1_page + 1;
+       } else {
+               this->bbt_md = NULL;
+       }
+
+       /* It's safe to set bd=NULL below because NAND_BBT_CREATE is not set.
+          At least as nand_bbt.c is currently written. */
+       if ((ret = nand_scan_bbt(mtd, NULL)))
+               return ret;
+       add_mtd_device(mtd);
+#ifdef CONFIG_MTD_PARTITIONS
+       if (!no_autopart)
+               add_mtd_partitions(mtd, parts, numparts);
+#endif
+       return 0;
+}
+
+static int __init inftl_scan_bbt(struct mtd_info *mtd)
+{
+       int ret, numparts;
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+       struct mtd_partition parts[5];
+
+       if (this->numchips > doc->chips_per_floor) {
+               printk(KERN_ERR "Multi-floor INFTL devices not yet supported.\n");
+               return -EIO;
+       }
+
+       if (DoC_is_MillenniumPlus(doc)) {
+               this->bbt_td->options = NAND_BBT_2BIT | NAND_BBT_ABSPAGE;
+               if (inftl_bbt_write)
+                       this->bbt_td->options |= NAND_BBT_WRITE;
+               this->bbt_td->pages[0] = 2;
+               this->bbt_md = NULL;
+       } else {
+               this->bbt_td->options = NAND_BBT_LASTBLOCK | NAND_BBT_8BIT |
+                                       NAND_BBT_VERSION;
+               if (inftl_bbt_write)
+                       this->bbt_td->options |= NAND_BBT_WRITE;
+               this->bbt_td->offs = 8;
+               this->bbt_td->len = 8;
+               this->bbt_td->veroffs = 7;
+               this->bbt_td->maxblocks = INFTL_BBT_RESERVED_BLOCKS;
+               this->bbt_td->reserved_block_code = 0x01;
+               this->bbt_td->pattern = "MSYS_BBT";
+
+               this->bbt_md->options = NAND_BBT_LASTBLOCK | NAND_BBT_8BIT |
+                                       NAND_BBT_VERSION;
+               if (inftl_bbt_write)
+                       this->bbt_md->options |= NAND_BBT_WRITE;
+               this->bbt_md->offs = 8;
+               this->bbt_md->len = 8;
+               this->bbt_md->veroffs = 7;
+               this->bbt_md->maxblocks = INFTL_BBT_RESERVED_BLOCKS;
+               this->bbt_md->reserved_block_code = 0x01;
+               this->bbt_md->pattern = "TBB_SYSM";
+       }
+
+       /* It's safe to set bd=NULL below because NAND_BBT_CREATE is not set.
+          At least as nand_bbt.c is currently written. */
+       if ((ret = nand_scan_bbt(mtd, NULL)))
+               return ret;
+       memset((char *) parts, 0, sizeof(parts));
+       numparts = inftl_partscan(mtd, parts);
+       /* At least for now, require the INFTL Media Header.  We could probably
+          do without it for non-INFTL use, since all it gives us is
+          autopartitioning, but I want to give it more thought. */
+       if (!numparts) return -EIO;
+       add_mtd_device(mtd);
+#ifdef CONFIG_MTD_PARTITIONS
+       if (!no_autopart)
+               add_mtd_partitions(mtd, parts, numparts);
+#endif
+       return 0;
+}
+
+static inline int __init doc2000_init(struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+
+       this->write_byte = doc2000_write_byte;
+       this->read_byte = doc2000_read_byte;
+       this->write_buf = doc2000_writebuf;
+       this->read_buf = doc2000_readbuf;
+       this->verify_buf = doc2000_verifybuf;
+       this->scan_bbt = nftl_scan_bbt;
+
+       doc->CDSNControl = CDSN_CTRL_FLASH_IO | CDSN_CTRL_ECC_IO;
+       doc2000_count_chips(mtd);
+       mtd->name = "DiskOnChip 2000 (NFTL Model)";
+       return (4 * doc->chips_per_floor);
+}
+
+static inline int __init doc2001_init(struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+
+       this->write_byte = doc2001_write_byte;
+       this->read_byte = doc2001_read_byte;
+       this->write_buf = doc2001_writebuf;
+       this->read_buf = doc2001_readbuf;
+       this->verify_buf = doc2001_verifybuf;
+
+       ReadDOC(doc->virtadr, ChipID);
+       ReadDOC(doc->virtadr, ChipID);
+       ReadDOC(doc->virtadr, ChipID);
+       if (ReadDOC(doc->virtadr, ChipID) != DOC_ChipID_DocMil) {
+               /* It's not a Millennium; it's one of the newer
+                  DiskOnChip 2000 units with a similar ASIC.
+                  Treat it like a Millennium, except that it
+                  can have multiple chips. */
+               doc2000_count_chips(mtd);
+               mtd->name = "DiskOnChip 2000 (INFTL Model)";
+               this->scan_bbt = inftl_scan_bbt;
+               return (4 * doc->chips_per_floor);
+       } else {
+               /* Bog-standard Millennium */
+               doc->chips_per_floor = 1;
+               mtd->name = "DiskOnChip Millennium";
+               this->scan_bbt = nftl_scan_bbt;
+               return 1;
+       }
+}
+
+static inline int __init doc2001plus_init(struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+       struct doc_priv *doc = this->priv;
+
+       this->write_byte = NULL;
+       this->read_byte = doc2001plus_read_byte;
+       this->write_buf = doc2001plus_writebuf;
+       this->read_buf = doc2001plus_readbuf;
+       this->verify_buf = doc2001plus_verifybuf;
+       this->scan_bbt = inftl_scan_bbt;
+       this->hwcontrol = NULL;
+       this->select_chip = doc2001plus_select_chip;
+       this->cmdfunc = doc2001plus_command;
+       this->enable_hwecc = doc2001plus_enable_hwecc;
+
+       doc->chips_per_floor = 1;
+       mtd->name = "DiskOnChip Millennium Plus";
+
+       return 1;
+}
+
+static inline int __init doc_probe(unsigned long physadr)
+{
+       unsigned char ChipID;
+       struct mtd_info *mtd;
+       struct nand_chip *nand;
+       struct doc_priv *doc;
+       void __iomem *virtadr;
+       unsigned char save_control;
+       unsigned char tmp, tmpb, tmpc;
+       int reg, len, numchips;
+       int ret = 0;
+
+       virtadr = ioremap(physadr, DOC_IOREMAP_LEN);
+       if (!virtadr) {
+               printk(KERN_ERR "Diskonchip ioremap failed: 0x%x bytes at 0x%lx\n", DOC_IOREMAP_LEN, physadr);
+               return -EIO;
+       }
+
+       /* It's not possible to cleanly detect the DiskOnChip - the
+        * bootup procedure will put the device into reset mode, and
+        * it's not possible to talk to it without actually writing
+        * to the DOCControl register. So we store the current contents
+        * of the DOCControl register's location, in case we later decide
+        * that it's not a DiskOnChip, and want to put it back how we
+        * found it.
+        */
+       save_control = ReadDOC(virtadr, DOCControl);
+
+       /* Reset the DiskOnChip ASIC */
+       WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET,
+                virtadr, DOCControl);
+       WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET,
+                virtadr, DOCControl);
+
+       /* Enable the DiskOnChip ASIC */
+       WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL,
+                virtadr, DOCControl);
+       WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL,
+                virtadr, DOCControl);
+
+       ChipID = ReadDOC(virtadr, ChipID);
+
+       switch(ChipID) {
+       case DOC_ChipID_Doc2k:
+               reg = DoC_2k_ECCStatus;
+               break;
+       case DOC_ChipID_DocMil:
+               reg = DoC_ECCConf;
+               break;
+       case DOC_ChipID_DocMilPlus16:
+       case DOC_ChipID_DocMilPlus32:
+       case 0:
+               /* Possible Millennium Plus, need to do more checks */
+               /* Possibly release from power down mode */
+               for (tmp = 0; (tmp < 4); tmp++)
+                       ReadDOC(virtadr, Mplus_Power);
+
+               /* Reset the Millennium Plus ASIC */
+               tmp = DOC_MODE_RESET | DOC_MODE_MDWREN | DOC_MODE_RST_LAT |
+                       DOC_MODE_BDECT;
+               WriteDOC(tmp, virtadr, Mplus_DOCControl);
+               WriteDOC(~tmp, virtadr, Mplus_CtrlConfirm);
+
+               mdelay(1);
+               /* Enable the Millennium Plus ASIC */
+               tmp = DOC_MODE_NORMAL | DOC_MODE_MDWREN | DOC_MODE_RST_LAT |
+                       DOC_MODE_BDECT;
+               WriteDOC(tmp, virtadr, Mplus_DOCControl);
+               WriteDOC(~tmp, virtadr, Mplus_CtrlConfirm);
+               mdelay(1);
+
+               ChipID = ReadDOC(virtadr, ChipID);
+
+               switch (ChipID) {
+               case DOC_ChipID_DocMilPlus16:
+                       reg = DoC_Mplus_Toggle;
+                       break;
+               case DOC_ChipID_DocMilPlus32:
+                       printk(KERN_ERR "DiskOnChip Millennium Plus 32MB is not supported, ignoring.\n");
+               default:
+                       ret = -ENODEV;
+                       goto notfound;
+               }
+               break;
+
+       default:
+               ret = -ENODEV;
+               goto notfound;
+       }
+       /* Check the TOGGLE bit in the ECC register */
+       tmp  = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT;
+       tmpb = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT;
+       tmpc = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT;
+       if ((tmp == tmpb) || (tmp != tmpc)) {
+               printk(KERN_WARNING "Possible DiskOnChip at 0x%lx failed TOGGLE test, dropping.\n", physadr);
+               ret = -ENODEV;
+               goto notfound;
+       }
+
+       for (mtd = doclist; mtd; mtd = doc->nextdoc) {
+               unsigned char oldval;
+               unsigned char newval;
+               nand = mtd->priv;
+               doc = nand->priv;
+               /* Use the alias resolution register to determine if this is
+                  in fact the same DOC aliased to a new address.  If writes
+                  to one chip's alias resolution register change the value on
+                  the other chip, they're the same chip. */
+               if (ChipID == DOC_ChipID_DocMilPlus16) {
+                       oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution);
+                       newval = ReadDOC(virtadr, Mplus_AliasResolution);
+               } else {
+                       oldval = ReadDOC(doc->virtadr, AliasResolution);
+                       newval = ReadDOC(virtadr, AliasResolution);
+               }
+               if (oldval != newval)
+                       continue;
+               if (ChipID == DOC_ChipID_DocMilPlus16) {
+                       WriteDOC(~newval, virtadr, Mplus_AliasResolution);
+                       oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution);
+                       WriteDOC(newval, virtadr, Mplus_AliasResolution); /* restore it */
+               } else {
+                       WriteDOC(~newval, virtadr, AliasResolution);
+                       oldval = ReadDOC(doc->virtadr, AliasResolution);
+                       WriteDOC(newval, virtadr, AliasResolution); /* restore it */
+               }
+               newval = ~newval;
+               if (oldval == newval) {
+                       printk(KERN_DEBUG "Found alias of DOC at 0x%lx to 0x%lx\n", doc->physadr, physadr);
+                       goto notfound;
+               }
+       }
+
+       printk(KERN_NOTICE "DiskOnChip found at 0x%lx\n", physadr);
+
+       len = sizeof(struct mtd_info) +
+             sizeof(struct nand_chip) +
+             sizeof(struct doc_priv) +
+             (2 * sizeof(struct nand_bbt_descr));
+       mtd =  kmalloc(len, GFP_KERNEL);
+       if (!mtd) {
+               printk(KERN_ERR "DiskOnChip kmalloc (%d bytes) failed!\n", len);
+               ret = -ENOMEM;
+               goto fail;
+       }
+       memset(mtd, 0, len);
+
+       nand                    = (struct nand_chip *) (mtd + 1);
+       doc                     = (struct doc_priv *) (nand + 1);
+       nand->bbt_td            = (struct nand_bbt_descr *) (doc + 1);
+       nand->bbt_md            = nand->bbt_td + 1;
+
+       mtd->priv               = nand;
+       mtd->owner              = THIS_MODULE;
+
+       nand->priv              = doc;
+       nand->select_chip       = doc200x_select_chip;
+       nand->hwcontrol         = doc200x_hwcontrol;
+       nand->dev_ready         = doc200x_dev_ready;
+       nand->waitfunc          = doc200x_wait;
+       nand->block_bad         = doc200x_block_bad;
+       nand->enable_hwecc      = doc200x_enable_hwecc;
+       nand->calculate_ecc     = doc200x_calculate_ecc;
+       nand->correct_data      = doc200x_correct_data;
+
+       nand->autooob           = &doc200x_oobinfo;
+       nand->eccmode           = NAND_ECC_HW6_512;
+       nand->options           = NAND_USE_FLASH_BBT | NAND_HWECC_SYNDROME;
+
+       doc->physadr            = physadr;
+       doc->virtadr            = virtadr;
+       doc->ChipID             = ChipID;
+       doc->curfloor           = -1;
+       doc->curchip            = -1;
+       doc->mh0_page           = -1;
+       doc->mh1_page           = -1;
+       doc->nextdoc            = doclist;
+
+       if (ChipID == DOC_ChipID_Doc2k)
+               numchips = doc2000_init(mtd);
+       else if (ChipID == DOC_ChipID_DocMilPlus16)
+               numchips = doc2001plus_init(mtd);
+       else
+               numchips = doc2001_init(mtd);
+
+       if ((ret = nand_scan(mtd, numchips))) {
+               /* DBB note: i believe nand_release is necessary here, as
+                  buffers may have been allocated in nand_base.  Check with
+                  Thomas. FIX ME! */
+               /* nand_release will call del_mtd_device, but we haven't yet
+                  added it.  This is handled without incident by
+                  del_mtd_device, as far as I can tell. */
+               nand_release(mtd);
+               kfree(mtd);
+               goto fail;
+       }
+
+       /* Success! */
+       doclist = mtd;
+       return 0;
+
+notfound:
+       /* Put back the contents of the DOCControl register, in case it's not
+          actually a DiskOnChip.  */
+       WriteDOC(save_control, virtadr, DOCControl);
+fail:
+       iounmap(virtadr);
+       return ret;
+}
+
+static void release_nanddoc(void)
+{
+       struct mtd_info *mtd, *nextmtd;
+       struct nand_chip *nand;
+       struct doc_priv *doc;
+
+       for (mtd = doclist; mtd; mtd = nextmtd) {
+               nand = mtd->priv;
+               doc = nand->priv;
+
+               nextmtd = doc->nextdoc;
+               nand_release(mtd);
+               iounmap(doc->virtadr);
+               kfree(mtd);
+       }
+}
+
+static int __init init_nanddoc(void)
+{
+       int i, ret = 0;
+
+       /* We could create the decoder on demand, if memory is a concern.
+        * This way we have it handy, if an error happens
+        *
+        * Symbolsize is 10 (bits)
+        * Primitve polynomial is x^10+x^3+1
+        * first consecutive root is 510
+        * primitve element to generate roots = 1
+        * generator polinomial degree = 4
+        */
+       rs_decoder = init_rs(10, 0x409, FCR, 1, NROOTS);
+       if (!rs_decoder) {
+               printk (KERN_ERR "DiskOnChip: Could not create a RS decoder\n");
+               return -ENOMEM;
+       }
+
+       if (doc_config_location) {
+               printk(KERN_INFO "Using configured DiskOnChip probe address 0x%lx\n", doc_config_location);
+               ret = doc_probe(doc_config_location);
+               if (ret < 0)
+                       goto outerr;
+       } else {
+               for (i=0; (doc_locations[i] != 0xffffffff); i++) {
+                       doc_probe(doc_locations[i]);
+               }
+       }
+       /* No banner message any more. Print a message if no DiskOnChip
+          found, so the user knows we at least tried. */
+       if (!doclist) {
+               printk(KERN_INFO "No valid DiskOnChip devices found\n");
+               ret = -ENODEV;
+               goto outerr;
+       }
+       return 0;
+outerr:
+       free_rs(rs_decoder);
+       return ret;
+}
+
+static void __exit cleanup_nanddoc(void)
+{
+       /* Cleanup the nand/DoC resources */
+       release_nanddoc();
+
+       /* Free the reed solomon resources */
+       if (rs_decoder) {
+               free_rs(rs_decoder);
+       }
+}
+
+module_init(init_nanddoc);
+module_exit(cleanup_nanddoc);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
+MODULE_DESCRIPTION("M-Systems DiskOnChip 2000, Millennium and Millennium Plus device driver\n");
+#endif

diff --git a/drivers/nand/nand.c b/drivers/nand/nand.c
new file mode 100644 (file)
index 0000000..e1781fc
--- /dev/null
+++ b/drivers/nand/nand.c
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2005
+ * 2N Telekomunikace, a.s. <www.2n.cz>
+ * Ladislav Michl <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
+
+#include <nand.h>
+
+#ifndef CFG_NAND_BASE_LIST
+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#endif
+
+int nand_curr_device = -1;
+nand_info_t nand_info[CFG_MAX_NAND_DEVICE];
+
+static struct nand_chip nand_chip[CFG_MAX_NAND_DEVICE];
+static ulong base_address[CFG_MAX_NAND_DEVICE] = CFG_NAND_BASE_LIST;
+
+static const char default_nand_name[] = "nand";
+
+extern void board_nand_init(struct nand_chip *nand);
+
+static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand,
+                          ulong base_addr)
+{
+       mtd->priv = nand;
+
+       nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
+       board_nand_init(nand);
+
+       if (nand_scan(mtd, 1) == 0) {
+               if (!mtd->name)
+                       mtd->name = (char *)default_nand_name;
+       } else
+               mtd->name = NULL;
+
+}
+
+void nand_init(void)
+{
+       int i;
+       unsigned int size = 0;
+       for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
+               nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]);
+               size += nand_info[i].size;
+               if (nand_curr_device == -1)
+                       nand_curr_device = i;
+}
+       printf("%lu MiB\n", size / (1024 * 1024));
+}
+
+#endif

diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c
new file mode 100644 (file)
index 0000000..b7a5d32
--- /dev/null
+++ b/drivers/nand/nand_base.c
@@ -0,0 +1,2665 @@
+/*
+ *  drivers/mtd/nand.c
+ *
+ *  Overview:
+ *   This is the generic MTD driver for NAND flash devices. It should be
+ *   capable of working with almost all NAND chips currently available.
+ *   Basic support for AG-AND chips is provided.
+ *
+ *     Additional technical information is available on
+ *     http://www.linux-mtd.infradead.org/tech/nand.html
+ *
+ *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
+ *               2002 Thomas Gleixner (tglx@linutronix.de)
+ *
+ *  02-08-2004  tglx: support for strange chips, which cannot auto increment
+ *             pages on read / read_oob
+ *
+ *  03-17-2004  tglx: Check ready before auto increment check. Simon Bayes
+ *             pointed this out, as he marked an auto increment capable chip
+ *             as NOAUTOINCR in the board driver.
+ *             Make reads over block boundaries work too
+ *
+ *  04-14-2004 tglx: first working version for 2k page size chips
+ *
+ *  05-19-2004  tglx: Basic support for Renesas AG-AND chips
+ *
+ *  09-24-2004  tglx: add support for hardware controllers (e.g. ECC) shared
+ *             among multiple independend devices. Suggestions and initial patch
+ *             from Ben Dooks <ben-mtd@fluff.org>
+ *
+ * Credits:
+ *     David Woodhouse for adding multichip support
+ *
+ *     Aleph One Ltd. and Toby Churchill Ltd. for supporting the
+ *     rework for 2K page size chips
+ *
+ * TODO:
+ *     Enable cached programming for 2k page size chips
+ *     Check, if mtd->ecctype should be set to MTD_ECC_HW
+ *     if we have HW ecc support.
+ *     The AG-AND chips have nice features for speed improvement,
+ *     which are not supported yet. Read / program 4 pages in one go.
+ *
+ * $Id: nand_base.c,v 1.126 2004/12/13 11:22:25 lavinen Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/* XXX U-BOOT XXX */
+#if 0
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/compatmac.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_MTD_PARTITIONS
+#include <linux/mtd/partitions.h>
+#endif
+
+#endif
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
+
+#include <malloc.h>
+#include <watchdog.h>
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+
+#include <asm/io.h>
+#include <asm/errno.h>
+
+#ifdef CONFIG_JFFS2_NAND
+#include <jffs2/jffs2.h>
+#endif
+
+/* Define default oob placement schemes for large and small page devices */
+static struct nand_oobinfo nand_oob_8 = {
+       .useecc = MTD_NANDECC_AUTOPLACE,
+       .eccbytes = 3,
+       .eccpos = {0, 1, 2},
+       .oobfree = { {3, 2}, {6, 2} }
+};
+
+static struct nand_oobinfo nand_oob_16 = {
+       .useecc = MTD_NANDECC_AUTOPLACE,
+       .eccbytes = 6,
+       .eccpos = {0, 1, 2, 3, 6, 7},
+       .oobfree = { {8, 8} }
+};
+
+static struct nand_oobinfo nand_oob_64 = {
+       .useecc = MTD_NANDECC_AUTOPLACE,
+       .eccbytes = 24,
+       .eccpos = {
+               40, 41, 42, 43, 44, 45, 46, 47,
+               48, 49, 50, 51, 52, 53, 54, 55,
+               56, 57, 58, 59, 60, 61, 62, 63},
+       .oobfree = { {2, 38} }
+};
+
+/* This is used for padding purposes in nand_write_oob */
+static u_char ffchars[] = {
+       0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+       0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+       0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+       0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+       0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+       0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+       0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+       0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+
+/*
+ * NAND low-level MTD interface functions
+ */
+static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
+static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
+static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
+
+static int nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf);
+static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
+                         size_t * retlen, u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel);
+static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf);
+static int nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf);
+static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
+                          size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel);
+static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char *buf);
+/* XXX U-BOOT XXX */
+#if 0
+static int nand_writev (struct mtd_info *mtd, const struct kvec *vecs,
+                       unsigned long count, loff_t to, size_t * retlen);
+static int nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs,
+                       unsigned long count, loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel);
+#endif
+static int nand_erase (struct mtd_info *mtd, struct erase_info *instr);
+static void nand_sync (struct mtd_info *mtd);
+
+/* Some internal functions */
+static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, u_char *oob_buf,
+               struct nand_oobinfo *oobsel, int mode);
+#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
+static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int page, int numpages,
+       u_char *oob_buf, struct nand_oobinfo *oobsel, int chipnr, int oobmode);
+#else
+#define nand_verify_pages(...) (0)
+#endif
+
+static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state);
+
+/**
+ * nand_release_device - [GENERIC] release chip
+ * @mtd:       MTD device structure
+ *
+ * Deselect, release chip lock and wake up anyone waiting on the device
+ */
+/* XXX U-BOOT XXX */
+#if 0
+static void nand_release_device (struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+
+       /* De-select the NAND device */
+       this->select_chip(mtd, -1);
+       /* Do we have a hardware controller ? */
+       if (this->controller) {
+               spin_lock(&this->controller->lock);
+               this->controller->active = NULL;
+               spin_unlock(&this->controller->lock);
+       }
+       /* Release the chip */
+       spin_lock (&this->chip_lock);
+       this->state = FL_READY;
+       wake_up (&this->wq);
+       spin_unlock (&this->chip_lock);
+}
+#else
+static void nand_release_device (struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+       this->select_chip(mtd, -1);     /* De-select the NAND device */
+}
+#endif
+
+/**
+ * nand_read_byte - [DEFAULT] read one byte from the chip
+ * @mtd:       MTD device structure
+ *
+ * Default read function for 8bit buswith
+ */
+static u_char nand_read_byte(struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+       return readb(this->IO_ADDR_R);
+}
+
+/**
+ * nand_write_byte - [DEFAULT] write one byte to the chip
+ * @mtd:       MTD device structure
+ * @byte:      pointer to data byte to write
+ *
+ * Default write function for 8it buswith
+ */
+static void nand_write_byte(struct mtd_info *mtd, u_char byte)
+{
+       struct nand_chip *this = mtd->priv;
+       writeb(byte, this->IO_ADDR_W);
+}
+
+/**
+ * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
+ * @mtd:       MTD device structure
+ *
+ * Default read function for 16bit buswith with
+ * endianess conversion
+ */
+static u_char nand_read_byte16(struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+       return (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
+}
+
+/**
+ * nand_write_byte16 - [DEFAULT] write one byte endianess aware to the chip
+ * @mtd:       MTD device structure
+ * @byte:      pointer to data byte to write
+ *
+ * Default write function for 16bit buswith with
+ * endianess conversion
+ */
+static void nand_write_byte16(struct mtd_info *mtd, u_char byte)
+{
+       struct nand_chip *this = mtd->priv;
+       writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
+}
+
+/**
+ * nand_read_word - [DEFAULT] read one word from the chip
+ * @mtd:       MTD device structure
+ *
+ * Default read function for 16bit buswith without
+ * endianess conversion
+ */
+static u16 nand_read_word(struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+       return readw(this->IO_ADDR_R);
+}
+
+/**
+ * nand_write_word - [DEFAULT] write one word to the chip
+ * @mtd:       MTD device structure
+ * @word:      data word to write
+ *
+ * Default write function for 16bit buswith without
+ * endianess conversion
+ */
+static void nand_write_word(struct mtd_info *mtd, u16 word)
+{
+       struct nand_chip *this = mtd->priv;
+       writew(word, this->IO_ADDR_W);
+}
+
+/**
+ * nand_select_chip - [DEFAULT] control CE line
+ * @mtd:       MTD device structure
+ * @chip:      chipnumber to select, -1 for deselect
+ *
+ * Default select function for 1 chip devices.
+ */
+static void nand_select_chip(struct mtd_info *mtd, int chip)
+{
+       struct nand_chip *this = mtd->priv;
+       switch(chip) {
+       case -1:
+               this->hwcontrol(mtd, NAND_CTL_CLRNCE);
+               break;
+       case 0:
+               this->hwcontrol(mtd, NAND_CTL_SETNCE);
+               break;
+
+       default:
+               BUG();
+       }
+}
+
+/**
+ * nand_write_buf - [DEFAULT] write buffer to chip
+ * @mtd:       MTD device structure
+ * @buf:       data buffer
+ * @len:       number of bytes to write
+ *
+ * Default write function for 8bit buswith
+ */
+static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+       int i;
+       struct nand_chip *this = mtd->priv;
+
+       for (i=0; i<len; i++)
+               writeb(buf[i], this->IO_ADDR_W);
+}
+
+/**
+ * nand_read_buf - [DEFAULT] read chip data into buffer
+ * @mtd:       MTD device structure
+ * @buf:       buffer to store date
+ * @len:       number of bytes to read
+ *
+ * Default read function for 8bit buswith
+ */
+static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+       int i;
+       struct nand_chip *this = mtd->priv;
+
+       for (i=0; i<len; i++)
+               buf[i] = readb(this->IO_ADDR_R);
+}
+
+/**
+ * nand_verify_buf - [DEFAULT] Verify chip data against buffer
+ * @mtd:       MTD device structure
+ * @buf:       buffer containing the data to compare
+ * @len:       number of bytes to compare
+ *
+ * Default verify function for 8bit buswith
+ */
+static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+       int i;
+       struct nand_chip *this = mtd->priv;
+
+       for (i=0; i<len; i++)
+               if (buf[i] != readb(this->IO_ADDR_R))
+                       return -EFAULT;
+
+       return 0;
+}
+
+/**
+ * nand_write_buf16 - [DEFAULT] write buffer to chip
+ * @mtd:       MTD device structure
+ * @buf:       data buffer
+ * @len:       number of bytes to write
+ *
+ * Default write function for 16bit buswith
+ */
+static void nand_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
+{
+       int i;
+       struct nand_chip *this = mtd->priv;
+       u16 *p = (u16 *) buf;
+       len >>= 1;
+
+       for (i=0; i<len; i++)
+               writew(p[i], this->IO_ADDR_W);
+
+}
+
+/**
+ * nand_read_buf16 - [DEFAULT] read chip data into buffer
+ * @mtd:       MTD device structure
+ * @buf:       buffer to store date
+ * @len:       number of bytes to read
+ *
+ * Default read function for 16bit buswith
+ */
+static void nand_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
+{
+       int i;
+       struct nand_chip *this = mtd->priv;
+       u16 *p = (u16 *) buf;
+       len >>= 1;
+
+       for (i=0; i<len; i++)
+               p[i] = readw(this->IO_ADDR_R);
+}
+
+/**
+ * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
+ * @mtd:       MTD device structure
+ * @buf:       buffer containing the data to compare
+ * @len:       number of bytes to compare
+ *
+ * Default verify function for 16bit buswith
+ */
+static int nand_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
+{
+       int i;
+       struct nand_chip *this = mtd->priv;
+       u16 *p = (u16 *) buf;
+       len >>= 1;
+
+       for (i=0; i<len; i++)
+               if (p[i] != readw(this->IO_ADDR_R))
+                       return -EFAULT;
+
+       return 0;
+}
+
+/**
+ * nand_block_bad - [DEFAULT] Read bad block marker from the chip
+ * @mtd:       MTD device structure
+ * @ofs:       offset from device start
+ * @getchip:   0, if the chip is already selected
+ *
+ * Check, if the block is bad.
+ */
+static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+{
+       int page, chipnr, res = 0;
+       struct nand_chip *this = mtd->priv;
+       u16 bad;
+
+       if (getchip) {
+               page = (int)(ofs >> this->page_shift);
+               chipnr = (int)(ofs >> this->chip_shift);
+
+               /* Grab the lock and see if the device is available */
+               nand_get_device (this, mtd, FL_READING);
+
+               /* Select the NAND device */
+               this->select_chip(mtd, chipnr);
+       } else
+               page = (int) ofs;
+
+       if (this->options & NAND_BUSWIDTH_16) {
+               this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos & 0xFE, page & this->pagemask);
+               bad = cpu_to_le16(this->read_word(mtd));
+               if (this->badblockpos & 0x1)
+                       bad >>= 1;
+               if ((bad & 0xFF) != 0xff)
+                       res = 1;
+       } else {
+               this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos, page & this->pagemask);
+               if (this->read_byte(mtd) != 0xff)
+                       res = 1;
+       }
+
+       if (getchip) {
+               /* Deselect and wake up anyone waiting on the device */
+               nand_release_device(mtd);
+       }
+
+       return res;
+}
+
+/**
+ * nand_default_block_markbad - [DEFAULT] mark a block bad
+ * @mtd:       MTD device structure
+ * @ofs:       offset from device start
+ *
+ * This is the default implementation, which can be overridden by
+ * a hardware specific driver.
+*/
+static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+       struct nand_chip *this = mtd->priv;
+       u_char buf[2] = {0, 0};
+       size_t  retlen;
+       int block;
+
+       /* Get block number */
+       block = ((int) ofs) >> this->bbt_erase_shift;
+       this->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
+
+       /* Do we have a flash based bad block table ? */
+       if (this->options & NAND_USE_FLASH_BBT)
+               return nand_update_bbt (mtd, ofs);
+
+       /* We write two bytes, so we dont have to mess with 16 bit access */
+       ofs += mtd->oobsize + (this->badblockpos & ~0x01);
+       return nand_write_oob (mtd, ofs , 2, &retlen, buf);
+}
+
+/**
+ * nand_check_wp - [GENERIC] check if the chip is write protected
+ * @mtd:       MTD device structure
+ * Check, if the device is write protected
+ *
+ * The function expects, that the device is already selected
+ */
+static int nand_check_wp (struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+       /* Check the WP bit */
+       this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1);
+       return (this->read_byte(mtd) & 0x80) ? 0 : 1;
+}
+
+/**
+ * nand_block_checkbad - [GENERIC] Check if a block is marked bad
+ * @mtd:       MTD device structure
+ * @ofs:       offset from device start
+ * @getchip:   0, if the chip is already selected
+ * @allowbbt:  1, if its allowed to access the bbt area
+ *
+ * Check, if the block is bad. Either by reading the bad block table or
+ * calling of the scan function.
+ */
+static int nand_block_checkbad (struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt)
+{
+       struct nand_chip *this = mtd->priv;
+
+       if (!this->bbt)
+               return this->block_bad(mtd, ofs, getchip);
+
+       /* Return info from the table */
+       return nand_isbad_bbt (mtd, ofs, allowbbt);
+}
+
+/**
+ * nand_command - [DEFAULT] Send command to NAND device
+ * @mtd:       MTD device structure
+ * @command:   the command to be sent
+ * @column:    the column address for this command, -1 if none
+ * @page_addr: the page address for this command, -1 if none
+ *
+ * Send command to NAND device. This function is used for small page
+ * devices (256/512 Bytes per page)
+ */
+static void nand_command (struct mtd_info *mtd, unsigned command, int column, int page_addr)
+{
+       register struct nand_chip *this = mtd->priv;
+
+       /* Begin command latch cycle */
+       this->hwcontrol(mtd, NAND_CTL_SETCLE);
+       /*
+        * Write out the command to the device.
+        */
+       if (command == NAND_CMD_SEQIN) {
+               int readcmd;
+
+               if (column >= mtd->oobblock) {
+                       /* OOB area */
+                       column -= mtd->oobblock;
+                       readcmd = NAND_CMD_READOOB;
+               } else if (column < 256) {
+                       /* First 256 bytes --> READ0 */
+                       readcmd = NAND_CMD_READ0;
+               } else {
+                       column -= 256;
+                       readcmd = NAND_CMD_READ1;
+               }
+               this->write_byte(mtd, readcmd);
+       }
+       this->write_byte(mtd, command);
+
+       /* Set ALE and clear CLE to start address cycle */
+       this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+
+       if (column != -1 || page_addr != -1) {
+               this->hwcontrol(mtd, NAND_CTL_SETALE);
+
+               /* Serially input address */
+               if (column != -1) {
+                       /* Adjust columns for 16 bit buswidth */
+                       if (this->options & NAND_BUSWIDTH_16)
+                               column >>= 1;
+                       this->write_byte(mtd, column);
+               }
+               if (page_addr != -1) {
+                       this->write_byte(mtd, (unsigned char) (page_addr & 0xff));
+                       this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff));
+                       /* One more address cycle for devices > 32MiB */
+                       if (this->chipsize > (32 << 20))
+                               this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0x0f));
+               }
+               /* Latch in address */
+               this->hwcontrol(mtd, NAND_CTL_CLRALE);
+       }
+
+       /*
+        * program and erase have their own busy handlers
+        * status and sequential in needs no delay
+       */
+       switch (command) {
+
+       case NAND_CMD_PAGEPROG:
+       case NAND_CMD_ERASE1:
+       case NAND_CMD_ERASE2:
+       case NAND_CMD_SEQIN:
+       case NAND_CMD_STATUS:
+               return;
+
+       case NAND_CMD_RESET:
+               if (this->dev_ready)
+                       break;
+               udelay(this->chip_delay);
+               this->hwcontrol(mtd, NAND_CTL_SETCLE);
+               this->write_byte(mtd, NAND_CMD_STATUS);
+               this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+               while ( !(this->read_byte(mtd) & 0x40));
+               return;
+
+       /* This applies to read commands */
+       default:
+               /*
+                * If we don't have access to the busy pin, we apply the given
+                * command delay
+               */
+               if (!this->dev_ready) {
+                       udelay (this->chip_delay);
+                       return;
+               }
+       }
+
+       /* Apply this short delay always to ensure that we do wait tWB in
+        * any case on any machine. */
+       ndelay (100);
+       /* wait until command is processed */
+       while (!this->dev_ready(mtd));
+}
+
+/**
+ * nand_command_lp - [DEFAULT] Send command to NAND large page device
+ * @mtd:       MTD device structure
+ * @command:   the command to be sent
+ * @column:    the column address for this command, -1 if none
+ * @page_addr: the page address for this command, -1 if none
+ *
+ * Send command to NAND device. This is the version for the new large page devices
+ * We dont have the seperate regions as we have in the small page devices.
+ * We must emulate NAND_CMD_READOOB to keep the code compatible.
+ *
+ */
+static void nand_command_lp (struct mtd_info *mtd, unsigned command, int column, int page_addr)
+{
+       register struct nand_chip *this = mtd->priv;
+
+       /* Emulate NAND_CMD_READOOB */
+       if (command == NAND_CMD_READOOB) {
+               column += mtd->oobblock;
+               command = NAND_CMD_READ0;
+       }
+
+
+       /* Begin command latch cycle */
+       this->hwcontrol(mtd, NAND_CTL_SETCLE);
+       /* Write out the command to the device. */
+       this->write_byte(mtd, command);
+       /* End command latch cycle */
+       this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+
+       if (column != -1 || page_addr != -1) {
+               this->hwcontrol(mtd, NAND_CTL_SETALE);
+
+               /* Serially input address */
+               if (column != -1) {
+                       /* Adjust columns for 16 bit buswidth */
+                       if (this->options & NAND_BUSWIDTH_16)
+                               column >>= 1;
+                       this->write_byte(mtd, column & 0xff);
+                       this->write_byte(mtd, column >> 8);
+               }
+               if (page_addr != -1) {
+                       this->write_byte(mtd, (unsigned char) (page_addr & 0xff));
+                       this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff));
+                       /* One more address cycle for devices > 128MiB */
+                       if (this->chipsize > (128 << 20))
+                               this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0xff));
+               }
+               /* Latch in address */
+               this->hwcontrol(mtd, NAND_CTL_CLRALE);
+       }
+
+       /*
+        * program and erase have their own busy handlers
+        * status and sequential in needs no delay
+       */
+       switch (command) {
+
+       case NAND_CMD_CACHEDPROG:
+       case NAND_CMD_PAGEPROG:
+       case NAND_CMD_ERASE1:
+       case NAND_CMD_ERASE2:
+       case NAND_CMD_SEQIN:
+       case NAND_CMD_STATUS:
+               return;
+
+
+       case NAND_CMD_RESET:
+               if (this->dev_ready)
+                       break;
+               udelay(this->chip_delay);
+               this->hwcontrol(mtd, NAND_CTL_SETCLE);
+               this->write_byte(mtd, NAND_CMD_STATUS);
+               this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+               while ( !(this->read_byte(mtd) & 0x40));
+               return;
+
+       case NAND_CMD_READ0:
+               /* Begin command latch cycle */
+               this->hwcontrol(mtd, NAND_CTL_SETCLE);
+               /* Write out the start read command */
+               this->write_byte(mtd, NAND_CMD_READSTART);
+               /* End command latch cycle */
+               this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+               /* Fall through into ready check */
+
+       /* This applies to read commands */
+       default:
+               /*
+                * If we don't have access to the busy pin, we apply the given
+                * command delay
+               */
+               if (!this->dev_ready) {
+                       udelay (this->chip_delay);
+                       return;
+               }
+       }
+
+       /* Apply this short delay always to ensure that we do wait tWB in
+        * any case on any machine. */
+       ndelay (100);
+       /* wait until command is processed */
+       while (!this->dev_ready(mtd));
+}
+
+/**
+ * nand_get_device - [GENERIC] Get chip for selected access
+ * @this:      the nand chip descriptor
+ * @mtd:       MTD device structure
+ * @new_state: the state which is requested
+ *
+ * Get the device and lock it for exclusive access
+ */
+/* XXX U-BOOT XXX */
+#if 0
+static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
+{
+       struct nand_chip *active = this;
+
+       DECLARE_WAITQUEUE (wait, current);
+
+       /*
+        * Grab the lock and see if the device is available
+       */
+retry:
+       /* Hardware controller shared among independend devices */
+       if (this->controller) {
+               spin_lock (&this->controller->lock);
+               if (this->controller->active)
+                       active = this->controller->active;
+               else
+                       this->controller->active = this;
+               spin_unlock (&this->controller->lock);
+       }
+
+       if (active == this) {
+               spin_lock (&this->chip_lock);
+               if (this->state == FL_READY) {
+                       this->state = new_state;
+                       spin_unlock (&this->chip_lock);
+                       return;
+               }
+       }
+       set_current_state (TASK_UNINTERRUPTIBLE);
+       add_wait_queue (&active->wq, &wait);
+       spin_unlock (&active->chip_lock);
+       schedule ();
+       remove_wait_queue (&active->wq, &wait);
+       goto retry;
+}
+#else
+static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state) {}
+#endif
+
+/**
+ * nand_wait - [DEFAULT]  wait until the command is done
+ * @mtd:       MTD device structure
+ * @this:      NAND chip structure
+ * @state:     state to select the max. timeout value
+ *
+ * Wait for command done. This applies to erase and program only
+ * Erase can take up to 400ms and program up to 20ms according to
+ * general NAND and SmartMedia specs
+ *
+*/
+/* XXX U-BOOT XXX */
+#if 0
+static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
+{
+       unsigned long   timeo = jiffies;
+       int     status;
+
+       if (state == FL_ERASING)
+                timeo += (HZ * 400) / 1000;
+       else
+                timeo += (HZ * 20) / 1000;
+
+       /* Apply this short delay always to ensure that we do wait tWB in
+        * any case on any machine. */
+       ndelay (100);
+
+       if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
+               this->cmdfunc (mtd, NAND_CMD_STATUS_MULTI, -1, -1);
+       else
+               this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1);
+
+       while (time_before(jiffies, timeo)) {
+               /* Check, if we were interrupted */
+               if (this->state != state)
+                       return 0;
+
+               if (this->dev_ready) {
+                       if (this->dev_ready(mtd))
+                               break;
+               } else {
+                       if (this->read_byte(mtd) & NAND_STATUS_READY)
+                               break;
+               }
+               yield ();
+       }
+       status = (int) this->read_byte(mtd);
+       return status;
+
+       return 0;
+}
+#else
+static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
+{
+       unsigned long   timeo;
+
+       if (state == FL_ERASING)
+               timeo = CFG_HZ * 400;
+       else
+               timeo = CFG_HZ * 20;
+
+       if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
+               this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
+       else
+               this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+
+       reset_timer();
+
+       while (1) {
+               if (get_timer(0) > timeo) {
+                       printf("Timeout!");
+                       return 0;
+                       }
+
+               if (this->dev_ready) {
+                       if (this->dev_ready(mtd))
+                               break;
+               } else {
+                       if (this->read_byte(mtd) & NAND_STATUS_READY)
+                               break;
+               }
+       }
+#ifdef PPCHAMELON_NAND_TIMER_HACK
+       reset_timer();
+       while (get_timer(0) < 10);
+#endif /*  PPCHAMELON_NAND_TIMER_HACK */
+
+       return this->read_byte(mtd);
+}
+#endif
+
+/**
+ * nand_write_page - [GENERIC] write one page
+ * @mtd:       MTD device structure
+ * @this:      NAND chip structure
+ * @page:      startpage inside the chip, must be called with (page & this->pagemask)
+ * @oob_buf:   out of band data buffer
+ * @oobsel:    out of band selecttion structre
+ * @cached:    1 = enable cached programming if supported by chip
+ *
+ * Nand_page_program function is used for write and writev !
+ * This function will always program a full page of data
+ * If you call it with a non page aligned buffer, you're lost :)
+ *
+ * Cached programming is not supported yet.
+ */
+static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page,
+       u_char *oob_buf,  struct nand_oobinfo *oobsel, int cached)
+{
+       int     i, status;
+       u_char  ecc_code[32];
+       int     eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
+       uint    *oob_config = oobsel->eccpos;
+       int     datidx = 0, eccidx = 0, eccsteps = this->eccsteps;
+       int     eccbytes = 0;
+
+       /* FIXME: Enable cached programming */
+       cached = 0;
+
+       /* Send command to begin auto page programming */
+       this->cmdfunc (mtd, NAND_CMD_SEQIN, 0x00, page);
+
+       /* Write out complete page of data, take care of eccmode */
+       switch (eccmode) {
+       /* No ecc, write all */
+       case NAND_ECC_NONE:
+               printk (KERN_WARNING "Writing data without ECC to NAND-FLASH is not recommended\n");
+               this->write_buf(mtd, this->data_poi, mtd->oobblock);
+               break;
+
+       /* Software ecc 3/256, write all */
+       case NAND_ECC_SOFT:
+               for (; eccsteps; eccsteps--) {
+                       this->calculate_ecc(mtd, &this->data_poi[datidx], ecc_code);
+                       for (i = 0; i < 3; i++, eccidx++)
+                               oob_buf[oob_config[eccidx]] = ecc_code[i];
+                       datidx += this->eccsize;
+               }
+               this->write_buf(mtd, this->data_poi, mtd->oobblock);
+               break;
+       default:
+               eccbytes = this->eccbytes;
+               for (; eccsteps; eccsteps--) {
+                       /* enable hardware ecc logic for write */
+                       this->enable_hwecc(mtd, NAND_ECC_WRITE);
+                       this->write_buf(mtd, &this->data_poi[datidx], this->eccsize);
+                       this->calculate_ecc(mtd, &this->data_poi[datidx], ecc_code);
+                       for (i = 0; i < eccbytes; i++, eccidx++)
+                               oob_buf[oob_config[eccidx]] = ecc_code[i];
+                       /* If the hardware ecc provides syndromes then
+                        * the ecc code must be written immidiately after
+                        * the data bytes (words) */
+                       if (this->options & NAND_HWECC_SYNDROME)
+                               this->write_buf(mtd, ecc_code, eccbytes);
+                       datidx += this->eccsize;
+               }
+               break;
+       }
+
+       /* Write out OOB data */
+       if (this->options & NAND_HWECC_SYNDROME)
+               this->write_buf(mtd, &oob_buf[oobsel->eccbytes], mtd->oobsize - oobsel->eccbytes);
+       else
+               this->write_buf(mtd, oob_buf, mtd->oobsize);
+
+       /* Send command to actually program the data */
+       this->cmdfunc (mtd, cached ? NAND_CMD_CACHEDPROG : NAND_CMD_PAGEPROG, -1, -1);
+
+       if (!cached) {
+               /* call wait ready function */
+               status = this->waitfunc (mtd, this, FL_WRITING);
+               /* See if device thinks it succeeded */
+               if (status & 0x01) {
+                       DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write, page 0x%08x, ", __FUNCTION__, page);
+                       return -EIO;
+               }
+       } else {
+               /* FIXME: Implement cached programming ! */
+               /* wait until cache is ready*/
+               /* status = this->waitfunc (mtd, this, FL_CACHEDRPG); */
+       }
+       return 0;
+}
+
+#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
+/**
+ * nand_verify_pages - [GENERIC] verify the chip contents after a write
+ * @mtd:       MTD device structure
+ * @this:      NAND chip structure
+ * @page:      startpage inside the chip, must be called with (page & this->pagemask)
+ * @numpages:  number of pages to verify
+ * @oob_buf:   out of band data buffer
+ * @oobsel:    out of band selecttion structre
+ * @chipnr:    number of the current chip
+ * @oobmode:   1 = full buffer verify, 0 = ecc only
+ *
+ * The NAND device assumes that it is always writing to a cleanly erased page.
+ * Hence, it performs its internal write verification only on bits that
+ * transitioned from 1 to 0. The device does NOT verify the whole page on a
+ * byte by byte basis. It is possible that the page was not completely erased
+ * or the page is becoming unusable due to wear. The read with ECC would catch
+ * the error later when the ECC page check fails, but we would rather catch
+ * it early in the page write stage. Better to write no data than invalid data.
+ */
+static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int page, int numpages,
+       u_char *oob_buf, struct nand_oobinfo *oobsel, int chipnr, int oobmode)
+{
+       int     i, j, datidx = 0, oobofs = 0, res = -EIO;
+       int     eccsteps = this->eccsteps;
+       int     hweccbytes;
+       u_char  oobdata[64];
+
+       hweccbytes = (this->options & NAND_HWECC_SYNDROME) ? (oobsel->eccbytes / eccsteps) : 0;
+
+       /* Send command to read back the first page */
+       this->cmdfunc (mtd, NAND_CMD_READ0, 0, page);
+
+       for(;;) {
+               for (j = 0; j < eccsteps; j++) {
+                       /* Loop through and verify the data */
+                       if (this->verify_buf(mtd, &this->data_poi[datidx], mtd->eccsize)) {
+                               DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
+                               goto out;
+                       }
+                       datidx += mtd->eccsize;
+                       /* Have we a hw generator layout ? */
+                       if (!hweccbytes)
+                               continue;
+                       if (this->verify_buf(mtd, &this->oob_buf[oobofs], hweccbytes)) {
+                               DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
+                               goto out;
+                       }
+                       oobofs += hweccbytes;
+               }
+
+               /* check, if we must compare all data or if we just have to
+                * compare the ecc bytes
+                */
+               if (oobmode) {
+                       if (this->verify_buf(mtd, &oob_buf[oobofs], mtd->oobsize - hweccbytes * eccsteps)) {
+                               DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
+                               goto out;
+                       }
+               } else {
+                       /* Read always, else autoincrement fails */
+                       this->read_buf(mtd, oobdata, mtd->oobsize - hweccbytes * eccsteps);
+
+                       if (oobsel->useecc != MTD_NANDECC_OFF && !hweccbytes) {
+                               int ecccnt = oobsel->eccbytes;
+
+                               for (i = 0; i < ecccnt; i++) {
+                                       int idx = oobsel->eccpos[i];
+                                       if (oobdata[idx] != oob_buf[oobofs + idx] ) {
+                                               DEBUG (MTD_DEBUG_LEVEL0,
+                                               "%s: Failed ECC write "
+                                               "verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i);
+                                               goto out;
+                                       }
+                               }
+                       }
+               }
+               oobofs += mtd->oobsize - hweccbytes * eccsteps;
+               page++;
+               numpages--;
+
+               /* Apply delay or wait for ready/busy pin
+                * Do this before the AUTOINCR check, so no problems
+                * arise if a chip which does auto increment
+                * is marked as NOAUTOINCR by the board driver.
+                * Do this also before returning, so the chip is
+                * ready for the next command.
+               */
+               if (!this->dev_ready)
+                       udelay (this->chip_delay);
+               else
+                       while (!this->dev_ready(mtd));
+
+               /* All done, return happy */
+               if (!numpages)
+                       return 0;
+
+
+               /* Check, if the chip supports auto page increment */
+               if (!NAND_CANAUTOINCR(this))
+                       this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page);
+       }
+       /*
+        * Terminate the read command. We come here in case of an error
+        * So we must issue a reset command.
+        */
+out:
+       this->cmdfunc (mtd, NAND_CMD_RESET, -1, -1);
+       return res;
+}
+#endif
+
+/**
+ * nand_read - [MTD Interface] MTD compability function for nand_read_ecc
+ * @mtd:       MTD device structure
+ * @from:      offset to read from
+ * @len:       number of bytes to read
+ * @retlen:    pointer to variable to store the number of read bytes
+ * @buf:       the databuffer to put data
+ *
+ * This function simply calls nand_read_ecc with oob buffer and oobsel = NULL
+*/
+static int nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf)
+{
+       return nand_read_ecc (mtd, from, len, retlen, buf, NULL, NULL);
+}
+
+
+/**
+ * nand_read_ecc - [MTD Interface] Read data with ECC
+ * @mtd:       MTD device structure
+ * @from:      offset to read from
+ * @len:       number of bytes to read
+ * @retlen:    pointer to variable to store the number of read bytes
+ * @buf:       the databuffer to put data
+ * @oob_buf:   filesystem supplied oob data buffer
+ * @oobsel:    oob selection structure
+ *
+ * NAND read with ECC
+ */
+static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
+                         size_t * retlen, u_char * buf, u_char * oob_buf, struct nand_oobinfo *oobsel)
+{
+       int i, j, col, realpage, page, end, ecc, chipnr, sndcmd = 1;
+       int read = 0, oob = 0, ecc_status = 0, ecc_failed = 0;
+       struct nand_chip *this = mtd->priv;
+       u_char *data_poi, *oob_data = oob_buf;
+       u_char ecc_calc[32];
+       u_char ecc_code[32];
+       int eccmode, eccsteps;
+       unsigned *oob_config;
+       int     datidx;
+       int     blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1;
+       int     eccbytes;
+       int     compareecc = 1;
+       int     oobreadlen;
+
+
+       DEBUG (MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
+
+       /* Do not allow reads past end of device */
+       if ((from + len) > mtd->size) {
+               DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: Attempt read beyond end of device\n");
+               *retlen = 0;
+               return -EINVAL;
+       }
+
+       /* Grab the lock and see if the device is available */
+       nand_get_device (this, mtd ,FL_READING);
+
+       /* use userspace supplied oobinfo, if zero */
+       if (oobsel == NULL)
+               oobsel = &mtd->oobinfo;
+
+       /* Autoplace of oob data ? Use the default placement scheme */
+       if (oobsel->useecc == MTD_NANDECC_AUTOPLACE)
+               oobsel = this->autooob;
+
+       eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
+       oob_config = oobsel->eccpos;
+
+       /* Select the NAND device */
+       chipnr = (int)(from >> this->chip_shift);
+       this->select_chip(mtd, chipnr);
+
+       /* First we calculate the starting page */
+       realpage = (int) (from >> this->page_shift);
+       page = realpage & this->pagemask;
+
+       /* Get raw starting column */
+       col = from & (mtd->oobblock - 1);
+
+       end = mtd->oobblock;
+       ecc = this->eccsize;
+       eccbytes = this->eccbytes;
+
+       if ((eccmode == NAND_ECC_NONE) || (this->options & NAND_HWECC_SYNDROME))
+               compareecc = 0;
+
+       oobreadlen = mtd->oobsize;
+       if (this->options & NAND_HWECC_SYNDROME)
+               oobreadlen -= oobsel->eccbytes;
+
+       /* Loop until all data read */
+       while (read < len) {
+
+               int aligned = (!col && (len - read) >= end);
+               /*
+                * If the read is not page aligned, we have to read into data buffer
+                * due to ecc, else we read into return buffer direct
+                */
+               if (aligned)
+                       data_poi = &buf[read];
+               else
+                       data_poi = this->data_buf;
+
+               /* Check, if we have this page in the buffer
+                *
+                * FIXME: Make it work when we must provide oob data too,
+                * check the usage of data_buf oob field
+                */
+               if (realpage == this->pagebuf && !oob_buf) {
+                       /* aligned read ? */
+                       if (aligned)
+                               memcpy (data_poi, this->data_buf, end);
+                       goto readdata;
+               }
+
+               /* Check, if we must send the read command */
+               if (sndcmd) {
+                       this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page);
+                       sndcmd = 0;
+               }
+
+               /* get oob area, if we have no oob buffer from fs-driver */
+               if (!oob_buf || oobsel->useecc == MTD_NANDECC_AUTOPLACE ||
+                       oobsel->useecc == MTD_NANDECC_AUTOPL_USR)
+                       oob_data = &this->data_buf[end];
+
+               eccsteps = this->eccsteps;
+
+               switch (eccmode) {
+               case NAND_ECC_NONE: {   /* No ECC, Read in a page */
+/* XXX U-BOOT XXX */
+#if 0
+                       static unsigned long lastwhinge = 0;
+                       if ((lastwhinge / HZ) != (jiffies / HZ)) {
+                               printk (KERN_WARNING "Reading data from NAND FLASH without ECC is not recommended\n");
+                               lastwhinge = jiffies;
+                       }
+#else
+                       puts("Reading data from NAND FLASH without ECC is not recommended\n");
+#endif
+                       this->read_buf(mtd, data_poi, end);
+                       break;
+               }
+
+               case NAND_ECC_SOFT:     /* Software ECC 3/256: Read in a page + oob data */
+                       this->read_buf(mtd, data_poi, end);
+                       for (i = 0, datidx = 0; eccsteps; eccsteps--, i+=3, datidx += ecc)
+                               this->calculate_ecc(mtd, &data_poi[datidx], &ecc_calc[i]);
+                       break;
+
+               default:
+                       for (i = 0, datidx = 0; eccsteps; eccsteps--, i+=eccbytes, datidx += ecc) {
+                               this->enable_hwecc(mtd, NAND_ECC_READ);
+                               this->read_buf(mtd, &data_poi[datidx], ecc);
+
+                               /* HW ecc with syndrome calculation must read the
+                                * syndrome from flash immidiately after the data */
+                               if (!compareecc) {
+                                       /* Some hw ecc generators need to know when the
+                                        * syndrome is read from flash */
+                                       this->enable_hwecc(mtd, NAND_ECC_READSYN);
+                                       this->read_buf(mtd, &oob_data[i], eccbytes);
+                                       /* We calc error correction directly, it checks the hw
+                                        * generator for an error, reads back the syndrome and
+                                        * does the error correction on the fly */
+                                       if (this->correct_data(mtd, &data_poi[datidx], &oob_data[i], &ecc_code[i]) == -1) {
+                                               DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: "
+                                                       "Failed ECC read, page 0x%08x on chip %d\n", page, chipnr);
+                                               ecc_failed++;
+                                       }
+                               } else {
+                                       this->calculate_ecc(mtd, &data_poi[datidx], &ecc_calc[i]);
+                               }
+                       }
+                       break;
+               }
+
+               /* read oobdata */
+               this->read_buf(mtd, &oob_data[mtd->oobsize - oobreadlen], oobreadlen);
+
+               /* Skip ECC check, if not requested (ECC_NONE or HW_ECC with syndromes) */
+               if (!compareecc)
+                       goto readoob;
+
+               /* Pick the ECC bytes out of the oob data */
+               for (j = 0; j < oobsel->eccbytes; j++)
+                       ecc_code[j] = oob_data[oob_config[j]];
+
+               /* correct data, if neccecary */
+               for (i = 0, j = 0, datidx = 0; i < this->eccsteps; i++, datidx += ecc) {
+                       ecc_status = this->correct_data(mtd, &data_poi[datidx], &ecc_code[j], &ecc_calc[j]);
+
+                       /* Get next chunk of ecc bytes */
+                       j += eccbytes;
+
+                       /* Check, if we have a fs supplied oob-buffer,
+                        * This is the legacy mode. Used by YAFFS1
+                        * Should go away some day
+                        */
+                       if (oob_buf && oobsel->useecc == MTD_NANDECC_PLACE) {
+                               int *p = (int *)(&oob_data[mtd->oobsize]);
+                               p[i] = ecc_status;
+                       }
+
+                       if (ecc_status == -1) {
+                               DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " "Failed ECC read, page 0x%08x\n", page);
+                               ecc_failed++;
+                       }
+               }
+
+       readoob:
+               /* check, if we have a fs supplied oob-buffer */
+               if (oob_buf) {
+                       /* without autoplace. Legacy mode used by YAFFS1 */
+                       switch(oobsel->useecc) {
+                       case MTD_NANDECC_AUTOPLACE:
+                       case MTD_NANDECC_AUTOPL_USR:
+                               /* Walk through the autoplace chunks */
+                               for (i = 0, j = 0; j < mtd->oobavail; i++) {
+                                       int from = oobsel->oobfree[i][0];
+                                       int num = oobsel->oobfree[i][1];
+                                       memcpy(&oob_buf[oob], &oob_data[from], num);
+                                       j+= num;
+                               }
+                               oob += mtd->oobavail;
+                               break;
+                       case MTD_NANDECC_PLACE:
+                               /* YAFFS1 legacy mode */
+                               oob_data += this->eccsteps * sizeof (int);
+                       default:
+                               oob_data += mtd->oobsize;
+                       }
+               }
+       readdata:
+               /* Partial page read, transfer data into fs buffer */
+               if (!aligned) {
+                       for (j = col; j < end && read < len; j++)
+                               buf[read++] = data_poi[j];
+                       this->pagebuf = realpage;
+               } else
+                       read += mtd->oobblock;
+
+               /* Apply delay or wait for ready/busy pin
+                * Do this before the AUTOINCR check, so no problems
+                * arise if a chip which does auto increment
+                * is marked as NOAUTOINCR by the board driver.
+               */
+               if (!this->dev_ready)
+                       udelay (this->chip_delay);
+               else
+                       while (!this->dev_ready(mtd));
+
+               if (read == len)
+                       break;
+
+               /* For subsequent reads align to page boundary. */
+               col = 0;
+               /* Increment page address */
+               realpage++;
+
+               page = realpage & this->pagemask;
+               /* Check, if we cross a chip boundary */
+               if (!page) {
+                       chipnr++;
+                       this->select_chip(mtd, -1);
+                       this->select_chip(mtd, chipnr);
+               }
+               /* Check, if the chip supports auto page increment
+                * or if we have hit a block boundary.
+               */
+               if (!NAND_CANAUTOINCR(this) || !(page & blockcheck))
+                       sndcmd = 1;
+       }
+
+       /* Deselect and wake up anyone waiting on the device */
+       nand_release_device(mtd);
+
+       /*
+        * Return success, if no ECC failures, else -EBADMSG
+        * fs driver will take care of that, because
+        * retlen == desired len and result == -EBADMSG
+        */
+       *retlen = read;
+       return ecc_failed ? -EBADMSG : 0;
+}
+
+/**
+ * nand_read_oob - [MTD Interface] NAND read out-of-band
+ * @mtd:       MTD device structure
+ * @from:      offset to read from
+ * @len:       number of bytes to read
+ * @retlen:    pointer to variable to store the number of read bytes
+ * @buf:       the databuffer to put data
+ *
+ * NAND read out-of-band data from the spare area
+ */
+static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf)
+{
+       int i, col, page, chipnr;
+       struct nand_chip *this = mtd->priv;
+       int     blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1;
+
+       DEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
+
+       /* Shift to get page */
+       page = (int)(from >> this->page_shift);
+       chipnr = (int)(from >> this->chip_shift);
+
+       /* Mask to get column */
+       col = from & (mtd->oobsize - 1);
+
+       /* Initialize return length value */
+       *retlen = 0;
+
+       /* Do not allow reads past end of device */
+       if ((from + len) > mtd->size) {
+               DEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: Attempt read beyond end of device\n");
+               *retlen = 0;
+               return -EINVAL;
+       }
+
+       /* Grab the lock and see if the device is available */
+       nand_get_device (this, mtd , FL_READING);
+
+       /* Select the NAND device */
+       this->select_chip(mtd, chipnr);
+
+       /* Send the read command */
+       this->cmdfunc (mtd, NAND_CMD_READOOB, col, page & this->pagemask);
+       /*
+        * Read the data, if we read more than one page
+        * oob data, let the device transfer the data !
+        */
+       i = 0;
+       while (i < len) {
+               int thislen = mtd->oobsize - col;
+               thislen = min_t(int, thislen, len);
+               this->read_buf(mtd, &buf[i], thislen);
+               i += thislen;
+
+               /* Apply delay or wait for ready/busy pin
+                * Do this before the AUTOINCR check, so no problems
+                * arise if a chip which does auto increment
+                * is marked as NOAUTOINCR by the board driver.
+               */
+               if (!this->dev_ready)
+                       udelay (this->chip_delay);
+               else
+                       while (!this->dev_ready(mtd));
+
+               /* Read more ? */
+               if (i < len) {
+                       page++;
+                       col = 0;
+
+                       /* Check, if we cross a chip boundary */
+                       if (!(page & this->pagemask)) {
+                               chipnr++;
+                               this->select_chip(mtd, -1);
+                               this->select_chip(mtd, chipnr);
+                       }
+
+                       /* Check, if the chip supports auto page increment
+                        * or if we have hit a block boundary.
+                       */
+                       if (!NAND_CANAUTOINCR(this) || !(page & blockcheck)) {
+                               /* For subsequent page reads set offset to 0 */
+                               this->cmdfunc (mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
+                       }
+               }
+       }
+
+       /* Deselect and wake up anyone waiting on the device */
+       nand_release_device(mtd);
+
+       /* Return happy */
+       *retlen = len;
+       return 0;
+}
+
+/**
+ * nand_read_raw - [GENERIC] Read raw data including oob into buffer
+ * @mtd:       MTD device structure
+ * @buf:       temporary buffer
+ * @from:      offset to read from
+ * @len:       number of bytes to read
+ * @ooblen:    number of oob data bytes to read
+ *
+ * Read raw data including oob into buffer
+ */
+int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen)
+{
+       struct nand_chip *this = mtd->priv;
+       int page = (int) (from >> this->page_shift);
+       int chip = (int) (from >> this->chip_shift);
+       int sndcmd = 1;
+       int cnt = 0;
+       int pagesize = mtd->oobblock + mtd->oobsize;
+       int     blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1;
+
+       /* Do not allow reads past end of device */
+       if ((from + len) > mtd->size) {
+               DEBUG (MTD_DEBUG_LEVEL0, "nand_read_raw: Attempt read beyond end of device\n");
+               return -EINVAL;
+       }
+
+       /* Grab the lock and see if the device is available */
+       nand_get_device (this, mtd , FL_READING);
+
+       this->select_chip (mtd, chip);
+
+       /* Add requested oob length */
+       len += ooblen;
+
+       while (len) {
+               if (sndcmd)
+                       this->cmdfunc (mtd, NAND_CMD_READ0, 0, page & this->pagemask);
+               sndcmd = 0;
+
+               this->read_buf (mtd, &buf[cnt], pagesize);
+
+               len -= pagesize;
+               cnt += pagesize;
+               page++;
+
+               if (!this->dev_ready)
+                       udelay (this->chip_delay);
+               else
+                       while (!this->dev_ready(mtd));
+
+               /* Check, if the chip supports auto page increment */
+               if (!NAND_CANAUTOINCR(this) || !(page & blockcheck))
+                       sndcmd = 1;
+       }
+
+       /* Deselect and wake up anyone waiting on the device */
+       nand_release_device(mtd);
+       return 0;
+}
+
+
+/**
+ * nand_prepare_oobbuf - [GENERIC] Prepare the out of band buffer
+ * @mtd:       MTD device structure
+ * @fsbuf:     buffer given by fs driver
+ * @oobsel:    out of band selection structre
+ * @autoplace: 1 = place given buffer into the oob bytes
+ * @numpages:  number of pages to prepare
+ *
+ * Return:
+ * 1. Filesystem buffer available and autoplacement is off,
+ *    return filesystem buffer
+ * 2. No filesystem buffer or autoplace is off, return internal
+ *    buffer
+ * 3. Filesystem buffer is given and autoplace selected
+ *    put data from fs buffer into internal buffer and
+ *    retrun internal buffer
+ *
+ * Note: The internal buffer is filled with 0xff. This must
+ * be done only once, when no autoplacement happens
+ * Autoplacement sets the buffer dirty flag, which
+ * forces the 0xff fill before using the buffer again.
+ *
+*/
+static u_char * nand_prepare_oobbuf (struct mtd_info *mtd, u_char *fsbuf, struct nand_oobinfo *oobsel,
+               int autoplace, int numpages)
+{
+       struct nand_chip *this = mtd->priv;
+       int i, len, ofs;
+
+       /* Zero copy fs supplied buffer */
+       if (fsbuf && !autoplace)
+               return fsbuf;
+
+       /* Check, if the buffer must be filled with ff again */
+       if (this->oobdirty) {
+               memset (this->oob_buf, 0xff,
+                       mtd->oobsize << (this->phys_erase_shift - this->page_shift));
+               this->oobdirty = 0;
+       }
+
+       /* If we have no autoplacement or no fs buffer use the internal one */
+       if (!autoplace || !fsbuf)
+               return this->oob_buf;
+
+       /* Walk through the pages and place the data */
+       this->oobdirty = 1;
+       ofs = 0;
+       while (numpages--) {
+               for (i = 0, len = 0; len < mtd->oobavail; i++) {
+                       int to = ofs + oobsel->oobfree[i][0];
+                       int num = oobsel->oobfree[i][1];
+                       memcpy (&this->oob_buf[to], fsbuf, num);
+                       len += num;
+                       fsbuf += num;
+               }
+               ofs += mtd->oobavail;
+       }
+       return this->oob_buf;
+}
+
+#define NOTALIGNED(x) (x & (mtd->oobblock-1)) != 0
+
+/**
+ * nand_write - [MTD Interface] compability function for nand_write_ecc
+ * @mtd:       MTD device structure
+ * @to:                offset to write to
+ * @len:       number of bytes to write
+ * @retlen:    pointer to variable to store the number of written bytes
+ * @buf:       the data to write
+ *
+ * This function simply calls nand_write_ecc with oob buffer and oobsel = NULL
+ *
+*/
+static int nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf)
+{
+       return (nand_write_ecc (mtd, to, len, retlen, buf, NULL, NULL));
+}
+
+/**
+ * nand_write_ecc - [MTD Interface] NAND write with ECC
+ * @mtd:       MTD device structure
+ * @to:                offset to write to
+ * @len:       number of bytes to write
+ * @retlen:    pointer to variable to store the number of written bytes
+ * @buf:       the data to write
+ * @eccbuf:    filesystem supplied oob data buffer
+ * @oobsel:    oob selection structure
+ *
+ * NAND write with ECC
+ */
+static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
+                          size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel)
+{
+       int startpage, page, ret = -EIO, oob = 0, written = 0, chipnr;
+       int autoplace = 0, numpages, totalpages;
+       struct nand_chip *this = mtd->priv;
+       u_char *oobbuf, *bufstart;
+       int     ppblock = (1 << (this->phys_erase_shift - this->page_shift));
+
+       DEBUG (MTD_DEBUG_LEVEL3, "nand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
+
+       /* Initialize retlen, in case of early exit */
+       *retlen = 0;
+
+       /* Do not allow write past end of device */
+       if ((to + len) > mtd->size) {
+               DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Attempt to write past end of page\n");
+               return -EINVAL;
+       }
+
+       /* reject writes, which are not page aligned */
+       if (NOTALIGNED (to) || NOTALIGNED(len)) {
+               printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n");
+               return -EINVAL;
+       }
+
+       /* Grab the lock and see if the device is available */
+       nand_get_device (this, mtd, FL_WRITING);
+
+       /* Calculate chipnr */
+       chipnr = (int)(to >> this->chip_shift);
+       /* Select the NAND device */
+       this->select_chip(mtd, chipnr);
+
+       /* Check, if it is write protected */
+       if (nand_check_wp(mtd))
+               goto out;
+
+       /* if oobsel is NULL, use chip defaults */
+       if (oobsel == NULL)
+               oobsel = &mtd->oobinfo;
+
+       /* Autoplace of oob data ? Use the default placement scheme */
+       if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) {
+               oobsel = this->autooob;
+               autoplace = 1;
+       }
+       if (oobsel->useecc == MTD_NANDECC_AUTOPL_USR)
+               autoplace = 1;
+
+       /* Setup variables and oob buffer */
+       totalpages = len >> this->page_shift;
+       page = (int) (to >> this->page_shift);
+       /* Invalidate the page cache, if we write to the cached page */
+       if (page <= this->pagebuf && this->pagebuf < (page + totalpages))
+               this->pagebuf = -1;
+
+       /* Set it relative to chip */
+       page &= this->pagemask;
+       startpage = page;
+       /* Calc number of pages we can write in one go */
+       numpages = min (ppblock - (startpage  & (ppblock - 1)), totalpages);
+       oobbuf = nand_prepare_oobbuf (mtd, eccbuf, oobsel, autoplace, numpages);
+       bufstart = (u_char *)buf;
+
+       /* Loop until all data is written */
+       while (written < len) {
+
+               this->data_poi = (u_char*) &buf[written];
+               /* Write one page. If this is the last page to write
+                * or the last page in this block, then use the
+                * real pageprogram command, else select cached programming
+                * if supported by the chip.
+                */
+               ret = nand_write_page (mtd, this, page, &oobbuf[oob], oobsel, (--numpages > 0));
+               if (ret) {
+                       DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: write_page failed %d\n", ret);
+                       goto out;
+               }
+               /* Next oob page */
+               oob += mtd->oobsize;
+               /* Update written bytes count */
+               written += mtd->oobblock;
+               if (written == len)
+                       goto cmp;
+
+               /* Increment page address */
+               page++;
+
+               /* Have we hit a block boundary ? Then we have to verify and
+                * if verify is ok, we have to setup the oob buffer for
+                * the next pages.
+               */
+               if (!(page & (ppblock - 1))){
+                       int ofs;
+                       this->data_poi = bufstart;
+                       ret = nand_verify_pages (mtd, this, startpage,
+                               page - startpage,
+                               oobbuf, oobsel, chipnr, (eccbuf != NULL));
+                       if (ret) {
+                               DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: verify_pages failed %d\n", ret);
+                               goto out;
+                       }
+                       *retlen = written;
+
+                       ofs = autoplace ? mtd->oobavail : mtd->oobsize;
+                       if (eccbuf)
+                               eccbuf += (page - startpage) * ofs;
+                       totalpages -= page - startpage;
+                       numpages = min (totalpages, ppblock);
+                       page &= this->pagemask;
+                       startpage = page;
+                       oob = 0;
+                       this->oobdirty = 1;
+                       oobbuf = nand_prepare_oobbuf (mtd, eccbuf, oobsel,
+                                       autoplace, numpages);
+                       /* Check, if we cross a chip boundary */
+                       if (!page) {
+                               chipnr++;
+                               this->select_chip(mtd, -1);
+                               this->select_chip(mtd, chipnr);
+                       }
+               }
+       }
+       /* Verify the remaining pages */
+cmp:
+       this->data_poi = bufstart;
+       ret = nand_verify_pages (mtd, this, startpage, totalpages,
+               oobbuf, oobsel, chipnr, (eccbuf != NULL));
+       if (!ret)
+               *retlen = written;
+       else
+               DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: verify_pages failed %d\n", ret);
+
+out:
+       /* Deselect and wake up anyone waiting on the device */
+       nand_release_device(mtd);
+
+       return ret;
+}
+
+
+/**
+ * nand_write_oob - [MTD Interface] NAND write out-of-band
+ * @mtd:       MTD device structure
+ * @to:                offset to write to
+ * @len:       number of bytes to write
+ * @retlen:    pointer to variable to store the number of written bytes
+ * @buf:       the data to write
+ *
+ * NAND write out-of-band
+ */
+static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf)
+{
+       int column, page, status, ret = -EIO, chipnr;
+       struct nand_chip *this = mtd->priv;
+
+       DEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
+
+       /* Shift to get page */
+       page = (int) (to >> this->page_shift);
+       chipnr = (int) (to >> this->chip_shift);
+
+       /* Mask to get column */
+       column = to & (mtd->oobsize - 1);
+
+       /* Initialize return length value */
+       *retlen = 0;
+
+       /* Do not allow write past end of page */
+       if ((column + len) > mtd->oobsize) {
+               DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Attempt to write past end of page\n");
+               return -EINVAL;
+       }
+
+       /* Grab the lock and see if the device is available */
+       nand_get_device (this, mtd, FL_WRITING);
+
+       /* Select the NAND device */
+       this->select_chip(mtd, chipnr);
+
+       /* Reset the chip. Some chips (like the Toshiba TC5832DC found
+          in one of my DiskOnChip 2000 test units) will clear the whole
+          data page too if we don't do this. I have no clue why, but
+          I seem to have 'fixed' it in the doc2000 driver in
+          August 1999.  dwmw2. */
+       this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+
+       /* Check, if it is write protected */
+       if (nand_check_wp(mtd))
+               goto out;
+
+       /* Invalidate the page cache, if we write to the cached page */
+       if (page == this->pagebuf)
+               this->pagebuf = -1;
+
+       if (NAND_MUST_PAD(this)) {
+               /* Write out desired data */
+               this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock, page & this->pagemask);
+               /* prepad 0xff for partial programming */
+               this->write_buf(mtd, ffchars, column);
+               /* write data */
+               this->write_buf(mtd, buf, len);
+               /* postpad 0xff for partial programming */
+               this->write_buf(mtd, ffchars, mtd->oobsize - (len+column));
+       } else {
+               /* Write out desired data */
+               this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock + column, page & this->pagemask);
+               /* write data */
+               this->write_buf(mtd, buf, len);
+       }
+       /* Send command to program the OOB data */
+       this->cmdfunc (mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+       status = this->waitfunc (mtd, this, FL_WRITING);
+
+       /* See if device thinks it succeeded */
+       if (status & 0x01) {
+               DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write, page 0x%08x\n", page);
+               ret = -EIO;
+               goto out;
+       }
+       /* Return happy */
+       *retlen = len;
+
+#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
+       /* Send command to read back the data */
+       this->cmdfunc (mtd, NAND_CMD_READOOB, column, page & this->pagemask);
+
+       if (this->verify_buf(mtd, buf, len)) {
+               DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write verify, page 0x%08x\n", page);
+               ret = -EIO;
+               goto out;
+       }
+#endif
+       ret = 0;
+out:
+       /* Deselect and wake up anyone waiting on the device */
+       nand_release_device(mtd);
+
+       return ret;
+}
+
+/* XXX U-BOOT XXX */
+#if 0
+/**
+ * nand_writev - [MTD Interface] compabilty function for nand_writev_ecc
+ * @mtd:       MTD device structure
+ * @vecs:      the iovectors to write
+ * @count:     number of vectors
+ * @to:                offset to write to
+ * @retlen:    pointer to variable to store the number of written bytes
+ *
+ * NAND write with kvec. This just calls the ecc function
+ */
+static int nand_writev (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count,
+               loff_t to, size_t * retlen)
+{
+       return (nand_writev_ecc (mtd, vecs, count, to, retlen, NULL, NULL));
+}
+
+/**
+ * nand_writev_ecc - [MTD Interface] write with iovec with ecc
+ * @mtd:       MTD device structure
+ * @vecs:      the iovectors to write
+ * @count:     number of vectors
+ * @to:                offset to write to
+ * @retlen:    pointer to variable to store the number of written bytes
+ * @eccbuf:    filesystem supplied oob data buffer
+ * @oobsel:    oob selection structure
+ *
+ * NAND write with iovec with ecc
+ */
+static int nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count,
+               loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel)
+{
+       int i, page, len, total_len, ret = -EIO, written = 0, chipnr;
+       int oob, numpages, autoplace = 0, startpage;
+       struct nand_chip *this = mtd->priv;
+       int     ppblock = (1 << (this->phys_erase_shift - this->page_shift));
+       u_char *oobbuf, *bufstart;
+
+       /* Preset written len for early exit */
+       *retlen = 0;
+
+       /* Calculate total length of data */
+       total_len = 0;
+       for (i = 0; i < count; i++)
+               total_len += (int) vecs[i].iov_len;
+
+       DEBUG (MTD_DEBUG_LEVEL3,
+              "nand_writev: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count);
+
+       /* Do not allow write past end of page */
+       if ((to + total_len) > mtd->size) {
+               DEBUG (MTD_DEBUG_LEVEL0, "nand_writev: Attempted write past end of device\n");
+               return -EINVAL;
+       }
+
+       /* reject writes, which are not page aligned */
+       if (NOTALIGNED (to) || NOTALIGNED(total_len)) {
+               printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n");
+               return -EINVAL;
+       }
+
+       /* Grab the lock and see if the device is available */
+       nand_get_device (this, mtd, FL_WRITING);
+
+       /* Get the current chip-nr */
+       chipnr = (int) (to >> this->chip_shift);
+       /* Select the NAND device */
+       this->select_chip(mtd, chipnr);
+
+       /* Check, if it is write protected */
+       if (nand_check_wp(mtd))
+               goto out;
+
+       /* if oobsel is NULL, use chip defaults */
+       if (oobsel == NULL)
+               oobsel = &mtd->oobinfo;
+
+       /* Autoplace of oob data ? Use the default placement scheme */
+       if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) {
+               oobsel = this->autooob;
+               autoplace = 1;
+       }
+       if (oobsel->useecc == MTD_NANDECC_AUTOPL_USR)
+               autoplace = 1;
+
+       /* Setup start page */
+       page = (int) (to >> this->page_shift);
+       /* Invalidate the page cache, if we write to the cached page */
+       if (page <= this->pagebuf && this->pagebuf < ((to + total_len) >> this->page_shift))
+               this->pagebuf = -1;
+
+       startpage = page & this->pagemask;
+
+       /* Loop until all kvec' data has been written */
+       len = 0;
+       while (count) {
+               /* If the given tuple is >= pagesize then
+                * write it out from the iov
+                */
+               if ((vecs->iov_len - len) >= mtd->oobblock) {
+                       /* Calc number of pages we can write
+                        * out of this iov in one go */
+                       numpages = (vecs->iov_len - len) >> this->page_shift;
+                       /* Do not cross block boundaries */
+                       numpages = min (ppblock - (startpage & (ppblock - 1)), numpages);
+                       oobbuf = nand_prepare_oobbuf (mtd, NULL, oobsel, autoplace, numpages);
+                       bufstart = (u_char *)vecs->iov_base;
+                       bufstart += len;
+                       this->data_poi = bufstart;
+                       oob = 0;
+                       for (i = 1; i <= numpages; i++) {
+                               /* Write one page. If this is the last page to write
+                                * then use the real pageprogram command, else select
+                                * cached programming if supported by the chip.
+                                */
+                               ret = nand_write_page (mtd, this, page & this->pagemask,
+                                       &oobbuf[oob], oobsel, i != numpages);
+                               if (ret)
+                                       goto out;
+                               this->data_poi += mtd->oobblock;
+                               len += mtd->oobblock;
+                               oob += mtd->oobsize;
+                               page++;
+                       }
+                       /* Check, if we have to switch to the next tuple */
+                       if (len >= (int) vecs->iov_len) {
+                               vecs++;
+                               len = 0;
+                               count--;
+                       }
+               } else {
+                       /* We must use the internal buffer, read data out of each
+                        * tuple until we have a full page to write
+                        */
+                       int cnt = 0;
+                       while (cnt < mtd->oobblock) {
+                               if (vecs->iov_base != NULL && vecs->iov_len)
+                                       this->data_buf[cnt++] = ((u_char *) vecs->iov_base)[len++];
+                               /* Check, if we have to switch to the next tuple */
+                               if (len >= (int) vecs->iov_len) {
+                                       vecs++;
+                                       len = 0;
+                                       count--;
+                               }
+                       }
+                       this->pagebuf = page;
+                       this->data_poi = this->data_buf;
+                       bufstart = this->data_poi;
+                       numpages = 1;
+                       oobbuf = nand_prepare_oobbuf (mtd, NULL, oobsel, autoplace, numpages);
+                       ret = nand_write_page (mtd, this, page & this->pagemask,
+                               oobbuf, oobsel, 0);
+                       if (ret)
+                               goto out;
+                       page++;
+               }
+
+               this->data_poi = bufstart;
+               ret = nand_verify_pages (mtd, this, startpage, numpages, oobbuf, oobsel, chipnr, 0);
+               if (ret)
+                       goto out;
+
+               written += mtd->oobblock * numpages;
+               /* All done ? */
+               if (!count)
+                       break;
+
+               startpage = page & this->pagemask;
+               /* Check, if we cross a chip boundary */
+               if (!startpage) {
+                       chipnr++;
+                       this->select_chip(mtd, -1);
+                       this->select_chip(mtd, chipnr);
+               }
+       }
+       ret = 0;
+out:
+       /* Deselect and wake up anyone waiting on the device */
+       nand_release_device(mtd);
+
+       *retlen = written;
+       return ret;
+}
+#endif
+
+/**
+ * single_erease_cmd - [GENERIC] NAND standard block erase command function
+ * @mtd:       MTD device structure
+ * @page:      the page address of the block which will be erased
+ *
+ * Standard erase command for NAND chips
+ */
+static void single_erase_cmd (struct mtd_info *mtd, int page)
+{
+       struct nand_chip *this = mtd->priv;
+       /* Send commands to erase a block */
+       this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page);
+       this->cmdfunc (mtd, NAND_CMD_ERASE2, -1, -1);
+}
+
+/**
+ * multi_erease_cmd - [GENERIC] AND specific block erase command function
+ * @mtd:       MTD device structure
+ * @page:      the page address of the block which will be erased
+ *
+ * AND multi block erase command function
+ * Erase 4 consecutive blocks
+ */
+static void multi_erase_cmd (struct mtd_info *mtd, int page)
+{
+       struct nand_chip *this = mtd->priv;
+       /* Send commands to erase a block */
+       this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++);
+       this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++);
+       this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++);
+       this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page);
+       this->cmdfunc (mtd, NAND_CMD_ERASE2, -1, -1);
+}
+
+/**
+ * nand_erase - [MTD Interface] erase block(s)
+ * @mtd:       MTD device structure
+ * @instr:     erase instruction
+ *
+ * Erase one ore more blocks
+ */
+static int nand_erase (struct mtd_info *mtd, struct erase_info *instr)
+{
+       return nand_erase_nand (mtd, instr, 0);
+}
+
+/**
+ * nand_erase_intern - [NAND Interface] erase block(s)
+ * @mtd:       MTD device structure
+ * @instr:     erase instruction
+ * @allowbbt:  allow erasing the bbt area
+ *
+ * Erase one ore more blocks
+ */
+int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt)
+{
+       int page, len, status, pages_per_block, ret, chipnr;
+       struct nand_chip *this = mtd->priv;
+
+       DEBUG (MTD_DEBUG_LEVEL3,
+              "nand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len);
+
+       /* Start address must align on block boundary */
+       if (instr->addr & ((1 << this->phys_erase_shift) - 1)) {
+               DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
+               return -EINVAL;
+       }
+
+       /* Length must align on block boundary */
+       if (instr->len & ((1 << this->phys_erase_shift) - 1)) {
+               DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Length not block aligned\n");
+               return -EINVAL;
+       }
+
+       /* Do not allow erase past end of device */
+       if ((instr->len + instr->addr) > mtd->size) {
+               DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Erase past end of device\n");
+               return -EINVAL;
+       }
+
+       instr->fail_addr = 0xffffffff;
+
+       /* Grab the lock and see if the device is available */
+       nand_get_device (this, mtd, FL_ERASING);
+
+       /* Shift to get first page */
+       page = (int) (instr->addr >> this->page_shift);
+       chipnr = (int) (instr->addr >> this->chip_shift);
+
+       /* Calculate pages in each block */
+       pages_per_block = 1 << (this->phys_erase_shift - this->page_shift);
+
+       /* Select the NAND device */
+       this->select_chip(mtd, chipnr);
+
+       /* Check the WP bit */
+       /* Check, if it is write protected */
+       if (nand_check_wp(mtd)) {
+               DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Device is write protected!!!\n");
+               instr->state = MTD_ERASE_FAILED;
+               goto erase_exit;
+       }
+
+       /* Loop through the pages */
+       len = instr->len;
+
+       instr->state = MTD_ERASING;
+
+       while (len) {
+#ifndef NAND_ALLOW_ERASE_ALL
+               /* Check if we have a bad block, we do not erase bad blocks ! */
+               if (nand_block_checkbad(mtd, ((loff_t) page) << this->page_shift, 0, allowbbt)) {
+                       printk (KERN_WARNING "nand_erase: attempt to erase a bad block at page 0x%08x\n", page);
+                       instr->state = MTD_ERASE_FAILED;
+                       goto erase_exit;
+               }
+#endif
+               /* Invalidate the page cache, if we erase the block which contains
+                  the current cached page */
+               if (page <= this->pagebuf && this->pagebuf < (page + pages_per_block))
+                       this->pagebuf = -1;
+
+               this->erase_cmd (mtd, page & this->pagemask);
+
+               status = this->waitfunc (mtd, this, FL_ERASING);
+
+               /* See if block erase succeeded */
+               if (status & 0x01) {
+                       DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " "Failed erase, page 0x%08x\n", page);
+                       instr->state = MTD_ERASE_FAILED;
+                       instr->fail_addr = (page << this->page_shift);
+                       goto erase_exit;
+               }
+
+               /* Increment page address and decrement length */
+               len -= (1 << this->phys_erase_shift);
+               page += pages_per_block;
+
+               /* Check, if we cross a chip boundary */
+               if (len && !(page & this->pagemask)) {
+                       chipnr++;
+                       this->select_chip(mtd, -1);
+                       this->select_chip(mtd, chipnr);
+               }
+       }
+       instr->state = MTD_ERASE_DONE;
+
+erase_exit:
+
+       ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
+       /* Do call back function */
+       if (!ret)
+               mtd_erase_callback(instr);
+
+       /* Deselect and wake up anyone waiting on the device */
+       nand_release_device(mtd);
+
+       /* Return more or less happy */
+       return ret;
+}
+
+/**
+ * nand_sync - [MTD Interface] sync
+ * @mtd:       MTD device structure
+ *
+ * Sync is actually a wait for chip ready function
+ */
+static void nand_sync (struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+
+       DEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
+
+       /* Grab the lock and see if the device is available */
+       nand_get_device (this, mtd, FL_SYNCING);
+       /* Release it and go back */
+       nand_release_device (mtd);
+}
+
+
+/**
+ * nand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
+ * @mtd:       MTD device structure
+ * @ofs:       offset relative to mtd start
+ */
+static int nand_block_isbad (struct mtd_info *mtd, loff_t ofs)
+{
+       /* Check for invalid offset */
+       if (ofs > mtd->size)
+               return -EINVAL;
+
+       return nand_block_checkbad (mtd, ofs, 1, 0);
+}
+
+/**
+ * nand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
+ * @mtd:       MTD device structure
+ * @ofs:       offset relative to mtd start
+ */
+static int nand_block_markbad (struct mtd_info *mtd, loff_t ofs)
+{
+       struct nand_chip *this = mtd->priv;
+       int ret;
+
+       if ((ret = nand_block_isbad(mtd, ofs))) {
+               /* If it was bad already, return success and do nothing. */
+               if (ret > 0)
+                       return 0;
+               return ret;
+       }
+
+       return this->block_markbad(mtd, ofs);
+}
+
+/**
+ * nand_scan - [NAND Interface] Scan for the NAND device
+ * @mtd:       MTD device structure
+ * @maxchips:  Number of chips to scan for
+ *
+ * This fills out all the not initialized function pointers
+ * with the defaults.
+ * The flash ID is read and the mtd/chip structures are
+ * filled with the appropriate values. Buffers are allocated if
+ * they are not provided by the board driver
+ *
+ */
+int nand_scan (struct mtd_info *mtd, int maxchips)
+{
+       int i, j, nand_maf_id, nand_dev_id, busw;
+       struct nand_chip *this = mtd->priv;
+
+       /* Get buswidth to select the correct functions*/
+       busw = this->options & NAND_BUSWIDTH_16;
+
+       /* check for proper chip_delay setup, set 20us if not */
+       if (!this->chip_delay)
+               this->chip_delay = 20;
+
+       /* check, if a user supplied command function given */
+       if (this->cmdfunc == NULL)
+               this->cmdfunc = nand_command;
+
+       /* check, if a user supplied wait function given */
+       if (this->waitfunc == NULL)
+               this->waitfunc = nand_wait;
+
+       if (!this->select_chip)
+               this->select_chip = nand_select_chip;
+       if (!this->write_byte)
+               this->write_byte = busw ? nand_write_byte16 : nand_write_byte;
+       if (!this->read_byte)
+               this->read_byte = busw ? nand_read_byte16 : nand_read_byte;
+       if (!this->write_word)
+               this->write_word = nand_write_word;
+       if (!this->read_word)
+               this->read_word = nand_read_word;
+       if (!this->block_bad)
+               this->block_bad = nand_block_bad;
+       if (!this->block_markbad)
+               this->block_markbad = nand_default_block_markbad;
+       if (!this->write_buf)
+               this->write_buf = busw ? nand_write_buf16 : nand_write_buf;
+       if (!this->read_buf)
+               this->read_buf = busw ? nand_read_buf16 : nand_read_buf;
+       if (!this->verify_buf)
+               this->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
+       if (!this->scan_bbt)
+               this->scan_bbt = nand_default_bbt;
+
+       /* Select the device */
+       this->select_chip(mtd, 0);
+
+       /* Send the command for reading device ID */
+       this->cmdfunc (mtd, NAND_CMD_READID, 0x00, -1);
+
+       /* Read manufacturer and device IDs */
+       nand_maf_id = this->read_byte(mtd);
+       nand_dev_id = this->read_byte(mtd);
+
+       /* Print and store flash device information */
+       for (i = 0; nand_flash_ids[i].name != NULL; i++) {
+
+               if (nand_dev_id != nand_flash_ids[i].id)
+                       continue;
+
+               if (!mtd->name) mtd->name = nand_flash_ids[i].name;
+               this->chipsize = nand_flash_ids[i].chipsize << 20;
+
+               /* New devices have all the information in additional id bytes */
+               if (!nand_flash_ids[i].pagesize) {
+                       int extid;
+                       /* The 3rd id byte contains non relevant data ATM */
+                       extid = this->read_byte(mtd);
+                       /* The 4th id byte is the important one */
+                       extid = this->read_byte(mtd);
+                       /* Calc pagesize */
+                       mtd->oobblock = 1024 << (extid & 0x3);
+                       extid >>= 2;
+                       /* Calc oobsize */
+                       mtd->oobsize = (8 << (extid & 0x03)) * (mtd->oobblock / 512);
+                       extid >>= 2;
+                       /* Calc blocksize. Blocksize is multiples of 64KiB */
+                       mtd->erasesize = (64 * 1024)  << (extid & 0x03);
+                       extid >>= 2;
+                       /* Get buswidth information */
+                       busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
+
+               } else {
+                       /* Old devices have this data hardcoded in the
+                        * device id table */
+                       mtd->erasesize = nand_flash_ids[i].erasesize;
+                       mtd->oobblock = nand_flash_ids[i].pagesize;
+                       mtd->oobsize = mtd->oobblock / 32;
+                       busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16;
+               }
+
+               /* Check, if buswidth is correct. Hardware drivers should set
+                * this correct ! */
+               if (busw != (this->options & NAND_BUSWIDTH_16)) {
+                       printk (KERN_INFO "NAND device: Manufacturer ID:"
+                               " 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id,
+                               nand_manuf_ids[i].name , mtd->name);
+                       printk (KERN_WARNING
+                               "NAND bus width %d instead %d bit\n",
+                                       (this->options & NAND_BUSWIDTH_16) ? 16 : 8,
+                                       busw ? 16 : 8);
+                       this->select_chip(mtd, -1);
+                       return 1;
+               }
+
+               /* Calculate the address shift from the page size */
+               this->page_shift = ffs(mtd->oobblock) - 1;
+               this->bbt_erase_shift = this->phys_erase_shift = ffs(mtd->erasesize) - 1;
+               this->chip_shift = ffs(this->chipsize) - 1;
+
+               /* Set the bad block position */
+               this->badblockpos = mtd->oobblock > 512 ?
+                       NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
+
+               /* Get chip options, preserve non chip based options */
+               this->options &= ~NAND_CHIPOPTIONS_MSK;
+               this->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK;
+               /* Set this as a default. Board drivers can override it, if neccecary */
+               this->options |= NAND_NO_AUTOINCR;
+               /* Check if this is a not a samsung device. Do not clear the options
+                * for chips which are not having an extended id.
+                */
+               if (nand_maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize)
+                       this->options &= ~NAND_SAMSUNG_LP_OPTIONS;
+
+               /* Check for AND chips with 4 page planes */
+               if (this->options & NAND_4PAGE_ARRAY)
+                       this->erase_cmd = multi_erase_cmd;
+               else
+                       this->erase_cmd = single_erase_cmd;
+
+               /* Do not replace user supplied command function ! */
+               if (mtd->oobblock > 512 && this->cmdfunc == nand_command)
+                       this->cmdfunc = nand_command_lp;
+
+               /* Try to identify manufacturer */
+               for (j = 0; nand_manuf_ids[j].id != 0x0; j++) {
+                       if (nand_manuf_ids[j].id == nand_maf_id)
+                               break;
+               }
+               break;
+       }
+
+       if (!nand_flash_ids[i].name) {
+               printk (KERN_WARNING "No NAND device found!!!\n");
+               this->select_chip(mtd, -1);
+               return 1;
+       }
+
+       for (i=1; i < maxchips; i++) {
+               this->select_chip(mtd, i);
+
+               /* Send the command for reading device ID */
+               this->cmdfunc (mtd, NAND_CMD_READID, 0x00, -1);
+
+               /* Read manufacturer and device IDs */
+               if (nand_maf_id != this->read_byte(mtd) ||
+                   nand_dev_id != this->read_byte(mtd))
+                       break;
+       }
+       if (i > 1)
+               printk(KERN_INFO "%d NAND chips detected\n", i);
+
+       /* Allocate buffers, if neccecary */
+       if (!this->oob_buf) {
+               size_t len;
+               len = mtd->oobsize << (this->phys_erase_shift - this->page_shift);
+               this->oob_buf = kmalloc (len, GFP_KERNEL);
+               if (!this->oob_buf) {
+                       printk (KERN_ERR "nand_scan(): Cannot allocate oob_buf\n");
+                       return -ENOMEM;
+               }
+               this->options |= NAND_OOBBUF_ALLOC;
+       }
+
+       if (!this->data_buf) {
+               size_t len;
+               len = mtd->oobblock + mtd->oobsize;
+               this->data_buf = kmalloc (len, GFP_KERNEL);
+               if (!this->data_buf) {
+                       if (this->options & NAND_OOBBUF_ALLOC)
+                               kfree (this->oob_buf);
+                       printk (KERN_ERR "nand_scan(): Cannot allocate data_buf\n");
+                       return -ENOMEM;
+               }
+               this->options |= NAND_DATABUF_ALLOC;
+       }
+
+       /* Store the number of chips and calc total size for mtd */
+       this->numchips = i;
+       mtd->size = i * this->chipsize;
+       /* Convert chipsize to number of pages per chip -1. */
+       this->pagemask = (this->chipsize >> this->page_shift) - 1;
+       /* Preset the internal oob buffer */
+       memset(this->oob_buf, 0xff, mtd->oobsize << (this->phys_erase_shift - this->page_shift));
+
+       /* If no default placement scheme is given, select an
+        * appropriate one */
+       if (!this->autooob) {
+               /* Select the appropriate default oob placement scheme for
+                * placement agnostic filesystems */
+               switch (mtd->oobsize) {
+               case 8:
+                       this->autooob = &nand_oob_8;
+                       break;
+               case 16:
+                       this->autooob = &nand_oob_16;
+                       break;
+               case 64:
+                       this->autooob = &nand_oob_64;
+                       break;
+               default:
+                       printk (KERN_WARNING "No oob scheme defined for oobsize %d\n",
+                               mtd->oobsize);
+/*                     BUG(); */
+               }
+       }
+
+       /* The number of bytes available for the filesystem to place fs dependend
+        * oob data */
+       if (this->options & NAND_BUSWIDTH_16) {
+               mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 2);
+               if (this->autooob->eccbytes & 0x01)
+                       mtd->oobavail--;
+       } else
+               mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 1);
+
+       /*
+        * check ECC mode, default to software
+        * if 3byte/512byte hardware ECC is selected and we have 256 byte pagesize
+        * fallback to software ECC
+       */
+       this->eccsize = 256;    /* set default eccsize */
+       this->eccbytes = 3;
+
+       switch (this->eccmode) {
+       case NAND_ECC_HW12_2048:
+               if (mtd->oobblock < 2048) {
+                       printk(KERN_WARNING "2048 byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
+                              mtd->oobblock);
+                       this->eccmode = NAND_ECC_SOFT;
+                       this->calculate_ecc = nand_calculate_ecc;
+                       this->correct_data = nand_correct_data;
+               } else
+                       this->eccsize = 2048;
+               break;
+
+       case NAND_ECC_HW3_512:
+       case NAND_ECC_HW6_512:
+       case NAND_ECC_HW8_512:
+               if (mtd->oobblock == 256) {
+                       printk (KERN_WARNING "512 byte HW ECC not possible on 256 Byte pagesize, fallback to SW ECC \n");
+                       this->eccmode = NAND_ECC_SOFT;
+                       this->calculate_ecc = nand_calculate_ecc;
+                       this->correct_data = nand_correct_data;
+               } else
+                       this->eccsize = 512; /* set eccsize to 512 */
+               break;
+
+       case NAND_ECC_HW3_256:
+               break;
+
+       case NAND_ECC_NONE:
+               printk (KERN_WARNING "NAND_ECC_NONE selected by board driver. This is not recommended !!\n");
+               this->eccmode = NAND_ECC_NONE;
+               break;
+
+       case NAND_ECC_SOFT:
+               this->calculate_ecc = nand_calculate_ecc;
+               this->correct_data = nand_correct_data;
+               break;
+
+       default:
+               printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
+/*             BUG(); */
+       }
+
+       /* Check hardware ecc function availability and adjust number of ecc bytes per
+        * calculation step
+       */
+       switch (this->eccmode) {
+       case NAND_ECC_HW12_2048:
+               this->eccbytes += 4;
+       case NAND_ECC_HW8_512:
+               this->eccbytes += 2;
+       case NAND_ECC_HW6_512:
+               this->eccbytes += 3;
+       case NAND_ECC_HW3_512:
+       case NAND_ECC_HW3_256:
+               if (this->calculate_ecc && this->correct_data && this->enable_hwecc)
+                       break;
+               printk (KERN_WARNING "No ECC functions supplied, Hardware ECC not possible\n");
+/*             BUG();  */
+       }
+
+       mtd->eccsize = this->eccsize;
+
+       /* Set the number of read / write steps for one page to ensure ECC generation */
+       switch (this->eccmode) {
+       case NAND_ECC_HW12_2048:
+               this->eccsteps = mtd->oobblock / 2048;
+               break;
+       case NAND_ECC_HW3_512:
+       case NAND_ECC_HW6_512:
+       case NAND_ECC_HW8_512:
+               this->eccsteps = mtd->oobblock / 512;
+               break;
+       case NAND_ECC_HW3_256:
+       case NAND_ECC_SOFT:
+               this->eccsteps = mtd->oobblock / 256;
+               break;
+
+       case NAND_ECC_NONE:
+               this->eccsteps = 1;
+               break;
+       }
+
+/* XXX U-BOOT XXX */
+#if 0
+       /* Initialize state, waitqueue and spinlock */
+       this->state = FL_READY;
+       init_waitqueue_head (&this->wq);
+       spin_lock_init (&this->chip_lock);
+#endif
+
+       /* De-select the device */
+       this->select_chip(mtd, -1);
+
+       /* Invalidate the pagebuffer reference */
+       this->pagebuf = -1;
+
+       /* Fill in remaining MTD driver data */
+       mtd->type = MTD_NANDFLASH;
+       mtd->flags = MTD_CAP_NANDFLASH | MTD_ECC;
+       mtd->ecctype = MTD_ECC_SW;
+       mtd->erase = nand_erase;
+       mtd->point = NULL;
+       mtd->unpoint = NULL;
+       mtd->read = nand_read;
+       mtd->write = nand_write;
+       mtd->read_ecc = nand_read_ecc;
+       mtd->write_ecc = nand_write_ecc;
+       mtd->read_oob = nand_read_oob;
+       mtd->write_oob = nand_write_oob;
+/* XXX U-BOOT XXX */
+#if 0
+       mtd->readv = NULL;
+       mtd->writev = nand_writev;
+       mtd->writev_ecc = nand_writev_ecc;
+#endif
+       mtd->sync = nand_sync;
+/* XXX U-BOOT XXX */
+#if 0
+       mtd->lock = NULL;
+       mtd->unlock = NULL;
+       mtd->suspend = NULL;
+       mtd->resume = NULL;
+#endif
+       mtd->block_isbad = nand_block_isbad;
+       mtd->block_markbad = nand_block_markbad;
+
+       /* and make the autooob the default one */
+       memcpy(&mtd->oobinfo, this->autooob, sizeof(mtd->oobinfo));
+/* XXX U-BOOT XXX */
+#if 0
+       mtd->owner = THIS_MODULE;
+#endif
+       /* Build bad block table */
+       return this->scan_bbt (mtd);
+}
+
+/**
+ * nand_release - [NAND Interface] Free resources held by the NAND device
+ * @mtd:       MTD device structure
+ */
+void nand_release (struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+
+#ifdef CONFIG_MTD_PARTITIONS
+       /* Deregister partitions */
+       del_mtd_partitions (mtd);
+#endif
+       /* Deregister the device */
+/* XXX U-BOOT XXX */
+#if 0
+       del_mtd_device (mtd);
+#endif
+       /* Free bad block table memory, if allocated */
+       if (this->bbt)
+               kfree (this->bbt);
+       /* Buffer allocated by nand_scan ? */
+       if (this->options & NAND_OOBBUF_ALLOC)
+               kfree (this->oob_buf);
+       /* Buffer allocated by nand_scan ? */
+       if (this->options & NAND_DATABUF_ALLOC)
+               kfree (this->data_buf);
+}
+
+#endif

diff --git a/drivers/nand/nand_bbt.c b/drivers/nand/nand_bbt.c
new file mode 100644 (file)
index 0000000..aaa9400
--- /dev/null
+++ b/drivers/nand/nand_bbt.c
@@ -0,0 +1,1052 @@
+/*
+ *  drivers/mtd/nand_bbt.c
+ *
+ *  Overview:
+ *   Bad block table support for the NAND driver
+ *
+ *  Copyright (C) 2004 Thomas Gleixner (tglx@linutronix.de)
+ *
+ * $Id: nand_bbt.c,v 1.28 2004/11/13 10:19:09 gleixner Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Description:
+ *
+ * When nand_scan_bbt is called, then it tries to find the bad block table
+ * depending on the options in the bbt descriptor(s). If a bbt is found
+ * then the contents are read and the memory based bbt is created. If a
+ * mirrored bbt is selected then the mirror is searched too and the
+ * versions are compared. If the mirror has a greater version number
+ * than the mirror bbt is used to build the memory based bbt.
+ * If the tables are not versioned, then we "or" the bad block information.
+ * If one of the bbt's is out of date or does not exist it is (re)created.
+ * If no bbt exists at all then the device is scanned for factory marked
+ * good / bad blocks and the bad block tables are created.
+ *
+ * For manufacturer created bbts like the one found on M-SYS DOC devices
+ * the bbt is searched and read but never created
+ *
+ * The autogenerated bad block table is located in the last good blocks
+ * of the device. The table is mirrored, so it can be updated eventually.
+ * The table is marked in the oob area with an ident pattern and a version
+ * number which indicates which of both tables is more up to date.
+ *
+ * The table uses 2 bits per block
+ * 11b:        block is good
+ * 00b:        block is factory marked bad
+ * 01b, 10b:   block is marked bad due to wear
+ *
+ * The memory bad block table uses the following scheme:
+ * 00b:                block is good
+ * 01b:                block is marked bad due to wear
+ * 10b:                block is reserved (to protect the bbt area)
+ * 11b:                block is factory marked bad
+ *
+ * Multichip devices like DOC store the bad block info per floor.
+ *
+ * Following assumptions are made:
+ * - bbts start at a page boundary, if autolocated on a block boundary
+ * - the space neccecary for a bbt in FLASH does not exceed a block boundary
+ *
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
+
+#include <malloc.h>
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+
+#include <asm/errno.h>
+
+/**
+ * check_pattern - [GENERIC] check if a pattern is in the buffer
+ * @buf:       the buffer to search
+ * @len:       the length of buffer to search
+ * @paglen:    the pagelength
+ * @td:                search pattern descriptor
+ *
+ * Check for a pattern at the given place. Used to search bad block
+ * tables and good / bad block identifiers.
+ * If the SCAN_EMPTY option is set then check, if all bytes except the
+ * pattern area contain 0xff
+ *
+*/
+static int check_pattern (uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td)
+{
+       int i, end;
+       uint8_t *p = buf;
+
+       end = paglen + td->offs;
+       if (td->options & NAND_BBT_SCANEMPTY) {
+               for (i = 0; i < end; i++) {
+                       if (p[i] != 0xff)
+                               return -1;
+               }
+       }
+       p += end;
+
+       /* Compare the pattern */
+       for (i = 0; i < td->len; i++) {
+               if (p[i] != td->pattern[i])
+                       return -1;
+       }
+
+       p += td->len;
+       end += td->len;
+       if (td->options & NAND_BBT_SCANEMPTY) {
+               for (i = end; i < len; i++) {
+                       if (*p++ != 0xff)
+                               return -1;
+               }
+       }
+       return 0;
+}
+
+/**
+ * read_bbt - [GENERIC] Read the bad block table starting from page
+ * @mtd:       MTD device structure
+ * @buf:       temporary buffer
+ * @page:      the starting page
+ * @num:       the number of bbt descriptors to read
+ * @bits:      number of bits per block
+ * @offs:      offset in the memory table
+ * @reserved_block_code:       Pattern to identify reserved blocks
+ *
+ * Read the bad block table starting from page.
+ *
+ */
+static int read_bbt (struct mtd_info *mtd, uint8_t *buf, int page, int num,
+       int bits, int offs, int reserved_block_code)
+{
+       int res, i, j, act = 0;
+       struct nand_chip *this = mtd->priv;
+       size_t retlen, len, totlen;
+       loff_t from;
+       uint8_t msk = (uint8_t) ((1 << bits) - 1);
+
+       totlen = (num * bits) >> 3;
+       from = ((loff_t)page) << this->page_shift;
+
+       while (totlen) {
+               len = min (totlen, (size_t) (1 << this->bbt_erase_shift));
+               res = mtd->read_ecc (mtd, from, len, &retlen, buf, NULL, this->autooob);
+               if (res < 0) {
+                       if (retlen != len) {
+                               printk (KERN_INFO "nand_bbt: Error reading bad block table\n");
+                               return res;
+                       }
+                       printk (KERN_WARNING "nand_bbt: ECC error while reading bad block table\n");
+               }
+
+               /* Analyse data */
+               for (i = 0; i < len; i++) {
+                       uint8_t dat = buf[i];
+                       for (j = 0; j < 8; j += bits, act += 2) {
+                               uint8_t tmp = (dat >> j) & msk;
+                               if (tmp == msk)
+                                       continue;
+                               if (reserved_block_code &&
+                                   (tmp == reserved_block_code)) {
+                                       printk (KERN_DEBUG "nand_read_bbt: Reserved block at 0x%08x\n",
+                                               ((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
+                                       this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06);
+                                       continue;
+                               }
+                               /* Leave it for now, if its matured we can move this
+                                * message to MTD_DEBUG_LEVEL0 */
+                               printk (KERN_DEBUG "nand_read_bbt: Bad block at 0x%08x\n",
+                                       ((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
+                               /* Factory marked bad or worn out ? */
+                               if (tmp == 0)
+                                       this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06);
+                               else
+                                       this->bbt[offs + (act >> 3)] |= 0x1 << (act & 0x06);
+                       }
+               }
+               totlen -= len;
+               from += len;
+       }
+       return 0;
+}
+
+/**
+ * read_abs_bbt - [GENERIC] Read the bad block table starting at a given page
+ * @mtd:       MTD device structure
+ * @buf:       temporary buffer
+ * @td:                descriptor for the bad block table
+ * @chip:      read the table for a specific chip, -1 read all chips.
+ *             Applies only if NAND_BBT_PERCHIP option is set
+ *
+ * Read the bad block table for all chips starting at a given page
+ * We assume that the bbt bits are in consecutive order.
+*/
+static int read_abs_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, int chip)
+{
+       struct nand_chip *this = mtd->priv;
+       int res = 0, i;
+       int bits;
+
+       bits = td->options & NAND_BBT_NRBITS_MSK;
+       if (td->options & NAND_BBT_PERCHIP) {
+               int offs = 0;
+               for (i = 0; i < this->numchips; i++) {
+                       if (chip == -1 || chip == i)
+                               res = read_bbt (mtd, buf, td->pages[i], this->chipsize >> this->bbt_erase_shift, bits, offs, td->reserved_block_code);
+                       if (res)
+                               return res;
+                       offs += this->chipsize >> (this->bbt_erase_shift + 2);
+               }
+       } else {
+               res = read_bbt (mtd, buf, td->pages[0], mtd->size >> this->bbt_erase_shift, bits, 0, td->reserved_block_code);
+               if (res)
+                       return res;
+       }
+       return 0;
+}
+
+/**
+ * read_abs_bbts - [GENERIC] Read the bad block table(s) for all chips starting at a given page
+ * @mtd:       MTD device structure
+ * @buf:       temporary buffer
+ * @td:                descriptor for the bad block table
+ * @md:                descriptor for the bad block table mirror
+ *
+ * Read the bad block table(s) for all chips starting at a given page
+ * We assume that the bbt bits are in consecutive order.
+ *
+*/
+static int read_abs_bbts (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td,
+       struct nand_bbt_descr *md)
+{
+       struct nand_chip *this = mtd->priv;
+
+       /* Read the primary version, if available */
+       if (td->options & NAND_BBT_VERSION) {
+               nand_read_raw (mtd, buf, td->pages[0] << this->page_shift, mtd->oobblock, mtd->oobsize);
+               td->version[0] = buf[mtd->oobblock + td->veroffs];
+               printk (KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", td->pages[0], td->version[0]);
+       }
+
+       /* Read the mirror version, if available */
+       if (md && (md->options & NAND_BBT_VERSION)) {
+               nand_read_raw (mtd, buf, md->pages[0] << this->page_shift, mtd->oobblock, mtd->oobsize);
+               md->version[0] = buf[mtd->oobblock + md->veroffs];
+               printk (KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", md->pages[0], md->version[0]);
+       }
+
+       return 1;
+}
+
+/**
+ * create_bbt - [GENERIC] Create a bad block table by scanning the device
+ * @mtd:       MTD device structure
+ * @buf:       temporary buffer
+ * @bd:                descriptor for the good/bad block search pattern
+ * @chip:      create the table for a specific chip, -1 read all chips.
+ *             Applies only if NAND_BBT_PERCHIP option is set
+ *
+ * Create a bad block table by scanning the device
+ * for the given good/bad block identify pattern
+ */
+static void create_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd, int chip)
+{
+       struct nand_chip *this = mtd->priv;
+       int i, j, numblocks, len, scanlen;
+       int startblock;
+       loff_t from;
+       size_t readlen, ooblen;
+
+       if (bd->options & NAND_BBT_SCANALLPAGES)
+               len = 1 << (this->bbt_erase_shift - this->page_shift);
+       else {
+               if (bd->options & NAND_BBT_SCAN2NDPAGE)
+                       len = 2;
+               else
+                       len = 1;
+       }
+       scanlen = mtd->oobblock + mtd->oobsize;
+       readlen = len * mtd->oobblock;
+       ooblen = len * mtd->oobsize;
+
+       if (chip == -1) {
+               /* Note that numblocks is 2 * (real numblocks) here, see i+=2 below as it
+                * makes shifting and masking less painful */
+               numblocks = mtd->size >> (this->bbt_erase_shift - 1);
+               startblock = 0;
+               from = 0;
+       } else {
+               if (chip >= this->numchips) {
+                       printk (KERN_WARNING "create_bbt(): chipnr (%d) > available chips (%d)\n",
+                               chip + 1, this->numchips);
+                       return;
+               }
+               numblocks = this->chipsize >> (this->bbt_erase_shift - 1);
+               startblock = chip * numblocks;
+               numblocks += startblock;
+               from = startblock << (this->bbt_erase_shift - 1);
+       }
+
+       for (i = startblock; i < numblocks;) {
+               nand_read_raw (mtd, buf, from, readlen, ooblen);
+               for (j = 0; j < len; j++) {
+                       if (check_pattern (&buf[j * scanlen], scanlen, mtd->oobblock, bd)) {
+                               this->bbt[i >> 3] |= 0x03 << (i & 0x6);
+                               break;
+                       }
+               }
+               i += 2;
+               from += (1 << this->bbt_erase_shift);
+       }
+}
+
+/**
+ * search_bbt - [GENERIC] scan the device for a specific bad block table
+ * @mtd:       MTD device structure
+ * @buf:       temporary buffer
+ * @td:                descriptor for the bad block table
+ *
+ * Read the bad block table by searching for a given ident pattern.
+ * Search is preformed either from the beginning up or from the end of
+ * the device downwards. The search starts always at the start of a
+ * block.
+ * If the option NAND_BBT_PERCHIP is given, each chip is searched
+ * for a bbt, which contains the bad block information of this chip.
+ * This is neccecary to provide support for certain DOC devices.
+ *
+ * The bbt ident pattern resides in the oob area of the first page
+ * in a block.
+ */
+static int search_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td)
+{
+       struct nand_chip *this = mtd->priv;
+       int i, chips;
+       int bits, startblock, block, dir;
+       int scanlen = mtd->oobblock + mtd->oobsize;
+       int bbtblocks;
+
+       /* Search direction top -> down ? */
+       if (td->options & NAND_BBT_LASTBLOCK) {
+               startblock = (mtd->size >> this->bbt_erase_shift) -1;
+               dir = -1;
+       } else {
+               startblock = 0;
+               dir = 1;
+       }
+
+       /* Do we have a bbt per chip ? */
+       if (td->options & NAND_BBT_PERCHIP) {
+               chips = this->numchips;
+               bbtblocks = this->chipsize >> this->bbt_erase_shift;
+               startblock &= bbtblocks - 1;
+       } else {
+               chips = 1;
+               bbtblocks = mtd->size >> this->bbt_erase_shift;
+       }
+
+       /* Number of bits for each erase block in the bbt */
+       bits = td->options & NAND_BBT_NRBITS_MSK;
+
+       for (i = 0; i < chips; i++) {
+               /* Reset version information */
+               td->version[i] = 0;
+               td->pages[i] = -1;
+               /* Scan the maximum number of blocks */
+               for (block = 0; block < td->maxblocks; block++) {
+                       int actblock = startblock + dir * block;
+                       /* Read first page */
+                       nand_read_raw (mtd, buf, actblock << this->bbt_erase_shift, mtd->oobblock, mtd->oobsize);
+                       if (!check_pattern(buf, scanlen, mtd->oobblock, td)) {
+                               td->pages[i] = actblock << (this->bbt_erase_shift - this->page_shift);
+                               if (td->options & NAND_BBT_VERSION) {
+                                       td->version[i] = buf[mtd->oobblock + td->veroffs];
+                               }
+                               break;
+                       }
+               }
+               startblock += this->chipsize >> this->bbt_erase_shift;
+       }
+       /* Check, if we found a bbt for each requested chip */
+       for (i = 0; i < chips; i++) {
+               if (td->pages[i] == -1)
+                       printk (KERN_WARNING "Bad block table not found for chip %d\n", i);
+               else
+                       printk (KERN_DEBUG "Bad block table found at page %d, version 0x%02X\n", td->pages[i], td->version[i]);
+       }
+       return 0;
+}
+
+/**
+ * search_read_bbts - [GENERIC] scan the device for bad block table(s)
+ * @mtd:       MTD device structure
+ * @buf:       temporary buffer
+ * @td:                descriptor for the bad block table
+ * @md:                descriptor for the bad block table mirror
+ *
+ * Search and read the bad block table(s)
+*/
+static int search_read_bbts (struct mtd_info *mtd, uint8_t *buf,
+       struct nand_bbt_descr *td, struct nand_bbt_descr *md)
+{
+       /* Search the primary table */
+       search_bbt (mtd, buf, td);
+
+       /* Search the mirror table */
+       if (md)
+               search_bbt (mtd, buf, md);
+
+       /* Force result check */
+       return 1;
+}
+
+
+/**
+ * write_bbt - [GENERIC] (Re)write the bad block table
+ *
+ * @mtd:       MTD device structure
+ * @buf:       temporary buffer
+ * @td:                descriptor for the bad block table
+ * @md:                descriptor for the bad block table mirror
+ * @chipsel:   selector for a specific chip, -1 for all
+ *
+ * (Re)write the bad block table
+ *
+*/
+static int write_bbt (struct mtd_info *mtd, uint8_t *buf,
+       struct nand_bbt_descr *td, struct nand_bbt_descr *md, int chipsel)
+{
+       struct nand_chip *this = mtd->priv;
+       struct nand_oobinfo oobinfo;
+       struct erase_info einfo;
+       int i, j, res, chip = 0;
+       int bits, startblock, dir, page, offs, numblocks, sft, sftmsk;
+       int nrchips, bbtoffs, pageoffs;
+       uint8_t msk[4];
+       uint8_t rcode = td->reserved_block_code;
+       size_t retlen, len = 0;
+       loff_t to;
+
+       if (!rcode)
+               rcode = 0xff;
+       /* Write bad block table per chip rather than per device ? */
+       if (td->options & NAND_BBT_PERCHIP) {
+               numblocks = (int) (this->chipsize >> this->bbt_erase_shift);
+               /* Full device write or specific chip ? */
+               if (chipsel == -1) {
+                       nrchips = this->numchips;
+               } else {
+                       nrchips = chipsel + 1;
+                       chip = chipsel;
+               }
+       } else {
+               numblocks = (int) (mtd->size >> this->bbt_erase_shift);
+               nrchips = 1;
+       }
+
+       /* Loop through the chips */
+       for (; chip < nrchips; chip++) {
+
+               /* There was already a version of the table, reuse the page
+                * This applies for absolute placement too, as we have the
+                * page nr. in td->pages.
+                */
+               if (td->pages[chip] != -1) {
+                       page = td->pages[chip];
+                       goto write;
+               }
+
+               /* Automatic placement of the bad block table */
+               /* Search direction top -> down ? */
+               if (td->options & NAND_BBT_LASTBLOCK) {
+                       startblock = numblocks * (chip + 1) - 1;
+                       dir = -1;
+               } else {
+                       startblock = chip * numblocks;
+                       dir = 1;
+               }
+
+               for (i = 0; i < td->maxblocks; i++) {
+                       int block = startblock + dir * i;
+                       /* Check, if the block is bad */
+                       switch ((this->bbt[block >> 2] >> (2 * (block & 0x03))) & 0x03) {
+                       case 0x01:
+                       case 0x03:
+                               continue;
+                       }
+                       page = block << (this->bbt_erase_shift - this->page_shift);
+                       /* Check, if the block is used by the mirror table */
+                       if (!md || md->pages[chip] != page)
+                               goto write;
+               }
+               printk (KERN_ERR "No space left to write bad block table\n");
+               return -ENOSPC;
+write:
+
+               /* Set up shift count and masks for the flash table */
+               bits = td->options & NAND_BBT_NRBITS_MSK;
+               switch (bits) {
+               case 1: sft = 3; sftmsk = 0x07; msk[0] = 0x00; msk[1] = 0x01; msk[2] = ~rcode; msk[3] = 0x01; break;
+               case 2: sft = 2; sftmsk = 0x06; msk[0] = 0x00; msk[1] = 0x01; msk[2] = ~rcode; msk[3] = 0x03; break;
+               case 4: sft = 1; sftmsk = 0x04; msk[0] = 0x00; msk[1] = 0x0C; msk[2] = ~rcode; msk[3] = 0x0f; break;
+               case 8: sft = 0; sftmsk = 0x00; msk[0] = 0x00; msk[1] = 0x0F; msk[2] = ~rcode; msk[3] = 0xff; break;
+               default: return -EINVAL;
+               }
+
+               bbtoffs = chip * (numblocks >> 2);
+
+               to = ((loff_t) page) << this->page_shift;
+
+               memcpy (&oobinfo, this->autooob, sizeof(oobinfo));
+               oobinfo.useecc = MTD_NANDECC_PLACEONLY;
+
+               /* Must we save the block contents ? */
+               if (td->options & NAND_BBT_SAVECONTENT) {
+                       /* Make it block aligned */
+                       to &= ~((loff_t) ((1 << this->bbt_erase_shift) - 1));
+                       len = 1 << this->bbt_erase_shift;
+                       res = mtd->read_ecc (mtd, to, len, &retlen, buf, &buf[len], &oobinfo);
+                       if (res < 0) {
+                               if (retlen != len) {
+                                       printk (KERN_INFO "nand_bbt: Error reading block for writing the bad block table\n");
+                                       return res;
+                               }
+                               printk (KERN_WARNING "nand_bbt: ECC error while reading block for writing bad block table\n");
+                       }
+                       /* Calc the byte offset in the buffer */
+                       pageoffs = page - (int)(to >> this->page_shift);
+                       offs = pageoffs << this->page_shift;
+                       /* Preset the bbt area with 0xff */
+                       memset (&buf[offs], 0xff, (size_t)(numblocks >> sft));
+                       /* Preset the bbt's oob area with 0xff */
+                       memset (&buf[len + pageoffs * mtd->oobsize], 0xff,
+                               ((len >> this->page_shift) - pageoffs) * mtd->oobsize);
+                       if (td->options & NAND_BBT_VERSION) {
+                               buf[len + (pageoffs * mtd->oobsize) + td->veroffs] = td->version[chip];
+                       }
+               } else {
+                       /* Calc length */
+                       len = (size_t) (numblocks >> sft);
+                       /* Make it page aligned ! */
+                       len = (len + (mtd->oobblock-1)) & ~(mtd->oobblock-1);
+                       /* Preset the buffer with 0xff */
+                       memset (buf, 0xff, len + (len >> this->page_shift) * mtd->oobsize);
+                       offs = 0;
+                       /* Pattern is located in oob area of first page */
+                       memcpy (&buf[len + td->offs], td->pattern, td->len);
+                       if (td->options & NAND_BBT_VERSION) {
+                               buf[len + td->veroffs] = td->version[chip];
+                       }
+               }
+
+               /* walk through the memory table */
+               for (i = 0; i < numblocks; ) {
+                       uint8_t dat;
+                       dat = this->bbt[bbtoffs + (i >> 2)];
+                       for (j = 0; j < 4; j++ , i++) {
+                               int sftcnt = (i << (3 - sft)) & sftmsk;
+                               /* Do not store the reserved bbt blocks ! */
+                               buf[offs + (i >> sft)] &= ~(msk[dat & 0x03] << sftcnt);
+                               dat >>= 2;
+                       }
+               }
+
+               memset (&einfo, 0, sizeof (einfo));
+               einfo.mtd = mtd;
+               einfo.addr = (unsigned long) to;
+               einfo.len = 1 << this->bbt_erase_shift;
+               res = nand_erase_nand (mtd, &einfo, 1);
+               if (res < 0) {
+                       printk (KERN_WARNING "nand_bbt: Error during block erase: %d\n", res);
+                       return res;
+               }
+
+               res = mtd->write_ecc (mtd, to, len, &retlen, buf, &buf[len], &oobinfo);
+               if (res < 0) {
+                       printk (KERN_WARNING "nand_bbt: Error while writing bad block table %d\n", res);
+                       return res;
+               }
+               printk (KERN_DEBUG "Bad block table written to 0x%08x, version 0x%02X\n",
+                       (unsigned int) to, td->version[chip]);
+
+               /* Mark it as used */
+               td->pages[chip] = page;
+       }
+       return 0;
+}
+
+/**
+ * nand_memory_bbt - [GENERIC] create a memory based bad block table
+ * @mtd:       MTD device structure
+ * @bd:                descriptor for the good/bad block search pattern
+ *
+ * The function creates a memory based bbt by scanning the device
+ * for manufacturer / software marked good / bad blocks
+*/
+static int nand_memory_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd)
+{
+       struct nand_chip *this = mtd->priv;
+
+       /* Ensure that we only scan for the pattern and nothing else */
+       bd->options = 0;
+       create_bbt (mtd, this->data_buf, bd, -1);
+       return 0;
+}
+
+/**
+ * check_create - [GENERIC] create and write bbt(s) if neccecary
+ * @mtd:       MTD device structure
+ * @buf:       temporary buffer
+ * @bd:                descriptor for the good/bad block search pattern
+ *
+ * The function checks the results of the previous call to read_bbt
+ * and creates / updates the bbt(s) if neccecary
+ * Creation is neccecary if no bbt was found for the chip/device
+ * Update is neccecary if one of the tables is missing or the
+ * version nr. of one table is less than the other
+*/
+static int check_create (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd)
+{
+       int i, chips, writeops, chipsel, res;
+       struct nand_chip *this = mtd->priv;
+       struct nand_bbt_descr *td = this->bbt_td;
+       struct nand_bbt_descr *md = this->bbt_md;
+       struct nand_bbt_descr *rd, *rd2;
+
+       /* Do we have a bbt per chip ? */
+       if (td->options & NAND_BBT_PERCHIP)
+               chips = this->numchips;
+       else
+               chips = 1;
+
+       for (i = 0; i < chips; i++) {
+               writeops = 0;
+               rd = NULL;
+               rd2 = NULL;
+               /* Per chip or per device ? */
+               chipsel = (td->options & NAND_BBT_PERCHIP) ? i : -1;
+               /* Mirrored table avilable ? */
+               if (md) {
+                       if (td->pages[i] == -1 && md->pages[i] == -1) {
+                               writeops = 0x03;
+                               goto create;
+                       }
+
+                       if (td->pages[i] == -1) {
+                               rd = md;
+                               td->version[i] = md->version[i];
+                               writeops = 1;
+                               goto writecheck;
+                       }
+
+                       if (md->pages[i] == -1) {
+                               rd = td;
+                               md->version[i] = td->version[i];
+                               writeops = 2;
+                               goto writecheck;
+                       }
+
+                       if (td->version[i] == md->version[i]) {
+                               rd = td;
+                               if (!(td->options & NAND_BBT_VERSION))
+                                       rd2 = md;
+                               goto writecheck;
+                       }
+
+                       if (((int8_t) (td->version[i] - md->version[i])) > 0) {
+                               rd = td;
+                               md->version[i] = td->version[i];
+                               writeops = 2;
+                       } else {
+                               rd = md;
+                               td->version[i] = md->version[i];
+                               writeops = 1;
+                       }
+
+                       goto writecheck;
+
+               } else {
+                       if (td->pages[i] == -1) {
+                               writeops = 0x01;
+                               goto create;
+                       }
+                       rd = td;
+                       goto writecheck;
+               }
+create:
+               /* Create the bad block table by scanning the device ? */
+               if (!(td->options & NAND_BBT_CREATE))
+                       continue;
+
+               /* Create the table in memory by scanning the chip(s) */
+               create_bbt (mtd, buf, bd, chipsel);
+
+               td->version[i] = 1;
+               if (md)
+                       md->version[i] = 1;
+writecheck:
+               /* read back first ? */
+               if (rd)
+                       read_abs_bbt (mtd, buf, rd, chipsel);
+               /* If they weren't versioned, read both. */
+               if (rd2)
+                       read_abs_bbt (mtd, buf, rd2, chipsel);
+
+               /* Write the bad block table to the device ? */
+               if ((writeops & 0x01) && (td->options & NAND_BBT_WRITE)) {
+                       res = write_bbt (mtd, buf, td, md, chipsel);
+                       if (res < 0)
+                               return res;
+               }
+
+               /* Write the mirror bad block table to the device ? */
+               if ((writeops & 0x02) && md && (md->options & NAND_BBT_WRITE)) {
+                       res = write_bbt (mtd, buf, md, td, chipsel);
+                       if (res < 0)
+                               return res;
+               }
+       }
+       return 0;
+}
+
+/**
+ * mark_bbt_regions - [GENERIC] mark the bad block table regions
+ * @mtd:       MTD device structure
+ * @td:                bad block table descriptor
+ *
+ * The bad block table regions are marked as "bad" to prevent
+ * accidental erasures / writes. The regions are identified by
+ * the mark 0x02.
+*/
+static void mark_bbt_region (struct mtd_info *mtd, struct nand_bbt_descr *td)
+{
+       struct nand_chip *this = mtd->priv;
+       int i, j, chips, block, nrblocks, update;
+       uint8_t oldval, newval;
+
+       /* Do we have a bbt per chip ? */
+       if (td->options & NAND_BBT_PERCHIP) {
+               chips = this->numchips;
+               nrblocks = (int)(this->chipsize >> this->bbt_erase_shift);
+       } else {
+               chips = 1;
+               nrblocks = (int)(mtd->size >> this->bbt_erase_shift);
+       }
+
+       for (i = 0; i < chips; i++) {
+               if ((td->options & NAND_BBT_ABSPAGE) ||
+                   !(td->options & NAND_BBT_WRITE)) {
+                       if (td->pages[i] == -1) continue;
+                       block = td->pages[i] >> (this->bbt_erase_shift - this->page_shift);
+                       block <<= 1;
+                       oldval = this->bbt[(block >> 3)];
+                       newval = oldval | (0x2 << (block & 0x06));
+                       this->bbt[(block >> 3)] = newval;
+                       if ((oldval != newval) && td->reserved_block_code)
+                               nand_update_bbt(mtd, block << (this->bbt_erase_shift - 1));
+                       continue;
+               }
+               update = 0;
+               if (td->options & NAND_BBT_LASTBLOCK)
+                       block = ((i + 1) * nrblocks) - td->maxblocks;
+               else
+                       block = i * nrblocks;
+               block <<= 1;
+               for (j = 0; j < td->maxblocks; j++) {
+                       oldval = this->bbt[(block >> 3)];
+                       newval = oldval | (0x2 << (block & 0x06));
+                       this->bbt[(block >> 3)] = newval;
+                       if (oldval != newval) update = 1;
+                       block += 2;
+               }
+               /* If we want reserved blocks to be recorded to flash, and some
+                  new ones have been marked, then we need to update the stored
+                  bbts.  This should only happen once. */
+               if (update && td->reserved_block_code)
+                       nand_update_bbt(mtd, (block - 2) << (this->bbt_erase_shift - 1));
+       }
+}
+
+/**
+ * nand_scan_bbt - [NAND Interface] scan, find, read and maybe create bad block table(s)
+ * @mtd:       MTD device structure
+ * @bd:                descriptor for the good/bad block search pattern
+ *
+ * The function checks, if a bad block table(s) is/are already
+ * available. If not it scans the device for manufacturer
+ * marked good / bad blocks and writes the bad block table(s) to
+ * the selected place.
+ *
+ * The bad block table memory is allocated here. It must be freed
+ * by calling the nand_free_bbt function.
+ *
+*/
+int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd)
+{
+       struct nand_chip *this = mtd->priv;
+       int len, res = 0;
+       uint8_t *buf;
+       struct nand_bbt_descr *td = this->bbt_td;
+       struct nand_bbt_descr *md = this->bbt_md;
+
+       len = mtd->size >> (this->bbt_erase_shift + 2);
+       /* Allocate memory (2bit per block) */
+       this->bbt = kmalloc (len, GFP_KERNEL);
+       if (!this->bbt) {
+               printk (KERN_ERR "nand_scan_bbt: Out of memory\n");
+               return -ENOMEM;
+       }
+       /* Clear the memory bad block table */
+       memset (this->bbt, 0x00, len);
+
+       /* If no primary table decriptor is given, scan the device
+        * to build a memory based bad block table
+        */
+       if (!td)
+               return nand_memory_bbt(mtd, bd);
+
+       /* Allocate a temporary buffer for one eraseblock incl. oob */
+       len = (1 << this->bbt_erase_shift);
+       len += (len >> this->page_shift) * mtd->oobsize;
+       buf = kmalloc (len, GFP_KERNEL);
+       if (!buf) {
+               printk (KERN_ERR "nand_bbt: Out of memory\n");
+               kfree (this->bbt);
+               this->bbt = NULL;
+               return -ENOMEM;
+       }
+
+       /* Is the bbt at a given page ? */
+       if (td->options & NAND_BBT_ABSPAGE) {
+               res = read_abs_bbts (mtd, buf, td, md);
+       } else {
+               /* Search the bad block table using a pattern in oob */
+               res = search_read_bbts (mtd, buf, td, md);
+       }
+
+       if (res)
+               res = check_create (mtd, buf, bd);
+
+       /* Prevent the bbt regions from erasing / writing */
+       mark_bbt_region (mtd, td);
+       if (md)
+               mark_bbt_region (mtd, md);
+
+       kfree (buf);
+       return res;
+}
+
+
+/**
+ * nand_update_bbt - [NAND Interface] update bad block table(s)
+ * @mtd:       MTD device structure
+ * @offs:      the offset of the newly marked block
+ *
+ * The function updates the bad block table(s)
+*/
+int nand_update_bbt (struct mtd_info *mtd, loff_t offs)
+{
+       struct nand_chip *this = mtd->priv;
+       int len, res = 0, writeops = 0;
+       int chip, chipsel;
+       uint8_t *buf;
+       struct nand_bbt_descr *td = this->bbt_td;
+       struct nand_bbt_descr *md = this->bbt_md;
+
+       if (!this->bbt || !td)
+               return -EINVAL;
+
+       len = mtd->size >> (this->bbt_erase_shift + 2);
+       /* Allocate a temporary buffer for one eraseblock incl. oob */
+       len = (1 << this->bbt_erase_shift);
+       len += (len >> this->page_shift) * mtd->oobsize;
+       buf = kmalloc (len, GFP_KERNEL);
+       if (!buf) {
+               printk (KERN_ERR "nand_update_bbt: Out of memory\n");
+               return -ENOMEM;
+       }
+
+       writeops = md != NULL ? 0x03 : 0x01;
+
+       /* Do we have a bbt per chip ? */
+       if (td->options & NAND_BBT_PERCHIP) {
+               chip = (int) (offs >> this->chip_shift);
+               chipsel = chip;
+       } else {
+               chip = 0;
+               chipsel = -1;
+       }
+
+       td->version[chip]++;
+       if (md)
+               md->version[chip]++;
+
+       /* Write the bad block table to the device ? */
+       if ((writeops & 0x01) && (td->options & NAND_BBT_WRITE)) {
+               res = write_bbt (mtd, buf, td, md, chipsel);
+               if (res < 0)
+                       goto out;
+       }
+       /* Write the mirror bad block table to the device ? */
+       if ((writeops & 0x02) && md && (md->options & NAND_BBT_WRITE)) {
+               res = write_bbt (mtd, buf, md, td, chipsel);
+       }
+
+out:
+       kfree (buf);
+       return res;
+}
+
+/* Define some generic bad / good block scan pattern which are used
+ * while scanning a device for factory marked good / bad blocks
+ *
+ * The memory based patterns just
+ */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr smallpage_memorybased = {
+       .options = 0,
+       .offs = 5,
+       .len = 1,
+       .pattern = scan_ff_pattern
+};
+
+static struct nand_bbt_descr largepage_memorybased = {
+       .options = 0,
+       .offs = 0,
+       .len = 2,
+       .pattern = scan_ff_pattern
+};
+
+static struct nand_bbt_descr smallpage_flashbased = {
+       .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
+       .offs = 5,
+       .len = 1,
+       .pattern = scan_ff_pattern
+};
+
+static struct nand_bbt_descr largepage_flashbased = {
+       .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
+       .offs = 0,
+       .len = 2,
+       .pattern = scan_ff_pattern
+};
+
+static uint8_t scan_agand_pattern[] = { 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7 };
+
+static struct nand_bbt_descr agand_flashbased = {
+       .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
+       .offs = 0x20,
+       .len = 6,
+       .pattern = scan_agand_pattern
+};
+
+/* Generic flash bbt decriptors
+*/
+static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
+static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+       .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+               | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+       .offs = 8,
+       .len = 4,
+       .veroffs = 12,
+       .maxblocks = 4,
+       .pattern = bbt_pattern
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+       .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+               | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+       .offs = 8,
+       .len = 4,
+       .veroffs = 12,
+       .maxblocks = 4,
+       .pattern = mirror_pattern
+};
+
+/**
+ * nand_default_bbt - [NAND Interface] Select a default bad block table for the device
+ * @mtd:       MTD device structure
+ *
+ * This function selects the default bad block table
+ * support for the device and calls the nand_scan_bbt function
+ *
+*/
+int nand_default_bbt (struct mtd_info *mtd)
+{
+       struct nand_chip *this = mtd->priv;
+
+       /* Default for AG-AND. We must use a flash based
+        * bad block table as the devices have factory marked
+        * _good_ blocks. Erasing those blocks leads to loss
+        * of the good / bad information, so we _must_ store
+        * this information in a good / bad table during
+        * startup
+       */
+       if (this->options & NAND_IS_AND) {
+               /* Use the default pattern descriptors */
+               if (!this->bbt_td) {
+                       this->bbt_td = &bbt_main_descr;
+                       this->bbt_md = &bbt_mirror_descr;
+               }
+               this->options |= NAND_USE_FLASH_BBT;
+               return nand_scan_bbt (mtd, &agand_flashbased);
+       }
+
+
+       /* Is a flash based bad block table requested ? */
+       if (this->options & NAND_USE_FLASH_BBT) {
+               /* Use the default pattern descriptors */
+               if (!this->bbt_td) {
+                       this->bbt_td = &bbt_main_descr;
+                       this->bbt_md = &bbt_mirror_descr;
+               }
+               if (!this->badblock_pattern) {
+                       this->badblock_pattern = (mtd->oobblock > 512) ?
+                               &largepage_flashbased : &smallpage_flashbased;
+               }
+       } else {
+               this->bbt_td = NULL;
+               this->bbt_md = NULL;
+               if (!this->badblock_pattern) {
+                       this->badblock_pattern = (mtd->oobblock > 512) ?
+                               &largepage_memorybased : &smallpage_memorybased;
+               }
+       }
+       return nand_scan_bbt (mtd, this->badblock_pattern);
+}
+
+/**
+ * nand_isbad_bbt - [NAND Interface] Check if a block is bad
+ * @mtd:       MTD device structure
+ * @offs:      offset in the device
+ * @allowbbt:  allow access to bad block table region
+ *
+ */
+int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt)
+{
+       struct nand_chip *this = mtd->priv;
+       int block;
+       uint8_t res;
+
+       /* Get block number * 2 */
+       block = (int) (offs >> (this->bbt_erase_shift - 1));
+       res = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03;
+
+       DEBUG (MTD_DEBUG_LEVEL2, "nand_isbad_bbt(): bbt info for offs 0x%08x: (block %d) 0x%02x\n",
+               (unsigned int)offs, res, block >> 1);
+
+       switch ((int)res) {
+       case 0x00:      return 0;
+       case 0x01:      return 1;
+       case 0x02:      return allowbbt ? 0 : 1;
+       }
+       return 1;
+}
+
+#endif

diff --git a/drivers/nand/nand_ecc.c b/drivers/nand/nand_ecc.c
new file mode 100644 (file)
index 0000000..f33be96
--- /dev/null
+++ b/drivers/nand/nand_ecc.c
@@ -0,0 +1,244 @@
+/*
+ * This file contains an ECC algorithm from Toshiba that detects and
+ * corrects 1 bit errors in a 256 byte block of data.
+ *
+ * drivers/mtd/nand/nand_ecc.c
+ *
+ * Copyright (C) 2000-2004 Steven J. Hill (sjhill@realitydiluted.com)
+ *                         Toshiba America Electronics Components, Inc.
+ *
+ * $Id: nand_ecc.c,v 1.14 2004/06/16 15:34:37 gleixner Exp $
+ *
+ * This file is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 or (at your option) any
+ * later version.
+ *
+ * This file is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this file; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * As a special exception, if other files instantiate templates or use
+ * macros or inline functions from these files, or you compile these
+ * files and link them with other works to produce a work based on these
+ * files, these files do not by themselves cause the resulting work to be
+ * covered by the GNU General Public License. However the source code for
+ * these files must still be made available in accordance with section (3)
+ * of the GNU General Public License.
+ *
+ * This exception does not invalidate any other reasons why a work based on
+ * this file might be covered by the GNU General Public License.
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
+
+#include<linux/mtd/mtd.h>
+/*
+ * Pre-calculated 256-way 1 byte column parity
+ */
+static const u_char nand_ecc_precalc_table[] = {
+       0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
+       0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
+       0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
+       0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
+       0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
+       0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
+       0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
+       0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
+       0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
+       0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
+       0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
+       0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
+       0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
+       0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
+       0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
+       0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
+};
+
+
+/**
+ * nand_trans_result - [GENERIC] create non-inverted ECC
+ * @reg2:      line parity reg 2
+ * @reg3:      line parity reg 3
+ * @ecc_code:  ecc
+ *
+ * Creates non-inverted ECC code from line parity
+ */
+static void nand_trans_result(u_char reg2, u_char reg3,
+       u_char *ecc_code)
+{
+       u_char a, b, i, tmp1, tmp2;
+
+       /* Initialize variables */
+       a = b = 0x80;
+       tmp1 = tmp2 = 0;
+
+       /* Calculate first ECC byte */
+       for (i = 0; i < 4; i++) {
+               if (reg3 & a)           /* LP15,13,11,9 --> ecc_code[0] */
+                       tmp1 |= b;
+               b >>= 1;
+               if (reg2 & a)           /* LP14,12,10,8 --> ecc_code[0] */
+                       tmp1 |= b;
+               b >>= 1;
+               a >>= 1;
+       }
+
+       /* Calculate second ECC byte */
+       b = 0x80;
+       for (i = 0; i < 4; i++) {
+               if (reg3 & a)           /* LP7,5,3,1 --> ecc_code[1] */
+                       tmp2 |= b;
+               b >>= 1;
+               if (reg2 & a)           /* LP6,4,2,0 --> ecc_code[1] */
+                       tmp2 |= b;
+               b >>= 1;
+               a >>= 1;
+       }
+
+       /* Store two of the ECC bytes */
+       ecc_code[0] = tmp1;
+       ecc_code[1] = tmp2;
+}
+
+/**
+ * nand_calculate_ecc - [NAND Interface] Calculate 3 byte ECC code for 256 byte block
+ * @mtd:       MTD block structure
+ * @dat:       raw data
+ * @ecc_code:  buffer for ECC
+ */
+int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
+{
+       u_char idx, reg1, reg2, reg3;
+       int j;
+
+       /* Initialize variables */
+       reg1 = reg2 = reg3 = 0;
+       ecc_code[0] = ecc_code[1] = ecc_code[2] = 0;
+
+       /* Build up column parity */
+       for(j = 0; j < 256; j++) {
+
+               /* Get CP0 - CP5 from table */
+               idx = nand_ecc_precalc_table[dat[j]];
+               reg1 ^= (idx & 0x3f);
+
+               /* All bit XOR = 1 ? */
+               if (idx & 0x40) {
+                       reg3 ^= (u_char) j;
+                       reg2 ^= ~((u_char) j);
+               }
+       }
+
+       /* Create non-inverted ECC code from line parity */
+       nand_trans_result(reg2, reg3, ecc_code);
+
+       /* Calculate final ECC code */
+       ecc_code[0] = ~ecc_code[0];
+       ecc_code[1] = ~ecc_code[1];
+       ecc_code[2] = ((~reg1) << 2) | 0x03;
+       return 0;
+}
+
+/**
+ * nand_correct_data - [NAND Interface] Detect and correct bit error(s)
+ * @mtd:       MTD block structure
+ * @dat:       raw data read from the chip
+ * @read_ecc:  ECC from the chip
+ * @calc_ecc:  the ECC calculated from raw data
+ *
+ * Detect and correct a 1 bit error for 256 byte block
+ */
+int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
+{
+       u_char a, b, c, d1, d2, d3, add, bit, i;
+
+       /* Do error detection */
+       d1 = calc_ecc[0] ^ read_ecc[0];
+       d2 = calc_ecc[1] ^ read_ecc[1];
+       d3 = calc_ecc[2] ^ read_ecc[2];
+
+       if ((d1 | d2 | d3) == 0) {
+               /* No errors */
+               return 0;
+       }
+       else {
+               a = (d1 ^ (d1 >> 1)) & 0x55;
+               b = (d2 ^ (d2 >> 1)) & 0x55;
+               c = (d3 ^ (d3 >> 1)) & 0x54;
+
+               /* Found and will correct single bit error in the data */
+               if ((a == 0x55) && (b == 0x55) && (c == 0x54)) {
+                       c = 0x80;
+                       add = 0;
+                       a = 0x80;
+                       for (i=0; i<4; i++) {
+                               if (d1 & c)
+                                       add |= a;
+                               c >>= 2;
+                               a >>= 1;
+                       }
+                       c = 0x80;
+                       for (i=0; i<4; i++) {
+                               if (d2 & c)
+                                       add |= a;
+                               c >>= 2;
+                               a >>= 1;
+                       }
+                       bit = 0;
+                       b = 0x04;
+                       c = 0x80;
+                       for (i=0; i<3; i++) {
+                               if (d3 & c)
+                                       bit |= b;
+                               c >>= 2;
+                               b >>= 1;
+                       }
+                       b = 0x01;
+                       a = dat[add];
+                       a ^= (b << bit);
+                       dat[add] = a;
+                       return 1;
+               } else {
+                       i = 0;
+                       while (d1) {
+                               if (d1 & 0x01)
+                                       ++i;
+                               d1 >>= 1;
+                       }
+                       while (d2) {
+                               if (d2 & 0x01)
+                                       ++i;
+                               d2 >>= 1;
+                       }
+                       while (d3) {
+                               if (d3 & 0x01)
+                                       ++i;
+                               d3 >>= 1;
+                       }
+                       if (i == 1) {
+                               /* ECC Code Error Correction */
+                               read_ecc[0] = calc_ecc[0];
+                               read_ecc[1] = calc_ecc[1];
+                               read_ecc[2] = calc_ecc[2];
+                               return 2;
+                       }
+                       else {
+                               /* Uncorrectable Error */
+                               return -1;
+                       }
+               }
+       }
+
+       /* Should never happen */
+       return -1;
+}
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */

diff --git a/drivers/nand/nand_ids.c b/drivers/nand/nand_ids.c
new file mode 100644 (file)
index 0000000..8b58736
--- /dev/null
+++ b/drivers/nand/nand_ids.c
@@ -0,0 +1,128 @@
+/*
+ *  drivers/mtd/nandids.c
+ *
+ *  Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
+  *
+ * $Id: nand_ids.c,v 1.10 2004/05/26 13:40:12 gleixner Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
+
+#include <linux/mtd/nand.h>
+
+/*
+*      Chip ID list
+*
+*      Name. ID code, pagesize, chipsize in MegaByte, eraseblock size,
+*      options
+*
+*      Pagesize; 0, 256, 512
+*      0       get this information from the extended chip ID
++      256     256 Byte page size
+*      512     512 Byte page size
+*/
+struct nand_flash_dev nand_flash_ids[] = {
+       {"NAND 1MiB 5V 8-bit",          0x6e, 256, 1, 0x1000, 0},
+       {"NAND 2MiB 5V 8-bit",          0x64, 256, 2, 0x1000, 0},
+       {"NAND 4MiB 5V 8-bit",          0x6b, 512, 4, 0x2000, 0},
+       {"NAND 1MiB 3,3V 8-bit",        0xe8, 256, 1, 0x1000, 0},
+       {"NAND 1MiB 3,3V 8-bit",        0xec, 256, 1, 0x1000, 0},
+       {"NAND 2MiB 3,3V 8-bit",        0xea, 256, 2, 0x1000, 0},
+       {"NAND 4MiB 3,3V 8-bit",        0xd5, 512, 4, 0x2000, 0},
+       {"NAND 4MiB 3,3V 8-bit",        0xe3, 512, 4, 0x2000, 0},
+       {"NAND 4MiB 3,3V 8-bit",        0xe5, 512, 4, 0x2000, 0},
+       {"NAND 8MiB 3,3V 8-bit",        0xd6, 512, 8, 0x2000, 0},
+
+       {"NAND 8MiB 1,8V 8-bit",        0x39, 512, 8, 0x2000, 0},
+       {"NAND 8MiB 3,3V 8-bit",        0xe6, 512, 8, 0x2000, 0},
+       {"NAND 8MiB 1,8V 16-bit",       0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
+       {"NAND 8MiB 3,3V 16-bit",       0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
+
+       {"NAND 16MiB 1,8V 8-bit",       0x33, 512, 16, 0x4000, 0},
+       {"NAND 16MiB 3,3V 8-bit",       0x73, 512, 16, 0x4000, 0},
+       {"NAND 16MiB 1,8V 16-bit",      0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
+       {"NAND 16MiB 3,3V 16-bit",      0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
+
+       {"NAND 32MiB 1,8V 8-bit",       0x35, 512, 32, 0x4000, 0},
+       {"NAND 32MiB 3,3V 8-bit",       0x75, 512, 32, 0x4000, 0},
+       {"NAND 32MiB 1,8V 16-bit",      0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
+       {"NAND 32MiB 3,3V 16-bit",      0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
+
+       {"NAND 64MiB 1,8V 8-bit",       0x36, 512, 64, 0x4000, 0},
+       {"NAND 64MiB 3,3V 8-bit",       0x76, 512, 64, 0x4000, 0},
+       {"NAND 64MiB 1,8V 16-bit",      0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
+       {"NAND 64MiB 3,3V 16-bit",      0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
+
+       {"NAND 128MiB 1,8V 8-bit",      0x78, 512, 128, 0x4000, 0},
+       {"NAND 128MiB 3,3V 8-bit",      0x79, 512, 128, 0x4000, 0},
+       {"NAND 128MiB 1,8V 16-bit",     0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
+       {"NAND 128MiB 3,3V 16-bit",     0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
+
+       {"NAND 256MiB 3,3V 8-bit",      0x71, 512, 256, 0x4000, 0},
+
+       {"NAND 512MiB 3,3V 8-bit",      0xDC, 512, 512, 0x4000, 0},
+
+       /* These are the new chips with large page size. The pagesize
+       * and the erasesize is determined from the extended id bytes
+       */
+       /* 1 Gigabit */
+       {"NAND 128MiB 1,8V 8-bit",      0xA1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+       {"NAND 128MiB 3,3V 8-bit",      0xF1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+       {"NAND 128MiB 1,8V 16-bit",     0xB1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+       {"NAND 128MiB 3,3V 16-bit",     0xC1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+
+       /* 2 Gigabit */
+       {"NAND 256MiB 1,8V 8-bit",      0xAA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+       {"NAND 256MiB 3,3V 8-bit",      0xDA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+       {"NAND 256MiB 1,8V 16-bit",     0xBA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+       {"NAND 256MiB 3,3V 16-bit",     0xCA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+
+       /* 4 Gigabit */
+       {"NAND 512MiB 1,8V 8-bit",      0xAC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+       {"NAND 512MiB 3,3V 8-bit",      0xDC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+       {"NAND 512MiB 1,8V 16-bit",     0xBC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+       {"NAND 512MiB 3,3V 16-bit",     0xCC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+
+       /* 8 Gigabit */
+       {"NAND 1GiB 1,8V 8-bit",        0xA3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+       {"NAND 1GiB 3,3V 8-bit",        0xD3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+       {"NAND 1GiB 1,8V 16-bit",       0xB3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+       {"NAND 1GiB 3,3V 16-bit",       0xC3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+
+       /* 16 Gigabit */
+       {"NAND 2GiB 1,8V 8-bit",        0xA5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+       {"NAND 2GiB 3,3V 8-bit",        0xD5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
+       {"NAND 2GiB 1,8V 16-bit",       0xB5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+       {"NAND 2GiB 3,3V 16-bit",       0xC5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+
+       /* Renesas AND 1 Gigabit. Those chips do not support extended id and have a strange page/block layout !
+        * The chosen minimum erasesize is 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page planes
+        * 1 block = 2 pages, but due to plane arrangement the blocks 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7
+        * Anyway JFFS2 would increase the eraseblock size so we chose a combined one which can be erased in one go
+        * There are more speed improvements for reads and writes possible, but not implemented now
+        */
+       {"AND 128MiB 3,3V 8-bit",       0x01, 2048, 128, 0x4000, NAND_IS_AND | NAND_NO_AUTOINCR | NAND_4PAGE_ARRAY},
+
+       {NULL,}
+};
+
+/*
+*      Manufacturer ID list
+*/
+struct nand_manufacturers nand_manuf_ids[] = {
+       {NAND_MFR_TOSHIBA, "Toshiba"},
+       {NAND_MFR_SAMSUNG, "Samsung"},
+       {NAND_MFR_FUJITSU, "Fujitsu"},
+       {NAND_MFR_NATIONAL, "National"},
+       {NAND_MFR_RENESAS, "Renesas"},
+       {NAND_MFR_STMICRO, "ST Micro"},
+       {0x0, "Unknown"}
+};
+#endif

diff --git a/drivers/nand_legacy/Makefile b/drivers/nand_legacy/Makefile
new file mode 100644 (file)
index 0000000..7e2cf66
--- /dev/null
+++ b/drivers/nand_legacy/Makefile
@@ -0,0 +1,16 @@
+include $(TOPDIR)/config.mk
+
+LIB := libnand_legacy.a
+
+OBJS := nand_legacy.o
+all:   $(LIB)
+
+$(LIB):        $(OBJS)
+       $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:       Makefile $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend

diff --git a/drivers/nand_legacy/nand_legacy.c b/drivers/nand_legacy/nand_legacy.c
new file mode 100644 (file)
index 0000000..458046d
--- /dev/null
+++ b/drivers/nand_legacy/nand_legacy.c
@@ -0,0 +1,1619 @@
+/*
+ * (C) 2006 Denx
+ * Driver for NAND support, Rick Bronson
+ * borrowed heavily from:
+ * (c) 1999 Machine Vision Holdings, Inc.
+ * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
+ *
+ * Added 16-bit nand support
+ * (C) 2004 Texas Instruments
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <watchdog.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+# define SHOW_BOOT_PROGRESS(arg)       show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+
+#include <linux/mtd/nand_legacy.h>
+#include <linux/mtd/nand_ids.h>
+#include <jffs2/jffs2.h>
+
+#ifdef CONFIG_OMAP1510
+void archflashwp(void *archdata, int wp);
+#endif
+
+#define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
+
+#undef PSYCHO_DEBUG
+#undef NAND_DEBUG
+
+/* ****************** WARNING *********************
+ * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will
+ * erase (or at least attempt to erase) blocks that are marked
+ * bad. This can be very handy if you are _sure_ that the block
+ * is OK, say because you marked a good block bad to test bad
+ * block handling and you are done testing, or if you have
+ * accidentally marked blocks bad.
+ *
+ * Erasing factory marked bad blocks is a _bad_ idea. If the
+ * erase succeeds there is no reliable way to find them again,
+ * and attempting to program or erase bad blocks can affect
+ * the data in _other_ (good) blocks.
+ */
+#define         ALLOW_ERASE_BAD_DEBUG 0
+
+#define CONFIG_MTD_NAND_ECC  /* enable ECC */
+#define CONFIG_MTD_NAND_ECC_JFFS2
+
+/* bits for nand_legacy_rw() `cmd'; or together as needed */
+#define NANDRW_READ    0x01
+#define NANDRW_WRITE   0x00
+#define NANDRW_JFFS2   0x02
+#define NANDRW_JFFS2_SKIP      0x04
+
+
+/*
+ * Exported variables etc.
+ */
+
+/* Definition of the out of band configuration structure */
+struct nand_oob_config {
+       /* position of ECC bytes inside oob */
+       int ecc_pos[6];
+       /* position of  bad blk flag inside oob -1 = inactive */
+       int badblock_pos;
+       /* position of ECC valid flag inside oob -1 = inactive */
+       int eccvalid_pos;
+} oob_config = { {0}, 0, 0};
+
+struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}};
+
+int curr_device = -1; /* Current NAND Device */
+
+
+/*
+ * Exported functionss
+ */
+int nand_legacy_erase(struct nand_chip* nand, size_t ofs,
+                    size_t len, int clean);
+int nand_legacy_rw(struct nand_chip* nand, int cmd,
+                 size_t start, size_t len,
+                 size_t * retlen, u_char * buf);
+void nand_print(struct nand_chip *nand);
+void nand_print_bad(struct nand_chip *nand);
+int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
+                size_t * retlen, u_char * buf);
+int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
+                size_t * retlen, const u_char * buf);
+
+/*
+ * Internals
+ */
+static int NanD_WaitReady(struct nand_chip *nand, int ale_wait);
+static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
+                size_t * retlen, u_char *buf, u_char *ecc_code);
+static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
+                          size_t * retlen, const u_char * buf,
+                          u_char * ecc_code);
+#ifdef CONFIG_MTD_NAND_ECC
+static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc);
+static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code);
+#endif
+
+
+/*
+ *
+ * Function definitions
+ *
+ */
+
+/* returns 0 if block containing pos is OK:
+ *             valid erase block and
+ *             not marked bad, or no bad mark position is specified
+ * returns 1 if marked bad or otherwise invalid
+ */
+static int check_block (struct nand_chip *nand, unsigned long pos)
+{
+       size_t retlen;
+       uint8_t oob_data;
+       uint16_t oob_data16[6];
+       int page0 = pos & (-nand->erasesize);
+       int page1 = page0 + nand->oobblock;
+       int badpos = oob_config.badblock_pos;
+
+       if (pos >= nand->totlen)
+               return 1;
+
+       if (badpos < 0)
+               return 0;       /* no way to check, assume OK */
+
+       if (nand->bus16) {
+               if (nand_read_oob(nand, (page0 + 0), 12, &retlen, (uint8_t *)oob_data16)
+                   || (oob_data16[2] & 0xff00) != 0xff00)
+                       return 1;
+               if (nand_read_oob(nand, (page1 + 0), 12, &retlen, (uint8_t *)oob_data16)
+                   || (oob_data16[2] & 0xff00) != 0xff00)
+                       return 1;
+       } else {
+               /* Note - bad block marker can be on first or second page */
+               if (nand_read_oob(nand, page0 + badpos, 1, &retlen, (unsigned char *)&oob_data)
+                   || oob_data != 0xff
+                   || nand_read_oob (nand, page1 + badpos, 1, &retlen, (unsigned char *)&oob_data)
+                   || oob_data != 0xff)
+                       return 1;
+       }
+
+       return 0;
+}
+
+/* print bad blocks in NAND flash */
+void nand_print_bad(struct nand_chip* nand)
+{
+       unsigned long pos;
+
+       for (pos = 0; pos < nand->totlen; pos += nand->erasesize) {
+               if (check_block(nand, pos))
+                       printf(" 0x%8.8lx\n", pos);
+       }
+       puts("\n");
+}
+
+/* cmd: 0: NANDRW_WRITE                        write, fail on bad block
+ *     1: NANDRW_READ                  read, fail on bad block
+ *     2: NANDRW_WRITE | NANDRW_JFFS2  write, skip bad blocks
+ *     3: NANDRW_READ | NANDRW_JFFS2   read, data all 0xff for bad blocks
+ *      7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks
+ */
+int nand_legacy_rw (struct nand_chip* nand, int cmd,
+                  size_t start, size_t len,
+                  size_t * retlen, u_char * buf)
+{
+       int ret = 0, n, total = 0;
+       char eccbuf[6];
+       /* eblk (once set) is the start of the erase block containing the
+        * data being processed.
+        */
+       unsigned long eblk = ~0;        /* force mismatch on first pass */
+       unsigned long erasesize = nand->erasesize;
+
+       while (len) {
+               if ((start & (-erasesize)) != eblk) {
+                       /* have crossed into new erase block, deal with
+                        * it if it is sure marked bad.
+                        */
+                       eblk = start & (-erasesize); /* start of block */
+                       if (check_block(nand, eblk)) {
+                               if (cmd == (NANDRW_READ | NANDRW_JFFS2)) {
+                                       while (len > 0 &&
+                                              start - eblk < erasesize) {
+                                               *(buf++) = 0xff;
+                                               ++start;
+                                               ++total;
+                                               --len;
+                                       }
+                                       continue;
+                               } else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) {
+                                       start += erasesize;
+                                       continue;
+                               } else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) {
+                                       /* skip bad block */
+                                       start += erasesize;
+                                       continue;
+                               } else {
+                                       ret = 1;
+                                       break;
+                               }
+                       }
+               }
+               /* The ECC will not be calculated correctly if
+                  less than 512 is written or read */
+               /* Is request at least 512 bytes AND it starts on a proper boundry */
+               if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200))
+                       printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n");
+
+               if (cmd & NANDRW_READ) {
+                       ret = nand_read_ecc(nand, start,
+                                          min(len, eblk + erasesize - start),
+                                          (size_t *)&n, (u_char*)buf, (u_char *)eccbuf);
+               } else {
+                       ret = nand_write_ecc(nand, start,
+                                           min(len, eblk + erasesize - start),
+                                           (size_t *)&n, (u_char*)buf, (u_char *)eccbuf);
+               }
+
+               if (ret)
+                       break;
+
+               start  += n;
+               buf   += n;
+               total += n;
+               len   -= n;
+       }
+       if (retlen)
+               *retlen = total;
+
+       return ret;
+}
+
+void nand_print(struct nand_chip *nand)
+{
+       if (nand->numchips > 1) {
+               printf("%s at 0x%lx,\n"
+                      "\t  %d chips %s, size %d MB, \n"
+                      "\t  total size %ld MB, sector size %ld kB\n",
+                      nand->name, nand->IO_ADDR, nand->numchips,
+                      nand->chips_name, 1 << (nand->chipshift - 20),
+                      nand->totlen >> 20, nand->erasesize >> 10);
+       }
+       else {
+               printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR);
+               print_size(nand->totlen, ", ");
+               print_size(nand->erasesize, " sector)\n");
+       }
+}
+
+/* ------------------------------------------------------------------------- */
+
+static int NanD_WaitReady(struct nand_chip *nand, int ale_wait)
+{
+       /* This is inline, to optimise the common case, where it's ready instantly */
+       int ret = 0;
+
+#ifdef NAND_NO_RB      /* in config file, shorter delays currently wrap accesses */
+       if(ale_wait)
+               NAND_WAIT_READY(nand);  /* do the worst case 25us wait */
+       else
+               udelay(10);
+#else  /* has functional r/b signal */
+       NAND_WAIT_READY(nand);
+#endif
+       return ret;
+}
+
+/* NanD_Command: Send a flash command to the flash chip */
+
+static inline int NanD_Command(struct nand_chip *nand, unsigned char command)
+{
+       unsigned long nandptr = nand->IO_ADDR;
+
+       /* Assert the CLE (Command Latch Enable) line to the flash chip */
+       NAND_CTL_SETCLE(nandptr);
+
+       /* Send the command */
+       WRITE_NAND_COMMAND(command, nandptr);
+
+       /* Lower the CLE line */
+       NAND_CTL_CLRCLE(nandptr);
+
+#ifdef NAND_NO_RB
+       if(command == NAND_CMD_RESET){
+               u_char ret_val;
+               NanD_Command(nand, NAND_CMD_STATUS);
+               do {
+                       ret_val = READ_NAND(nandptr);/* wait till ready */
+               } while((ret_val & 0x40) != 0x40);
+       }
+#endif
+       return NanD_WaitReady(nand, 0);
+}
+
+/* NanD_Address: Set the current address for the flash chip */
+
+static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs)
+{
+       unsigned long nandptr;
+       int i;
+
+       nandptr = nand->IO_ADDR;
+
+       /* Assert the ALE (Address Latch Enable) line to the flash chip */
+       NAND_CTL_SETALE(nandptr);
+
+       /* Send the address */
+       /* Devices with 256-byte page are addressed as:
+        * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31)
+        * there is no device on the market with page256
+        * and more than 24 bits.
+        * Devices with 512-byte page are addressed as:
+        * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31)
+        * 25-31 is sent only if the chip support it.
+        * bit 8 changes the read command to be sent
+        * (NAND_CMD_READ0 or NAND_CMD_READ1).
+        */
+
+       if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE)
+               WRITE_NAND_ADDRESS(ofs, nandptr);
+
+       ofs = ofs >> nand->page_shift;
+
+       if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) {
+               for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8) {
+                       WRITE_NAND_ADDRESS(ofs, nandptr);
+               }
+       }
+
+       /* Lower the ALE line */
+       NAND_CTL_CLRALE(nandptr);
+
+       /* Wait for the chip to respond */
+       return NanD_WaitReady(nand, 1);
+}
+
+/* NanD_SelectChip: Select a given flash chip within the current floor */
+
+static inline int NanD_SelectChip(struct nand_chip *nand, int chip)
+{
+       /* Wait for it to be ready */
+       return NanD_WaitReady(nand, 0);
+}
+
+/* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */
+
+static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip)
+{
+       int mfr, id, i;
+
+       NAND_ENABLE_CE(nand);  /* set pin low */
+       /* Reset the chip */
+       if (NanD_Command(nand, NAND_CMD_RESET)) {
+#ifdef NAND_DEBUG
+               printf("NanD_Command (reset) for %d,%d returned true\n",
+                      floor, chip);
+#endif
+               NAND_DISABLE_CE(nand);  /* set pin high */
+               return 0;
+       }
+
+       /* Read the NAND chip ID: 1. Send ReadID command */
+       if (NanD_Command(nand, NAND_CMD_READID)) {
+#ifdef NAND_DEBUG
+               printf("NanD_Command (ReadID) for %d,%d returned true\n",
+                      floor, chip);
+#endif
+               NAND_DISABLE_CE(nand);  /* set pin high */
+               return 0;
+       }
+
+       /* Read the NAND chip ID: 2. Send address byte zero */
+       NanD_Address(nand, ADDR_COLUMN, 0);
+
+       /* Read the manufacturer and device id codes from the device */
+
+       mfr = READ_NAND(nand->IO_ADDR);
+
+       id = READ_NAND(nand->IO_ADDR);
+
+       NAND_DISABLE_CE(nand);  /* set pin high */
+
+#ifdef NAND_DEBUG
+       printf("NanD_Command (ReadID) got %x %x\n", mfr, id);
+#endif
+       if (mfr == 0xff || mfr == 0) {
+               /* No response - return failure */
+               return 0;
+       }
+
+       /* Check it's the same as the first chip we identified.
+        * M-Systems say that any given nand_chip device should only
+        * contain _one_ type of flash part, although that's not a
+        * hardware restriction. */
+       if (nand->mfr) {
+               if (nand->mfr == mfr && nand->id == id) {
+                       return 1;       /* This is another the same the first */
+               } else {
+                       printf("Flash chip at floor %d, chip %d is different:\n",
+                              floor, chip);
+               }
+       }
+
+       /* Print and store the manufacturer and ID codes. */
+       for (i = 0; nand_flash_ids[i].name != NULL; i++) {
+               if (mfr == nand_flash_ids[i].manufacture_id &&
+                   id == nand_flash_ids[i].model_id) {
+#ifdef NAND_DEBUG
+                       printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, "
+                              "Chip ID: 0x%2.2X (%s)\n", mfr, id,
+                              nand_flash_ids[i].name);
+#endif
+                       if (!nand->mfr) {
+                               nand->mfr = mfr;
+                               nand->id = id;
+                               nand->chipshift =
+                                   nand_flash_ids[i].chipshift;
+                               nand->page256 = nand_flash_ids[i].page256;
+                               nand->eccsize = 256;
+                               if (nand->page256) {
+                                       nand->oobblock = 256;
+                                       nand->oobsize = 8;
+                                       nand->page_shift = 8;
+                               } else {
+                                       nand->oobblock = 512;
+                                       nand->oobsize = 16;
+                                       nand->page_shift = 9;
+                               }
+                               nand->pageadrlen = nand_flash_ids[i].pageadrlen;
+                               nand->erasesize  = nand_flash_ids[i].erasesize;
+                               nand->chips_name = nand_flash_ids[i].name;
+                               nand->bus16      = nand_flash_ids[i].bus16;
+                               return 1;
+                       }
+                       return 0;
+               }
+       }
+
+
+#ifdef NAND_DEBUG
+       /* We haven't fully identified the chip. Print as much as we know. */
+       printf("Unknown flash chip found: %2.2X %2.2X\n",
+              id, mfr);
+#endif
+
+       return 0;
+}
+
+/* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */
+
+static void NanD_ScanChips(struct nand_chip *nand)
+{
+       int floor, chip;
+       int numchips[NAND_MAX_FLOORS];
+       int maxchips = NAND_MAX_CHIPS;
+       int ret = 1;
+
+       nand->numchips = 0;
+       nand->mfr = 0;
+       nand->id = 0;
+
+
+       /* For each floor, find the number of valid chips it contains */
+       for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
+               ret = 1;
+               numchips[floor] = 0;
+               for (chip = 0; chip < maxchips && ret != 0; chip++) {
+
+                       ret = NanD_IdentChip(nand, floor, chip);
+                       if (ret) {
+                               numchips[floor]++;
+                               nand->numchips++;
+                       }
+               }
+       }
+
+       /* If there are none at all that we recognise, bail */
+       if (!nand->numchips) {
+#ifdef NAND_DEBUG
+               puts ("No NAND flash chips recognised.\n");
+#endif
+               return;
+       }
+
+       /* Allocate an array to hold the information for each chip */
+       nand->chips = malloc(sizeof(struct Nand) * nand->numchips);
+       if (!nand->chips) {
+               puts ("No memory for allocating chip info structures\n");
+               return;
+       }
+
+       ret = 0;
+
+       /* Fill out the chip array with {floor, chipno} for each
+        * detected chip in the device. */
+       for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
+               for (chip = 0; chip < numchips[floor]; chip++) {
+                       nand->chips[ret].floor = floor;
+                       nand->chips[ret].chip = chip;
+                       nand->chips[ret].curadr = 0;
+                       nand->chips[ret].curmode = 0x50;
+                       ret++;
+               }
+       }
+
+       /* Calculate and print the total size of the device */
+       nand->totlen = nand->numchips * (1 << nand->chipshift);
+
+#ifdef NAND_DEBUG
+       printf("%d flash chips found. Total nand_chip size: %ld MB\n",
+              nand->numchips, nand->totlen >> 20);
+#endif
+}
+
+/* we need to be fast here, 1 us per read translates to 1 second per meg */
+static void NanD_ReadBuf (struct nand_chip *nand, u_char * data_buf, int cntr)
+{
+       unsigned long nandptr = nand->IO_ADDR;
+
+       NanD_Command (nand, NAND_CMD_READ0);
+
+       if (nand->bus16) {
+               u16 val;
+
+               while (cntr >= 16) {
+                       val = READ_NAND (nandptr);
+                       *data_buf++ = val & 0xff;
+                       *data_buf++ = val >> 8;
+                       val = READ_NAND (nandptr);
+                       *data_buf++ = val & 0xff;
+                       *data_buf++ = val >> 8;
+                       val = READ_NAND (nandptr);
+                       *data_buf++ = val & 0xff;
+                       *data_buf++ = val >> 8;
+                       val = READ_NAND (nandptr);
+                       *data_buf++ = val & 0xff;
+                       *data_buf++ = val >> 8;
+                       val = READ_NAND (nandptr);
+                       *data_buf++ = val & 0xff;
+                       *data_buf++ = val >> 8;
+                       val = READ_NAND (nandptr);
+                       *data_buf++ = val & 0xff;
+                       *data_buf++ = val >> 8;
+                       val = READ_NAND (nandptr);
+                       *data_buf++ = val & 0xff;
+                       *data_buf++ = val >> 8;
+                       val = READ_NAND (nandptr);
+                       *data_buf++ = val & 0xff;
+                       *data_buf++ = val >> 8;
+                       cntr -= 16;
+               }
+
+               while (cntr > 0) {
+                       val = READ_NAND (nandptr);
+                       *data_buf++ = val & 0xff;
+                       *data_buf++ = val >> 8;
+                       cntr -= 2;
+               }
+       } else {
+               while (cntr >= 16) {
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       *data_buf++ = READ_NAND (nandptr);
+                       cntr -= 16;
+               }
+
+               while (cntr > 0) {
+                       *data_buf++ = READ_NAND (nandptr);
+                       cntr--;
+               }
+       }
+}
+
+/*
+ * NAND read with ECC
+ */
+static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
+                size_t * retlen, u_char *buf, u_char *ecc_code)
+{
+       int col, page;
+       int ecc_status = 0;
+#ifdef CONFIG_MTD_NAND_ECC
+       int j;
+       int ecc_failed = 0;
+       u_char *data_poi;
+       u_char ecc_calc[6];
+#endif
+
+       /* Do not allow reads past end of device */
+       if ((start + len) > nand->totlen) {
+               printf ("%s: Attempt read beyond end of device %x %x %x\n",
+                       __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen);
+               *retlen = 0;
+               return -1;
+       }
+
+       /* First we calculate the starting page */
+       /*page = shr(start, nand->page_shift);*/
+       page = start >> nand->page_shift;
+
+       /* Get raw starting column */
+       col = start & (nand->oobblock - 1);
+
+       /* Initialize return value */
+       *retlen = 0;
+
+       /* Select the NAND device */
+       NAND_ENABLE_CE(nand);  /* set pin low */
+
+       /* Loop until all data read */
+       while (*retlen < len) {
+
+#ifdef CONFIG_MTD_NAND_ECC
+               /* Do we have this page in cache ? */
+               if (nand->cache_page == page)
+                       goto readdata;
+               /* Send the read command */
+               NanD_Command(nand, NAND_CMD_READ0);
+               if (nand->bus16) {
+                       NanD_Address(nand, ADDR_COLUMN_PAGE,
+                                    (page << nand->page_shift) + (col >> 1));
+               } else {
+                       NanD_Address(nand, ADDR_COLUMN_PAGE,
+                                    (page << nand->page_shift) + col);
+               }
+
+               /* Read in a page + oob data */
+               NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize);
+
+               /* copy data into cache, for read out of cache and if ecc fails */
+               if (nand->data_cache) {
+                       memcpy (nand->data_cache, nand->data_buf,
+                               nand->oobblock + nand->oobsize);
+               }
+
+               /* Pick the ECC bytes out of the oob data */
+               for (j = 0; j < 6; j++) {
+                       ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])];
+               }
+
+               /* Calculate the ECC and verify it */
+               /* If block was not written with ECC, skip ECC */
+               if (oob_config.eccvalid_pos != -1 &&
+                   (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) {
+
+                       nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]);
+                       switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) {
+                       case -1:
+                               printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
+                               ecc_failed++;
+                               break;
+                       case 1:
+                       case 2: /* transfer ECC corrected data to cache */
+                               if (nand->data_cache)
+                                       memcpy (nand->data_cache, nand->data_buf, 256);
+                               break;
+                       }
+               }
+
+               if (oob_config.eccvalid_pos != -1 &&
+                   nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) {
+
+                       nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]);
+                       switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) {
+                       case -1:
+                               printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
+                               ecc_failed++;
+                               break;
+                       case 1:
+                       case 2: /* transfer ECC corrected data to cache */
+                               if (nand->data_cache)
+                                       memcpy (&nand->data_cache[256], &nand->data_buf[256], 256);
+                               break;
+                       }
+               }
+readdata:
+               /* Read the data from ECC data buffer into return buffer */
+               data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf;
+               data_poi += col;
+               if ((*retlen + (nand->oobblock - col)) >= len) {
+                       memcpy (buf + *retlen, data_poi, len - *retlen);
+                       *retlen = len;
+               } else {
+                       memcpy (buf + *retlen, data_poi,  nand->oobblock - col);
+                       *retlen += nand->oobblock - col;
+               }
+               /* Set cache page address, invalidate, if ecc_failed */
+               nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1;
+
+               ecc_status += ecc_failed;
+               ecc_failed = 0;
+
+#else
+               /* Send the read command */
+               NanD_Command(nand, NAND_CMD_READ0);
+               if (nand->bus16) {
+                       NanD_Address(nand, ADDR_COLUMN_PAGE,
+                                    (page << nand->page_shift) + (col >> 1));
+               } else {
+                       NanD_Address(nand, ADDR_COLUMN_PAGE,
+                                    (page << nand->page_shift) + col);
+               }
+
+               /* Read the data directly into the return buffer */
+               if ((*retlen + (nand->oobblock - col)) >= len) {
+                       NanD_ReadBuf(nand, buf + *retlen, len - *retlen);
+                       *retlen = len;
+                       /* We're done */
+                       continue;
+               } else {
+                       NanD_ReadBuf(nand, buf + *retlen, nand->oobblock - col);
+                       *retlen += nand->oobblock - col;
+                       }
+#endif
+               /* For subsequent reads align to page boundary. */
+               col = 0;
+               /* Increment page address */
+               page++;
+       }
+
+       /* De-select the NAND device */
+       NAND_DISABLE_CE(nand);  /* set pin high */
+
+       /*
+        * Return success, if no ECC failures, else -EIO
+        * fs driver will take care of that, because
+        * retlen == desired len and result == -EIO
+        */
+       return ecc_status ? -1 : 0;
+}
+
+/*
+ *     Nand_page_program function is used for write and writev !
+ */
+static int nand_write_page (struct nand_chip *nand,
+                           int page, int col, int last, u_char * ecc_code)
+{
+
+       int i;
+       unsigned long nandptr = nand->IO_ADDR;
+
+#ifdef CONFIG_MTD_NAND_ECC
+#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
+       int ecc_bytes = (nand->oobblock == 512) ? 6 : 3;
+#endif
+#endif
+       /* pad oob area */
+       for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++)
+               nand->data_buf[i] = 0xff;
+
+#ifdef CONFIG_MTD_NAND_ECC
+       /* Zero out the ECC array */
+       for (i = 0; i < 6; i++)
+               ecc_code[i] = 0x00;
+
+       /* Read back previous written data, if col > 0 */
+       if (col) {
+               NanD_Command (nand, NAND_CMD_READ0);
+               if (nand->bus16) {
+                       NanD_Address (nand, ADDR_COLUMN_PAGE,
+                                     (page << nand->page_shift) + (col >> 1));
+               } else {
+                       NanD_Address (nand, ADDR_COLUMN_PAGE,
+                                     (page << nand->page_shift) + col);
+               }
+
+               if (nand->bus16) {
+                       u16 val;
+
+                       for (i = 0; i < col; i += 2) {
+                               val = READ_NAND (nandptr);
+                               nand->data_buf[i] = val & 0xff;
+                               nand->data_buf[i + 1] = val >> 8;
+                       }
+               } else {
+                       for (i = 0; i < col; i++)
+                               nand->data_buf[i] = READ_NAND (nandptr);
+               }
+       }
+
+       /* Calculate and write the ECC if we have enough data */
+       if ((col < nand->eccsize) && (last >= nand->eccsize)) {
+               nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0]));
+               for (i = 0; i < 3; i++) {
+                       nand->data_buf[(nand->oobblock +
+                                       oob_config.ecc_pos[i])] = ecc_code[i];
+               }
+               if (oob_config.eccvalid_pos != -1) {
+                       nand->data_buf[nand->oobblock +
+                                      oob_config.eccvalid_pos] = 0xf0;
+               }
+       }
+
+       /* Calculate and write the second ECC if we have enough data */
+       if ((nand->oobblock == 512) && (last == nand->oobblock)) {
+               nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3]));
+               for (i = 3; i < 6; i++) {
+                       nand->data_buf[(nand->oobblock +
+                                       oob_config.ecc_pos[i])] = ecc_code[i];
+               }
+               if (oob_config.eccvalid_pos != -1) {
+                       nand->data_buf[nand->oobblock +
+                                      oob_config.eccvalid_pos] &= 0x0f;
+               }
+       }
+#endif
+       /* Prepad for partial page programming !!! */
+       for (i = 0; i < col; i++)
+               nand->data_buf[i] = 0xff;
+
+       /* Postpad for partial page programming !!! oob is already padded */
+       for (i = last; i < nand->oobblock; i++)
+               nand->data_buf[i] = 0xff;
+
+       /* Send command to begin auto page programming */
+       NanD_Command (nand, NAND_CMD_READ0);
+       NanD_Command (nand, NAND_CMD_SEQIN);
+       if (nand->bus16) {
+               NanD_Address (nand, ADDR_COLUMN_PAGE,
+                             (page << nand->page_shift) + (col >> 1));
+       } else {
+               NanD_Address (nand, ADDR_COLUMN_PAGE,
+                             (page << nand->page_shift) + col);
+       }
+
+       /* Write out complete page of data */
+       if (nand->bus16) {
+               for (i = 0; i < (nand->oobblock + nand->oobsize); i += 2) {
+                       WRITE_NAND (nand->data_buf[i] +
+                                   (nand->data_buf[i + 1] << 8),
+                                   nand->IO_ADDR);
+               }
+       } else {
+               for (i = 0; i < (nand->oobblock + nand->oobsize); i++)
+                       WRITE_NAND (nand->data_buf[i], nand->IO_ADDR);
+       }
+
+       /* Send command to actually program the data */
+       NanD_Command (nand, NAND_CMD_PAGEPROG);
+       NanD_Command (nand, NAND_CMD_STATUS);
+#ifdef NAND_NO_RB
+       {
+               u_char ret_val;
+
+               do {
+                       ret_val = READ_NAND (nandptr);  /* wait till ready */
+               } while ((ret_val & 0x40) != 0x40);
+       }
+#endif
+       /* See if device thinks it succeeded */
+       if (READ_NAND (nand->IO_ADDR) & 0x01) {
+               printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__,
+                       page);
+               return -1;
+       }
+#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
+       /*
+        * The NAND device assumes that it is always writing to
+        * a cleanly erased page. Hence, it performs its internal
+        * write verification only on bits that transitioned from
+        * 1 to 0. The device does NOT verify the whole page on a
+        * byte by byte basis. It is possible that the page was
+        * not completely erased or the page is becoming unusable
+        * due to wear. The read with ECC would catch the error
+        * later when the ECC page check fails, but we would rather
+        * catch it early in the page write stage. Better to write
+        * no data than invalid data.
+        */
+
+       /* Send command to read back the page */
+       if (col < nand->eccsize)
+               NanD_Command (nand, NAND_CMD_READ0);
+       else
+               NanD_Command (nand, NAND_CMD_READ1);
+       if (nand->bus16) {
+               NanD_Address (nand, ADDR_COLUMN_PAGE,
+                             (page << nand->page_shift) + (col >> 1));
+       } else {
+               NanD_Address (nand, ADDR_COLUMN_PAGE,
+                             (page << nand->page_shift) + col);
+       }
+
+       /* Loop through and verify the data */
+       if (nand->bus16) {
+               for (i = col; i < last; i = +2) {
+                       if ((nand->data_buf[i] +
+                            (nand->data_buf[i + 1] << 8)) != READ_NAND (nand->IO_ADDR)) {
+                               printf ("%s: Failed write verify, page 0x%08x ",
+                                       __FUNCTION__, page);
+                               return -1;
+                       }
+               }
+       } else {
+               for (i = col; i < last; i++) {
+                       if (nand->data_buf[i] != READ_NAND (nand->IO_ADDR)) {
+                               printf ("%s: Failed write verify, page 0x%08x ",
+                                       __FUNCTION__, page);
+                               return -1;
+                       }
+               }
+       }
+
+#ifdef CONFIG_MTD_NAND_ECC
+       /*
+        * We also want to check that the ECC bytes wrote
+        * correctly for the same reasons stated above.
+        */
+       NanD_Command (nand, NAND_CMD_READOOB);
+       if (nand->bus16) {
+               NanD_Address (nand, ADDR_COLUMN_PAGE,
+                             (page << nand->page_shift) + (col >> 1));
+       } else {
+               NanD_Address (nand, ADDR_COLUMN_PAGE,
+                             (page << nand->page_shift) + col);
+       }
+       if (nand->bus16) {
+               for (i = 0; i < nand->oobsize; i += 2) {
+                       u16 val;
+
+                       val = READ_NAND (nand->IO_ADDR);
+                       nand->data_buf[i] = val & 0xff;
+                       nand->data_buf[i + 1] = val >> 8;
+               }
+       } else {
+               for (i = 0; i < nand->oobsize; i++) {
+                       nand->data_buf[i] = READ_NAND (nand->IO_ADDR);
+               }
+       }
+       for (i = 0; i < ecc_bytes; i++) {
+               if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) {
+                       printf ("%s: Failed ECC write "
+                               "verify, page 0x%08x, "
+                               "%6i bytes were succesful\n",
+                               __FUNCTION__, page, i);
+                       return -1;
+               }
+       }
+#endif /* CONFIG_MTD_NAND_ECC */
+#endif /* CONFIG_MTD_NAND_VERIFY_WRITE */
+       return 0;
+}
+
+static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
+                          size_t * retlen, const u_char * buf, u_char * ecc_code)
+{
+       int i, page, col, cnt, ret = 0;
+
+       /* Do not allow write past end of device */
+       if ((to + len) > nand->totlen) {
+               printf ("%s: Attempt to write past end of page\n", __FUNCTION__);
+               return -1;
+       }
+
+       /* Shift to get page */
+       page = ((int) to) >> nand->page_shift;
+
+       /* Get the starting column */
+       col = to & (nand->oobblock - 1);
+
+       /* Initialize return length value */
+       *retlen = 0;
+
+       /* Select the NAND device */
+#ifdef CONFIG_OMAP1510
+       archflashwp(0,0);
+#endif
+#ifdef CFG_NAND_WP
+       NAND_WP_OFF();
+#endif
+
+       NAND_ENABLE_CE(nand);  /* set pin low */
+
+       /* Check the WP bit */
+       NanD_Command(nand, NAND_CMD_STATUS);
+       if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
+               printf ("%s: Device is write protected!!!\n", __FUNCTION__);
+               ret = -1;
+               goto out;
+       }
+
+       /* Loop until all data is written */
+       while (*retlen < len) {
+               /* Invalidate cache, if we write to this page */
+               if (nand->cache_page == page)
+                       nand->cache_page = -1;
+
+               /* Write data into buffer */
+               if ((col + len) >= nand->oobblock) {
+                       for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++) {
+                               nand->data_buf[i] = buf[(*retlen + cnt)];
+                       }
+               } else {
+                       for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++) {
+                               nand->data_buf[i] = buf[(*retlen + cnt)];
+                       }
+               }
+               /* We use the same function for write and writev !) */
+               ret = nand_write_page (nand, page, col, i, ecc_code);
+               if (ret)
+                       goto out;
+
+               /* Next data start at page boundary */
+               col = 0;
+
+               /* Update written bytes count */
+               *retlen += cnt;
+
+               /* Increment page address */
+               page++;
+       }
+
+       /* Return happy */
+       *retlen = len;
+
+out:
+       /* De-select the NAND device */
+       NAND_DISABLE_CE(nand);  /* set pin high */
+#ifdef CONFIG_OMAP1510
+       archflashwp(0,1);
+#endif
+#ifdef CFG_NAND_WP
+       NAND_WP_ON();
+#endif
+
+       return ret;
+}
+
+/* read from the 16 bytes of oob data that correspond to a 512 byte
+ * page or 2 256-byte pages.
+ */
+int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
+                        size_t * retlen, u_char * buf)
+{
+       int len256 = 0;
+       struct Nand *mychip;
+       int ret = 0;
+
+       mychip = &nand->chips[ofs >> nand->chipshift];
+
+       /* update address for 2M x 8bit devices. OOB starts on the second */
+       /* page to maintain compatibility with nand_read_ecc. */
+       if (nand->page256) {
+               if (!(ofs & 0x8))
+                       ofs += 0x100;
+               else
+                       ofs -= 0x8;
+       }
+
+       NAND_ENABLE_CE(nand);  /* set pin low */
+       NanD_Command(nand, NAND_CMD_READOOB);
+       if (nand->bus16) {
+               NanD_Address(nand, ADDR_COLUMN_PAGE,
+                            ((ofs >> nand->page_shift) << nand->page_shift) +
+                               ((ofs & (nand->oobblock - 1)) >> 1));
+       } else {
+               NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
+       }
+
+       /* treat crossing 8-byte OOB data for 2M x 8bit devices */
+       /* Note: datasheet says it should automaticaly wrap to the */
+       /*       next OOB block, but it didn't work here. mf.      */
+       if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
+               len256 = (ofs | 0x7) + 1 - ofs;
+               NanD_ReadBuf(nand, buf, len256);
+
+               NanD_Command(nand, NAND_CMD_READOOB);
+               NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
+       }
+
+       NanD_ReadBuf(nand, &buf[len256], len - len256);
+
+       *retlen = len;
+       /* Reading the full OOB data drops us off of the end of the page,
+        * causing the flash device to go into busy mode, so we need
+        * to wait until ready 11.4.1 and Toshiba TC58256FT nands */
+
+       ret = NanD_WaitReady(nand, 1);
+       NAND_DISABLE_CE(nand);  /* set pin high */
+
+       return ret;
+
+}
+
+/* write to the 16 bytes of oob data that correspond to a 512 byte
+ * page or 2 256-byte pages.
+ */
+int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
+                 size_t * retlen, const u_char * buf)
+{
+       int len256 = 0;
+       int i;
+       unsigned long nandptr = nand->IO_ADDR;
+
+#ifdef PSYCHO_DEBUG
+       printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n",
+              (long)ofs, len, buf[0], buf[1], buf[2], buf[3],
+              buf[8], buf[9], buf[14],buf[15]);
+#endif
+
+       NAND_ENABLE_CE(nand);  /* set pin low to enable chip */
+
+       /* Reset the chip */
+       NanD_Command(nand, NAND_CMD_RESET);
+
+       /* issue the Read2 command to set the pointer to the Spare Data Area. */
+       NanD_Command(nand, NAND_CMD_READOOB);
+       if (nand->bus16) {
+               NanD_Address(nand, ADDR_COLUMN_PAGE,
+                            ((ofs >> nand->page_shift) << nand->page_shift) +
+                               ((ofs & (nand->oobblock - 1)) >> 1));
+       } else {
+               NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
+       }
+
+       /* update address for 2M x 8bit devices. OOB starts on the second */
+       /* page to maintain compatibility with nand_read_ecc. */
+       if (nand->page256) {
+               if (!(ofs & 0x8))
+                       ofs += 0x100;
+               else
+                       ofs -= 0x8;
+       }
+
+       /* issue the Serial Data In command to initial the Page Program process */
+       NanD_Command(nand, NAND_CMD_SEQIN);
+       if (nand->bus16) {
+               NanD_Address(nand, ADDR_COLUMN_PAGE,
+                            ((ofs >> nand->page_shift) << nand->page_shift) +
+                               ((ofs & (nand->oobblock - 1)) >> 1));
+       } else {
+               NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
+       }
+
+       /* treat crossing 8-byte OOB data for 2M x 8bit devices */
+       /* Note: datasheet says it should automaticaly wrap to the */
+       /*       next OOB block, but it didn't work here. mf.      */
+       if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
+               len256 = (ofs | 0x7) + 1 - ofs;
+               for (i = 0; i < len256; i++)
+                       WRITE_NAND(buf[i], nandptr);
+
+               NanD_Command(nand, NAND_CMD_PAGEPROG);
+               NanD_Command(nand, NAND_CMD_STATUS);
+#ifdef NAND_NO_RB
+               { u_char ret_val;
+                       do {
+                               ret_val = READ_NAND(nandptr); /* wait till ready */
+                       } while ((ret_val & 0x40) != 0x40);
+               }
+#endif
+               if (READ_NAND(nandptr) & 1) {
+                       puts ("Error programming oob data\n");
+                       /* There was an error */
+                       NAND_DISABLE_CE(nand);  /* set pin high */
+                       *retlen = 0;
+                       return -1;
+               }
+               NanD_Command(nand, NAND_CMD_SEQIN);
+               NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
+       }
+
+       if (nand->bus16) {
+               for (i = len256; i < len; i += 2) {
+                       WRITE_NAND(buf[i] + (buf[i+1] << 8), nandptr);
+               }
+       } else {
+               for (i = len256; i < len; i++)
+                       WRITE_NAND(buf[i], nandptr);
+       }
+
+       NanD_Command(nand, NAND_CMD_PAGEPROG);
+       NanD_Command(nand, NAND_CMD_STATUS);
+#ifdef NAND_NO_RB
+       {       u_char ret_val;
+               do {
+                       ret_val = READ_NAND(nandptr); /* wait till ready */
+               } while ((ret_val & 0x40) != 0x40);
+       }
+#endif
+       if (READ_NAND(nandptr) & 1) {
+               puts ("Error programming oob data\n");
+               /* There was an error */
+               NAND_DISABLE_CE(nand);  /* set pin high */
+               *retlen = 0;
+               return -1;
+       }
+
+       NAND_DISABLE_CE(nand);  /* set pin high */
+       *retlen = len;
+       return 0;
+
+}
+
+int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean)
+{
+       /* This is defined as a structure so it will work on any system
+        * using native endian jffs2 (the default).
+        */
+       static struct jffs2_unknown_node clean_marker = {
+               JFFS2_MAGIC_BITMASK,
+               JFFS2_NODETYPE_CLEANMARKER,
+               8               /* 8 bytes in this node */
+       };
+       unsigned long nandptr;
+       struct Nand *mychip;
+       int ret = 0;
+
+       if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) {
+               printf ("Offset and size must be sector aligned, erasesize = %d\n",
+                       (int) nand->erasesize);
+               return -1;
+       }
+
+       nandptr = nand->IO_ADDR;
+
+       /* Select the NAND device */
+#ifdef CONFIG_OMAP1510
+       archflashwp(0,0);
+#endif
+#ifdef CFG_NAND_WP
+       NAND_WP_OFF();
+#endif
+    NAND_ENABLE_CE(nand);  /* set pin low */
+
+       /* Check the WP bit */
+       NanD_Command(nand, NAND_CMD_STATUS);
+       if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
+               printf ("nand_write_ecc: Device is write protected!!!\n");
+               ret = -1;
+               goto out;
+       }
+
+       /* Check the WP bit */
+       NanD_Command(nand, NAND_CMD_STATUS);
+       if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
+               printf ("%s: Device is write protected!!!\n", __FUNCTION__);
+               ret = -1;
+               goto out;
+       }
+
+       /* FIXME: Do nand in the background. Use timers or schedule_task() */
+       while(len) {
+               /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/
+               mychip = &nand->chips[ofs >> nand->chipshift];
+
+               /* always check for bad block first, genuine bad blocks
+                * should _never_  be erased.
+                */
+               if (ALLOW_ERASE_BAD_DEBUG || !check_block(nand, ofs)) {
+                       /* Select the NAND device */
+                       NAND_ENABLE_CE(nand);  /* set pin low */
+
+                       NanD_Command(nand, NAND_CMD_ERASE1);
+                       NanD_Address(nand, ADDR_PAGE, ofs);
+                       NanD_Command(nand, NAND_CMD_ERASE2);
+
+                       NanD_Command(nand, NAND_CMD_STATUS);
+
+#ifdef NAND_NO_RB
+                       {       u_char ret_val;
+                               do {
+                                       ret_val = READ_NAND(nandptr); /* wait till ready */
+                               } while ((ret_val & 0x40) != 0x40);
+                       }
+#endif
+                       if (READ_NAND(nandptr) & 1) {
+                               printf ("%s: Error erasing at 0x%lx\n",
+                                       __FUNCTION__, (long)ofs);
+                               /* There was an error */
+                               ret = -1;
+                               goto out;
+                       }
+                       if (clean) {
+                               int n;  /* return value not used */
+                               int p, l;
+
+                               /* clean marker position and size depend
+                                * on the page size, since 256 byte pages
+                                * only have 8 bytes of oob data
+                                */
+                               if (nand->page256) {
+                                       p = NAND_JFFS2_OOB8_FSDAPOS;
+                                       l = NAND_JFFS2_OOB8_FSDALEN;
+                               } else {
+                                       p = NAND_JFFS2_OOB16_FSDAPOS;
+                                       l = NAND_JFFS2_OOB16_FSDALEN;
+                               }
+
+                               ret = nand_write_oob(nand, ofs + p, l, (size_t *)&n,
+                                                    (u_char *)&clean_marker);
+                               /* quit here if write failed */
+                               if (ret)
+                                       goto out;
+                       }
+               }
+               ofs += nand->erasesize;
+               len -= nand->erasesize;
+       }
+
+out:
+       /* De-select the NAND device */
+       NAND_DISABLE_CE(nand);  /* set pin high */
+#ifdef CONFIG_OMAP1510
+       archflashwp(0,1);
+#endif
+#ifdef CFG_NAND_WP
+       NAND_WP_ON();
+#endif
+
+       return ret;
+}
+
+
+static inline int nandcheck(unsigned long potential, unsigned long physadr)
+{
+       return 0;
+}
+
+unsigned long nand_probe(unsigned long physadr)
+{
+       struct nand_chip *nand = NULL;
+       int i = 0, ChipID = 1;
+
+#ifdef CONFIG_MTD_NAND_ECC_JFFS2
+       oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0;
+       oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1;
+       oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2;
+       oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3;
+       oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4;
+       oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5;
+       oob_config.eccvalid_pos = 4;
+#else
+       oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0;
+       oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1;
+       oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2;
+       oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3;
+       oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4;
+       oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5;
+       oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS;
+#endif
+       oob_config.badblock_pos = 5;
+
+       for (i=0; i<CFG_MAX_NAND_DEVICE; i++) {
+               if (nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) {
+                       nand = &nand_dev_desc[i];
+                       break;
+               }
+       }
+       if (!nand)
+               return (0);
+
+       memset((char *)nand, 0, sizeof(struct nand_chip));
+
+       nand->IO_ADDR = physadr;
+       nand->cache_page = -1;  /* init the cache page */
+       NanD_ScanChips(nand);
+
+       if (nand->totlen == 0) {
+               /* no chips found, clean up and quit */
+               memset((char *)nand, 0, sizeof(struct nand_chip));
+               nand->ChipID = NAND_ChipID_UNKNOWN;
+               return (0);
+       }
+
+       nand->ChipID = ChipID;
+       if (curr_device == -1)
+               curr_device = i;
+
+       nand->data_buf = malloc (nand->oobblock + nand->oobsize);
+       if (!nand->data_buf) {
+               puts ("Cannot allocate memory for data structures.\n");
+               return (0);
+       }
+
+       return (nand->totlen);
+}
+
+#ifdef CONFIG_MTD_NAND_ECC
+/*
+ * Pre-calculated 256-way 1 byte column parity
+ */
+static const u_char nand_ecc_precalc_table[] = {
+       0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a,
+       0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
+       0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f,
+       0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
+       0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c,
+       0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
+       0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59,
+       0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
+       0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33,
+       0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
+       0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56,
+       0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
+       0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55,
+       0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
+       0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30,
+       0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
+       0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30,
+       0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
+       0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55,
+       0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
+       0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56,
+       0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
+       0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33,
+       0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
+       0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59,
+       0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
+       0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c,
+       0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
+       0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f,
+       0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
+       0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a,
+       0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
+};
+
+
+/*
+ * Creates non-inverted ECC code from line parity
+ */
+static void nand_trans_result(u_char reg2, u_char reg3,
+       u_char *ecc_code)
+{
+       u_char a, b, i, tmp1, tmp2;
+
+       /* Initialize variables */
+       a = b = 0x80;
+       tmp1 = tmp2 = 0;
+
+       /* Calculate first ECC byte */
+       for (i = 0; i < 4; i++) {
+               if (reg3 & a)           /* LP15,13,11,9 --> ecc_code[0] */
+                       tmp1 |= b;
+               b >>= 1;
+               if (reg2 & a)           /* LP14,12,10,8 --> ecc_code[0] */
+                       tmp1 |= b;
+               b >>= 1;
+               a >>= 1;
+       }
+
+       /* Calculate second ECC byte */
+       b = 0x80;
+       for (i = 0; i < 4; i++) {
+               if (reg3 & a)           /* LP7,5,3,1 --> ecc_code[1] */
+                       tmp2 |= b;
+               b >>= 1;
+               if (reg2 & a)           /* LP6,4,2,0 --> ecc_code[1] */
+                       tmp2 |= b;
+               b >>= 1;
+               a >>= 1;
+       }
+
+       /* Store two of the ECC bytes */
+       ecc_code[0] = tmp1;
+       ecc_code[1] = tmp2;
+}
+
+/*
+ * Calculate 3 byte ECC code for 256 byte block
+ */
+static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code)
+{
+       u_char idx, reg1, reg3;
+       int j;
+
+       /* Initialize variables */
+       reg1 = reg3 = 0;
+       ecc_code[0] = ecc_code[1] = ecc_code[2] = 0;
+
+       /* Build up column parity */
+       for(j = 0; j < 256; j++) {
+
+               /* Get CP0 - CP5 from table */
+               idx = nand_ecc_precalc_table[dat[j]];
+               reg1 ^= idx;
+
+               /* All bit XOR = 1 ? */
+               if (idx & 0x40) {
+                       reg3 ^= (u_char) j;
+               }
+       }
+
+       /* Create non-inverted ECC code from line parity */
+       nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code);
+
+       /* Calculate final ECC code */
+       ecc_code[0] = ~ecc_code[0];
+       ecc_code[1] = ~ecc_code[1];
+       ecc_code[2] = ((~reg1) << 2) | 0x03;
+}
+
+/*
+ * Detect and correct a 1 bit error for 256 byte block
+ */
+static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc)
+{
+       u_char a, b, c, d1, d2, d3, add, bit, i;
+
+       /* Do error detection */
+       d1 = calc_ecc[0] ^ read_ecc[0];
+       d2 = calc_ecc[1] ^ read_ecc[1];
+       d3 = calc_ecc[2] ^ read_ecc[2];
+
+       if ((d1 | d2 | d3) == 0) {
+               /* No errors */
+               return 0;
+       } else {
+               a = (d1 ^ (d1 >> 1)) & 0x55;
+               b = (d2 ^ (d2 >> 1)) & 0x55;
+               c = (d3 ^ (d3 >> 1)) & 0x54;
+
+               /* Found and will correct single bit error in the data */
+               if ((a == 0x55) && (b == 0x55) && (c == 0x54)) {
+                       c = 0x80;
+                       add = 0;
+                       a = 0x80;
+                       for (i=0; i<4; i++) {
+                               if (d1 & c)
+                                       add |= a;
+                               c >>= 2;
+                               a >>= 1;
+                       }
+                       c = 0x80;
+                       for (i=0; i<4; i++) {
+                               if (d2 & c)
+                                       add |= a;
+                               c >>= 2;
+                               a >>= 1;
+                       }
+                       bit = 0;
+                       b = 0x04;
+                       c = 0x80;
+                       for (i=0; i<3; i++) {
+                               if (d3 & c)
+                                       bit |= b;
+                               c >>= 2;
+                               b >>= 1;
+                       }
+                       b = 0x01;
+                       a = dat[add];
+                       a ^= (b << bit);
+                       dat[add] = a;
+                       return 1;
+               }
+               else {
+                       i = 0;
+                       while (d1) {
+                               if (d1 & 0x01)
+                                       ++i;
+                               d1 >>= 1;
+                       }
+                       while (d2) {
+                               if (d2 & 0x01)
+                                       ++i;
+                               d2 >>= 1;
+                       }
+                       while (d3) {
+                               if (d3 & 0x01)
+                                       ++i;
+                               d3 >>= 1;
+                       }
+                       if (i == 1) {
+                               /* ECC Code Error Correction */
+                               read_ecc[0] = calc_ecc[0];
+                               read_ecc[1] = calc_ecc[1];
+                               read_ecc[2] = calc_ecc[2];
+                               return 2;
+                       }
+                       else {
+                               /* Uncorrectable Error */
+                               return -1;
+                       }
+               }
+       }
+
+       /* Should never happen */
+       return -1;
+}
+
+#endif
+
+#ifdef CONFIG_JFFS2_NAND
+int read_jffs2_nand(size_t start, size_t len,
+               size_t * retlen, u_char * buf, int nanddev)
+{
+       return nand_legacy_rw(nand_dev_desc + nanddev, NANDRW_READ | NANDRW_JFFS2,
+                       start, len, retlen, buf);
+}
+#endif /* CONFIG_JFFS2_NAND */
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) */

diff --git a/drivers/netconsole.c b/drivers/netconsole.c
index 9a0a24f3ac4bd8fb402723e00295fd12d220991a..69089f92cec913b1ab6d0c33f94273d8cc10badf 100644 (file)
--- a/drivers/netconsole.c
+++ b/drivers/netconsole.c
@@ -29,6 +29,8 @@
 #include <devices.h>
 #include <net.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static char input_buffer[512];
 static int input_size = 0;             /* char count in input buffer */
 static int input_offset = 0;           /* offset to valid chars in input buffer */
@@ -105,8 +107,6 @@ int nc_input_packet (uchar * pkt, unsigned dest, unsigned src, unsigned len)
 
 static void nc_send_packet (const char *buf, int len)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        struct eth_device *eth;
        int inited = 0;
        uchar *pkt;

diff --git a/drivers/ns9750_serial.c b/drivers/ns9750_serial.c
index aced3dae8e26ebcdb59a9065c2e076a587cef047..8dff36774500a343f72efb4a9ba6224bc094076b 100644 (file)
--- a/drivers/ns9750_serial.c
+++ b/drivers/ns9750_serial.c
@@ -33,6 +33,8 @@
 #include "ns9750_bbus.h"       /* for GPIOs */
 #include "ns9750_ser.h"                /* for serial configuration */
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define CONSOLE CONFIG_CONS_INDEX
 
 static unsigned int calcBitrateRegister( void );
@@ -183,8 +185,6 @@ void serial_setbrg( void )
 
 static unsigned int calcBitrateRegister( void )
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        return ( NS9750_SER_BITRATE_EBIT |
                 NS9750_SER_BITRATE_CLKMUX_BCLK |
                 NS9750_SER_BITRATE_TMODE |
@@ -204,8 +204,6 @@ static unsigned int calcBitrateRegister( void )
 
 static unsigned int calcRxCharGapRegister( void )
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        return NS9750_SER_RX_CHAR_TIMER_TRUN;
 }
 

diff --git a/drivers/pci.c b/drivers/pci.c
index 5360030661814c7cfb2f75273b172991fbb808f5..3c24b99c3767fc89d7ceff71d84021e63ea1ed1e 100644 (file)
--- a/drivers/pci.c
+++ b/drivers/pci.c
@@ -459,6 +459,7 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus)
                                              PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
                        if (cfg) {
                                cfg->config_device(hose, dev, cfg);
+                               sub_bus = max(sub_bus, hose->current_busno);
 #ifdef CONFIG_PCI_PNP
                        } else {
                                int n = pciauto_config_device(hose, dev);

diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c
index 3302457a3909dc1590d4a8961ddeb6a8c9200be0..15f74328f0a6a011c58cd425c56cb3a561dd1c98 100644 (file)
--- a/drivers/pci_auto.c
+++ b/drivers/pci_auto.c
@@ -77,6 +77,7 @@ int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned
 void pciauto_setup_device(struct pci_controller *hose,
                          pci_dev_t dev, int bars_num,
                          struct pci_region *mem,
+                         struct pci_region *prefetch,
                          struct pci_region *io)
 {
        unsigned int bar_value, bar_response, bar_size;
@@ -111,7 +112,10 @@ void pciauto_setup_device(struct pci_controller *hose,
                                found_mem64 = 1;
 
                        bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
-                       bar_res = mem;
+                       if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
+                               bar_res = prefetch;
+                       else
+                               bar_res = mem;
 
                        DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
                }
@@ -148,6 +152,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
                                         pci_dev_t dev, int sub_bus)
 {
        struct pci_region *pci_mem = hose->pci_mem;
+       struct pci_region *pci_prefetch = hose->pci_prefetch;
        struct pci_region *pci_io = hose->pci_io;
        unsigned int cmdstat;
 
@@ -169,6 +174,21 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
                cmdstat |= PCI_COMMAND_MEMORY;
        }
 
+       if (pci_prefetch) {
+               /* Round memory allocator to 1MB boundary */
+               pciauto_region_align(pci_prefetch, 0x100000);
+
+               /* Set up memory and I/O filter limits, assume 32-bit I/O space */
+               pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
+                                       (pci_prefetch->bus_lower & 0xfff00000) >> 16);
+
+               cmdstat |= PCI_COMMAND_MEMORY;
+       } else {
+               /* We don't support prefetchable memory for now, so disable */
+               pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
+               pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
+       }
+
        if (pci_io) {
                /* Round I/O allocator to 4KB boundary */
                pciauto_region_align(pci_io, 0x1000);
@@ -181,10 +201,6 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
                cmdstat |= PCI_COMMAND_IO;
        }
 
-       /* We don't support prefetchable memory for now, so disable */
-       pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
-       pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
-
        /* Enable memory and I/O accesses, enable bus master */
        pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
 }
@@ -193,6 +209,7 @@ static void pciauto_postscan_setup_bridge(struct pci_controller *hose,
                                          pci_dev_t dev, int sub_bus)
 {
        struct pci_region *pci_mem = hose->pci_mem;
+       struct pci_region *pci_prefetch = hose->pci_prefetch;
        struct pci_region *pci_io = hose->pci_io;
 
        /* Configure bus number registers */
@@ -206,6 +223,14 @@ static void pciauto_postscan_setup_bridge(struct pci_controller *hose,
                                        (pci_mem->bus_lower-1) >> 16);
        }
 
+       if (pci_prefetch) {
+               /* Round memory allocator to 1MB boundary */
+               pciauto_region_align(pci_prefetch, 0x100000);
+
+               pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
+                                       (pci_prefetch->bus_lower-1) >> 16);
+       }
+
        if (pci_io) {
                /* Round I/O allocator to 4KB boundary */
                pciauto_region_align(pci_io, 0x1000);
@@ -239,6 +264,11 @@ void pciauto_config_init(struct pci_controller *hose)
                            hose->pci_mem->size < hose->regions[i].size)
                                hose->pci_mem = hose->regions + i;
                        break;
+               case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
+                       if (!hose->pci_prefetch ||
+                           hose->pci_prefetch->size < hose->regions[i].size)
+                               hose->pci_prefetch = hose->regions + i;
+                       break;
                }
        }
 
@@ -251,6 +281,14 @@ void pciauto_config_init(struct pci_controller *hose)
                    hose->pci_mem->bus_start + hose->pci_mem->size - 1);
        }
 
+       if (hose->pci_prefetch) {
+               pciauto_region_init(hose->pci_prefetch);
+
+               DEBUGF("PCI Autoconfig: Prefetchable Memory region: [%lx-%lx]\n",
+                   hose->pci_prefetch->bus_start,
+                   hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1);
+       }
+
        if (hose->pci_io) {
                pciauto_region_init(hose->pci_io);
 
@@ -275,7 +313,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
        switch(class) {
        case PCI_CLASS_BRIDGE_PCI:
                hose->current_busno++;
-               pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
+               pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
 
                DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
 
@@ -301,12 +339,12 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
                        return sub_bus;
                }
 
-               pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
+               pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
                break;
 
        case PCI_CLASS_BRIDGE_CARDBUS:
                /* just do a minimal setup of the bridge, let the OS take care of the rest */
-               pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
+               pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
 
                DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
 
@@ -328,11 +366,11 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
                 * the PIMMR window to be allocated (BAR0 - 1MB size)
                 */
                DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
-               pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
+               pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
                break;
 #endif
        default:
-               pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
+               pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
                break;
        }
 

diff --git a/drivers/pci_indirect.c b/drivers/pci_indirect.c
index e8f19f57010dfcb49d1258b38794f720661fb57c..f0c4a1ccf4742b2a993873b191d74cff635667f2 100644 (file)
--- a/drivers/pci_indirect.c
+++ b/drivers/pci_indirect.c
@@ -36,6 +36,10 @@ static int                                                            \
 indirect_##rw##_config_##size(struct pci_controller *hose,              \
                              pci_dev_t dev, int offset, type val)       \
 {                                                                       \
+       u32 b, d,f;                                                      \
+       b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);           \
+       b = b - hose->first_busno;                                       \
+       dev = PCI_BDF(b, d, f);                                          \
        out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);    \
        sync();                                                          \
        cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
@@ -47,6 +51,10 @@ static int                                                               \
 indirect_##rw##_config_##size(struct pci_controller *hose,               \
                              pci_dev_t dev, int offset, type val)       \
 {                                                                        \
+       u32 b, d,f;                                                      \
+       b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);           \
+       b = b - hose->first_busno;                                       \
+       dev = PCI_BDF(b, d, f);                                          \
        *(hose->cfg_addr) = dev | (offset & 0xfc) | 0x80000000;          \
        sync();                                                          \
        cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
@@ -58,6 +66,10 @@ static int                                                            \
 indirect_##rw##_config_##size(struct pci_controller *hose,              \
                              pci_dev_t dev, int offset, type val)       \
 {                                                                       \
+       u32 b, d,f;                                                      \
+       b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);           \
+       b = b - hose->first_busno;                                       \
+       dev = PCI_BDF(b, d, f);                                          \
        if (PCI_BUS(dev) > 0)                                            \
                out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); \
        else                                                             \
@@ -71,6 +83,10 @@ static int                                                            \
 indirect_##rw##_config_##size(struct pci_controller *hose,              \
                              pci_dev_t dev, int offset, type val)       \
 {                                                                       \
+       u32 b, d,f;                                                      \
+       b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);           \
+       b = b - hose->first_busno;                                       \
+       dev = PCI_BDF(b, d, f);                                          \
        out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);    \
        cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
        return 0;                                                        \

diff --git a/drivers/ps2ser.c b/drivers/ps2ser.c
index e2a38dc3dccd923c1c807e48d5a8e25048b99f42..724fa4058278b63fbfe59192814cdd70bdc983cb 100644 (file)
--- a/drivers/ps2ser.c
+++ b/drivers/ps2ser.c
@@ -21,6 +21,8 @@
 #include <asm/atomic.h>
 #include <ps2mult.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* #define     DEBUG */
 
 #define PS2SER_BAUD    57600
@@ -61,8 +63,6 @@ static int    ps2buf_out_idx;
 #ifdef CONFIG_MPC5xxx
 int ps2ser_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
        unsigned long baseclk;
        int div;

diff --git a/drivers/s3c4510b_uart.c b/drivers/s3c4510b_uart.c
index 44b96a9c5e7a377c3b2de711534cdc8a9bf7236f..ddcd591f84a3b0bd08c12bf890cf89b750d850d5 100644 (file)
--- a/drivers/s3c4510b_uart.c
+++ b/drivers/s3c4510b_uart.c
@@ -50,6 +50,8 @@
 #include <asm/hardware.h>
 #include "s3c4510b_uart.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static UART    *uart;
 
 /* flush serial input queue. returns 0 on success or negative error
@@ -82,8 +84,6 @@ static int serial_flush_output(void)
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        UART_LINE_CTRL ulctrl;
        UART_CTRL      uctrl;
        UART_BAUD_DIV  ubd;

diff --git a/drivers/serial.c b/drivers/serial.c
index 057a1ab0174ec9566bdc630f549b086fb0d4d1d7..228781b46a63409c2565e3751f2c0c8022644c96 100644 (file)
--- a/drivers/serial.c
+++ b/drivers/serial.c
@@ -30,6 +30,8 @@
 #include <ns87308.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if !defined(CONFIG_CONS_INDEX)
 #error "No console index specified."
 #elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4)
@@ -77,7 +79,6 @@ static NS16550_t serial_ports[4] = {
 
 static int calc_divisor (NS16550_t port)
 {
-       DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_OMAP1510
        /* If can't cleanly clock 115200 set div to 1 */
        if ((CFG_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) {

diff --git a/drivers/serial_max3100.c b/drivers/serial_max3100.c
index bbe212b81f79e3e2e6f465087e0d46aa7388cbb9..35c5596985bbf6ee05cf01f0c1ba4bb734c22531 100644 (file)
--- a/drivers/serial_max3100.c
+++ b/drivers/serial_max3100.c
@@ -28,6 +28,8 @@
 
 #ifdef CONFIG_MAX3100_SERIAL
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /**************************************************************/
 
 /* convienient macros */
@@ -217,7 +219,6 @@ int serial_init(void)
 {
        unsigned int wconf, rconf;
        int i;
-       DECLARE_GLOBAL_DATA_PTR;
 
        wconf = 0;
 

diff --git a/drivers/smc91111.c b/drivers/smc91111.c
index 060da8ff2aaec74500bd5c400cdea60a42dd8f3c..f91e4b984369fca9c75138be33a808134e779610 100644 (file)
--- a/drivers/smc91111.c
+++ b/drivers/smc91111.c
@@ -160,6 +160,9 @@ extern void eth_halt(void);
 extern int eth_rx(void);
 extern int eth_send(volatile void *packet, int length);
 
+#ifdef SHARED_RESOURCES
+       extern void swap_to(int device_id);
+#endif
 
 /*
  . This is called by  register_netdev().  It is responsible for
@@ -210,7 +213,7 @@ static int smc_rcv(void);
  . If an EEPROM is present it really should be consulted.
 */
 int smc_get_ethaddr(bd_t *bd);
-int get_rom_mac(char *v_rom_mac);
+int get_rom_mac(uchar *v_rom_mac);
 
 /*
  ------------------------------------------------------------
@@ -276,17 +279,23 @@ static inline void SMC_outb(byte value, dword offset)
 
 static inline void SMC_insw(dword offset, volatile uchar* buf, dword len)
 {
+       volatile word *p = (volatile word *)buf;
+
        while (len-- > 0) {
-               *((word*)buf)++ = SMC_inw(offset);
-               barrier(); *((volatile u32*)(0xc0000000));
+               *p++ = SMC_inw(offset);
+               barrier();
+               *((volatile u32*)(0xc0000000));
        }
 }
 
 static inline void SMC_outsw(dword offset, uchar* buf, dword len)
 {
+       volatile word *p = (volatile word *)buf;
+
        while (len-- > 0) {
-               SMC_outw(*((word*)buf)++, offset);
-               barrier(); *(volatile u32*)(0xc0000000);
+               SMC_outw(*p++, offset);
+               barrier();
+               *(volatile u32*)(0xc0000000);
        }
 }
 #endif  /* CONFIG_SMC_USE_IOFUNCS */
@@ -298,7 +307,7 @@ static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
  * the default mac address.
  */
 
-void smc_set_mac_addr(const char *addr) {
+void smc_set_mac_addr(const unsigned char *addr) {
        int i;
 
        for (i=0; i < sizeof(smc_mac_addr); i++){
@@ -527,6 +536,9 @@ static void smc_shutdown()
        SMC_SELECT_BANK( 0 );
        SMC_outb( RCR_CLEAR, RCR_REG );
        SMC_outb( TCR_CLEAR, TCR_REG );
+#ifdef SHARED_RESOURCES
+       swap_to(FLASH);
+#endif
 }
 
 
@@ -1505,6 +1517,9 @@ static void print_packet( byte * buf, int length )
 #endif
 
 int eth_init(bd_t *bd) {
+#ifdef SHARED_RESOURCES
+       swap_to(ETHERNET);
+#endif
        return (smc_open(bd));
 }
 
@@ -1524,7 +1539,8 @@ int smc_get_ethaddr (bd_t * bd)
 {
        int env_size, rom_valid, env_present = 0, reg;
        char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66";
-       uchar s_env_mac[64], v_env_mac[6], v_rom_mac[6];
+       char s_env_mac[64];
+       uchar v_env_mac[6], v_rom_mac[6];
 
        env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac));
        if ((env_size > 0) && (env_size < sizeof (es))) {       /* exit if env is bad */
@@ -1547,7 +1563,7 @@ int smc_get_ethaddr (bd_t * bd)
 
        if (!env_present) {     /* if NO env */
                if (rom_valid) {        /* but ROM is valid */
-                       v_mac = v_rom_mac;
+                       v_mac = (char *)v_rom_mac;
                        sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
                                 v_mac[0], v_mac[1], v_mac[2], v_mac[3],
                                 v_mac[4], v_mac[5]);
@@ -1557,7 +1573,7 @@ int smc_get_ethaddr (bd_t * bd)
                        return (-1);
                }
        } else {                /* good env, don't care ROM */
-               v_mac = v_env_mac;      /* always use a good env over a ROM */
+               v_mac = (char *)v_env_mac;      /* always use a good env over a ROM */
        }
 
        if (env_present && rom_valid) { /* if both env and ROM are good */
@@ -1577,13 +1593,13 @@ int smc_get_ethaddr (bd_t * bd)
                }
        }
        memcpy (bd->bi_enetaddr, v_mac, 6);     /* update global address to match env (allows env changing) */
-       smc_set_mac_addr (v_mac);       /* use old function to update smc default */
+       smc_set_mac_addr ((uchar *)v_mac);      /* use old function to update smc default */
        PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1],
                v_mac[2], v_mac[3], v_mac[4], v_mac[5]);
        return (0);
 }
 
-int get_rom_mac (char *v_rom_mac)
+int get_rom_mac (uchar *v_rom_mac)
 {
 #ifdef HARDCODE_MAC    /* used for testing or to supress run time warnings */
        char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };

diff --git a/drivers/smc91111.h b/drivers/smc91111.h
index cf08582fbf21e8500a4c89644fbf217d260b6641..d03cbc320bf11a1bc8071f24259e0a15202982b7 100644 (file)
--- a/drivers/smc91111.h
+++ b/drivers/smc91111.h
@@ -49,7 +49,7 @@
  * in order to override the default mac address.
  */
 
-void smc_set_mac_addr(const char *addr);
+void smc_set_mac_addr (const unsigned char *addr);
 
 
 /* I want some simple types */
@@ -185,6 +185,8 @@ typedef unsigned long int           dword;
 
 #ifdef CONFIG_ADNPESC1
 #define        SMC_inw(r)      (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))))
+#elif CONFIG_BLACKFIN
+#define        SMC_inw(r)      ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); asm("ssync;"); __v;})
 #else
 #define        SMC_inw(r)      (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
 #endif
@@ -192,6 +194,8 @@ typedef unsigned long int           dword;
 
 #ifdef CONFIG_ADNPESC1
 #define        SMC_outw(d,r)   (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d)
+#elif CONFIG_BLACKFIN
+#define        SMC_outw(d,r)   {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d);asm("ssync;");}
 #else
 #define        SMC_outw(d,r)   (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
 #endif

diff --git a/drivers/tsec.c b/drivers/tsec.c
index f860dae8b009f6deec85afb2516c8885ed6b10c1..7ec565ca67bf9b3a8c226888c4122b485c72517e 100644 (file)
--- a/drivers/tsec.c
+++ b/drivers/tsec.c
@@ -23,6 +23,8 @@
 #include "tsec.h"
 #include "miiphy.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define TX_BUF_CNT             2
 
 static uint rxIdx;     /* index of the current RX buffer */
@@ -940,6 +942,56 @@ static struct phy_info phy_info_lxt971 = {
        },
 };
 
+/* Parse the DP83865's link and auto-neg status register for speed and duplex
+ * information */
+uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
+{
+       switch (mii_reg & MIIM_DP83865_SPD_MASK) {
+
+       case MIIM_DP83865_SPD_1000:
+               priv->speed = 1000;
+               break;
+
+       case MIIM_DP83865_SPD_100:
+               priv->speed = 100;
+               break;
+
+       default:
+               priv->speed = 10;
+               break;
+
+       }
+
+       if (mii_reg & MIIM_DP83865_DPX_FULL)
+               priv->duplexity = 1;
+       else
+               priv->duplexity = 0;
+
+       return 0;
+}
+
+struct phy_info phy_info_dp83865 = {
+       0x20005c7,
+       "NatSemi DP83865",
+       4,
+       (struct phy_cmd[]) { /* config */
+               {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
+               {miim_end,}
+       },
+       (struct phy_cmd[]) { /* startup */
+               /* Status is read once to clear old link state */
+               {MIIM_STATUS, miim_read, NULL},
+               /* Auto-negotiate */
+               {MIIM_STATUS, miim_read, &mii_parse_sr},
+               /* Read the link and auto-neg status */
+               {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr},
+               {miim_end,}
+       },
+       (struct phy_cmd[]) { /* shutdown */
+               {miim_end,}
+       },
+};
+
 struct phy_info *phy_info[] = {
 #if 0
        &phy_info_cis8201,
@@ -949,6 +1001,7 @@ struct phy_info *phy_info[] = {
        &phy_info_M88E1111S,
        &phy_info_dm9161,
        &phy_info_lxt971,
+       &phy_info_dp83865,
        NULL
 };
 
@@ -1031,7 +1084,6 @@ static void relocate_cmds(void)
        struct phy_cmd **cmdlistptr;
        struct phy_cmd *cmd;
        int i,j,k;
-       DECLARE_GLOBAL_DATA_PTR;
 
        for(i=0; phy_info[i]; i++) {
                /* First thing's first: relocate the pointers to the

diff --git a/drivers/tsec.h b/drivers/tsec.h
index c26fcc0e732fe656a9d000bc4339d928490fe085..b55b2992b226f921a889bcf4a4c3338116668952 100644 (file)
--- a/drivers/tsec.h
+++ b/drivers/tsec.h
@@ -124,7 +124,7 @@
 /* Cicada 8204 Extended PHY Control Register 1 */
 #define MIIM_CIS8204_EPHY_CON          0x17
 #define MIIM_CIS8204_EPHYCON_INIT      0x0006
-#define MIIM_CIS8204_EPHYCON_RGMII     0x1000
+#define MIIM_CIS8204_EPHYCON_RGMII     0x1100
 
 /* Cicada 8204 Serial LED Control Register */
 #define MIIM_CIS8204_SLED_CON          0x1b
@@ -161,12 +161,22 @@
 #define MIIM_DM9161_10BTCSR_INIT       0x7800
 
 /* LXT971 Status 2 registers */
-#define MIIM_LXT971_SR2        17  /* Status Register 2  */
-#define MIIM_LXT971_SR2_SPEED_MASK     0xf000
-#define MIIM_LXT971_SR2_10HDX  0x1000  /* 10 Mbit half duplex selected */
-#define MIIM_LXT971_SR2_10FDX  0x2000  /* 10 Mbit full duplex selected */
-#define MIIM_LXT971_SR2_100HDX 0x4000  /* 100 Mbit half duplex selected */
-#define MIIM_LXT971_SR2_100FDX 0x8000  /* 100 Mbit full duplex selected */
+#define MIIM_LXT971_SR2              0x11  /* Status Register 2  */
+#define MIIM_LXT971_SR2_SPEED_MASK 0x4200
+#define MIIM_LXT971_SR2_10HDX      0x0000  /*  10 Mbit half duplex selected */
+#define MIIM_LXT971_SR2_10FDX      0x0200  /*  10 Mbit full duplex selected */
+#define MIIM_LXT971_SR2_100HDX     0x4000  /* 100 Mbit half duplex selected */
+#define MIIM_LXT971_SR2_100FDX     0x4200  /* 100 Mbit full duplex selected */
+
+/* DP83865 Control register values */
+#define MIIM_DP83865_CR_INIT   0x9200
+
+/* DP83865 Link and Auto-Neg Status Register */
+#define MIIM_DP83865_LANR      0x11
+#define MIIM_DP83865_SPD_MASK  0x0018
+#define MIIM_DP83865_SPD_1000  0x0010
+#define MIIM_DP83865_SPD_100   0x0008
+#define MIIM_DP83865_DPX_FULL  0x0002
 
 #define MIIM_READ_COMMAND       0x00000001
 

diff --git a/examples/Makefile b/examples/Makefile
index a244d24680aa6809dadc231f72ce46b2ab403dec..b198048973e84ab9f9e1f6f82e048136cda05864 100644 (file)
--- a/examples/Makefile
+++ b/examples/Makefile
@@ -53,6 +53,10 @@ ifeq ($(ARCH),microblaze)
 LOAD_ADDR = 0x80F00000
 endif
 
+ifeq ($(ARCH),blackfin)
+LOAD_ADDR = 0x1000
+endif
+
 include $(TOPDIR)/config.mk
 
 SREC   = hello_world.srec
@@ -73,6 +77,11 @@ SREC   += sched.srec
 BIN    += sched.bin sched
 endif
 
+ifeq ($(ARCH),blackfin)
+SREC   += smc91111_eeprom.srec
+BIN    += smc91111_eeprom.bin smc91111_eeprom
+endif
+
 # The following example is pretty 8xx specific...
 ifeq ($(CPU),mpc8xx)
 SREC   += timer.srec

diff --git a/examples/mem_to_mem_idma2intr.c b/examples/mem_to_mem_idma2intr.c
index 3a269c9082a588732605340ea16a42fec0293d4b..3ff28041f81267bdf548a2a4b7fd062e8e59de5a 100644 (file)
--- a/examples/mem_to_mem_idma2intr.c
+++ b/examples/mem_to_mem_idma2intr.c
@@ -30,6 +30,8 @@
 #include <common.h>
 #include <exports.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define STANDALONE
 
 #ifndef STANDALONE                     /* Linked into/Part of  PPCBoot */
@@ -346,8 +348,6 @@ static uint dpbase = 0;
 
 uint dpalloc (uint size, uint align)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile immap_t *immr = (immap_t *) CFG_IMMR;
        uint retloc;
        uint align_mask, off;

diff --git a/examples/smc91111_eeprom.c b/examples/smc91111_eeprom.c
index 885f9336cd9e22211d80025a16253dff34876ff9..98e3e86ffa555906b0eb34c2cd3fff40fb425767 100644 (file)
--- a/examples/smc91111_eeprom.c
+++ b/examples/smc91111_eeprom.c
@@ -214,13 +214,11 @@ int smc91111_eeprom (int argc, char *argv[])
 
                        switch (what) {
                        case 1:
-                               printf ("Writing EEPROM register %02x with %04x\n",
-                                       reg, value);
+                               printf ("Writing EEPROM register %02x with %04x\n", reg, value);
                                write_eeprom_reg (value, reg);
                                break;
                        case 2:
-                               printf ("Writing MAC register bank %i,
-                                       reg %02x with %04x\n", reg >> 4, reg & 0xE, value);
+                               printf ("Writing MAC register bank %i, reg %02x with %04x\n", reg >> 4, reg & 0xE, value);
                                SMC_SELECT_BANK (reg >> 4);
                                SMC_outw (value, reg & 0xE);
                                break;

diff --git a/examples/stubs.c b/examples/stubs.c
index d4c6e063e3ed1428f0eb4d7a84710b4496e6e34e..250a9af6e5667fbd95b2644b68ec0ce7dcbeb365 100644 (file)
--- a/examples/stubs.c
+++ b/examples/stubs.c
@@ -125,6 +125,19 @@ gd_t *global_data;
 "      lwi     r5, r5, %1\n"                   \
 "      bra     r5\n"                           \
        : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r5");
+#elif defined(CONFIG_BLACKFIN)
+/*
+ * P5 holds the pointer to the global_data, P0 is a call-clobbered
+ * register
+ */
+#define EXPORT_FUNC(x)                 \
+       asm volatile (                  \
+"       .globl " #x "\n"               \
+#x ":\n"                               \
+"      P0 = [P5 + %0]\n"               \
+"      P0 = [P0 + %1]\n"               \
+"      JUMP (P0)\n"                    \
+       : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "P0");
 #else
 #error stubs definition missing for this architecture
 #endif

diff --git a/examples/timer.c b/examples/timer.c
index 037fdfdb3a811885987ffdb76c2dba285a046a60..13ec06f02c44453b991329e49b97f052b47d204f 100644 (file)
--- a/examples/timer.c
+++ b/examples/timer.c
@@ -26,6 +26,8 @@
 #include <mpc8xx_irq.h>
 #include <exports.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef DEBUG
 
 #define        TIMER_PERIOD    1000000         /* 1 second clock */
@@ -115,8 +117,6 @@ static char *usage = "\n[q, b, e, ?] ";
 
 int timer (int argc, char *argv[])
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        cpmtimer8xx_t *cpmtimerp;       /* Pointer to the CPM Timer structure   */
        tid_8xx_cpmtimer_t hw;
        tid_8xx_cpmtimer_t *hwp = &hw;

diff --git a/fs/ext2/ext2fs.c b/fs/ext2/ext2fs.c
index c21d2d6172214e6a4ff2909851413ff89b52d398..9cf2fb7ba494499a1afe38a63f6c6fb378895cf1 100644 (file)
--- a/fs/ext2/ext2fs.c
+++ b/fs/ext2/ext2fs.c
@@ -389,7 +389,7 @@ int ext2fs_read_file
        int blockcnt;
        int log2blocksize = LOG2_EXT2_BLOCK_SIZE (node->data);
        int blocksize = 1 << (log2blocksize + DISK_SECTOR_BITS);
-       unsigned int filesize = node->inode.size;
+       unsigned int filesize = __le32_to_cpu(node->inode.size);
 
        /* Adjust len so it we can't read past the end of the file.  */
        if (len > filesize) {

diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index c6c0c2a57fd2f22b52d26e0d506d55096382d9e1..41ff4c1fbbd369a191debb703c03caf3ac36e86e 100644 (file)
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -144,6 +144,11 @@
 static struct part_info *current_part;
 
 #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CFG_NAND_LEGACY)
+#include <linux/mtd/nand_legacy.h>
+#else
+#include <nand.h>
+#endif
 /*
  * Support for jffs2 on top of NAND-flash
  *
@@ -154,9 +159,14 @@ static struct part_info *current_part;
  *
  */
 
-/* this one defined in cmd_nand.c */
+#if defined(CFG_NAND_LEGACY)
+/* this one defined in nand_legacy.c */
 int read_jffs2_nand(size_t start, size_t len,
-                   size_t * retlen, u_char * buf, int nanddev);
+               size_t * retlen, u_char * buf, int nanddev);
+#else
+/* info for NAND chips, defined in drivers/nand/nand.c */
+extern nand_info_t nand_info[];
+#endif
 
 #define NAND_PAGE_SIZE 512
 #define NAND_PAGE_SHIFT 9
@@ -174,7 +184,11 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf)
 {
        struct mtdids *id = current_part->dev->id;
        u32 bytes_read = 0;
+#if defined(CFG_NAND_LEGACY)
        size_t retlen;
+#else
+       ulong retlen;
+#endif
        int cpy_bytes;
 
        while (bytes_read < size) {
@@ -191,6 +205,8 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf)
                                        return -1;
                                }
                        }
+
+#if defined(CFG_NAND_LEGACY)
                        if (read_jffs2_nand(nand_cache_off, NAND_CACHE_SIZE,
                                                &retlen, nand_cache, id->num) < 0 ||
                                        retlen != NAND_CACHE_SIZE) {
@@ -198,6 +214,16 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf)
                                                nand_cache_off, NAND_CACHE_SIZE);
                                return -1;
                        }
+#else
+                       retlen = NAND_CACHE_SIZE;
+                       if (nand_read(&nand_info[id->num], nand_cache_off,
+                                               &retlen, nand_cache) != 0 ||
+                                       retlen != NAND_CACHE_SIZE) {
+                               printf("read_nand_cached: error reading nand off %#x size %d bytes\n",
+                                               nand_cache_off, NAND_CACHE_SIZE);
+                               return -1;
+                       }
+#endif
                }
                cpy_bytes = nand_cache_off + NAND_CACHE_SIZE - (off + bytes_read);
                if (cpy_bytes > size - bytes_read)
@@ -1167,7 +1193,8 @@ jffs2_1pass_build_lists(struct part_info * part)
                if (node->magic == JFFS2_MAGIC_BITMASK && hdr_crc(node)) {
                        /* if its a fragment add it */
                        if (node->nodetype == JFFS2_NODETYPE_INODE &&
-                                   inode_crc((struct jffs2_raw_inode *) node)) {
+                                   inode_crc((struct jffs2_raw_inode *) node) &&
+                                   data_crc((struct jffs2_raw_inode *) node)) {
                                if (insert_node(&pL->frag, (u32) part->offset +
                                                offset) == NULL) {
                                        put_fl_mem(node);

diff --git a/fs/jffs2/jffs2_nand_1pass.c b/fs/jffs2/jffs2_nand_1pass.c
new file mode 100644 (file)
index 0000000..e78af75
--- /dev/null
+++ b/fs/jffs2/jffs2_nand_1pass.c
@@ -0,0 +1,1036 @@
+#include <common.h>
+
+#if !defined(CFG_NAND_LEGACY) && (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+
+#include <malloc.h>
+#include <linux/stat.h>
+#include <linux/time.h>
+
+#include <jffs2/jffs2.h>
+#include <jffs2/jffs2_1pass.h>
+#include <nand.h>
+
+#include "jffs2_nand_private.h"
+
+#define        NODE_CHUNK      1024    /* size of memory allocation chunk in b_nodes */
+
+/* Debugging switches */
+#undef DEBUG_DIRENTS           /* print directory entry list after scan */
+#undef DEBUG_FRAGMENTS         /* print fragment list after scan */
+#undef DEBUG                   /* enable debugging messages */
+
+#ifdef  DEBUG
+# define DEBUGF(fmt,args...)   printf(fmt ,##args)
+#else
+# define DEBUGF(fmt,args...)
+#endif
+
+static nand_info_t *nand;
+
+/* Compression names */
+static char *compr_names[] = {
+       "NONE",
+       "ZERO",
+       "RTIME",
+       "RUBINMIPS",
+       "COPY",
+       "DYNRUBIN",
+       "ZLIB",
+#if defined(CONFIG_JFFS2_LZO_LZARI)
+       "LZO",
+       "LZARI",
+#endif
+};
+
+/* Spinning wheel */
+static char spinner[] = { '|', '/', '-', '\\' };
+
+/* Memory management */
+struct mem_block {
+       unsigned index;
+       struct mem_block *next;
+       char nodes[0];
+};
+
+static void
+free_nodes(struct b_list *list)
+{
+       while (list->listMemBase != NULL) {
+               struct mem_block *next = list->listMemBase->next;
+               free(list->listMemBase);
+               list->listMemBase = next;
+       }
+}
+
+static struct b_node *
+add_node(struct b_list *list, int size)
+{
+       u32 index = 0;
+       struct mem_block *memBase;
+       struct b_node *b;
+
+       memBase = list->listMemBase;
+       if (memBase != NULL)
+               index = memBase->index;
+
+       if (memBase == NULL || index >= NODE_CHUNK) {
+               /* we need more space before we continue */
+               memBase = mmalloc(sizeof(struct mem_block) + NODE_CHUNK * size);
+               if (memBase == NULL) {
+                       putstr("add_node: malloc failed\n");
+                       return NULL;
+               }
+               memBase->next = list->listMemBase;
+               index = 0;
+       }
+       /* now we have room to add it. */
+       b = (struct b_node *)&memBase->nodes[size * index];
+       index ++;
+
+       memBase->index = index;
+       list->listMemBase = memBase;
+       list->listCount++;
+       return b;
+}
+
+static struct b_node *
+insert_node(struct b_list *list, struct b_node *new)
+{
+#ifdef CFG_JFFS2_SORT_FRAGMENTS
+       struct b_node *b, *prev;
+
+       if (list->listTail != NULL && list->listCompare(new, list->listTail))
+               prev = list->listTail;
+       else if (list->listLast != NULL && list->listCompare(new, list->listLast))
+               prev = list->listLast;
+       else
+               prev = NULL;
+
+       for (b = (prev ? prev->next : list->listHead);
+            b != NULL && list->listCompare(new, b);
+            prev = b, b = b->next) {
+               list->listLoops++;
+       }
+       if (b != NULL)
+               list->listLast = prev;
+
+       if (b != NULL) {
+               new->next = b;
+               if (prev != NULL)
+                       prev->next = new;
+               else
+                       list->listHead = new;
+       } else
+#endif
+       {
+               new->next = (struct b_node *) NULL;
+               if (list->listTail != NULL) {
+                       list->listTail->next = new;
+                       list->listTail = new;
+               } else {
+                       list->listTail = list->listHead = new;
+               }
+       }
+
+       return new;
+}
+
+static struct b_node *
+insert_inode(struct b_list *list, struct jffs2_raw_inode *node, u32 offset)
+{
+       struct b_inode *new;
+
+       if (!(new = (struct b_inode *)add_node(list, sizeof(struct b_inode)))) {
+               putstr("add_node failed!\r\n");
+               return NULL;
+       }
+       new->offset = offset;
+       new->version = node->version;
+       new->ino = node->ino;
+       new->isize = node->isize;
+       new->csize = node->csize;
+
+       return insert_node(list, (struct b_node *)new);
+}
+
+static struct b_node *
+insert_dirent(struct b_list *list, struct jffs2_raw_dirent *node, u32 offset)
+{
+       struct b_dirent *new;
+
+       if (!(new = (struct b_dirent *)add_node(list, sizeof(struct b_dirent)))) {
+               putstr("add_node failed!\r\n");
+               return NULL;
+       }
+       new->offset = offset;
+       new->version = node->version;
+       new->pino = node->pino;
+       new->ino = node->ino;
+       new->nhash = full_name_hash(node->name, node->nsize);
+       new->nsize = node->nsize;
+       new->type = node->type;
+
+       return insert_node(list, (struct b_node *)new);
+}
+
+#ifdef CFG_JFFS2_SORT_FRAGMENTS
+/* Sort data entries with the latest version last, so that if there
+ * is overlapping data the latest version will be used.
+ */
+static int compare_inodes(struct b_node *new, struct b_node *old)
+{
+       struct jffs2_raw_inode ojNew;
+       struct jffs2_raw_inode ojOld;
+       struct jffs2_raw_inode *jNew =
+               (struct jffs2_raw_inode *)get_fl_mem(new->offset, sizeof(ojNew), &ojNew);
+       struct jffs2_raw_inode *jOld =
+               (struct jffs2_raw_inode *)get_fl_mem(old->offset, sizeof(ojOld), &ojOld);
+
+       return jNew->version > jOld->version;
+}
+
+/* Sort directory entries so all entries in the same directory
+ * with the same name are grouped together, with the latest version
+ * last. This makes it easy to eliminate all but the latest version
+ * by marking the previous version dead by setting the inode to 0.
+ */
+static int compare_dirents(struct b_node *new, struct b_node *old)
+{
+       struct jffs2_raw_dirent ojNew;
+       struct jffs2_raw_dirent ojOld;
+       struct jffs2_raw_dirent *jNew =
+               (struct jffs2_raw_dirent *)get_fl_mem(new->offset, sizeof(ojNew), &ojNew);
+       struct jffs2_raw_dirent *jOld =
+               (struct jffs2_raw_dirent *)get_fl_mem(old->offset, sizeof(ojOld), &ojOld);
+       int cmp;
+
+       /* ascending sort by pino */
+       if (jNew->pino != jOld->pino)
+               return jNew->pino > jOld->pino;
+
+       /* pino is the same, so use ascending sort by nsize, so
+        * we don't do strncmp unless we really must.
+        */
+       if (jNew->nsize != jOld->nsize)
+               return jNew->nsize > jOld->nsize;
+
+       /* length is also the same, so use ascending sort by name
+        */
+       cmp = strncmp(jNew->name, jOld->name, jNew->nsize);
+       if (cmp != 0)
+               return cmp > 0;
+
+       /* we have duplicate names in this directory, so use ascending
+        * sort by version
+        */
+       if (jNew->version > jOld->version) {
+               /* since jNew is newer, we know jOld is not valid, so
+                * mark it with inode 0 and it will not be used
+                */
+               jOld->ino = 0;
+               return 1;
+       }
+
+       return 0;
+}
+#endif
+
+static u32
+jffs_init_1pass_list(struct part_info *part)
+{
+       struct b_lists *pL;
+
+       if (part->jffs2_priv != NULL) {
+               pL = (struct b_lists *)part->jffs2_priv;
+               free_nodes(&pL->frag);
+               free_nodes(&pL->dir);
+               free(pL);
+       }
+       if (NULL != (part->jffs2_priv = malloc(sizeof(struct b_lists)))) {
+               pL = (struct b_lists *)part->jffs2_priv;
+
+               memset(pL, 0, sizeof(*pL));
+#ifdef CFG_JFFS2_SORT_FRAGMENTS
+               pL->dir.listCompare = compare_dirents;
+               pL->frag.listCompare = compare_inodes;
+#endif
+       }
+       return 0;
+}
+
+/* find the inode from the slashless name given a parent */
+static long
+jffs2_1pass_read_inode(struct b_lists *pL, u32 ino, char *dest,
+                      struct stat *stat)
+{
+       struct b_inode *jNode;
+       u32 totalSize = 0;
+       u32 latestVersion = 0;
+       long ret;
+
+#ifdef CFG_JFFS2_SORT_FRAGMENTS
+       /* Find file size before loading any data, so fragments that
+        * start past the end of file can be ignored. A fragment
+        * that is partially in the file is loaded, so extra data may
+        * be loaded up to the next 4K boundary above the file size.
+        * This shouldn't cause trouble when loading kernel images, so
+        * we will live with it.
+        */
+       for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) {
+               if ((ino == jNode->ino)) {
+                       /* get actual file length from the newest node */
+                       if (jNode->version >= latestVersion) {
+                               totalSize = jNode->isize;
+                               latestVersion = jNode->version;
+                       }
+               }
+       }
+#endif
+
+       for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) {
+               if ((ino != jNode->ino))
+                       continue;
+#ifndef CFG_JFFS2_SORT_FRAGMENTS
+               /* get actual file length from the newest node */
+               if (jNode->version >= latestVersion) {
+                       totalSize = jNode->isize;
+                       latestVersion = jNode->version;
+               }
+#endif
+               if (dest || stat) {
+                       char *src, *dst;
+                       char data[4096 + sizeof(struct jffs2_raw_inode)];
+                       struct jffs2_raw_inode *inode;
+                       size_t len;
+
+                       inode = (struct jffs2_raw_inode *)&data;
+                       len = sizeof(struct jffs2_raw_inode);
+                       if (dest)
+                               len += jNode->csize;
+                       nand_read(nand, jNode->offset, &len, inode);
+                       /* ignore data behind latest known EOF */
+                       if (inode->offset > totalSize)
+                               continue;
+
+                       if (stat) {
+                               stat->st_mtime = inode->mtime;
+                               stat->st_mode = inode->mode;
+                               stat->st_ino = inode->ino;
+                               stat->st_size = totalSize;
+                       }
+
+                       if (!dest)
+                               continue;
+
+                       src = ((char *) inode) + sizeof(struct jffs2_raw_inode);
+                       dst = (char *) (dest + inode->offset);
+
+                       switch (inode->compr) {
+                       case JFFS2_COMPR_NONE:
+                               ret = 0;
+                               memcpy(dst, src, inode->dsize);
+                               break;
+                       case JFFS2_COMPR_ZERO:
+                               ret = 0;
+                               memset(dst, 0, inode->dsize);
+                               break;
+                       case JFFS2_COMPR_RTIME:
+                               ret = 0;
+                               rtime_decompress(src, dst, inode->csize, inode->dsize);
+                               break;
+                       case JFFS2_COMPR_DYNRUBIN:
+                               /* this is slow but it works */
+                               ret = 0;
+                               dynrubin_decompress(src, dst, inode->csize, inode->dsize);
+                               break;
+                       case JFFS2_COMPR_ZLIB:
+                               ret = zlib_decompress(src, dst, inode->csize, inode->dsize);
+                               break;
+#if defined(CONFIG_JFFS2_LZO_LZARI)
+                       case JFFS2_COMPR_LZO:
+                               ret = lzo_decompress(src, dst, inode->csize, inode->dsize);
+                               break;
+                       case JFFS2_COMPR_LZARI:
+                               ret = lzari_decompress(src, dst, inode->csize, inode->dsize);
+                               break;
+#endif
+                       default:
+                               /* unknown */
+                               putLabeledWord("UNKOWN COMPRESSION METHOD = ", inode->compr);
+                               return -1;
+                       }
+               }
+       }
+
+       return totalSize;
+}
+
+/* find the inode from the slashless name given a parent */
+static u32
+jffs2_1pass_find_inode(struct b_lists * pL, const char *name, u32 pino)
+{
+       struct b_dirent *jDir;
+       int len = strlen(name); /* name is assumed slash free */
+       unsigned int nhash = full_name_hash(name, len);
+       u32 version = 0;
+       u32 inode = 0;
+
+       /* we need to search all and return the inode with the highest version */
+       for (jDir = (struct b_dirent *)pL->dir.listHead; jDir; jDir = jDir->next) {
+               if ((pino == jDir->pino) && (jDir->ino) &&      /* 0 for unlink */
+                   (len == jDir->nsize) && (nhash == jDir->nhash)) {
+                       /* TODO: compare name */
+                       if (jDir->version < version)
+                               continue;
+
+                       if (jDir->version == version && inode != 0) {
+                               /* I'm pretty sure this isn't legal */
+                               putstr(" ** ERROR ** ");
+/*                             putnstr(jDir->name, jDir->nsize); */
+/*                             putLabeledWord(" has dup version =", version); */
+                       }
+                       inode = jDir->ino;
+                       version = jDir->version;
+               }
+       }
+       return inode;
+}
+
+char *mkmodestr(unsigned long mode, char *str)
+{
+       static const char *l = "xwr";
+       int mask = 1, i;
+       char c;
+
+       switch (mode & S_IFMT) {
+               case S_IFDIR:    str[0] = 'd'; break;
+               case S_IFBLK:    str[0] = 'b'; break;
+               case S_IFCHR:    str[0] = 'c'; break;
+               case S_IFIFO:    str[0] = 'f'; break;
+               case S_IFLNK:    str[0] = 'l'; break;
+               case S_IFSOCK:   str[0] = 's'; break;
+               case S_IFREG:    str[0] = '-'; break;
+               default:         str[0] = '?';
+       }
+
+       for(i = 0; i < 9; i++) {
+               c = l[i%3];
+               str[9-i] = (mode & mask)?c:'-';
+               mask = mask<<1;
+       }
+
+       if(mode & S_ISUID) str[3] = (mode & S_IXUSR)?'s':'S';
+       if(mode & S_ISGID) str[6] = (mode & S_IXGRP)?'s':'S';
+       if(mode & S_ISVTX) str[9] = (mode & S_IXOTH)?'t':'T';
+       str[10] = '\0';
+       return str;
+}
+
+static inline void dump_stat(struct stat *st, const char *name)
+{
+       char str[20];
+       char s[64], *p;
+
+       if (st->st_mtime == (time_t)(-1)) /* some ctimes really hate -1 */
+               st->st_mtime = 1;
+
+       ctime_r(&st->st_mtime, s/*,64*/); /* newlib ctime doesn't have buflen */
+
+       if ((p = strchr(s,'\n')) != NULL) *p = '\0';
+       if ((p = strchr(s,'\r')) != NULL) *p = '\0';
+
+/*
+       printf("%6lo %s %8ld %s %s\n", st->st_mode, mkmodestr(st->st_mode, str),
+               st->st_size, s, name);
+*/
+
+       printf(" %s %8ld %s %s", mkmodestr(st->st_mode,str), st->st_size, s, name);
+}
+
+static inline int
+dump_inode(struct b_lists *pL, struct b_dirent *d, struct b_inode *i)
+{
+       char fname[JFFS2_MAX_NAME_LEN + 1];
+       struct stat st;
+       size_t len;
+
+       if(!d || !i) return -1;
+       len = d->nsize;
+       nand_read(nand, d->offset + sizeof(struct jffs2_raw_dirent),
+                 &len, &fname);
+       fname[d->nsize] = '\0';
+
+       memset(&st, 0, sizeof(st));
+
+       jffs2_1pass_read_inode(pL, i->ino, NULL, &st);
+
+       dump_stat(&st, fname);
+/* FIXME
+       if (d->type == DT_LNK) {
+               unsigned char *src = (unsigned char *) (&i[1]);
+               putstr(" -> ");
+               putnstr(src, (int)i->dsize);
+       }
+*/
+       putstr("\r\n");
+
+       return 0;
+}
+
+/* list inodes with the given pino */
+static u32
+jffs2_1pass_list_inodes(struct b_lists * pL, u32 pino)
+{
+       struct b_dirent *jDir;
+       u32 i_version = 0;
+
+       for (jDir = (struct b_dirent *)pL->dir.listHead; jDir; jDir = jDir->next) {
+               if ((pino == jDir->pino) && (jDir->ino)) { /* ino=0 -> unlink */
+                       struct b_inode *jNode = (struct b_inode *)pL->frag.listHead;
+                       struct b_inode *i = NULL;
+
+                       while (jNode) {
+                               if (jNode->ino == jDir->ino && jNode->version >= i_version) {
+                                       i_version = jNode->version;
+                                       i = jNode;
+                               }
+                               jNode = jNode->next;
+                       }
+                       dump_inode(pL, jDir, i);
+               }
+       }
+       return pino;
+}
+
+static u32
+jffs2_1pass_search_inode(struct b_lists * pL, const char *fname, u32 pino)
+{
+       int i;
+       char tmp[256];
+       char working_tmp[256];
+       char *c;
+
+       /* discard any leading slash */
+       i = 0;
+       while (fname[i] == '/')
+               i++;
+       strcpy(tmp, &fname[i]);
+
+       while ((c = (char *) strchr(tmp, '/'))) /* we are still dired searching */
+       {
+               strncpy(working_tmp, tmp, c - tmp);
+               working_tmp[c - tmp] = '\0';
+#if 0
+               putstr("search_inode: tmp = ");
+               putstr(tmp);
+               putstr("\r\n");
+               putstr("search_inode: wtmp = ");
+               putstr(working_tmp);
+               putstr("\r\n");
+               putstr("search_inode: c = ");
+               putstr(c);
+               putstr("\r\n");
+#endif
+               for (i = 0; i < strlen(c) - 1; i++)
+                       tmp[i] = c[i + 1];
+               tmp[i] = '\0';
+#if 0
+               putstr("search_inode: post tmp = ");
+               putstr(tmp);
+               putstr("\r\n");
+#endif
+
+               if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino))) {
+                       putstr("find_inode failed for name=");
+                       putstr(working_tmp);
+                       putstr("\r\n");
+                       return 0;
+               }
+       }
+       /* this is for the bare filename, directories have already been mapped */
+       if (!(pino = jffs2_1pass_find_inode(pL, tmp, pino))) {
+               putstr("find_inode failed for name=");
+               putstr(tmp);
+               putstr("\r\n");
+               return 0;
+       }
+       return pino;
+
+}
+
+static u32
+jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino)
+{
+       struct b_dirent *jDir;
+       struct b_inode *jNode;
+       u8 jDirFoundType = 0;
+       u32 jDirFoundIno = 0;
+       u32 jDirFoundPino = 0;
+       char tmp[JFFS2_MAX_NAME_LEN + 1];
+       u32 version = 0;
+       u32 pino;
+
+       /* we need to search all and return the inode with the highest version */
+       for (jDir = (struct b_dirent *)pL->dir.listHead; jDir; jDir = jDir->next) {
+               if (ino == jDir->ino) {
+                       if (jDir->version < version)
+                               continue;
+
+                       if (jDir->version == version && jDirFoundType) {
+                               /* I'm pretty sure this isn't legal */
+                               putstr(" ** ERROR ** ");
+/*                             putnstr(jDir->name, jDir->nsize); */
+/*                             putLabeledWord(" has dup version (resolve) = ", */
+/*                                     version); */
+                       }
+
+                       jDirFoundType = jDir->type;
+                       jDirFoundIno = jDir->ino;
+                       jDirFoundPino = jDir->pino;
+                       version = jDir->version;
+               }
+       }
+       /* now we found the right entry again. (shoulda returned inode*) */
+       if (jDirFoundType != DT_LNK)
+               return jDirFoundIno;
+
+       /* it's a soft link so we follow it again. */
+       for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) {
+               if (jNode->ino == jDirFoundIno) {
+                       size_t len = jNode->csize;
+                       nand_read(nand, jNode->offset + sizeof(struct jffs2_raw_inode), &len, &tmp);
+                       tmp[jNode->csize] = '\0';
+                       break;
+               }
+       }
+       /* ok so the name of the new file to find is in tmp */
+       /* if it starts with a slash it is root based else shared dirs */
+       if (tmp[0] == '/')
+               pino = 1;
+       else
+               pino = jDirFoundPino;
+
+       return jffs2_1pass_search_inode(pL, tmp, pino);
+}
+
+static u32
+jffs2_1pass_search_list_inodes(struct b_lists * pL, const char *fname, u32 pino)
+{
+       int i;
+       char tmp[256];
+       char working_tmp[256];
+       char *c;
+
+       /* discard any leading slash */
+       i = 0;
+       while (fname[i] == '/')
+               i++;
+       strcpy(tmp, &fname[i]);
+       working_tmp[0] = '\0';
+       while ((c = (char *) strchr(tmp, '/'))) /* we are still dired searching */
+       {
+               strncpy(working_tmp, tmp, c - tmp);
+               working_tmp[c - tmp] = '\0';
+               for (i = 0; i < strlen(c) - 1; i++)
+                       tmp[i] = c[i + 1];
+               tmp[i] = '\0';
+               /* only a failure if we arent looking at top level */
+               if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino)) &&
+                   (working_tmp[0])) {
+                       putstr("find_inode failed for name=");
+                       putstr(working_tmp);
+                       putstr("\r\n");
+                       return 0;
+               }
+       }
+
+       if (tmp[0] && !(pino = jffs2_1pass_find_inode(pL, tmp, pino))) {
+               putstr("find_inode failed for name=");
+               putstr(tmp);
+               putstr("\r\n");
+               return 0;
+       }
+       /* this is for the bare filename, directories have already been mapped */
+       if (!(pino = jffs2_1pass_list_inodes(pL, pino))) {
+               putstr("find_inode failed for name=");
+               putstr(tmp);
+               putstr("\r\n");
+               return 0;
+       }
+       return pino;
+
+}
+
+unsigned char
+jffs2_1pass_rescan_needed(struct part_info *part)
+{
+       struct b_node *b;
+       struct jffs2_unknown_node onode;
+       struct jffs2_unknown_node *node;
+       struct b_lists *pL = (struct b_lists *)part->jffs2_priv;
+
+       if (part->jffs2_priv == 0){
+               DEBUGF ("rescan: First time in use\n");
+               return 1;
+       }
+       /* if we have no list, we need to rescan */
+       if (pL->frag.listCount == 0) {
+               DEBUGF ("rescan: fraglist zero\n");
+               return 1;
+       }
+
+       /* or if we are scanning a new partition */
+       if (pL->partOffset != part->offset) {
+               DEBUGF ("rescan: different partition\n");
+               return 1;
+       }
+
+       /* FIXME */
+#if 0
+       /* but suppose someone reflashed a partition at the same offset... */
+       b = pL->dir.listHead;
+       while (b) {
+               node = (struct jffs2_unknown_node *) get_fl_mem(b->offset,
+                       sizeof(onode), &onode);
+               if (node->nodetype != JFFS2_NODETYPE_DIRENT) {
+                       DEBUGF ("rescan: fs changed beneath me? (%lx)\n",
+                                       (unsigned long) b->offset);
+                       return 1;
+               }
+               b = b->next;
+       }
+#endif
+       return 0;
+}
+
+#ifdef DEBUG_FRAGMENTS
+static void
+dump_fragments(struct b_lists *pL)
+{
+       struct b_node *b;
+       struct jffs2_raw_inode ojNode;
+       struct jffs2_raw_inode *jNode;
+
+       putstr("\r\n\r\n******The fragment Entries******\r\n");
+       b = pL->frag.listHead;
+       while (b) {
+               jNode = (struct jffs2_raw_inode *) get_fl_mem(b->offset,
+                       sizeof(ojNode), &ojNode);
+               putLabeledWord("\r\n\tbuild_list: FLASH_OFFSET = ", b->offset);
+               putLabeledWord("\tbuild_list: totlen = ", jNode->totlen);
+               putLabeledWord("\tbuild_list: inode = ", jNode->ino);
+               putLabeledWord("\tbuild_list: version = ", jNode->version);
+               putLabeledWord("\tbuild_list: isize = ", jNode->isize);
+               putLabeledWord("\tbuild_list: atime = ", jNode->atime);
+               putLabeledWord("\tbuild_list: offset = ", jNode->offset);
+               putLabeledWord("\tbuild_list: csize = ", jNode->csize);
+               putLabeledWord("\tbuild_list: dsize = ", jNode->dsize);
+               putLabeledWord("\tbuild_list: compr = ", jNode->compr);
+               putLabeledWord("\tbuild_list: usercompr = ", jNode->usercompr);
+               putLabeledWord("\tbuild_list: flags = ", jNode->flags);
+               putLabeledWord("\tbuild_list: offset = ", b->offset);   /* FIXME: ? [RS] */
+               b = b->next;
+       }
+}
+#endif
+
+#ifdef DEBUG_DIRENTS
+static void
+dump_dirents(struct b_lists *pL)
+{
+       struct b_node *b;
+       struct jffs2_raw_dirent *jDir;
+
+       putstr("\r\n\r\n******The directory Entries******\r\n");
+       b = pL->dir.listHead;
+       while (b) {
+               jDir = (struct jffs2_raw_dirent *) get_node_mem(b->offset);
+               putstr("\r\n");
+               putnstr(jDir->name, jDir->nsize);
+               putLabeledWord("\r\n\tbuild_list: magic = ", jDir->magic);
+               putLabeledWord("\tbuild_list: nodetype = ", jDir->nodetype);
+               putLabeledWord("\tbuild_list: hdr_crc = ", jDir->hdr_crc);
+               putLabeledWord("\tbuild_list: pino = ", jDir->pino);
+               putLabeledWord("\tbuild_list: version = ", jDir->version);
+               putLabeledWord("\tbuild_list: ino = ", jDir->ino);
+               putLabeledWord("\tbuild_list: mctime = ", jDir->mctime);
+               putLabeledWord("\tbuild_list: nsize = ", jDir->nsize);
+               putLabeledWord("\tbuild_list: type = ", jDir->type);
+               putLabeledWord("\tbuild_list: node_crc = ", jDir->node_crc);
+               putLabeledWord("\tbuild_list: name_crc = ", jDir->name_crc);
+               putLabeledWord("\tbuild_list: offset = ", b->offset);   /* FIXME: ? [RS] */
+               b = b->next;
+               put_fl_mem(jDir);
+       }
+}
+#endif
+
+static int
+jffs2_fill_scan_buf(nand_info_t *nand, unsigned char *buf,
+                   unsigned ofs, unsigned len)
+{
+       int ret;
+       unsigned olen;
+
+       olen = len;
+       ret = nand_read(nand, ofs, &olen, buf);
+       if (ret) {
+               printf("nand_read(0x%x bytes from 0x%x) returned %d\n", len, ofs, ret);
+               return ret;
+       }
+       if (olen < len) {
+               printf("Read at 0x%x gave only 0x%x bytes\n", ofs, olen);
+               return -1;
+       }
+       return 0;
+}
+
+#define        EMPTY_SCAN_SIZE 1024
+static u32
+jffs2_1pass_build_lists(struct part_info * part)
+{
+       struct b_lists *pL;
+       struct jffs2_unknown_node *node;
+       unsigned nr_blocks, sectorsize, ofs, offset;
+       char *buf;
+       int i;
+       u32 counter = 0;
+       u32 counter4 = 0;
+       u32 counterF = 0;
+       u32 counterN = 0;
+
+       struct mtdids *id = part->dev->id;
+       nand = nand_info + id->num;
+
+       /* if we are building a list we need to refresh the cache. */
+       jffs_init_1pass_list(part);
+       pL = (struct b_lists *)part->jffs2_priv;
+       pL->partOffset = part->offset;
+       puts ("Scanning JFFS2 FS:   ");
+
+       sectorsize = nand->erasesize;
+       nr_blocks = part->size / sectorsize;
+       buf = malloc(sectorsize);
+       if (!buf)
+               return 0;
+
+       for (i = 0; i < nr_blocks; i++) {
+               printf("\b\b%c ", spinner[counter++ % sizeof(spinner)]);
+
+               offset = part->offset + i * sectorsize;
+
+               if (nand_block_isbad(nand, offset))
+                       continue;
+
+               if (jffs2_fill_scan_buf(nand, buf, offset, EMPTY_SCAN_SIZE))
+                       return 0;
+
+               ofs = 0;
+               /* Scan only 4KiB of 0xFF before declaring it's empty */
+               while (ofs < EMPTY_SCAN_SIZE && *(uint32_t *)(&buf[ofs]) == 0xFFFFFFFF)
+                       ofs += 4;
+               if (ofs == EMPTY_SCAN_SIZE)
+                       continue;
+
+               if (jffs2_fill_scan_buf(nand, buf + EMPTY_SCAN_SIZE, offset + EMPTY_SCAN_SIZE, sectorsize - EMPTY_SCAN_SIZE))
+                       return 0;
+               offset += ofs;
+
+               while (ofs < sectorsize - sizeof(struct jffs2_unknown_node)) {
+                       node = (struct jffs2_unknown_node *)&buf[ofs];
+                       if (node->magic != JFFS2_MAGIC_BITMASK || !hdr_crc(node)) {
+                               offset += 4;
+                               ofs += 4;
+                               counter4++;
+                               continue;
+                       }
+                       /* if its a fragment add it */
+                       if (node->nodetype == JFFS2_NODETYPE_INODE &&
+                                   inode_crc((struct jffs2_raw_inode *) node)) {
+                               if (insert_inode(&pL->frag, (struct jffs2_raw_inode *) node,
+                                                offset) == NULL) {
+                                       return 0;
+                               }
+                       } else if (node->nodetype == JFFS2_NODETYPE_DIRENT &&
+                                  dirent_crc((struct jffs2_raw_dirent *) node)  &&
+                                  dirent_name_crc((struct jffs2_raw_dirent *) node)) {
+                               if (! (counterN%100))
+                                       puts ("\b\b.  ");
+                               if (insert_dirent(&pL->dir, (struct jffs2_raw_dirent *) node,
+                                                 offset) == NULL) {
+                                       return 0;
+                               }
+                               counterN++;
+                       } else if (node->nodetype == JFFS2_NODETYPE_CLEANMARKER) {
+                               if (node->totlen != sizeof(struct jffs2_unknown_node))
+                                       printf("OOPS Cleanmarker has bad size "
+                                               "%d != %d\n", node->totlen,
+                                               sizeof(struct jffs2_unknown_node));
+                       } else if (node->nodetype == JFFS2_NODETYPE_PADDING) {
+                               if (node->totlen < sizeof(struct jffs2_unknown_node))
+                                       printf("OOPS Padding has bad size "
+                                               "%d < %d\n", node->totlen,
+                                               sizeof(struct jffs2_unknown_node));
+                       } else {
+                               printf("Unknown node type: %x len %d "
+                                       "offset 0x%x\n", node->nodetype,
+                                       node->totlen, offset);
+                       }
+                       offset += ((node->totlen + 3) & ~3);
+                       ofs += ((node->totlen + 3) & ~3);
+                       counterF++;
+               }
+       }
+
+       putstr("\b\b done.\r\n");               /* close off the dots */
+
+#if 0
+       putLabeledWord("dir entries = ", pL->dir.listCount);
+       putLabeledWord("frag entries = ", pL->frag.listCount);
+       putLabeledWord("+4 increments = ", counter4);
+       putLabeledWord("+file_offset increments = ", counterF);
+#endif
+
+#ifdef DEBUG_DIRENTS
+       dump_dirents(pL);
+#endif
+
+#ifdef DEBUG_FRAGMENTS
+       dump_fragments(pL);
+#endif
+
+       /* give visual feedback that we are done scanning the flash */
+       led_blink(0x0, 0x0, 0x1, 0x1);  /* off, forever, on 100ms, off 100ms */
+       free(buf);
+
+       return 1;
+}
+
+
+static u32
+jffs2_1pass_fill_info(struct b_lists * pL, struct b_jffs2_info * piL)
+{
+       struct b_node *b;
+       struct jffs2_raw_inode ojNode;
+       struct jffs2_raw_inode *jNode;
+       int i;
+
+       for (i = 0; i < JFFS2_NUM_COMPR; i++) {
+               piL->compr_info[i].num_frags = 0;
+               piL->compr_info[i].compr_sum = 0;
+               piL->compr_info[i].decompr_sum = 0;
+       }
+/*     FIXME
+       b = pL->frag.listHead;
+       while (b) {
+               jNode = (struct jffs2_raw_inode *) get_fl_mem(b->offset,
+                       sizeof(ojNode), &ojNode);
+               if (jNode->compr < JFFS2_NUM_COMPR) {
+                       piL->compr_info[jNode->compr].num_frags++;
+                       piL->compr_info[jNode->compr].compr_sum += jNode->csize;
+                       piL->compr_info[jNode->compr].decompr_sum += jNode->dsize;
+               }
+               b = b->next;
+       }
+*/
+       return 0;
+}
+
+
+static struct b_lists *
+jffs2_get_list(struct part_info * part, const char *who)
+{
+       if (jffs2_1pass_rescan_needed(part)) {
+               if (!jffs2_1pass_build_lists(part)) {
+                       printf("%s: Failed to scan JFFSv2 file structure\n", who);
+                       return NULL;
+               }
+       }
+       return (struct b_lists *)part->jffs2_priv;
+}
+
+
+/* Print directory / file contents */
+u32
+jffs2_1pass_ls(struct part_info * part, const char *fname)
+{
+       struct b_lists *pl;
+       long ret = 0;
+       u32 inode;
+
+       if (! (pl = jffs2_get_list(part, "ls")))
+               return 0;
+
+       if (! (inode = jffs2_1pass_search_list_inodes(pl, fname, 1))) {
+               putstr("ls: Failed to scan jffs2 file structure\r\n");
+               return 0;
+       }
+
+#if 0
+       putLabeledWord("found file at inode = ", inode);
+       putLabeledWord("read_inode returns = ", ret);
+#endif
+
+       return ret;
+}
+
+
+/* Load a file from flash into memory. fname can be a full path */
+u32
+jffs2_1pass_load(char *dest, struct part_info * part, const char *fname)
+{
+
+       struct b_lists *pl;
+       long ret = 0;
+       u32 inode;
+
+       if (! (pl = jffs2_get_list(part, "load")))
+               return 0;
+
+       if (! (inode = jffs2_1pass_search_inode(pl, fname, 1))) {
+               putstr("load: Failed to find inode\r\n");
+               return 0;
+       }
+
+       /* Resolve symlinks */
+       if (! (inode = jffs2_1pass_resolve_inode(pl, inode))) {
+               putstr("load: Failed to resolve inode structure\r\n");
+               return 0;
+       }
+
+       if ((ret = jffs2_1pass_read_inode(pl, inode, dest, NULL)) < 0) {
+               putstr("load: Failed to read inode\r\n");
+               return 0;
+       }
+
+       DEBUGF ("load: loaded '%s' to 0x%lx (%ld bytes)\n", fname,
+                               (unsigned long) dest, ret);
+       return ret;
+}
+
+/* Return information about the fs on this partition */
+u32
+jffs2_1pass_info(struct part_info * part)
+{
+       struct b_jffs2_info info;
+       struct b_lists *pl;
+       int i;
+
+       if (! (pl = jffs2_get_list(part, "info")))
+               return 0;
+
+       jffs2_1pass_fill_info(pl, &info);
+       for (i = 0; i < JFFS2_NUM_COMPR; i++) {
+               printf ("Compression: %s\n"
+                       "\tfrag count: %d\n"
+                       "\tcompressed sum: %d\n"
+                       "\tuncompressed sum: %d\n",
+                       compr_names[i],
+                       info.compr_info[i].num_frags,
+                       info.compr_info[i].compr_sum,
+                       info.compr_info[i].decompr_sum);
+       }
+       return 1;
+}
+
+#endif /* CFG_CMD_JFFS2 */

diff --git a/fs/jffs2/jffs2_nand_private.h b/fs/jffs2/jffs2_nand_private.h
new file mode 100644 (file)
index 0000000..18cca8d
--- /dev/null
+++ b/fs/jffs2/jffs2_nand_private.h
@@ -0,0 +1,133 @@
+#ifndef jffs2_private_h
+#define jffs2_private_h
+
+#include <jffs2/jffs2.h>
+
+struct b_node {
+       struct b_node *next;
+};
+
+struct b_inode {
+       struct b_inode *next;
+       u32 offset;     /* physical offset to beginning of real inode */
+       u32 version;
+       u32 ino;
+       u32 isize;
+       u32 csize;
+};
+
+struct b_dirent {
+       struct b_dirent *next;
+       u32 offset;     /* physical offset to beginning of real dirent */
+       u32 version;
+       u32 pino;
+       u32 ino;
+       unsigned int nhash;
+       unsigned char nsize;
+       unsigned char type;
+};
+
+struct b_list {
+       struct b_node *listTail;
+       struct b_node *listHead;
+       unsigned int listCount;
+       struct mem_block *listMemBase;
+};
+
+struct b_lists {
+       char *partOffset;
+       struct b_list dir;
+       struct b_list frag;
+};
+
+struct b_compr_info {
+       u32 num_frags;
+       u32 compr_sum;
+       u32 decompr_sum;
+};
+
+struct b_jffs2_info {
+       struct b_compr_info compr_info[JFFS2_NUM_COMPR];
+};
+
+static inline int
+hdr_crc(struct jffs2_unknown_node *node)
+{
+#if 1
+       u32 crc = crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4);
+#else
+       /* what's the semantics of this? why is this here? */
+       u32 crc = crc32_no_comp(~0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4);
+
+       crc ^= ~0;
+#endif
+       if (node->hdr_crc != crc) {
+               return 0;
+       } else {
+               return 1;
+       }
+}
+
+static inline int
+dirent_crc(struct jffs2_raw_dirent *node)
+{
+       if (node->node_crc != crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_raw_dirent) - 8)) {
+               return 0;
+       } else {
+               return 1;
+       }
+}
+
+static inline int
+dirent_name_crc(struct jffs2_raw_dirent *node)
+{
+       if (node->name_crc != crc32_no_comp(0, (unsigned char *)&(node->name), node->nsize)) {
+               return 0;
+       } else {
+               return 1;
+       }
+}
+
+static inline int
+inode_crc(struct jffs2_raw_inode *node)
+{
+       if (node->node_crc != crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_raw_inode) - 8)) {
+               return 0;
+       } else {
+               return 1;
+       }
+}
+
+/* Borrowed from include/linux/dcache.h */
+
+/* Name hashing routines. Initial hash value */
+/* Hash courtesy of the R5 hash in reiserfs modulo sign bits */
+#define init_name_hash()               0
+
+/* partial hash update function. Assume roughly 4 bits per character */
+static inline unsigned long
+partial_name_hash(unsigned long c, unsigned long prevhash)
+{
+       return (prevhash + (c << 4) + (c >> 4)) * 11;
+}
+
+/*
+ * Finally: cut down the number of bits to a int value (and try to avoid
+ * losing bits)
+ */
+static inline unsigned long end_name_hash(unsigned long hash)
+{
+       return (unsigned int) hash;
+}
+
+/* Compute the hash for a name string. */
+static inline unsigned int
+full_name_hash(const unsigned char *name, unsigned int len)
+{
+       unsigned long hash = init_name_hash();
+       while (len--)
+               hash = partial_name_hash(*name++, hash);
+       return end_name_hash(hash);
+}
+
+#endif /* jffs2_private.h */

diff --git a/fs/jffs2/jffs2_private.h b/fs/jffs2/jffs2_private.h
index 65ca6eb98f239ab26599ac2a6423b6a04c48d145..46ed644e4d4a6dd795ae70a639484447f660751c 100644 (file)
--- a/fs/jffs2/jffs2_private.h
+++ b/fs/jffs2/jffs2_private.h
@@ -85,4 +85,16 @@ inode_crc(struct jffs2_raw_inode *node)
        }
 }
 
+static inline int
+data_crc(struct jffs2_raw_inode *node)
+{
+       if (node->data_crc != crc32_no_comp(0, (unsigned char *)
+                                           ((int) &node->node_crc + sizeof (node->node_crc)),
+                                            node->csize)) {
+               return 0;
+       } else {
+               return 1;
+       }
+}
+
 #endif /* jffs2_private.h */

diff --git a/include/asm-arm/arch-arm720t/s3c4510b.h b/include/asm-arm/arch-arm720t/s3c4510b.h
index 517b1ada99bbedca8a9bdcbbab16928907895266..73a3b6d856bff813c8e12065e89238705f490e53 100644 (file)
--- a/include/asm-arm/arch-arm720t/s3c4510b.h
+++ b/include/asm-arm/arch-arm720t/s3c4510b.h
@@ -267,8 +267,6 @@ struct _irq_handler {
        void (*m_func)( void *data);
 };
 
-extern struct _irq_handler IRQ_HANDLER[];
-
 #endif
 
 #endif /* __S3C4510_h */

diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index 3ff1d26145c4d7ff5d6b07eac857a9ba49c96934..c8c479a186923d78f057d9a0d8a6089009a1b4e8 100644 (file)
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -92,6 +92,10 @@ typedef struct { volatile u32 offset[4096]; } __regbase;
 #  define __REG2(x,y)  (*(volatile u32 *)((u32)&__REG(x) + (y)))
 # else
 #  define __REG(x) (x)
+#  ifdef CONFIG_CPU_MONAHANS /* Hack to make this work with mona's pxa-regs.h */
+#   define __REG_2(x) (x)
+#   define __REG_3(x) (x)
+#  endif
 # endif
 #endif /* UBOOT_REG_FIX */
 

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 41d37d791a836262003fc6194242b56ea591964a..ebda7192ed07f1f2cc31f0c1a469c48918c7bb09 100644 (file)
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -33,12 +33,21 @@ typedef void                (*ExcpHndlr) (void) ;
 /*
  * PXA Chip selects
  */
+#ifdef CONFIG_CPU_MONAHANS
+#define PXA_CS0_PHYS   0x00000000 /* for both small and large same start */
+#define PXA_CS1_PHYS   0x04000000 /* Small partition start address (64MB) */
+#define PXA_CS1_LPHYS  0x30000000 /* Large partition start address (256MB) */
+#define PXA_CS2_PHYS   0x10000000 /* (64MB) */
+#define PXA_CS3_PHYS   0x14000000 /* (64MB) */
+#define PXA_PCMCIA_PHYS        0x20000000 /* (256MB) */
+#else
 #define PXA_CS0_PHYS   0x00000000
 #define PXA_CS1_PHYS   0x04000000
 #define PXA_CS2_PHYS   0x08000000
 #define PXA_CS3_PHYS   0x0C000000
 #define PXA_CS4_PHYS   0x10000000
 #define PXA_CS5_PHYS   0x14000000
+#endif /* CONFIG_CPU_MONAHANS */
 
 /*
  * Personal Computer Memory Card International Association (PCMCIA) sockets
@@ -49,10 +58,12 @@ typedef void                (*ExcpHndlr) (void) ;
 #define PCMCIAAttrSp   PCMCIAPrtSp     /* PCMCIA Attribute Space [byte]   */
 #define PCMCIAMemSp    PCMCIAPrtSp     /* PCMCIA Memory Space [byte]      */
 
+#ifndef CONFIG_CPU_MONAHANS             /* Monahans supports only one slot */
 #define PCMCIA0Sp      PCMCIASp        /* PCMCIA 0 Space [byte]           */
 #define PCMCIA0IOSp    PCMCIAIOSp      /* PCMCIA 0 I/O Space [byte]       */
 #define PCMCIA0AttrSp  PCMCIAAttrSp    /* PCMCIA 0 Attribute Space [byte] */
 #define PCMCIA0MemSp   PCMCIAMemSp     /* PCMCIA 0 Memory Space [byte]    */
+#endif
 
 #define PCMCIA1Sp      PCMCIASp        /* PCMCIA 1 Space [byte]           */
 #define PCMCIA1IOSp    PCMCIAIOSp      /* PCMCIA 1 I/O Space [byte]       */
@@ -72,10 +83,12 @@ typedef void                (*ExcpHndlr) (void) ;
 #define _PCMCIA0Attr   _PCMCIAAttr (0) /* PCMCIA 0 Attribute              */
 #define _PCMCIA0Mem    _PCMCIAMem (0)  /* PCMCIA 0 Memory                 */
 
+#ifndef CONFIG_CPU_MONAHANS             /* Monahans supports only one slot */
 #define _PCMCIA1       _PCMCIA (1)     /* PCMCIA 1                        */
 #define _PCMCIA1IO     _PCMCIAIO (1)   /* PCMCIA 1 I/O                    */
 #define _PCMCIA1Attr   _PCMCIAAttr (1) /* PCMCIA 1 Attribute              */
 #define _PCMCIA1Mem    _PCMCIAMem (1)  /* PCMCIA 1 Memory                 */
+#endif
 
 /*
  * DMA Controller
@@ -96,6 +109,24 @@ typedef void                (*ExcpHndlr) (void) ;
 #define DCSR13         __REG(0x40000034)  /* DMA Control / Status Register for Channel 13 */
 #define DCSR14         __REG(0x40000038)  /* DMA Control / Status Register for Channel 14 */
 #define DCSR15         __REG(0x4000003c)  /* DMA Control / Status Register for Channel 15 */
+#ifdef CONFIG_CPU_MONAHANS
+#define DCSR16         __REG(0x40000040)  /* DMA Control / Status Register for Channel 16 */
+#define DCSR17         __REG(0x40000044)  /* DMA Control / Status Register for Channel 17 */
+#define DCSR18         __REG(0x40000048)  /* DMA Control / Status Register for Channel 18 */
+#define DCSR19         __REG(0x4000004c)  /* DMA Control / Status Register for Channel 19 */
+#define DCSR20         __REG(0x40000050)  /* DMA Control / Status Register for Channel 20 */
+#define DCSR21         __REG(0x40000054)  /* DMA Control / Status Register for Channel 21 */
+#define DCSR22         __REG(0x40000058)  /* DMA Control / Status Register for Channel 22 */
+#define DCSR23         __REG(0x4000005c)  /* DMA Control / Status Register for Channel 23 */
+#define DCSR24         __REG(0x40000060)  /* DMA Control / Status Register for Channel 24 */
+#define DCSR25         __REG(0x40000064)  /* DMA Control / Status Register for Channel 25 */
+#define DCSR26         __REG(0x40000068)  /* DMA Control / Status Register for Channel 26 */
+#define DCSR27         __REG(0x4000006c)  /* DMA Control / Status Register for Channel 27 */
+#define DCSR28         __REG(0x40000070)  /* DMA Control / Status Register for Channel 28 */
+#define DCSR29         __REG(0x40000074)  /* DMA Control / Status Register for Channel 29 */
+#define DCSR30         __REG(0x40000078)  /* DMA Control / Status Register for Channel 30 */
+#define DCSR31         __REG(0x4000007c)  /* DMA Control / Status Register for Channel 31 */
+#endif /* CONFIG_CPU_MONAHANS */
 
 #define DCSR(x)                __REG2(0x40000000, (x) << 2)
 
@@ -103,7 +134,7 @@ typedef void                (*ExcpHndlr) (void) ;
 #define DCSR_NODESC    (1 << 30)       /* No-Descriptor Fetch (read / write) */
 #define DCSR_STOPIRQEN (1 << 29)       /* Stop Interrupt Enable (read / write) */
 
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS)
 #define DCSR_EORIRQEN  (1 << 28)       /* End of Receive Interrupt Enable (R/W) */
 #define DCSR_EORJMPEN  (1 << 27)       /* Jump to next descriptor on EOR */
 #define DCSR_EORSTOPEN (1 << 26)       /* STOP on an EOR */
@@ -444,11 +475,11 @@ typedef void              (*ExcpHndlr) (void) ;
 #define ICR_ACKNAK     0x4             /* send ACK(0) or NAK(1) */
 #define ICR_TB         0x8             /* transfer byte bit */
 #define ICR_MA         0x10            /* master abort */
-#define ICR_SCLE       0x20            /* master clock enable */
+#define ICR_SCLE       0x20            /* master clock enable, mona SCLEA */
 #define ICR_IUE                0x40            /* unit enable */
 #define ICR_GCD                0x80            /* general call disable */
 #define ICR_ITEIE      0x100           /* enable tx interrupts */
-#define ICR_IRFIE      0x200           /* enable rx interrupts */
+#define ICR_IRFIE      0x200           /* enable rx interrupts, mona: DRFIE */
 #define ICR_BEIE       0x400           /* enable bus error ints */
 #define ICR_SSDIE      0x800           /* slave STOP detected int enable */
 #define ICR_ALDIE      0x1000          /* enable arbitration interrupt */
@@ -790,21 +821,21 @@ typedef void              (*ExcpHndlr) (void) ;
 #define RTAR           __REG(0x40900004)  /* RTC Alarm Register */
 #define RTSR           __REG(0x40900008)  /* RTC Status Register */
 #define RTTR           __REG(0x4090000C)  /* RTC Timer Trim Register */
-#define RDAR1     __REG(0x40900018)  /* Wristwatch Day Alarm Reg 1 */
-#define RDAR2     __REG(0x40900020)  /* Wristwatch Day Alarm Reg 2 */
-#define RYAR1     __REG(0x4090001C)  /* Wristwatch Year Alarm Reg 1 */
-#define RYAR2     __REG(0x40900024)  /* Wristwatch Year Alarm Reg 2 */
-#define SWAR1     __REG(0x4090002C)  /* Stopwatch Alarm Register 1 */
-#define SWAR2     __REG(0x40900030)  /* Stopwatch Alarm Register 2 */
-#define PIAR      __REG(0x40900038)  /* Periodic Interrupt Alarm Register */
-#define RDCR      __REG(0x40900010)  /* RTC Day Count Register. */
-#define RYCR      __REG(0x40900014)  /* RTC Year Count Register. */
-#define SWCR      __REG(0x40900028)  /* Stopwatch Count Register */
-#define RTCPICR           __REG(0x40900034)  /* Periodic Interrupt Counter Register */
-
-#define RTSR_PICE  (1 << 15)   /* Peridoc interrupt count enable */
-#define RTSR_PIALE (1 << 14)   /* Peridoc interrupt Alarm enable */
-#define RTSR_PIAL  (1 << 13)   /* Peridoc  interrupt Alarm status */
+#define RDAR1          __REG(0x40900018)  /* Wristwatch Day Alarm Reg 1 */
+#define RDAR2          __REG(0x40900020)  /* Wristwatch Day Alarm Reg 2 */
+#define RYAR1          __REG(0x4090001C)  /* Wristwatch Year Alarm Reg 1 */
+#define RYAR2          __REG(0x40900024)  /* Wristwatch Year Alarm Reg 2 */
+#define SWAR1          __REG(0x4090002C)  /* Stopwatch Alarm Register 1 */
+#define SWAR2          __REG(0x40900030)  /* Stopwatch Alarm Register 2 */
+#define PIAR           __REG(0x40900038)  /* Periodic Interrupt Alarm Register */
+#define RDCR           __REG(0x40900010)  /* RTC Day Count Register. */
+#define RYCR           __REG(0x40900014)  /* RTC Year Count Register. */
+#define SWCR           __REG(0x40900028)  /* Stopwatch Count Register */
+#define RTCPICR                __REG(0x40900034)  /* Periodic Interrupt Counter Register */
+
+#define RTSR_PICE      (1 << 15)       /* Peridoc interrupt count enable */
+#define RTSR_PIALE     (1 << 14)       /* Peridoc interrupt Alarm enable */
+#define RTSR_PIAL      (1 << 13)       /* Peridoc  interrupt Alarm status */
 #define RTSR_HZE       (1 << 3)        /* HZ interrupt enable */
 #define RTSR_ALE       (1 << 2)        /* RTC alarm interrupt enable */
 #define RTSR_HZ                (1 << 1)        /* HZ rising-edge detected */
@@ -813,15 +844,47 @@ typedef void              (*ExcpHndlr) (void) ;
 /*
  * OS Timer & Match Registers
  */
-#define OSMR0          __REG(0x40A00000)  /* */
-#define OSMR1          __REG(0x40A00004)  /* */
-#define OSMR2          __REG(0x40A00008)  /* */
-#define OSMR3          __REG(0x40A0000C)  /* */
+#define OSMR0          __REG(0x40A00000)  /* OS Timer Match Register 0 */
+#define OSMR1          __REG(0x40A00004)  /* OS Timer Match Register 1 */
+#define OSMR2          __REG(0x40A00008)  /* OS Timer Match Register 2 */
+#define OSMR3          __REG(0x40A0000C)  /* OS Timer Match Register 3 */
 #define OSCR           __REG(0x40A00010)  /* OS Timer Counter Register */
 #define OSSR           __REG(0x40A00014)  /* OS Timer Status Register */
 #define OWER           __REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
 #define OIER           __REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
 
+#ifdef CONFIG_CPU_MONAHANS
+#define OSCR4          __REG(0x40A00040)  /* OS Timer Counter Register 4 */
+#define OSCR5          __REG(0x40A00044)  /* OS Timer Counter Register 5 */
+#define OSCR6          __REG(0x40A00048)  /* OS Timer Counter Register 6 */
+#define OSCR7          __REG(0x40A0004C)  /* OS Timer Counter Register 7 */
+#define OSCR8          __REG(0x40A00050)  /* OS Timer Counter Register 8 */
+#define OSCR9          __REG(0x40A00054)  /* OS Timer Counter Register 9 */
+#define OSCR10         __REG(0x40A00058)  /* OS Timer Counter Register 10 */
+#define OSCR11         __REG(0x40A0005C)  /* OS Timer Counter Register 11 */
+
+#define OSMR4          __REG(0x40A00080)  /* OS Timer Match Register 4 */
+#define OSMR5          __REG(0x40A00084)  /* OS Timer Match Register 5 */
+#define OSMR6          __REG(0x40A00088)  /* OS Timer Match Register 6 */
+#define OSMR7          __REG(0x40A0008C)  /* OS Timer Match Register 7 */
+#define OSMR8          __REG(0x40A00090)  /* OS Timer Match Register 8 */
+#define OSMR9          __REG(0x40A00094)  /* OS Timer Match Register 9 */
+#define OSMR10         __REG(0x40A00098)  /* OS Timer Match Register 10 */
+#define OSMR11         __REG(0x40A0009C)  /* OS Timer Match Register 11 */
+
+#define OMCR4          __REG(0x40A000C0)  /* OS Match Control Register 4 */
+#define OMCR5          __REG(0x40A000C4)  /* OS Match Control Register 5 */
+#define OMCR6          __REG(0x40A000C8)  /* OS Match Control Register 6 */
+#define OMCR7          __REG(0x40A000CC)  /* OS Match Control Register 7 */
+#define OMCR8          __REG(0x40A000D0)  /* OS Match Control Register 8 */
+#define OMCR9          __REG(0x40A000D4)  /* OS Match Control Register 9 */
+#define OMCR10         __REG(0x40A000D8)  /* OS Match Control Register 10 */
+#define OMCR11         __REG(0x40A000DC)  /* OS Match Control Register 11 */
+
+#define OSCR_CLK_FREQ   3.250             /* MHz */
+#endif /* CONFIG_CPU_MONAHANS */
+
+#define OSSR_M4                (1 << 4)        /* Match status channel 4 */
 #define OSSR_M3                (1 << 3)        /* Match status channel 3 */
 #define OSSR_M2                (1 << 2)        /* Match status channel 2 */
 #define OSSR_M1                (1 << 1)        /* Match status channel 1 */
@@ -829,6 +892,7 @@ typedef void                (*ExcpHndlr) (void) ;
 
 #define OWER_WME       (1 << 0)        /* Watchdog Match Enable */
 
+#define OIER_E4                (1 << 4)        /* Interrupt enable channel 4 */
 #define OIER_E3                (1 << 3)        /* Interrupt enable channel 3 */
 #define OIER_E2                (1 << 2)        /* Interrupt enable channel 2 */
 #define OIER_E1                (1 << 1)        /* Interrupt enable channel 1 */
@@ -855,6 +919,20 @@ typedef void               (*ExcpHndlr) (void) ;
 #define ICPR           __REG(0x40D00010)  /* Interrupt Controller Pending Register */
 #define ICCR           __REG(0x40D00014)  /* Interrupt Controller Control Register */
 
+#ifdef CONFIG_CPU_MONAHANS
+#define ICHP           __REG(0x40D00018)  /* Interrupt Controller Highest Priority Register */
+/* Missing: 32 Interrupt priority registers
+ * These are the same as beneath for PXA27x: maybe can be merged if
+ * GPIO Stuff is same too.
+ */
+#define ICIP2          __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2          __REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
+#define ICLR2          __REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
+#define ICFP2          __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2          __REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
+/* Missing: 2 Interrupt priority registers */
+#endif /* CONFIG_CPU_MONAHANS */
+
 /*
  * General Purpose I/O
  */
@@ -886,12 +964,287 @@ typedef void             (*ExcpHndlr) (void) ;
 #define GEDR1          __REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
 #define GEDR2          __REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */
 
+#ifdef CONFIG_CPU_MONAHANS
+#define GPLR3          __REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<127:96> */
+#define GPDR3          __REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<127:96> */
+#define GPSR3          __REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<127:96> */
+#define GPCR3          __REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO<127:96> */
+#define GRER3          __REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
+#define GFER3          __REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
+#define GEDR3          __REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<127:96> */
+
+#define GSDR0          __REG(0x40E00400) /* Bit-wise Set of GPDR[31:0] */
+#define GSDR1          __REG(0x40E00404) /* Bit-wise Set of GPDR[63:32] */
+#define GSDR2          __REG(0x40E00408) /* Bit-wise Set of GPDR[95:64] */
+#define GSDR3          __REG(0x40E0040C) /* Bit-wise Set of GPDR[127:96] */
+
+#define GCDR0          __REG(0x40E00420) /* Bit-wise Clear of GPDR[31:0] */
+#define GCDR1          __REG(0x40E00424) /* Bit-wise Clear of GPDR[63:32] */
+#define GCDR2          __REG(0x40E00428) /* Bit-wise Clear of GPDR[95:64] */
+#define GCDR3          __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */
+
+#define GSRER0         __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */
+#define GSRER1         __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
+#define GSRER2         __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */
+#define GSRER3         __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
+
+#define GCRER0         __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */
+#define GCRER1         __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
+#define GCRER2         __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */
+#define GCRER3         __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
+
+#define GSFER0         __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */
+#define GSFER1         __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
+#define GSFER2         __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */
+#define GSFER3         __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
+
+#define GCFER0         __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */
+#define GCFER1         __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
+#define GCFER2         __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */
+#define GCFER3         __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
+
+#define GSDR(x)                __REG2(0x40E00400, ((x) & 0x60) >> 3)
+#define GCDR(x)                __REG2(0x40300420, ((x) & 0x60) >> 3)
+
+/* Multi-funktion Pin Registers, uncomplete, only:
+ *    - GPIO
+ *    - Data Flash DF_* pins defined.
+ */
+#define GPIO0          __REG(0x40e10124)
+#define GPIO1          __REG(0x40e10128)
+#define GPIO2          __REG(0x40e1012c)
+#define GPIO3          __REG(0x40e10130)
+#define GPIO4          __REG(0x40e10134)
+#define nXCVREN                __REG(0x40e10138)
+
+#define DF_CLE_NOE     __REG(0x40e10204)
+#define DF_ALE_WE1     __REG(0x40e10208)
+
+#define DF_SCLK_E      __REG(0x40e10210)
+#define nBE0           __REG(0x40e10214)
+#define nBE1           __REG(0x40e10218)
+#define DF_ALE_WE2     __REG(0x40e1021c)
+#define DF_INT_RnB     __REG(0x40e10220)
+#define DF_nCS0                __REG(0x40e10224)
+#define DF_nCS1                __REG(0x40e10228)
+#define DF_nWE         __REG(0x40e1022c)
+#define DF_nRE         __REG(0x40e10230)
+#define nLUA           __REG(0x40e10234)
+#define nLLA           __REG(0x40e10238)
+#define DF_ADDR0       __REG(0x40e1023c)
+#define DF_ADDR1       __REG(0x40e10240)
+#define DF_ADDR2       __REG(0x40e10244)
+#define DF_ADDR3       __REG(0x40e10248)
+#define DF_IO0         __REG(0x40e1024c)
+#define DF_IO8         __REG(0x40e10250)
+#define DF_IO1         __REG(0x40e10254)
+#define DF_IO9         __REG(0x40e10258)
+#define DF_IO2         __REG(0x40e1025c)
+#define DF_IO10                __REG(0x40e10260)
+#define DF_IO3         __REG(0x40e10264)
+#define DF_IO11                __REG(0x40e10268)
+#define DF_IO4         __REG(0x40e1026c)
+#define DF_IO12                __REG(0x40e10270)
+#define DF_IO5         __REG(0x40e10274)
+#define DF_IO13                __REG(0x40e10278)
+#define DF_IO6         __REG(0x40e1027c)
+#define DF_IO14                __REG(0x40e10280)
+#define DF_IO7         __REG(0x40e10284)
+#define DF_IO15                __REG(0x40e10288)
+
+#define GPIO5          __REG(0x40e1028c)
+#define GPIO6          __REG(0x40e10290)
+#define GPIO7          __REG(0x40e10294)
+#define GPIO8          __REG(0x40e10298)
+#define GPIO9          __REG(0x40e1029c)
+
+#define GPIO11         __REG(0x40e102a0)
+#define GPIO12         __REG(0x40e102a4)
+#define GPIO13         __REG(0x40e102a8)
+#define GPIO14         __REG(0x40e102ac)
+#define GPIO15         __REG(0x40e102b0)
+#define GPIO16         __REG(0x40e102b4)
+#define GPIO17         __REG(0x40e102b8)
+#define GPIO18         __REG(0x40e102bc)
+#define GPIO19         __REG(0x40e102c0)
+#define GPIO20         __REG(0x40e102c4)
+#define GPIO21         __REG(0x40e102c8)
+#define GPIO22         __REG(0x40e102cc)
+#define GPIO23         __REG(0x40e102d0)
+#define GPIO24         __REG(0x40e102d4)
+#define GPIO25         __REG(0x40e102d8)
+#define GPIO26         __REG(0x40e102dc)
+
+#define GPIO27         __REG(0x40e10400)
+#define GPIO28         __REG(0x40e10404)
+#define GPIO29         __REG(0x40e10408)
+#define GPIO30         __REG(0x40e1040c)
+#define GPIO31         __REG(0x40e10410)
+#define GPIO32         __REG(0x40e10414)
+#define GPIO33         __REG(0x40e10418)
+#define GPIO34         __REG(0x40e1041c)
+#define GPIO35         __REG(0x40e10420)
+#define GPIO36         __REG(0x40e10424)
+#define GPIO37         __REG(0x40e10428)
+#define GPIO38         __REG(0x40e1042c)
+#define GPIO39         __REG(0x40e10430)
+#define GPIO40         __REG(0x40e10434)
+#define GPIO41         __REG(0x40e10438)
+#define GPIO42         __REG(0x40e1043c)
+#define GPIO43         __REG(0x40e10440)
+#define GPIO44         __REG(0x40e10444)
+#define GPIO45         __REG(0x40e10448)
+#define GPIO46         __REG(0x40e1044c)
+#define GPIO47         __REG(0x40e10450)
+#define GPIO48         __REG(0x40e10454)
+
+#define GPIO10         __REG(0x40e10458)
+
+#define GPIO49         __REG(0x40e1045c)
+#define GPIO50         __REG(0x40e10460)
+#define GPIO51         __REG(0x40e10464)
+#define GPIO52         __REG(0x40e10468)
+#define GPIO53         __REG(0x40e1046c)
+#define GPIO54         __REG(0x40e10470)
+#define GPIO55         __REG(0x40e10474)
+#define GPIO56         __REG(0x40e10478)
+#define GPIO57         __REG(0x40e1047c)
+#define GPIO58         __REG(0x40e10480)
+#define GPIO59         __REG(0x40e10484)
+#define GPIO60         __REG(0x40e10488)
+#define GPIO61         __REG(0x40e1048c)
+#define GPIO62         __REG(0x40e10490)
+
+#define GPIO6_2                __REG(0x40e10494)
+#define GPIO7_2                __REG(0x40e10498)
+#define GPIO8_2                __REG(0x40e1049c)
+#define GPIO9_2                __REG(0x40e104a0)
+#define GPIO10_2       __REG(0x40e104a4)
+#define GPIO11_2       __REG(0x40e104a8)
+#define GPIO12_2       __REG(0x40e104ac)
+#define GPIO13_2       __REG(0x40e104b0)
+
+#define GPIO63         __REG(0x40e104b4)
+#define GPIO64         __REG(0x40e104b8)
+#define GPIO65         __REG(0x40e104bc)
+#define GPIO66         __REG(0x40e104c0)
+#define GPIO67         __REG(0x40e104c4)
+#define GPIO68         __REG(0x40e104c8)
+#define GPIO69         __REG(0x40e104cc)
+#define GPIO70         __REG(0x40e104d0)
+#define GPIO71         __REG(0x40e104d4)
+#define GPIO72         __REG(0x40e104d8)
+#define GPIO73         __REG(0x40e104dc)
+
+#define GPIO14_2       __REG(0x40e104e0)
+#define GPIO15_2       __REG(0x40e104e4)
+#define GPIO16_2       __REG(0x40e104e8)
+#define GPIO17_2       __REG(0x40e104ec)
+
+#define GPIO74         __REG(0x40e104f0)
+#define GPIO75         __REG(0x40e104f4)
+#define GPIO76         __REG(0x40e104f8)
+#define GPIO77         __REG(0x40e104fc)
+#define GPIO78         __REG(0x40e10500)
+#define GPIO79         __REG(0x40e10504)
+#define GPIO80         __REG(0x40e10508)
+#define GPIO81         __REG(0x40e1050c)
+#define GPIO82         __REG(0x40e10510)
+#define GPIO83         __REG(0x40e10514)
+#define GPIO84         __REG(0x40e10518)
+#define GPIO85         __REG(0x40e1051c)
+#define GPIO86         __REG(0x40e10520)
+#define GPIO87         __REG(0x40e10524)
+#define GPIO88         __REG(0x40e10528)
+#define GPIO89         __REG(0x40e1052c)
+#define GPIO90         __REG(0x40e10530)
+#define GPIO91         __REG(0x40e10534)
+#define GPIO92         __REG(0x40e10538)
+#define GPIO93         __REG(0x40e1053c)
+#define GPIO94         __REG(0x40e10540)
+#define GPIO95         __REG(0x40e10544)
+#define GPIO96         __REG(0x40e10548)
+#define GPIO97         __REG(0x40e1054c)
+#define GPIO98         __REG(0x40e10550)
+
+#define GPIO99         __REG(0x40e10600)
+#define GPIO100                __REG(0x40e10604)
+#define GPIO101                __REG(0x40e10608)
+#define GPIO102                __REG(0x40e1060c)
+#define GPIO103                __REG(0x40e10610)
+#define GPIO104                __REG(0x40e10614)
+#define GPIO105                __REG(0x40e10618)
+#define GPIO106                __REG(0x40e1061c)
+#define GPIO107                __REG(0x40e10620)
+#define GPIO108                __REG(0x40e10624)
+#define GPIO109                __REG(0x40e10628)
+#define GPIO110                __REG(0x40e1062c)
+#define GPIO111                __REG(0x40e10630)
+#define GPIO112                __REG(0x40e10634)
+
+#define GPIO113                __REG(0x40e10638)
+#define GPIO114                __REG(0x40e1063c)
+#define GPIO115                __REG(0x40e10640)
+#define GPIO116                __REG(0x40e10644)
+#define GPIO117                __REG(0x40e10648)
+#define GPIO118                __REG(0x40e1064c)
+#define GPIO119                __REG(0x40e10650)
+#define GPIO120                __REG(0x40e10654)
+#define GPIO121                __REG(0x40e10658)
+#define GPIO122                __REG(0x40e1065c)
+#define GPIO123                __REG(0x40e10660)
+#define GPIO124                __REG(0x40e10664)
+#define GPIO125                __REG(0x40e10668)
+#define GPIO126                __REG(0x40e1066c)
+#define GPIO127                __REG(0x40e10670)
+
+#define GPIO0_2                __REG(0x40e10674)
+#define GPIO1_2                __REG(0x40e10678)
+#define GPIO2_2                __REG(0x40e1067c)
+#define GPIO3_2                __REG(0x40e10680)
+#define GPIO4_2                __REG(0x40e10684)
+#define GPIO5_2                __REG(0x40e10688)
+
+/* MFPR Bit Definitions, see 4-10, Vol. 1 */
+#define PULL_SEL       0x8000
+#define PULLUP_EN      0x4000
+#define PULLDOWN_EN    0x2000
+
+#define DRIVE_FAST_1mA 0x0
+#define DRIVE_FAST_2mA 0x400
+#define DRIVE_FAST_3mA 0x800
+#define DRIVE_FAST_4mA 0xC00
+#define DRIVE_SLOW_6mA 0x1000
+#define DRIVE_FAST_6mA 0x1400
+#define DRIVE_SLOW_10mA        0x1800
+#define DRIVE_FAST_10mA        0x1C00
+
+#define SLEEP_SEL      0x200
+#define SLEEP_DATA     0x100
+#define SLEEP_OE_N     0x80
+#define EDGE_CLEAR     0x40
+#define EDGE_FALL_EN   0x20
+#define EDGE_RISE_EN   0x10
+
+#define AF_SEL_0       0x0     /* Alternate function 0 (reset state) */
+#define AF_SEL_1       0x1     /* Alternate function 1 */
+#define AF_SEL_2       0x2     /* Alternate function 2 */
+#define AF_SEL_3       0x3     /* Alternate function 3 */
+#define AF_SEL_4       0x4     /* Alternate function 4 */
+#define AF_SEL_5       0x5     /* Alternate function 5 */
+#define AF_SEL_6       0x6     /* Alternate function 6 */
+#define AF_SEL_7       0x7     /* Alternate function 7 */
+
+
+#else /* CONFIG_CPU_MONAHANS */
+
 #define GAFR0_L                __REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
 #define GAFR0_U                __REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
 #define GAFR1_L                __REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
 #define GAFR1_U                __REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
 #define GAFR2_L                __REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
 #define GAFR2_U                __REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO 80 */
+#endif /* CONFIG_CPU_MONAHANS */
 
 /* More handy macros.  The argument is a literal GPIO number. */
 
@@ -1136,12 +1489,85 @@ typedef void            (*ExcpHndlr) (void) ;
 #define GPIO79_nCS_3_MD                (79 | GPIO_ALT_FN_2_OUT)
 #define GPIO80_nCS_4_MD                (80 | GPIO_ALT_FN_2_OUT)
 
-#define GPIO117_SCL         (117 | GPIO_ALT_FN_1_OUT)
-#define GPIO118_SDA         (118 | GPIO_ALT_FN_1_OUT)
+#define GPIO117_SCL            (117 | GPIO_ALT_FN_1_OUT)
+#define GPIO118_SDA            (118 | GPIO_ALT_FN_1_OUT)
 
 /*
  * Power Manager
  */
+#ifdef CONFIG_CPU_MONAHANS
+
+#define ASCR           __REG(0x40F40000)  /* Application Subsystem Power Status/Control Register */
+#define ARSR           __REG(0x40F40004)  /* Application Subsystem Reset Status Register */
+#define AD3ER          __REG(0x40F40008)  /* Application Subsystem D3 state Wakeup Enable Register */
+#define AD3SR          __REG(0x40F4000C)  /* Application Subsystem D3 state Wakeup Status Register */
+#define AD2D0ER                __REG(0x40F40010)  /* Application Subsystem D2 to D0 state Wakeup Enable Register */
+#define AD2D0SR                __REG(0x40F40014)  /* Application Subsystem D2 to D0 state Wakeup Status Register */
+#define AD2D1ER                __REG(0x40F40018)  /* Application Subsystem D2 to D1 state Wakeup Enable Register */
+#define AD2D1SR                __REG(0x40F4001C)  /* Application Subsystem D2 to D1 state Wakeup Status Register */
+#define AD1D0ER                __REG(0x40F40020)  /* Application Subsystem D1 to D0 state Wakeup Enable Register */
+#define AD1D0SR                __REG(0x40F40024)  /* Application Subsystem D1 to D0 state Wakeup Status Register */
+#define ASDCNT         __REG(0x40F40028)  /* Application Subsystem SRAM Drowsy Count Register */
+#define AD3R           __REG(0x40F40030)  /* Application Subsystem D3 State Configuration Register */
+#define AD2R           __REG(0x40F40034)  /* Application Subsystem D2 State Configuration Register */
+#define AD1R           __REG(0x40F40038)  /* Application Subsystem D1 State Configuration Register */
+
+#define PMCR           __REG(0x40F50000)  /* Power Manager Control Register */
+#define PSR            __REG(0x40F50004)  /* Power Manager S2 Status Register */
+#define PSPR           __REG(0x40F50008)  /* Power Manager Scratch Pad Register */
+#define PCFR           __REG(0x40F5000C)  /* Power Manager General Configuration Register */
+#define PWER           __REG(0x40F50010)  /* Power Manager Wake-up Enable Register */
+#define PWSR           __REG(0x40F50014)  /* Power Manager Wake-up Status Register */
+#define PECR           __REG(0x40F50018)  /* Power Manager EXT_WAKEUP[1:0] Control Register */
+#define DCDCSR         __REG(0x40F50080)  /* DC-DC Controller Status Register */
+#define PVCR           __REG(0x40F50100)  /* Power Manager Voltage Change Control Register */
+#define    PCMD(x) __REG(0x40F50110 + x*4)
+#define    PCMD0   __REG(0x40F50110 + 0 * 4)
+#define    PCMD1   __REG(0x40F50110 + 1 * 4)
+#define    PCMD2   __REG(0x40F50110 + 2 * 4)
+#define    PCMD3   __REG(0x40F50110 + 3 * 4)
+#define    PCMD4   __REG(0x40F50110 + 4 * 4)
+#define    PCMD5   __REG(0x40F50110 + 5 * 4)
+#define    PCMD6   __REG(0x40F50110 + 6 * 4)
+#define    PCMD7   __REG(0x40F50110 + 7 * 4)
+#define    PCMD8   __REG(0x40F50110 + 8 * 4)
+#define    PCMD9   __REG(0x40F50110 + 9 * 4)
+#define    PCMD10  __REG(0x40F50110 + 10 * 4)
+#define    PCMD11  __REG(0x40F50110 + 11 * 4)
+#define    PCMD12  __REG(0x40F50110 + 12 * 4)
+#define    PCMD13  __REG(0x40F50110 + 13 * 4)
+#define    PCMD14  __REG(0x40F50110 + 14 * 4)
+#define    PCMD15  __REG(0x40F50110 + 15 * 4)
+#define    PCMD16  __REG(0x40F50110 + 16 * 4)
+#define    PCMD17  __REG(0x40F50110 + 17 * 4)
+#define    PCMD18  __REG(0x40F50110 + 18 * 4)
+#define    PCMD19  __REG(0x40F50110 + 19 * 4)
+#define    PCMD20  __REG(0x40F50110 + 20 * 4)
+#define    PCMD21  __REG(0x40F50110 + 21 * 4)
+#define    PCMD22  __REG(0x40F50110 + 22 * 4)
+#define    PCMD23  __REG(0x40F50110 + 23 * 4)
+#define    PCMD24  __REG(0x40F50110 + 24 * 4)
+#define    PCMD25  __REG(0x40F50110 + 25 * 4)
+#define    PCMD26  __REG(0x40F50110 + 26 * 4)
+#define    PCMD27  __REG(0x40F50110 + 27 * 4)
+#define    PCMD28  __REG(0x40F50110 + 28 * 4)
+#define    PCMD29  __REG(0x40F50110 + 29 * 4)
+#define    PCMD30  __REG(0x40F50110 + 30 * 4)
+#define    PCMD31  __REG(0x40F50110 + 31 * 4)
+
+#define    PCMD_MBC    (1<<12)
+#define    PCMD_DCE    (1<<11)
+#define    PCMD_LC     (1<<10)
+#define    PCMD_SQC    (3<<8)  /* only 00 and 01 are valid */
+
+#define PVCR_FVC                   (0x1 << 28)
+#define PVCR_VCSA                  (0x1<<14)
+#define PVCR_CommandDelay          (0xf80)
+#define PVCR_ReadPointer           (0x01f00000)
+#define PVCR_SlaveAddress          (0x7f)
+
+#else /* ifdef CONFIG_CPU_MONAHANS */
+
 #define PMCR           __REG(0x40F00000)  /* Power Manager Control Register */
 #define PSSR           __REG(0x40F00004)  /* Power Manager Sleep Status Register */
 #define PSPR           __REG(0x40F00008)  /* Power Manager Scratch Pad Register */
@@ -1225,6 +1651,8 @@ typedef void              (*ExcpHndlr) (void) ;
 #define RCSR_WDR       (1 << 1)        /* Watchdog Reset */
 #define RCSR_HWR       (1 << 0)        /* Hardware Reset */
 
+#endif /* CONFIG_CPU_MONAHANS */
+
 /*
  * SSP Serial Port Registers
  */
@@ -1259,6 +1687,67 @@ typedef void             (*ExcpHndlr) (void) ;
 /*
  * Core Clock
  */
+
+#if defined(CONFIG_CPU_MONAHANS)
+#define ACCR           __REG(0x41340000)  /* Application Subsystem Clock Configuration Register */
+#define ACSR           __REG(0x41340004)  /* Application Subsystem Clock Status Register */
+#define AICSR          __REG(0x41340008)  /* Application Subsystem Interrupt Control/Status Register */
+#define CKENA          __REG(0x4134000C)  /* A Clock Enable Register */
+#define CKENB          __REG(0x41340010)  /* B Clock Enable Register */
+#define AC97_DIV       __REG(0x41340014)  /* AC97 clock divisor value register */
+
+#define ACCR_SMC_MASK  0x03800000      /* Static Memory Controller Frequency Select */
+#define ACCR_SRAM_MASK 0x000c0000      /* SRAM Controller Frequency Select */
+#define ACCR_FC_MASK   0x00030000      /* Frequency Change Frequency Select */
+#define ACCR_HSIO_MASK 0x0000c000      /* High Speed IO Frequency Select */
+#define ACCR_DDR_MASK  0x00003000      /* DDR Memory Controller Frequency Select */
+#define ACCR_XN_MASK   0x00000700      /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#define ACCR_XL_MASK   0x0000001f      /* Crystal Frequency to Memory Frequency Multiplier */
+#define ACCR_XPDIS     (1 << 31)
+#define ACCR_SPDIS     (1 << 30)
+#define ACCR_13MEND1   (1 << 27)
+#define ACCR_D0CS      (1 << 26)
+#define ACCR_13MEND2   (1 << 21)
+#define ACCR_PCCE      (1 << 11)
+
+#define CKENA_30_MSL0  (1 << 30)       /* MSL0 Interface Unit Clock Enable */
+#define CKENA_29_SSP4  (1 << 29)       /* SSP3 Unit Clock Enable */
+#define CKENA_28_SSP3  (1 << 28)       /* SSP2 Unit Clock Enable */
+#define CKENA_27_SSP2  (1 << 27)       /* SSP1 Unit Clock Enable */
+#define CKENA_26_SSP1  (1 << 26)       /* SSP0 Unit Clock Enable */
+#define CKENA_25_TSI   (1 << 25)       /* TSI Clock Enable */
+#define CKENA_24_AC97  (1 << 24)       /* AC97 Unit Clock Enable */
+#define CKENA_23_STUART        (1 << 23)       /* STUART Unit Clock Enable */
+#define CKENA_22_FFUART        (1 << 22)       /* FFUART Unit Clock Enable */
+#define CKENA_21_BTUART        (1 << 21)       /* BTUART Unit Clock Enable */
+#define CKENA_20_UDC   (1 << 20)       /* UDC Clock Enable */
+#define CKENA_19_TPM   (1 << 19)       /* TPM Unit Clock Enable */
+#define CKENA_18_USIM1 (1 << 18)       /* USIM1 Unit Clock Enable */
+#define CKENA_17_USIM0 (1 << 17)       /* USIM0 Unit Clock Enable */
+#define CKENA_15_CIR   (1 << 15)       /* Consumer IR Clock Enable */
+#define CKENA_14_KEY   (1 << 14)       /* Keypad Controller Clock Enable */
+#define CKENA_13_MMC1  (1 << 13)       /* MMC1 Clock Enable */
+#define CKENA_12_MMC0  (1 << 12)       /* MMC0 Clock Enable */
+#define CKENA_11_FLASH (1 << 11)       /* Boot ROM Clock Enable */
+#define CKENA_10_SRAM  (1 << 10)       /* SRAM Controller Clock Enable */
+#define CKENA_9_SMC    (1 << 9)        /* Static Memory Controller */
+#define CKENA_8_DMC    (1 << 8)        /* Dynamic Memory Controller */
+#define CKENA_7_GRAPHICS (1 << 7)      /* 2D Graphics Clock Enable */
+#define CKENA_6_USBCLI (1 << 6)        /* USB Client Unit Clock Enable */
+#define CKENA_4_NAND   (1 << 4)        /* NAND Flash Controller Clock Enable */
+#define CKENA_3_CAMERA (1 << 3)        /* Camera Interface Clock Enable */
+#define CKENA_2_USBHOST        (1 << 2)        /* USB Host Unit Clock Enable */
+#define CKENA_1_LCD    (1 << 1)        /* LCD Unit Clock Enable */
+
+#define CKENB_8_1WIRE  ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */
+#define CKENB_7_GPIO   ((1 << 7) + 32) /* GPIO Clock Enable */
+#define CKENB_6_IRQ    ((1 << 6) + 32) /* Interrupt Controller Clock Enable */
+#define CKENB_4_I2C    ((1 << 4) + 32) /* I2C Unit Clock Enable */
+#define CKENB_1_PWM1   ((1 << 1) + 32) /* PWM2 & PWM3 Clock Enable */
+#define CKENB_0_PWM0   ((1 << 0) + 32) /* PWM0 & PWM1 Clock Enable */
+
+#else /* if defined CONFIG_CPU_MONAHANS */
+
 #define CCCR           __REG(0x41300000)  /* Core Clock Configuration Register */
 #define CKEN           __REG(0x41300004)  /* Clock Enable Register */
 #define OSCC           __REG(0x41300008)  /* Oscillator Configuration Register */
@@ -1318,6 +1807,8 @@ typedef void              (*ExcpHndlr) (void) ;
 #define         CCCR_N30      (0x6 << 7)
 #endif
 
+#endif /* CONFIG_CPU_MONAHANS */
+
 /*
  * LCD
  */
@@ -1502,6 +1993,163 @@ typedef void            (*ExcpHndlr) (void) ;
 /*
  * Memory controller
  */
+
+#ifdef CONFIG_CPU_MONAHANS
+/* Static Memory Controller Registers */
+#define MSC0           __REG_2(0x4A000008)  /* Static Memory Control Register 0 */
+#define MSC1           __REG_2(0x4A00000C)  /* Static Memory Control Register 1 */
+#define MECR           __REG_2(0x4A000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXCNFG         __REG_2(0x4A00001C)  /* Synchronous Static Memory Control Register */
+#define MCMEM0         __REG_2(0x4A000028)  /* Card interface Common Memory Space Socket 0 Timing */
+#define MCATT0         __REG_2(0x4A000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCIO0          __REG_2(0x4A000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MEMCLKCFG      __REG_2(0x4A000068)  /* SCLK speed configuration */
+#define CSADRCFG0      __REG_2(0x4A000080)  /* Address Configuration for chip select 0 */
+#define CSADRCFG1      __REG_2(0x4A000084)  /* Address Configuration for chip select 1 */
+#define CSADRCFG2      __REG_2(0x4A000088)  /* Address Configuration for chip select 2 */
+#define CSADRCFG3      __REG_2(0x4A00008C)  /* Address Configuration for chip select 3 */
+#define CSADRCFG_P     __REG_2(0x4A000090)  /* Address Configuration for pcmcia card interface */
+#define CSMSADRCFG     __REG_2(0x4A0000A0)  /* Master Address Configuration Register */
+#define CLK_RET_DEL    __REG_2(0x4A0000B0)  /* Delay line and mux selects for return data latching for sync. flash */
+#define ADV_RET_DEL    __REG_2(0x4A0000B4)  /* Delay line and mux selects for return data latching for sync. flash */
+
+/* Dynamic Memory Controller Registers */
+#define MDCNFG         __REG_2(0x48100000)  /* SDRAM Configuration Register 0 */
+#define MDREFR         __REG_2(0x48100004)  /* SDRAM Refresh Control Register */
+#define FLYCNFG                __REG_2(0x48100020)  /* Fly-by DMA DVAL[1:0] polarities */
+#define MDMRS          __REG_2(0x48100040)  /* MRS value to be written to SDRAM */
+#define        DDR_SCAL        __REG_2(0x48100050)  /* Software Delay Line Calibration/Configuration for external DDR memory. */
+#define        DDR_HCAL        __REG_2(0x48100060)  /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
+#define        DDR_WCAL        __REG_2(0x48100068)  /* DDR Write Strobe Calibration Register */
+#define        DMCIER          __REG_2(0x48100070)  /* Dynamic MC Interrupt Enable Register. */
+#define        DMCISR          __REG_2(0x48100078)  /* Dynamic MC Interrupt Status Register. */
+#define        DDR_DLS         __REG_2(0x48100080)  /* DDR Delay Line Value Status register for external DDR memory. */
+#define        EMPI            __REG_2(0x48100090)  /* EMPI Control Register */
+#define RCOMP           __REG_2(0x48100100)
+#define PAD_MA          __REG_2(0x48100110)
+#define PAD_MDMSB       __REG_2(0x48100114)
+#define PAD_MDLSB       __REG_2(0x48100118)
+#define PAD_DMEM        __REG_2(0x4810011c)
+#define PAD_SDCLK       __REG_2(0x48100120)
+#define PAD_SDCS        __REG_2(0x48100124)
+#define PAD_SMEM        __REG_2(0x48100128)
+#define PAD_SCLK        __REG_2(0x4810012C)
+#define TAI            __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */
+
+/* Some frequently used bits */
+#define MDCNFG_DMAP    0x80000000      /* SDRAM 1GB Memory Map Enable */
+#define MDCNFG_DMCEN   0x40000000      /* Enable Dynamic Memory Controller */
+#define MDCNFG_HWFREQ  0x20000000      /* Hardware Frequency Change Calibration */
+#define MDCNFG_DTYPE   0x400           /* SDRAM Type: 1=DDR SDRAM */
+
+#define MDCNFG_DTC_0   0x0             /* Timing Category of SDRAM */
+#define MDCNFG_DTC_1   0x100
+#define MDCNFG_DTC_2   0x200
+#define MDCNFG_DTC_3   0x300
+
+#define MDCNFG_DRAC_12 0x0             /* Number of Row Access Bits */
+#define MDCNFG_DRAC_13 0x20
+#define MDCNFG_DRAC_14 0x40
+
+#define MDCNFG_DCAC_9  0x0             /* Number of Column Acess Bits */
+#define MDCNFG_DCAC_10 0x08
+#define MDCNFG_DCAC_11 0x10
+
+#define MDCNFG_DBW_16  0x4             /* SDRAM Data Bus width 16bit */
+#define MDCNFG_DCSE1   0x2             /* SDRAM CS 1 Enable */
+#define MDCNFG_DCSE0   0x1             /* SDRAM CS 0 Enable */
+
+
+/* Data Flash Controller Registers */
+
+#define NDCR           __REG(0x43100000)  /* Data Flash Control register */
+#define NDTR0CS0       __REG(0x43100004)  /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
+/* #define NDTR0CS1    __REG(0x43100008)  /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
+#define NDTR1CS0       __REG(0x4310000C)  /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
+/* #define NDTR1CS1    __REG(0x43100010)  /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
+#define NDSR           __REG(0x43100014)  /* Data Controller Status Register */
+#define NDPCR          __REG(0x43100018)  /* Data Controller Page Count Register */
+#define NDBDR0         __REG(0x4310001C)  /* Data Controller Bad Block Register 0 */
+#define NDBDR1         __REG(0x43100020)  /* Data Controller Bad Block Register 1 */
+#define NDDB           __REG(0x43100040)  /* Data Controller Data Buffer */
+#define NDCB0          __REG(0x43100048)  /* Data Controller Command Buffer0 */
+#define NDCB1          __REG(0x4310004C)  /* Data Controller Command Buffer1 */
+#define NDCB2          __REG(0x43100050)  /* Data Controller Command Buffer2 */
+
+#define NDCR_SPARE_EN  (0x1<<31)
+#define NDCR_ECC_EN    (0x1<<30)
+#define NDCR_DMA_EN    (0x1<<29)
+#define NDCR_ND_RUN    (0x1<<28)
+#define NDCR_DWIDTH_C  (0x1<<27)
+#define NDCR_DWIDTH_M  (0x1<<26)
+#define NDCR_PAGE_SZ   (0x3<<24)
+#define NDCR_NCSX      (0x1<<23)
+#define NDCR_ND_STOP   (0x1<<22)
+/* reserved:
+ * #define NDCR_ND_MODE        (0x3<<21)
+ * #define NDCR_NAND_MODE   0x0 */
+#define NDCR_CLR_PG_CNT        (0x1<<20)
+#define NDCR_CLR_ECC   (0x1<<19)
+#define NDCR_RD_ID_CNT (0x7<<16)
+#define NDCR_RA_START  (0x1<<15)
+#define NDCR_PG_PER_BLK        (0x1<<14)
+#define NDCR_ND_ARB_EN (0x1<<12)
+#define NDCR_RDYM      (0x1<<11)
+#define NDCR_CS0_PAGEDM        (0x1<<10)
+#define NDCR_CS1_PAGEDM        (0x1<<9)
+#define NDCR_CS0_CMDDM (0x1<<8)
+#define NDCR_CS1_CMDDM (0x1<<7)
+#define NDCR_CS0_BBDM  (0x1<<6)
+#define NDCR_CS1_BBDM  (0x1<<5)
+#define NDCR_DBERRM    (0x1<<4)
+#define NDCR_SBERRM    (0x1<<3)
+#define NDCR_WRDREQM   (0x1<<2)
+#define NDCR_RDDREQM   (0x1<<1)
+#define NDCR_WRCMDREQM (0x1)
+
+#define NDSR_RDY       (0x1<<11)
+#define NDSR_CS0_PAGED (0x1<<10)
+#define NDSR_CS1_PAGED (0x1<<9)
+#define NDSR_CS0_CMDD  (0x1<<8)
+#define NDSR_CS1_CMDD  (0x1<<7)
+#define NDSR_CS0_BBD   (0x1<<6)
+#define NDSR_CS1_BBD   (0x1<<5)
+#define NDSR_DBERR     (0x1<<4)
+#define NDSR_SBERR     (0x1<<3)
+#define NDSR_WRDREQ    (0x1<<2)
+#define NDSR_RDDREQ    (0x1<<1)
+#define NDSR_WRCMDREQ  (0x1)
+
+#define NDCB0_AUTO_RS  (0x1<<25)
+#define NDCB0_CSEL     (0x1<<24)
+#define NDCB0_CMD_TYPE (0x7<<21)
+#define NDCB0_NC       (0x1<<20)
+#define NDCB0_DBC      (0x1<<19)
+#define NDCB0_ADDR_CYC (0x7<<16)
+#define NDCB0_CMD2     (0xff<<8)
+#define NDCB0_CMD1     (0xff)
+#define MCMEM(s) MCMEM0
+#define MCATT(s) MCATT0
+#define MCIO(s) MCIO0
+#define MECR_CIT       (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
+
+/* Maximum values for NAND Interface Timing Registers in DFC clock
+ * periods */
+#define DFC_MAX_tCH    7
+#define DFC_MAX_tCS    7
+#define DFC_MAX_tWH    7
+#define DFC_MAX_tWP    7
+#define DFC_MAX_tRH    7
+#define DFC_MAX_tRP    15
+#define DFC_MAX_tR     65535
+#define DFC_MAX_tWHR   15
+#define DFC_MAX_tAR    15
+
+#define DFC_CLOCK      104             /* DFC Clock is 104 MHz */
+#define DFC_CLK_PER_US DFC_CLOCK/1000  /* clock period in ns */
+
+#else /* CONFIG_CPU_MONAHANS */
+
 #define MEMC_BASE      __REG(0x48000000)  /* Base of Memory Controller */
 #define MDCNFG_OFFSET  0x0
 #define MDREFR_OFFSET  0x4
@@ -1573,6 +2221,8 @@ typedef void              (*ExcpHndlr) (void) ;
 #define ARB_CORE_PARK          (1<<24)    /* Be parked with core when idle */
 #define ARB_LOCK_FLAG          (1<<23)    /* Only Locking masters gain access to the bus */
 
+#endif /* CONFIG_CPU_MONAHANS */
+
 /* Interrupt Controller */
 
 #define ICIP2          __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
@@ -1733,16 +2383,16 @@ typedef void            (*ExcpHndlr) (void) ;
 #define KPAS_SO                (0x1 << 31)
 #define KPASMKPx_SO    (0x1 << 31)
 
-#define GPIO113_BIT       (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
-#define PSLR      __REG(0x40F00034)
-#define PSTR      __REG(0x40F00038)  /* Power Manager Standby Configuration Reg */
-#define PSNR      __REG(0x40F0003C)  /* Power Manager Sense Configuration Reg */
-#define PVCR      __REG(0x40F00040)  /* Power Manager Voltage Change Control Reg */
-#define PKWR      __REG(0x40F00050)  /* Power Manager KB Wake-Up Enable Reg */
-#define PKSR      __REG(0x40F00054)  /* Power Manager KB Level-Detect Status Reg */
-#define OSMR4      __REG(0x40A00080)  /* */
-#define OSCR4      __REG(0x40A00040)  /* OS Timer Counter Register */
-#define OMCR4      __REG(0x40A000C0)  /* */
+#define GPIO113_BIT    (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
+#define PSLR           __REG(0x40F00034)
+#define PSTR           __REG(0x40F00038)  /* Power Manager Standby Configuration Reg */
+#define PSNR           __REG(0x40F0003C)  /* Power Manager Sense Configuration Reg */
+#define PVCR           __REG(0x40F00040)  /* Power Manager Voltage Change Control Reg */
+#define PKWR           __REG(0x40F00050)  /* Power Manager KB Wake-Up Enable Reg */
+#define PKSR           __REG(0x40F00054)  /* Power Manager KB Level-Detect Status Reg */
+#define OSMR4          __REG(0x40A00080)  /* */
+#define OSCR4          __REG(0x40A00040)  /* OS Timer Counter Register */
+#define OMCR4          __REG(0x40A000C0)  /* */
 
 #endif /* CONFIG_PXA27X */
 

diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index c2b69fb2dd92ac1d1ddc5ded23dc820c45e45a91..648a10dd92368745e2529c73fb0ff12604ac451e 100644 (file)
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -58,6 +58,14 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
 #define __raw_readw(a)                 __arch_getw(a)
 #define __raw_readl(a)                 __arch_getl(a)
 
+#define writeb(v,a)                    __arch_putb(v,a)
+#define writew(v,a)                    __arch_putw(v,a)
+#define writel(v,a)                    __arch_putl(v,a)
+
+#define readb(a)                       __arch_getb(a)
+#define readw(a)                       __arch_getw(a)
+#define readl(a)                       __arch_getl(a)
+
 /*
  * The compiler seems to be incapable of optimising constants
  * properly.  Spell it out to the compiler in some cases.

diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h
new file mode 100644 (file)
index 0000000..65d2c25
--- /dev/null
+++ b/include/asm-blackfin/bitops.h
@@ -0,0 +1,380 @@
+/*
+ * U-boot - bitops.h Routines for bit operations
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_BITOPS_H
+#define _BLACKFIN_BITOPS_H
+
+/*
+ * Copyright 1992, Linus Torvalds.
+ */
+
+#include <linux/config.h>
+#include <asm/byteorder.h>
+#include <asm/system.h>
+
+#ifdef __KERNEL__
+/*
+ * Function prototypes to keep gcc -Wall happy
+ */
+
+/*
+ * The __ functions are not atomic
+ */
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static __inline__ unsigned long ffz(unsigned long word)
+{
+       unsigned long result = 0;
+
+       while (word & 1) {
+               result++;
+               word >>= 1;
+       }
+       return result;
+}
+
+static __inline__ void set_bit(int nr, volatile void *addr)
+{
+       int *a = (int *) addr;
+       int mask;
+       unsigned long flags;
+
+       a += nr >> 5;
+       mask = 1 << (nr & 0x1f);
+       save_and_cli(flags);
+       *a |= mask;
+       restore_flags(flags);
+}
+
+static __inline__ void __set_bit(int nr, volatile void *addr)
+{
+       int *a = (int *) addr;
+       int mask;
+
+       a += nr >> 5;
+       mask = 1 << (nr & 0x1f);
+       *a |= mask;
+}
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()     barrier()
+#define smp_mb__after_clear_bit()      barrier()
+
+static __inline__ void clear_bit(int nr, volatile void *addr)
+{
+       int *a = (int *) addr;
+       int mask;
+       unsigned long flags;
+
+       a += nr >> 5;
+       mask = 1 << (nr & 0x1f);
+       save_and_cli(flags);
+       *a &= ~mask;
+       restore_flags(flags);
+}
+
+static __inline__ void change_bit(int nr, volatile void *addr)
+{
+       int mask, flags;
+       unsigned long *ADDR = (unsigned long *) addr;
+
+       ADDR += nr >> 5;
+       mask = 1 << (nr & 31);
+       save_and_cli(flags);
+       *ADDR ^= mask;
+       restore_flags(flags);
+}
+
+static __inline__ void __change_bit(int nr, volatile void *addr)
+{
+       int mask;
+       unsigned long *ADDR = (unsigned long *) addr;
+
+       ADDR += nr >> 5;
+       mask = 1 << (nr & 31);
+       *ADDR ^= mask;
+}
+
+static __inline__ int test_and_set_bit(int nr, volatile void *addr)
+{
+       int mask, retval;
+       volatile unsigned int *a = (volatile unsigned int *) addr;
+       unsigned long flags;
+
+       a += nr >> 5;
+       mask = 1 << (nr & 0x1f);
+       save_and_cli(flags);
+       retval = (mask & *a) != 0;
+       *a |= mask;
+       restore_flags(flags);
+
+       return retval;
+}
+
+static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
+{
+       int mask, retval;
+       volatile unsigned int *a = (volatile unsigned int *) addr;
+
+       a += nr >> 5;
+       mask = 1 << (nr & 0x1f);
+       retval = (mask & *a) != 0;
+       *a |= mask;
+       return retval;
+}
+
+static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
+{
+       int mask, retval;
+       volatile unsigned int *a = (volatile unsigned int *) addr;
+       unsigned long flags;
+
+       a += nr >> 5;
+       mask = 1 << (nr & 0x1f);
+       save_and_cli(flags);
+       retval = (mask & *a) != 0;
+       *a &= ~mask;
+       restore_flags(flags);
+
+       return retval;
+}
+
+static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
+{
+       int mask, retval;
+       volatile unsigned int *a = (volatile unsigned int *) addr;
+
+       a += nr >> 5;
+       mask = 1 << (nr & 0x1f);
+       retval = (mask & *a) != 0;
+       *a &= ~mask;
+       return retval;
+}
+
+static __inline__ int test_and_change_bit(int nr, volatile void *addr)
+{
+       int mask, retval;
+       volatile unsigned int *a = (volatile unsigned int *) addr;
+       unsigned long flags;
+
+       a += nr >> 5;
+       mask = 1 << (nr & 0x1f);
+       save_and_cli(flags);
+       retval = (mask & *a) != 0;
+       *a ^= mask;
+       restore_flags(flags);
+
+       return retval;
+}
+
+static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
+{
+       int mask, retval;
+       volatile unsigned int *a = (volatile unsigned int *) addr;
+
+       a += nr >> 5;
+       mask = 1 << (nr & 0x1f);
+       retval = (mask & *a) != 0;
+       *a ^= mask;
+       return retval;
+}
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static __inline__ int __constant_test_bit(int nr,
+                                         const volatile void *addr)
+{
+       return ((1UL << (nr & 31)) &
+               (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
+}
+
+static __inline__ int __test_bit(int nr, volatile void *addr)
+{
+       int *a = (int *) addr;
+       int mask;
+
+       a += nr >> 5;
+       mask = 1 << (nr & 0x1f);
+       return ((mask & *a) != 0);
+}
+
+#define        test_bit(nr,addr) \
+(__builtin_constant_p(nr) ? \
+ __constant_test_bit((nr),(addr)) : \
+ __test_bit((nr),(addr)))
+
+#define        find_first_zero_bit(addr, size) \
+       find_next_zero_bit((addr), (size), 0)
+
+static __inline__ int find_next_zero_bit(void *addr, int size, int offset)
+{
+       unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+       unsigned long result = offset & ~31UL;
+       unsigned long tmp;
+
+       if (offset >= size)
+               return size;
+       size -= result;
+       offset &= 31UL;
+       if (offset) {
+               tmp = *(p++);
+               tmp |= ~0UL >> (32 - offset);
+               if (size < 32)
+                       goto found_first;
+               if (~tmp)
+                       goto found_middle;
+               size -= 32;
+               result += 32;
+       }
+       while (size & ~31UL) {
+               if (~(tmp = *(p++)))
+                       goto found_middle;
+               result += 32;
+               size -= 32;
+       }
+       if (!size)
+               return result;
+       tmp = *p;
+
+      found_first:
+       tmp |= ~0UL >> size;
+      found_middle:
+       return result + ffz(tmp);
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+#define ffs(x)         generic_ffs(x)
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x)   generic_hweight32(x)
+#define hweight16(x)   generic_hweight16(x)
+#define hweight8(x)    generic_hweight8(x)
+
+static __inline__ int ext2_set_bit(int nr, volatile void *addr)
+{
+       int mask, retval;
+       unsigned long flags;
+       volatile unsigned char *ADDR = (unsigned char *) addr;
+
+       ADDR += nr >> 3;
+       mask = 1 << (nr & 0x07);
+       save_and_cli(flags);
+       retval = (mask & *ADDR) != 0;
+       *ADDR |= mask;
+       restore_flags(flags);
+       return retval;
+}
+
+static __inline__ int ext2_clear_bit(int nr, volatile void *addr)
+{
+       int mask, retval;
+       unsigned long flags;
+       volatile unsigned char *ADDR = (unsigned char *) addr;
+
+       ADDR += nr >> 3;
+       mask = 1 << (nr & 0x07);
+       save_and_cli(flags);
+       retval = (mask & *ADDR) != 0;
+       *ADDR &= ~mask;
+       restore_flags(flags);
+       return retval;
+}
+
+static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
+{
+       int mask;
+       const volatile unsigned char *ADDR = (const unsigned char *) addr;
+
+       ADDR += nr >> 3;
+       mask = 1 << (nr & 0x07);
+       return ((mask & *ADDR) != 0);
+}
+
+#define ext2_find_first_zero_bit(addr, size) \
+       ext2_find_next_zero_bit((addr), (size), 0)
+
+static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
+                                                       unsigned long size,
+                                                       unsigned long
+                                                       offset)
+{
+       unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+       unsigned long result = offset & ~31UL;
+       unsigned long tmp;
+
+       if (offset >= size)
+               return size;
+       size -= result;
+       offset &= 31UL;
+       if (offset) {
+               tmp = *(p++);
+               tmp |= ~0UL >> (32 - offset);
+               if (size < 32)
+                       goto found_first;
+               if (~tmp)
+                       goto found_middle;
+               size -= 32;
+               result += 32;
+       }
+       while (size & ~31UL) {
+               if (~(tmp = *(p++)))
+                       goto found_middle;
+               result += 32;
+               size -= 32;
+       }
+       if (!size)
+               return result;
+       tmp = *p;
+
+      found_first:
+       tmp |= ~0UL >> size;
+      found_middle:
+       return result + ffz(tmp);
+}
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr,addr)                test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr)                 set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr)      test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr)                        test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size)   find_first_zero_bit(addr,size)
+
+#endif
+
+#endif

diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
new file mode 100644 (file)
index 0000000..fbdbf30
--- /dev/null
+++ b/include/asm-blackfin/blackfin.h
@@ -0,0 +1,46 @@
+/*
+ * U-boot - blackfin.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_H_
+#define _BLACKFIN_H_
+
+#include <asm/cpu/defBF533.h>
+#include <asm/cpu/bf533_serial.h>
+
+#ifndef __ASSEMBLY__
+#ifndef ASSEMBLY
+
+#ifdef SHARED_RESOURCES
+ #include <asm/shared_resources.h>
+#endif
+#include <asm/cpu/cdefBF53x.h>
+
+#endif
+#endif
+
+#include <asm/cpu/defBF533.h>
+#include <asm/cpu/defBF533_extn.h>
+#include <asm/cpu/bf533_serial.h>
+
+#endif

diff --git a/include/asm-blackfin/blackfin_defs.h b/include/asm-blackfin/blackfin_defs.h
new file mode 100644 (file)
index 0000000..2190215
--- /dev/null
+++ b/include/asm-blackfin/blackfin_defs.h
@@ -0,0 +1,83 @@
+/*
+ * U-boot - blackfin_defs.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_DEFS_H__
+#define __BLACKFIN_DEFS_H__
+
+#define TS_MAGICKEY            0x5a5a5a5a
+#define TASK_STATE             0
+#define TASK_FLAGS             4
+#define TASK_PTRACE            24
+#define TASK_BLOCKED           636
+#define TASK_COUNTER           32
+#define TASK_SIGPENDING                8
+#define TASK_NEEDRESCHED       20
+#define TASK_THREAD            600
+#define TASK_MM                        44
+#define TASK_ACTIVE_MM         80
+#define THREAD_KSP             0
+#define THREAD_USP             4
+#define THREAD_SR              8
+#define THREAD_ESP0            12
+#define THREAD_PC              16
+#define PT_ORIG_R0             208
+#define PT_R0                  204
+#define PT_R1                  200
+#define PT_R2                  196
+#define PT_R3                  192
+#define PT_R4                  188
+#define PT_R5                  184
+#define PT_R6                  180
+#define PT_R7                  176
+#define PT_P0                  172
+#define PT_P1                  168
+#define PT_P2                  164
+#define PT_P3                  160
+#define PT_P4                  156
+#define PT_P5                  152
+#define PT_A0w                 72
+#define PT_A1w                 64
+#define PT_A0x                 76
+#define PT_A1x                 68
+#define PT_RETS                        28
+#define PT_RESERVED            32
+#define PT_ASTAT               36
+#define PT_SEQSTAT             8
+#define PT_PC                  24
+#define PT_IPEND               0
+#define PT_USP                 144
+#define PT_FP                  148
+#define PT_SYSCFG              4
+#define IRQ_HANDLER            0
+#define IRQ_DEVID              8
+#define IRQ_NEXT               16
+#define STAT_IRQ               5148
+#define SIGSEGV                        11
+#define SEGV_MAPERR            196609
+#define SIGTRAP                        5
+#define PT_PTRACED             1
+#define PT_TRACESYS            2
+#define PT_DTRACE              4
+
+#endif

diff --git a/include/asm-blackfin/byteorder.h b/include/asm-blackfin/byteorder.h
new file mode 100644 (file)
index 0000000..3b4df4e
--- /dev/null
+++ b/include/asm-blackfin/byteorder.h
@@ -0,0 +1,40 @@
+/*
+ * U-boot -  byteorder.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_BYTEORDER_H
+#define _BLACKFIN_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#include <linux/byteorder/little_endian.h>
+
+#endif

diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
new file mode 100644 (file)
index 0000000..7715f64
--- /dev/null
+++ b/include/asm-blackfin/cplb.h
@@ -0,0 +1,48 @@
+/************************************************************************
+ *
+ * cplb.h
+ *
+ * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
+ *
+ ************************************************************************/
+
+/* Defines necessary for cplb initialisation routines. */
+
+#ifndef _CPLB_H
+#define _CPLB_H
+
+#define CPLB_ENABLE_ICACHE_P   0
+#define CPLB_ENABLE_DCACHE_P   1
+#define CPLB_ENABLE_DCACHE2_P  2
+#define CPLB_ENABLE_CPLBS_P    3       /* Deprecated!*/
+#define CPLB_ENABLE_ICPLBS_P   4
+#define CPLB_ENABLE_DCPLBS_P   5
+
+#define CPLB_ENABLE_ICACHE     (1<<CPLB_ENABLE_ICACHE_P)
+#define CPLB_ENABLE_DCACHE     (1<<CPLB_ENABLE_DCACHE_P)
+#define CPLB_ENABLE_DCACHE2    (1<<CPLB_ENABLE_DCACHE2_P)
+#define CPLB_ENABLE_CPLBS      (1<<CPLB_ENABLE_CPLBS_P)
+#define CPLB_ENABLE_ICPLBS     (1<<CPLB_ENABLE_ICPLBS_P)
+#define CPLB_ENABLE_DCPLBS     (1<<CPLB_ENABLE_DCPLBS_P)
+#define CPLB_ENABLE_ANY_CPLBS  CPLB_ENABLE_CPLBS | \
+                               CPLB_ENABLE_ICPLBS | \
+                               CPLB_ENABLE_DCPLBS
+
+#define CPLB_RELOADED          0x0000
+#define CPLB_NO_UNLOCKED       0x0001
+#define CPLB_NO_ADDR_MATCH     0x0002
+#define CPLB_PROT_VIOL         0x0003
+
+#define CPLB_DEF_CACHE         CPLB_L1_CHBL | CPLB_WT
+#define CPLB_CACHE_ENABLED     CPLB_L1_CHBL | CPLB_DIRTY
+
+#define CPLB_ALL_ACCESS        CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
+
+#define CPLB_I_PAGE_MGMT       CPLB_LOCK | CPLB_VALID
+#define CPLB_D_PAGE_MGMT       CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
+#define CPLB_DNOCACHE          CPLB_ALL_ACCESS | CPLB_VALID
+#define CPLB_DDOCACHE          CPLB_DNOCACHE | CPLB_DEF_CACHE
+#define CPLB_INOCACHE          CPLB_USER_RD | CPLB_VALID
+#define CPLB_IDOCACHE          CPLB_INOCACHE | CPLB_L1_CHBL
+
+#endif /* _CPLB_H */

diff --git a/include/asm-blackfin/cplbtab.h b/include/asm-blackfin/cplbtab.h
new file mode 100644 (file)
index 0000000..ab7d989
--- /dev/null
+++ b/include/asm-blackfin/cplbtab.h
@@ -0,0 +1,572 @@
+/*This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
+ * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
+ *             shouldn't be victimized. cplbmgr.S search logic is corrected
+ *             to findout the appropriate victim.
+ *          2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
+ *          : LG Soft India
+ */
+#include <config.h>
+
+#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
+#define __ARCH_BFINNOMMU_CPLBTAB_H
+
+/*************************************************************************
+ *                     ICPLB TABLE
+ *************************************************************************/
+
+.data
+
+/* This table is configurable */
+
+.align 4;
+
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC         (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY             (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL                (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
+
+#define ANOMALY_05000158               0x200
+#ifdef CONFIG_BLKFIN_WB        /*Write Back Policy */
+       #define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+       #define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+       #define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+       #define L1_DMEMORY              (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+       #define SDRAM_EBIU              (PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+
+#else  /*Write Through*/
+       #define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+       #define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+       #define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+       #define L1_DMEMORY              (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+       #define SDRAM_EBIU              (PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+#endif
+
+.global icplb_table
+icplb_table:
+.byte4 0xFFA00000;
+.byte4 (L1_IMEMORY);
+.byte4 0x00000000;
+.byte4 (SDRAM_IKERNEL);                        /*SDRAM_Page1*/
+.byte4 0x00400000;
+.byte4 (SDRAM_IKERNEL);                /*SDRAM_Page1*/
+.byte4 0x07C00000;
+.byte4 (SDRAM_IKERNEL);                /*SDRAM_Page14*/
+.byte4 0x00800000;
+.byte4 (SDRAM_IGENERIC);               /*SDRAM_Page2*/
+.byte4 0x00C00000;
+.byte4 (SDRAM_IGENERIC);               /*SDRAM_Page2*/
+.byte4 0x01000000;
+.byte4 (SDRAM_IGENERIC);               /*SDRAM_Page4*/
+.byte4 0x01400000;
+.byte4 (SDRAM_IGENERIC);               /*SDRAM_Page5*/
+.byte4 0x01800000;
+.byte4 (SDRAM_IGENERIC);               /*SDRAM_Page6*/
+.byte4 0x01C00000;
+.byte4 (SDRAM_IGENERIC);               /*SDRAM_Page7*/
+#ifndef CONFIG_EZKIT                   /*STAMP Memory regions*/
+.byte4 0x02000000;
+.byte4 (SDRAM_IGENERIC);               /*SDRAM_Page8*/
+.byte4 0x02400000;
+.byte4 (SDRAM_IGENERIC);               /*SDRAM_Page9*/
+.byte4 0x02800000;
+.byte4 (SDRAM_IGENERIC);               /*SDRAM_Page10*/
+.byte4 0x02C00000;
+.byte4 (SDRAM_IGENERIC);               /*SDRAM_Page11*/
+.byte4 0x03000000;
+.byte4 (SDRAM_IGENERIC);               /*SDRAM_Page12*/
+.byte4 0x03400000;
+.byte4 (SDRAM_IGENERIC);               /*SDRAM_Page13*/
+#endif
+.byte4 0xffffffff;                     /* end of section - termination*/
+
+.align 4;
+.global ipdt_table
+ipdt_table:
+#ifdef CONFIG_CPLB_INFO
+.byte4 0x00000000;
+.byte4 (SDRAM_IKERNEL);               /*SDRAM_Page0*/
+.byte4 0x00400000;
+.byte4 (SDRAM_IKERNEL);               /*SDRAM_Page1*/
+#endif
+.byte4 0x00800000;
+.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page2*/
+.byte4 0x00C00000;
+.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page3*/
+.byte4 0x01000000;
+.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page4*/
+.byte4 0x01400000;
+.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page5*/
+.byte4 0x01800000;
+.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page6*/
+.byte4 0x01C00000;
+.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page7*/
+#ifndef CONFIG_EZKIT                  /*STAMP Memory regions*/
+.byte4  0x02000000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page8*/
+.byte4  0x02400000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page9*/
+.byte4  0x02800000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page10*/
+.byte4  0x02C00000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page11*/
+.byte4  0x03000000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page12*/
+.byte4  0x03400000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page13*/
+.byte4  0x03800000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page14*/
+.byte4  0x03C00000;
+.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page15*/
+#endif
+.byte4  0x20200000;
+.byte4  (SDRAM_EBIU);      /* Async Memory Bank 2 (Secnd)*/
+.byte4  0x20100000;
+.byte4  (SDRAM_EBIU);      /* Async Memory Bank 1 (Prim B)*/
+.byte4  0x20000000;
+.byte4  (SDRAM_EBIU);      /* Async Memory Bank 0 (Prim A)*/
+.byte4  0x20300000;             /*Fix for Network*/
+.byte4  (SDRAM_EBIU);    /*Async Memory bank 3*/
+
+#ifdef CONFIG_STAMP
+.byte4        0x04000000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x04400000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x04800000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x04C00000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x05000000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x05400000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x05800000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x05C00000;
+.byte4  (SDRAM_IGENERIC);
+.byte4        0x06000000;
+.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page25*/
+.byte4        0x06400000;
+.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page26*/
+.byte4        0x06800000;
+.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page27*/
+.byte4        0x06C00000;
+.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page28*/
+.byte4        0x07000000;
+.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page29*/
+.byte4        0x07400000;
+.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page30*/
+.byte4        0x07800000;
+.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page31*/
+#ifdef CONFIG_CPLB_INFO
+.byte4        0x07C00000;
+.byte4  (SDRAM_IKERNEL);        /*SDRAM_Page32*/
+#endif
+#endif
+.byte4 0xffffffff;                    /* end of section - termination*/
+
+/*********************************************************************
+ *                     DCPLB TABLE
+ ********************************************************************/
+
+.global dcplb_table
+dcplb_table:
+.byte4 0x00000000;
+.byte4 (SDRAM_DKERNEL);        /*SDRAM_Page1*/
+.byte4 0x00400000;
+.byte4 (SDRAM_DKERNEL);        /*SDRAM_Page1*/
+.byte4 0x07C00000;
+.byte4 (SDRAM_DKERNEL);        /*SDRAM_Page15*/
+.byte4 0x00800000;
+.byte4         (SDRAM_DGENERIC);       /*SDRAM_Page2*/
+.byte4         0x00C00000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page3*/
+.byte4 0x01000000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page4*/
+.byte4 0x01400000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page5*/
+.byte4 0x01800000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page6*/
+.byte4 0x01C00000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page7*/
+#ifndef CONFIG_EZKIT
+.byte4 0x02000000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page8*/
+.byte4 0x02400000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page9*/
+.byte4 0x02800000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page10*/
+.byte4 0x02C00000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page11*/
+.byte4 0x03000000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page12*/
+.byte4 0x03400000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page13*/
+.byte4 0x03800000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page14*/
+#endif
+.byte4 0xffffffff;             /*end of section - termination*/
+
+/**********************************************************************
+ *             PAGE DESCRIPTOR TABLE
+ *
+ **********************************************************************/
+
+/* Till here we are discussing about the static memory management model.
+ * However, the operating envoronments commonly define more CPLB
+ * descriptors to cover the entire addressable memory than will fit into
+ * the available on-chip 16 CPLB MMRs. When this happens, the below table
+ * will be used which will hold all the potentially required CPLB descriptors
+ *
+ * This is how Page descriptor Table is implemented in uClinux/Blackfin.
+ */
+.global dpdt_table
+dpdt_table:
+#ifdef CONFIG_CPLB_INFO
+.byte4        0x00000000;
+.byte4        (SDRAM_DKERNEL);        /*SDRAM_Page0*/
+.byte4        0x00400000;
+.byte4        (SDRAM_DKERNEL);        /*SDRAM_Page1*/
+#endif
+.byte4        0x00800000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page2*/
+.byte4        0x00C00000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page3*/
+.byte4        0x01000000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page4*/
+.byte4        0x01400000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page5*/
+.byte4        0x01800000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page6*/
+.byte4        0x01C00000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page7*/
+
+#ifndef CONFIG_EZKIT
+.byte4        0x02000000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page8*/
+.byte4        0x02400000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page9*/
+.byte4        0x02800000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page10*/
+.byte4        0x02C00000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page11*/
+.byte4        0x03000000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page12*/
+.byte4        0x03400000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page13*/
+.byte4        0x03800000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page14*/
+.byte4        0x03C00000;
+.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page15*/
+#endif
+.byte4 0x20200000;
+.byte4 (SDRAM_EBIU);   /* Async Memory Bank 2 (Secnd)*/
+.byte4 0x20100000;
+.byte4 (SDRAM_EBIU);   /* Async Memory Bank 1 (Prim B)*/
+.byte4 0x20000000;
+.byte4 (SDRAM_EBIU);   /* Async Memory Bank 0 (Prim A)*/
+.byte4 0x20300000;             /*Fix for Network*/
+.byte4  (SDRAM_EBIU);  /*Async Memory bank 3*/
+
+#ifdef CONFIG_STAMP
+.byte4 0x04000000;
+.byte4  (SDRAM_DGENERIC);
+.byte4 0x04400000;
+.byte4  (SDRAM_DGENERIC);
+.byte4 0x04800000;
+.byte4  (SDRAM_DGENERIC);
+.byte4 0x04C00000;
+.byte4  (SDRAM_DGENERIC);
+.byte4 0x05000000;
+.byte4  (SDRAM_DGENERIC);
+.byte4 0x05400000;
+.byte4  (SDRAM_DGENERIC);
+.byte4 0x05800000;
+.byte4  (SDRAM_DGENERIC);
+.byte4 0x05C00000;
+.byte4  (SDRAM_DGENERIC);
+.byte4 0x06000000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page25*/
+.byte4 0x06400000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page26*/
+.byte4 0x06800000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page27*/
+.byte4 0x06C00000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page28*/
+.byte4 0x07000000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page29*/
+.byte4 0x07400000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page30*/
+.byte4 0x07800000;
+.byte4 (SDRAM_DGENERIC);       /*SDRAM_Page31*/
+#ifdef CONFIG_CPLB_INFO
+.byte4 0x07C00000;
+.byte4 (SDRAM_DKERNEL);        /*SDRAM_Page32*/
+#endif
+#endif
+
+.byte4  0xFF900000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF901000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF902000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF903000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF904000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF905000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF906000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF907000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF800000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF801000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF802000;
+.byte4  (L1_DMEMORY);
+.byte4  0xFF803000;
+.byte4  (L1_DMEMORY);
+
+.byte4 0xffffffff;             /*end of section - termination*/
+
+#ifdef CONFIG_CPLB_INFO
+.global ipdt_swapcount_table;  /* swapin count first, then swapout count*/
+ipdt_swapcount_table:
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 10 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 20 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 30 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 40 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 50 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 60 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 70 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 80 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 90 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 100 */
+
+.global dpdt_swapcount_table;  /* swapin count first, then swapout count*/
+dpdt_swapcount_table:
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 10 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 20 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 30 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 40 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 50 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 60 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 70 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 80 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 80 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 100 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 110 */
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;
+.byte4        0x00000000;      /* 120 */
+
+#endif
+
+#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/

diff --git a/include/asm-blackfin/cpu/bf533_irq.h b/include/asm-blackfin/cpu/bf533_irq.h
new file mode 100644 (file)
index 0000000..9c5230d
--- /dev/null
+++ b/include/asm-blackfin/cpu/bf533_irq.h
@@ -0,0 +1,137 @@
+/*
+ * U-boot bf533_irq.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
+ * Changed by HuTao Apr18, 2003
+ *
+ * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
+ * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
+ *
+ * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
+ *
+ * Adapted for BlackFin BF533 by Bas Vermeulen <bas@buyways.nl>
+ * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF533_IRQ_H_
+#define _BF533_IRQ_H_
+
+/*
+ * Interrupt source definitions
+ * Event Source                        Core Event Name         Number
+ *                             EMU                     0
+ * Reset                       RST                     1
+ * NMI                         NMI                     2
+ * Exception                   EVX                     3
+ * Reserved                    --                      4
+ * Hardware Error              IVHW                    5
+ * Core Timer                  IVTMR                   6
+ * PLL Wakeup Interrupt                IVG7                    7
+ * DMA Error (generic)         IVG7                    8
+ * PPI Error Interrupt         IVG7                    9
+ * SPORT0 Error Interrupt      IVG7                    10
+ * SPORT1 Error Interrupt      IVG7                    11
+ * SPI Error Interrupt         IVG7                    12
+ * UART Error Interrupt                IVG7                    13
+ * RTC Interrupt               IVG8                    14
+ * DMA0 Interrupt (PPI)                IVG8                    15
+ * DMA1 (SPORT0 RX)            IVG9                    16
+ * DMA2 (SPORT0 TX)            IVG9                    17
+ * DMA3 (SPORT1 RX)            IVG9                    18
+ * DMA4 (SPORT1 TX)            IVG9                    19
+ * DMA5 (PPI)                  IVG10                   20
+ * DMA6 (UART RX)              IVG10                   21
+ * DMA7 (UART TX)              IVG10                   22
+ * Timer0                      IVG11                   23
+ * Timer1                      IVG11                   24
+ * Timer2                      IVG11                   25
+ * PF Interrupt A              IVG12                   26
+ * PF Interrupt B              IVG12                   27
+ * DMA8/9 Interrupt            IVG13                   28
+ * DMA10/11 Interrupt          IVG13                   29
+ * Watchdog Timer              IVG13                   30
+ * Software Interrupt 1                IVG14                   31
+ * Software Interrupt 2                --
+ * (lowest priority)           IVG15                   32
+ */
+
+/* The ABSTRACT IRQ definitions */
+
+/* The first seven of the following are fixed,
+ * the rest you change if you need to
+ */
+
+#define        IRQ_EMU                 0       /* Emulation */
+#define        IRQ_RST                 1       /* reset */
+#define        IRQ_NMI                 2       /* Non Maskable */
+#define        IRQ_EVX                 3       /* Exception */
+#define        IRQ_UNUSED              4       /*  - unused interrupt */
+#define        IRQ_HWERR               5       /* Hardware Error */
+#define        IRQ_CORETMR             6       /* Core timer */
+#define        IRQ_PLL_WAKEUP          7       /* PLL Wakeup Interrupt */
+#define        IRQ_DMA_ERROR           8       /* DMA Error (general) */
+#define        IRQ_PPI_ERROR           9       /* PPI Error Interrupt */
+#define        IRQ_SPORT0_ERROR        10      /* SPORT0 Error Interrupt */
+#define        IRQ_SPORT1_ERROR        11      /* SPORT1 Error Interrupt */
+#define        IRQ_SPI_ERROR           12      /* SPI Error Interrupt */
+#define        IRQ_UART_ERROR          13      /* UART Error Interrupt */
+#define        IRQ_RTC                 14      /* RTC Interrupt */
+#define        IRQ_PPI                 15      /* DMA0 Interrupt (PPI) */
+#define        IRQ_SPORT0              16      /* DMA1 Interrupt (SPORT0 RX) */
+#define        IRQ_SPARE1              17      /* DMA2 Interrupt (SPORT0 TX) */
+#define        IRQ_SPORT1              18      /* DMA3 Interrupt (SPORT1 RX) */
+#define        IRQ_SPARE2              19      /* DMA4 Interrupt (SPORT1 TX) */
+#define IRQ_SPI                        20      /* DMA5 Interrupt (SPI) */
+#define        IRQ_UART                21      /* DMA6 Interrupt (UART RX) */
+#define        IRQ_SPARE3              22      /* DMA7 Interrupt (UART TX) */
+#define        IRQ_TMR0                23      /* Timer 0 */
+#define        IRQ_TMR1                24      /* Timer 1 */
+#define        IRQ_TMR2                25      /* Timer 2 */
+#define        IRQ_PROG_INTA           26      /* Programmable Flags A (8) */
+#define        IRQ_PROG_INTB           27      /* Programmable Flags B (8) */
+#define        IRQ_MEM_DMA0            28      /* DMA8/9 Interrupt (Memory DMA Stream 0) */
+#define        IRQ_MEM_DMA1            29      /* DMA10/11 Interrupt (Memory DMA Stream 1) */
+#define        IRQ_WATCH               30      /* Watch Dog Timer */
+#define        IRQ_SW_INT1             31      /* Software Int 1 */
+#define        IRQ_SW_INT2             32      /* Software Int 2 (reserved for SYSCALL) */
+
+#define IRQ_UART_RX_BIT                0x4000
+#define IRQ_UART_TX_BIT                0x8000
+#define IRQ_UART_ERROR_BIT     0x40
+
+#define IVG7                   7
+#define IVG8                   8
+#define IVG9                   9
+#define IVG10                  10
+#define IVG11                  11
+#define IVG12                  12
+#define IVG13                  13
+#define IVG14                  14
+#define IVG15                  15
+#define SYS_IRQS               33
+
+#endif

diff --git a/include/asm-blackfin/cpu/bf533_rtc.h b/include/asm-blackfin/cpu/bf533_rtc.h
new file mode 100644 (file)
index 0000000..bc09922
--- /dev/null
+++ b/include/asm-blackfin/cpu/bf533_rtc.h
@@ -0,0 +1,46 @@
+/*
+ * U-boot - bf533_rtc.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF533_RTC_H_
+#define _BF533_RTC_H_
+
+void rtc_init(void);
+void wait_for_complete(void);
+void rtc_reset(void);
+
+#define MIN_TO_SECS(_x_)       (60 * _x_)
+#define HRS_TO_SECS(_x_)       (60 * 60 * _x_)
+#define DAYS_TO_SECS(_x_)      (24 * 60 * 60 * _x_)
+
+#define NUM_SECS_IN_DAY                (24 * 3600)
+#define NUM_SECS_IN_HOUR       (3600)
+#define NUM_SECS_IN_MIN                (60)
+
+/* Shift values for RTC_STAT register */
+#define DAY_BITS_OFF           17
+#define HOUR_BITS_OFF          12
+#define MIN_BITS_OFF           6
+#define SEC_BITS_OFF           0
+
+#endif

diff --git a/include/asm-blackfin/cpu/bf533_serial.h b/include/asm-blackfin/cpu/bf533_serial.h
new file mode 100644 (file)
index 0000000..d5e162a
--- /dev/null
+++ b/include/asm-blackfin/cpu/bf533_serial.h
@@ -0,0 +1,79 @@
+/*
+ * U-boot bf533_serial.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef _BF533_SERIAL_H_
+#define _BF533_SERIAL_H_
+
+#define BYTE_REF(addr)         (*((volatile char*)addr))
+#define HALFWORD_REF(addr)     (*((volatile short*)addr))
+#define WORD_REF(addr)         (*((volatile long*)addr))
+
+#define UART_THR_LO            HALFWORD_REF(UART_THR)
+#define UART_RBR_LO            HALFWORD_REF(UART_RBR)
+#define UART_DLL_LO            HALFWORD_REF(UART_DLL)
+#define UART_IER_LO            HALFWORD_REF(UART_IER)
+#define UART_IER_ERBFI         0x01
+#define UART_IER_ETBEI         0x02
+#define UART_IER_ELSI          0x04
+#define UART_IER_EDDSI         0x08
+
+#define UART_DLH_LO            HALFWORD_REF(UART_DLH)
+#define UART_IIR_LO            HALFWORD_REF(UART_IIR)
+#define UART_IIR_NOINT         0x01
+#define UART_IIR_STATUS                0x06
+#define UART_IIR_LSR           0x06
+#define UART_IIR_RBR           0x04
+#define UART_IIR_THR           0x02
+#define UART_IIR_MSR           0x00
+
+#define UART_LCR_LO            HALFWORD_REF(UART_LCR)
+#define UART_LCR_WLS5          0
+#define UART_LCR_WLS6          0x01
+#define UART_LCR_WLS7          0x02
+#define UART_LCR_WLS8          0x03
+#define UART_LCR_STB           0x04
+#define UART_LCR_PEN           0x08
+#define UART_LCR_EPS           0x10
+#define UART_LCR_SP            0x20
+#define UART_LCR_SB            0x40
+#define UART_LCR_DLAB          0x80
+
+#define UART_MCR_LO            HALFWORD_REF(UART_MCR)
+
+#define UART_LSR_LO            HALFWORD_REF(UART_LSR)
+#define UART_LSR_DR            0x01
+#define UART_LSR_OE            0x02
+#define UART_LSR_PE            0x04
+#define UART_LSR_FE            0x08
+#define UART_LSR_BI            0x10
+#define UART_LSR_THRE          0x20
+#define UART_LSR_TEMT          0x40
+
+#define UART_MSR_LO            HALFWORD_REF(UART_MSR)
+#define UART_SCR_LO            HALFWORD_REF(UART_SCR)
+#define UART_GCTL_LO           HALFWORD_REF(UART_GCTL)
+#define UART_GCTL_UCEN         0x01
+
+#endif

diff --git a/include/asm-blackfin/cpu/cdefBF531.h b/include/asm-blackfin/cpu/cdefBF531.h
new file mode 100644 (file)
index 0000000..68d841d
--- /dev/null
+++ b/include/asm-blackfin/cpu/cdefBF531.h
@@ -0,0 +1,24 @@
+/*
+ * cdefBF531.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _CDEFBF531_H
+#define _CDEFBF531_H
+
+#include <cdefBF532.h>
+
+#endif /* _CDEFBF531_H */

diff --git a/include/asm-blackfin/cpu/cdefBF532.h b/include/asm-blackfin/cpu/cdefBF532.h
new file mode 100644 (file)
index 0000000..a4d422f
--- /dev/null
+++ b/include/asm-blackfin/cpu/cdefBF532.h
@@ -0,0 +1,398 @@
+/*
+ * cdefBF532.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _CDEF_BF532_H
+#define _CDEF_BF532_H
+
+/*
+ * #if !defined(__ADSPLPBLACKFIN__)
+ * #warning cdefBF532.h should only be included for 532 compatible chips.
+ * #endif
+ */
+
+/* include all Core registers and bit definitions */
+#include <asm/cpu/defBF532.h>
+
+/* include core specific register pointer definitions */
+#include <asm/cpu/cdef_LPBlackfin.h>
+
+/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
+#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
+#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
+#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
+#define pCHIPID ((volatile unsigned long *)CHIPID)
+#define pSWRST ((volatile unsigned short *)SWRST)
+#define pSYSCR ((volatile unsigned short *)SYSCR)
+#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
+#define pVR_CTL ((volatile unsigned short *)VR_CTL)
+
+/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
+#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
+#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
+#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
+#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3)
+#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)
+#define pSIC_ISR ((volatile unsigned long *)SIC_ISR)
+#define pSIC_IWR ((volatile unsigned long *)SIC_IWR)
+
+/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
+#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
+#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
+#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
+
+/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
+#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
+#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
+#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
+#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
+#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
+#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
+#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)
+
+/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
+#define pFIO_DIR ((volatile unsigned short *)FIO_DIR)
+#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C)
+#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S)
+#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C)
+#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S)
+#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C)
+#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S)
+#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR)
+#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE)
+#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH)
+#define pFIO_INEN ((volatile unsigned short *)FIO_INEN)
+#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D)
+#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T)
+#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D)
+#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T)
+#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D)
+#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T)
+
+/* DMA Test Registers */
+#define pDMA_CCOMP     ((volatile unsigned long *)DMA_CCOMP)
+#define        pDMA_ACOMP      ((volatile unsigned long *)DMA_ACOMP)
+#define        pDMA_MISR       ((volatile unsigned long *)DMA_MISR)
+#define        pDMA_TCPER      ((volatile unsigned short *)DMA_TCPER)
+#define        pDMA_TCCNT      ((volatile unsigned short *)DMA_TCCNT)
+#define        pDMA_TMODE      ((volatile unsigned short *)DMA_TMODE)
+#define        pDMA_TMCHAN     ((volatile unsigned short *)DMA_TMCHAN)
+#define        pDMA_TMSTAT     ((volatile unsigned short *)DMA_TMSTAT)
+#define        pDMA_TMBD       ((volatile unsigned short *)DMA_TMBD)
+#define        pDMA_TMM0D      ((volatile unsigned short *)DMA_TMM0D)
+#define        pDMA_TMM1D      ((volatile unsigned short *)DMA_TMM1D)
+#define pDMA_TMMA      ((volatile void **)DMA_TMMA)
+
+/* DMA Controller */
+#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
+#define pDMA0_NEXT_DESC_PTR ((volatile void **)DMA0_NEXT_DESC_PTR)
+#define pDMA0_START_ADDR ((volatile void **)DMA0_START_ADDR)
+#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
+#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
+#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
+#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
+#define pDMA0_CURR_DESC_PTR ((volatile void **)DMA0_CURR_DESC_PTR)
+#define pDMA0_CURR_ADDR ((volatile void **)DMA0_CURR_ADDR)
+#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
+#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
+#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
+#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
+
+#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
+#define pDMA1_NEXT_DESC_PTR ((volatile void **)DMA1_NEXT_DESC_PTR)
+#define pDMA1_START_ADDR ((volatile void **)DMA1_START_ADDR)
+#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
+#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
+#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
+#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
+#define pDMA1_CURR_DESC_PTR ((volatile void **)DMA1_CURR_DESC_PTR)
+#define pDMA1_CURR_ADDR ((volatile void **)DMA1_CURR_ADDR)
+#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
+#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
+#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
+#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
+
+#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
+#define pDMA2_NEXT_DESC_PTR ((volatile void **)DMA2_NEXT_DESC_PTR)
+#define pDMA2_START_ADDR ((volatile void **)DMA2_START_ADDR)
+#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
+#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
+#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
+#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
+#define pDMA2_CURR_DESC_PTR ((volatile void **)DMA2_CURR_DESC_PTR)
+#define pDMA2_CURR_ADDR ((volatile void **)DMA2_CURR_ADDR)
+#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
+#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
+#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
+#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
+
+#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
+#define pDMA3_NEXT_DESC_PTR ((volatile void **)DMA3_NEXT_DESC_PTR)
+#define pDMA3_START_ADDR ((volatile void **)DMA3_START_ADDR)
+#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
+#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
+#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
+#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
+#define pDMA3_CURR_DESC_PTR ((volatile void **)DMA3_CURR_DESC_PTR)
+#define pDMA3_CURR_ADDR ((volatile void **)DMA3_CURR_ADDR)
+#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
+#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
+#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
+#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
+
+#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
+#define pDMA4_NEXT_DESC_PTR ((volatile void **)DMA4_NEXT_DESC_PTR)
+#define pDMA4_START_ADDR ((volatile void **)DMA4_START_ADDR)
+#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
+#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
+#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
+#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
+#define pDMA4_CURR_DESC_PTR ((volatile void **)DMA4_CURR_DESC_PTR)
+#define pDMA4_CURR_ADDR ((volatile void **)DMA4_CURR_ADDR)
+#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
+#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
+#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
+#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
+
+#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
+#define pDMA5_NEXT_DESC_PTR ((volatile void **)DMA5_NEXT_DESC_PTR)
+#define pDMA5_START_ADDR ((volatile void **)DMA5_START_ADDR)
+#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
+#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
+#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
+#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
+#define pDMA5_CURR_DESC_PTR ((volatile void **)DMA5_CURR_DESC_PTR)
+#define pDMA5_CURR_ADDR ((volatile void **)DMA5_CURR_ADDR)
+#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
+#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
+#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
+#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
+
+#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
+#define pDMA6_NEXT_DESC_PTR ((volatile void **)DMA6_NEXT_DESC_PTR)
+#define pDMA6_START_ADDR ((volatile void **)DMA6_START_ADDR)
+#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
+#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
+#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
+#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
+#define pDMA6_CURR_DESC_PTR ((volatile void **)DMA6_CURR_DESC_PTR)
+#define pDMA6_CURR_ADDR ((volatile void **)DMA6_CURR_ADDR)
+#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
+#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
+#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
+#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
+
+#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
+#define pDMA7_NEXT_DESC_PTR ((volatile void **)DMA7_NEXT_DESC_PTR)
+#define pDMA7_START_ADDR ((volatile void **)DMA7_START_ADDR)
+#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
+#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
+#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
+#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
+#define pDMA7_CURR_DESC_PTR ((volatile void **)DMA7_CURR_DESC_PTR)
+#define pDMA7_CURR_ADDR ((volatile void **)DMA7_CURR_ADDR)
+#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
+#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
+#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
+#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
+
+#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG)
+#define pMDMA_D1_NEXT_DESC_PTR ((volatile void **)MDMA_D1_NEXT_DESC_PTR)
+#define pMDMA_D1_START_ADDR ((volatile void **)MDMA_D1_START_ADDR)
+#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT)
+#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT)
+#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY)
+#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY)
+#define pMDMA_D1_CURR_DESC_PTR ((volatile void **)MDMA_D1_CURR_DESC_PTR)
+#define pMDMA_D1_CURR_ADDR ((volatile void **)MDMA_D1_CURR_ADDR)
+#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
+#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
+#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
+#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
+
+#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG)
+#define pMDMA_S1_NEXT_DESC_PTR ((volatile void **)MDMA_S1_NEXT_DESC_PTR)
+#define pMDMA_S1_START_ADDR ((volatile void **)MDMA_S1_START_ADDR)
+#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT)
+#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT)
+#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY)
+#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY)
+#define pMDMA_S1_CURR_DESC_PTR ((volatile void **)MDMA_S1_CURR_DESC_PTR)
+#define pMDMA_S1_CURR_ADDR ((volatile void **)MDMA_S1_CURR_ADDR)
+#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
+#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
+#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
+#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
+
+#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG)
+#define pMDMA_D0_NEXT_DESC_PTR ((volatile void **)MDMA_D0_NEXT_DESC_PTR)
+#define pMDMA_D0_START_ADDR ((volatile void **)MDMA_D0_START_ADDR)
+#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT)
+#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT)
+#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY)
+#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY)
+#define pMDMA_D0_CURR_DESC_PTR ((volatile void **)MDMA_D0_CURR_DESC_PTR)
+#define pMDMA_D0_CURR_ADDR ((volatile void **)MDMA_D0_CURR_ADDR)
+#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
+#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
+#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
+#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
+
+#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG)
+#define pMDMA_S0_NEXT_DESC_PTR ((volatile void **)MDMA_S0_NEXT_DESC_PTR)
+#define pMDMA_S0_START_ADDR ((volatile void **)MDMA_S0_START_ADDR)
+#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT)
+#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT)
+#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY)
+#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY)
+#define pMDMA_S0_CURR_DESC_PTR ((volatile void **)MDMA_S0_CURR_DESC_PTR)
+#define pMDMA_S0_CURR_ADDR ((volatile void **)MDMA_S0_CURR_ADDR)
+#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
+#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
+#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
+#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
+
+/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
+#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
+#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
+#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
+
+/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */
+/* #define L1SBAR 0xFFC04840 */        /* L1 SRAM Base Address Register */
+/* #define L1CSR  0xFFC04844 */        /* L1 SRAM Control Initialization Register */
+
+/*
+ * #define pDB_ACOMP ((volatile void **)DB_ACOMP)
+ * #define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP)
+ */
+
+/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
+#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
+#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
+#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
+#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL)
+
+/* UART Controller */
+#define pUART_THR ((volatile unsigned short *)UART_THR)
+#define pUART_RBR ((volatile unsigned short *)UART_RBR)
+#define pUART_DLL ((volatile unsigned short *)UART_DLL)
+#define pUART_IER ((volatile unsigned short *)UART_IER)
+#define pUART_DLH ((volatile unsigned short *)UART_DLH)
+#define pUART_IIR ((volatile unsigned short *)UART_IIR)
+#define pUART_LCR ((volatile unsigned short *)UART_LCR)
+#define pUART_MCR ((volatile unsigned short *)UART_MCR)
+#define pUART_LSR ((volatile unsigned short *)UART_LSR)
+
+/*
+ * #define UART_MSR
+ */
+#define pUART_SCR ((volatile unsigned short *)UART_SCR)
+#define pUART_GCTL ((volatile unsigned short *)UART_GCTL)
+
+/* SPI Controller */
+#define pSPI_CTL ((volatile unsigned short *)SPI_CTL)
+#define pSPI_FLG ((volatile unsigned short *)SPI_FLG)
+#define pSPI_STAT ((volatile unsigned short *)SPI_STAT)
+#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR)
+#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR)
+#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD)
+#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW)
+
+/* TIMER 0, 1, 2 Registers */
+#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
+#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
+#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
+#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
+
+#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
+#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
+#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
+#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
+
+#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
+#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
+#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
+#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
+
+#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE)
+#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE)
+#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS)
+
+/* SPORT0 Controller */
+#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
+#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
+#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
+#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_TX ((volatile long *)SPORT0_TX)
+#define pSPORT0_RX ((volatile long *)SPORT0_RX)
+#define pSPORT0_TX32 ((volatile long *)SPORT0_TX)
+#define pSPORT0_RX32 ((volatile long *)SPORT0_RX)
+#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
+#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
+#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
+#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
+#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
+#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
+#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
+#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
+
+/* SPORT1 Controller */
+#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
+#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
+#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
+#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
+#define pSPORT1_TX ((volatile long *)SPORT1_TX)
+#define pSPORT1_RX ((volatile long *)SPORT1_RX)
+#define pSPORT1_TX32 ((volatile long *)SPORT1_TX)
+#define pSPORT1_RX32 ((volatile long *)SPORT1_RX)
+#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
+#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
+#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
+#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
+#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
+#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
+#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
+#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
+#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
+#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
+#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
+#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
+#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
+#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
+#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
+#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
+#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
+#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
+
+/* Parallel Peripheral Interface (PPI) */
+#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL)
+#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS)
+#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY)
+#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT)
+#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME)
+
+#endif /* _CDEF_BF532_H */

diff --git a/include/asm-blackfin/cpu/cdefBF533.h b/include/asm-blackfin/cpu/cdefBF533.h
new file mode 100644 (file)
index 0000000..8c751e6
--- /dev/null
+++ b/include/asm-blackfin/cpu/cdefBF533.h
@@ -0,0 +1,24 @@
+/*
+ * cdefBF533.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _CDEFBF533_H
+#define _CDEFBF533_H
+
+#include <asm/cpu/cdefBF532.h>
+
+#endif /* _CDEFBF533_H */

diff --git a/include/asm-blackfin/cpu/cdefBF53x.h b/include/asm-blackfin/cpu/cdefBF53x.h
new file mode 100644 (file)
index 0000000..db4eaa9
--- /dev/null
+++ b/include/asm-blackfin/cpu/cdefBF53x.h
@@ -0,0 +1,32 @@
+/************************************************************************
+ *
+ * cdefBF53x.h
+ *
+ * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
+ *
+ ************************************************************************/
+
+#ifndef _CDEFBF53x_H
+#define _CDEFBF53x_H
+
+#if defined(__ADSPBF531__)
+       #include <asm/cpu/cdefBF531.h>
+#elif defined(__ADSPBF532__)
+       #include <asm/cpu/cdefBF532.h>
+#elif defined(__ADSPBF533__)
+       #include <asm/cpu/cdefBF533.h>
+#elif defined(__ADSPBF561__)
+       #include <asm/cpu/cdefBF561.h>
+#elif defined(__ADSPBF535__)
+       #include <asm/cpu/cdefBF535.h>
+#elif defined(__AD6532__)
+       #include <sam/cpu/cdefAD6532.h>
+#else
+       #if defined(__ADSPLPBLACKFIN__)
+               #include <asm/cpu/cdefBF532.h>
+       #else
+               #include <asm/cpu/cdefBF535.h>
+       #endif
+#endif
+
+#endif /* _CDEFBF53x_H */

diff --git a/include/asm-blackfin/cpu/cdef_LPBlackfin.h b/include/asm-blackfin/cpu/cdef_LPBlackfin.h
new file mode 100644 (file)
index 0000000..e6471cb
--- /dev/null
+++ b/include/asm-blackfin/cpu/cdef_LPBlackfin.h
@@ -0,0 +1,185 @@
+/*
+ * cdef_LPBlackfin.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _CDEF_LPBLACKFIN_H
+#define _CDEF_LPBLACKFIN_H
+
+/*
+ * #if !defined(__ADSPLPBLACKFIN__)
+ * #warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
+ * #endif
+ */
+#include <asm/cpu/def_LPBlackfin.h>
+
+/* Cache & SRAM Memory */
+#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
+#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
+#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
+#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
+
+/* #define MMR_TIMEOUT 0xFFE00010 */   /* Memory-Mapped Register Timeout Register */
+#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
+#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
+#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
+#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3)
+#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4)
+#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5)
+#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6)
+#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7)
+#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8)
+#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9)
+#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10)
+#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11)
+#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12)
+#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13)
+#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14)
+#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15)
+#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
+#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
+#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
+#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
+#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
+#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
+#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
+#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
+#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
+#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
+#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
+#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
+#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
+#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
+#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
+#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
+#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
+
+/* #define DTEST_INDEX            0xFFE00304 */        /* Data Test Index Register */
+#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
+#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
+
+/*
+ * # define DTEST_DATA2        0xFFE00408   Data Test Data Register
+ * #define DTEST_DATA3 0xFFE0040C   Data Test Data Register
+ */
+#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
+#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
+#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
+#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0)
+#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1)
+#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2)
+#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3)
+#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4)
+#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5)
+#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6)
+#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7)
+#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8)
+#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9)
+#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10)
+#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11)
+#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12)
+#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13)
+#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14)
+#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15)
+#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
+#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
+#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
+#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
+#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
+#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
+#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
+#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
+#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
+#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
+#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
+#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
+#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
+#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
+#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
+#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
+#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
+
+/* #define ITEST_INDEX 0xFFE01304 */   /* Instruction Test Index Register */
+#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
+#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
+
+/* Event/Interrupt Registers */
+#define pEVT0 ((volatile void **)EVT0)
+#define pEVT1 ((volatile void **)EVT1)
+#define pEVT2 ((volatile void **)EVT2)
+#define pEVT3 ((volatile void **)EVT3)
+#define pEVT4 ((volatile void **)EVT4)
+#define pEVT5 ((volatile void **)EVT5)
+#define pEVT6 ((volatile void **)EVT6)
+#define pEVT7 ((volatile void **)EVT7)
+#define pEVT8 ((volatile void **)EVT8)
+#define pEVT9 ((volatile void **)EVT9)
+#define pEVT10 ((volatile void **)EVT10)
+#define pEVT11 ((volatile void **)EVT11)
+#define pEVT12 ((volatile void **)EVT12)
+#define pEVT13 ((volatile void **)EVT13)
+#define pEVT14 ((volatile void **)EVT14)
+#define pEVT15 ((volatile void **)EVT15)
+#define pIMASK ((volatile unsigned long *)IMASK)
+#define pIPEND ((volatile unsigned long *)IPEND)
+#define pILAT ((volatile unsigned long *)ILAT)
+
+/* Core Timer Registers */
+#define pTCNTL ((volatile unsigned long *)TCNTL)
+#define pTPERIOD ((volatile unsigned long *)TPERIOD)
+#define pTSCALE ((volatile unsigned long *)TSCALE)
+#define pTCOUNT ((volatile unsigned long *)TCOUNT)
+
+/* Debug/MP/Emulation Registers */
+#define pDSPID ((volatile unsigned long *)DSPID)
+#define pDBGCTL ((volatile unsigned long *)DBGCTL)
+#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
+#define pEMUDAT ((volatile unsigned long *)EMUDAT)
+
+/* Trace Buffer Registers */
+#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
+#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
+#define pTBUF ((volatile void **)TBUF)
+
+/* Watch Point Control Registers */
+#define pWPIACTL ((volatile unsigned long *)WPIACTL)
+#define pWPIA0 ((volatile void **)WPIA0)
+#define pWPIA1 ((volatile void **)WPIA1)
+#define pWPIA2 ((volatile void **)WPIA2)
+#define pWPIA3 ((volatile void **)WPIA3)
+#define pWPIA4 ((volatile void **)WPIA4)
+#define pWPIA5 ((volatile void **)WPIA5)
+#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
+#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
+#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
+#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
+#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
+#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
+#define pWPDACTL ((volatile unsigned long *)WPDACTL)
+#define pWPDA0 ((volatile void **)WPDA0)
+#define pWPDA1 ((volatile void **)WPDA1)
+#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
+#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
+#define pWPSTAT ((volatile unsigned long *)WPSTAT)
+
+/* Performance Monitor Registers */
+#define pPFCTL ((volatile unsigned long *)PFCTL)
+#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
+#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
+
+/* #define IPRIO 0xFFE02110 */ /* Core Interrupt Priority Register */
+
+#endif /* _CDEF_LPBLACKFIN_H */

diff --git a/include/asm-blackfin/cpu/defBF531.h b/include/asm-blackfin/cpu/defBF531.h
new file mode 100644 (file)
index 0000000..6c7cd5a
--- /dev/null
+++ b/include/asm-blackfin/cpu/defBF531.h
@@ -0,0 +1,24 @@
+/*
+ * defBF531.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _DEFBF531_H
+#define _DEFBF531_H
+
+#include <defBF532.h>
+
+#endif /* _DEFBF531_H */

diff --git a/include/asm-blackfin/cpu/defBF532.h b/include/asm-blackfin/cpu/defBF532.h
new file mode 100644 (file)
index 0000000..26a5fe6
--- /dev/null
+++ b/include/asm-blackfin/cpu/defBF532.h
@@ -0,0 +1,1159 @@
+/*
+ * defBF532.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
+
+#ifndef _DEF_BF532_H
+#define _DEF_BF532_H
+
+/*
+ * #if !defined(__ADSPLPBLACKFIN__)
+ * #warning defBF532.h should only be included for 532 compatible chips
+ * #endif
+ */
+
+/* include all Core registers and bit definitions */
+#include <asm/cpu/def_LPBlackfin.h>
+
+/* Helper macros
+ * usage:
+ *  P0.H = HI(UART_THR);
+ *  P0.L = LO(UART_THR);
+ */
+
+#define LO(con32)              ((con32) & 0xFFFF)
+#define lo(con32)              ((con32) & 0xFFFF)
+#define HI(con32)              (((con32) >> 16) & 0xFFFF)
+#define hi(con32)              (((con32) >> 16) & 0xFFFF)
+
+/*
+ * System MMR Register Map
+ */
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+#define PLL_CTL                        0xFFC00000      /* PLL Control register (16-bit) */
+#define PLL_DIV                        0xFFC00004      /* PLL Divide Register (16-bit) */
+#define VR_CTL                 0xFFC00008      /* Voltage Regulator Control Register (16-bit) */
+#define PLL_STAT               0xFFC0000C      /* PLL Status register (16-bit) */
+#define PLL_LOCKCNT            0xFFC00010      /* PLL Lock Count register (16-bit) */
+#define        CHIPID                  0xFFC00014      /* Chip ID register (32-bit)    */
+#define SWRST                  0xFFC00100      /* Software Reset Register (16-bit) */
+#define SYSCR                  0xFFC00104      /* System Configuration register */
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SIC_RVECT              0xFFC00108      /* Interrupt Reset Vector Address Register */
+#define SIC_IMASK              0xFFC0010C      /* Interrupt Mask Register */
+#define SIC_IAR0               0xFFC00110      /* Interrupt Assignment Register 0 */
+#define SIC_IAR1               0xFFC00114      /* Interrupt Assignment Register 1 */
+#define SIC_IAR2               0xFFC00118      /* Interrupt Assignment Register 2 */
+#define SIC_ISR                        0xFFC00120      /* Interrupt Status Register */
+#define SIC_IWR                        0xFFC00124      /* Interrupt Wakeup Register */
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define WDOG_CTL               0xFFC00200      /* Watchdog Control Register */
+#define WDOG_CNT               0xFFC00204      /* Watchdog Count Register */
+#define WDOG_STAT              0xFFC00208      /* Watchdog Status Register */
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define RTC_STAT               0xFFC00300      /* RTC Status Register */
+#define RTC_ICTL               0xFFC00304      /* RTC Interrupt Control Register */
+#define RTC_ISTAT              0xFFC00308      /* RTC Interrupt Status Register */
+#define RTC_SWCNT              0xFFC0030C      /* RTC Stopwatch Count Register */
+#define RTC_ALARM              0xFFC00310      /* RTC Alarm Time Register */
+#define RTC_FAST               0xFFC00314      /* RTC Prescaler Enable Register */
+#define RTC_PREN               0xFFC00314      /* RTC Prescaler Enable Register (alternate macro) */
+
+/* UART Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART_THR               0xFFC00400      /* Transmit Holding register */
+#define UART_RBR               0xFFC00400      /* Receive Buffer register */
+#define UART_DLL               0xFFC00400      /* Divisor Latch (Low-Byte) */
+#define UART_IER               0xFFC00404      /* Interrupt Enable Register */
+#define UART_DLH               0xFFC00404      /* Divisor Latch (High-Byte) */
+#define UART_IIR               0xFFC00408      /* Interrupt Identification Register */
+#define UART_LCR               0xFFC0040C      /* Line Control Register */
+#define UART_MCR               0xFFC00410      /* Modem Control Register */
+#define UART_LSR               0xFFC00414      /* Line Status Register */
+/* #define UART_MSR 0xFFC00418 */      /* Modem Status Register (UNUSED in ADSP-BF532) */
+#define UART_SCR               0xFFC0041C      /* SCR Scratch Register */
+#define UART_GCTL              0xFFC00424      /* Global Control Register */
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI_CTL                        0xFFC00500      /* SPI Control Register */
+#define SPI_FLG                        0xFFC00504      /* SPI Flag register */
+#define SPI_STAT               0xFFC00508      /* SPI Status register */
+#define SPI_TDBR               0xFFC0050C      /* SPI Transmit Data Buffer Register */
+#define SPI_RDBR               0xFFC00510      /* SPI Receive Data Buffer Register */
+#define SPI_BAUD               0xFFC00514      /* SPI Baud rate Register */
+#define SPI_SHADOW             0xFFC00518      /* SPI_RDBR Shadow Register */
+
+/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
+#define TIMER0_CONFIG          0xFFC00600      /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER         0xFFC00604      /* Timer 0 Counter Register */
+#define TIMER0_PERIOD          0xFFC00608      /* Timer 0 Period Register */
+#define TIMER0_WIDTH           0xFFC0060C      /* Timer 0 Width Register */
+
+#define TIMER1_CONFIG          0xFFC00610      /*  Timer 1 Configuration Register */
+#define TIMER1_COUNTER         0xFFC00614      /*  Timer 1 Counter Register */
+#define TIMER1_PERIOD          0xFFC00618      /*  Timer 1 Period Register */
+#define TIMER1_WIDTH           0xFFC0061C      /*  Timer 1 Width Register */
+
+#define TIMER2_CONFIG          0xFFC00620      /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER         0xFFC00624      /* Timer 2 Counter Register */
+#define TIMER2_PERIOD          0xFFC00628      /* Timer 2 Period Register */
+#define TIMER2_WIDTH           0xFFC0062C      /* Timer 2 Width Register */
+
+#define TIMER_ENABLE           0xFFC00640      /* Timer Enable Register */
+#define TIMER_DISABLE          0xFFC00644      /* Timer Disable Register */
+#define TIMER_STATUS           0xFFC00648      /* Timer Status Register */
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
+#define FIO_FLAG_D             0xFFC00700      /* Flag Mask to directly specify state of pins */
+#define FIO_FLAG_C             0xFFC00704      /* Peripheral Interrupt Flag Register (clear) */
+#define FIO_FLAG_S             0xFFC00708      /* Peripheral Interrupt Flag Register (set) */
+#define FIO_FLAG_T             0xFFC0070C      /* Flag Mask to directly toggle state of pins */
+#define FIO_MASKA_D            0xFFC00710      /* Flag Mask Interrupt A Register (set directly) */
+#define FIO_MASKA_C            0xFFC00714      /* Flag Mask Interrupt A Register (clear) */
+#define FIO_MASKA_S            0xFFC00718      /* Flag Mask Interrupt A Register (set) */
+#define FIO_MASKA_T            0xFFC0071C      /* Flag Mask Interrupt A Register (toggle) */
+#define FIO_MASKB_D            0xFFC00720      /* Flag Mask Interrupt B Register (set directly) */
+#define FIO_MASKB_C            0xFFC00724      /* Flag Mask Interrupt B Register (clear) */
+#define FIO_MASKB_S            0xFFC00728      /* Flag Mask Interrupt B Register (set) */
+#define FIO_MASKB_T            0xFFC0072C      /* Flag Mask Interrupt B Register (toggle) */
+#define FIO_DIR                        0xFFC00730      /* Peripheral Flag Direction Register */
+#define FIO_POLAR              0xFFC00734      /* Flag Source Polarity Register */
+#define FIO_EDGE               0xFFC00738      /* Flag Source Sensitivity Register */
+#define FIO_BOTH               0xFFC0073C      /* Flag Set on BOTH Edges Register */
+#define FIO_INEN               0xFFC00740      /* Flag Input Enable Register */
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1            0xFFC00800      /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2            0xFFC00804      /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV         0xFFC00808      /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV          0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX              0xFFC00810      /* SPORT0 TX Data Register */
+#define SPORT0_RX              0xFFC00818      /* SPORT0 RX Data Register */
+#define SPORT0_RCR1            0xFFC00820      /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2            0xFFC00824      /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV         0xFFC00828      /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV          0xFFC0082C      /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT            0xFFC00830      /* SPORT0 Status Register */
+#define SPORT0_CHNL            0xFFC00834      /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1           0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2           0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0           0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1           0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2           0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3           0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0           0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1           0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2           0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3           0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3 */
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1            0xFFC00900      /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2            0xFFC00904      /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV         0xFFC00908      /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV          0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX              0xFFC00910      /* SPORT1 TX Data Register */
+#define SPORT1_RX              0xFFC00918      /* SPORT1 RX Data Register */
+#define SPORT1_RCR1            0xFFC00920      /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2            0xFFC00924      /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV         0xFFC00928      /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV          0xFFC0092C      /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT            0xFFC00930      /* SPORT1 Status Register */
+#define SPORT1_CHNL            0xFFC00934      /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1           0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2           0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0           0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1           0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2           0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3           0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0           0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1           0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2           0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3           0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3 */
+
+/* Asynchronous Memory Controller - External Bus Interface Unit */
+#define EBIU_AMGCTL            0xFFC00A00      /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0           0xFFC00A04      /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1           0xFFC00A08      /* Asynchronous Memory Bank Control Register 1 */
+
+/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define EBIU_SDGCTL            0xFFC00A10      /* SDRAM Global Control Register */
+#define EBIU_SDBCTL            0xFFC00A14      /* SDRAM Bank Control Register */
+#define EBIU_SDRRC             0xFFC00A18      /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT            0xFFC00A1C      /* SDRAM Status Register */
+
+/* DMA Test Registers */
+#define DMA_CCOMP              0xFFC00B04      /* DMA Cycle Count Register */
+#define DMA_ACOMP              0xFFC00B00      /* Debug Compare Address Register */
+#define DMA_MISR               0xFFC00B08      /* MISR Register */
+#define DMA_TCPER              0xFFC00B0C      /* Traffic Control Periods Register */
+#define DMA_TCCNT              0xFFC00B10      /* Traffic Control Current Counts Register */
+#define DMA_TMODE              0xFFC00B14      /* DMA Test Modes Register */
+#define DMA_TMCHAN             0xFFC00B18      /* DMA Testmode Selected Channel Register */
+#define DMA_TMSTAT             0xFFC00B1C      /* DMA Testmode Channel Status Register */
+#define DMA_TMBD               0xFFC00B20      /* DMA Testmode DAB Bus Data Register */
+#define DMA_TMM0D              0xFFC00B24      /* DMA Testmode Mem0 Data Register */
+#define DMA_TMM1D              0xFFC00B28      /* DMA Testmode Mem1 Data Register */
+#define DMA_TMMA               0xFFC00B2C      /* DMA Testmode Memory Address Register */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
+#define DMA0_CONFIG            0xFFC00C08      /* DMA Channel 0 Configuration Register */
+#define DMA0_NEXT_DESC_PTR     0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                0xFFC00C04      /* DMA Channel 0 Start Address Register */
+#define DMA0_X_COUNT           0xFFC00C10      /* DMA Channel 0 X Count Register */
+#define DMA0_Y_COUNT           0xFFC00C18      /* DMA Channel 0 Y Count Register */
+#define DMA0_X_MODIFY          0xFFC00C14      /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_MODIFY          0xFFC00C1C      /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR     0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR         0xFFC00C24      /* DMA Channel 0 Current Address Register */
+#define DMA0_CURR_X_COUNT      0xFFC00C30      /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT      0xFFC00C38      /* DMA Channel 0 Current Y Count Register */
+#define DMA0_IRQ_STATUS                0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP    0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register */
+
+#define DMA1_CONFIG            0xFFC00C48      /* DMA Channel 1 Configuration Register */
+#define DMA1_NEXT_DESC_PTR     0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                0xFFC00C44      /* DMA Channel 1 Start Address Register */
+#define DMA1_X_COUNT           0xFFC00C50      /* DMA Channel 1 X Count Register */
+#define DMA1_Y_COUNT           0xFFC00C58      /* DMA Channel 1 Y Count Register */
+#define DMA1_X_MODIFY          0xFFC00C54      /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_MODIFY          0xFFC00C5C      /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR     0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR         0xFFC00C64      /* DMA Channel 1 Current Address Register */
+#define DMA1_CURR_X_COUNT      0xFFC00C70      /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT      0xFFC00C78      /* DMA Channel 1 Current Y Count Register */
+#define DMA1_IRQ_STATUS                0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP    0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register */
+
+#define DMA2_CONFIG            0xFFC00C88      /* DMA Channel 2 Configuration Register */
+#define DMA2_NEXT_DESC_PTR     0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                0xFFC00C84      /* DMA Channel 2 Start Address Register */
+#define DMA2_X_COUNT           0xFFC00C90      /* DMA Channel 2 X Count Register */
+#define DMA2_Y_COUNT           0xFFC00C98      /* DMA Channel 2 Y Count Register */
+#define DMA2_X_MODIFY          0xFFC00C94      /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_MODIFY          0xFFC00C9C      /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR     0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR         0xFFC00CA4      /* DMA Channel 2 Current Address Register */
+#define DMA2_CURR_X_COUNT      0xFFC00CB0      /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT      0xFFC00CB8      /* DMA Channel 2 Current Y Count Register */
+#define DMA2_IRQ_STATUS                0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP    0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register */
+
+#define DMA3_CONFIG            0xFFC00CC8      /* DMA Channel 3 Configuration Register */
+#define DMA3_NEXT_DESC_PTR     0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                0xFFC00CC4      /* DMA Channel 3 Start Address Register */
+#define DMA3_X_COUNT           0xFFC00CD0      /* DMA Channel 3 X Count Register */
+#define DMA3_Y_COUNT           0xFFC00CD8      /* DMA Channel 3 Y Count Register */
+#define DMA3_X_MODIFY          0xFFC00CD4      /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_MODIFY          0xFFC00CDC      /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR     0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR         0xFFC00CE4      /* DMA Channel 3 Current Address Register */
+#define DMA3_CURR_X_COUNT      0xFFC00CF0      /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT      0xFFC00CF8      /* DMA Channel 3 Current Y Count Register */
+#define DMA3_IRQ_STATUS                0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP    0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register */
+
+#define DMA4_CONFIG            0xFFC00D08      /* DMA Channel 4 Configuration Register */
+#define DMA4_NEXT_DESC_PTR     0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                0xFFC00D04      /* DMA Channel 4 Start Address Register */
+#define DMA4_X_COUNT           0xFFC00D10      /* DMA Channel 4 X Count Register */
+#define DMA4_Y_COUNT           0xFFC00D18      /* DMA Channel 4 Y Count Register */
+#define DMA4_X_MODIFY          0xFFC00D14      /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_MODIFY          0xFFC00D1C      /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR     0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR         0xFFC00D24      /* DMA Channel 4 Current Address Register */
+#define DMA4_CURR_X_COUNT      0xFFC00D30      /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT      0xFFC00D38      /* DMA Channel 4 Current Y Count Register */
+#define DMA4_IRQ_STATUS                0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP    0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register */
+
+#define DMA5_CONFIG            0xFFC00D48      /* DMA Channel 5 Configuration Register */
+#define DMA5_NEXT_DESC_PTR     0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                0xFFC00D44      /* DMA Channel 5 Start Address Register */
+#define DMA5_X_COUNT           0xFFC00D50      /* DMA Channel 5 X Count Register */
+#define DMA5_Y_COUNT           0xFFC00D58      /* DMA Channel 5 Y Count Register */
+#define DMA5_X_MODIFY          0xFFC00D54      /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_MODIFY          0xFFC00D5C      /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR     0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR         0xFFC00D64      /* DMA Channel 5 Current Address Register */
+#define DMA5_CURR_X_COUNT      0xFFC00D70      /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT      0xFFC00D78      /* DMA Channel 5 Current Y Count Register */
+#define DMA5_IRQ_STATUS                0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP    0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register */
+
+#define DMA6_CONFIG            0xFFC00D88      /* DMA Channel 6 Configuration Register */
+#define DMA6_NEXT_DESC_PTR     0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                0xFFC00D84      /* DMA Channel 6 Start Address Register */
+#define DMA6_X_COUNT           0xFFC00D90      /* DMA Channel 6 X Count Register */
+#define DMA6_Y_COUNT           0xFFC00D98      /* DMA Channel 6 Y Count Register */
+#define DMA6_X_MODIFY          0xFFC00D94      /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_MODIFY          0xFFC00D9C      /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR     0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR         0xFFC00DA4      /* DMA Channel 6 Current Address Register */
+#define DMA6_CURR_X_COUNT      0xFFC00DB0      /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT      0xFFC00DB8      /* DMA Channel 6 Current Y Count Register */
+#define DMA6_IRQ_STATUS                0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP    0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register */
+
+#define DMA7_CONFIG            0xFFC00DC8      /* DMA Channel 7 Configuration Register */
+#define DMA7_NEXT_DESC_PTR     0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                0xFFC00DC4      /* DMA Channel 7 Start Address Register */
+#define DMA7_X_COUNT           0xFFC00DD0      /* DMA Channel 7 X Count Register */
+#define DMA7_Y_COUNT           0xFFC00DD8      /* DMA Channel 7 Y Count Register */
+#define DMA7_X_MODIFY          0xFFC00DD4      /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_MODIFY          0xFFC00DDC      /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR     0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR         0xFFC00DE4      /* DMA Channel 7 Current Address Register */
+#define DMA7_CURR_X_COUNT      0xFFC00DF0      /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT      0xFFC00DF8      /* DMA Channel 7 Current Y Count Register */
+#define DMA7_IRQ_STATUS                0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP    0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register */
+
+#define MDMA_D1_CONFIG         0xFFC00E88      /* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_NEXT_DESC_PTR  0xFFC00E80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR     0xFFC00E84      /* MemDMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_X_COUNT                0xFFC00E90      /* MemDMA Stream 1 Destination X Count Register */
+#define MDMA_D1_Y_COUNT                0xFFC00E98      /* MemDMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_X_MODIFY       0xFFC00E94      /* MemDMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_MODIFY       0xFFC00E9C      /* MemDMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR  0xFFC00EA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR      0xFFC00EA4      /* MemDMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_CURR_X_COUNT   0xFFC00EB0      /* MemDMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT   0xFFC00EB8      /* MemDMA Stream 1 Destination Current Y Count Register */
+#define MDMA_D1_IRQ_STATUS     0xFFC00EA8      /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC      /* MemDMA Stream 1 Destination Peripheral Map Register */
+
+#define MDMA_S1_CONFIG         0xFFC00EC8      /* MemDMA Stream 1 Source Configuration Register */
+#define MDMA_S1_NEXT_DESC_PTR  0xFFC00EC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR     0xFFC00EC4      /* MemDMA Stream 1 Source Start Address Register */
+#define MDMA_S1_X_COUNT                0xFFC00ED0      /* MemDMA Stream 1 Source X Count Register */
+#define MDMA_S1_Y_COUNT                0xFFC00ED8      /* MemDMA Stream 1 Source Y Count Register */
+#define MDMA_S1_X_MODIFY       0xFFC00ED4      /* MemDMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_MODIFY       0xFFC00EDC      /* MemDMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR  0xFFC00EE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR      0xFFC00EE4      /* MemDMA Stream 1 Source Current Address Register */
+#define MDMA_S1_CURR_X_COUNT   0xFFC00EF0      /* MemDMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT   0xFFC00EF8      /* MemDMA Stream 1 Source Current Y Count Register */
+#define MDMA_S1_IRQ_STATUS     0xFFC00EE8      /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC      /* MemDMA Stream 1 Source Peripheral Map Register */
+
+#define MDMA_D0_CONFIG         0xFFC00E08      /* MemDMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_NEXT_DESC_PTR  0xFFC00E00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR     0xFFC00E04      /* MemDMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_X_COUNT                0xFFC00E10      /* MemDMA Stream 0 Destination X Count Register */
+#define MDMA_D0_Y_COUNT                0xFFC00E18      /* MemDMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_X_MODIFY       0xFFC00E14      /* MemDMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_MODIFY       0xFFC00E1C      /* MemDMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR  0xFFC00E20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR      0xFFC00E24      /* MemDMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_CURR_X_COUNT   0xFFC00E30      /* MemDMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT   0xFFC00E38      /* MemDMA Stream 0 Destination Current Y Count Register */
+#define MDMA_D0_IRQ_STATUS     0xFFC00E28      /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C      /* MemDMA Stream 0 Destination Peripheral Map Register */
+
+#define MDMA_S0_CONFIG         0xFFC00E48      /* MemDMA Stream 0 Source Configuration Register */
+#define MDMA_S0_NEXT_DESC_PTR  0xFFC00E40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR     0xFFC00E44      /* MemDMA Stream 0 Source Start Address Register */
+#define MDMA_S0_X_COUNT                0xFFC00E50      /* MemDMA Stream 0 Source X Count Register */
+#define MDMA_S0_Y_COUNT                0xFFC00E58      /* MemDMA Stream 0 Source Y Count Register */
+#define MDMA_S0_X_MODIFY       0xFFC00E54      /* MemDMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_MODIFY       0xFFC00E5C      /* MemDMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR  0xFFC00E60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR      0xFFC00E64      /* MemDMA Stream 0 Source Current Address Register */
+#define MDMA_S0_CURR_X_COUNT   0xFFC00E70      /* MemDMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT   0xFFC00E78      /* MemDMA Stream 0 Source Current Y Count Register */
+#define MDMA_S0_IRQ_STATUS     0xFFC00E68      /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C      /* MemDMA Stream 0 Source Peripheral Map Register */
+
+/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
+#define PPI_CONTROL            0xFFC01000      /* PPI Control Register */
+#define PPI_STATUS             0xFFC01004      /* PPI Status Register */
+#define PPI_COUNT              0xFFC01008      /* PPI Transfer Count Register */
+#define PPI_DELAY              0xFFC0100C      /* PPI Delay Count Register */
+#define PPI_FRAME              0xFFC01010      /* PPI Frame Length Register */
+
+/*
+ * System MMR Register Bits
+ */
+/*
+ * PLL AND RESET MASKS
+ */
+
+/* PLL_CTL Masks */
+#define PLL_CLKIN              0x00000000      /* Pass CLKIN to PLL */
+#define PLL_CLKIN_DIV2         0x00000001      /* Pass CLKIN/2 to PLL */
+#define PLL_OFF                        0x00000002      /* Shut off PLL clocks */
+#define STOPCK_OFF             0x00000008      /* Core clock off */
+#define PDWN                   0x00000020      /* Put the PLL in a Deep Sleep state */
+#define BYPASS                 0x00000100      /* Bypass the PLL */
+
+/* PLL_DIV Masks */
+#define SCLK_DIV(x)            (x)             /* SCLK = VCO / x */
+
+#define CCLK_DIV1              0x00000000      /* CCLK = VCO / 1 */
+#define CCLK_DIV2              0x00000010      /* CCLK = VCO / 2 */
+#define CCLK_DIV4              0x00000020      /* CCLK = VCO / 4 */
+#define CCLK_DIV8              0x00000030      /* CCLK = VCO / 8 */
+
+/* SWRST Mask */
+#define SYSTEM_RESET           0x00000007      /* Initiates a system software reset */
+
+/*
+ * SYSTEM INTERRUPT CONTROLLER MASKS
+ */
+
+/* SIC_IAR0 Masks */
+#define P0_IVG(x)              ((x)-7)         /* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x)              ((x)-7) << 0x4  /* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x)              ((x)-7) << 0x8  /* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x)              ((x)-7) << 0xC  /* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x)              ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x)              ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x)              ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x)              ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
+
+/* SIC_IAR1 Masks */
+#define P8_IVG(x)              ((x)-7)         /* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x)              ((x)-7) << 0x4  /* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x)             ((x)-7) << 0x8  /* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x)             ((x)-7) << 0xC  /* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x)             ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x)             ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
+#define P14_IVG(x)             ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x)             ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
+
+/* SIC_IAR2 Masks */
+#define P16_IVG(x)             ((x)-7)         /* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x)             ((x)-7) << 0x4  /* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x)             ((x)-7) << 0x8  /* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x)             ((x)-7) << 0xC  /* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x)             ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x)             ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
+#define P22_IVG(x)             ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x)             ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
+
+/* SIC_IMASK Masks */
+#define SIC_UNMASK_ALL         0x00000000      /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL           0xFFFFFFFF      /* Mask all peripheral interrupts */
+#define SIC_MASK(x)            (1 << (x))      /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x)          (0xFFFFFFFF ^ (1 << (x)))       /* Unmask Peripheral #x interrupt */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL                0x00000000      /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL         0xFFFFFFFF      /* Wakeup Enable all peripherals */
+#define IWR_ENABLE(x)          (1 << (x))      /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x)         (0xFFFFFFFF ^ (1 << (x)))       /*  Wakeup Disable Peripheral #x */
+
+/*
+ * WATCHDOG TIMER MASKS
+ */
+/* Watchdog Timer WDOG_CTL Register */
+#define ICTL(x)                        ((x<<1) & 0x0006)
+#define ENABLE_RESET           0x00000000      /* Set Watchdog Timer to generate reset */
+#define ENABLE_NMI             0x00000002      /* Set Watchdog Timer to generate non-maskable interrupt */
+#define ENABLE_GPI             0x00000004      /* Set Watchdog Timer to generate general-purpose interrupt */
+#define DISABLE_EVT            0x00000006      /* Disable Watchdog Timer interrupts */
+
+#define TMR_EN                 0x0000
+#define TMR_DIS                        0x0AD0
+#define TRO                    0x8000
+
+#define ICTL_P0                        0x01
+#define ICTL_P1                        0x02
+#define TRO_P                  0x0F
+
+/* RTC_STAT and RTC_ALARM register */
+#define        RTSEC                   0x0000003F      /* Real-Time Clock Seconds */
+#define        RTMIN                   0x00000FC0      /* Real-Time Clock Minutes */
+#define        RTHR                    0x0001F000      /* Real-Time Clock Hours */
+#define        RTDAY                   0xFFFE0000      /* Real-Time Clock Days */
+
+/* RTC_ICTL register */
+#define        SWIE                    0x0001          /* Stopwatch Interrupt Enable */
+#define        AIE                     0x0002          /* Alarm Interrupt Enable */
+#define        SIE                     0x0004          /* Seconds (1 Hz) Interrupt Enable */
+#define        MIE                     0x0008          /* Minutes Interrupt Enable */
+#define        HIE                     0x0010          /* Hours Interrupt Enable */
+#define        DIE                     0x0020          /* 24 Hours (Days) Interrupt Enable */
+#define        DAIE                    0x0040          /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define        WCIE                    0x8000          /* Write Complete Interrupt Enable */
+
+/* RTC_ISTAT register */
+#define        SWEF                    0x0001          /* Stopwatch Event Flag */
+#define        AEF                     0x0002          /* Alarm Event Flag */
+#define        SEF                     0x0004          /* Seconds (1 Hz) Event Flag */
+#define        MEF                     0x0008          /* Minutes Event Flag */
+#define        HEF                     0x0010          /* Hours Event Flag */
+#define        DEF                     0x0020          /* 24 Hours (Days) Event Flag */
+#define        DAEF                    0x0040          /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
+#define        WPS                     0x4000          /* Write Pending Status (RO) */
+#define        WCOM                    0x8000          /* Write Complete */
+
+/* RTC_FAST Mask (RTC_PREN Mask) */
+#define ENABLE_PRESCALE                0x00000001      /* Enable prescaler so RTC runs at 1 Hz */
+#define PREN                   0x00000001      /* ** Must be set after power-up for proper operation of RTC */
+
+/*
+ * UART CONTROLLER MASKS
+ */
+
+/* UART_LCR Register */
+#define DLAB                   0x80
+#define SB                     0x40
+#define STP                    0x20
+#define EPS                    0x10
+#define PEN                    0x08
+#define STB                    0x04
+#define WLS(x)                 ((x-5) & 0x03)
+
+#define DLAB_P                 0x07
+#define SB_P                   0x06
+#define STP_P                  0x05
+#define EPS_P                  0x04
+#define PEN_P                  0x03
+#define STB_P                  0x02
+#define WLS_P1                 0x01
+#define WLS_P0                 0x00
+
+/* UART_MCR Register */
+#define LOOP_ENA               0x10
+#define LOOP_ENA_P             0x04
+
+/* UART_LSR Register */
+#define TEMT                   0x40
+#define THRE                   0x20
+#define BI                     0x10
+#define FE                     0x08
+#define PE                     0x04
+#define OE                     0x02
+#define DR                     0x01
+
+#define TEMP_P                 0x06
+#define THRE_P                 0x05
+#define BI_P                   0x04
+#define FE_P                   0x03
+#define PE_P                   0x02
+#define OE_P                   0x01
+#define DR_P                   0x00
+
+/* UART_IER Register */
+#define ELSI                   0x04
+#define ETBEI                  0x02
+#define ERBFI                  0x01
+
+#define ELSI_P                 0x02
+#define ETBEI_P                        0x01
+#define ERBFI_P                        0x00
+
+/* UART_IIR Register */
+#define STATUS(x)              ((x << 1) & 0x06)
+#define NINT                   0x01
+#define STATUS_P1              0x02
+#define STATUS_P0              0x01
+#define NINT_P                 0x00
+
+/* UART_GCTL Register */
+#define FFE                    0x20
+#define FPE                    0x10
+#define RPOLC                  0x08
+#define TPOLC                  0x04
+#define IREN                   0x02
+#define UCEN                   0x01
+
+#define FFE_P                  0x05
+#define FPE_P                  0x04
+#define RPOLC_P                        0x03
+#define TPOLC_P                        0x02
+#define IREN_P                 0x01
+#define UCEN_P                 0x00
+
+/*
+ * SERIAL PORT MASKS
+ */
+/* SPORTx_TCR1 Masks */
+#define TSPEN                  0x0001          /* TX enable */
+#define ITCLK                  0x0002          /* Internal TX Clock Select */
+#define TDTYPE                 0x000C          /* TX Data Formatting Select */
+#define TLSBIT                 0x0010          /* TX Bit Order */
+#define ITFS                   0x0200          /* Internal TX Frame Sync Select */
+#define TFSR                   0x0400          /* TX Frame Sync Required Select */
+#define DITFS                  0x0800          /* Data Independent TX Frame Sync Select */
+#define LTFS                   0x1000          /* Low TX Frame Sync Select */
+#define LATFS                  0x2000          /* Late TX Frame Sync Select */
+#define TCKFE                  0x4000          /* TX Clock Falling Edge Select */
+
+/* SPORTx_TCR2 Masks */
+#define SLEN                   0x001F          /*TX Word Length */
+#define TXSE                   0x0100          /*TX Secondary Enable */
+#define TSFSE                  0x0200          /*TX Stereo Frame Sync Enable */
+#define TRFST                  0x0400          /*TX Right-First Data Order */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN                  0x0001          /* RX enable */
+#define IRCLK                  0x0002          /* Internal RX Clock Select */
+#define RDTYPE                 0x000C          /* RX Data Formatting Select */
+#define RULAW                  0x0008          /* u-Law enable */
+#define RALAW                  0x000C          /* A-Law enable */
+#define RLSBIT                 0x0010          /* RX Bit Order */
+#define IRFS                   0x0200          /* Internal RX Frame Sync Select */
+#define RFSR                   0x0400          /* RX Frame Sync Required Select */
+#define LRFS                   0x1000          /* Low RX Frame Sync Select */
+#define LARFS                  0x2000          /* Late RX Frame Sync Select */
+#define RCKFE                  0x4000          /* RX Clock Falling Edge Select */
+
+/* SPORTx_RCR2 Masks */
+#define SLEN                   0x001F          /* RX Word Length */
+#define RXSE                   0x0100          /* RX Secondary Enable */
+#define RSFSE                  0x0200          /* RX Stereo Frame Sync Enable */
+#define RRFST                  0x0400          /* Right-First Data Order */
+
+/* SPORTx_STAT Masks */
+#define RXNE                   0x0001          /* RX FIFO Not Empty Status */
+#define RUVF                   0x0002          /* RX Underflow Status */
+#define ROVF                   0x0004          /* RX Overflow Status */
+#define TXF                    0x0008          /* TX FIFO Full Status */
+#define TUVF                   0x0010          /* TX Underflow Status */
+#define TOVF                   0x0020          /* TX Overflow Status */
+#define TXHRE                  0x0040          /* TX Hold Register Empty */
+
+/* SPORTx_MCMC1 Masks */
+#define WSIZE                  0x0000F000      /* Multichannel Window Size Field */
+#define WOFF                   0x000003FF      /* /Multichannel Window Offset Field */
+
+/* SPORTx_MCMC2 Masks */
+#define MCCRM                  0x00000003      /* Multichannel Clock Recovery Mode */
+#define MCDTXPE                        0x00000004      /* Multichannel DMA Transmit Packing */
+#define MCDRXPE                        0x00000008      /* Multichannel DMA Receive Packing */
+#define MCMEN                  0x00000010      /* Multichannel Frame Mode Enable */
+#define FSDR                   0x00000080      /* Multichannel Frame Sync to Data Relationship */
+#define MFD                    0x0000F000      /* Multichannel Frame Delay */
+
+/*
+ * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS
+ */
+
+/* PPI_CONTROL Masks */
+#define PORT_EN                        0x00000001      /* PPI Port Enable */
+#define PORT_DIR               0x00000002      /* PPI Port Direction */
+#define XFR_TYPE               0x0000000C      /* PPI Transfer Type */
+#define PORT_CFG               0x00000030      /* PPI Port Configuration */
+#define FLD_SEL                        0x00000040      /* PPI Active Field Select */
+#define PACK_EN                        0x00000080      /* PPI Packing Mode */
+#define DMA32                  0x00000100      /* PPI 32-bit DMA Enable */
+#define SKIP_EN                        0x00000200      /* PPI Skip Element Enable */
+#define SKIP_EO                        0x00000400      /* PPI Skip Even/Odd Elements */
+#define DLENGTH                        0x00003800      /* PPI Data Length */
+#define DLEN_8                 0x0             /* PPI Data Length mask for DLEN=8 */
+#define DLEN(x)                        (((x-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
+#define POL                    0x0000C000      /* PPI Signal Polarities */
+
+/* PPI_STATUS Masks */
+#define FLD                    0x00000400      /* Field Indicator */
+#define FT_ERR                 0x00000800      /* Frame Track Error */
+#define OVR                    0x00001000      /* FIFO Overflow Error */
+#define UNDR                   0x00002000      /* FIFO Underrun Error */
+#define ERR_DET                        0x00004000      /* Error Detected Indicator */
+#define ERR_NCOR               0x00008000      /* Error Not Corrected Indicator */
+
+/*
+ * DMA CONTROLLER MASKS
+ */
+
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define DMAEN                  0x00000001      /* Channel Enable */
+#define WNR                    0x00000002      /* Channel Direction (W/R*) */
+#define WDSIZE_8               0x00000000      /* Word Size 8 bits */
+#define WDSIZE_16              0x00000004      /* Word Size 16 bits */
+#define WDSIZE_32              0x00000008      /* Word Size 32 bits */
+#define DMA2D                  0x00000010      /* 2D/1D* Mode */
+#define RESTART                        0x00000020      /* Restart */
+#define DI_SEL                 0x00000040      /* Data Interrupt Select */
+#define DI_EN                  0x00000080      /* Data Interrupt Enable */
+#define NDSIZE                 0x00000900      /* Next Descriptor Size */
+#define FLOW                   0x00007000      /* Flow Control */
+
+#define DMAEN_P                        0               /* Channel Enable */
+#define WNR_P                  1               /* Channel Direction (W/R*) */
+#define DMA2D_P                        4               /* 2D/1D* Mode */
+#define RESTART_P              5               /* Restart */
+#define DI_SEL_P               6               /* Data Interrupt Select */
+#define DI_EN_P                        7               /* Data Interrupt Enable */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
+#define DMA_DONE               0x00000001      /* DMA Done Indicator */
+#define DMA_ERR                        0x00000002      /* DMA Error Indicator */
+#define DFETCH                 0x00000004      /* Descriptor Fetch Indicator */
+#define DMA_RUN                        0x00000008      /* DMA Running Indicator */
+
+#define DMA_DONE_P             0               /* DMA Done Indicator */
+#define DMA_ERR_P              1               /* DMA Error Indicator */
+#define DFETCH_P               2               /* Descriptor Fetch Indicator */
+#define DMA_RUN_P              3               /* DMA Running Indicator */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+#define CTYPE                  0x00000040      /* DMA Channel Type Indicator */
+#define CTYPE_P                        6               /* DMA Channel Type Indicator BIT POSITION */
+#define PCAP8                  0x00000080      /* DMA 8-bit Operation Indicator */
+#define PCAP16                 0x00000100      /* DMA 16-bit Operation Indicator */
+#define PCAP32                 0x00000200      /* DMA 32-bit Operation Indicator */
+#define PCAPWR                 0x00000400      /* DMA Write Operation Indicator */
+#define PCAPRD                 0x00000800      /* DMA Read Operation Indicator */
+#define PMAP                   0x00007000      /* DMA Peripheral Map Field */
+
+/*
+ * GENERAL PURPOSE TIMER MASKS
+ */
+
+/* PWM Timer bit definitions */
+
+/* TIMER_ENABLE Register */
+#define TIMEN0                 0x0001
+#define TIMEN1                 0x0002
+#define TIMEN2                 0x0004
+
+#define TIMEN0_P               0x00
+#define TIMEN1_P               0x01
+#define TIMEN2_P               0x02
+
+/* TIMER_DISABLE Register */
+#define TIMDIS0                        0x0001
+#define TIMDIS1                        0x0002
+#define TIMDIS2                        0x0004
+
+#define TIMDIS0_P              0x00
+#define TIMDIS1_P              0x01
+#define TIMDIS2_P              0x02
+
+/* TIMER_STATUS Register */
+#define TIMIL0                 0x0001
+#define TIMIL1                 0x0002
+#define TIMIL2                 0x0004
+#define TOVL_ERR0              0x0010
+#define TOVL_ERR1              0x0020
+#define TOVL_ERR2              0x0040
+#define TRUN0                  0x1000
+#define TRUN1                  0x2000
+#define TRUN2                  0x4000
+
+#define TIMIL0_P               0x00
+#define TIMIL1_P               0x01
+#define TIMIL2_P               0x02
+#define TOVL_ERR0_P            0x04
+#define TOVL_ERR1_P            0x05
+#define TOVL_ERR2_P            0x06
+#define TRUN0_P                        0x0C
+#define TRUN1_P                        0x0D
+#define TRUN2_P                        0x0E
+
+/* TIMERx_CONFIG Registers */
+#define PWM_OUT                        0x0001
+#define WDTH_CAP               0x0002
+#define EXT_CLK                        0x0003
+#define PULSE_HI               0x0004
+#define PERIOD_CNT             0x0008
+#define IRQ_ENA                        0x0010
+#define TIN_SEL                        0x0020
+#define OUT_DIS                        0x0040
+#define CLK_SEL                        0x0080
+#define TOGGLE_HI              0x0100
+#define EMU_RUN                        0x0200
+#define ERR_TYP(x)             ((x & 0x03) << 14)
+
+#define TMODE_P0               0x00
+#define TMODE_P1               0x01
+#define PULSE_HI_P             0x02
+#define PERIOD_CNT_P           0x03
+#define IRQ_ENA_P              0x04
+#define TIN_SEL_P              0x05
+#define OUT_DIS_P              0x06
+#define CLK_SEL_P              0x07
+#define TOGGLE_HI_P            0x08
+#define EMU_RUN_P              0x09
+#define ERR_TYP_P0             0x0E
+#define ERR_TYP_P1             0x0F
+
+/*
+ * PROGRAMMABLE FLAG MASKS
+ */
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
+#define PF0                    0x0001
+#define PF1                    0x0002
+#define PF2                    0x0004
+#define PF3                    0x0008
+#define PF4                    0x0010
+#define PF5                    0x0020
+#define PF6                    0x0040
+#define PF7                    0x0080
+#define PF8                    0x0100
+#define PF9                    0x0200
+#define PF10                   0x0400
+#define PF11                   0x0800
+#define PF12                   0x1000
+#define PF13                   0x2000
+#define PF14                   0x4000
+#define PF15                   0x8000
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
+#define PF0_P                  0
+#define PF1_P                  1
+#define PF2_P                  2
+#define PF3_P                  3
+#define PF4_P                  4
+#define PF5_P                  5
+#define PF6_P                  6
+#define PF7_P                  7
+#define PF8_P                  8
+#define PF9_P                  9
+#define PF10_P                 10
+#define PF11_P                 11
+#define PF12_P                 12
+#define PF13_P                 13
+#define PF14_P                 14
+#define PF15_P                 15
+
+/*
+ * SERIAL PERIPHERAL INTERFACE (SPI) MASKS
+ */
+
+/* SPI_CTL Masks */
+#define TIMOD                  0x00000003      /* Transfer initiation mode and interrupt generation */
+#define SZ                     0x00000004      /* Send Zero (=0) or last (=1) word when TDBR empty. */
+#define GM                     0x00000008      /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
+#define PSSE                   0x00000010      /* Enable (=1) Slave-Select input for Master. */
+#define EMISO                  0x00000020      /* Enable (=1) MISO pin as an output. */
+#define SIZE                   0x00000100      /* Word length (0 => 8 bits, 1 => 16 bits) */
+#define LSBF                   0x00000200      /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
+#define CPHA                   0x00000400      /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
+#define CPOL                   0x00000800      /* Clock polarity (0 => active-high, 1 => active-low) */
+#define MSTR                   0x00001000      /* Configures SPI as master (=1) or slave (=0) */
+#define WOM                    0x00002000      /* Open drain (=1) data output enable (for MOSI and MISO) */
+#define SPE                    0x00004000      /* SPI module enable (=1), disable (=0) */
+
+/* SPI_FLG Masks */
+#define FLS1                   0x00000002      /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2                   0x00000004      /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3                   0x00000008      /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4                   0x00000010      /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5                   0x00000020      /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6                   0x00000040      /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7                   0x00000080      /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1                   0x00000200      /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2                   0x00000400      /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3                   0x00000800      /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4                   0x00001000      /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5                   0x00002000      /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6                   0x00004000      /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7                   0x00008000      /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_FLG Bit Positions */
+#define FLS1_P                 0x00000001      /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2_P                 0x00000002      /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3_P                 0x00000003      /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4_P                 0x00000004      /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5_P                 0x00000005      /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6_P                 0x00000006      /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7_P                 0x00000007      /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1_P                 0x00000009      /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2_P                 0x0000000A      /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3_P                 0x0000000B      /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4_P                 0x0000000C      /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5_P                 0x0000000D      /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6_P                 0x0000000E      /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7_P                 0x0000000F      /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_STAT Masks */
+#define SPIF                   0x00000001      /* Set (=1) when SPI single-word transfer complete */
+#define MODF                   0x00000002      /* Set(=1)in a master device when some other device tries to become master */
+#define TXE                    0x00000004      /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
+#define TXS                    0x00000008      /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
+#define RBSY                   0x00000010      /* Set (=1) when data is received with RDBR full */
+#define RXS                    0x00000020      /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
+#define TXCOL                  0x00000040      /* When set (=1), corrupt data may have been transmitted */
+
+/*
+ * ASYNCHRONOUS MEMORY CONTROLLER MASKS
+ */
+
+/* AMGCTL Masks */
+#define AMCKEN                 0x00000001      /* Enable CLKOUT */
+#define AMBEN_B0               0x00000002      /* Enable Asynchronous Memory Bank 0 only */
+#define AMBEN_B0_B1            0x00000004      /* Enable Asynchronous Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2         0x00000006      /* Enable Asynchronous Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL              0x00000008      /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
+
+/* AMGCTL Bit Positions */
+#define AMCKEN_P               0x00000000      /* Enable CLKOUT */
+#define AMBEN_P0               0x00000001      /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
+#define AMBEN_P1               0x00000002      /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
+#define AMBEN_P2               0x00000003      /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
+
+/* AMBCTL0 Masks */
+#define B0RDYEN                        0x00000001      /* Bank 0 RDY Enable, 0=disable, 1=enable */
+#define B0RDYPOL               0x00000002      /* Bank 0 RDY Active high, 0=active low, 1=active high */
+#define B0TT_1                 0x00000004      /* Bank 0 Transition Time from Read to Write = 1 cycle */
+#define B0TT_2                 0x00000008      /* Bank 0 Transition Time from Read to Write = 2 cycles */
+#define B0TT_3                 0x0000000C      /* Bank 0 Transition Time from Read to Write = 3 cycles */
+#define B0TT_4                 0x00000000      /* Bank 0 Transition Time from Read to Write = 4 cycles */
+#define B0ST_1                 0x00000010      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
+#define B0ST_2                 0x00000020      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
+#define B0ST_3                 0x00000030      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
+#define B0ST_4                 0x00000000      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
+#define B0HT_1                 0x00000040      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
+#define B0HT_2                 0x00000080      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
+#define B0HT_3                 0x000000C0      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
+#define B0HT_0                 0x00000000      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
+#define B0RAT_1                        0x00000100      /* Bank 0 Read Access Time = 1 cycle */
+#define B0RAT_2                        0x00000200      /* Bank 0 Read Access Time = 2 cycles */
+#define B0RAT_3                        0x00000300      /* Bank 0 Read Access Time = 3 cycles */
+#define B0RAT_4                        0x00000400      /* Bank 0 Read Access Time = 4 cycles */
+#define B0RAT_5                        0x00000500      /* Bank 0 Read Access Time = 5 cycles */
+#define B0RAT_6                        0x00000600      /* Bank 0 Read Access Time = 6 cycles */
+#define B0RAT_7                        0x00000700      /* Bank 0 Read Access Time = 7 cycles */
+#define B0RAT_8                        0x00000800      /* Bank 0 Read Access Time = 8 cycles */
+#define B0RAT_9                        0x00000900      /* Bank 0 Read Access Time = 9 cycles */
+#define B0RAT_10               0x00000A00      /* Bank 0 Read Access Time = 10 cycles */
+#define B0RAT_11               0x00000B00      /* Bank 0 Read Access Time = 11 cycles */
+#define B0RAT_12               0x00000C00      /* Bank 0 Read Access Time = 12 cycles */
+#define B0RAT_13               0x00000D00      /* Bank 0 Read Access Time = 13 cycles */
+#define B0RAT_14               0x00000E00      /* Bank 0 Read Access Time = 14 cycles */
+#define B0RAT_15               0x00000F00      /* Bank 0 Read Access Time = 15 cycles */
+#define B0WAT_1                        0x00001000      /* Bank 0 Write Access Time = 1 cycle */
+#define B0WAT_2                        0x00002000      /* Bank 0 Write Access Time = 2 cycles */
+#define B0WAT_3                        0x00003000      /* Bank 0 Write Access Time = 3 cycles */
+#define B0WAT_4                        0x00004000      /* Bank 0 Write Access Time = 4 cycles */
+#define B0WAT_5                        0x00005000      /* Bank 0 Write Access Time = 5 cycles */
+#define B0WAT_6                        0x00006000      /* Bank 0 Write Access Time = 6 cycles */
+#define B0WAT_7                        0x00007000      /* Bank 0 Write Access Time = 7 cycles */
+#define B0WAT_8                        0x00008000      /* Bank 0 Write Access Time = 8 cycles */
+#define B0WAT_9                        0x00009000      /* Bank 0 Write Access Time = 9 cycles */
+#define B0WAT_10               0x0000A000      /* Bank 0 Write Access Time = 10 cycles */
+#define B0WAT_11               0x0000B000      /* Bank 0 Write Access Time = 11 cycles */
+#define B0WAT_12               0x0000C000      /* Bank 0 Write Access Time = 12 cycles */
+#define B0WAT_13               0x0000D000      /* Bank 0 Write Access Time = 13 cycles */
+#define B0WAT_14               0x0000E000      /* Bank 0 Write Access Time = 14 cycles */
+#define B0WAT_15               0x0000F000      /* Bank 0 Write Access Time = 15 cycles */
+#define B1RDYEN                        0x00010000      /* Bank 1 RDY enable, 0=disable, 1=enable */
+#define B1RDYPOL               0x00020000      /* Bank 1 RDY Active high, 0=active low, 1=active high */
+#define B1TT_1                 0x00040000      /* Bank 1 Transition Time from Read to Write = 1 cycle */
+#define B1TT_2                 0x00080000      /* Bank 1 Transition Time from Read to Write = 2 cycles */
+#define B1TT_3                 0x000C0000      /* Bank 1 Transition Time from Read to Write = 3 cycles */
+#define B1TT_4                 0x00000000      /* Bank 1 Transition Time from Read to Write = 4 cycles */
+#define B1ST_1                 0x00100000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B1ST_2                 0x00200000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B1ST_3                 0x00300000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B1ST_4                 0x00000000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B1HT_1                 0x00400000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B1HT_2                 0x00800000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B1HT_3                 0x00C00000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B1HT_0                 0x00000000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B1RAT_1                        0x01000000      /* Bank 1 Read Access Time = 1 cycle */
+#define B1RAT_2                        0x02000000      /* Bank 1 Read Access Time = 2 cycles */
+#define B1RAT_3                        0x03000000      /* Bank 1 Read Access Time = 3 cycles */
+#define B1RAT_4                        0x04000000      /* Bank 1 Read Access Time = 4 cycles */
+#define B1RAT_5                        0x05000000      /* Bank 1 Read Access Time = 5 cycles */
+#define B1RAT_6                        0x06000000      /* Bank 1 Read Access Time = 6 cycles */
+#define B1RAT_7                        0x07000000      /* Bank 1 Read Access Time = 7 cycles */
+#define B1RAT_8                        0x08000000      /* Bank 1 Read Access Time = 8 cycles */
+#define B1RAT_9                        0x09000000      /* Bank 1 Read Access Time = 9 cycles */
+#define B1RAT_10               0x0A000000      /* Bank 1 Read Access Time = 10 cycles */
+#define B1RAT_11               0x0B000000      /* Bank 1 Read Access Time = 11 cycles */
+#define B1RAT_12               0x0C000000      /* Bank 1 Read Access Time = 12 cycles */
+#define B1RAT_13               0x0D000000      /* Bank 1 Read Access Time = 13 cycles */
+#define B1RAT_14               0x0E000000      /* Bank 1 Read Access Time = 14 cycles */
+#define B1RAT_15               0x0F000000      /* Bank 1 Read Access Time = 15 cycles */
+#define B1WAT_1                        0x10000000      /* Bank 1 Write Access Time = 1 cycle */
+#define B1WAT_2                        0x20000000      /* Bank 1 Write Access Time = 2 cycles */
+#define B1WAT_3                        0x30000000      /* Bank 1 Write Access Time = 3 cycles */
+#define B1WAT_4                        0x40000000      /* Bank 1 Write Access Time = 4 cycles */
+#define B1WAT_5                        0x50000000      /* Bank 1 Write Access Time = 5 cycles */
+#define B1WAT_6                        0x60000000      /* Bank 1 Write Access Time = 6 cycles */
+#define B1WAT_7                        0x70000000      /* Bank 1 Write Access Time = 7 cycles */
+#define B1WAT_8                        0x80000000      /* Bank 1 Write Access Time = 8 cycles */
+#define B1WAT_9                        0x90000000      /* Bank 1 Write Access Time = 9 cycles */
+#define B1WAT_10               0xA0000000      /* Bank 1 Write Access Time = 10 cycles */
+#define B1WAT_11               0xB0000000      /* Bank 1 Write Access Time = 11 cycles */
+#define B1WAT_12               0xC0000000      /* Bank 1 Write Access Time = 12 cycles */
+#define B1WAT_13               0xD0000000      /* Bank 1 Write Access Time = 13 cycles */
+#define B1WAT_14               0xE0000000      /* Bank 1 Write Access Time = 14 cycles */
+#define B1WAT_15               0xF0000000      /* Bank 1 Write Access Time = 15 cycles */
+
+/* AMBCTL1 Masks */
+#define B2RDYEN                        0x00000001      /* Bank 2 RDY Enable, 0=disable, 1=enable */
+#define B2RDYPOL               0x00000002      /* Bank 2 RDY Active high, 0=active low, 1=active high */
+#define B2TT_1                 0x00000004      /* Bank 2 Transition Time from Read to Write = 1 cycle */
+#define B2TT_2                 0x00000008      /* Bank 2 Transition Time from Read to Write = 2 cycles */
+#define B2TT_3                 0x0000000C      /* Bank 2 Transition Time from Read to Write = 3 cycles */
+#define B2TT_4                 0x00000000      /* Bank 2 Transition Time from Read to Write = 4 cycles */
+#define B2ST_1                 0x00000010      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B2ST_2                 0x00000020      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B2ST_3                 0x00000030      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B2ST_4                 0x00000000      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B2HT_1                 0x00000040      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B2HT_2                 0x00000080      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B2HT_3                 0x000000C0      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B2HT_0                 0x00000000      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B2RAT_1                        0x00000100      /* Bank 2 Read Access Time = 1 cycle */
+#define B2RAT_2                        0x00000200      /* Bank 2 Read Access Time = 2 cycles */
+#define B2RAT_3                        0x00000300      /* Bank 2 Read Access Time = 3 cycles */
+#define B2RAT_4                        0x00000400      /* Bank 2 Read Access Time = 4 cycles */
+#define B2RAT_5                        0x00000500      /* Bank 2 Read Access Time = 5 cycles */
+#define B2RAT_6                        0x00000600      /* Bank 2 Read Access Time = 6 cycles */
+#define B2RAT_7                        0x00000700      /* Bank 2 Read Access Time = 7 cycles */
+#define B2RAT_8                        0x00000800      /* Bank 2 Read Access Time = 8 cycles */
+#define B2RAT_9                        0x00000900      /* Bank 2 Read Access Time = 9 cycles */
+#define B2RAT_10               0x00000A00      /* Bank 2 Read Access Time = 10 cycles */
+#define B2RAT_11               0x00000B00      /* Bank 2 Read Access Time = 11 cycles */
+#define B2RAT_12               0x00000C00      /* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13               0x00000D00      /* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14               0x00000E00      /* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15               0x00000F00      /* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1                        0x00001000      /* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2                        0x00002000      /* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3                        0x00003000      /* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4                        0x00004000      /* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5                        0x00005000      /* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6                        0x00006000      /* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7                        0x00007000      /* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8                        0x00008000      /* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9                        0x00009000      /* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10               0x0000A000      /* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11               0x0000B000      /* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12               0x0000C000      /* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13               0x0000D000      /* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14               0x0000E000      /* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15               0x0000F000      /* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN                        0x00010000      /* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL               0x00020000      /* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1                 0x00040000      /* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2                 0x00080000      /* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3                 0x000C0000      /* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4                 0x00000000      /* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1                 0x00100000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2                 0x00200000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3                 0x00300000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4                 0x00000000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1                 0x00400000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2                 0x00800000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3                 0x00C00000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0                 0x00000000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1                        0x01000000      /* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2                        0x02000000      /* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3                        0x03000000      /* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4                        0x04000000      /* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5                        0x05000000      /* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6                        0x06000000      /* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7                        0x07000000      /* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8                        0x08000000      /* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9                        0x09000000      /* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10               0x0A000000      /* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11               0x0B000000      /* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12               0x0C000000      /* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13               0x0D000000      /* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14               0x0E000000      /* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15               0x0F000000      /* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1                        0x10000000      /* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2                        0x20000000      /* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3                        0x30000000      /* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4                        0x40000000      /* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5                        0x50000000      /* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6                        0x60000000      /* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7                        0x70000000      /* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8                        0x80000000      /* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9                        0x90000000      /* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10               0xA0000000      /* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11               0xB0000000      /* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12               0xC0000000      /* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13               0xD0000000      /* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14               0xE0000000      /* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15               0xF0000000      /* Bank 3 Write Access Time = 15 cycles */
+
+/*
+ * SDRAM CONTROLLER MASKS
+ */
+
+/* SDGCTL Masks */
+#define SCTLE                  0x00000001      /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define CL_2                   0x00000008      /* SDRAM CAS latency = 2 cycles */
+#define CL_3                   0x0000000C      /* SDRAM CAS latency = 3 cycles */
+#define PFE                    0x00000010      /* Enable SDRAM prefetch */
+#define PFP                    0x00000020      /* Prefetch has priority over AMC requests */
+#define TRAS_1                 0x00000040      /* SDRAM tRAS = 1 cycle */
+#define TRAS_2                 0x00000080      /* SDRAM tRAS = 2 cycles */
+#define TRAS_3                 0x000000C0      /* SDRAM tRAS = 3 cycles */
+#define TRAS_4                 0x00000100      /* SDRAM tRAS = 4 cycles */
+#define TRAS_5                 0x00000140      /* SDRAM tRAS = 5 cycles */
+#define TRAS_6                 0x00000180      /* SDRAM tRAS = 6 cycles */
+#define TRAS_7                 0x000001C0      /* SDRAM tRAS = 7 cycles */
+#define TRAS_8                 0x00000200      /* SDRAM tRAS = 8 cycles */
+#define TRAS_9                 0x00000240      /* SDRAM tRAS = 9 cycles */
+#define TRAS_10                        0x00000280      /* SDRAM tRAS = 10 cycles */
+#define TRAS_11                        0x000002C0      /* SDRAM tRAS = 11 cycles */
+#define TRAS_12                        0x00000300      /* SDRAM tRAS = 12 cycles */
+#define TRAS_13                        0x00000340      /* SDRAM tRAS = 13 cycles */
+#define TRAS_14                        0x00000380      /* SDRAM tRAS = 14 cycles */
+#define TRAS_15                        0x000003C0      /* SDRAM tRAS = 15 cycles */
+#define TRP_1                  0x00000800      /* SDRAM tRP = 1 cycle */
+#define TRP_2                  0x00001000      /* SDRAM tRP = 2 cycles */
+#define TRP_3                  0x00001800      /* SDRAM tRP = 3 cycles */
+#define TRP_4                  0x00002000      /* SDRAM tRP = 4 cycles */
+#define TRP_5                  0x00002800      /* SDRAM tRP = 5 cycles */
+#define TRP_6                  0x00003000      /* SDRAM tRP = 6 cycles */
+#define TRP_7                  0x00003800      /* SDRAM tRP = 7 cycles */
+#define TRCD_1                 0x00008000      /* SDRAM tRCD = 1 cycle */
+#define TRCD_2                 0x00010000      /* SDRAM tRCD = 2 cycles */
+#define TRCD_3                 0x00018000      /* SDRAM tRCD = 3 cycles */
+#define TRCD_4                 0x00020000      /* SDRAM tRCD = 4 cycles */
+#define TRCD_5                 0x00028000      /* SDRAM tRCD = 5 cycles */
+#define TRCD_6                 0x00030000      /* SDRAM tRCD = 6 cycles */
+#define TRCD_7                 0x00038000      /* SDRAM tRCD = 7 cycles */
+#define TWR_1                  0x00080000      /* SDRAM tWR = 1 cycle */
+#define TWR_2                  0x00100000      /* SDRAM tWR = 2 cycles */
+#define TWR_3                  0x00180000      /* SDRAM tWR = 3 cycles */
+#define PUPSD                  0x00200000      /* Power-up start delay */
+#define PSM                    0x00400000      /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
+#define PSS                    0x00800000      /* enable SDRAM power-up sequence on next SDRAM access */
+#define SRFS                   0x01000000      /* Start SDRAM self-refresh mode */
+#define EBUFE                  0x02000000      /* Enable external buffering timing */
+#define FBBRW                  0x04000000      /* Fast back-to-back read write enable */
+#define EMREN                  0x10000000      /* Extended mode register enable */
+#define TCSR                   0x20000000      /* Temp compensated self refresh value 85 deg C */
+#define CDDBG                  0x40000000      /* Tristate SDRAM controls during bus grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE                    0x00000001      /* Enable SDRAM external bank */
+#define EBSZ_16                        0x00000000      /* SDRAM external bank size = 16MB */
+#define EBSZ_32                        0x00000002      /* SDRAM external bank size = 32MB */
+#define EBSZ_64                        0x00000004      /* SDRAM external bank size = 64MB */
+#define EBSZ_128               0x00000006      /* SDRAM external bank size = 128MB */
+#define EBCAW_8                        0x00000000      /* SDRAM external bank column address width = 8 bits */
+#define EBCAW_9                        0x00000010      /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_10               0x00000020      /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_11               0x00000030      /* SDRAM external bank column address width = 9 bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI                   0x00000001      /* SDRAM controller is idle */
+#define SDSRA                  0x00000002      /* SDRAM SDRAM self refresh is active */
+#define SDPUA                  0x00000004      /* SDRAM power up active */
+#define SDRS                   0x00000008      /* SDRAM is in reset state */
+#define SDEASE                 0x00000010      /* SDRAM EAB sticky error status - W1C */
+#define BGSTAT                 0x00000020      /* Bus granted */
+
+#endif /* _DEF_BF532_H */

diff --git a/include/asm-blackfin/cpu/defBF533.h b/include/asm-blackfin/cpu/defBF533.h
new file mode 100644 (file)
index 0000000..90e50af
--- /dev/null
+++ b/include/asm-blackfin/cpu/defBF533.h
@@ -0,0 +1,24 @@
+/*
+ * defBF533.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _DEFBF533_H
+#define _DEFBF533_H
+
+#include <asm/cpu/defBF532.h>
+
+#endif /* _DEFBF533_H */

diff --git a/include/asm-blackfin/cpu/defBF533_extn.h b/include/asm-blackfin/cpu/defBF533_extn.h
new file mode 100644 (file)
index 0000000..a9a1c7c
--- /dev/null
+++ b/include/asm-blackfin/cpu/defBF533_extn.h
@@ -0,0 +1,76 @@
+/*
+ * defBF533_extn.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _DEF_BF533_EXTN_H
+#define _DEF_BF533_EXTN_H
+
+#define OFFSET_( x )           ((x) & 0x0000FFFF) /* define macro for offset */
+/* Delay inserted for PLL transition */
+#define DELAY                  0x1000
+
+#define L1_ISRAM               0xFFA00000
+#define L1_ISRAM_END           0xFFA10000
+#define DATA_BANKA_SRAM                0xFF800000
+#define DATA_BANKA_SRAM_END    0xFF808000
+#define DATA_BANKB_SRAM                0xFF900000
+#define DATA_BANKB_SRAM_END    0xFF908000
+#define SYSMMR_BASE            0xFFC00000
+#define WDSIZE16               0x00000004
+
+/* Event Vector Table Address */
+#define EVT_EMULATION_ADDR     0xffe02000
+#define EVT_RESET_ADDR         0xffe02004
+#define EVT_NMI_ADDR           0xffe02008
+#define EVT_EXCEPTION_ADDR     0xffe0200c
+#define EVT_GLOBAL_INT_ENB_ADDR        0xffe02010
+#define EVT_HARDWARE_ERROR_ADDR        0xffe02014
+#define EVT_TIMER_ADDR         0xffe02018
+#define EVT_IVG7_ADDR          0xffe0201c
+#define EVT_IVG8_ADDR          0xffe02020
+#define EVT_IVG9_ADDR          0xffe02024
+#define EVT_IVG10_ADDR         0xffe02028
+#define EVT_IVG11_ADDR         0xffe0202c
+#define EVT_IVG12_ADDR         0xffe02030
+#define EVT_IVG13_ADDR         0xffe02034
+#define EVT_IVG14_ADDR         0xffe02038
+#define EVT_IVG15_ADDR         0xffe0203c
+#define EVT_OVERRIDE_ADDR      0xffe02100
+
+/* IMASK Bit values */
+#define IVG15_POS              0x00008000
+#define IVG14_POS              0x00004000
+#define IVG13_POS              0x00002000
+#define IVG12_POS              0x00001000
+#define IVG11_POS              0x00000800
+#define IVG10_POS              0x00000400
+#define IVG9_POS               0x00000200
+#define IVG8_POS               0x00000100
+#define IVG7_POS               0x00000080
+#define IVGTMR_POS             0x00000040
+#define IVGHW_POS              0x00000020
+
+#define WDOG_TMR_DISABLE       (0xAD << 4)
+#define ICTL_RST               0x00000000
+#define ICTL_NMI               0x00000002
+#define ICTL_GP                        0x00000004
+#define ICTL_DISABLE           0x00000003
+
+/* Watch Dog timer values setup */
+#define WATCHDOG_DISABLE       WDOG_TMR_DISABLE | ICTL_DISABLE
+
+#endif /* _DEF_BF533_EXTN_H */

diff --git a/include/asm-blackfin/cpu/def_LPBlackfin.h b/include/asm-blackfin/cpu/def_LPBlackfin.h
new file mode 100644 (file)
index 0000000..9ac78c8
--- /dev/null
+++ b/include/asm-blackfin/cpu/def_LPBlackfin.h
@@ -0,0 +1,445 @@
+/*
+ * def_LPBlackfin.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
+
+#ifndef _DEF_LPBLACKFIN_H
+#define _DEF_LPBLACKFIN_H
+
+/*
+ * #if !defined(__ADSPLPBLACKFIN__)
+ * #warning def_LPBlackfin.h should only be included for 532 compatible chips.
+ * #endif
+ */
+
+#define MK_BMSK_( x ) (1<<x)   /* Make a bit mask from a bit position */
+
+/*
+ * System Register Bits
+ */
+
+/*
+ * ASTAT register
+ */
+
+/* definitions of ASTAT bit positions */
+#define ASTAT_AZ_P             0x00000000      /* Result of last ALU0 or shifter operation is zero */
+#define ASTAT_AN_P             0x00000001      /* Result of last ALU0 or shifter operation is negative */
+#define ASTAT_CC_P             0x00000005      /* Condition Code, used for holding comparison results */
+#define ASTAT_AQ_P             0x00000006      /* Quotient Bit */
+#define ASTAT_RND_MOD_P                0x00000008      /* Rounding mode, set for biased, clear for unbiased */
+#define ASTAT_AC0_P            0x0000000C      /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC0_COPY_P       0x00000002      /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC1_P            0x0000000D      /* Result of last ALU1 operation generated a carry */
+#define ASTAT_AV0_P            0x00000010      /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
+#define ASTAT_AV0S_P           0x00000011      /* Sticky version of ASTAT_AV0  */
+#define ASTAT_AV1_P            0x00000012      /* Result of last MAC1 operation overflowed, sticky for MAC */
+#define ASTAT_AV1S_P           0x00000013      /* Sticky version of ASTAT_AV1  */
+#define ASTAT_V_P              0x00000018      /* Result of last ALU0 or MAC0 operation overflowed */
+#define ASTAT_V_COPY_P         0x00000003      /* Result of last ALU0 or MAC0 operation overflowed */
+#define ASTAT_VS_P             0x00000019      /* Sticky version of ASTAT_V */
+
+/* ** Masks */
+#define ASTAT_AZ               MK_BMSK_(ASTAT_AZ_P)    /* Result of last ALU0 or shifter operation is zero */
+#define ASTAT_AN               MK_BMSK_(ASTAT_AN_P)    /* Result of last ALU0 or shifter operation is negative */
+#define ASTAT_AC0              MK_BMSK_(ASTAT_AC0_P)   /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC0_COPY         MK_BMSK_(ASTAT_AC0_COPY_P)      /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC1              MK_BMSK_(ASTAT_AC1_P)   /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AV0              MK_BMSK_(ASTAT_AV0_P)   /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
+#define ASTAT_AV1              MK_BMSK_(ASTAT_AV1_P)   /* Result of last MAC1 operation overflowed, sticky for MAC */
+#define ASTAT_CC               MK_BMSK_(ASTAT_CC_P)    /* Condition Code, used for holding comparison results */
+#define ASTAT_AQ               MK_BMSK_(ASTAT_AQ_P)    /* Quotient Bit */
+#define ASTAT_RND_MOD          MK_BMSK_(ASTAT_RND_MOD_P)       /* Rounding mode, set for biased, clear for unbiased */
+#define ASTAT_V                        MK_BMSK_(ASTAT_V_P)     /* Overflow Bit */
+#define ASTAT_V_COPY           MK_BMSK_(ASTAT_V_COPY_P)        /* Overflow Bit */
+
+/*
+ * SEQSTAT register
+ */
+
+/* ** Bit Positions */
+#define SEQSTAT_EXCAUSE0_P     0x00000000      /* Last exception cause bit 0 */
+#define SEQSTAT_EXCAUSE1_P     0x00000001      /* Last exception cause bit 1 */
+#define SEQSTAT_EXCAUSE2_P     0x00000002      /* Last exception cause bit 2 */
+#define SEQSTAT_EXCAUSE3_P     0x00000003      /* Last exception cause bit 3 */
+#define SEQSTAT_EXCAUSE4_P     0x00000004      /* Last exception cause bit 4 */
+#define SEQSTAT_EXCAUSE5_P     0x00000005      /* Last exception cause bit 5 */
+#define SEQSTAT_IDLE_REQ_P     0x0000000C      /* Pending idle mode request, set by IDLE instruction */
+#define SEQSTAT_SFTRESET_P     0x0000000D      /* Indicates whether the last reset was a software reset (=1) */
+#define SEQSTAT_HWERRCAUSE0_P  0x0000000E      /* Last hw error cause bit 0 */
+#define SEQSTAT_HWERRCAUSE1_P  0x0000000F      /* Last hw error cause bit 1 */
+#define SEQSTAT_HWERRCAUSE2_P  0x00000010      /* Last hw error cause bit 2 */
+#define SEQSTAT_HWERRCAUSE3_P  0x00000011      /* Last hw error cause bit 3 */
+#define SEQSTAT_HWERRCAUSE4_P  0x00000012      /* Last hw error cause bit 4 */
+#define SEQSTAT_HWERRCAUSE5_P  0x00000013      /* Last hw error cause bit 5 */
+#define SEQSTAT_HWERRCAUSE6_P  0x00000014      /* Last hw error cause bit 6 */
+#define SEQSTAT_HWERRCAUSE7_P  0x00000015      /* Last hw error cause bit 7 */
+
+/* ** Masks */
+/* Exception cause */
+#define SEQSTAT_EXCAUSE                MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
+                               MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
+                               MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
+                               MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
+                               MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
+                               MK_BMSK_(SEQSTAT_EXCAUSE5_P ) | \
+                               0
+
+/* Indicates whether the last reset was a software reset (=1) */
+#define SEQSTAT_SFTRESET       MK_BMSK_(SEQSTAT_SFTRESET_P )
+
+/* Last hw error cause */
+#define SEQSTAT_HWERRCAUSE     MK_BMSK_(SEQSTAT_HWERRCAUSE0_P ) | \
+                               MK_BMSK_(SEQSTAT_HWERRCAUSE1_P ) | \
+                               MK_BMSK_(SEQSTAT_HWERRCAUSE2_P ) | \
+                               MK_BMSK_(SEQSTAT_HWERRCAUSE3_P ) | \
+                               MK_BMSK_(SEQSTAT_HWERRCAUSE4_P ) | \
+                               0
+
+/*
+ * SYSCFG register
+ */
+
+/* ** Bit Positions */
+#define SYSCFG_SSSTEP_P                0x00000000      /* Supervisor single step, when set it forces an exception for each instruction executed */
+#define SYSCFG_CCEN_P          0x00000001      /* Enable cycle counter (=1) */
+#define SYSCFG_SNEN_P          0x00000002      /* Self nesting Interrupt Enable */
+
+/* ** Masks */
+#define SYSCFG_SSSTEP          MK_BMSK_(SYSCFG_SSSTEP_P)       /* Supervisor single step, when set it forces an exception for each instruction executed */
+#define SYSCFG_CCEN            MK_BMSK_(SYSCFG_CCEN_P)         /* Enable cycle counter (=1) */
+#define SYSCFG_SNEN            MK_BMSK_(SYSCFG_SNEN_P          /* Self Nesting Interrupt Enable */
+
+/* Backward-compatibility for typos in prior releases */
+#define SYSCFG_SSSSTEP         SYSCFG_SSSTEP
+#define SYSCFG_CCCEN           SYSCFG_CCEN
+
+/*
+ * Core MMR Register Map
+ */
+
+/* Data Cache & SRAM Memory  (0xFFE00000 - 0xFFE00404) */
+#define SRAM_BASE_ADDRESS      0xFFE00000      /* SRAM Base Address Register */
+#define DMEM_CONTROL           0xFFE00004      /* Data memory control */
+#define DCPLB_STATUS           0xFFE00008      /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_STATUS     0xFFE00008      /* "" (older define) */
+#define DCPLB_FAULT_ADDR       0xFFE0000C      /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0            0xFFE00100      /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1            0xFFE00104      /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2            0xFFE00108      /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3            0xFFE0010C      /* Data Cacheability Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4            0xFFE00110      /* Data Cacheability Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5            0xFFE00114      /* Data Cacheability Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6            0xFFE00118      /* Data Cacheability Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7            0xFFE0011C      /* Data Cacheability Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8            0xFFE00120      /* Data Cacheability Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9            0xFFE00124      /* Data Cacheability Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10           0xFFE00128      /* Data Cacheability Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11           0xFFE0012C      /* Data Cacheability Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12           0xFFE00130      /* Data Cacheability Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13           0xFFE00134      /* Data Cacheability Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14           0xFFE00138      /* Data Cacheability Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15           0xFFE0013C      /* Data Cacheability Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0            0xFFE00200      /* Data Cache 0 Status */
+#define DCPLB_DATA1            0xFFE00204      /* Data Cache 1 Status */
+#define DCPLB_DATA2            0xFFE00208      /* Data Cache 2 Status */
+#define DCPLB_DATA3            0xFFE0020C      /* Data Cache 3 Status */
+#define DCPLB_DATA4            0xFFE00210      /* Data Cache 4 Status */
+#define DCPLB_DATA5            0xFFE00214      /* Data Cache 5 Status */
+#define DCPLB_DATA6            0xFFE00218      /* Data Cache 6 Status */
+#define DCPLB_DATA7            0xFFE0021C      /* Data Cache 7 Status */
+#define DCPLB_DATA8            0xFFE00220      /* Data Cache 8 Status */
+#define DCPLB_DATA9            0xFFE00224      /* Data Cache 9 Status */
+#define DCPLB_DATA10           0xFFE00228      /* Data Cache 10 Status */
+#define DCPLB_DATA11           0xFFE0022C      /* Data Cache 11 Status */
+#define DCPLB_DATA12           0xFFE00230      /* Data Cache 12 Status */
+#define DCPLB_DATA13           0xFFE00234      /* Data Cache 13 Status */
+#define DCPLB_DATA14           0xFFE00238      /* Data Cache 14 Status */
+#define DCPLB_DATA15           0xFFE0023C      /* Data Cache 15 Status */
+#define DTEST_COMMAND          0xFFE00300      /* Data Test Command Register */
+#define DTEST_DATA0            0xFFE00400      /* Data Test Data Register */
+#define DTEST_DATA1            0xFFE00404      /* Data Test Data Register */
+
+/* Instruction Cache & SRAM Memory  (0xFFE01004 - 0xFFE01404) */
+#define IMEM_CONTROL           0xFFE01004      /* Instruction Memory Control */
+#define ICPLB_STATUS           0xFFE01008      /* Instruction Cache miss status */
+#define CODE_FAULT_STATUS      0xFFE01008      /* "" (older define) */
+#define ICPLB_FAULT_ADDR       0xFFE0100C      /* Instruction Cache miss address */
+#define CODE_FAULT_ADDR                0xFFE0100C      /* "" (older define) */
+#define ICPLB_ADDR0            0xFFE01100      /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1            0xFFE01104      /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2            0xFFE01108      /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3            0xFFE0110C      /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4            0xFFE01110      /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5            0xFFE01114      /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6            0xFFE01118      /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7            0xFFE0111C      /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8            0xFFE01120      /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9            0xFFE01124      /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10           0xFFE01128      /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11           0xFFE0112C      /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12           0xFFE01130      /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13           0xFFE01134      /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14           0xFFE01138      /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15           0xFFE0113C      /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0            0xFFE01200      /* Instruction Cache 0 Status */
+#define ICPLB_DATA1            0xFFE01204      /* Instruction Cache 1 Status */
+#define ICPLB_DATA2            0xFFE01208      /* Instruction Cache 2 Status */
+#define ICPLB_DATA3            0xFFE0120C      /* Instruction Cache 3 Status */
+#define ICPLB_DATA4            0xFFE01210      /* Instruction Cache 4 Status */
+#define ICPLB_DATA5            0xFFE01214      /* Instruction Cache 5 Status */
+#define ICPLB_DATA6            0xFFE01218      /* Instruction Cache 6 Status */
+#define ICPLB_DATA7            0xFFE0121C      /* Instruction Cache 7 Status */
+#define ICPLB_DATA8            0xFFE01220      /* Instruction Cache 8 Status */
+#define ICPLB_DATA9            0xFFE01224      /* Instruction Cache 9 Status */
+#define ICPLB_DATA10           0xFFE01228      /* Instruction Cache 10 Status */
+#define ICPLB_DATA11           0xFFE0122C      /* Instruction Cache 11 Status */
+#define ICPLB_DATA12           0xFFE01230      /* Instruction Cache 12 Status */
+#define ICPLB_DATA13           0xFFE01234      /* Instruction Cache 13 Status */
+#define ICPLB_DATA14           0xFFE01238      /* Instruction Cache 14 Status */
+#define ICPLB_DATA15           0xFFE0123C      /* Instruction Cache 15 Status */
+#define ITEST_COMMAND          0xFFE01300      /* Instruction Test Command Register */
+#define ITEST_DATA0            0xFFE01400      /* Instruction Test Data Register */
+#define ITEST_DATA1            0xFFE01404      /* Instruction Test Data Register */
+
+/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
+#define EVT0                   0xFFE02000      /* Event Vector 0 ESR Address */
+#define EVT1                   0xFFE02004      /* Event Vector 1 ESR Address */
+#define EVT2                   0xFFE02008      /* Event Vector 2 ESR Address */
+#define EVT3                   0xFFE0200C      /* Event Vector 3 ESR Address */
+#define EVT4                   0xFFE02010      /* Event Vector 4 ESR Address */
+#define EVT5                   0xFFE02014      /* Event Vector 5 ESR Address */
+#define EVT6                   0xFFE02018      /* Event Vector 6 ESR Address */
+#define EVT7                   0xFFE0201C      /* Event Vector 7 ESR Address */
+#define EVT8                   0xFFE02020      /* Event Vector 8 ESR Address */
+#define EVT9                   0xFFE02024      /* Event Vector 9 ESR Address */
+#define EVT10                  0xFFE02028      /* Event Vector 10 ESR Address */
+#define EVT11                  0xFFE0202C      /* Event Vector 11 ESR Address */
+#define EVT12                  0xFFE02030      /* Event Vector 12 ESR Address */
+#define EVT13                  0xFFE02034      /* Event Vector 13 ESR Address */
+#define EVT14                  0xFFE02038      /* Event Vector 14 ESR Address */
+#define EVT15                  0xFFE0203C      /* Event Vector 15 ESR Address */
+#define IMASK                  0xFFE02104      /* Interrupt Mask Register */
+#define IPEND                  0xFFE02108      /* Interrupt Pending Register */
+#define ILAT                   0xFFE0210C      /* Interrupt Latch Register */
+#define IPRIO                  0xFFE02110      /* Core Interrupt Priority Register */
+
+/* Core Timer Registers     (0xFFE03000 - 0xFFE0300C) */
+#define TCNTL                  0xFFE03000      /* Core Timer Control Register */
+#define TPERIOD                        0xFFE03004      /* Core Timer Period Register */
+#define TSCALE                 0xFFE03008      /* Core Timer Scale Register */
+#define TCOUNT                 0xFFE0300C      /* Core Timer Count Register */
+
+/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
+#define DSPID                  0xFFE05000      /* DSP Processor ID Register for MP implementations */
+#define DBGSTAT                        0xFFE05008      /* Debug Status Register */
+
+/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
+#define TBUFCTL                        0xFFE06000      /* Trace Buffer Control Register */
+#define TBUFSTAT               0xFFE06004      /* Trace Buffer Status Register */
+#define TBUF                   0xFFE06100      /* Trace Buffer */
+
+/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
+#define WPIACTL                        0xFFE07000      /* Watchpoint Instruction Address Control Register */
+#define WPIA0                  0xFFE07040      /* Watchpoint Instruction Address Register 0 */
+#define WPIA1                  0xFFE07044      /* Watchpoint Instruction Address Register 1 */
+#define WPIA2                  0xFFE07048      /* Watchpoint Instruction Address Register 2 */
+#define WPIA3                  0xFFE0704C      /* Watchpoint Instruction Address Register 3 */
+#define WPIA4                  0xFFE07050      /* Watchpoint Instruction Address Register 4 */
+#define WPIA5                  0xFFE07054      /* Watchpoint Instruction Address Register 5 */
+#define WPIACNT0               0xFFE07080      /* Watchpoint Instruction Address Count Register 0 */
+#define WPIACNT1               0xFFE07084      /* Watchpoint Instruction Address Count Register 1 */
+#define WPIACNT2               0xFFE07088      /* Watchpoint Instruction Address Count Register 2 */
+#define WPIACNT3               0xFFE0708C      /* Watchpoint Instruction Address Count Register 3 */
+#define WPIACNT4               0xFFE07090      /* Watchpoint Instruction Address Count Register 4 */
+#define WPIACNT5               0xFFE07094      /* Watchpoint Instruction Address Count Register 5 */
+#define WPDACTL                        0xFFE07100      /* Watchpoint Data Address Control Register */
+#define WPDA0                  0xFFE07140      /* Watchpoint Data Address Register 0 */
+#define WPDA1                  0xFFE07144      /* Watchpoint Data Address Register 1 */
+#define WPDACNT0               0xFFE07180      /* Watchpoint Data Address Count Value Register 0 */
+#define WPDACNT1               0xFFE07184      /* Watchpoint Data Address Count Value Register 1 */
+#define WPSTAT                 0xFFE07200      /* Watchpoint Status Register */
+
+/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
+#define PFCTL                  0xFFE08000      /* Performance Monitor Control Register */
+#define PFCNTR0                        0xFFE08100      /* Performance Monitor Counter Register 0 */
+#define PFCNTR1                        0xFFE08104      /* Performance Monitor Counter Register 1 */
+
+/*
+ * Core MMR Register Bits
+ */
+
+/*
+ * EVT registers (ILAT, IMASK, and IPEND).
+ */
+
+/* ** Bit Positions */
+#define EVT_EMU_P              0x00000000      /* Emulator interrupt bit position */
+#define EVT_RST_P              0x00000001      /* Reset interrupt bit position */
+#define EVT_NMI_P              0x00000002      /* Non Maskable interrupt bit position */
+#define EVT_EVX_P              0x00000003      /* Exception bit position */
+#define EVT_IRPTEN_P           0x00000004      /* Global interrupt enable bit position */
+#define EVT_IVHW_P             0x00000005      /* Hardware Error interrupt bit position */
+#define EVT_IVTMR_P            0x00000006      /* Timer interrupt bit position */
+#define EVT_IVG7_P             0x00000007      /* IVG7 interrupt bit position */
+#define EVT_IVG8_P             0x00000008      /* IVG8 interrupt bit position */
+#define EVT_IVG9_P             0x00000009      /* IVG9 interrupt bit position */
+#define EVT_IVG10_P            0x0000000a      /* IVG10 interrupt bit position */
+#define EVT_IVG11_P            0x0000000b      /* IVG11 interrupt bit position */
+#define EVT_IVG12_P            0x0000000c      /* IVG12 interrupt bit position */
+#define EVT_IVG13_P            0x0000000d      /* IVG13 interrupt bit position */
+#define EVT_IVG14_P            0x0000000e      /* IVG14 interrupt bit position */
+#define EVT_IVG15_P            0x0000000f      /* IVG15 interrupt bit position */
+
+/* ** Masks */
+#define EVT_EMU                        MK_BMSK_(EVT_EMU_P   )  /* Emulator interrupt mask */
+#define EVT_RST                        MK_BMSK_(EVT_RST_P   )  /* Reset interrupt mask */
+#define EVT_NMI                        MK_BMSK_(EVT_NMI_P   )  /* Non Maskable interrupt mask */
+#define EVT_EVX                        MK_BMSK_(EVT_EVX_P   )  /* Exception mask */
+#define EVT_IRPTEN             MK_BMSK_(EVT_IRPTEN_P)  /* Global interrupt enable mask */
+#define EVT_IVHW               MK_BMSK_(EVT_IVHW_P  )  /* Hardware Error interrupt mask */
+#define EVT_IVTMR              MK_BMSK_(EVT_IVTMR_P )  /* Timer interrupt mask */
+#define EVT_IVG7               MK_BMSK_(EVT_IVG7_P  )  /* IVG7 interrupt mask */
+#define EVT_IVG8               MK_BMSK_(EVT_IVG8_P  )  /* IVG8 interrupt mask */
+#define EVT_IVG9               MK_BMSK_(EVT_IVG9_P  )  /* IVG9 interrupt mask */
+#define EVT_IVG10              MK_BMSK_(EVT_IVG10_P )  /* IVG10 interrupt mask */
+#define EVT_IVG11              MK_BMSK_(EVT_IVG11_P )  /* IVG11 interrupt mask */
+#define EVT_IVG12              MK_BMSK_(EVT_IVG12_P )  /* IVG12 interrupt mask */
+#define EVT_IVG13              MK_BMSK_(EVT_IVG13_P )  /* IVG13 interrupt mask */
+#define EVT_IVG14              MK_BMSK_(EVT_IVG14_P )  /* IVG14 interrupt mask */
+#define EVT_IVG15              MK_BMSK_(EVT_IVG15_P )  /* IVG15 interrupt mask */
+
+/*
+ * DMEM_CONTROL Register
+ */
+
+/* ** Bit Positions */
+#define ENDM_P                 0x00    /* (doesn't really exist) Enable Data Memory L1 */
+#define DMCTL_ENDM_P           0x00    /* "" (older define) */
+#define DMC0_P                 0x01    /* Data Memory Configuration, 00 - A SRAM, B SRAM */
+#define DMCTL_DMC0_P           0x01    /* "" (older define) */
+#define DMC1_P                 0x02    /* Data Memory Configuration, 10 - A SRAM, B SRAM */
+#define DMCTL_DMC1_P           0x02    /* "" (older define) */
+#define DMC2_P                 0x03    /* Data Memory Configuration, 11 - A CACHE, B CACHE */
+#define DMCTL_DMC2_P           0x03    /* "" (older define) */
+#define DCBS_P                 0x04    /* L1 Data Cache Bank Select */
+#define PORT_PREF0_P           0x12    /* DAG0 Port Preference */
+#define PORT_PREF1_P           0x13    /* DAG1 Port Preference */
+
+/* ** Masks */
+#define ENDM                   0x00000001      /* (doesn't really exist) Enable Data Memory L1 */
+#define ENDCPLB                        0x00000002      /* Enable DCPLB */
+#define ASRAM_BSRAM            0x00000000
+#define ACACHE_BSRAM           0x00000008
+#define ACACHE_BCACHE          0x0000000C
+#define DCBS                   0x00000010      /*  L1 Data Cache Bank Select */
+#define PORT_PREF0             0x00001000      /* DAG0 Port Preference */
+#define PORT_PREF1             0x00002000      /* DAG1 Port Preference */
+
+/* IMEM_CONTROL Register */
+/* ** Bit Positions */
+#define ENIM_P                 0x00    /* Enable L1 Code Memory */
+#define IMCTL_ENIM_P           0x00    /* "" (older define) */
+#define ENICPLB_P              0x01    /* Enable ICPLB */
+#define IMCTL_ENICPLB_P                0x01    /* "" (older define) */
+#define IMC_P                  0x02    /* Enable */
+#define IMCTL_IMC_P            0x02    /* Configure L1 code memory as cache (0=SRAM) */
+#define ILOC0_P                        0x03    /* Lock Way 0 */
+#define ILOC1_P                        0x04    /* Lock Way 1 */
+#define ILOC2_P                        0x05    /* Lock Way 2 */
+#define ILOC3_P                        0x06    /* Lock Way 3 */
+#define LRUPRIORST_P           0x0D    /* Least Recently Used Replacement Priority */
+
+/* ** Masks */
+#define ENIM                   0x00000001      /* Enable L1 Code Memory */
+#define ENICPLB                        0x00000002      /* Enable ICPLB */
+#define IMC                    0x00000004      /* Configure L1 code memory as cache (0=SRAM) */
+#define ILOC0                  0x00000008      /* Lock Way 0 */
+#define ILOC1                  0x00000010      /* Lock Way 1 */
+#define ILOC2                  0x00000020      /* Lock Way 2 */
+#define ILOC3                  0x00000040      /* Lock Way 3 */
+#define LRUPRIORST             0x00002000      /* Least Recently Used Replacement Priority */
+
+/* TCNTL Masks */
+#define TMPWR                  0x00000001      /* Timer Low Power Control, 0=low power mode, 1=active state */
+#define TMREN                  0x00000002      /* Timer enable, 0=disable, 1=enable */
+#define TAUTORLD               0x00000004      /* Timer auto reload */
+#define TINT                   0x00000008      /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
+
+/* TCNTL Bit Positions */
+#define TMPWR_P                        0x00000000      /* Timer Low Power Control, 0=low power mode, 1=active state */
+#define TMREN_P                        0x00000001      /* Timer enable, 0=disable, 1=enable */
+#define TAUTORLD_P             0x00000002      /* Timer auto reload */
+#define TINT_P                 0x00000003      /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
+
+/* DCPLB_DATA and ICPLB_DATA Registers */
+/* ** Bit Positions */
+#define CPLB_VALID_P           0x00000000      /* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK_P            0x00000001      /* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD_P         0x00000002      /* 0=no read access, 1=read access allowed (user mode) */
+
+/* ** Masks */
+#define CPLB_VALID             0x00000001      /* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK              0x00000002      /* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD           0x00000004      /* 0=no read access, 1=read access allowed (user mode) */
+#define PAGE_SIZE_1KB          0x00000000      /* 1 KB page size */
+#define PAGE_SIZE_4KB          0x00010000      /* 4 KB page size */
+#define PAGE_SIZE_1MB          0x00020000      /* 1 MB page size */
+#define PAGE_SIZE_4MB          0x00030000      /* 4 MB page size */
+#define CPLB_L1SRAM            0x00000020      /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
+#define CPLB_PORTPRIO          0x00000200      /* 0=low priority port, 1= high priority port */
+#define CPLB_L1_CHBL           0x00001000      /* 0=non-cacheable in L1, 1=cacheable in L1 */
+
+/* ICPLB_DATA only */
+#define CPLB_LRUPRIO           0x00000100      /* 0=can be replaced by any line, 1=priority for non-replacement */
+
+/* DCPLB_DATA only */
+#define CPLB_USER_WR           0x00000008      /* 0=no write access, 0=write access allowed (user mode) */
+#define CPLB_SUPV_WR           0x00000010      /* 0=no write access, 0=write access allowed (supervisor mode) */
+#define CPLB_DIRTY             0x00000080      /* 1=dirty, 0=clean */
+#define CPLB_L1_AOW            0x00008000      /* 0=do not allocate cache lines on write-through writes */
+                                               /* 1= allocate cache lines on write-through writes. */
+#define CPLB_WT                        0x00004000      /* 0=write-back, 1=write-through */
+
+/* ITEST_COMMAND and DTEST_COMMAND Registers */
+/* ** Masks */
+#define TEST_READ              0x00000000      /* Read Access */
+#define TEST_WRITE             0x00000002      /* Write Access */
+#define TEST_TAG               0x00000000      /* Access TAG */
+#define TEST_DATA              0x00000004      /* Access DATA */
+#define TEST_DW0               0x00000000      /* Select Double Word 0 */
+#define TEST_DW1               0x00000008      /* Select Double Word 1 */
+#define TEST_DW2               0x00000010      /* Select Double Word 2 */
+#define TEST_DW3               0x00000018      /* Select Double Word 3 */
+#define TEST_MB0               0x00000000      /* Select Mini-Bank 0 */
+#define TEST_MB1               0x00010000      /* Select Mini-Bank 1 */
+#define TEST_MB2               0x00020000      /* Select Mini-Bank 2 */
+#define TEST_MB3               0x00030000      /* Select Mini-Bank 3 */
+#define TEST_SET(x)            ((x << 5) & 0x03E0)     /* Set Index 0->31 */
+#define TEST_WAY0              0x00000000      /* Access Way0 */
+#define TEST_WAY1              0x04000000      /* Access Way1 */
+
+/* ** ITEST_COMMAND only */
+#define TEST_WAY2              0x08000000      /* Access Way2 */
+#define TEST_WAY3              0x0C000000      /* Access Way3 */
+
+/* ** DTEST_COMMAND only */
+#define TEST_BNKSELA           0x00000000      /* Access SuperBank A */
+#define TEST_BNKSELB           0x00800000      /* Access SuperBank B */
+
+#endif /* _DEF_LPBLACKFIN_H */

diff --git a/include/asm-blackfin/current.h b/include/asm-blackfin/current.h
new file mode 100644 (file)
index 0000000..108c279
--- /dev/null
+++ b/include/asm-blackfin/current.h
@@ -0,0 +1,40 @@
+/*
+ * U-boot - current.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_CURRENT_H
+#define _BLACKFIN_CURRENT_H
+/*
+ *     current.h
+ *     (C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com>
+ *
+ *     rather than dedicate a register (as the m68k source does), we
+ *     just keep a global,  we should probably just change it all to be
+ *     current and lose _current_task.
+ */
+
+extern struct task_struct *_current_task;
+#define get_current()  _current_task
+#define current        _current_task
+
+#endif

diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
new file mode 100644 (file)
index 0000000..dbb7388
--- /dev/null
+++ b/include/asm-blackfin/delay.h
@@ -0,0 +1,55 @@
+/*
+ * U-boot - delay.h Routines for introducing delays
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_DELAY_H
+#define _BLACKFIN_DELAY_H
+
+/*
+ * Changes made by akbar.hussain@Lineo.com, for BLACKFIN
+ * Copyright (C) 1994 Hamish Macdonald
+ *
+ * Delay routines, using a pre-computed "loops_per_second" value.
+ */
+
+extern __inline__ void __delay(unsigned long loops)
+{
+       __asm__ __volatile__("1:\t%0 += -1;\n\t"
+                               "cc = %0 == 0;\n\t"
+                               "if ! cc jump 1b;\n":"=d"(loops)
+                               :"0"(loops));
+}
+
+/*
+ * Use only for very small delays ( < 1 msec).  Should probably use a
+ * lookup table, really, as the multiplications take much too long with
+ * short delays.  This is a "reasonable" implementation, though (and the
+ * first constant multiplications gets optimized away if the delay is
+ * a constant)
+ */
+extern __inline__ void udelay(unsigned long usecs)
+{
+       __delay(usecs);
+}
+
+#endif

diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h
new file mode 100644 (file)
index 0000000..607a5b8
--- /dev/null
+++ b/include/asm-blackfin/entry.h
@@ -0,0 +1,385 @@
+/*
+ * U-boot - entry.h Routines for context saving and restoring
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_ENTRY_H
+#define __BLACKFIN_ENTRY_H
+
+#include <linux/config.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+
+/*
+ * Stack layout in 'ret_from_exception':
+ *
+ */
+
+/*
+ * Register %p2 is now set to the current task throughout
+ * the whole kernel.
+ */
+
+#ifdef __ASSEMBLY__
+
+#define        LFLUSH_I_AND_D  0x00000808
+#define        LSIGTRAP        5
+
+/* process bits for task_struct.flags */
+#define        PF_TRACESYS_OFF 3
+#define        PF_TRACESYS_BIT 5
+#define        PF_PTRACED_OFF  3
+#define        PF_PTRACED_BIT  4
+#define        PF_DTRACE_OFF   1
+#define        PF_DTRACE_BIT   5
+
+#define NEW_PT_REGS
+
+#if defined(NEW_PT_REGS)
+
+#define SAVE_ALL_INT           save_context_no_interrupts
+#define SAVE_ALL_SYS           save_context_no_interrupts
+#define SAVE_CONTEXT           save_context_with_interrupts
+
+#define RESTORE_ALL            restore_context_no_interrupts
+#define RESTORE_ALL_SYS                restore_context_no_interrupts
+#define RESTORE_CONTEXT                restore_context_with_interrupts
+
+#else
+
+#define SAVE_ALL_INT           save_all_int
+#define SAVE_ALL_SYS           save_all_sys
+#define SAVE_CONTEXT           save_context
+#define RESTORE_ALL            restore_context
+#define RESTORE_CONTEXT                restore_context
+
+#endif
+
+/*
+ * Code to save processor context.
+ * We even save the register which are preserved by a function call
+ * - r4, r5, r6, r7, p3, p4, p5
+ */
+.macro save_context_with_interrupts
+       [--sp] = R0;
+       [--sp] = ( R7:0, P5:0 );
+       [--sp] = fp;
+       [--sp] = usp;
+
+       [--sp] = i0;
+       [--sp] = i1;
+       [--sp] = i2;
+       [--sp] = i3;
+
+       [--sp] = m0;
+       [--sp] = m1;
+       [--sp] = m2;
+       [--sp] = m3;
+
+       [--sp] = l0;
+       [--sp] = l1;
+       [--sp] = l2;
+       [--sp] = l3;
+
+       [--sp] = b0;
+       [--sp] = b1;
+       [--sp] = b2;
+       [--sp] = b3;
+       [--sp] = a0.x;
+       [--sp] = a0.w;
+       [--sp] = a1.x;
+       [--sp] = a1.w;
+
+       [--sp] = LC0;
+       [--sp] = LC1;
+       [--sp] = LT0;
+       [--sp] = LT1;
+       [--sp] = LB0;
+       [--sp] = LB1;
+
+       [--sp] = ASTAT;
+
+       [--sp] = r0;    /* Skip reserved */
+       [--sp] = RETS;
+       [--sp] = RETI;
+       [--sp] = RETX;
+       [--sp] = RETN;
+       [--sp] = RETE;
+       [--sp] = SEQSTAT;
+       [--sp] = SYSCFG;
+       [--sp] = r0;    /* Skip IPEND as well. */
+.endm
+
+.macro save_context_no_interrupts
+       [--sp] = R0;
+       [--sp] = ( R7:0, P5:0 );
+       [--sp] = fp;
+       [--sp] = usp;
+
+       [--sp] = i0;
+       [--sp] = i1;
+       [--sp] = i2;
+       [--sp] = i3;
+
+       [--sp] = m0;
+       [--sp] = m1;
+       [--sp] = m2;
+       [--sp] = m3;
+
+       [--sp] = l0;
+       [--sp] = l1;
+       [--sp] = l2;
+       [--sp] = l3;
+
+       [--sp] = b0;
+       [--sp] = b1;
+       [--sp] = b2;
+       [--sp] = b3;
+       [--sp] = a0.x;
+       [--sp] = a0.w;
+       [--sp] = a1.x;
+       [--sp] = a1.w;
+
+       [--sp] = LC0;
+       [--sp] = LC1;
+       [--sp] = LT0;
+       [--sp] = LT1;
+       [--sp] = LB0;
+       [--sp] = LB1;
+
+       [--sp] = ASTAT;
+
+       [--sp] = r0;    /* Skip reserved */
+       [--sp] = RETS;
+       r0 = RETI;
+       [--sp] = r0;
+       [--sp] = RETX;
+       [--sp] = RETN;
+       [--sp] = RETE;
+       [--sp] = SEQSTAT;
+       [--sp] = SYSCFG;
+       [--sp] = r0;    /* Skip IPEND as well. */
+.endm
+
+.macro restore_context_no_interrupts
+       sp += 4;
+       SYSCFG = [sp++];
+       SEQSTAT = [sp++];
+       RETE = [sp++];
+       RETN = [sp++];
+       RETX = [sp++];
+       r0 = [sp++];
+       RETI = r0;
+       RETS = [sp++];
+
+       sp += 4;
+
+       ASTAT = [sp++];
+
+       LB1 = [sp++];
+       LB0 = [sp++];
+       LT1 = [sp++];
+       LT0 = [sp++];
+       LC1 = [sp++];
+       LC0 = [sp++];
+
+       a1.w = [sp++];
+       a1.x = [sp++];
+       a0.w = [sp++];
+       a0.x = [sp++];
+       b3 = [sp++];
+       b2 = [sp++];
+       b1 = [sp++];
+       b0 = [sp++];
+
+       l3 = [sp++];
+       l2 = [sp++];
+       l1 = [sp++];
+       l0 = [sp++];
+
+       m3 = [sp++];
+       m2 = [sp++];
+       m1 = [sp++];
+       m0 = [sp++];
+
+       i3 = [sp++];
+       i2 = [sp++];
+       i1 = [sp++];
+       i0 = [sp++];
+
+       sp += 4;
+       fp = [sp++];
+
+       ( R7 : 0, P5 : 0) = [ SP ++ ];
+       sp += 4;
+.endm
+
+.macro restore_context_with_interrupts
+       sp += 4;
+       SYSCFG = [sp++];
+       SEQSTAT = [sp++];
+       RETE = [sp++];
+       RETN = [sp++];
+       RETX = [sp++];
+       RETI = [sp++];
+       RETS = [sp++];
+
+       sp += 4;
+
+       ASTAT = [sp++];
+
+       LB1 = [sp++];
+       LB0 = [sp++];
+       LT1 = [sp++];
+       LT0 = [sp++];
+       LC1 = [sp++];
+       LC0 = [sp++];
+
+       a1.w = [sp++];
+       a1.x = [sp++];
+       a0.w = [sp++];
+       a0.x = [sp++];
+       b3 = [sp++];
+       b2 = [sp++];
+       b1 = [sp++];
+       b0 = [sp++];
+
+       l3 = [sp++];
+       l2 = [sp++];
+       l1 = [sp++];
+       l0 = [sp++];
+
+       m3 = [sp++];
+       m2 = [sp++];
+       m1 = [sp++];
+       m0 = [sp++];
+
+       i3 = [sp++];
+       i2 = [sp++];
+       i1 = [sp++];
+       i0 = [sp++];
+
+       sp += 4;
+       fp = [sp++];
+
+       ( R7 : 0, P5 : 0) = [ SP ++ ];
+       sp += 4;
+.endm
+
+#if !defined(NEW_PT_REGS)
+/*
+ * a -1 in the orig_r0 field signifies
+ * that the stack frame is NOT for syscall
+ */
+.macro save_all_int
+/* reserved and disable the single step of SYSCFG, by Steven Chen 03/07/10 */
+       [--sp] = r0;
+       r0.l = 0x30;            /* Errata for BF533 */
+       r0.h = 0x0;
+       syscfg = r0;            /* disable single step flag in SYSCFG */
+       r0 = [sp++];
+       [--sp] = syscfg;        /* store SYSCFG */
+
+       [--sp] = r0;    /* Reserved for IPEND */
+       [--sp] = fp;
+       [--sp] = usp;
+       [--sp] = r0;
+
+       [--sp] = r0;
+       r0 = [sp + 8];
+       [--sp] = a0.x;
+       [--sp] = a1.x;
+       [--sp] = a0.w;
+       [--sp] = a1.w;
+       [--sp] = rets;
+       [--sp] = astat;
+       [--sp] = seqstat;
+       [--sp] = retx;  /* current pc when exception happens */
+       [--sp] = ( r7:5, p5:0 );
+       [--sp] = r1;
+       [--sp] = r2;
+       [--sp] = r4;
+       [--sp] = r3;
+.endm
+
+.macro save_all_sys
+       [--sp] = r0;
+       [--sp] = r0;
+       [--sp] = a0.x;
+       [--sp] = a1.x;
+       [--sp] = a0.w;
+       [--sp] = a1.w;
+       [--sp] = rets;
+       [--sp] = astat;
+       [--sp] = seqstat;
+       [--sp] = retx;  /* current pc when exception happens */
+       [--sp] = ( r7:5, p5:0 );
+       [--sp] = r1;
+       [--sp] = r2;
+       [--sp] = r4;
+       [--sp] = r3;
+.endm
+
+.macro restore_all
+       r3 = [sp++];
+       r4 = [sp++];
+       r2 = [sp++];
+       r1 = [sp++];
+       ( r7:5, p5:0 ) = [sp++];
+       retx = [sp++];
+       seqstat = [sp++];
+       astat = [sp++];
+       rets = [sp++];
+       a1.w = [sp++];
+       a0.w = [sp++];
+       a1.x = [sp++];
+       a0.x = [sp++];
+       sp += 4;        /* orig r0 */
+       r0 = [sp++];
+
+       sp += 4;
+       fp = [sp++];
+       sp +=4;         /* Skip the IPEND */
+
+       syscfg = [sp++];
+
+.endm
+
+#endif
+
+#define STR(X)                         STR1(X)
+#define STR1(X)                #X
+
+#if defined(NEW_PT_REGS)
+
+#define PT_OFF_ORIG_R0         208
+#define PT_OFF_SR              8
+
+#else
+
+#define PT_OFF_ORIG_R0         0x54
+#define PT_OFF_SR              0x38    /* seqstat in pt_regs */
+
+#endif
+#endif
+
+#endif

diff --git a/include/asm-blackfin/errno.h b/include/asm-blackfin/errno.h
new file mode 100644 (file)
index 0000000..713bba0
--- /dev/null
+++ b/include/asm-blackfin/errno.h
@@ -0,0 +1,156 @@
+/*
+ * U-boot - errno.h Error number defines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_ERRNO_H
+#define _BLACKFIN_ERRNO_H
+
+#define        EPERM           1       /* Operation not permitted */
+#define        ENOENT          2       /* No such file or directory */
+#define        ESRCH           3       /* No such process */
+#define        EINTR           4       /* Interrupted system call */
+#define        EIO             5       /* I/O error */
+#define        ENXIO           6       /* No such device or address */
+#define        E2BIG           7       /* Arg list too long */
+#define        ENOEXEC         8       /* Exec format error */
+#define        EBADF           9       /* Bad file number */
+#define        ECHILD          10      /* No child processes */
+#define        EAGAIN          11      /* Try again */
+#define        ENOMEM          12      /* Out of memory */
+#define        EACCES          13      /* Permission denied */
+#define        EFAULT          14      /* Bad address */
+#define        ENOTBLK         15      /* Block device required */
+#define        EBUSY           16      /* Device or resource busy */
+#define        EEXIST          17      /* File exists */
+#define        EXDEV           18      /* Cross-device link */
+#define        ENODEV          19      /* No such device */
+#define        ENOTDIR         20      /* Not a directory */
+#define        EISDIR          21      /* Is a directory */
+#define        EINVAL          22      /* Invalid argument */
+#define        ENFILE          23      /* File table overflow */
+#define        EMFILE          24      /* Too many open files */
+#define        ENOTTY          25      /* Not a typewriter */
+#define        ETXTBSY         26      /* Text file busy */
+#define        EFBIG           27      /* File too large */
+#define        ENOSPC          28      /* No space left on device */
+#define        ESPIPE          29      /* Illegal seek */
+#define        EROFS           30      /* Read-only file system */
+#define        EMLINK          31      /* Too many links */
+#define        EPIPE           32      /* Broken pipe */
+#define        EDOM            33      /* Math argument out of domain of func */
+#define        ERANGE          34      /* Math result not representable */
+#define        EDEADLK         35      /* Resource deadlock would occur */
+#define        ENAMETOOLONG    36      /* File name too long */
+#define        ENOLCK          37      /* No record locks available */
+#define        ENOSYS          38      /* Function not implemented */
+#define        ENOTEMPTY       39      /* Directory not empty */
+#define        ELOOP           40      /* Too many symbolic links encountered */
+#define        EWOULDBLOCK     EAGAIN  /* Operation would block */
+#define        ENOMSG          42      /* No message of desired type */
+#define        EIDRM           43      /* Identifier removed */
+#define        ECHRNG          44      /* Channel number out of range */
+#define        EL2NSYNC        45      /* Level 2 not synchronized */
+#define        EL3HLT          46      /* Level 3 halted */
+#define        EL3RST          47      /* Level 3 reset */
+#define        ELNRNG          48      /* Link number out of range */
+#define        EUNATCH         49      /* Protocol driver not attached */
+#define        ENOCSI          50      /* No CSI structure available */
+#define        EL2HLT          51      /* Level 2 halted */
+#define        EBADE           52      /* Invalid exchange */
+#define        EBADR           53      /* Invalid request descriptor */
+#define        EXFULL          54      /* Exchange full */
+#define        ENOANO          55      /* No anode */
+#define        EBADRQC         56      /* Invalid request code */
+#define        EBADSLT         57      /* Invalid slot */
+
+#define        EDEADLOCK       EDEADLK
+
+#define        EBFONT          59      /* Bad font file format */
+#define        ENOSTR          60      /* Device not a stream */
+#define        ENODATA         61      /* No data available */
+#define        ETIME           62      /* Timer expired */
+#define        ENOSR           63      /* Out of streams resources */
+#define        ENONET          64      /* Machine is not on the network */
+#define        ENOPKG          65      /* Package not installed */
+#define        EREMOTE         66      /* Object is remote */
+#define        ENOLINK         67      /* Link has been severed */
+#define        EADV            68      /* Advertise error */
+#define        ESRMNT          69      /* Srmount error */
+#define        ECOMM           70      /* Communication error on send */
+#define        EPROTO          71      /* Protocol error */
+#define        EMULTIHOP       72      /* Multihop attempted */
+#define        EDOTDOT         73      /* RFS specific error */
+#define        EBADMSG         74      /* Not a data message */
+#define        EOVERFLOW       75      /* Value too large for defined data type */
+#define        ENOTUNIQ        76      /* Name not unique on network */
+#define        EBADFD          77      /* File descriptor in bad state */
+#define        EREMCHG         78      /* Remote address changed */
+#define        ELIBACC         79      /* Can not access a needed shared library */
+#define        ELIBBAD         80      /* Accessing a corrupted shared library */
+#define        ELIBSCN         81      /* .lib section in a.out corrupted */
+#define        ELIBMAX         82      /* Attempting to link in too many shared libraries */
+#define        ELIBEXEC        83      /* Cannot exec a shared library directly */
+#define        EILSEQ          84      /* Illegal byte sequence */
+#define        ERESTART        85      /* Interrupted system call should be restarted */
+#define        ESTRPIPE        86      /* Streams pipe error */
+#define        EUSERS          87      /* Too many users */
+#define        ENOTSOCK        88      /* Socket operation on non-socket */
+#define        EDESTADDRREQ    89      /* Destination address required */
+#define        EMSGSIZE        90      /* Message too long */
+#define        EPROTOTYPE      91      /* Protocol wrong type for socket */
+#define        ENOPROTOOPT     92      /* Protocol not available */
+#define        EPROTONOSUPPORT 93      /* Protocol not supported */
+#define        ESOCKTNOSUPPORT 94      /* Socket type not supported */
+#define        EOPNOTSUPP      95      /* Operation not supported on transport endpoint */
+#define        EPFNOSUPPORT    96      /* Protocol family not supported */
+#define        EAFNOSUPPORT    97      /* Address family not supported by protocol */
+#define        EADDRINUSE      98      /* Address already in use */
+#define        EADDRNOTAVAIL   99      /* Cannot assign requested address */
+#define        ENETDOWN        100     /* Network is down */
+#define        ENETUNREACH     101     /* Network is unreachable */
+#define        ENETRESET       102     /* Network dropped connection because of reset */
+#define        ECONNABORTED    103     /* Software caused connection abort */
+#define        ECONNRESET      104     /* Connection reset by peer */
+#define        ENOBUFS         105     /* No buffer space available */
+#define        EISCONN         106     /* Transport endpoint is already connected */
+#define        ENOTCONN        107     /* Transport endpoint is not connected */
+#define        ESHUTDOWN       108     /* Cannot send after transport endpoint shutdown */
+#define        ETOOMANYREFS    109     /* Too many references: cannot splice */
+#define        ETIMEDOUT       110     /* Connection timed out */
+#define        ECONNREFUSED    111     /* Connection refused */
+#define        EHOSTDOWN       112     /* Host is down */
+#define        EHOSTUNREACH    113     /* No route to host */
+#define        EALREADY        114     /* Operation already in progress */
+#define        EINPROGRESS     115     /* Operation now in progress */
+#define        ESTALE          116     /* Stale NFS file handle */
+#define        EUCLEAN         117     /* Structure needs cleaning */
+#define        ENOTNAM         118     /* Not a XENIX named type file */
+#define        ENAVAIL         119     /* No XENIX semaphores available */
+#define        EISNAM          120     /* Is a named type file */
+#define        EREMOTEIO       121     /* Remote I/O error */
+#define        EDQUOT          122     /* Quota exceeded */
+
+#define        ENOMEDIUM       123     /* No medium found */
+#define        EMEDIUMTYPE     124     /* Wrong medium type */
+
+#endif

diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h
new file mode 100644 (file)
index 0000000..56a12f0
--- /dev/null
+++ b/include/asm-blackfin/global_data.h
@@ -0,0 +1,64 @@
+/*
+ * U-boot - global_data.h Declarations for global data of u-boot
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef        __ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+#include <asm/irq.h>
+
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+typedef struct global_data {
+       bd_t *bd;
+       unsigned long flags;
+       unsigned long board_type;
+       unsigned long baudrate;
+       unsigned long have_console;     /* serial_init() was called */
+       unsigned long ram_size;         /* RAM size */
+       unsigned long reloc_off;        /* Relocation Offset */
+       unsigned long env_addr;         /* Address  of Environment struct */
+       unsigned long env_valid;        /* Checksum of Environment valid? */
+       void **jt;                      /* jump table */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define        GD_FLG_RELOC    0x00001 /* Code was relocated to RAM     */
+#define        GD_FLG_DEVINIT  0x00002 /* Devices have been initialized */
+#define        GD_FLG_SILENT   0x00004 /* Silent mode                   */
+
+#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("P5")
+
+#endif

diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h
new file mode 100644 (file)
index 0000000..1ee050e
--- /dev/null
+++ b/include/asm-blackfin/hw_irq.h
@@ -0,0 +1,37 @@
+/*
+ * U-boot - hw_irq.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * linux/arch/$(ARCH)/platform/$(PLATFORM)/hw_irq.h
+ * BlackFin (ADI) assembler restricted values by Ted Ma <mated@sympatico.ca>
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2002 Lineo, Inc <mattw@lineo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/config.h>
+#ifdef CONFIG_EZKIT533
+#include <asm/board/bf533_irq.h>
+#endif
+#ifdef CONFIG_STAMP
+#include <asm/board/bf533_irq.h>
+#endif

diff --git a/include/asm-blackfin/io-kernel.h b/include/asm-blackfin/io-kernel.h
new file mode 100644 (file)
index 0000000..0b0572f
--- /dev/null
+++ b/include/asm-blackfin/io-kernel.h
@@ -0,0 +1,135 @@
+/*
+ * U-boot - io-kernel.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_IO_H
+#define _BLACKFIN_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+/*
+ * These are for ISA/PCI shared memory _only_ and should never be used
+ * on any other type of memory, including Zorro memory. They are meant to
+ * access the bus in the bus byte order which is little-endian!.
+ *
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the m68k architecture, we just read/write the
+ * memory location directly.
+ */
+/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
+ * two accesses to memory, which may be undesireable for some devices.
+ */
+#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; })
+#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; })
+#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; })
+#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+#define memset_io(a,b,c)       memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c)     memcpy((void *)(a),(b),(c))
+#define inb(addr)      cf_inb((volatile unsigned char*)(addr))
+#define inw(addr)      readw(addr)
+#define inl(addr)      readl(addr)
+#define outb(x,addr)   cf_outb((unsigned char)(x), (volatile unsigned char*)(addr))
+#define outw(x,addr)   ((void) writew(x,addr))
+#define outl(x,addr)   ((void) writel(x,addr))
+#define inb_p(addr)    inb(addr)
+#define inw_p(addr)    inw(addr)
+#define inl_p(addr)    inl(addr)
+#define outb_p(x,addr) outb(x,addr)
+#define outw_p(x,addr) outw(x,addr)
+#define outl_p(x,addr) outl(x,addr)
+#define insb(port, addr, count)        memcpy((void*)addr, (void*)port, count)
+#define insw(port, addr, count)        cf_insw((unsigned short*)addr, (unsigned short*)(port), (count))
+#define insl(port, addr, count)        memcpy((void*)addr, (void*)port, (4*count))
+#define outsb(port, addr, count)       memcpy((void*)port, (void*)addr, count)
+#define outsw(port,addr,count)         cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count))
+#define outsl(port, addr, count)       memcpy((void*)port, (void*)addr, (4*count))
+#define IO_SPACE_LIMIT 0xffff
+
+/* Values for nocacheflag and cmode */
+#define IOMAP_FULL_CACHING             0
+#define IOMAP_NOCACHE_SER              1
+#define IOMAP_NOCACHE_NONSER           2
+#define IOMAP_WRITETHROUGH             3
+
+#ifndef __ASSEMBLY__
+extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
+extern void __iounmap(void *addr, unsigned long size);
+extern inline void *ioremap(unsigned long physaddr, unsigned long size)
+{
+       return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
+{
+       return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+extern inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
+{
+       return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
+}
+extern inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
+{
+       return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
+}
+
+extern void iounmap(void *addr);
+
+/* Nothing to do */
+
+extern void blkfin_inv_cache_all(void);
+
+#endif
+
+#define dma_cache_inv(_start,_size) do { blkfin_inv_cache_all();} while (0)
+#define dma_cache_wback(_start,_size) do { } while (0)
+#define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0)
+
+/* Pages to physical address... */
+#define page_to_phys(page)      ((page - mem_map) << PAGE_SHIFT)
+#define page_to_bus(page)       ((page - mem_map) << PAGE_SHIFT)
+
+#define mm_ptov(vaddr)         ((void *) (vaddr))
+#define mm_vtop(vaddr)         ((unsigned long) (vaddr))
+#define phys_to_virt(vaddr)    ((void *) (vaddr))
+#define virt_to_phys(vaddr)    ((unsigned long) (vaddr))
+
+#define virt_to_bus virt_to_phys
+#define bus_to_virt phys_to_virt
+
+#endif
+
+#endif

diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
new file mode 100644 (file)
index 0000000..e5b388e
--- /dev/null
+++ b/include/asm-blackfin/io.h
@@ -0,0 +1,122 @@
+/*
+ * U-boot - io.h IO routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_IO_H
+#define _BLACKFIN_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+/* function prototypes for CF support */
+extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
+extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
+extern unsigned char cf_inb(volatile unsigned char *addr);
+extern void cf_outb(unsigned char val, volatile unsigned char* addr);
+
+/*
+ * These are for ISA/PCI shared memory _only_ and should never be used
+ * on any other type of memory, including Zorro memory. They are meant to
+ * access the bus in the bus byte order which is little-endian!.
+ *
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the m68k architecture, we just read/write the
+ * memory location directly.
+ */
+
+
+#define readb(addr)            ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; })
+#define readw(addr)            ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; })
+#define readl(addr)            ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; })
+
+#define writeb(b,addr)         {((*(volatile unsigned char *) (addr)) = (b)); asm("ssync;");}
+#define writew(b,addr)         {((*(volatile unsigned short *) (addr)) = (b)); asm("ssync;");}
+#define writel(b,addr)         {((*(volatile unsigned int *) (addr)) = (b)); asm("ssync;");}
+
+#define memset_io(a,b,c)       memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c)     memcpy((void *)(a),(b),(c))
+
+#define inb_p(addr)            readb((addr) + BF533_PCIIO_BASE)
+#define inb(addr)              cf_inb((volatile unsigned char*)(addr))
+
+#define outb(x,addr)           cf_outb((unsigned char)(x), (volatile unsigned char*)(addr))
+#define outb_p(x,addr)         outb(x, (addr) + BF533_PCIIO_BASE)
+
+#define inw(addr)              readw((addr) + BF533_PCIIO_BASE)
+#define inl(addr)              readl((addr) + BF533_PCIIO_BASE)
+
+#define outw(x,addr)           writew(x, (addr) + BF533_PCIIO_BASE)
+#define outl(x,addr)           writel(x, (addr) + BF533_PCIIO_BASE)
+
+#define insb(port, addr, count)        memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), count)
+#define insw(port, addr, count)        cf_insw((unsigned short*)addr, (unsigned short*)(port), (count))
+#define insl(port, addr, count)        memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), (4*count))
+
+#define outsb(port,addr,count) memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, count)
+#define outsw(port,addr,count) cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count))
+#define outsl(port,addr,count) memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, (4*count))
+
+#define IO_SPACE_LIMIT         0xffff
+
+/* Values for nocacheflag and cmode */
+#define IOMAP_FULL_CACHING     0
+#define IOMAP_NOCACHE_SER      1
+#define IOMAP_NOCACHE_NONSER   2
+#define IOMAP_WRITETHROUGH     3
+
+extern void *__ioremap(unsigned long physaddr, unsigned long size,
+                      int cacheflag);
+extern void __iounmap(void *addr, unsigned long size);
+
+extern inline void *ioremap(unsigned long physaddr, unsigned long size)
+{
+       return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+extern inline void *ioremap_nocache(unsigned long physaddr,
+                                   unsigned long size)
+{
+       return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+extern inline void *ioremap_writethrough(unsigned long physaddr,
+                                        unsigned long size)
+{
+       return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
+}
+extern inline void *ioremap_fullcache(unsigned long physaddr,
+                                     unsigned long size)
+{
+       return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
+}
+
+extern void iounmap(void *addr);
+
+extern void blkfin_inv_cache_all(void);
+#define dma_cache_inv(_start,_size)            do { blkfin_inv_cache_all();} while (0)
+#define dma_cache_wback(_start,_size)          do { } while (0)
+#define dma_cache_wback_inv(_start,_size)      do { blkfin_inv_cache_all();} while (0)
+
+#endif
+#endif

diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h
new file mode 100644 (file)
index 0000000..5fbc5a3
--- /dev/null
+++ b/include/asm-blackfin/irq.h
@@ -0,0 +1,142 @@
+/*
+ * U-boot - irq.h Interrupt related header file
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file was based on
+ * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
+ *
+ * Changed by HuTao Apr18, 2003
+ *
+ * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
+ * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
+ *
+ * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_IRQ_H_
+#define _BLACKFIN_IRQ_H_
+
+#include <linux/config.h>
+#include <asm/cpu/bf533_irq.h>
+
+/*
+ *   On the Blackfin, the interrupt structure allows remmapping of the hardware
+ *   levels.
+ * - I'm going to assume that the H/W level is going to stay at the default
+ *   settings. If someone wants to go through and abstart this out, feel free
+ *   to mod the interrupt numbering scheme.
+ * - I'm abstracting the interrupts so that uClinux does not know anything
+ *   about the H/W levels. If you want to change the H/W AND keep the abstracted
+ *   levels that uClinux sees, you should be able to do most of it here.
+ * - I've left the "abstract" numbering sparce in case someone wants to pull the
+ *   interrupts apart (just the TX/RX for the various devices)
+ */
+
+#define        NR_IRQS         SYS_IRQS
+/*
+ * "Generic" interrupt sources
+ */
+#define IRQ_SCHED_TIMER        (8)     /* interrupt source for scheduling timer */
+
+static __inline__ int irq_cannonicalize(int irq)
+{
+       return irq;
+}
+
+/*
+ * Machine specific interrupt sources.
+ *
+ * Adding an interrupt service routine for a source with this bit
+ * set indicates a special machine specific interrupt source.
+ * The machine specific files define these sources.
+ *
+ * The IRQ_MACHSPEC bit is now gone - the only thing it did was to
+ * introduce unnecessary overhead.
+ *
+ * All interrupt handling is actually machine specific so it is better
+ * to use function pointers, as used by the Sparc port, and select the
+ * interrupt handling functions when initializing the kernel. This way
+ * we save some unnecessary overhead at run-time.
+ * 01/11/97 - Jes
+ */
+
+extern void (*mach_enable_irq) (unsigned int);
+extern void (*mach_disable_irq) (unsigned int);
+extern int sys_request_irq(unsigned int,
+                       void (*)(int, void *, struct pt_regs *),
+                       unsigned long, const char *, void *);
+extern void sys_free_irq(unsigned int, void *);
+
+/*
+ * various flags for request_irq() - the Amiga now uses the standard
+ * mechanism like all other architectures - SA_INTERRUPT and SA_SHIRQ
+ * are your friends.
+ */
+#define IRQ_FLG_LOCK   (0x0001)        /* handler is not replaceable   */
+#define IRQ_FLG_REPLACE        (0x0002)        /* replace existing handler     */
+#define IRQ_FLG_FAST   (0x0004)
+#define IRQ_FLG_SLOW   (0x0008)
+#define IRQ_FLG_STD    (0x8000)        /* internally used              */
+
+/*
+ * This structure is used to chain together the ISRs for a particular
+ * interrupt source (if it supports chaining).
+ */
+typedef struct irq_node {
+       void (*handler) (int, void *, struct pt_regs *);
+       unsigned long flags;
+       void *dev_id;
+       const char *devname;
+       struct irq_node *next;
+} irq_node_t;
+
+/*
+ * This structure has only 4 elements for speed reasons
+ */
+typedef struct irq_handler {
+       void (*handler) (int, void *, struct pt_regs *);
+       unsigned long flags;
+       void *dev_id;
+       const char *devname;
+} irq_handler_t;
+
+/* count of spurious interrupts */
+extern volatile unsigned int num_spurious;
+
+/*
+ * This function returns a new irq_node_t
+ */
+extern irq_node_t *new_irq_node(void);
+
+/*
+ * Some drivers want these entry points
+ */
+#define enable_irq(x)  (mach_enable_irq  ? (*mach_enable_irq)(x)  : 0)
+#define disable_irq(x) (mach_disable_irq ? (*mach_disable_irq)(x) : 0)
+
+#define enable_irq_nosync(x)   enable_irq(x)
+#define disable_irq_nosync(x)  disable_irq(x)
+
+#endif

diff --git a/include/asm-blackfin/linkage.h b/include/asm-blackfin/linkage.h
new file mode 100644 (file)
index 0000000..18f0c36
--- /dev/null
+++ b/include/asm-blackfin/linkage.h
@@ -0,0 +1,60 @@
+/*
+ * U-boot - linkage.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _LINUX_LINKAGE_H
+#define _LINUX_LINKAGE_H
+
+#include <linux/config.h>
+
+#ifdef __cplusplus
+#define CPP_ASMLINKAGE         extern "C"
+#else
+#define CPP_ASMLINKAGE
+#endif
+
+#define asmlinkage CPP_ASMLINKAGE
+
+#define SYMBOL_NAME_STR(X)     #X
+#define SYMBOL_NAME(X)         X
+#ifdef __STDC__
+#define SYMBOL_NAME_LABEL(X)   X##:
+#else
+#define SYMBOL_NAME_LABEL(X)   X:
+#endif
+
+#define __ALIGN .align         4
+#define __ALIGN_STR            ".align 4"
+
+#ifdef __ASSEMBLY__
+
+#define ALIGN                  __ALIGN
+#define ALIGN_STR              __ALIGN_STR
+
+#define ENTRY(name) \
+       .globl SYMBOL_NAME(name); \
+       ALIGN; \
+       SYMBOL_NAME_LABEL(name)
+#endif
+
+#endif

diff --git a/include/asm-blackfin/machdep.h b/include/asm-blackfin/machdep.h
new file mode 100644 (file)
index 0000000..0a43ba1
--- /dev/null
+++ b/include/asm-blackfin/machdep.h
@@ -0,0 +1,89 @@
+/*
+ * U-boot - machdep.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_MACHDEP_H
+#define _BLACKFIN_MACHDEP_H
+
+/* Machine dependent initial routines:
+ *
+ * Based on include/asm-m68knommu/machdep.h
+ * For blackfin, just now we only have bfin, so they'd point to the default bfin
+ *
+ */
+
+struct pt_regs;
+struct kbd_repeat;
+struct mktime;
+struct hwclk_time;
+struct gendisk;
+struct buffer_head;
+
+extern void (*mach_sched_init) (void (*handler)        (int, void *, struct pt_regs *));
+
+/* machine dependent keyboard functions */
+extern int (*mach_keyb_init) (void);
+extern int (*mach_kbdrate) (struct kbd_repeat *);
+extern void (*mach_kbd_leds) (unsigned int);
+
+/* machine dependent irq functions */
+extern void (*mach_init_IRQ) (void);
+extern void (*(*mach_default_handler)[]) (int, void *, struct pt_regs *);
+extern int (*mach_request_irq) (unsigned int irq,
+                               void (*handler) (int, void *,
+                                                struct pt_regs *),
+                               unsigned long flags, const char *devname,
+                               void *dev_id);
+extern void (*mach_free_irq) (unsigned int irq, void *dev_id);
+extern void (*mach_get_model) (char *model);
+extern int (*mach_get_hardware_list) (char *buffer);
+extern int (*mach_get_irq_list) (char *buf);
+extern void (*mach_process_int) (int irq, struct pt_regs * fp);
+
+/* machine dependent timer functions */
+extern unsigned long (*mach_gettimeoffset) (void);
+extern void (*mach_gettod) (int *year, int *mon, int *day, int *hour,
+                           int *min, int *sec);
+extern int (*mach_hwclk) (int, struct hwclk_time *);
+extern int (*mach_set_clock_mmss) (unsigned long);
+extern void (*mach_reset) (void);
+extern void (*mach_halt) (void);
+extern void (*mach_power_off) (void);
+extern unsigned long (*mach_hd_init) (unsigned long, unsigned long);
+extern void (*mach_hd_setup) (char *, int *);
+extern long mach_max_dma_address;
+extern void (*mach_floppy_setup) (char *, int *);
+extern void (*mach_floppy_eject) (void);
+extern void (*mach_heartbeat) (int);
+extern void (*mach_l2_flush) (int);
+extern int mach_sysrq_key;
+extern int mach_sysrq_shift_state;
+extern int mach_sysrq_shift_mask;
+extern char *mach_sysrq_xlate;
+
+#ifdef CONFIG_UCLINUX
+extern void config_BSP(char *command, int len);
+extern void (*mach_tick) (void);
+#endif
+
+#endif

diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h
new file mode 100644 (file)
index 0000000..1a13d90
--- /dev/null
+++ b/include/asm-blackfin/mem_init.h
@@ -0,0 +1,287 @@
+/*
+ * U-boot - mem_init.h Header file for memory initialization
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if ( CONFIG_MEM_MT48LC16M16A2TG_75  ||  CONFIG_MEM_MT48LC64M4A2FB_7E )
+       #if ( CONFIG_SCLK_HZ > 119402985 )
+               #define SDRAM_tRP       TRP_2
+               #define SDRAM_tRP_num   2
+               #define SDRAM_tRAS      TRAS_7
+               #define SDRAM_tRAS_num  7
+               #define SDRAM_tRCD      TRCD_2
+               #define SDRAM_tWR       TWR_2
+       #endif
+       #if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 )
+               #define SDRAM_tRP       TRP_2
+               #define SDRAM_tRP_num   2
+               #define SDRAM_tRAS      TRAS_6
+               #define SDRAM_tRAS_num  6
+               #define SDRAM_tRCD      TRCD_2
+               #define SDRAM_tWR       TWR_2
+       #endif
+       #if ( CONFIG_SCLK_HZ >  89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 )
+               #define SDRAM_tRP       TRP_2
+               #define SDRAM_tRP_num   2
+               #define SDRAM_tRAS      TRAS_5
+               #define SDRAM_tRAS_num  5
+               #define SDRAM_tRCD      TRCD_2
+               #define SDRAM_tWR       TWR_2
+       #endif
+       #if ( CONFIG_SCLK_HZ >  74626866 ) && ( CONFIG_SCLK_HZ <=  89552239 )
+               #define SDRAM_tRP       TRP_2
+               #define SDRAM_tRP_num   2
+               #define SDRAM_tRAS      TRAS_4
+               #define SDRAM_tRAS_num  4
+               #define SDRAM_tRCD      TRCD_2
+               #define SDRAM_tWR       TWR_2
+       #endif
+       #if ( CONFIG_SCLK_HZ >  66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 )
+               #define SDRAM_tRP       TRP_2
+               #define SDRAM_tRP_num   2
+               #define SDRAM_tRAS      TRAS_3
+               #define SDRAM_tRAS_num  3
+               #define SDRAM_tRCD      TRCD_2
+               #define SDRAM_tWR       TWR_2
+       #endif
+       #if ( CONFIG_SCLK_HZ >  59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
+               #define SDRAM_tRP       TRP_1
+               #define SDRAM_tRP_num   1
+               #define SDRAM_tRAS      TRAS_4
+               #define SDRAM_tRAS_num  3
+               #define SDRAM_tRCD      TRCD_1
+               #define SDRAM_tWR       TWR_2
+       #endif
+       #if ( CONFIG_SCLK_HZ >  44776119 ) && ( CONFIG_SCLK_HZ <=  59701493 )
+               #define SDRAM_tRP       TRP_1
+               #define SDRAM_tRP_num   1
+               #define SDRAM_tRAS      TRAS_3
+               #define SDRAM_tRAS_num  3
+               #define SDRAM_tRCD      TRCD_1
+               #define SDRAM_tWR       TWR_2
+       #endif
+       #if ( CONFIG_SCLK_HZ >  29850746 ) && ( CONFIG_SCLK_HZ <=  44776119 )
+               #define SDRAM_tRP       TRP_1
+               #define SDRAM_tRP_num   1
+               #define SDRAM_tRAS      TRAS_2
+               #define SDRAM_tRAS_num  2
+               #define SDRAM_tRCD      TRCD_1
+               #define SDRAM_tWR       TWR_2
+       #endif
+       #if ( CONFIG_SCLK_HZ <=  29850746 )
+               #define SDRAM_tRP       TRP_1
+               #define SDRAM_tRP_num   1
+               #define SDRAM_tRAS      TRAS_1
+               #define SDRAM_tRAS_num  1
+               #define SDRAM_tRCD      TRCD_1
+               #define SDRAM_tWR       TWR_2
+       #endif
+#endif
+
+#if (CONFIG_MEM_MT48LC16M16A2TG_75)
+       /*SDRAM INFORMATION: */
+       #define SDRAM_Tref      64       /* Refresh period in milliseconds   */
+       #define SDRAM_NRA       8192     /* Number of row addresses in SDRAM */
+       #define SDRAM_CL        CL_3
+#endif
+
+#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
+       /*SDRAM INFORMATION: */
+       #define SDRAM_Tref      64       /* Refresh period in milliseconds   */
+       #define SDRAM_NRA       8192     /* Number of row addresses in SDRAM */
+       #define SDRAM_CL        CL_2
+#endif
+
+#if ( CONFIG_MEM_SIZE == 128 )
+       #define SDRAM_SIZE      EBSZ_128
+#endif
+#if ( CONFIG_MEM_SIZE == 64 )
+       #define SDRAM_SIZE      EBSZ_64
+#endif
+#if (  CONFIG_MEM_SIZE == 32 )
+       #define SDRAM_SIZE      EBSZ_32
+#endif
+#if ( CONFIG_MEM_SIZE == 16 )
+       #define SDRAM_SIZE      EBSZ_16
+#endif
+#if ( CONFIG_MEM_ADD_WDTH == 11 )
+       #define SDRAM_WIDTH     EBCAW_11
+#endif
+#if ( CONFIG_MEM_ADD_WDTH == 10 )
+       #define SDRAM_WIDTH     EBCAW_10
+#endif
+#if ( CONFIG_MEM_ADD_WDTH == 9 )
+       #define SDRAM_WIDTH     EBCAW_9
+#endif
+#if ( CONFIG_MEM_ADD_WDTH == 8 )
+       #define SDRAM_WIDTH     EBCAW_8
+#endif
+
+#define mem_SDBCTL     SDRAM_WIDTH | SDRAM_SIZE | EBE
+
+/* Equation from section 17 (p17-46) of BF533 HRM */
+#define mem_SDRRC      ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref)  / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
+
+/* Enable SCLK Out */
+#define mem_SDGCTL     ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS )
+
+#define flash_EBIU_AMBCTL_WAT  ( ( CONFIG_FLASH_SPEED_BWAT * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
+#define flash_EBIU_AMBCTL_RAT  ( ( CONFIG_FLASH_SPEED_BRAT * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
+#define flash_EBIU_AMBCTL_HT   ( ( CONFIG_FLASH_SPEED_BHT  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) )
+#define flash_EBIU_AMBCTL_ST   ( ( CONFIG_FLASH_SPEED_BST  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
+#define flash_EBIU_AMBCTL_TT   ( ( CONFIG_FLASH_SPEED_BTT  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
+
+#if (flash_EBIU_AMBCTL_TT > 3 )
+       #define flash_EBIU_AMBCTL0_TT   B0TT_4
+#endif
+#if (flash_EBIU_AMBCTL_TT == 3 )
+       #define flash_EBIU_AMBCTL0_TT   B0TT_3
+#endif
+#if (flash_EBIU_AMBCTL_TT == 2 )
+       #define flash_EBIU_AMBCTL0_TT   B0TT_2
+#endif
+#if (flash_EBIU_AMBCTL_TT < 2 )
+       #define flash_EBIU_AMBCTL0_TT   B0TT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_ST > 3 )
+       #define flash_EBIU_AMBCTL0_ST   B0ST_4
+#endif
+#if (flash_EBIU_AMBCTL_ST == 3 )
+       #define flash_EBIU_AMBCTL0_ST   B0ST_3
+#endif
+#if (flash_EBIU_AMBCTL_ST == 2 )
+       #define flash_EBIU_AMBCTL0_ST   B0ST_2
+#endif
+#if (flash_EBIU_AMBCTL_ST < 2 )
+       #define flash_EBIU_AMBCTL0_ST   B0ST_1
+#endif
+
+#if (flash_EBIU_AMBCTL_HT > 2 )
+       #define flash_EBIU_AMBCTL0_HT   B0HT_3
+#endif
+#if (flash_EBIU_AMBCTL_HT == 2 )
+       #define flash_EBIU_AMBCTL0_HT   B0HT_2
+#endif
+#if (flash_EBIU_AMBCTL_HT == 1 )
+       #define flash_EBIU_AMBCTL0_HT   B0HT_1
+#endif
+#if (flash_EBIU_AMBCTL_HT == 0  && CONFIG_FLASH_SPEED_BHT == 0)
+       #define flash_EBIU_AMBCTL0_HT   B0HT_0
+#endif
+#if (flash_EBIU_AMBCTL_HT == 0  && CONFIG_FLASH_SPEED_BHT != 0)
+       #define flash_EBIU_AMBCTL0_HT   B0HT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_WAT > 14)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_15
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 14)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_14
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 13)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_13
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 12)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_12
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 11)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_11
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 10)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_10
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 9)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_9
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 8)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_8
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 7)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_7
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 6)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_6
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 5)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_5
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 4)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_4
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 3)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_3
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 2)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_2
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 1)
+       #define flash_EBIU_AMBCTL0_WAT  B0WAT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_RAT > 14)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_15
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 14)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_14
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 13)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_13
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 12)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_12
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 11)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_11
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 10)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_10
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 9)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_9
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 8)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_8
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 7)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_7
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 6)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_6
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 5)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_5
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 4)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_4
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 3)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_3
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 2)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_2
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 1)
+       #define flash_EBIU_AMBCTL0_RAT  B0RAT_1
+#endif
+
+#define flash_EBIU_AMBCTL0     flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN

diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h
new file mode 100644 (file)
index 0000000..406ece5
--- /dev/null
+++ b/include/asm-blackfin/page.h
@@ -0,0 +1,128 @@
+/*
+ * U-boot -  page.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_PAGE_H
+#define _BLACKFIN_PAGE_H
+
+#include <linux/config.h>
+
+/* PAGE_SHIFT determines the page size */
+
+#define PAGE_SHIFT                     (12)
+#define PAGE_SIZE                      (4096)
+#define PAGE_MASK                      (~(PAGE_SIZE-1))
+
+#ifdef __KERNEL__
+
+#include <asm/setup.h>
+
+#if PAGE_SHIFT < 13
+#define                                        KTHREAD_SIZE (8192)
+#else
+#define                                        KTHREAD_SIZE PAGE_SIZE
+#endif
+
+#ifndef __ASSEMBLY__
+
+#define get_user_page(vaddr)           __get_free_page(GFP_KERNEL)
+#define free_user_page(page, addr)     free_page(addr)
+
+#define clear_page(page)               memset((page), 0, PAGE_SIZE)
+#define copy_page(to,from)             memcpy((to), (from), PAGE_SIZE)
+
+#define clear_user_page(page, vaddr)   clear_page(page)
+#define copy_user_page(to, from, vaddr)        copy_page(to, from)
+
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct {
+       unsigned long pte;
+} pte_t;
+typedef struct {
+       unsigned long pmd[16];
+} pmd_t;
+typedef struct {
+       unsigned long pgd;
+} pgd_t;
+typedef struct {
+       unsigned long pgprot;
+} pgprot_t;
+
+#define pte_val(x)                     ((x).pte)
+#define pmd_val(x)                     ((&x)->pmd[0])
+#define pgd_val(x)                     ((x).pgd)
+#define pgprot_val(x)                  ((x).pgprot)
+
+#define __pte(x)                       ((pte_t) { (x) } )
+#define __pmd(x)                       ((pmd_t) { (x) } )
+#define __pgd(x)                       ((pgd_t) { (x) } )
+#define __pgprot(x)                    ((pgprot_t) { (x) } )
+
+/* to align the pointer to the (next) page boundary */
+#define PAGE_ALIGN(addr)               (((addr)+PAGE_SIZE-1)&PAGE_MASK)
+
+/* Pure 2^n version of get_order */
+extern __inline__ int get_order(unsigned long size)
+{
+       int order;
+
+       size = (size - 1) >> (PAGE_SHIFT - 1);
+       order = -1;
+       do {
+               size >>= 1;
+               order++;
+       } while (size);
+       return order;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#include <asm/page_offset.h>
+
+#define PAGE_OFFSET                    (PAGE_OFFSET_RAW)
+
+#ifndef __ASSEMBLY__
+
+#define __pa(vaddr)                    virt_to_phys((void *)vaddr)
+#define __va(paddr)                    phys_to_virt((unsigned long)paddr)
+
+#define MAP_NR(addr)                   (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
+#define virt_to_page(addr)             (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
+#define VALID_PAGE(page)               ((page - mem_map) < max_mapnr)
+
+#define BUG() do       { \
+        \
+       while (1);      /* dead-loop */ \
+} while (0)
+
+#define PAGE_BUG(page) do      { \
+       BUG(); \
+} while (0)
+
+#endif
+
+#endif
+
+#endif

diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h
new file mode 100644 (file)
index 0000000..262473f
--- /dev/null
+++ b/include/asm-blackfin/page_offset.h
@@ -0,0 +1,35 @@
+/*
+ * U-boot - page_offset.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Changes made by Akbar Hussain April 10, 2001
+ */
+
+#include <linux/config.h>
+
+/* This handles the memory map.. */
+
+#ifdef CONFIG_BLACKFIN
+#define PAGE_OFFSET_RAW                0x00000000
+#endif

diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h
new file mode 100644 (file)
index 0000000..f1f2b5f
--- /dev/null
+++ b/include/asm-blackfin/posix_types.h
@@ -0,0 +1,90 @@
+/*
+ * U-boot - posix_types.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARCH_BLACKFIN_POSIX_TYPES_H
+#define __ARCH_BLACKFIN_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short __kernel_dev_t;
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned short __kernel_ipc_pid_t;
+typedef unsigned short __kernel_uid_t;
+typedef unsigned short __kernel_gid_t;
+typedef unsigned int __kernel_size_t;
+typedef int __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_daddr_t;
+typedef char *__kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+       int val[2];
+#else                          /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+       int __val[2];
+#endif                         /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef __FD_SET
+#define        __FD_SET(d, set)        ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+
+#undef __FD_CLR
+#define        __FD_CLR(d, set)        ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+
+#undef __FD_ISSET
+#define        __FD_ISSET(d, set)      ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+
+#undef __FD_ZERO
+#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif

diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h
new file mode 100644 (file)
index 0000000..19bd720
--- /dev/null
+++ b/include/asm-blackfin/processor.h
@@ -0,0 +1,174 @@
+/*
+ * U-boot - processor.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * include/asm-m68k/processor.h
+ * Changes made by Akbar Hussain Lineo, Inc, May 2001 for BLACKFIN
+ * Copyright (C) 1995 Hamish Macdonald
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_BLACKFIN_PROCESSOR_H
+#define __ASM_BLACKFIN_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr()    ({ __label__ _l; _l: &&_l;})
+
+#include <linux/config.h>
+#include <asm/segment.h>
+#include <asm/ptrace.h>
+#include <asm/current.h>
+
+extern inline unsigned long rdusp(void)
+{
+       unsigned long usp;
+
+       __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp));
+       return usp;
+}
+
+extern inline void wrusp(unsigned long usp)
+{
+       __asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
+}
+
+/*
+ * User space process size: 3.75GB. This is hardcoded into a few places,
+ * so don't change it unless you know what you are doing.
+ */
+#define TASK_SIZE              (0xF0000000UL)
+
+/*
+ * Bus types
+ */
+#define EISA_bus               0
+#define MCA_bus                        0
+
+/*  There is no pc register avaliable for BLACKFIN, so we are going to get
+ *  it indirectly
+ */
+
+#if 0
+inline unsigned long obtain_pc_indirectly(void)
+{
+       unsigned long pc;
+       __asm__ __volatile__("%0 = rets;\n":"=d"(pc));
+       return (pc - 4);        /* call pcrel24 is 4 bytes long  */
+}
+#endif
+
+/*
+ * if you change this structure, you must change the code and offsets
+ * in m68k/machasm.S
+ */
+
+struct thread_struct {
+       unsigned long ksp;      /* kernel stack pointer */
+       unsigned long usp;      /* user stack pointer */
+       unsigned short seqstat; /* saved status register */
+       unsigned long esp0;     /* points to SR of stack frame pt_regs */
+       unsigned long pc;       /* instruction pointer */
+};
+
+#define INIT_MMAP { &init_mm, 0, 0x40000000, NULL, __pgprot(_PAGE_PRESENT|_PAGE_ACCESSED), VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
+
+#define INIT_THREAD  { \
+       sizeof(init_stack) + (unsigned long) init_stack, 0, \
+       PS_S, 0\
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ *
+ * pass the data segment into user programs if it exists,
+ * it can't hurt anything as far as I can tell
+ */
+#define start_thread(_regs, _pc, _usp)           \
+do {                                             \
+       set_fs(USER_DS); /* reads from user space */ \
+       (_regs)->pc = (_pc);                         \
+       if (current->mm)                             \
+               (_regs)->r5 = current->mm->start_data;   \
+       (_regs)->seqstat &= ~0x0c00;                      \
+       wrusp(_usp);                                 \
+       /* Adde by HuTao, May 26, 2003 3:39PM */\
+       if ((_regs)->ipend & 0x8000) /* check whether system in supper mode - StChen */\
+               (_regs)->ipend = 0x0;\
+} while(0)
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+static inline void release_thread(struct task_struct *dead_task)
+{
+}
+
+extern int kernel_thread(int (*fn) (void *), void *arg,
+                        unsigned long flags);
+
+#define copy_segments(tsk, mm)         do { } while (0)
+#define release_segments(mm)           do { } while (0)
+#define forget_segments()              do { } while (0)
+
+/*
+ * Free current thread data structures etc..
+ */
+static inline void exit_thread(void)
+{
+}
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+extern inline unsigned long thread_saved_pc(struct thread_struct *t)
+{
+       extern void scheduling_functions_start_here(void);
+       extern void scheduling_functions_end_here(void);
+       return 0;
+}
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define        KSTK_EIP(tsk)   \
+       ({                      \
+       unsigned long eip = 0;   \
+       if ((tsk)->thread.esp0 > PAGE_SIZE && \
+               MAP_NR((tsk)->thread.esp0) < max_mapnr) \
+               eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
+       eip; })
+#define        KSTK_ESP(tsk)   ((tsk) == current ? rdusp() : (tsk)->thread.usp)
+#define THREAD_SIZE    (2*PAGE_SIZE)
+
+/* Allocation and freeing of basic task resources. */
+#define alloc_task_struct() \
+       ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
+#define free_task_struct(p)    free_pages((unsigned long)(p),1)
+#define get_task_struct(tsk)   atomic_inc(&mem_map[MAP_NR(tsk)].count)
+
+#define init_task              (init_task_union.task)
+#define init_stack             (init_task_union.stack)
+
+#endif

diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h
new file mode 100644 (file)
index 0000000..afd5777
--- /dev/null
+++ b/include/asm-blackfin/ptrace.h
@@ -0,0 +1,269 @@
+/*
+ * U-boot - ptrace.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_PTRACE_H
+#define _BLACKFIN_PTRACE_H
+
+#define NEW_PT_REGS
+
+/*
+ * GCC defines register number like this:
+ * -----------------------------
+ *       0 - 7 are data registers R0-R7
+ *       8 - 15 are address registers P0-P7
+ *      16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
+ *      32 - 33 A registers A0 & A1
+ *      34 -    status register
+ *
+ * We follows above, except:
+ *      32-33 --- Low 32-bit of A0&1
+ *      34-35 --- High 8-bit of A0&1
+ */
+
+#if defined(NEW_PT_REGS)
+
+#define PT_IPEND       0
+#define PT_SYSCFG      (PT_IPEND+4)
+#define PT_SEQSTAT     (PT_SYSCFG+4)
+#define PT_RETE                (PT_SEQSTAT+4)
+#define PT_RETN                (PT_RETE+4)
+#define PT_RETX                (PT_RETN+4)
+#define PT_RETI                (PT_RETX+4)
+#define PT_PC          PT_RETI
+#define PT_RETS                (PT_RETI+4)
+#define PT_RESERVED    (PT_RETS+4)
+#define PT_ASTAT       (PT_RESERVED+4)
+#define PT_LB1         (PT_ASTAT+4)
+#define PT_LB0         (PT_LB1+4)
+#define PT_LT1         (PT_LB0+4)
+#define PT_LT0         (PT_LT1+4)
+#define PT_LC1         (PT_LT0+4)
+#define PT_LC0         (PT_LC1+4)
+#define PT_A1W         (PT_LC0+4)
+#define PT_A1X         (PT_A1W+4)
+#define PT_A0W         (PT_A1X+4)
+#define PT_A0X         (PT_A0W+4)
+#define PT_B3          (PT_A0X+4)
+#define PT_B2          (PT_B3+4)
+#define PT_B1          (PT_B2+4)
+#define PT_B0          (PT_B1+4)
+#define PT_L3          (PT_B0+4)
+#define PT_L2          (PT_L3+4)
+#define PT_L1          (PT_L2+4)
+#define PT_L0          (PT_L1+4)
+#define PT_M3          (PT_L0+4)
+#define PT_M2          (PT_M3+4)
+#define PT_M1          (PT_M2+4)
+#define PT_M0          (PT_M1+4)
+#define PT_I3          (PT_M0+4)
+#define PT_I2          (PT_I3+4)
+#define PT_I1          (PT_I2+4)
+#define PT_I0          (PT_I1+4)
+#define PT_USP         (PT_I0+4)
+#define PT_FP          (PT_USP+4)
+#define PT_P5          (PT_FP+4)
+#define PT_P4          (PT_P5+4)
+#define PT_P3          (PT_P4+4)
+#define PT_P2          (PT_P3+4)
+#define PT_P1          (PT_P2+4)
+#define PT_P0          (PT_P1+4)
+#define PT_R7          (PT_P0+4)
+#define PT_R6          (PT_R7+4)
+#define PT_R5          (PT_R6+4)
+#define PT_R4          (PT_R5+4)
+#define PT_R3          (PT_R4+4)
+#define PT_R2          (PT_R3+4)
+#define PT_R1          (PT_R2+4)
+#define PT_R0          (PT_R1+4)
+#define PT_ORIG_R0     (PT_R0+4)
+#define PT_SR          PT_SEQSTAT
+
+#else
+/*
+ * Here utilize blackfin : dpregs = [pregs + imm16s4]
+ *                     [pregs + imm16s4] = dpregs
+ * to access defferent saved reg in stack
+ */
+#define PT_R3          0
+#define PT_R4          4
+#define PT_R2          8
+#define PT_R1          12
+#define PT_P5          16
+#define PT_P4          20
+#define PT_P3          24
+#define PT_P2          28
+#define PT_P1          32
+#define PT_P0          36
+#define PT_R7          40
+#define PT_R6          44
+#define PT_R5          48
+#define PT_PC          52
+#define PT_SEQSTAT     56      /* so-called SR reg */
+#define PT_SR          PT_SEQSTAT
+#define PT_ASTAT       60
+#define PT_RETS                64
+#define PT_A1w         68
+#define PT_A0w         72
+#define PT_A1x         76
+#define PT_A0x         80
+#define PT_ORIG_R0     84
+#define PT_R0          88
+#define PT_USP         92
+#define PT_FP          96
+#define PT_SP          100
+
+/* Added by HuTao, May26 2003 3:18PM */
+#define PT_IPEND       100
+
+/* Add SYSCFG register for single stepping support */
+#define PT_SYSCFG      104
+
+#endif
+
+#ifndef __ASSEMBLY__
+
+#if defined(NEW_PT_REGS)
+/* this struct defines the way the registers are stored on the
+ * stack during a system call.
+ */
+struct pt_regs {
+       long ipend;
+       long syscfg;
+       long seqstat;
+       long rete;
+       long retn;
+       long retx;
+       long pc;
+       long rets;
+       long reserved;
+       long astat;
+       long lb1;
+       long lb0;
+       long lt1;
+       long lt0;
+       long lc1;
+       long lc0;
+       long a1w;
+       long a1x;
+       long a0w;
+       long a0x;
+       long b3;
+       long b2;
+       long b1;
+       long b0;
+       long l3;
+       long l2;
+       long l1;
+       long l0;
+       long m3;
+       long m2;
+       long m1;
+       long m0;
+       long i3;
+       long i2;
+       long i1;
+       long i0;
+       long usp;
+       long fp;
+       long p5;
+       long p4;
+       long p3;
+       long p2;
+       long p1;
+       long p0;
+       long r7;
+       long r6;
+       long r5;
+       long r4;
+       long r3;
+       long r2;
+       long r1;
+       long r0;
+       long orig_r0;
+};
+
+#else
+/* now we don't know what regs the system call will use        */
+struct pt_regs {
+       long r3;
+       long r4;
+       long r2;
+       long r1;
+       long p5;
+       long p4;
+       long p3;
+       long p2;
+       long p1;
+       long p0;
+       long r7;
+       long r6;
+       long r5;
+       unsigned long pc;
+       unsigned long seqstat;
+       unsigned long astat;
+       unsigned long rets;
+       long a1w;
+       long a0w;
+       long a1x;
+       long a0x;
+       long orig_r0;
+       long r0;
+       long usp;
+       long fp;
+/*
+ * Added for supervisor/user mode switch.
+ *
+ * HuTao May26 03 3:23PM
+ */
+       long ipend;
+       long syscfg;
+};
+
+#endif
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+#define PTRACE_GETREGS         12
+#define PTRACE_SETREGS         13      /* ptrace signal */
+
+#ifdef __KERNEL__
+
+#ifndef PS_S
+#define PS_S                   (0x0c00)
+
+/* Bit 11:10 of SEQSTAT defines user/supervisor/debug mode
+ *        00: user
+ *        01: supervisor
+ *        1x: debug
+ */
+
+#define PS_M                   (0x1000)        /* I am not sure why this is required here Akbar */
+#endif
+
+#define user_mode(regs)                        (!((regs)->seqstat & PS_S))
+#define instruction_pointer(regs)      ((regs)->pc)
+extern void show_regs(struct pt_regs *);
+
+#endif
+#endif
+#endif

diff --git a/include/asm-blackfin/segment.h b/include/asm-blackfin/segment.h
new file mode 100644 (file)
index 0000000..9e6d817
--- /dev/null
+++ b/include/asm-blackfin/segment.h
@@ -0,0 +1,46 @@
+/*
+ * U-boot - segment.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_SEGMENT_H
+#define _BLACKFIN_SEGMENT_H
+
+/* define constants */
+typedef unsigned long mm_segment_t;    /* domain register */
+
+#define KERNEL_CS              0x0
+#define KERNEL_DS              0x0
+#define __KERNEL_CS            0x0
+#define __KERNEL_DS            0x0
+
+#define USER_CS                        0x1
+#define USER_DS                        0x1
+#define __USER_CS              0x1
+#define __USER_DS              0x1
+
+#define get_ds()               (KERNEL_DS)
+#define get_fs()               (__USER_DS)
+#define segment_eq(a,b)                ((a) == (b))
+#define set_fs(val)
+
+#endif

diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h
new file mode 100644 (file)
index 0000000..6ce9688
--- /dev/null
+++ b/include/asm-blackfin/setup.h
@@ -0,0 +1,86 @@
+/*
+ * U-boot - setup.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * asm/setup.h -- Definition of the Linux/Blackfin setup information
+ * Copyright Lineo, Inc 2001 Tony Kou
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_SETUP_H
+#define _BLACKFIN_SETUP_H
+
+#include <linux/config.h>
+
+/*
+ * Linux/Blackfin Architectures
+ */
+
+#define MACH_BFIN      1
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+extern unsigned long blackfin_machtype;
+#endif
+
+#if defined(CONFIG_BFIN)
+#define MACH_IS_BFIN (blackfin_machtype == MACH_BFIN)
+#endif
+
+#ifndef MACH_TYPE
+#define MACH_TYPE (blackfin_machtype)
+#endif
+
+#endif
+
+/*
+ * CPU, FPU and MMU types
+ *
+ * Note: we don't need now:
+ *
+ */
+
+#ifndef __ASSEMBLY__
+extern unsigned long blackfin_cputype;
+#ifdef CONFIG_VME
+extern unsigned long vme_brdtype;
+#endif
+
+/*
+ *  Miscellaneous
+ */
+
+#define NUM_MEMINFO    4
+#define CL_SIZE                256
+
+extern int blackfin_num_memory;        /* # of memory blocks found (and used) */
+extern int blackfin_realnum_memory;    /* real # of memory blocks found */
+extern struct mem_info blackfin_memory[NUM_MEMINFO];   /* memory description */
+
+struct mem_info {
+       unsigned long addr;     /* physical address of memory chunk */
+       unsigned long size;     /* length of memory chunk (in bytes) */
+};
+#endif
+
+#endif

diff --git a/include/asm-blackfin/shared_resources.h b/include/asm-blackfin/shared_resources.h
new file mode 100644 (file)
index 0000000..fbef186
--- /dev/null
+++ b/include/asm-blackfin/shared_resources.h
@@ -0,0 +1,33 @@
+/*
+ * U-boot - setup.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SHARED_RESOURCES_H_
+#define _SHARED_RESOURCES_H_
+
+void swap_to(int device_id);
+
+#define FLASH   0
+#define ETHERNET 1
+
+#endif /* _SHARED_RESOURCES_H_ */

diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
new file mode 100644 (file)
index 0000000..ffd81d6
--- /dev/null
+++ b/include/asm-blackfin/string.h
@@ -0,0 +1,79 @@
+/*
+ * U-boot - string.h String functions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Changed by Lineo Inc. May 2001 */
+
+#ifndef _BLACKFINNOMMU_STRING_H_
+#define _BLACKFINNOMMU_STRING_H_
+
+#ifdef __KERNEL__              /* only set these up for kernel code */
+
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/cpu/defBF533.h>
+
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRNCPY
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRNCMP
+#define __HAVE_ARCH_MEMCPY
+
+extern char *strcpy(char *dest, const char *src);
+extern char *strncpy(char *dest, const char *src, size_t n);
+extern int strcmp(const char *cs, const char *ct);
+extern int strncmp(const char *cs, const char *ct, size_t count);
+extern void * memcpy(void * dest,const void *src,size_t count);
+extern void *memset(void *s, int c, size_t count);
+extern int memcmp(const void *, const void *, __kernel_size_t);
+
+#else                          /* KERNEL */
+
+/*
+ * let user libraries deal with these,
+ * IMHO the kernel has no place defining these functions for user apps
+ */
+
+#define __HAVE_ARCH_STRCPY     1
+#define __HAVE_ARCH_STRNCPY    1
+#define __HAVE_ARCH_STRCAT     1
+#define __HAVE_ARCH_STRNCAT    1
+#define __HAVE_ARCH_STRCMP     1
+#define __HAVE_ARCH_STRNCMP    1
+#define __HAVE_ARCH_STRNICMP   1
+#define __HAVE_ARCH_STRCHR     1
+#define __HAVE_ARCH_STRRCHR    1
+#define __HAVE_ARCH_STRSTR     1
+#define __HAVE_ARCH_STRLEN     1
+#define __HAVE_ARCH_STRNLEN    1
+#define __HAVE_ARCH_MEMSET     1
+#define __HAVE_ARCH_MEMCPY     1
+#define __HAVE_ARCH_MEMMOVE    1
+#define __HAVE_ARCH_MEMSCAN    1
+#define __HAVE_ARCH_MEMCMP     1
+#define __HAVE_ARCH_MEMCHR     1
+#define __HAVE_ARCH_STRTOK     1
+
+#endif                         /* KERNEL */
+
+#endif                         /* _BLACKFIN_STRING_H_ */

diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h
new file mode 100644 (file)
index 0000000..0e53adf
--- /dev/null
+++ b/include/asm-blackfin/system.h
@@ -0,0 +1,182 @@
+/*
+ * U-boot - system.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_SYSTEM_H
+#define _BLACKFIN_SYSTEM_H
+
+#include <linux/config.h>      /* get configuration macros */
+#include <asm/linkage.h>
+#include <asm/blackfin.h>
+#include <asm/segment.h>
+#include <asm/entry.h>
+
+#define prepare_to_switch()    do { } while(0)
+
+/*
+ * switch_to(n) should switch tasks to task ptr, first checking that
+ * ptr isn't the current task, in which case it does nothing.  This
+ * also clears the TS-flag if the task we switched to has used the
+ * math co-processor latest.
+ *
+ * 05/25/01 - Tony Kou (tonyko@lineo.ca)
+ *
+ * Adapted for BlackFin (ADI) by Ted Ma, Metrowerks, and Motorola GSG
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2003 Metrowerks (www.metrowerks.com)
+ */
+
+asmlinkage void resume(void);
+
+#define switch_to(prev,next,last)      {                                       \
+       void *_last;                                                            \
+       __asm__ __volatile__(                                                   \
+                       "r0 = %1;\n\t"                                          \
+                       "r1 = %2;\n\t"                                          \
+                       "call resume;\n\t"                                      \
+                       "%0 = r0;\n\t"                                          \
+                       : "=d" (_last)                                          \
+                       : "d" (prev),                                           \
+                       "d" (next)                                              \
+                       : "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\
+                       (last) = _last;                                         \
+}
+
+/* Force kerenl switch to user mode -- Steven Chen */
+#define switch_to_user_mode()  {                                               \
+       __asm__ __volatile__(                                                   \
+                       "call kernel_to_user_mode;\n\t"                         \
+                       ::                                                      \
+                       : "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\
+}
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define __sti()        {                       \
+       __asm__ __volatile__ (          \
+               "r3 = %0;"              \
+               "sti r3;"               \
+               ::"m"(irq_flags):"R3"); \
+}
+
+#define __cli()        {                       \
+       __asm__ __volatile__ (          \
+               "cli r3;"               \
+               :::"R3");               \
+}
+
+#define __save_flags(x)        {               \
+       __asm__ __volatile__ (          \
+               "cli r3;"               \
+               "%0 = r3;"              \
+               "sti r3;"               \
+               ::"m"(x):"R3");         \
+}
+
+#define __save_and_cli(x)      {       \
+       __asm__ __volatile__ (          \
+               "cli r3;"               \
+               "%0 = r3;"              \
+               ::"m"(x):"R3");         \
+}
+
+#define __restore_flags(x) {           \
+       __asm__ __volatile__ (          \
+               "r3 = %0;"              \
+               "sti r3;"               \
+               ::"m"(x):"R3");         \
+}
+
+/* For spinlocks etc */
+#define local_irq_save(x)      __save_and_cli(x)
+#define local_irq_restore(x)   __restore_flags(x)
+#define local_irq_disable()    __cli()
+#define local_irq_enable()     __sti()
+
+#define cli()                  __cli()
+#define sti()                  __sti()
+#define save_flags(x)          __save_flags(x)
+#define restore_flags(x)       __restore_flags(x)
+#define save_and_cli(x)                __save_and_cli(x)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()                  asm volatile ("nop;\n\t"::)
+#define mb()                   asm volatile (""   : : :"memory")
+#define rmb()                  asm volatile (""   : : :"memory")
+#define wmb()                  asm volatile (""   : : :"memory")
+#define set_rmb(var, value)    do { xchg(&var, value); } while (0)
+#define set_mb(var, value)     set_rmb(var, value)
+#define set_wmb(var, value)    do { var = value; wmb(); } while (0)
+
+#ifdef CONFIG_SMP
+#define smp_mb()               mb()
+#define smp_rmb()              rmb()
+#define smp_wmb()              wmb()
+#else
+#define smp_mb()               barrier()
+#define smp_rmb()              barrier()
+#define smp_wmb()              barrier()
+#endif
+
+#define xchg(ptr,x)            ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+#define tas(ptr)               (xchg((ptr),1))
+
+struct __xchg_dummy {
+       unsigned long a[100];
+};
+#define __xg(x)                        ((volatile struct __xchg_dummy *)(x))
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+                                  int size)
+{
+       unsigned long tmp;
+       unsigned long flags = 0;
+
+       save_and_cli(flags);
+
+       switch (size) {
+       case 1:
+             __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory");
+               break;
+       case 2:
+             __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory");
+               break;
+       case 4:
+             __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory");
+               break;
+       }
+       restore_flags(flags);
+       return tmp;
+}
+
+/* Depend on whether Blackfin has hard reset function */
+/* YES it does, but it is tricky to implement - FIXME later ...MaTed--- */
+#define HARD_RESET_NOW() ({})
+
+#endif /* _BLACKFIN_SYSTEM_H */

diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
new file mode 100644 (file)
index 0000000..29e6eba
--- /dev/null
+++ b/include/asm-blackfin/traps.h
@@ -0,0 +1,86 @@
+/*
+ * U-boot - traps.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * linux/include/asm/traps.h
+ * Copyright (C) 1993        Hamish Macdonald
+ * Lineo, Inc    Jul 2001    Tony Kou
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+  */
+
+#ifndef _BLACKFIN_TRAPS_H
+#define _BLACKFIN_TRAPS_H
+
+#ifndef __ASSEMBLY__
+typedef void (*e_vector) (void);
+extern e_vector vectors[];
+#endif
+
+#define VEC_SYS                (0)
+#define VEC_EXCPT01    (1)
+#define VEC_EXCPT02    (2)
+#define VEC_EXCPT03    (3)
+#define VEC_EXCPT04    (4)
+#define VEC_EXCPT05    (5)
+#define VEC_EXCPT06    (6)
+#define VEC_EXCPT07    (7)
+#define VEC_EXCPT08    (8)
+#define VEC_EXCPT09    (9)
+#define VEC_EXCPT10    (10)
+#define VEC_EXCPT11    (11)
+#define VEC_EXCPT12    (12)
+#define VEC_EXCPT13    (13)
+#define VEC_EXCPT14    (14)
+#define VEC_EXCPT15    (15)
+#define VEC_STEP       (16)
+#define VEC_OVFLOW     (17)
+#define VEC_UNDEF_I    (33)
+#define VEC_ILGAL_I    (34)
+#define VEC_CPLB_VL    (35)
+#define VEC_MISALI_D   (36)
+#define VEC_UNCOV      (37)
+#define VEC_CPLB_M     (38)
+#define VEC_CPLB_MHIT  (39)
+#define VEC_WATCH      (40)
+#define VEC_ISTRU_VL   (41)
+#define VEC_MISALI_I   (42)
+#define VEC_CPLB_I_VL  (43)
+#define VEC_CPLB_I_M   (44)
+#define VEC_CPLB_I_MHIT        (45)
+#define VEC_ILL_RES    (46)    /* including unvalid supervisor mode insn */
+
+#define VECOFF(vec)    ((vec)<<2)
+
+#ifndef __ASSEMBLY__
+
+/* Status register bits */
+#define PS_T  (0x8000)
+#define PS_S  (0x0c00)         /*  Supervisor mode = 0b01      */
+#define PS_D  (0x0c00)         /*  Debug mode = 0b1x           */
+#define PS_M  (0x1000)
+#define PS_C  (0x0001)
+
+#endif
+#endif

diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h
new file mode 100644 (file)
index 0000000..942ed27
--- /dev/null
+++ b/include/asm-blackfin/types.h
@@ -0,0 +1,83 @@
+/*
+ * U-boot - types.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BLACKFIN_TYPES_H
+#define _BLACKFIN_TYPES_H
+
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue.  However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ */
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+/* HK0617   -- Changes to unsigned long temporarily */
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+#endif
+
+#endif

diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h
new file mode 100644 (file)
index 0000000..ec39338
--- /dev/null
+++ b/include/asm-blackfin/u-boot.h
@@ -0,0 +1,47 @@
+/*
+ * U-boot - u-boot.h Structure declarations for board specific data
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_     1
+
+typedef struct bd_info {
+       int bi_baudrate;                /* serial console baudrate */
+       unsigned long bi_ip_addr;       /* IP Address */
+       unsigned char bi_enetaddr[6];   /* Ethernet adress */
+       unsigned long bi_arch_number;   /* unique id for this board */
+       unsigned long bi_boot_params;   /* where this board expects params */
+       unsigned long bi_memstart;      /* start of DRAM memory */
+       unsigned long bi_memsize;       /* size  of DRAM memory in bytes */
+       unsigned long bi_flashstart;    /* start of FLASH memory */
+       unsigned long bi_flashsize;     /* size  of FLASH memory */
+       unsigned long bi_flashoffset;   /* reserved area for startup monitor */
+} bd_t;
+
+#define bi_env_data bi_env->data
+#define bi_env_crc  bi_env->crc
+
+#endif /* _U_BOOT_H_ */

diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
new file mode 100644 (file)
index 0000000..8578166
--- /dev/null
+++ b/include/asm-blackfin/uaccess.h
@@ -0,0 +1,207 @@
+/*
+ * U-boot - uaccess.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * Based on: include/asm-m68knommu/uaccess.h
+ * Changes made by Lineo Inc.    May 2001
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_UACCESS_H
+#define __BLACKFIN_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include <asm/segment.h>
+#include <asm/errno.h>
+
+#define VERIFY_READ    0
+#define VERIFY_WRITE   1
+
+/* We let the MMU do all checking */
+static inline int access_ok(int type, const void *addr, unsigned long size)
+{
+       return ((unsigned long) addr < 0x10f00000);     /* need final decision - Tony */
+}
+
+static inline int verify_area(int type, const void *addr,
+                             unsigned long size)
+{
+       return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry {
+       unsigned long insn, fixup;
+};
+
+/* Returns 0 if exception not found and fixup otherwise.  */
+extern unsigned long search_exception_table(unsigned long);
+
+/*
+ * These are the main single-value transfer routines.  They automatically
+ * use the right size if we just have the right pointer type.
+ */
+
+#define put_user(x, ptr)                               \
+({                                                     \
+    int __pu_err = 0;                                  \
+    typeof(*(ptr)) __pu_val = (x);                     \
+    switch (sizeof (*(ptr))) {                         \
+    case 1:                                            \
+       __put_user_asm(__pu_err, __pu_val, ptr, B);     \
+       break;                                          \
+    case 2:                                            \
+       __put_user_asm(__pu_err, __pu_val, ptr, W);     \
+       break;                                          \
+    case 4:                                            \
+       __put_user_asm(__pu_err, __pu_val, ptr,  );     \
+       break;                                          \
+    default:                                           \
+       __pu_err = __put_user_bad();                    \
+       break;                                          \
+    }                                                  \
+    __pu_err;                                          \
+})
+/*
+ * [pregs] = dregs  ==> 32bits
+ * H[pregs] = dregs  ==> 16bits
+ * B[pregs] = dregs  ==> 8 bits
+ */
+
+#define __put_user(x, ptr) put_user(x, ptr)
+
+static inline int bad_user_access_length(void)
+{
+       panic("bad_user_access_length");
+       return -1;
+}
+
+#define __put_user_bad() (bad_user_access_length(), (-EFAULT))
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+
+#define __ptr(x) ((unsigned long *)(x))
+
+#define __put_user_asm(err,x,ptr,bhw)                                  \
+       __asm__ (#bhw"[%1] = %0;\n\t"                                   \
+               :       /* no outputs */                                \
+               :"d" (x),"a" (__ptr(ptr)) : "memory")
+
+#define get_user(x, ptr)                                               \
+({                                                                     \
+       int __gu_err = 0;                                               \
+       typeof(*(ptr)) __gu_val = 0;                                    \
+       switch (sizeof(*(ptr))) {                                       \
+       case 1:                                                         \
+               __get_user_asm(__gu_err, __gu_val, ptr, B, "=d",(Z));   \
+               break;                                                  \
+       case 2:                                                         \
+               __get_user_asm(__gu_err, __gu_val, ptr, W, "=r",(Z));   \
+               break;                                                  \
+       case 4:                                                         \
+               __get_user_asm(__gu_err, __gu_val, ptr,  , "=r",);      \
+               break;                                                  \
+       default:                                                        \
+               __gu_val = 0;                                           \
+               __gu_err = __get_user_bad();                            \
+               break;                                                  \
+       }                                                               \
+       (x) = __gu_val;                                                 \
+       __gu_err;                                                       \
+})
+
+/* dregs = [pregs] ==> 32bits
+ * H[pregs]   ==> 16bits
+ * B[pregs]   ==> 8 bits
+ */
+
+#define __get_user(x, ptr)     get_user(x, ptr)
+#define __get_user_bad()       (bad_user_access_length(), (-EFAULT))
+
+#define __get_user_asm(err,x,ptr,bhw,reg,option)               \
+       __asm__ ("%0 =" #bhw "[%1]"#option";\n\t"               \
+               : "=d" (x)                                      \
+               : "a" (__ptr(ptr)))
+
+#define copy_from_user(to, from, n)    (memcpy(to, from, n), 0)
+#define copy_to_user(to, from, n)      (memcpy(to, from, n), 0)
+
+#define __copy_from_user(to, from, n)  copy_from_user(to, from, n)
+#define __copy_to_user(to, from, n)    copy_to_user(to, from, n)
+
+#define copy_to_user_ret(to,from,n,retval)     ({ if (copy_to_user(to,from,n)) return retval; })
+#define copy_from_user_ret(to,from,n,retval)   ({ if (copy_from_user(to,from,n)) return retval; })
+
+/*
+ * Copy a null terminated string from userspace.
+ */
+
+static inline long strncpy_from_user(char *dst, const char *src,
+                                    long count)
+{
+       char *tmp;
+       strncpy(dst, src, count);
+       for (tmp = dst; *tmp && count > 0; tmp++, count--);
+       return (tmp - dst);     /* DAVIDM should we count a NUL ?  check getname */
+}
+
+/*
+ * Return the size of a string (including the ending 0)
+ *
+ * Return 0 on exception, a value greater than N if too long
+ */
+static inline long strnlen_user(const char *src, long n)
+{
+       return (strlen(src) + 1);       /* DAVIDM make safer */
+}
+
+#define strlen_user(str) strnlen_user(str, 32767)
+
+/*
+ * Zero Userspace
+ */
+
+static inline unsigned long clear_user(void *to, unsigned long n)
+{
+       memset(to, 0, n);
+       return (0);
+}
+
+#endif

diff --git a/include/asm-blackfin/virtconvert.h b/include/asm-blackfin/virtconvert.h
new file mode 100644 (file)
index 0000000..769f5a0
--- /dev/null
+++ b/include/asm-blackfin/virtconvert.h
@@ -0,0 +1,47 @@
+/*
+ * U-boot - virtconvert.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_VIRT_CONVERT__
+#define __BLACKFIN_VIRT_CONVERT__
+
+/*
+ * Macros used for converting between virtual and physical mappings.
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+
+#define mm_vtop(vaddr)         ((unsigned long) vaddr)
+#define mm_ptov(vaddr)         ((unsigned long) vaddr)
+#define phys_to_virt(vaddr)    ((unsigned long) vaddr)
+#define virt_to_phys(vaddr)    ((unsigned long) vaddr)
+
+#define virt_to_bus            virt_to_phys
+#define bus_to_virt            phys_to_virt
+
+#endif
+#endif

diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 6c2c712a268edf14f72eb94c31e7d5c2284574d4..c2b4c5c6ab424bfeb6d3d78d64e6583c71d4bf4a 100644 (file)
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -71,8 +71,8 @@ typedef struct sysconf8349 {
                        | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
        u32 sicrl; /* System General Purpose Register Low */
 #define SICRL_LDP_A   0x80000000
-#define SICRL_USB0    0x40000000
-#define SICRL_USB1    0x20000000
+#define SICRL_USB1    0x40000000
+#define SICRL_USB0    0x20000000
 #define SICRL_UART    0x0C000000
 #define SICRL_GPIO1_A 0x02000000
 #define SICRL_GPIO1_B 0x01000000
@@ -675,24 +675,76 @@ typedef struct ddr8349{
        u8   res9[8];
        u32  sdram_clk_cntl;
 #define DDR_SDRAM_CLK_CNTL_SS_EN               0x80000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025      0x01000000
 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05       0x02000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075      0x03000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1                0x04000000
 
        u8 res4[0xCCC];
        u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
        u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
        u32 ecc_err_inject;     /**< Memory Data Path Error Injection Mask ECC */
+#define ECC_ERR_INJECT_EMB                     (0x80000000>>22)        /* ECC Mirror Byte */
+#define ECC_ERR_INJECT_EIEN                    (0x80000000>>23)        /* Error Injection Enable */
+#define ECC_ERR_INJECT_EEIM                    (0xff000000>>24)        /* ECC Erroe Injection Enable */
+#define ECC_ERR_INJECT_EEIM_SHIFT              0
        u8 res5[0x14];
        u32 capture_data_hi;    /**< Memory Data Path Read Capture High */
        u32 capture_data_lo;    /**< Memory Data Path Read Capture Low */
        u32 capture_ecc;        /**< Memory Data Path Read Capture ECC */
+#define CAPTURE_ECC_ECE                                (0xff000000>>24)
+#define CAPTURE_ECC_ECE_SHIFT                  0
        u8 res6[0x14];
        u32 err_detect;         /**< Memory Error Detect */
+#define ECC_ERROR_DETECT_MME                   (0x80000000>>0)         /* Multiple Memory Errors */
+#define ECC_ERROR_DETECT_MBE                   (0x80000000>>28)        /* Multiple-Bit Error */
+#define ECC_ERROR_DETECT_SBE                   (0x80000000>>29)        /* Single-Bit ECC Error Pickup */
+#define ECC_ERROR_DETECT_MSE                   (0x80000000>>31)        /* Memory Select Error */
        u32 err_disable;        /**< Memory Error Disable */
+#define ECC_ERROR_DISABLE_MBED                 (0x80000000>>28)        /* Multiple-Bit ECC Error Disable */
+#define ECC_ERROR_DISABLE_SBED                 (0x80000000>>29)        /* Sinle-Bit ECC Error disable */
+#define ECC_ERROR_DISABLE_MSED                 (0x80000000>>31)        /* Memory Select Error Disable */
+#define ECC_ERROR_ENABLE                       ~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED)
        u32 err_int_en;         /**< Memory Error Interrupt Enable */
+#define ECC_ERR_INT_EN_MBEE                    (0x80000000>>28)        /* Multiple-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_SBEE                    (0x80000000>>29)        /* Single-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_MSEE                    (0x80000000>>31)        /* Memory Select Error Interrupt Enable */
+#define ECC_ERR_INT_DISABLE                    ~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE)
        u32 capture_attributes; /**< Memory Error Attributes Capture */
+#define ECC_CAPT_ATTR_BNUM                     (0xe0000000>>1)         /* Data Beat Num */
+#define ECC_CAPT_ATTR_BNUM_SHIFT               28
+#define ECC_CAPT_ATTR_TSIZ                     (0xc0000000>>6)         /* Transaction Size */
+#define ECC_CAPT_ATTR_TSIZ_FOUR_DW             0
+#define ECC_CAPT_ATTR_TSIZ_ONE_DW              1
+#define ECC_CAPT_ATTR_TSIZ_TWO_DW              2
+#define ECC_CAPT_ATTR_TSIZ_THREE_DW            3
+#define ECC_CAPT_ATTR_TSIZ_SHIFT               24
+#define ECC_CAPT_ATTR_TSRC                     (0xf8000000>>11)        /* Transaction Source */
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT                0x0
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF                0x2
+#define ECC_CAPT_ATTR_TSRC_TSEC1               0x4
+#define ECC_CAPT_ATTR_TSRC_TSEC2               0x5
+#define ECC_CAPT_ATTR_TSRC_USB                 (0x06|0x07)
+#define ECC_CAPT_ATTR_TSRC_ENCRYPT             0x8
+#define ECC_CAPT_ATTR_TSRC_I2C                 0x9
+#define ECC_CAPT_ATTR_TSRC_JTAG                        0xA
+#define ECC_CAPT_ATTR_TSRC_PCI1                        0xD
+#define ECC_CAPT_ATTR_TSRC_PCI2                        0xE
+#define ECC_CAPT_ATTR_TSRC_DMA                 0xF
+#define ECC_CAPT_ATTR_TSRC_SHIFT               16
+#define ECC_CAPT_ATTR_TTYP                     (0xe0000000>>18)        /* Transaction Type */
+#define ECC_CAPT_ATTR_TTYP_WRITE               0x1
+#define ECC_CAPT_ATTR_TTYP_READ                        0x2
+#define ECC_CAPT_ATTR_TTYP_R_M_W               0x3
+#define ECC_CAPT_ATTR_TTYP_SHIFT               12
+#define ECC_CAPT_ATTR_VLD                      (0x80000000>>31)        /* Valid */
        u32 capture_address;    /**< Memory Error Address Capture */
        u32 capture_ext_address;/**< Memory Error Extended Address Capture */
        u32 err_sbe;            /**< Memory Single-Bit ECC Error Management */
+#define ECC_ERROR_MAN_SBET                     (0xff000000>>8)         /* Single-Bit Error Threshold 0..255*/
+#define ECC_ERROR_MAN_SBET_SHIFT               16
+#define ECC_ERROR_MAN_SBEC                     (0xff000000>>24)        /* Single Bit Error Counter 0..255*/
+#define ECC_ERROR_MAN_SBEC_SHIFT               0
        u8 res7[0xA4];
        u32 debug_reg;
        u8 res8[0xFC];
@@ -795,10 +847,95 @@ typedef struct spi8349
        u8 res1[0xD8];
 } spi8349_t;
 
+
+/*
+ * DMA/Messaging Unit
+ */
 typedef struct dma8349 {
-       u8 fixme[0x300];
+       u32 res0[0xC];  /* 0x0-0x29 reseverd */
+       u32 omisr;      /* 0x30 Outbound message interrupt status register */
+       u32 omimr;      /* 0x34 Outbound message interrupt mask register */
+       u32 res1[0x6];  /* 0x38-0x49 reserved */
+
+       u32 imr0;       /* 0x50 Inbound message register 0 */
+       u32 imr1;       /* 0x54 Inbound message register 1 */
+       u32 omr0;       /* 0x58 Outbound message register 0 */
+       u32 omr1;       /* 0x5C Outbound message register 1 */
+
+       u32 odr;        /* 0x60 Outbound doorbell register */
+       u32 res2;       /* 0x64-0x67 reserved */
+       u32 idr;        /* 0x68 Inbound doorbell register */
+       u32 res3[0x5];  /* 0x6C-0x79 reserved */
+
+       u32 imisr;      /* 0x80 Inbound message interrupt status register */
+       u32 imimr;      /* 0x84 Inbound message interrupt mask register */
+       u32 res4[0x1E]; /* 0x88-0x99 reserved */
+
+       u32 dmamr0;     /* 0x100 DMA 0 mode register */
+       u32 dmasr0;     /* 0x104 DMA 0 status register */
+       u32 dmacdar0;   /* 0x108 DMA 0 current descriptor address register */
+       u32 res5;       /* 0x10C reserved */
+       u32 dmasar0;    /* 0x110 DMA 0 source address register */
+       u32 res6;       /* 0x114 reserved */
+       u32 dmadar0;    /* 0x118 DMA 0 destination address register */
+       u32 res7;       /* 0x11C reserved */
+       u32 dmabcr0;    /* 0x120 DMA 0 byte count register */
+       u32 dmandar0;   /* 0x124 DMA 0 next descriptor address register */
+       u32 res8[0x16]; /* 0x128-0x179 reserved */
+
+       u32 dmamr1;     /* 0x180 DMA 1 mode register */
+       u32 dmasr1;     /* 0x184 DMA 1 status register */
+       u32 dmacdar1;   /* 0x188 DMA 1 current descriptor address register */
+       u32 res9;       /* 0x18C reserved */
+       u32 dmasar1;    /* 0x190 DMA 1 source address register */
+       u32 res10;      /* 0x194 reserved */
+       u32 dmadar1;    /* 0x198 DMA 1 destination address register */
+       u32 res11;      /* 0x19C reserved */
+       u32 dmabcr1;    /* 0x1A0 DMA 1 byte count register */
+       u32 dmandar1;   /* 0x1A4 DMA 1 next descriptor address register */
+       u32 res12[0x16];/* 0x1A8-0x199 reserved */
+
+       u32 dmamr2;     /* 0x200 DMA 2 mode register */
+       u32 dmasr2;     /* 0x204 DMA 2 status register */
+       u32 dmacdar2;   /* 0x208 DMA 2 current descriptor address register */
+       u32 res13;      /* 0x20C reserved */
+       u32 dmasar2;    /* 0x210 DMA 2 source address register */
+       u32 res14;      /* 0x214 reserved */
+       u32 dmadar2;    /* 0x218 DMA 2 destination address register */
+       u32 res15;      /* 0x21C reserved */
+       u32 dmabcr2;    /* 0x220 DMA 2 byte count register */
+       u32 dmandar2;   /* 0x224 DMA 2 next descriptor address register */
+       u32 res16[0x16];/* 0x228-0x279 reserved */
+
+       u32 dmamr3;     /* 0x280 DMA 3 mode register */
+       u32 dmasr3;     /* 0x284 DMA 3 status register */
+       u32 dmacdar3;   /* 0x288 DMA 3 current descriptor address register */
+       u32 res17;      /* 0x28C reserved */
+       u32 dmasar3;    /* 0x290 DMA 3 source address register */
+       u32 res18;      /* 0x294 reserved */
+       u32 dmadar3;    /* 0x298 DMA 3 destination address register */
+       u32 res19;      /* 0x29C reserved */
+       u32 dmabcr3;    /* 0x2A0 DMA 3 byte count register */
+       u32 dmandar3;   /* 0x2A4 DMA 3 next descriptor address register */
+
+       u32 dmagsr;     /* 0x2A8 DMA general status register */
+       u32 res20[0x15];/* 0x2AC-0x2FF reserved */
 } dma8349_t;
 
+/* DMAMRn bits */
+#define DMA_CHANNEL_START                      (0x00000001)            /* Bit - DMAMRn CS */
+#define DMA_CHANNEL_TRANSFER_MODE_DIRECT       (0x00000004)            /* Bit - DMAMRn CTM */
+#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN     (0x00001000)            /* Bit - DMAMRn SAHE */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B     (0x00000000)            /* 2Bit- DMAMRn SAHTS 1byte */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B     (0x00004000)            /* 2Bit- DMAMRn SAHTS 2bytes */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B     (0x00008000)            /* 2Bit- DMAMRn SAHTS 4bytes */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B     (0x0000c000)            /* 2Bit- DMAMRn SAHTS 8bytes */
+#define DMA_CHANNEL_SNOOP                      (0x00010000)            /* Bit - DMAMRn DMSEN */
+
+/* DMASRn bits */
+#define DMA_CHANNEL_BUSY                       (0x00000004)            /* Bit - DMASRn CB */
+#define DMA_CHANNEL_TRANSFER_ERROR             (0x00000080)            /* Bit - DMASRn TE */
+
 /*
  * PCI Software Configuration Registers
  */

diff --git a/include/asm-ppc/iopin_85xx.h b/include/asm-ppc/iopin_85xx.h
new file mode 100644 (file)
index 0000000..f854df6
--- /dev/null
+++ b/include/asm-ppc/iopin_85xx.h
@@ -0,0 +1,146 @@
+/*
+ * MPC85xx I/O port pin manipulation functions
+ */
+
+#ifndef _ASM_IOPIN_85xx_H_
+#define _ASM_IOPIN_85xx_H_
+
+#include <linux/types.h>
+#include <asm/immap_85xx.h>
+
+#ifdef __KERNEL__
+
+typedef struct {
+       u_char port:2;          /* port number (A=0, B=1, C=2, D=3) */
+       u_char pin:5;           /* port pin (0-31) */
+       u_char flag:1;          /* for whatever */
+} iopin_t;
+
+#define IOPIN_PORTA    0
+#define IOPIN_PORTB    1
+#define IOPIN_PORTC    2
+#define IOPIN_PORTD    3
+
+extern __inline__ void iopin_set_high (iopin_t * iopin)
+{
+       volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+       datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void iopin_set_low (iopin_t * iopin)
+{
+       volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+       datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint iopin_is_high (iopin_t * iopin)
+{
+       volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+       return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint iopin_is_low (iopin_t * iopin)
+{
+       volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
+       return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void iopin_set_out (iopin_t * iopin)
+{
+       volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+       dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void iopin_set_in (iopin_t * iopin)
+{
+       volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+       dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint iopin_is_out (iopin_t * iopin)
+{
+       volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+       return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint iopin_is_in (iopin_t * iopin)
+{
+       volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
+       return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void iopin_set_odr (iopin_t * iopin)
+{
+       volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+       odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void iopin_set_act (iopin_t * iopin)
+{
+       volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+       odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint iopin_is_odr (iopin_t * iopin)
+{
+       volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+       return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint iopin_is_act (iopin_t * iopin)
+{
+       volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
+       return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void iopin_set_ded (iopin_t * iopin)
+{
+       volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+       parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void iopin_set_gen (iopin_t * iopin)
+{
+       volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+       parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint iopin_is_ded (iopin_t * iopin)
+{
+       volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+       return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint iopin_is_gen (iopin_t * iopin)
+{
+       volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
+       return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void iopin_set_opt2 (iopin_t * iopin)
+{
+       volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+       sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void iopin_set_opt1 (iopin_t * iopin)
+{
+       volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+       sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint iopin_is_opt2 (iopin_t * iopin)
+{
+       volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+       return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint iopin_is_opt1 (iopin_t * iopin)
+{
+       volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
+       return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IOPIN_85xx_H_ */

diff --git a/include/asm-ppc/mpc8349_pci.h b/include/asm-ppc/mpc8349_pci.h
index 48255a34f94769b530b6707819780be344fe6ef3..7a1adba950d14e6bfb33b7a7b78e194950dadc9a 100644 (file)
--- a/include/asm-ppc/mpc8349_pci.h
+++ b/include/asm-ppc/mpc8349_pci.h
@@ -77,6 +77,7 @@
 #define POCMR_ENABLE        0x80000000
 #define POCMR_PCI_IO        0x40000000
 #define POCMR_PREFETCH_EN   0x20000000
+#define POCMR_PCI2          0x10000000
 
 /* Soft PCI reset */
 

diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h
index 9ee4849611c3cf812027d979ea6b7eba28d2bf58..cf36583108c7bd1513eb1f1863fc1eb4053a66b9 100644 (file)
--- a/include/cmd_confdefs.h
+++ b/include/cmd_confdefs.h
@@ -112,7 +112,6 @@
                        CFG_CMD_DISPLAY | \
                        CFG_CMD_DOC     | \
                        CFG_CMD_DTT     | \
-                       CFG_CMD_ECHO    | \
                        CFG_CMD_EEPROM  | \
                        CFG_CMD_ELF     | \
                        CFG_CMD_EXT2    | \

diff --git a/include/common.h b/include/common.h
index d2570a803ea45eb96b924c956e015a3d3f7df65d..5d8b15628b5d7aa8587bb2020c898674eebeea00 100644 (file)
--- a/include/common.h
+++ b/include/common.h
@@ -365,7 +365,8 @@ void        trap_init     (ulong);
     defined (CONFIG_75x)       || \
     defined (CONFIG_74xx)      || \
     defined (CONFIG_MPC8220)   || \
-    defined(CONFIG_MPC85xx)
+    defined (CONFIG_MPC85xx)   || \
+    defined (CONFIG_MPC83XX)
 unsigned char  in8(unsigned int);
 void           out8(unsigned int, unsigned char);
 unsigned short in16(unsigned int);

diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 9841893899adc1d5fa426a65f1d49c44de64c70b..d03c05bf349fd141f95d5711aa82a50ac57e62ff 100644 (file)
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -132,6 +132,9 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
+
+#define CFG_NAND_LEGACY
+
 #define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices           */
 #define SECTORSIZE 512
 

diff --git a/include/configs/Adder.h b/include/configs/Adder.h
index f8075466c48c8b5e18408bcd168fbac4a5bb8419..0e6b50f8b0e019e8124ccb6c818908e68c1da92f 100644 (file)
--- a/include/configs/Adder.h
+++ b/include/configs/Adder.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004 Arabella Software Ltd.
+ * Copyright (C) 2004-2005 Arabella Software Ltd.
  * Yuli Barcohen <yuli@arabellasw.com>
  *
  * Support for Analogue&Micro Adder boards family.
@@ -35,11 +35,13 @@
 #define        CONFIG_8xx_CONS_SMC1    1               /* Console is on SMC1           */
 #define CONFIG_BAUDRATE                38400
 
-#define        CONFIG_FEC_ENET                         /* Ethernet is on FEC           */
-#ifdef  CONFIG_FEC_ENET
+#define CONFIG_ETHER_ON_FEC1
+#define CONFIG_ETHER_ON_FEC2
+
+#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
 #define CFG_DISCOVER_PHY
 #define FEC_ENET
-#endif /* CONFIG_FEC_ENET */
+#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */
 
 #define CONFIG_8xx_OSCLK               10000000 /* 10 MHz oscillator on EXTCLK */
 #define CONFIG_8xx_CPUCLK_DEFAULT      50000000
@@ -47,7 +49,7 @@
 #ifdef CONFIG_MPC852T
 #define CFG_8xx_CPUCLK_MAX             50000000
 #else
-#define CFG_8xx_CPUCLK_MAX             120000000
+#define CFG_8xx_CPUCLK_MAX             133000000
 #endif /* CONFIG_MPC852T */
 
 #define CONFIG_COMMANDS                (CONFIG_CMD_DFL  \
@@ -62,7 +64,7 @@
 
 #define CONFIG_BOOTDELAY       5               /* Autoboot after 5 seconds     */
 #define CONFIG_BOOTCOMMAND     "bootm fe040000"        /* Autoboot command     */
-#define CONFIG_BOOTARGS                "root=/dev/mtdblock2 rw"
+#define CONFIG_BOOTARGS                "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)"
 
 #define CONFIG_BZIP2           /* Include support for bzip2 compressed images  */
 #undef CONFIG_WATCHDOG         /* Disable platform specific watchdog           */
@@ -79,7 +81,7 @@
 #define CFG_MAXARGS            16              /* Max number of command args   */
 #define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size    */
 
-#define CFG_LOAD_ADDR          0x100000        /* Default load address         */
+#define CFG_LOAD_ADDR          0x400000        /* Default load address         */
 
 #define CFG_HZ                 1000            /* Decrementer freq: 1 ms ticks */
 
@@ -89,24 +91,21 @@
  * RAM configuration (note that CFG_SDRAM_BASE must be zero)
  */
 #define CFG_SDRAM_BASE         0x00000000
-#define CFG_SDRAM_SIZE         0x00800000      /* 8 Mbyte                      */
-
-#define CFG_OR1_PRELIM         (0xFF800000 | OR_CSNT_SAM | OR_ACS_DIV2)
-#define CFG_BR1_PRELIM         (CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V)
+#define CFG_SDRAM_MAX_SIZE     0x01000000      /* Up to 16 Mbyte               */
 
-#define CFG_MAMR               0x00802114
+#define CFG_MAMR               0x00002114
 
 /*
- * 2048        SDRAM rows
+ * 4096        Up to 4096 SDRAM rows
  * 1000        factor s -> ms
- * 64  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 32  PTP (pre-divider from MPTPR)
  * 4   Number of refresh cycles per period
  * 64  Refresh cycle in ms per number of rows
  */
-#define CFG_PTA_PER_CLK                ((2048 * 64 * 1000) / (4 * 64))
+#define CFG_PTA_PER_CLK                ((4096 * 32 * 1000) / (4 * 64))
 
 #define CFG_MEMTEST_START      0x00100000      /* memtest works on             */
-#define CFG_MEMTEST_END                0x00700000      /* 1 ... 7 MB in SDRAM          */
+#define CFG_MEMTEST_END                0x00500000      /* 1 ... 5 MB in SDRAM          */
 
 #define CFG_RESET_ADDRESS      0x09900000
 
@@ -139,6 +138,8 @@
 #define CFG_ENV_SECT_SIZE      0x10000         /* We use one complete sector   */
 #define CFG_ENV_ADDR           (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 
+#define CONFIG_ENV_OVERWRITE
+
 #define CFG_OR0_PRELIM         0xFF000774
 #define CFG_BR0_PRELIM         (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
 

diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
new file mode 100644 (file)
index 0000000..a79de40
--- /dev/null
+++ b/include/configs/BC3450.h
@@ -0,0 +1,568 @@
+/*
+ * -- Version 1.1 --
+ *
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * (C) Copyright 2005
+ * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
+ *
+ * History:
+ *     1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC5xxx         1       /* This is an MPC5xxx CPU           */
+#define CONFIG_MPC5200         1       /* (more precisely a MPC5200 CPU)   */
+#define CONFIG_TQM5200         1       /* ... on a TQM5200 module          */
+
+#define CONFIG_BC3450           1       /* ... on a BC3450 mainboard       */
+#define CONFIG_BC3450_PS2      1       /*  + a PS/2 converter onboard      */
+#define CONFIG_BC3450_IDE      1       /*  + IDE drives (Compact Flash)    */
+#define CONFIG_BC3450_USB      1       /*  + USB support                   */
+# define CONFIG_FAT            1       /*    + FAT support                 */
+# define CONFIG_EXT2           1       /*    + EXT2 support                */
+#undef CONFIG_BC3450_BUZZER            /*  + Buzzer onboard                */
+#undef CONFIG_BC3450_CAN               /*  + CAN transceiver               */
+#undef CONFIG_BC3450_DS1340            /*  + a RTC DS1340 onboard          */
+#undef CONFIG_BC3450_DS3231            /*  + a RTC DS3231 onboard      tbd */
+#undef CONFIG_BC3450_AC97              /*  + AC97 on PSC2,             tbd */
+#define CONFIG_BC3450_FP       1       /*  + enable FP O/P                 */
+#undef CONFIG_BC3450_CRT               /*  + enable CRT O/P (Debug only!)  */
+
+#define CFG_MPC5XXX_CLKIN      33000000 /* ... running at 33.000000MHz     */
+
+#define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM          0x02    /* Software reboot                  */
+
+#define CFG_CACHELINE_SIZE     32      /* For MPC5xxx CPUs                 */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT  5       /* log base 2 of the above value    */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE     1       /* console is on PSC1           */
+#define CONFIG_BAUDRATE                115200  /* ... at 115200 bps            */
+#define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * AT-PS/2 Multiplexer
+ */
+#ifdef CONFIG_BC3450_PS2
+# define CONFIG_PS2KBD                 /* AT-PS/2 Keyboard             */
+# define CONFIG_PS2MULT                        /* .. on PS/2 Multiplexer       */
+# define CONFIG_PS2SERIAL      6               /* .. on PSC6           */
+# define CONFIG_PS2MULT_DELAY  (CFG_HZ/2)      /* Initial delay        */
+# define CONFIG_BOARD_EARLY_INIT_R
+#endif /* CONFIG_BC3450_PS2 */
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+# define CONFIG_PCI            1
+# define CONFIG_PCI_PNP                1
+/* #define CONFIG_PCI_SCAN_SHOW        1 */
+
+#define CONFIG_PCI_MEM_BUS     0x40000000
+#define CONFIG_PCI_MEM_PHYS    CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE    0x10000000
+
+#define CONFIG_PCI_IO_BUS      0x50000000
+#define CONFIG_PCI_IO_PHYS     CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE     0x01000000
+
+#define CONFIG_NET_MULTI       1
+/*#define CONFIG_EEPRO100      XXX - FIXME: conflicts when CONFIG_MII is enabled */
+#define CFG_RX_ETH_BUFFER      8       /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X         1
+
+#ifdef CONFIG_PCI
+# define ADD_PCI_CMD           CFG_CMD_PCI
+#else
+# define ADD_PCI_CMD           0
+#endif
+
+/*
+ * Video console
+ */
+# define CONFIG_VIDEO
+# define CONFIG_VIDEO_SM501
+# define CONFIG_VIDEO_SM501_32BPP
+# define CONFIG_CFB_CONSOLE
+# define CONFIG_VIDEO_LOGO
+# define CONFIG_VGA_AS_SINGLE_DEVICE
+# define CONFIG_CONSOLE_EXTRA_INFO     /* display Board/Device-Infos */
+# define CONFIG_VIDEO_SW_CURSOR
+# define CONFIG_SPLASH_SCREEN
+# define CFG_CONSOLE_IS_IN_ENV
+
+#ifdef CONFIG_VIDEO
+# define ADD_BMP_CMD           CFG_CMD_BMP
+#else
+# define ADD_BMP_CMD           0
+#endif
+
+/* 
+ * Partitions 
+ */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* 
+ * USB 
+ */
+#ifdef CONFIG_BC3450_USB
+# define CONFIG_USB_OHCI
+# define ADD_USB_CMD           CFG_CMD_USB
+# define CONFIG_USB_STORAGE
+#else /* !CONFIG_BC3450_USB */
+# define ADD_USB_CMD           0
+#endif /* CONFIG_BC3450_USB */
+
+/* 
+ * POST support 
+ */
+#define CONFIG_POST            (CFG_POST_MEMORY   | \
+                                CFG_POST_CPU      | \
+                                CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+# define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+/* preserve space for the post_word at end of on-chip SRAM */
+# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#else
+# define CFG_CMD_POST_DIAG 0
+#endif /* CONFIG_POST */
+
+/* 
+ * IDE 
+ */
+#ifdef CONFIG_BC3450_IDE
+# define ADD_IDE_CMD           CFG_CMD_IDE
+#else
+# define ADD_IDE_CMD           0
+#endif /* CONFIG_BC3450_IDE */
+
+/*
+ * Filesystem support
+ */
+#if defined (CONFIG_BC3450_IDE) || defined (CONFIG_BC3450_USB)
+#ifdef CONFIG_FAT
+# define ADD_FAT_CMD           CFG_CMD_FAT
+#else
+# define ADD_FAT_CMD           0
+#endif /* CONFIG_FAT */
+
+#ifdef CONFIG_EXT2
+# define ADD_EXT2_CMD          CFG_CMD_EXT2
+#else
+# define ADD_EXT2_CMD          0
+#endif /* CONFIG_EXT2 */
+#endif /* CONFIG_BC3450_IDE / _USB */
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS               (CONFIG_CMD_DFL  | \
+                               ADD_BMP_CMD     | \
+                               ADD_IDE_CMD     | \
+                               ADD_FAT_CMD     | \
+                               ADD_EXT2_CMD    | \
+                               ADD_PCI_CMD     | \
+                               ADD_USB_CMD     | \
+                               CFG_CMD_ASKENV  | \
+                               CFG_CMD_DATE    | \
+                               CFG_CMD_DHCP    | \
+                               CFG_CMD_ECHO    | \
+                               CFG_CMD_EEPROM  | \
+                               CFG_CMD_I2C     | \
+                               CFG_CMD_JFFS2   | \
+                               CFG_CMD_MII     | \
+                               CFG_CMD_NFS     | \
+                               CFG_CMD_PING    | \
+                               CFG_CMD_POST_DIAG | \
+                               CFG_CMD_REGINFO | \
+                               CFG_CMD_SNTP    | \
+                               CFG_CMD_BSP)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define        CONFIG_TIMESTAMP                /* display image timestamps */
+
+#if (TEXT_BASE == 0xFC000000)          /* Boot low */
+#   define CFG_LOWBOOT         1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds */
+#define CONFIG_ZERO_BOOTDELAY_CHECK    /* check for keypress on bootdelay==0 */
+
+#define CONFIG_PREBOOT "echo;" \
+       "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+       "echo;"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS                                      \
+       "netdev=eth0\0"                                                 \
+       "ipaddr=192.168.1.10\0"                                         \
+       "serverip=192.168.1.3\0"                                        \
+       "netmask=255.255.255.0\0"                                       \
+        "hostname=bc3450\0"                                             \
+       "rootpath=/opt/eldk/ppc_6xx\0"                                  \
+        "kernel_addr=fc0a0000\0"                                       \
+        "ramdisk_addr=fc1c0000\0"                                      \
+       "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
+       "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
+               "nfsroot=$(serverip):$(rootpath)\0"                     \
+        "ideargs=setenv bootargs root=/dev/hda2 ro\0"                  \
+       "addip=setenv bootargs $(bootargs) "                            \
+               "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
+               ":$(hostname):$(netdev):off panic=1\0"                  \
+       "addcons=setenv bootargs $(bootargs) "                          \
+               "console=ttyS0,$(baudrate) console=tty0\0"              \
+       "flash_self=run ramargs addip addcons;"                         \
+               "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
+       "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0"   \
+       "net_nfs=tftp 200000 $(bootfile); "                             \
+               "run nfsargs addip addcons; bootm\0"                    \
+        "ide_nfs=run nfsargs addip addcons; "                          \
+                "disk 200000 0:1; bootm\0"                             \
+        "ide_ide=run ideargs addip addcons; "                          \
+                "disk 200000 0:1; bootm\0"                             \
+       "usb_self=run usbload; run ramargs addip addcons; "             \
+               "bootm 200000 400000\0"                                 \
+       "usbload=usb reset; usb scan; usbboot 200000 0:1; "             \
+               "usbboot 400000 0:2\0"                                  \
+       "bootfile=uImage\0"                                             \
+       "load=tftp 200000 $(u-boot)\0"                                  \
+       "u-boot=u-boot.bin\0"                                           \
+       "update=protect off FC000000 FC05FFFF;"                         \
+               "erase FC000000 FC05FFFF;"                              \
+               "cp.b 200000 FC000000 $(filesize);"                     \
+               "protect on FC000000 FC05FFFF\0"                        \
+       ""
+
+#define CONFIG_BOOTCOMMAND     "run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133               /* define for 133MHz speed */
+
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet 
+ * hasn't been tested with a IPB Bus Clock of 66 MHz.
+ */
+#if defined(CFG_IPBSPEED_133)
+# define CFG_PCISPEED_66                       /* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C                1       /* I2C with hardware support */
+#define CFG_I2C_MODULE         2       /* Select I2C module #2 */
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CFG_I2C_SPEED          100000 /* 100 kHz */
+#define CFG_I2C_SLAVE          0x7F
+
+/*
+ * EEPROM configuration for I²C EEPROM M24C32 
+ * M24C64 should work also. For other EEPROMs config should be verified.
+ * 
+ * The TQM5200 module may hold an EEPROM at address 0x50.
+ */
+#define CFG_I2C_EEPROM_ADDR            0x50    /* 1010000x (TQM) */
+#define CFG_I2C_EEPROM_ADDR_LEN                2
+#define CFG_EEPROM_PAGE_WRITE_BITS     5       /* =32 Bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
+
+/*
+ * RTC configuration
+ */
+#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
+# define CONFIG_RTC_M41T11     1
+# define CFG_I2C_RTC_ADDR      0x68
+#else
+# define CONFIG_RTC_MPC5200    1       /* use MPC5200 internal RTC */
+# define CONFIG_BOARD_EARLY_INIT_R
+#endif
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE         TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver if no module variant is spezified */
+#define CFG_FLASH_CFI          1       /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER   1       /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST   { CFG_BOOTCS_START }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_SIZE         0x04000000 /* 64 MByte */
+#define CFG_MAX_FLASH_SECT     512     /* max num of sects on one chip */
+#undef CFG_FLASH_USE_BUFFER_WRITE      /* not supported yet for AMD */
+
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR           (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
+#else  /* CFG_LOWBOOT */
+#define CFG_ENV_ADDR           (CFG_FLASH_BASE + 0x00060000)
+#endif /* CFG_LOWBOOT */
+#define CFG_MAX_FLASH_BANKS    1       /* max num of flash banks
+                                          (= chip selects) */
+#define CFG_FLASH_ERASE_TOUT   240000  /* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT   500     /* Flash Write Timeout (in ms)  */
+
+/* Dynamic MTD partition support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT         "nor0=TQM5200-0"
+#define MTDPARTS_DEFAULT       "mtdparts=TQM5200-0:640k(firmware),"    \
+                                               "1408k(kernel),"        \
+                                               "2m(initrd),"           \
+                                               "4m(small-fs),"         \
+                                               "16m(big-fs),"          \
+                                               "8m(misc)"
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH    1
+#define CFG_ENV_SIZE           0x10000
+#define CFG_ENV_SECT_SIZE      0x20000
+#define CFG_ENV_ADDR_REDUND    (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define        CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR               0xF0000000
+#define CFG_SDRAM_BASE         0x00000000
+#define CFG_DEFAULT_MBAR       0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR      MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+# define CFG_INIT_RAM_END      MPC5XXX_SRAM_POST_SIZE
+#else
+# define CFG_INIT_RAM_END      MPC5XXX_SRAM_SIZE
+#endif /*CONFIG_POST*/
+
+#define CFG_GBL_DATA_SIZE      128     /* Bytes reserved for initial data  */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE       TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT         1
+#endif
+
+#define CFG_MONITOR_LEN                (384 << 10) /* Reserve 384 kB for Monitor   */
+#define CFG_MALLOC_LEN         (128 << 10) /* Reserve 128 kB for malloc()  */
+#define CFG_BOOTMAPSZ          (8 << 20)   /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ *
+ * Define CONFIG_FEC10MBIT to force FEC at 10MBIT
+ */
+#define CONFIG_MPC5xxx_FEC     1
+#undef CONFIG_FEC_10MBIT
+#define CONFIG_PHY_ADDR                0x00
+
+/*
+ * GPIO configuration on BC3450
+ *
+ *  PSC1:   UART1 (Service-UART)         [0x xxxxxxx4]
+ *  PSC2:   UART2                        [0x xxxxxx4x]
+ *    or:   AC/97 if CONFIG_BC3450_AC97  [0x xxxxxx2x]
+ *  PSC3:   USB2                         [0x xxxxx1xx]
+ *  USB:    UART4(ext.)/UART5(int.)      [0x xxxx2xxx]
+ *            (this has to match 
+ *            CONFIG_USB_CONFIG which is
+ *            used by usb_ohci.c to set 
+ *            the USB ports)
+ *  Eth:    10/100Mbit Ethernet          [0x xxx0xxxx]
+ *            (this is reset to '5' 
+ *            in FEC driver: fec.c)
+ *  PSC6:   UART6 (int. to PS/2 contr.)  [0x xx5xxxxx]
+ *  ATA/CS: ???                          [0x x1xxxxxx]
+ *          FIXME! UM Fig 2-10 suggests  [0x x0xxxxxx]
+ *  CS1:    Use Pin gpio_wkup_6 as second
+ *          SDRAM chip select (mem_cs1)
+ *  Timer:  CAN2 / SPI
+ *  I2C:    CAN1 / I²C2                  [0x bxxxxxxx]
+ */
+#ifdef CONFIG_BC3450_AC97
+# define CFG_GPS_PORT_CONFIG   0xb1502124
+#else /* PSC2=UART2 */
+# define CFG_GPS_PORT_CONFIG   0xb1502144
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                           /* undef to save memory     */
+#define CFG_PROMPT             "=> "           /* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE             1024            /* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE             256             /* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size  */
+#define CFG_MAXARGS            16              /* max no of command args   */
+#define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Arg. Buffer Size    */
+
+#define CFG_ALT_MEMTEST                                /* Enable an alternative,   */
+                                               /*  more extensive mem test */
+
+#define CFG_MEMTEST_START      0x00100000      /* memtest works on         */
+#define CFG_MEMTEST_END                0x00f00000      /* 1 ... 15 MB in DRAM      */
+
+#define CFG_LOAD_ADDR          0x100000        /* default load address     */
+
+#define CFG_HZ                 1000            /* dec freq: 1ms ticks      */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+# define CFG_HID0_INIT         HID0_ICE | HID0_ICFI
+# define CFG_HID0_FINAL                HID0_ICE
+#else
+# define CFG_HID0_INIT         0
+# define CFG_HID0_FINAL                0
+#endif
+
+#define CFG_BOOTCS_START       CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE                CFG_FLASH_SIZE
+#ifdef CFG_PCISPEED_66
+# define CFG_BOOTCS_CFG                0x0008DF30      /* for pci_clk  = 66 MHz */
+#else
+# define CFG_BOOTCS_CFG                0x0004DF30      /* for pci_clk = 33 MHz  */
+#endif
+#define CFG_CS0_START          CFG_FLASH_BASE
+#define CFG_CS0_SIZE           CFG_FLASH_SIZE
+
+/* automatic configuration of chip selects */
+#ifdef CONFIG_TQM5200
+# define CONFIG_LAST_STAGE_INIT
+#endif /* CONFIG_TQM5200 */
+
+/*
+ * SRAM - Do not map below 2 GB in address space, because this area is used
+ * for SDRAM autosizing.
+ */
+#ifdef CONFIG_TQM5200
+# define CFG_CS2_START         0xE5000000
+# define CFG_CS2_SIZE          0x100000        /* 1 MByte */
+# define CFG_CS2_CFG           0x0004D930
+#endif /* CONFIG_TQM5200 */
+
+/*
+ * Grafic controller - Do not map below 2 GB in address space, because this
+ * area is used for SDRAM autosizing.
+ */
+#ifdef CONFIG_TQM5200
+# define SM501_FB_BASE         0xE0000000
+# define CFG_CS1_START         (SM501_FB_BASE)
+# define CFG_CS1_SIZE          0x4000000       /* 64 MByte */
+# define CFG_CS1_CFG           0x8F48FF70
+# define SM501_MMIO_BASE       CFG_CS1_START + 0x03E00000
+#endif /* CONFIG_TQM5200 */
+
+#define CFG_CS_BURST           0x00000000
+#define CFG_CS_DEADCYCLE       0x33333311      /* 1 dead cycle for     */
+                                               /*  flash and SM501     */
+
+#define CFG_RESET_ADDRESS      0xff000000
+
+/*
+ * USB stuff
+ */
+#define CONFIG_USB_CLOCK       0x0001BBBB
+#define CONFIG_USB_CONFIG      0x00002000      /* we're using Port 2   */
+
+/*
+ * IDE/ATA stuff Supports IDE harddisk
+ */
+#undef CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT           /* Direct IDE     not supported */
+#undef CONFIG_IDE_LED                  /* LED for ide    not supported */
+
+#define CONFIG_IDE_RESET               /* reset for ide      supported */
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS         1       /* max. 1 IDE bus               */
+#define CFG_IDE_MAXDEVICE      2       /* max. 2 drives per IDE bus    */
+
+#define CFG_ATA_IDE0_OFFSET    0x0000
+
+#define CFG_ATA_BASE_ADDR      MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET    (0x0060)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET     (CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET     (0x005C)
+
+/* Interval between registers */
+#define CFG_ATA_STRIDE         4
+
+#endif /* __CONFIG_H */

diff --git a/include/configs/BMW.h b/include/configs/BMW.h
index 050054d274c7ee3dd2b22fceb8b7dfe0a3dcdd6d..3bd43d836930aaaee01924ea3bc3d367b663cec6 100644 (file)
--- a/include/configs/BMW.h
+++ b/include/configs/BMW.h
@@ -69,6 +69,10 @@
                                CFG_CMD_DOC     | \
                                CFG_CMD_ELF     | \
                                0 )
+
+/* CFG_CMD_DOC required legacy NAND support */
+#define CFG_NAND_LEGACY
+
 #if 0
 #define CONFIG_COMMANDS                (CONFIG_CMD_DFL | CFG_CMD_DHCP | \
                                 CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE)

diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index ffe89cb78fc990f3be96dfe3592974d5be7325f6..7ec4599ebb5df33c8916ce3797ddb3c00f2d6b5e 100644 (file)
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -193,6 +193,8 @@
  */
 #define CFG_NAND0_BASE 0xFF400000
 #define CFG_NAND1_BASE 0xFF000000
+#define CFG_NAND_BASE_LIST     { CFG_NAND0_BASE }
+#define NAND_BIG_DELAY_US      25
 
 /* For CATcenter there is only NAND on the module */
 #define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices           */
@@ -218,9 +220,9 @@
 #define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 
 
-#define NAND_DISABLE_CE(nand) do \
+#define MACRO_NAND_DISABLE_CE(nandptr) do \
 { \
-       switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+       switch((unsigned long)nandptr) \
        { \
            case CFG_NAND0_BASE: \
                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
@@ -231,9 +233,9 @@
        } \
 } while(0)
 
-#define NAND_ENABLE_CE(nand) do \
+#define MACRO_NAND_ENABLE_CE(nandptr) do \
 { \
-       switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+       switch((unsigned long)nandptr) \
        { \
            case CFG_NAND0_BASE: \
                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
@@ -244,8 +246,7 @@
        } \
 } while(0)
 
-
-#define NAND_CTL_CLRALE(nandptr) do \
+#define MACRO_NAND_CTL_CLRALE(nandptr) do \
 { \
        switch((unsigned long)nandptr) \
        { \
@@ -258,7 +259,7 @@
        } \
 } while(0)
 
-#define NAND_CTL_SETALE(nandptr) do \
+#define MACRO_NAND_CTL_SETALE(nandptr) do \
 { \
        switch((unsigned long)nandptr) \
        { \
@@ -271,7 +272,7 @@
        } \
 } while(0)
 
-#define NAND_CTL_CLRCLE(nandptr) do \
+#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
 { \
        switch((unsigned long)nandptr) \
        { \
@@ -284,7 +285,7 @@
        } \
 } while(0)
 
-#define NAND_CTL_SETCLE(nandptr) do { \
+#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
        switch((unsigned long)nandptr) { \
        case CFG_NAND0_BASE: \
                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \

diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index 6025886e3eaf63eee1a03871e402862e31dc11d8..1cca2859f4ba8dc4f2d45a10244619490825c0cc 100644 (file)
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -81,6 +81,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
 #define CONFIG_SDRAM_BANK0     1       /* init onboard SDRAM bank 0    */

diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index 756bb8ceacaceed0b47e7c61e472c0506b963ca9..56fd9a6d356687b2b7d7427470a2eee5438e2d3c 100644 (file)
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -143,8 +143,9 @@
 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 #define CFG_PCI_SUBSYS_DEVICEID 0x040b  /* PCI Device ID: CPCI-2DP      */
 #define CFG_PCI_CLASSCODE       0x0280 /* PCI Class Code: Network/Other*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+
+#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 #define CFG_PCI_PTM2LA 0xef000000      /* point to internal regs + PB0/1 */
 #define CFG_PCI_PTM2MS  0xff000001      /* 16MB, enable                  */
@@ -250,14 +251,15 @@
 
 #define CFG_INIT_RAM_ADDR      0x40000000  /* use data cache                  */
 #define CFG_INIT_RAM_END       0x2000  /* End of used area in RAM             */
-#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_GBL_DATA_SIZE       128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * GPIO definitions
  */
 #define CFG_EEPROM_WP          (0x80000000 >> 13)   /* GPIO13 */
+#define CFG_SELF_RST           (0x80000000 >> 14)   /* GPIO14 */
 #define CFG_PB_LED             (0x80000000 >> 16)   /* GPIO16 */
 #define CFG_INTA_FAKE          (0x80000000 >> 23)   /* GPIO23 */
 

diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index d49020db76f01d0df5081d406f25d61de7ddffb9..047e2f1eef9cc57f7a5ba6517de8cf828d2f358b 100644 (file)
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -79,6 +79,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
 #define CONFIG_SDRAM_BANK0     1       /* init onboard SDRAM bank 0    */
@@ -151,8 +153,8 @@
 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */

diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index 13dbe80daf92dcc8b9f7c56dca422baeeaabb6b7..d756f447f7faed06880c80c343de219f93b836de 100644 (file)
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -100,6 +100,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
 #define CONFIG_SDRAM_BANK0     1       /* init onboard SDRAM bank 0    */
@@ -178,8 +180,8 @@
 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */

diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index aaaafa94fd7e106cdf91cd5e221133f8519486d5..852d94a410ac8a45de3b0a8daaf110fa0de9559d 100644 (file)
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -87,6 +87,9 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
+
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
 #define CONFIG_SDRAM_BANK0     1       /* init onboard SDRAM bank 0    */
@@ -161,8 +164,8 @@
 #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405      */
 #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A   */
 #define CFG_PCI_CLASSCODE      0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS 0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 #define CFG_PCI_PTM1PCI 0x00000000     /* Host: use this pci address   */
 #define CFG_PCI_PTM2LA 0xffc00000      /* point to flash               */
 #define CFG_PCI_PTM2MS 0xffc00001      /* 4MB, enable                  */

diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index 5cd9aba9e53ddb7e263525c09e8057620d6ecff2..2260327c3f855ba88a3429695bae0b7c875abe20 100644 (file)
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -98,6 +98,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
 #define CONFIG_SDRAM_BANK0     1       /* init onboard SDRAM bank 0    */
@@ -183,8 +185,8 @@
 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */

diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index 8bfd0ee820f0674463470c6ecfa20725d9927ef8..244e45a7505d69af9f3d805127c2ab73738d9970 100644 (file)
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -57,7 +57,7 @@
 
 #define CONFIG_CPCI750         1       /* this is an CPCI750 board     */
 
-#define CONFIG_BAUDRATE                9600    /* console baudrate = 9600      */
+#define CONFIG_BAUDRATE                9600    /* console baudrate = 9600      */
 
 #undef CONFIG_ECC                      /* enable ECC support */
 
@@ -70,10 +70,12 @@
 #define CONFIG_IDENT_STRING    "Marvell 64360 + IBM750FX"
 
 /*#define CFG_HUSH_PARSER*/
-#undef CFG_HUSH_PARSER
+#define CFG_HUSH_PARSER
 
 #define CFG_PROMPT_HUSH_PS2    "> "
 
+#define CFG_AUTO_COMPLETE 1
+
 /* Define which ETH port will be used for connecting the network */
 #define CFG_ETH_PORT           ETH_0
 
@@ -82,19 +84,19 @@
  * for your console driver.
  *
  * what to do:
- * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
+ * to use the DUART, undef CONFIG_MPSC.         If you have hacked a serial
  * cable onto the second DUART channel, change the CFG_DUART port from 1
  * to 0 below.
  *
  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
  * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
  */
-#define        CONFIG_MPSC
+#define CONFIG_MPSC
 #define CONFIG_MPSC_PORT       0
 
 /* to change the default ethernet port, use this define (options: 0, 1, 2) */
 #define CONFIG_NET_MULTI
-#define MV_ETH_DEVS             1
+#define MV_ETH_DEVS            1
 #define CONFIG_ETHER_PORT      0
 
 #undef CONFIG_ETHER_PORT_MII   /* use RMII */
@@ -116,38 +118,38 @@
 
 #define CONFIG_SERIAL          "AA000001"
 #define CONFIG_SERVERIP                "10.0.0.79"
-#define CONFIG_ROOTPATH                "/export/nfs_cpci750/%s"
+#define CONFIG_ROOTPATH                "/export/nfs_cpci750/%s"
 
 #define CONFIG_TESTDRAMDATA    y
-#define CONFIG_TESTDRAMADDRESS  n
+#define CONFIG_TESTDRAMADDRESS n
 #define CONFIG_TESETDRAMWALK   n
 
 /* ----------------------------------------------------------------------------- */
 
 
-#define CONFIG_LOADS_ECHO      0       /* echo off for serial download */
-#define        CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes       */
+#define CONFIG_LOADS_ECHO      0       /* echo off for serial download */
+#define CFG_LOADS_BAUD_CHANGE          /* allow baudrate changes       */
 
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
-#undef CONFIG_ALTIVEC                  /* undef to disable             */
+#undef CONFIG_ALTIVEC                  /* undef to disable             */
 
 #define CONFIG_BOOTP_MASK      (CONFIG_BOOTP_DEFAULT | \
                                 CONFIG_BOOTP_BOOTFILESIZE)
 
 
-#define CONFIG_COMMANDS        (CONFIG_CMD_DFL    \
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL           \
                         | CFG_CMD_ASKENV  \
-                        | CFG_CMD_I2C     \
+                        | CFG_CMD_I2C     \
                         | CFG_CMD_CACHE   \
                         | CFG_CMD_EEPROM  \
-                        | CFG_CMD_PCI     \
+                        | CFG_CMD_PCI     \
                         | CFG_CMD_ELF     \
                         | CFG_CMD_DATE    \
-                        | CFG_CMD_NET     \
-                        | CFG_CMD_PING    \
-                        | CFG_CMD_IDE     \
-                        | CFG_CMD_FAT     \
-                        | CFG_CMD_EXT2    \
+                        | CFG_CMD_NET     \
+                        | CFG_CMD_PING    \
+                        | CFG_CMD_IDE     \
+                        | CFG_CMD_FAT     \
+                        | CFG_CMD_EXT2    \
                                        )
 
 #define CONFIG_DOS_PARTITION
@@ -155,28 +157,40 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CONFIG_USE_CPCIDVI
+
+#ifdef CONFIG_USE_CPCIDVI
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_CT69000
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_I8042_KBD
+#define CFG_ISA_IO 0
+#endif
+
 /*
  * Miscellaneous configurable options
  */
 #define CFG_I2C_EEPROM_ADDR_LEN 2
 #define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_SPEED   80000          /* I2C speed default */
+#define CFG_I2C_SPEED  80000           /* I2C speed default */
 
 #define CFG_GT_DUAL_CPU                        /* also for JTAG even with one cpu */
-#define        CFG_LONGHELP                    /* undef to save memory         */
-#define        CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
+#define CFG_LONGHELP                   /* undef to save memory         */
+#define CFG_PROMPT     "=> "           /* Monitor Command Prompt       */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define        CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
+#define CFG_CBSIZE     1024            /* Console I/O Buffer Size      */
 #else
-#define        CFG_CBSIZE      256             /* Console I/O Buffer Size      */
+#define CFG_CBSIZE     256             /* Console I/O Buffer Size      */
 #endif
-#define        CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define        CFG_MAXARGS     16              /* max number of command args   */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS    16              /* max number of command args   */
 #define CFG_BARGSIZE   CFG_CBSIZE      /* Boot Argument Buffer Size    */
 
 /*#define CFG_MEMTEST_START    0x00400000*/    /* memtest works on     */
 /*#define CFG_MEMTEST_END              0x00C00000*/    /* 4 ... 12 MB in DRAM  */
-/*#define CFG_MEMTEST_END              0x07c00000*/    /* 4 ... 124 MB in DRAM */
+/*#define CFG_MEMTEST_END              0x07c00000*/    /* 4 ... 124 MB in DRAM */
 
 /*
 #define CFG_DRAM_TEST
@@ -184,21 +198,21 @@
  *   CFG_DRAM_TEST - enables the following tests.
  *
  *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
- *                        Environment variable 'test_dram_data' must be
- *                        set to 'y'.
+ *                       Environment variable 'test_dram_data' must be
+ *                       set to 'y'.
  *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
- *                        addressable. Environment variable
- *                        'test_dram_address' must be set to 'y'.
+ *                       addressable. Environment variable
+ *                       'test_dram_address' must be set to 'y'.
  *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
- *                        This test takes about 6 minutes to test 64 MB.
- *                        Environment variable 'test_dram_walk' must be
- *                        set to 'y'.
+ *                       This test takes about 6 minutes to test 64 MB.
+ *                       Environment variable 'test_dram_walk' must be
+ *                       set to 'y'.
  */
 #define CFG_DRAM_TEST
 #if defined(CFG_DRAM_TEST)
 #define CFG_MEMTEST_START              0x00400000      /* memtest works on     */
 /*#define CFG_MEMTEST_END              0x00C00000*/    /* 4 ... 12 MB in DRAM  */
-#define CFG_MEMTEST_END                0x07c00000      /* 4 ... 124 MB in DRAM */
+#define CFG_MEMTEST_END                0x07c00000      /* 4 ... 124 MB in DRAM */
 #define CFG_DRAM_TEST_DATA
 #define CFG_DRAM_TEST_ADDRESS
 #define CFG_DRAM_TEST_WALK
@@ -207,10 +221,10 @@
 #define CONFIG_DISPLAY_MEMMAP          /* at the end of the bootprocess show the memory map */
 #undef CFG_DISPLAY_DIMM_SPD_CONTENT    /* show SPD content during boot */
 
-#define        CFG_LOAD_ADDR           0x00300000      /* default load address */
+#define CFG_LOAD_ADDR          0x00300000      /* default load address */
 
-#define        CFG_HZ                  1000            /* decr freq: 1ms ticks */
-#define CFG_BUS_HZ             133000000       /* 133 MHz (CPU = 5*Bus = 666MHz)               */
+#define CFG_HZ                 1000            /* decr freq: 1ms ticks */
+#define CFG_BUS_HZ             133000000       /* 133 MHz (CPU = 5*Bus = 666MHz)               */
 #define CFG_BUS_CLK            CFG_BUS_HZ
 
 #define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200, 230400 }
@@ -237,7 +251,7 @@
  * To an unused memory region. The stack will remain in cache until RAM
  * is initialized
 */
-#undef    CFG_INIT_RAM_LOCK
+#undef   CFG_INIT_RAM_LOCK
 /* #define CFG_INIT_RAM_ADDR   0x40000000*/ /* unused memory region */
 /* #define CFG_INIT_RAM_ADDR   0xfba00000*/ /* unused memory region */
 #define CFG_INIT_RAM_ADDR      0xf1080000 /* unused memory region */
@@ -247,7 +261,7 @@
 
 #define RELOCATE_INTERNAL_RAM_ADDR
 #ifdef RELOCATE_INTERNAL_RAM_ADDR
-/*#define CFG_INTERNAL_RAM_ADDR        0xfba00000*/
+/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/
 #define CFG_INTERNAL_RAM_ADDR  0xf1080000
 #endif
 
@@ -256,28 +270,34 @@
  * (Set up by the startup code)
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
-#define        CFG_SDRAM_BASE          0x00000000
+#define CFG_SDRAM_BASE         0x00000000
 /* Dummies for BAT 4-7 */
-#define        CFG_SDRAM1_BASE         0x10000000      /* each 256 MByte */
-#define        CFG_SDRAM2_BASE         0x20000000
-#define        CFG_SDRAM3_BASE         0x30000000
-#define        CFG_SDRAM4_BASE         0x40000000
+#define CFG_SDRAM1_BASE                0x10000000      /* each 256 MByte */
+#define CFG_SDRAM2_BASE                0x20000000
+#define CFG_SDRAM3_BASE                0x30000000
+#define CFG_SDRAM4_BASE                0x40000000
 #define CFG_RESET_ADDRESS      0xfff00100
-#define        CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_LEN                (256 << 10)     /* Reserve 256 kB for Monitor */
 #define CFG_MONITOR_BASE       0xfff00000
-#define        CFG_MALLOC_LEN          (128 << 10)     /* Reserve 256 kB for malloc */
+#define CFG_MALLOC_LEN         (128 << 10)     /* Reserve 256 kB for malloc */
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
 
+#define CFG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI          1          /* Flash is CFI conformant           */
-#define CFG_MAX_FLASH_SECT     128        /* max number of sectors on one chip */
-#define CFG_MAX_FLASH_BANKS    4          /* max number of memory banks        */
-#define CFG_FLASH_INCREMENT    0x01000000 /* there is only one bank            */
 #define CFG_FLASH_PROTECTION   1          /* use hardware protection           */
 #define CFG_FLASH_USE_BUFFER_WRITE 1      /* use buffered writes (20x faster)  */
-#define CFG_FLASH_BASE         0xfc000000 /* start of flash banks              */
+#define CFG_FLASH_BASE         0xfc000000 /* start of flash banks              */
+#define CFG_MAX_FLASH_BANKS    4          /* max number of memory banks        */
+#define CFG_FLASH_INCREMENT    0x01000000 /* size of  flash bank               */
+#define CFG_MAX_FLASH_SECT     128        /* max number of sectors on one chip */
+#define CFG_FLASH_BANKS_LIST  { CFG_FLASH_BASE,                                   \
+                               CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT,    \
+                               CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT,    \
+                               CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT }
+#define CFG_FLASH_EMPTY_INFO   1          /* show if bank is empty             */
 
 /* areas to map different things with the GT in physical space */
 #define CFG_DRAM_BANKS         4
@@ -288,20 +308,20 @@
 /* Peripheral Device section */
 
 /*******************************************************/
-/* We have on the cpci750 Board :                      */
-/* GT-Chipset Register Area                            */
-/* GT-Chipset internal SRAM 256k                       */
-/* SRAM on external device module                      */
-/* Real time clock on external device module           */
-/* dobble UART on external device module               */
-/* Data flash on external device module                */
-/* Boot flash on external device module                */
+/* We have on the cpci750 Board :                     */
+/* GT-Chipset Register Area                           */
+/* GT-Chipset internal SRAM 256k                      */
+/* SRAM on external device module                     */
+/* Real time clock on external device module          */
+/* dobble UART on external device module              */
+/* Data flash on external device module                       */
+/* Boot flash on external device module                       */
 /*******************************************************/
 #define CFG_DFL_GT_REGS                0x14000000                              /* boot time GT_REGS */
-#define  CFG_CPCI750_RESET_ADDR        0x14000000                              /* After power on Reset the CPCI750 is here */
+#define         CFG_CPCI750_RESET_ADDR 0x14000000                              /* After power on Reset the CPCI750 is here */
 
-#undef         MARVEL_STANDARD_CFG
-#ifndef        MARVEL_STANDARD_CFG
+#undef MARVEL_STANDARD_CFG
+#ifndef                MARVEL_STANDARD_CFG
 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
 #define CFG_GT_REGS            0xf1000000                              /* GT Registers will be mapped here */
 /*#define CFG_DEV_BASE         0xfc000000*/                            /* GT Devices CS start here */
@@ -313,11 +333,11 @@
 #define CFG_DEV2_SPACE         0xfe000000                              /* DEV_CS2 flash 3     */
 #define CFG_DEV3_SPACE         0xf0000000                              /* DEV_CS3 nvram/can   */
 
-#define CFG_BOOT_SIZE          _16M                                    /* cpci750 flash 0     */
-#define CFG_DEV0_SIZE          _16M                                    /* cpci750 flash 1     */
-#define CFG_DEV1_SIZE          _16M                                    /* cpci750 flash 2     */
-#define CFG_DEV2_SIZE          _16M                                    /* cpci750 flash 3     */
-#define CFG_DEV3_SIZE          _16M                                    /* cpci750 nvram/can   */
+#define CFG_BOOT_SIZE          _16M                                    /* cpci750 flash 0     */
+#define CFG_DEV0_SIZE          _16M                                    /* cpci750 flash 1     */
+#define CFG_DEV1_SIZE          _16M                                    /* cpci750 flash 2     */
+#define CFG_DEV2_SIZE          _16M                                    /* cpci750 flash 3     */
+#define CFG_DEV3_SIZE          _16M                                    /* cpci750 nvram/can   */
 
 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
 #endif
@@ -326,22 +346,22 @@
 #define CFG_DEV0_PAR           0x8FDFFFFF                              /* 16 bit flash */
 #define CFG_DEV1_PAR           0x8FDFFFFF                              /* 16 bit flash */
 #define CFG_DEV2_PAR           0x8FDFFFFF                              /* 16 bit flash */
-#define CFG_DEV3_PAR           0x8FCFFFFF                              /* nvram/can    */
+#define CFG_DEV3_PAR           0x8FCFFFFF                              /* nvram/can    */
 #define CFG_BOOT_PAR           0x8FDFFFFF                              /* 16 bit flash */
 
-       /*   c    4    a      8     2     4    1      c         */
-       /* 33 22|2222|22 22|111 1|11 11|1 1  |    |             */
+       /*   c    4    a      8     2     4    1      c         */
+       /* 33 22|2222|22 22|111 1|11 11|1 1  |    |             */
        /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210       */
        /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100       */
        /*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4        */
 
 
 /* MPP Control MV64360 Appendix P P. 632*/
-#define CFG_MPP_CONTROL_0      0x00002222      /*                                   */
-#define CFG_MPP_CONTROL_1      0x11110000      /*                                   */
-#define CFG_MPP_CONTROL_2      0x11111111      /*                                   */
-#define CFG_MPP_CONTROL_3      0x00001111      /*                                   */
-/* #define CFG_SERIAL_PORT_MUX 0x00000102*/    /*                                   */
+#define CFG_MPP_CONTROL_0      0x00002222      /*                                   */
+#define CFG_MPP_CONTROL_1      0x11110000      /*                                   */
+#define CFG_MPP_CONTROL_2      0x11111111      /*                                   */
+#define CFG_MPP_CONTROL_3      0x00001111      /*                                   */
+/* #define CFG_SERIAL_PORT_MUX 0x00000102*/    /*                                   */
 
 
 #define CFG_GPP_LEVEL_CONTROL  0xffffffff      /* 1111 1111 1111 1111 1111 1111 1111 1111*/
@@ -358,12 +378,12 @@
                                   ECC disable
                                   non registered DRAM */
                                /* 31:26   25:22  21:20 19 18 17 16 */
-                               /* 100001 0000   010   0   0   0  0 */
+                               /* 100001 0000   010   0   0   0  0 */
                                /* refresh_count=0x400
                                   phisical interleaving disable
                                   virtual interleaving enable */
                                /* 15 14 13:0 */
-                               /* 0  1  0x400 */
+                               /* 0  1  0x400 */
 # define CFG_SDRAM_CONFIG      0x58200400      /* 0x1400  copied from Dink32 bzw. VxWorks*/
 
 
@@ -372,14 +392,14 @@
  *-----------------------------------------------------------------------
  */
 
-#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+#define PCI_HOST_ADAPTER 0             /* configure ar pci adapter     */
+#define PCI_HOST_FORCE 1               /* configure as pci host        */
+#define PCI_HOST_AUTO  2               /* detected via arbiter enable  */
 
-#define CONFIG_PCI                      /* include pci support          */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
-#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
-#define CONFIG_PCI_SCAN_SHOW            /* show devices on bus          */
+#define CONFIG_PCI                     /* include pci support          */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function     */
+#define CONFIG_PCI_PNP                 /* do pci plug-and-play         */
+#define CONFIG_PCI_SCAN_SHOW           /* show devices on bus          */
 
 /* PCI MEMORY MAP section */
 #define CFG_PCI0_MEM_BASE      0x80000000
@@ -401,6 +421,8 @@
 #define CFG_PCI1_IO_SPACE      (CFG_PCI1_IO_BASE)
 #define CFG_PCI1_IO_SPACE_PCI  0x00000000
 
+#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
+
 #if defined (CONFIG_750CX)
 #define CFG_PCI_IDSEL 0x0
 #else
@@ -411,21 +433,21 @@
  * IDE/ATA stuff
  *-----------------------------------------------------------------------
  */
-#undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
-#define CONFIG_IDE_RESET                /* no reset for ide supported   */
-#define CONFIG_IDE_PREINIT              /* check for units              */
+#undef CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
+#undef CONFIG_IDE_LED                  /* no led for ide supported     */
+#define CONFIG_IDE_RESET               /* no reset for ide supported   */
+#define CONFIG_IDE_PREINIT             /* check for units              */
 
-#define CFG_IDE_MAXBUS          2               /* max. 1 IDE busses    */
-#define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
+#define CFG_IDE_MAXBUS         2               /* max. 1 IDE busses    */
+#define CFG_IDE_MAXDEVICE      (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR       0
-#define CFG_ATA_IDE0_OFFSET     0
-#define CFG_ATA_IDE1_OFFSET     0
+#define CFG_ATA_BASE_ADDR      0
+#define CFG_ATA_IDE0_OFFSET    0
+#define CFG_ATA_IDE1_OFFSET    0
 
-#define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O                  */
-#define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses  */
-#define CFG_ATA_ALT_OFFSET      0x0000  /* Offset for alternate registers       */
+#define CFG_ATA_DATA_OFFSET    0x0000  /* Offset for data I/O                  */
+#define CFG_ATA_REG_OFFSET     0x0000  /* Offset for normal register accesses  */
+#define CFG_ATA_ALT_OFFSET     0x0000  /* Offset for alternate registers       */
 
 
 /*----------------------------------------------------------------------
@@ -529,7 +551,7 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define        CFG_BOOTMAPSZ           (8<<20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ          (8<<20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
@@ -541,23 +563,23 @@
 #define CFG_FLASH_LOCK_TOUT    500     /* Timeout for Flash Lock (in ms) */
 
 #if 0
-#define        CFG_ENV_IS_IN_FLASH     0
-#define        CFG_ENV_SIZE            0x1000  /* Total Size of Environment Sector */
+#define CFG_ENV_IS_IN_FLASH    0
+#define CFG_ENV_SIZE           0x1000  /* Total Size of Environment Sector */
 #define CFG_ENV_SECT_SIZE      0x10000
 #define CFG_ENV_ADDR           0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
-/* #define CFG_ENV_ADDR    (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
+/* #define CFG_ENV_ADDR           (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
 #endif
 
 #define CFG_ENV_IS_IN_EEPROM   1       /* use EEPROM for environment vars */
 #define CFG_EEPROM_PAGE_WRITE_BITS 5
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CFG_I2C_EEPROM_ADDR     0x050
+#define CFG_I2C_EEPROM_ADDR    0x050
 #define CFG_ENV_OFFSET         0x200   /* environment starts at the beginning of the EEPROM */
 #define CFG_ENV_SIZE           0x600   /* 2048 bytes may be used for env vars*/
 
 #define CFG_NVRAM_BASE_ADDR    0xf0000000              /* NVRAM base address   */
 #define CFG_NVRAM_SIZE         (32*1024)               /* NVRAM size           */
-#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40)
+#define CFG_VXWORKS_MAC_PTR    (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40)
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
@@ -579,7 +601,7 @@
 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
 #define L2_INIT 0
 #else
-#define L2_INIT        (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+#define L2_INIT                (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
                        L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 #endif
 
@@ -590,9 +612,9 @@
  *
  * Boot Flags
  */
-#define        BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM  0x02            /* Software reboot                  */
 
-#define CFG_BOARD_ASM_INIT      1
+#define CFG_BOARD_ASM_INIT     1
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index a23d7e50b7bda3f2b64523ac223a08ec8a522291..9a98e5c191e183b5323731a4f9761d9eb12773e4 100644 (file)
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -189,6 +189,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 /*
  * Miscellaneous configurable options
  */

diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h
new file mode 100644 (file)
index 0000000..738763b
--- /dev/null
+++ b/include/configs/EP88x.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (C) 2005 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Embedded Planet EP88x boards.
+ * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC885
+
+#define CONFIG_EP88X                           /* Embedded Planet EP88x board  */
+
+#define CONFIG_BOARD_EARLY_INIT_F              /* Call board_early_init_f      */
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+#define        CONFIG_8xx_CONS_SMC1    1               /* Console is on SMC1           */
+#define CONFIG_BAUDRATE                38400
+
+#define        CONFIG_ETHER_ON_FEC1                    /* Enable Ethernet on FEC1      */
+#define        CONFIG_ETHER_ON_FEC2                    /* Enable Ethernet on FEC2      */
+#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
+#define CFG_DISCOVER_PHY
+#define FEC_ENET
+#endif /* CONFIG_FEC_ENET */
+
+#define CONFIG_8xx_OSCLK               10000000 /* 10 MHz oscillator on EXTCLK */
+#define CONFIG_8xx_CPUCLK_DEFAULT      100000000
+#define CFG_8xx_CPUCLK_MIN             40000000
+#define CFG_8xx_CPUCLK_MAX             133000000
+
+#define CONFIG_COMMANDS                (CONFIG_CMD_DFL  \
+                               | CFG_CMD_DHCP   \
+                               | CFG_CMD_IMMAP  \
+                               | CFG_CMD_MII    \
+                               | CFG_CMD_PING   \
+                               )
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY       5               /* Autoboot after 5 seconds     */
+#define CONFIG_BOOTCOMMAND     "bootm fe060000"        /* Autoboot command     */
+#define CONFIG_BOOTARGS                "root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)"
+
+#define CONFIG_BZIP2           /* Include support for bzip2 compressed images  */
+#undef CONFIG_WATCHDOG         /* Disable platform specific watchdog           */
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CFG_PROMPT             "=> "           /* Monitor Command Prompt       */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2    "> "
+#define CFG_LONGHELP                           /* #undef to save memory        */
+#define CFG_CBSIZE             256             /* Console I/O Buffer Size      */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)  /* Print Buffer Size */
+#define CFG_MAXARGS            16              /* Max number of command args   */
+#define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size    */
+
+#define CFG_LOAD_ADDR          0x400000        /* Default load address         */
+
+#define CFG_HZ                 1000            /* Decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * RAM configuration (note that CFG_SDRAM_BASE must be zero)
+ */
+#define CFG_SDRAM_BASE         0x00000000
+#define CFG_SDRAM_MAX_SIZE     0x08000000      /* Up to 128 Mbyte              */
+
+#define CFG_MAMR               0x00805000
+
+/*
+ * 4096        Up to 4096 SDRAM rows
+ * 1000        factor s -> ms
+ * 32  PTP (pre-divider from MPTPR)
+ * 4   Number of refresh cycles per period
+ * 64  Refresh cycle in ms per number of rows
+ */
+#define CFG_PTA_PER_CLK                ((4096 * 32 * 1000) / (4 * 64))
+
+#define CFG_MEMTEST_START      0x00100000      /* memtest works on             */
+#define CFG_MEMTEST_END                0x00500000      /* 1 ... 5 MB in SDRAM          */
+
+#define CFG_RESET_ADDRESS      0x09900000
+
+/*-----------------------------------------------------------------------
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
+
+#define CFG_MONITOR_BASE       TEXT_BASE
+#define CFG_MONITOR_LEN                (256 << 10)     /* Reserve 256 KB for Monitor   */
+#ifdef CONFIG_BZIP2
+#define CFG_MALLOC_LEN         (4096 << 10)    /* Reserve ~4 MB for malloc()   */
+#else
+#define CFG_MALLOC_LEN         (128 << 10)     /* Reserve 128 KB for malloc()  */
+#endif /* CONFIG_BZIP2 */
+
+/*-----------------------------------------------------------------------
+ * Flash organisation
+ */
+#define CFG_FLASH_BASE         0xFC000000
+#define CFG_FLASH_CFI                          /* The flash is CFI compatible  */
+#define CFG_FLASH_CFI_DRIVER                   /* Use common CFI driver        */
+#define CFG_MAX_FLASH_BANKS    1               /* Max number of flash banks    */
+#define CFG_MAX_FLASH_SECT     512             /* Max num of sects on one chip */
+
+/* Environment is in flash */
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE      0x20000         /* We use one complete sector   */
+#define CFG_ENV_ADDR           (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+
+#define CFG_OR0_PRELIM         0xFC000160
+#define CFG_BR0_PRELIM         (CFG_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V)
+
+#define        CFG_DIRECT_FLASH_TFTP
+
+/*-----------------------------------------------------------------------
+ * BCSR
+ */
+#define CFG_OR3_PRELIM         0xFF0005B0
+#define CFG_BR3_PRELIM         (0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V)
+
+#define CFG_BCSR               0xFA400000
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Map Register
+ */
+#define CFG_IMMR               0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR      CFG_IMMR
+#define CFG_INIT_RAM_END       0x2F00          /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE      128  /* Size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Configuration registers
+ */
+#ifdef CONFIG_WATCHDOG
+#define CFG_SYPCR              (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
+                                SYPCR_SWF  | SYPCR_SWE | SYPCR_SWRI | \
+                                SYPCR_SWP)
+#else
+#define CFG_SYPCR              (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
+                                SYPCR_SWF  | SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+#define CFG_SIUMCR             (SIUMCR_MLRC01 | SIUMCR_DBGC11)
+
+/* TBSCR - Time Base Status and Control Register */
+#define CFG_TBSCR              (TBSCR_TBF | TBSCR_TBE)
+
+/* PISCR - Periodic Interrupt Status and Control */
+#define CFG_PISCR              PISCR_PS
+
+/* SCCR - System Clock and reset Control Register */
+#define SCCR_MASK              SCCR_EBDF11
+#define CFG_SCCR               SCCR_RTSEL
+
+#define CFG_DER                0
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE     16      /* For all MPC8xx chips                 */
+
+/*-----------------------------------------------------------------------
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from flash     */
+#define BOOTFLAG_WARM          0x02    /* Software reboot                      */
+
+#endif /* __CONFIG_H */

diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index de8f7ae7112d6f02c19b202fcf83990324ce408d..6613f90a770075547700e0cfd12c08d5fc0023b6 100644 (file)
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -284,6 +284,8 @@
  */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 /*
  * Verbose help from command monitor.
  */

diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 131c21555d3e674fefddb0ccf6556611e56e9555..dc40ebc861d715e6a65684db2631761b12957404 100644 (file)
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -5,6 +5,9 @@
  * (C) Copyright 2005
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
+ * (C) Copyright 2006
+ * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -61,9 +64,13 @@
 
 #define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
 
+#define CONFIG_NET_MULTI       1
+#undef  CONFIG_HAS_ETH1
+
 #define CONFIG_MII             1       /* MII PHY management           */
-#define        CONFIG_PHY_ADDR         0       /* PHY address                  */
+#define CONFIG_PHY_ADDR                0       /* PHY address                  */
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
 
 #define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
 
@@ -79,6 +86,7 @@
 #else
 #define CONFIG_VIDEO_SM501_16BPP
 #endif
+#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VGA_AS_SINGLE_DEVICE
@@ -122,6 +130,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #undef  CONFIG_BZIP2    /* include support for bzip2 compressed images */
 #undef  CONFIG_WATCHDOG                        /* watchdog disabled            */
 
@@ -434,9 +444,12 @@
 #define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008
 #define CFG_FPGA_CTRL_CF_RESET  0x0040
 #define CFG_FPGA_CTRL_PS2_PWR   0x0080
-#define CFG_FPGA_CTRL_CF_PWR    0x0100      /* low active                    */
+#define CFG_FPGA_CTRL_CF_PWRN   0x0100      /* low active                    */
 #define CFG_FPGA_CTRL_CF_BUS_EN 0x0200
 #define CFG_FPGA_CTRL_LCD_CLK   0x7000      /* Mask for lcd clock            */
+#define CFG_FPGA_CTRL_OW_ENABLE 0x8000
+
+#define CFG_FPGA_STATUS_CF_DETECT 0x8000
 
 #define LCD_CLK_OFF             0x0000      /* Off                           */
 #define LCD_CLK_02083           0x1000      /* 2.083 MHz                     */

diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index eb627e881dd50883e826c5e78bebf3da1dfcb8f9..f84e356216bd9a0e941872f9739a01a7e29d9099 100644 (file)
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -135,6 +135,8 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
+#define CFG_NAND_LEGACY
+
 #define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices           */
 #define SECTORSIZE 512
 

diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index aaa44c539893aee2463cb9e98ac33c9e46d81413..29eb874dbf0e210586aedf350461a03b224152a1 100644 (file)
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -236,6 +236,7 @@
  */
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 
+#define CFG_NAND_LEGACY
 #define CFG_NAND0_BASE 0xE1000000
 
 #define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */

diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h
index 65056a21eee92a96e5c75e7cb6c39249c2f857e6..706bdb94f57ddd038ba9418b3a58c57a6e298b60 100644 (file)
--- a/include/configs/ISPAN.h
+++ b/include/configs/ISPAN.h
@@ -109,7 +109,6 @@
 #define CONFIG_COMMANDS                ( CONFIG_CMD_DFL  \
                                | CFG_CMD_ASKENV  \
                                | CFG_CMD_DHCP    \
-                               | CFG_CMD_ECHO    \
                                | CFG_CMD_IMMAP   \
                                | CFG_CMD_MII     \
                                | CFG_CMD_PING    \

diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index afba5c625e8b362dec68eda378006c62fec0a2d2..1152f838d9880682e3e7652bd76582e8bfb05d60 100644 (file)
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -56,7 +56,9 @@
  * 0x40000000 - 0x4fffffff - PCI Memory
  * 0x50000000 - 0x50ffffff - PCI IO Space
  */
-#define CONFIG_PCI             1
+#define CONFIG_PCI
+
+#if defined(CONFIG_PCI)
 #define CONFIG_PCI_PNP         1
 #define CONFIG_PCI_SCAN_SHOW   1
 
@@ -67,6 +69,8 @@
 #define CONFIG_PCI_IO_BUS      0x50000000
 #define CONFIG_PCI_IO_PHYS     CONFIG_PCI_IO_BUS
 #define CONFIG_PCI_IO_SIZE     0x01000000
+#define ADD_PCI_CMD            CFG_CMD_PCI
+#endif
 
 #define CFG_XLB_PIPELINING     1
 
@@ -76,8 +80,6 @@
 #define CFG_RX_ETH_BUFFER      8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X         1
 
-#define ADD_PCI_CMD            CFG_CMD_PCI
-
 #else  /* MPC5100 */
 
 #define CONFIG_MII             1
@@ -122,9 +124,13 @@
 #   define CFG_LOWBOOT16       1
 #endif
 #if (TEXT_BASE == 0xFF800000)          /* Boot low with  8 MB Flash */
+#if defined(CONFIG_LITE5200B)
+#   error CFG_LOWBOOT08 is incompatible with the Lite5200B
+#else
 #   define CFG_LOWBOOT         1
 #   define CFG_LOWBOOT08       1
 #endif
+#endif
 
 /*
  * Autobooting
@@ -160,8 +166,12 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133                /* define for 133MHz speed */
+#if defined(CONFIG_LITE5200B)
+#define CFG_IPBSPEED_133       /* define for 133MHz speed */
+#else
+#undef CFG_IPBSPEED_133        /* define for 133MHz speed */
 #endif
+#endif /* CONFIG_MPC5200 */
 /*
  * I2C configuration
  */
@@ -182,6 +192,20 @@
 /*
  * Flash configuration
  */
+#if defined(CONFIG_LITE5200B)
+#define CFG_FLASH_BASE         0xFE000000
+#define CFG_FLASH_SIZE         0x01000000
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR           (CFG_FLASH_BASE + 0x01760000 + 0x00800000)
+#else  /* CFG_LOWBOOT */
+#if defined(CFG_LOWBOOT08)
+# error CFG_LOWBOOT08 is incompatible with the Lite5200B
+#endif
+#if defined(CFG_LOWBOOT16)
+#define CFG_ENV_ADDR           (CFG_FLASH_BASE + 0x01060000)
+#endif
+#endif /* CFG_LOWBOOT */
+#else /* !CONFIG_LITE5200B (IceCube)*/
 #define CFG_FLASH_BASE         0xFF000000
 #define CFG_FLASH_SIZE         0x01000000
 #if !defined(CFG_LOWBOOT)
@@ -194,6 +218,7 @@
 #define CFG_ENV_ADDR           (CFG_FLASH_BASE + 0x00040000)
 #endif
 #endif /* CFG_LOWBOOT */
+#endif /* CONFIG_LITE5200B */
 #define CFG_MAX_FLASH_BANKS    2       /* max num of memory banks      */
 
 #define CFG_MAX_FLASH_SECT     128     /* max num of sects on one chip */
@@ -203,13 +228,23 @@
 
 #undef CONFIG_FLASH_16BIT      /* Flash is 8-bit */
 
+#if defined(CONFIG_LITE5200B)
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_BANKS_LIST   {CFG_CS1_START,CFG_CS0_START}
+#endif
+
 
 /*
  * Environment settings
  */
 #define CFG_ENV_IS_IN_FLASH    1
 #define CFG_ENV_SIZE           0x10000
+#if defined(CONFIG_LITE5200B)
+#define CFG_ENV_SECT_SIZE      0x20000
+#else
 #define CFG_ENV_SECT_SIZE      0x10000
+#endif
 #define CONFIG_ENV_OVERWRITE   1
 
 /*
@@ -246,6 +281,9 @@
  */
 /* #define CONFIG_FEC_10MBIT 1 */
 #define CONFIG_PHY_ADDR                0x00
+#if defined(CONFIG_LITE5200B)
+#define CONFIG_FEC_MII100      1
+#endif
 
 /*
  * GPIO configuration
@@ -288,6 +326,16 @@
 #define CFG_HID0_FINAL         0
 #endif
 
+#if defined(CONFIG_LITE5200B)
+#define CFG_CS1_START          CFG_FLASH_BASE
+#define CFG_CS1_SIZE           CFG_FLASH_SIZE
+#define CFG_CS1_CFG            0x00047800
+#define CFG_CS0_START          (CFG_FLASH_BASE + CFG_FLASH_SIZE)
+#define CFG_CS0_SIZE           CFG_FLASH_SIZE
+#define CFG_BOOTCS_START       CFG_CS0_START
+#define CFG_BOOTCS_SIZE                CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG         0x00047800
+#else /* IceCube aka Lite5200 */
 #ifdef CONFIG_MPC5200_DDR
 
 #define CFG_BOOTCS_START       (CFG_CS1_START + CFG_CS1_SIZE)
@@ -306,6 +354,7 @@
 #define CFG_CS0_SIZE           CFG_FLASH_SIZE
 
 #endif /* CONFIG_MPC5200_DDR */
+#endif /*CONFIG_LITE5200B */
 
 #define CFG_CS_BURST           0x00000000
 #define CFG_CS_DEADCYCLE       0x33333333

diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index db2147b481a4467a2559847804c37703482dbfc8..7e57a0fae1497c9afba1960aa688f16f0bd341dc 100644 (file)
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -58,7 +58,6 @@
                        CFG_CMD_CACHE   | \
                        CFG_CMD_DATE    | \
                        CFG_CMD_DHCP    | \
-                       CFG_CMD_ECHO    | \
                        CFG_CMD_EEPROM  | \
                        CFG_CMD_ELF     | \
                        CFG_CMD_FAT     | \
@@ -87,6 +86,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS  (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #define         CFG_HUSH_PARSER
 #define         CFG_PROMPT_HUSH_PS2 "> "
 /**************************************************************

diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h
index d6d2fabeec88bd7f1f7ca028fba38abd6375749d..1e9a1f7ab61c8792a645846ee49be1092ea56574 100644 (file)
--- a/include/configs/MPC8349ADS.h
+++ b/include/configs/MPC8349ADS.h
@@ -41,9 +41,8 @@
 #define CONFIG_MPC8349         1       /* MPC8349 specific */
 #define CONFIG_MPC8349ADS      1       /* MPC8349ADS board specific */
 
-/* FIXME: Real PCI support will come in a follow-up update. */
-#undef CONFIG_PCI
-
+#define CONFIG_PCI
+#undef  CONFIG_MPC83XX_PCI2            /* support for 2nd PCI controller */
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
@@ -150,7 +149,7 @@
 
 #define CONFIG_L1_INIT_RAM
 #define CFG_INIT_RAM_LOCK      1
-#define CFG_INIT_RAM_ADDR      0xe4010000   /* Initial RAM address */
+#define CFG_INIT_RAM_ADDR      0x40000000   /* Initial RAM address */
 #define CFG_INIT_RAM_END       0x1000       /* End of used area in RAM*/
 
 #define CFG_GBL_DATA_SIZE      0x100     /* num bytes initial data */
@@ -324,19 +323,26 @@
  * General PCI
  * Addresses are mapped 1-1.
  */
+
 #define CFG_PCI1_MEM_BASE      0x80000000
 #define CFG_PCI1_MEM_PHYS      CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE      0x20000000      /* 512M */
+#define CFG_PCI1_MEM_SIZE      0x10000000      /* 256M */
+#define CFG_PCI1_MMIO_BASE     0x90000000
+#define CFG_PCI1_MMIO_PHYS     CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE     0x10000000      /* 256M */
 #define CFG_PCI1_IO_BASE       0x00000000
 #define CFG_PCI1_IO_PHYS       0xe2000000
-#define CFG_PCI1_IO_SIZE       0x1000000       /* 16M */
+#define CFG_PCI1_IO_SIZE       0x00100000      /* 1M */
 
-#define CFG_PCI2_MEM_BASE      0xA0000000
+#define CFG_PCI2_MEM_BASE      0xa0000000
 #define CFG_PCI2_MEM_PHYS      CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE      0x20000000      /* 512M */
+#define CFG_PCI2_MEM_SIZE      0x10000000      /* 256M */
+#define CFG_PCI2_MMIO_BASE     0xb0000000
+#define CFG_PCI2_MMIO_PHYS     CFG_PCI2_MMIO_BASE
+#define CFG_PCI2_MMIO_SIZE     0x10000000      /* 256M */
 #define CFG_PCI2_IO_BASE       0x00000000
-#define CFG_PCI2_IO_PHYS       0xe3000000
-#define CFG_PCI2_IO_SIZE       0x1000000       /* 16M */
+#define CFG_PCI2_IO_PHYS       0xe2100000
+#define CFG_PCI2_IO_SIZE       0x00100000      /* 1M */
 #if defined(CONFIG_PCI)
 
 #define PCI_ALL_PCI1
@@ -506,6 +512,10 @@
        HRCWH_TSEC2M_IN_GMII )
 #endif
 
+/* System IO Config */
+#define CFG_SICRH      SICRH_TSOBI1
+#define CFG_SICRL      SICRL_LDP_A
+
 #define CFG_HID0_INIT 0x000000000
 
 #define CFG_HID0_FINAL CFG_HID0_INIT
@@ -515,7 +525,66 @@
        HID0_ENABLE_M_BIT |\
        HID0_ENABLE_ADDRESS_BROADCAST ) */
 
-#define CFG_HID2 0x000000000
+#define CFG_HID2 HID2_HBE
+
+/* DDR 0 - 256MB */
+#define CFG_IBAT0L     (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U     (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#define CFG_IBAT1L     (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U     (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* 2G - 3G PCI */
+#ifdef CONFIG_PCI
+#define CFG_IBAT2L     (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT2U     (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L     (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT3U     (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT2L     (0)
+#define CFG_IBAT2U     (0)
+#define CFG_IBAT3L     (0)
+#define CFG_IBAT3U     (0)
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CFG_IBAT4L     (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT4U     (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT5L     (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U     (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT4L     (0)
+#define CFG_IBAT4U     (0)
+#define CFG_IBAT5L     (0)
+#define CFG_IBAT5U     (0)
+#endif
+
+/* IMMRBAR */
+#define CFG_IBAT6L     (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U     (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* SDRAM, BCSR & FLASH */
+#define CFG_IBAT7L     (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U     (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L     CFG_IBAT0L
+#define CFG_DBAT0U     CFG_IBAT0U
+#define CFG_DBAT1L     CFG_IBAT1L
+#define CFG_DBAT1U     CFG_IBAT1U
+#define CFG_DBAT2L     CFG_IBAT2L
+#define CFG_DBAT2U     CFG_IBAT2U
+#define CFG_DBAT3L     CFG_IBAT3L
+#define CFG_DBAT3U     CFG_IBAT3U
+#define CFG_DBAT4L     CFG_IBAT4L
+#define CFG_DBAT4U     CFG_IBAT4U
+#define CFG_DBAT5L     CFG_IBAT5L
+#define CFG_DBAT5U     CFG_IBAT5U
+#define CFG_DBAT6L     CFG_IBAT6L
+#define CFG_DBAT6U     CFG_IBAT6U
+#define CFG_DBAT7L     CFG_IBAT7L
+#define CFG_DBAT7U     CFG_IBAT7U
+
 
 /*
  * Internal Definitions

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
new file mode 100644 (file)
index 0000000..1a47980
--- /dev/null
+++ b/include/configs/MPC8349EMDS.h
@@ -0,0 +1,716 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8349emds board configuration file
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DEBUG
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300            1       /* E300 Family */
+#define CONFIG_MPC83XX         1       /* MPC83XX family */
+#define CONFIG_MPC8349         1       /* MPC8349 specific */
+#define CONFIG_MPC8349EMDS     1       /* MPC8349EMDS board specific */
+
+/* FIXME: Real PCI support will come in a follow-up update. */
+#undef CONFIG_PCI
+
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN      66000000        /* in Hz */
+#else
+#define CONFIG_83XX_CLKIN      33000000        /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef PCI_66M
+#define CONFIG_SYS_CLK_FREQ    66000000
+#else
+#define CONFIG_SYS_CLK_FREQ    33000000
+#endif
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F              /* call board_pre_init */
+
+#define CFG_IMMRBAR            0xE0000000
+
+#undef CFG_DRAM_TEST                           /* memory test, takes time */
+#define CFG_MEMTEST_START      0x00000000      /* memtest region */
+#define CFG_MEMTEST_END                0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC                 /* only for ECC DDR module */
+#define CONFIG_DDR_ECC_CMD             /* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM              /* use SPD EEPROM for DDR setup*/
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CFG_DDR_BASE           0x00000000      /* DDR is system memory*/
+#define CFG_SDRAM_BASE         CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE     CFG_DDR_BASE
+#undef  CONFIG_DDR_2T_TIMING
+
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS     0x51            /* DDR DIMM */
+#else
+/*
+ * Manually set up DDR parameters
+ */
+#define CFG_DDR_SIZE           256             /* MB */
+#define CFG_DDR_CONFIG         (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CFG_DDR_TIMING_1       0x36332321
+#define CFG_DDR_TIMING_2       0x00000800      /* P9-45,may need tuning */
+#define CFG_DDR_CONTROL                0xc2000000      /* unbuffered,no DYN_PWR */
+#define CFG_DDR_INTERVAL       0x04060100      /* autocharge,no open page */
+
+#if defined(CONFIG_DDR_32BIT)
+/* set burst length to 8 for 32-bit data path */
+#define CFG_DDR_MODE           0x00000023      /* DLL,normal,seq,4/2.5, 8 burst len */
+#else
+/* the default burst length is 4 - for 64-bit data path */
+#define CFG_DDR_MODE           0x00000022      /* DLL,normal,seq,4/2.5, 4 burst len */
+#endif
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE     0xF0000000      /* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE     64              /* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI                          /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER                   /* use the CFI driver */
+#define CFG_FLASH_BASE         0xFE000000      /* start of FLASH   */
+#define CFG_FLASH_SIZE         8               /* flash size in MB */
+/* #define CFG_FLASH_USE_BUFFER_WRITE */
+
+#define CFG_BR0_PRELIM         (CFG_FLASH_BASE |       /* flash Base address */ \
+                               (2 << BR_PS_SHIFT) |    /* 32 bit port size */   \
+                               BR_V)                   /* valid */
+
+#define CFG_OR0_PRELIM         0xFF806FF7      /* 8 MB flash size */
+#define CFG_LBLAWBAR0_PRELIM   CFG_FLASH_BASE  /* window base at flash base */
+#define CFG_LBLAWAR0_PRELIM    0x80000016      /* 8 MB window size */
+
+#define CFG_MAX_FLASH_BANKS    1               /* number of banks */
+#define CFG_MAX_FLASH_SECT     64              /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT   60000   /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT   500     /* Flash Write Timeout (ms) */
+
+#define CFG_MID_FLASH_JUMP     0x7F000000
+#define CFG_MONITOR_BASE       TEXT_BASE       /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+/*
+ * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
+ */
+#define CFG_BCSR               0xF8000000
+#define CFG_LBLAWBAR1_PRELIM   CFG_BCSR                /* Access window base at BCSR base */
+#define CFG_LBLAWAR1_PRELIM    0x8000000E              /* Access window size 32K */
+#define CFG_BR1_PRELIM         (CFG_BCSR|0x00000801)   /* Port-size=8bit, MSEL=GPCM */
+#define CFG_OR1_PRELIM         0xFFFFE8F0              /* length 32K */
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK      1
+#define CFG_INIT_RAM_ADDR      0xE8000000              /* Initial RAM address */
+#define CFG_INIT_RAM_END       0x1000                  /* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE      0x100                   /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN                (256 * 1024)            /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN         (128 * 1024)            /* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ *    LCRR:  DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR       (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CFG_LBC_LBCR   0x00000000
+
+#define CFG_LB_SDRAM   /* if board has SRDAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM         0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
+#define CFG_LBLAWBAR2_PRELIM   0xF0000000
+#define CFG_LBLAWAR2_PRELIM    0x80000019 /* 64M */
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *                 XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
+ */
+
+#define CFG_OR2_PRELIM 0xFC006901
+
+#define CFG_LBC_LSRT   0x32000000    /* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR  0x20000000    /* LB refresh timer prescal, 266MHz/32 */
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN     (1 << (31 -  1))
+#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR5    (3 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR8    (5 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR16   (7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT3        (3 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT6        (5 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT7        (7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8      (1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC2     (2 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC3     (3 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC4     (0 << (31 - 27))
+#define CFG_LBC_LSDMR_BUFCMD   (1 << (31 - 29))
+#define CFG_LBC_LSDMR_CL3      (3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL        (0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH        (1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH        (2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW   (3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL        (5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK        (6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFEN            \
+                               | CFG_LBC_LSDMR_BSMA1516        \
+                               | CFG_LBC_LSDMR_RFCR8           \
+                               | CFG_LBC_LSDMR_PRETOACT6       \
+                               | CFG_LBC_LSDMR_ACTTORW3        \
+                               | CFG_LBC_LSDMR_BL8             \
+                               | CFG_LBC_LSDMR_WRC3            \
+                               | CFG_LBC_LSDMR_CL3             \
+                               )
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1                ( CFG_LBC_LSDMR_COMMON \
+                               | CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2                ( CFG_LBC_LSDMR_COMMON \
+                               | CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3                ( CFG_LBC_LSDMR_COMMON \
+                               | CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4                ( CFG_LBC_LSDMR_COMMON \
+                               | CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5                ( CFG_LBC_LSDMR_COMMON \
+                               | CFG_LBC_LSDMR_OP_NORMAL)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK                get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_IMMRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_IMMRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C                        /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C                 /* I2C bit-banged */
+#define CFG_I2C_SPEED          400000  /* I2C speed and slave address */
+#define CFG_I2C_SLAVE          0x7F
+#define CFG_I2C_NOPROBES       {0x69}  /* Don't probe these addrs */
+#define CFG_I2C_OFFSET         0x3000
+#define CFG_I2C2_OFFSET                0x3100
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
+
+/* IO Configuration */
+#define CFG_IO_CONF (\
+       IO_CONF_UART |\
+       IO_CONF_TSEC1 |\
+       IO_CONF_IRQ0 |\
+       IO_CONF_IRQ1 |\
+       IO_CONF_IRQ2 |\
+       IO_CONF_IRQ3 |\
+       IO_CONF_IRQ4 |\
+       IO_CONF_IRQ5 |\
+       IO_CONF_IRQ6 |\
+       IO_CONF_IRQ7 )
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE      0x80000000
+#define CFG_PCI1_MEM_PHYS      CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE      0x20000000      /* 512M */
+#define CFG_PCI1_IO_BASE       0x00000000
+#define CFG_PCI1_IO_PHYS       0xe2000000
+#define CFG_PCI1_IO_SIZE       0x1000000       /* 16M */
+
+#define CFG_PCI2_MEM_BASE      0xA0000000
+#define CFG_PCI2_MEM_PHYS      CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE      0x20000000      /* 512M */
+#define CFG_PCI2_IO_BASE       0x00000000
+#define CFG_PCI2_IO_PHYS       0xe3000000
+#define CFG_PCI2_IO_SIZE       0x1000000       /* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define PCI_ALL_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP         /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+       #define PCI_ENET0_IOADDR        0xFIXME
+       #define PCI_ENET0_MEMADDR       0xFIXME
+       #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET               /* TSEC ethernet support */
+
+#if defined(CONFIG_TSEC_ENET)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI       1
+#endif
+
+#define CONFIG_GMII            1       /* MII PHY management */
+#define CONFIG_MPC83XX_TSEC1   1
+#define CONFIG_MPC83XX_TSEC1_NAME      "TSEC0"
+#define CONFIG_MPC83XX_TSEC2   1
+#define CONFIG_MPC83XX_TSEC2_NAME      "TSEC1"
+#define TSEC1_PHY_ADDR         0
+#define TSEC2_PHY_ADDR         1
+#define TSEC1_PHYIDX           0
+#define TSEC2_PHYIDX           0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME                "TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1374                      /* use ds1374 rtc via i2c       */
+#define CFG_I2C_RTC_ADDR               0x68    /* at address 0x68              */
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+       #define CFG_ENV_IS_IN_FLASH     1
+       #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
+       #define CFG_ENV_SECT_SIZE       0x20000 /* 128K(one sector) for env */
+       #define CFG_ENV_SIZE            0x2000
+
+/* Address and size of Redundant Environment Sector    */
+#define CFG_ENV_ADDR_REDUND    (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND    (CFG_ENV_SIZE)
+
+#else
+       #define CFG_NO_FLASH            1       /* Flash is not usable now */
+       #define CFG_ENV_IS_NOWHERE      1       /* Store ENV in memory only */
+       #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - 0x1000)
+       #define CFG_ENV_SIZE            0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO      1       /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS       ((CONFIG_CMD_DFL        \
+                                | CFG_CMD_PING         \
+                                | CFG_CMD_PCI          \
+                                | CFG_CMD_I2C          \
+                                | CFG_CMD_DATE)        \
+                               &                       \
+                                ~(CFG_CMD_ENV          \
+                                 | CFG_CMD_LOADS))
+#else
+#define  CONFIG_COMMANDS       ((CONFIG_CMD_DFL        \
+                                | CFG_CMD_PING         \
+                                | CFG_CMD_I2C          \
+                                | CFG_CMD_DATE)        \
+                               &                       \
+                                ~(CFG_CMD_ENV          \
+                                 | CFG_CMD_LOADS))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS       (CONFIG_CMD_DFL         \
+                               | CFG_CMD_PCI           \
+                               | CFG_CMD_PING          \
+                               | CFG_CMD_I2C           \
+                               | CFG_CMD_DATE          \
+                               )
+#else
+#define  CONFIG_COMMANDS       (CONFIG_CMD_DFL         \
+                               | CFG_CMD_PING          \
+                               | CFG_CMD_I2C           \
+                               | CFG_CMD_MII           \
+                               | CFG_CMD_DATE          \
+                               )
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG                 /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                   /* undef to save memory */
+#define CFG_LOAD_ADDR  0x2000000       /* default load address */
+#define CFG_PROMPT     "=> "           /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+       #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
+#else
+       #define CFG_CBSIZE      256             /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS    16              /* max number of command args */
+#define CFG_BARGSIZE   CFG_CBSIZE      /* Boot Argument Buffer Size */
+#define CFG_HZ         1000            /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ  (8 << 20)       /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE                32768
+#define CFG_CACHELINE_SIZE     32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT    5       /*log base 2 of the above value*/
+#endif
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+#if 1 /*528/264*/
+#define CFG_HRCW_LOW (\
+       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+       HRCWL_DDR_TO_SCB_CLK_1X1 |\
+       HRCWL_CSB_TO_CLKIN_4X1 |\
+       HRCWL_VCO_1X2 |\
+       HRCWL_CORE_TO_CSB_2X1)
+#elif 0 /*396/132*/
+#define CFG_HRCW_LOW (\
+       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+       HRCWL_DDR_TO_SCB_CLK_1X1 |\
+       HRCWL_CSB_TO_CLKIN_2X1 |\
+       HRCWL_VCO_1X4 |\
+       HRCWL_CORE_TO_CSB_3X1)
+#elif 0 /*264/132*/
+#define CFG_HRCW_LOW (\
+       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+       HRCWL_DDR_TO_SCB_CLK_1X1 |\
+       HRCWL_CSB_TO_CLKIN_2X1 |\
+       HRCWL_VCO_1X4 |\
+       HRCWL_CORE_TO_CSB_2X1)
+#elif 0 /*132/132*/
+#define CFG_HRCW_LOW (\
+       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+       HRCWL_DDR_TO_SCB_CLK_1X1 |\
+       HRCWL_CSB_TO_CLKIN_2X1 |\
+       HRCWL_VCO_1X4 |\
+       HRCWL_CORE_TO_CSB_1X1)
+#elif 0 /*264/264 */
+#define CFG_HRCW_LOW (\
+       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+       HRCWL_DDR_TO_SCB_CLK_1X1 |\
+       HRCWL_CSB_TO_CLKIN_4X1 |\
+       HRCWL_VCO_1X4 |\
+       HRCWL_CORE_TO_CSB_1X1)
+#endif
+
+#if defined(PCI_64BIT)
+#define CFG_HRCW_HIGH (\
+       HRCWH_PCI_HOST |\
+       HRCWH_64_BIT_PCI |\
+       HRCWH_PCI1_ARBITER_ENABLE |\
+       HRCWH_PCI2_ARBITER_DISABLE |\
+       HRCWH_CORE_ENABLE |\
+       HRCWH_FROM_0X00000100 |\
+       HRCWH_BOOTSEQ_DISABLE |\
+       HRCWH_SW_WATCHDOG_DISABLE |\
+       HRCWH_ROM_LOC_LOCAL_16BIT |\
+       HRCWH_TSEC1M_IN_GMII |\
+       HRCWH_TSEC2M_IN_GMII )
+#else
+#define CFG_HRCW_HIGH (\
+       HRCWH_PCI_HOST |\
+       HRCWH_32_BIT_PCI |\
+       HRCWH_PCI1_ARBITER_ENABLE |\
+       HRCWH_PCI2_ARBITER_ENABLE |\
+       HRCWH_CORE_ENABLE |\
+       HRCWH_FROM_0X00000100 |\
+       HRCWH_BOOTSEQ_DISABLE |\
+       HRCWH_SW_WATCHDOG_DISABLE |\
+       HRCWH_ROM_LOC_LOCAL_16BIT |\
+       HRCWH_TSEC1M_IN_GMII |\
+       HRCWH_TSEC2M_IN_GMII )
+#endif
+
+/* System IO Config */
+#define CFG_SICRH SICRH_TSOBI1
+#define CFG_SICRL SICRL_LDP_A
+
+#define CFG_HID0_INIT  0x000000000
+#define CFG_HID0_FINAL CFG_HID0_INIT
+
+/* #define CFG_HID0_FINAL              (\
+       HID0_ENABLE_INSTRUCTION_CACHE |\
+       HID0_ENABLE_M_BIT |\
+       HID0_ENABLE_ADDRESS_BROADCAST ) */
+
+
+#define CFG_HID2 HID2_HBE
+
+/* DDR @ 0x00000000 */
+#define CFG_IBAT0L     (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U     (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#ifdef CONFIG_PCI
+#define CFG_IBAT1L     (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U     (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L     (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U     (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT1L     (0)
+#define CFG_IBAT1U     (0)
+#define CFG_IBAT2L     (0)
+#define CFG_IBAT2U     (0)
+#endif
+
+/* IMMRBAR @ 0xE0000000 */
+#define CFG_IBAT3L     (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT3U     (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE (no backing mem) @ 0xE8000000 */
+#define CFG_IBAT4L     (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT4U     (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* LBC SDRAM @ 0xF0000000 */
+#define CFG_IBAT5L     (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT5U     (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+
+/* BCSR  @ 0xF8000000 */
+#define CFG_IBAT6L     (CFG_BCSR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U     (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* FLASH @ 0xFE000000 */
+#define CFG_IBAT7L     (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT7U     (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L     CFG_IBAT0L
+#define CFG_DBAT0U     CFG_IBAT0U
+#define CFG_DBAT1L     CFG_IBAT1L
+#define CFG_DBAT1U     CFG_IBAT1U
+#define CFG_DBAT2L     CFG_IBAT2L
+#define CFG_DBAT2U     CFG_IBAT2U
+#define CFG_DBAT3L     CFG_IBAT3L
+#define CFG_DBAT3U     CFG_IBAT3U
+#define CFG_DBAT4L     CFG_IBAT4L
+#define CFG_DBAT4U     CFG_IBAT4U
+#define CFG_DBAT5L     CFG_IBAT5L
+#define CFG_DBAT5U     CFG_IBAT5U
+#define CFG_DBAT6L     CFG_IBAT6L
+#define CFG_DBAT6U     CFG_IBAT6U
+#define CFG_DBAT7L     CFG_IBAT7L
+#define CFG_DBAT7U     CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD  0x01    /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM  0x02    /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE   230400  /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX  2       /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR         00:04:9f:ef:23:33
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR                00:E0:0C:00:7E:21
+#endif
+
+#define CONFIG_IPADDR          192.168.205.5
+
+#define CONFIG_HOSTNAME                mpc8349emds
+#define CONFIG_ROOTPATH                /opt/eldk/ppc_6xx
+#define CONFIG_BOOTFILE                /tftpboot/tqm83xx/uImage
+
+#define CONFIG_SERVERIP                192.168.1.1
+#define CONFIG_GATEWAYIP       192.168.1.1
+#define CONFIG_NETMASK         255.255.255.0
+
+#define CONFIG_LOADADDR                200000  /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY       6       /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS                        /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE         115200
+
+#define CONFIG_PREBOOT "echo;" \
+       "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+       "echo"
+
+#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
+       "netdev=eth0\0"                                                 \
+       "hostname=mpc8349emds\0"                                        \
+       "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
+               "nfsroot=${serverip}:${rootpath}\0"                     \
+       "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
+       "addip=setenv bootargs ${bootargs} "                            \
+               "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
+               ":${hostname}:${netdev}:off panic=1\0"                  \
+       "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+       "flash_nfs=run nfsargs addip addtty;"                           \
+               "bootm ${kernel_addr}\0"                                \
+       "flash_self=run ramargs addip addtty;"                          \
+               "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
+       "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+               "bootm\0"                                               \
+       "rootpath=/opt/eldk/ppc_6xx\0"                                  \
+       "bootfile=/tftpboot/mpc8349emds/uImage\0"                       \
+       "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
+       "update=protect off fe000000 fe03ffff; "                        \
+               "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"     \
+       "upd=run load;run update\0"                                     \
+       ""
+
+#define CONFIG_BOOTCOMMAND     "run flash_self"
+
+#endif /* __CONFIG_H */

diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h
index 565f9bb5c037a35edabb1314cfa99b050b891977..831cc5ecd3258f05138e34bd96dcd57638ee9dc3 100644 (file)
--- a/include/configs/MPC86xADS.h
+++ b/include/configs/MPC86xADS.h
@@ -21,7 +21,7 @@
 #define CONFIG_MPC86xADS        1       /* new ADS */
 #define CONFIG_FADS            1       /* We are FADS compatible (more or less) */
 
-/* New MPC86xADS - pick one of these */
+/* CPU type - pick one of these */
 #define CONFIG_MPC866T                 1
 #undef CONFIG_MPC866P
 #undef CONFIG_MPC859T
@@ -33,7 +33,10 @@
 #undef CONFIG_8xx_CONS_NONE
 #define CONFIG_BAUDRATE                38400
 
-#define CONFIG_8xx_OSCLK       10000000 /* 10MHz oscillator on EXTCLK  */
+#define CONFIG_8xx_OSCLK               10000000 /* 10MHz oscillator on EXTCLK  */
+#define CONFIG_8xx_CPUCLK_DEFAULT      50000000
+#define CFG_8xx_CPUCLK_MIN             40000000
+#define CFG_8xx_CPUCLK_MAX             80000000
 
 #define CONFIG_DRAM_50MHZ       1
 #define CONFIG_SDRAM_50MHZ      1

diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h
index 74318e55456f6e8a19f02f295cf66c6ac4c595fc..1867c5bf0a2c30837891acdb7ee1e81b585ac861 100644 (file)
--- a/include/configs/MPC885ADS.h
+++ b/include/configs/MPC885ADS.h
@@ -1,44 +1,34 @@
 /*
  * A collection of structures, addresses, and values associated with
- * the Motorola DUET ADS board. Values common to all FADS family boards
+ * the Motorola MPC885ADS board. Values common to all FADS family boards
  * are in board/fads/fads.h
  *
- * Copyright (C) 2003 Arabella Software Ltd.
+ * Copyright (C) 2003-2004 Arabella Software Ltd.
  * Yuli Barcohen <yuli@arabellasw.com>
  */
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* Board type */
-#define CONFIG_MPC885ADS               1       /* Duet (MPC87x/88x) ADS */
+#define CONFIG_MPC885ADS       1       /* MPC885ADS board */
 #define CONFIG_FADS            1       /* We are FADS compatible (more or less) */
 
-#define CONFIG_MPC885          1       /* MPC885 CPU (Duet family) */
+#define CONFIG_MPC885          1       /* MPC885 CPU (Duet family) */
 
-#define        CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
+#define        CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1 */
 #undef CONFIG_8xx_CONS_SMC2
 #undef CONFIG_8xx_CONS_NONE
 #define CONFIG_BAUDRATE                38400
 
-#define CONFIG_8xx_OSCLK       10000000 /* 10 MHz oscillator on EXTCLK  */
-
-#define CFG_PLPRCR             ((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS)
+#define CONFIG_8xx_OSCLK               10000000 /* 10 MHz oscillator on EXTCLK  */
+#define CONFIG_8xx_CPUCLK_DEFAULT      50000000
+#define CFG_8xx_CPUCLK_MIN             40000000
+#define CFG_8xx_CPUCLK_MAX             133000000
 
 #define CONFIG_SDRAM_50MHZ      1
 
-#define CONFIG_COMMANDS        (CONFIG_CMD_DFL   \
-                        | CFG_CMD_DHCP   \
-                        | CFG_CMD_IMMAP  \
-                        | CFG_CMD_MII    \
-                        | CFG_CMD_PING   \
-                       )
-
 #include "fads.h"
 
-#undef CFG_SCCR
-#define CFG_SCCR       (SCCR_TBS|SCCR_EBDF11)
-
 #define CFG_OR5_PRELIM         0xFFFF8110      /* 64Kbyte address space */
 #define CFG_BR5_PRELIM         (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)
 

diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index 371ea17edd231530ec1483a8fb8eda8de11c2edf..8da29c4afc01659c54fc730f976c76114aed3142 100644 (file)
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -1,4 +1,5 @@
 /*
+ * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
  * (C) Copyright 2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
@@ -65,6 +66,11 @@
 #define CFG_8XX_XIN                    CONFIG_8xx_OSCLK
 
 #define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT         "\nEnter password - autoboot in %d seconds...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR      "ids"
+#define CONFIG_BOOT_RETRY_TIME         900
+#define CONFIG_BOOT_RETRY_MIN          30
 
 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
 
@@ -75,7 +81,7 @@
        "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
        "bootm"
 
-#undef CONFIG_WATCHDOG                 /* watchdog disabled            */
+#define CONFIG_WATCHDOG                        /* watchdog enabled             */
 
 #undef CONFIG_STATUS_LED               /* Status LED disabled          */
 
@@ -96,12 +102,26 @@
 /*
  * Software (bit-bang) I2C driver configuration
  */
+#if defined(CONFIG_IDS852_REV1)
+
 #define SCL            0x1000          /* PA 3 */
 #define SDA            0x2000          /* PA 2 */
 
 #define __I2C_DIR      immr->im_ioport.iop_padir
 #define __I2C_DAT      immr->im_ioport.iop_padat
 #define __I2C_PAR      immr->im_ioport.iop_papar
+
+#elif defined(CONFIG_IDS852_REV2)
+
+#define SCL            0x0002          /* PB 30 */
+#define SDA            0x0001          /* PB 31 */
+
+#define __I2C_PAR      immr->im_cpm.cp_pbpar
+#define __I2C_DIR      immr->im_cpm.cp_pbdir
+#define __I2C_DAT      immr->im_cpm.cp_pbdat
+
+#endif
+
 #define        I2C_INIT        { __I2C_PAR &= ~(SDA|SCL);      \
                          __I2C_DIR |= (SDA|SCL);       }
 #define        I2C_READ        ((__I2C_DAT & SDA) ? 1 : 0)
@@ -217,6 +237,8 @@
 /*
  * NAND flash support
  */
+#define CFG_NAND_LEGACY
+
 #define CFG_MAX_NAND_DEVICE    1
 #define NAND_ChipID_UNKNOWN    0x00
 #define SECTORSIZE             512
@@ -227,17 +249,6 @@
 #define ADDR_COLUMN            1
 #define NAND_NO_RB
 
-#define NAND_WAIT_READY(nand)          udelay(12)
-#define WRITE_NAND_COMMAND(d, adr)     WRITE_NAND(d, adr + 2)
-#define WRITE_NAND_ADDRESS(d, adr)     WRITE_NAND(d, adr + 1)
-#define WRITE_NAND(d, adr)             (*(volatile uint8_t *)(adr) = (uint8_t)(d))
-#define READ_NAND(adr)                 (*(volatile uint8_t *)(adr))
-#define NAND_DISABLE_CE(nand)          /* nop */
-#define NAND_ENABLE_CE(nand)           /* nop */
-#define NAND_CTL_CLRALE(nandptr)       /* nop */
-#define NAND_CTL_SETALE(nandptr)       /* nop */
-#define NAND_CTL_CLRCLE(nandptr)       /* nop */
-#define NAND_CTL_SETCLE(nandptr)       /* nop */
 
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control                                   11-9
@@ -310,7 +321,8 @@
 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
 
 /*
- * BR2 and OR2 (NAND Flash) - now addressed through UPMB
+ * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
+ * rev2 only uses the chipselect
  */
 #define CFG_NAND_BASE          0x50000000
 #define CFG_NAND_SIZE          0x04000000
@@ -335,6 +347,18 @@
 #define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 
+/*
+ * BR4 and OR4 (CPLD)
+ */
+#define CFG_CPLD_BASE           0x80000000      /* CPLD                 */
+#define CFG_CPLD_SIZE           0x10000         /* only 16 used         */
+
+#define CFG_OR_TIMING_CPLD     (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+                                OR_SCY_1_CLK)
+
+#define CFG_BR4_PRELIM  ((CFG_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CFG_OR4_PRELIM  (((-CFG_CPLD_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_CPLD)
+
 /*
  * BR5 and OR5 (SRAM)
  */
@@ -347,6 +371,16 @@
 #define CFG_BR5_PRELIM  ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 #define CFG_OR5_PRELIM  (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
 
+#if defined(CONFIG_CP850)
+/*
+ *  BR6 and OR6 (DPRAM) - only on CP850
+ */
+#define CFG_OR6_PRELIM          0xffff8170
+#define CFG_BR6_PRELIM          0xa0000401
+#define DPRAM_BASE_ADDR         0xa0000000
+
+#define CONFIG_MISC_INIT_R      1
+#endif
 
 /*
  * 4096 Rows from SDRAM example configuration
@@ -411,14 +445,12 @@
 #define CONFIG_JFFS2_PART_OFFSET       0x00000000
 
 /* mtdparts command line support */
-/*
 #define CONFIG_JFFS2_CMDLINE
 #define MTDIDS_DEFAULT         "nor0=nc650-0,nand0=nc650-nand"
 
 #define MTDPARTS_DEFAULT       "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
-                                       "2560k(cramfs1),2560k(cramfs2)," \
-                                       "256k(u-boot),256k(env);" \
-                               "nc650-nand:4m(nand1),28m(nand2)"
-*/
+                                       "4m(cramfs1),1m(cramfs2)," \
+                                       "256k(u-boot),128k(env);" \
+                               "nc650-nand:4m(jffs1),28m(jffs2)"
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
index bf4c899592fed76a4f9000b9a37d0d6ce2ac5479..444f721cc85a847bfdf704002a49ebae75043b80 100644 (file)
--- a/include/configs/NETPHONE.h
+++ b/include/configs/NETPHONE.h
@@ -491,6 +491,7 @@
 /****************************************************************/
 
 /* NAND */
+#define CFG_NAND_LEGACY
 #define CFG_NAND_BASE          NAND_BASE
 #define CONFIG_MTD_NAND_ECC_JFFS2
 #define CONFIG_MTD_NAND_VERIFY_WRITE

diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 1bcd88d208a3ea3027f9b2dc0a4339c23e4781c6..25b63457c74d814d4b22a0ed0489a2752d92f8a5 100644 (file)
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -609,6 +609,7 @@
 /****************************************************************/
 
 /* NAND */
+#define CFG_NAND_LEGACY
 #define CFG_NAND_BASE                  NAND_BASE
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_MTD_NAND_UNSAFE

diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
index 529cb4cbae2e2b34af3a5681028113f3882bd311..e20e72495ccbc8dce1602f8817690d9ae9684601 100644 (file)
--- a/include/configs/NETTA2.h
+++ b/include/configs/NETTA2.h
@@ -491,6 +491,7 @@
 /****************************************************************/
 
 /* NAND */
+#define CFG_NAND_LEGACY
 #define CFG_NAND_BASE          NAND_BASE
 #define CONFIG_MTD_NAND_ECC_JFFS2
 #define CONFIG_MTD_NAND_VERIFY_WRITE

diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
index dc6b15fcdc492c0aec9efe55c54811370cd77525..e30be0987aa47619863424afe90229304ad54c25 100644 (file)
--- a/include/configs/NETVIA.h
+++ b/include/configs/NETVIA.h
@@ -387,6 +387,8 @@
 
 /*****************************************************************************/
 
+#define CFG_NAND_LEGACY
+
 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
 
 /* NAND */

diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h
index d03706e19365c667b59e4dea8f10e024ff589a60..3a97fbcbde84056918ad52d625c72fe2a966b2a5 100644 (file)
--- a/include/configs/PCIPPC2.h
+++ b/include/configs/PCIPPC2.h
@@ -77,6 +77,7 @@
  */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
 
 /*
  * Miscellaneous configurable options

diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h
index 92b2f7cf839753744ad936ea9b7ce1b951be41b7..130beb78e637682ed35a69ba5dcd9150e9fcf779 100644 (file)
--- a/include/configs/PCIPPC6.h
+++ b/include/configs/PCIPPC6.h
@@ -79,6 +79,7 @@
  */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
 
 /*
  * Miscellaneous configurable options

diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 9668fb0ce2fc919372e0e03ff948eef9ac33a805..806e95f48083d2c943652fbf87309d5f09de0726 100644 (file)
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -50,7 +50,6 @@
                        CFG_CMD_PCI     | \
                        CFG_CMD_CACHE   | \
                        CFG_CMD_IRQ     | \
-                       CFG_CMD_ECHO    | \
                        CFG_CMD_EEPROM  | \
                        CFG_CMD_I2C     | \
                        CFG_CMD_REGINFO | \
@@ -69,6 +68,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS  (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #define         CFG_HUSH_PARSER
 #define         CFG_PROMPT_HUSH_PS2 "> "
 /**************************************************************

diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 54ecfa4c5e31e32c04b91d48c99a0b3930242e51..dd5d83168042f121c85a6c7938e2234bfabcb2d9 100644 (file)
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -160,6 +160,8 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
+#define CFG_NAND_LEGACY
+
 #define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices           */
 #define SECTORSIZE 512
 

diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index e73ad5100c2ea5a7c20b60afc62bfdfe3ce7f20a..9c241e67e732359d1f2568f3a1d6006f0b03d53e 100644 (file)
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -101,6 +101,8 @@
 #define ADD_DOC_CMD             0
 #else
 #define ADD_DOC_CMD             CFG_CMD_DOC
+/* DoC requires legacy NAND for now */
+#define CFG_NAND_LEGACY
 #endif
 
 /*

diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index 6e5e3bbe18cf29334fced893fe9c6db6e10b5ae0..88fdb51adef553924a89c326cd81454170ab6c8b 100644 (file)
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -180,6 +180,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 /*
  * Disk-On-Chip configuration
  */

diff --git a/include/configs/PM828.h b/include/configs/PM828.h
index 982a1f814301a57cbbb27b2937137cb390758e81..37ee9771b52fa5c3b57ef27c2d7b98a765734b64 100644 (file)
--- a/include/configs/PM828.h
+++ b/include/configs/PM828.h
@@ -183,6 +183,7 @@
 /*
  * Disk-On-Chip configuration
  */
+#define CFG_NAND_LEGACY
 
 #define CFG_DOC_SHORT_TIMEOUT
 #define CFG_MAX_DOC_DEVICE     1       /* Max number of DOC devices    */

diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index 8bcab0b0f378ea0571aabc9a3c8b8f8f6fd30975..6e0bd7f23ec7408bba2bdc33801b4f442a46ccfd 100644 (file)
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -53,9 +53,15 @@
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
 #define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
 
+#define CONFIG_NET_MULTI       1
+#undef  CONFIG_HAS_ETH1
+
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                0       /* PHY address                  */
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NETCONSOLE              /* include NetConsole support   */
 
 #define CONFIG_COMMANDS              ( CONFIG_CMD_DFL  | \
                                CFG_CMD_BSP     | \
@@ -154,15 +160,24 @@
 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 
 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0408  /* PCI Device ID: PMC-405       */
+#define CFG_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408  /* PCI Device ID: Non-Monarch */
+#define CFG_PCI_SUBSYS_DEVICEID_MONARCH 0x0409     /* PCI Device ID: Monarch */
+#define CFG_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
+
 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+
+#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#if 1
+#define CFG_PCI_PTM2LA 0xef000000      /* point to internal regs       */
+#define CFG_PCI_PTM2MS  0xff000001      /* 16MB, enable                 */
+#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
+#else /* old mapping */
 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
+#endif
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
@@ -259,7 +274,7 @@
 #define FLASH1_BA      0xFE000000          /* FLASH 1 Base Address             */
 #define CAN_BA         0xF0000000          /* CAN Base Address                 */
 #define RTC_BA         0xF0000500          /* RTC Base Address                 */
-#define CF_BA          0xF0100000          /* CompactFlash Base Address        */
+#define NVRAM_BA        0xF0200000          /* NVRAM Base Address               */
 
 /* Memory Bank 0 (Flash Bank 0) initialization                                 */
 #define CFG_EBC_PB0AP  0x92015480
@@ -273,9 +288,11 @@
 #define CFG_EBC_PB2AP  0x03000440   /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
 #define CFG_EBC_PB2CR  CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 
-/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization              */
-#define CFG_EBC_PB3AP  0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR  CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 -> unused */
+
+/* Memory Bank 4 (NVRAM) initialization                                        */
+#define CFG_EBC_PB4AP  0x03000440   /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
+#define CFG_EBC_PB4CR  NVRAM_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit        */
 
 /*-----------------------------------------------------------------------
  * FPGA stuff
@@ -292,6 +309,15 @@
 
 #define CFG_VXWORKS_MAC_PTR    0x00000000      /* Pass Ethernet MAC to VxWorks */
 
+/*-----------------------------------------------------------------------
+ * GPIOs
+ */
+#define CFG_NONMONARCH         (0x80000000 >> 14)   /* GPIO24 */
+#define CFG_XEREADY            (0x80000000 >> 15)   /* GPIO15 */
+#define CFG_INTA_FAKE          (0x80000000 >> 19)   /* GPIO19 */
+#define CFG_SELF_RST           (0x80000000 >> 21)   /* GPIO21 */
+#define CFG_REV1_2             (0x80000000 >> 23)   /* GPIO23 */
+
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */

diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 7ca827fa4b4f18d341f77ba6e83b97c676ee9925..16e2cc6d648b08a667e67d938f5fd057defe9927 100644 (file)
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -139,8 +139,18 @@
 #define CFG_I2C_RTC_ADDR       0x68
 #define CFG_M41T11_BASE_YEAR   1900
 
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
 #define CONFIG_SDRAM_BANK0     1       /* init onboard SDRAM bank 0    */
 
+/* SDRAM timings used in datasheet */
+#define CFG_SDRAM_CL            2
+#define CFG_SDRAM_tRP           20
+#define CFG_SDRAM_tRC           65
+#define CFG_SDRAM_tRCD          20
+#undef  CFG_SDRAM_tRFC
+
 /*
  * Miscellaneous configurable options
  */
@@ -188,34 +198,34 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
+/*
+ * nand device 1 on dave (PPChameleonEVB) needs more time,
+ * so we just introduce additional wait in nand_wait(),
+ * effectively for both devices.
+ */
+#define PPCHAMELON_NAND_TIMER_HACK
+
 #define CFG_NAND0_BASE 0xFF400000
 #define CFG_NAND1_BASE 0xFF000000
+#define CFG_NAND_BASE_LIST     { CFG_NAND0_BASE, CFG_NAND1_BASE }
+#define NAND_BIG_DELAY_US      25
+#define CFG_MAX_NAND_DEVICE    2       /* Max number of NAND devices */
 
-#define CFG_MAX_NAND_DEVICE    2       /* Max number of NAND devices           */
-#define SECTORSIZE 512
-#define NAND_NO_RB
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN    0x00
-#define NAND_MAX_FLOORS 1
 #define NAND_MAX_CHIPS 1
 
 #define CFG_NAND0_CE  (0x80000000 >> 1)         /* our CE is GPIO1 */
+#define CFG_NAND0_RDY (0x80000000 >> 4)         /* our RDY is GPIO4 */
 #define CFG_NAND0_CLE (0x80000000 >> 2)         /* our CLE is GPIO2 */
 #define CFG_NAND0_ALE (0x80000000 >> 3)         /* our ALE is GPIO3 */
-#define CFG_NAND0_RDY (0x80000000 >> 4)         /* our RDY is GPIO4 */
 
 #define CFG_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
+#define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 #define CFG_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
 #define CFG_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
-#define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 
-#define NAND_DISABLE_CE(nand) do \
+#define MACRO_NAND_DISABLE_CE(nandptr) do \
 { \
-       switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+       switch((unsigned long)nandptr) \
        { \
            case CFG_NAND0_BASE: \
                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
@@ -226,9 +236,9 @@
        } \
 } while(0)
 
-#define NAND_ENABLE_CE(nand) do \
+#define MACRO_NAND_ENABLE_CE(nandptr) do \
 { \
-       switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+       switch((unsigned long)nandptr) \
        { \
            case CFG_NAND0_BASE: \
                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
@@ -239,7 +249,7 @@
        } \
 } while(0)
 
-#define NAND_CTL_CLRALE(nandptr) do \
+#define MACRO_NAND_CTL_CLRALE(nandptr) do \
 { \
        switch((unsigned long)nandptr) \
        { \
@@ -252,7 +262,7 @@
        } \
 } while(0)
 
-#define NAND_CTL_SETALE(nandptr) do \
+#define MACRO_NAND_CTL_SETALE(nandptr) do \
 { \
        switch((unsigned long)nandptr) \
        { \
@@ -265,7 +275,7 @@
        } \
 } while(0)
 
-#define NAND_CTL_CLRCLE(nandptr) do \
+#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
 { \
        switch((unsigned long)nandptr) \
        { \
@@ -278,7 +288,7 @@
        } \
 } while(0)
 
-#define NAND_CTL_SETCLE(nandptr) do { \
+#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
        switch((unsigned long)nandptr) { \
        case CFG_NAND0_BASE: \
                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
@@ -289,6 +299,17 @@
        } \
 } while(0)
 
+#if 0
+#define SECTORSIZE 512
+#define NAND_NO_RB
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN    0x00
+#define NAND_MAX_FLOORS 1
+
 #ifdef NAND_NO_RB
 /* constant delay (see also tR in the datasheet) */
 #define NAND_WAIT_READY(nand) do { \
@@ -303,7 +324,7 @@
 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
+#endif
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
@@ -338,16 +359,16 @@
 #define CFG_SDRAM_BASE         0x00000000
 
 /* Reserve 256 kB for Monitor  */
+/*
 #define CFG_FLASH_BASE         0xFFFC0000
 #define CFG_MONITOR_BASE       CFG_FLASH_BASE
 #define CFG_MONITOR_LEN                (256 * 1024)
+*/
 
 /* Reserve 320 kB for Monitor  */
-/*
 #define CFG_FLASH_BASE         0xFFFB0000
 #define CFG_MONITOR_BASE       CFG_FLASH_BASE
 #define CFG_MONITOR_LEN                (320 * 1024)
-*/
 
 #define CFG_MALLOC_LEN         (256 * 1024)    /* Reserve 256 kB for malloc()  */
 

diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h
index 6b65031099444a9d92ae06aa2510328ff38cfc19..48ada0ed9b6f9afc8feeaf51796adaf669018eeb 100644 (file)
--- a/include/configs/RPXlite.h
+++ b/include/configs/RPXlite.h
@@ -21,10 +21,6 @@
  * MA 02111-1307 USA
  */
 
-/*
- * board/config.h - configuration options, board specific
- */
-
 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
  * U-Boot port on RPXlite board
  */
@@ -53,8 +49,6 @@
 #define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
 #endif
 
-#define        CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
-
 #undef CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND                                                     \
        "bootp; "                                                               \
@@ -65,6 +59,7 @@
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
 #undef CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
 
+#define CONFIG_BZIP2           /* Include support for bzip2 compressed images  */
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
 #define CONFIG_BOOTP_MASK      (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
@@ -86,12 +81,14 @@
 #define        CFG_MAXARGS     16              /* max number of command args   */
 #define CFG_BARGSIZE   CFG_CBSIZE      /* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START      0x0040000       /* memtest works on     */
-#define CFG_MEMTEST_END                0x00C0000       /* 4 ... 12 MB in DRAM  */
+#define CFG_MEMTEST_START      0x00400000      /* memtest works on     */
+#define CFG_MEMTEST_END                0x00C00000      /* 4 ... 12 MB in DRAM  */
 
-#define        CFG_LOAD_ADDR           0x100000        /* default load address */
+#define CFG_RESET_ADDRESS      0x09900000
 
-#define        CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
+#define        CFG_LOAD_ADDR           0x400000        /* default load address */
+
+#define        CFG_HZ                  1000            /* decrementer freq: 1 ms ticks */
 
 #define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
 
@@ -120,16 +117,14 @@
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
 #define        CFG_SDRAM_BASE          0x00000000
-#define CFG_FLASH_BASE 0xFFC00000
-/*%%% #define CFG_FLASH_BASE           0xFFF00000 */
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define CFG_FLASH_BASE         0xFFC00000
+#define CFG_MONITOR_BASE       TEXT_BASE
 #define        CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
+#ifdef CONFIG_BZIP2
+#define CFG_MALLOC_LEN         (4096 << 10)    /* Reserve ~4 MB for malloc()   */
 #else
-#define        CFG_MONITOR_LEN         (128 << 10)     /* Reserve 128 kB for Monitor   */
-#endif
-#define CFG_MONITOR_BASE       0xFFF00000
-/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
-#define        CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
+#define CFG_MALLOC_LEN         (128 << 10)     /* Reserve 128 KB for malloc()  */
+#endif /* CONFIG_BZIP2 */
 
 /*
  * For booting Linux, the board info and command line data
@@ -147,9 +142,13 @@
 #define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
 #define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)      */
 
+#define        CFG_DIRECT_FLASH_TFTP
+
 #define        CFG_ENV_IS_IN_FLASH     1
-#define        CFG_ENV_OFFSET          0x8000  /*   Offset   of Environment Sector     */
-#define        CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
+#define CFG_ENV_SECT_SIZE      0x40000         /* We use one complete sector   */
+#define CFG_ENV_ADDR           (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+
+#define CONFIG_ENV_OVERWRITE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
@@ -352,12 +351,12 @@
 
 #define BCSR0_ENMONXCVR        0x01    /* Monitor XVCR Control */
 #define BCSR0_ENNVRAM  0x02    /* CS4# Control */
-#define BCSR0_LED5             0x04    /* LED5 control 0='on' 1='off' */
-#define BCSR0_LED4             0x08    /* LED4 control 0='on' 1='off' */
+#define BCSR0_LED5     0x04    /* LED5 control 0='on' 1='off' */
+#define BCSR0_LED4     0x08    /* LED4 control 0='on' 1='off' */
 #define BCSR0_FULLDPLX 0x10    /* Ethernet XCVR Control */
 #define BCSR0_COLTEST  0x20
 #define BCSR0_ETHLPBK  0x40
-#define BCSR0_ETHEN            0x80
+#define BCSR0_ETHEN    0x80
 
 #define BCSR1_PCVCTL7  0x01    /* PC Slot B Control */
 #define BCSR1_PCVCTL6  0x02
@@ -371,22 +370,13 @@
 #define BCSR2_USBSPD   0x40
 #define BCSR2_USBSUSP  0x80
 
-#define BCSR3_BWRTC            0x01    /* Real Time Clock Battery */
-#define BCSR3_BWNVR            0x02    /* NVRAM Battery */
+#define BCSR3_BWRTC    0x01    /* Real Time Clock Battery */
+#define BCSR3_BWNVR    0x02    /* NVRAM Battery */
 #define BCSR3_RDY_BSY  0x04    /* Flash Operation */
-#define BCSR3_RPXL             0x08    /* Reserved (reads back '1') */
-#define BCSR3_D27              0x10    /* Dip Switch settings */
-#define BCSR3_D26              0x20
-#define BCSR3_D25              0x40
-#define BCSR3_D24              0x80
-
-
-/*
- * Environment setting
- */
-
-#define CONFIG_ETHADDR 00:10:EC:00:1D:0B
-#define CONFIG_IPADDR  192.168.1.65
-#define CONFIG_SERVERIP        192.168.1.27
+#define BCSR3_RPXL     0x08    /* Reserved (reads back '1') */
+#define BCSR3_D27      0x10    /* Dip Switch settings */
+#define BCSR3_D26      0x20
+#define BCSR3_D25      0x40
+#define BCSR3_D24      0x80
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h
index 8cd7df1ecff4c86a2d6dfcaf8b5d12466a9c5d88..31025473f43799793381a33a437f6b2a6316a35f 100644 (file)
--- a/include/configs/RPXlite_DW.h
+++ b/include/configs/RPXlite_DW.h
@@ -45,7 +45,7 @@
  */
 
 /* #define DEBUG       1 */
-/* #ifdef DEPLOYMENT   1 */
+/* #define DEPLOYMENT  1 */
 
 #undef CONFIG_MPC860
 #define CONFIG_MPC823          1       /* This is a MPC823e CPU. */
@@ -61,23 +61,23 @@
 #define CONFIG_BAUDRATE                9600    /* console default baudrate = 9600bps   */
 
 #ifdef DEBUG
-#define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
+#define CONFIG_BOOTDELAY       -1      /* autoboot disabled            */
 #else
-#define CONFIG_BOOTDELAY        6       /* autoboot after 6 seconds     */
+#define CONFIG_BOOTDELAY       6       /* autoboot after 6 seconds     */
 
 #ifdef DEPLOYMENT
-#define CONFIG_BOOT_RETRY_TIME          -1
+#define CONFIG_BOOT_RETRY_TIME         -1
 #define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT          "autoboot in %d seconds (stop with 'st')...\n"
-#define CONFIG_AUTOBOOT_STOP_STR        "st"
+#define CONFIG_AUTOBOOT_PROMPT         "autoboot in %d seconds (stop with 'st')...\n"
+#define CONFIG_AUTOBOOT_STOP_STR       "st"
 #define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY           1
-#define CONFIG_BOOT_RETRY_MIN           1
+#define CONFIG_RESET_TO_RETRY          1
+#define CONFIG_BOOT_RETRY_MIN          1
 #endif /* DEPLOYMENT */
 #endif /* DEBUG */
 
 /* pre-boot commands */
-#define CONFIG_PREBOOT          "setenv stdout serial;setenv stdin serial"
+#define CONFIG_PREBOOT         "setenv stdout serial;setenv stdin serial"
 
 #undef CONFIG_BOOTARGS
 #define CONFIG_EXTRA_ENV_SETTINGS                                      \
@@ -117,6 +117,36 @@
 
 #define CONFIG_BOOTP_MASK      (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
 
+#if 1         /* Enable this stuff could make image enlarge about 25KB. Mask it if you
+                 don't want the advanced function */
+
+#ifdef CONFIG_SPLASH_SCREEN
+#define CONFIG_COMMANDS              ( CONFIG_CMD_DFL  | \
+                               CFG_CMD_ASKENV  | \
+                               CFG_CMD_BMP     | \
+                               CFG_CMD_JFFS2   | \
+                               CFG_CMD_PING    | \
+                               CFG_CMD_ELF     | \
+                               CFG_CMD_REGINFO | \
+                               CFG_CMD_DHCP    )
+#else
+#define CONFIG_COMMANDS              ( CONFIG_CMD_DFL  | \
+                               CFG_CMD_ASKENV  | \
+                               CFG_CMD_JFFS2   | \
+                               CFG_CMD_PING    | \
+                               CFG_CMD_ELF     | \
+                               CFG_CMD_REGINFO | \
+                               CFG_CMD_DHCP    )
+#endif /* CONFIG_SPLASH_SCREEN */
+
+/* test-only */
+#define CFG_JFFS2_FIRST_BANK   0           /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS    1           /* ! second bank contains U-Boot */
+
+#define CONFIG_NETCONSOLE
+
+#endif /* 1 */
+
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
@@ -280,7 +310,7 @@
 #if defined(RPXlite_64MHz)
 #define CFG_SCCR       ( SCCR_TBS | SCCR_EBDF01 )  /* %%%SCCR:0x02020000 */
 #else
-#define CFG_SCCR        ( SCCR_TBS | SCCR_EBDF00 )  /* %%%SCCR:0x02000000 */
+#define CFG_SCCR       ( SCCR_TBS | SCCR_EBDF00 )  /* %%%SCCR:0x02000000 */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -446,5 +476,6 @@
 #define CONFIG_SERVERIP 172.16.115.6
 #define CONFIG_ROOTPATH /workspace/myfilesystem/target/
 #define CONFIG_BOOTFILE uImage.rpxusb
+#define CONFIG_HOSTNAME LITE_H1_DW
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h
index 6ae9403c4690ce705c3aa2211a6299166f95b545..45907aa0e79f562d05e820f80fcf967445875e55 100644 (file)
--- a/include/configs/RPXsuper.h
+++ b/include/configs/RPXsuper.h
@@ -154,7 +154,6 @@
 #define CONFIG_COMMANDS         ( CONFIG_CMD_DFL | \
                                  CFG_CMD_IMMAP  | \
                                  CFG_CMD_ASKENV | \
-                                 CFG_CMD_ECHO   | \
                                  CFG_CMD_I2C    | \
                                  CFG_CMD_REGINFO & \
                                 ~CFG_CMD_KGDB )

diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
index a170f290e0e876cb0ed718c1d7fff19fadf28d72..dbc57e8b271cd9742ee979da0d82be72a81ecbad 100644 (file)
--- a/include/configs/Rattler.h
+++ b/include/configs/Rattler.h
@@ -127,7 +127,6 @@
 
 #define CONFIG_COMMANDS                (CONFIG_CMD_DFL   \
                                | CFG_CMD_DHCP    \
-                               | CFG_CMD_ECHO    \
                                | CFG_CMD_IMMAP   \
                                | CFG_CMD_JFFS2   \
                                | CFG_CMD_MII     \

diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
index c1c765f39d000e11054924bc8ec58a460af5a475..a8454d99fc0a8fc450048d71cfdc044584aba679 100644 (file)
--- a/include/configs/SXNI855T.h
+++ b/include/configs/SXNI855T.h
@@ -183,6 +183,7 @@
 */
 
 /* NAND flash support */
+#define CFG_NAND_LEGACY
 #define CONFIG_MTD_NAND_ECC_JFFS2
 #define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices   */
 #define SECTORSIZE 512

diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 5ad19394817fed4b3ce3bec0e6815c4ffe140a18..6020998ae20bc0e567aa1c72b90b423372c344d2 100644 (file)
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -161,7 +161,6 @@
                                CFG_CMD_ASKENV  | \
                                CFG_CMD_DATE    | \
                                CFG_CMD_DHCP    | \
-                               CFG_CMD_ECHO    | \
                                CFG_CMD_EEPROM  | \
                                CFG_CMD_I2C     | \
                                CFG_CMD_JFFS2   | \

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 41f44c5a37c977eb84009e3c3490910fc7f6089b..cec7e3ece445d26ee6e7510958411c325705dab4 100644 (file)
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -417,11 +417,58 @@ extern int tqm834x_num_flash_banks;
        HRCWH_TSEC2M_IN_GMII )
 #endif
 
+/* System IO Config */
+#define CFG_SICRH      SICRH_TSOBI1
+#define CFG_SICRL      SICRL_LDP_A
+
 /* i-cache and d-cache disabled */
 #define CFG_HID0_INIT          0x000000000
 #define CFG_HID0_FINAL         CFG_HID0_INIT
 #define CFG_HID2               0x000000000
 
+/* DDR 0 - 512M */
+#define CFG_IBAT0L     (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U     (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT1L     (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U     (CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 512M (no backing mem) */
+#define CFG_IBAT2L     (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT2U     (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* PCI */
+#define CFG_IBAT3L     (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT3U     (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L     (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT4U     (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT5L     (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U     (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
+
+/* IMMRBAR */
+#define CFG_IBAT6L     (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U     (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+
+/* FLASH */
+#define CFG_IBAT7L     (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U     (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L     CFG_IBAT0L
+#define CFG_DBAT0U     CFG_IBAT0U
+#define CFG_DBAT1L     CFG_IBAT1L
+#define CFG_DBAT1U     CFG_IBAT1U
+#define CFG_DBAT2L     CFG_IBAT2L
+#define CFG_DBAT2U     CFG_IBAT2U
+#define CFG_DBAT3L     CFG_IBAT3L
+#define CFG_DBAT3U     CFG_IBAT3U
+#define CFG_DBAT4L     CFG_IBAT4L
+#define CFG_DBAT4U     CFG_IBAT4U
+#define CFG_DBAT5L     CFG_IBAT5L
+#define CFG_DBAT5U     CFG_IBAT5U
+#define CFG_DBAT6L     CFG_IBAT6L
+#define CFG_DBAT6U     CFG_IBAT6U
+#define CFG_DBAT7L     CFG_IBAT7L
+#define CFG_DBAT7U     CFG_IBAT7U
+
 /*
  * Internal Definitions
  *

diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 3f29190e43217d9fe1cb63ecd2a03974db88dc98..5f48a709381f4a39f19a5040972953aaf90c8132 100644 (file)
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -248,6 +248,7 @@
  */
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 
+#define CFG_NAND_LEGACY
 #define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices           */
 #define SECTORSIZE 512
 

diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index 3ca137e53aca281879073e572b2fc476986ee83e..96f3d26cc5eea997c1406a525222030180ac36ba 100644 (file)
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -141,6 +141,8 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
+#define CFG_NAND_LEGACY
+
 #define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices           */
 #define SECTORSIZE 512
 

diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index d92f81f78ee4f6784ef14f678174a0422ebbc6e1..faf855d2492c072fe238a4e978ac7fc7de7204e8 100644 (file)
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -133,6 +133,8 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
+#define CFG_NAND_LEGACY
+
 #define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices           */
 #define SECTORSIZE 512
 

diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
index f71e691b262c417a3c4b3b9c5630b7d4f0085dad..a5085cfb79d52fdfbcc048252dac6845d3f144db 100644 (file)
--- a/include/configs/ZPC1900.h
+++ b/include/configs/ZPC1900.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2003-2004 Arabella Software Ltd.
+ * Copyright (C) 2003-2005 Arabella Software Ltd.
  * Yuli Barcohen <yuli@arabellasw.com>
  *
  * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
@@ -32,11 +32,7 @@
 #define CPU_ID_STR             "MPC8265"
 #define CONFIG_CPM2            1       /* Has a CPM2 */
 
-#undef DEBUG
-
-#undef CONFIG_BOARD_EARLY_INIT_F       /* Don't call board_early_init_f */
-
-/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
 #define CONFIG_ENV_OVERWRITE
 
 /*
@@ -113,7 +109,6 @@
 #define CONFIG_COMMANDS                (CONFIG_CMD_DFL   \
                                | CFG_CMD_ASKENV  \
                                | CFG_CMD_DHCP    \
-                               | CFG_CMD_ECHO    \
                                | CFG_CMD_IMMAP   \
                                | CFG_CMD_MII     \
                                | CFG_CMD_PING    \
@@ -154,31 +149,30 @@
 #define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size  */
 
 #define CFG_MEMTEST_START      0x00100000      /* memtest works on */
-#define CFG_MEMTEST_END                0x00f00000      /* 1 ... 15 MB in DRAM  */
+#define CFG_MEMTEST_END                0x03800000      /* 1 ... 56 MB in DRAM  */
 
-#define CFG_LOAD_ADDR          0x100000        /* default load address */
+#define CFG_LOAD_ADDR          0x400000        /* default load address */
 
 #define CFG_HZ                 1000    /* decrementer freq: 1 ms ticks */
 
 #define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define CFG_FLASH_BASE         0xFFE00000
-#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
-#define CFG_MAX_FLASH_BANKS    1       /* max num of flash banks       */
-#define CFG_MAX_FLASH_SECT     32      /* max num of sects on one chip */
-
-#define CFG_DEFAULT_IMMR       0x0F010000
-
-#define CFG_IMMR               0xF0000000
 #define CFG_SDRAM_BASE         0x00000000
 #define CFG_SDRAM_SIZE         64
-#define CFG_FLSIMM_BASE                0xFC000000
-#define CFG_LSDRAM_BASE                0xFE000000
+
+#define CFG_IMMR               0xF0000000
+#define CFG_LSDRAM_BASE                0xFC000000
+#define CFG_FLASH_BASE         0xFE000000
 #define CFG_BCSR               0xFEA00000
 #define CFG_EEPROM             0xFEB00000
+#define CFG_FLSIMM_BASE                0xFF000000
 
-#define CFG_FLASH_BANKS_LIST   { CFG_FLASH_BASE }
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS    2       /* max num of flash banks       */
+#define CFG_MAX_FLASH_SECT     32      /* max num of sects on one chip */
+
+#define CFG_FLASH_BANKS_LIST   { CFG_FLASH_BASE, CFG_FLSIMM_BASE }
 
 #define BCSR_PCI_MODE          0x01
 
@@ -190,10 +184,10 @@
 
 /* Hard reset configuration word */
 #define CFG_HRCW_MASTER                (HRCW_EBM | HRCW_BPS01| HRCW_CIP          |\
-                                HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\
-                                HRCW_BMS | HRCW_LBPC01 | HRCW_APPC10     |\
-                                HRCW_MODCK_H0101                          \
-                               ) /* 0x16828605 */
+                                HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
+                                HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10     |\
+                                HRCW_MODCK_H0111                          \
+                               ) /* 0x16848207 */
 /* No slaves */
 #define CFG_HRCW_SLAVE1        0
 #define CFG_HRCW_SLAVE2        0
@@ -211,7 +205,7 @@
 #define CFG_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN                (192 << 10)     /* Reserve 192 kB for Monitor   */
+#define CFG_MONITOR_LEN                (256 << 10)     /* Reserve 256 kB for Monitor   */
 #define CFG_MALLOC_LEN         (4096 << 10)    /* Reserve 4 MB for malloc()    */
 #define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
 
@@ -233,14 +227,14 @@
 #  define CFG_CACHELINE_SHIFT  5       /* log base 2 of the above value */
 #endif
 
-#define CFG_HID0_INIT          0
-#define CFG_HID0_FINAL         (HID0_ICE | HID0_IFEM | HID0_ABE )
+#define CFG_HID0_INIT          (HID0_ICFI)
+#define CFG_HID0_FINAL         (HID0_ICE | HID0_IFEM | HID0_ABE)
 
 #define CFG_HID2               0
 
 #define CFG_SIUMCR             0x42200000
 #define CFG_SYPCR              0xFFFFFFC3
-#define CFG_BCR                        0x90400000
+#define CFG_BCR                        0x90000000
 #define CFG_SCCR               SCCR_DFBRG01
 
 #define CFG_RMR                        RMR_CSRE
@@ -248,18 +242,23 @@
 #define CFG_PISCR              (PISCR_PS|PISCR_PTF|PISCR_PTE)
 #define CFG_RCCR               0
 
-#define CFG_PSDMR              0x014EB45A
-#define CFG_PSRT               0x0C
-#define CFG_LSDMR              0x008AB552
-#define CFG_LSRT               0x0E
+#define CFG_PSDMR              /* 0x834DA43B */0x014DA43A
+#define CFG_PSRT               0x0F/* 0x0C */
+#define CFG_LSDMR              0x0085A562
+#define CFG_LSRT               0x0F
 #define CFG_MPTPR              0x4000
 
+#define CFG_PSDRAM_BR          CFG_SDRAM_BASE | 0x00000041
+#define CFG_PSDRAM_OR          0xFC0028C0
+#define CFG_LSDRAM_BR          CFG_LSDRAM_BASE | 0x00001861
+#define CFG_LSDRAM_OR          0xFF803480
+
 #define CFG_BR0_PRELIM         CFG_FLASH_BASE | 0x00000801
 #define CFG_OR0_PRELIM         0xFFE00856
 #define CFG_BR5_PRELIM         CFG_EEPROM | 0x00000801
 #define CFG_OR5_PRELIM         0xFFFF03F6
-#define CFG_BR6_PRELIM         CFG_FLSIMM_BASE | 0x00000801
-#define CFG_OR6_PRELIM         0xFE000856
+#define CFG_BR6_PRELIM         CFG_FLSIMM_BASE | 0x00001801
+#define CFG_OR6_PRELIM         0xFF000856
 #define CFG_BR7_PRELIM         CFG_BCSR | 0x00000801
 #define CFG_OR7_PRELIM         0xFFFF83F6
 

diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index eacc74446cebc27bb9a6e20b6c2769838252b731..6d3282150d7686dccebc503fb8b72a0dd8203a85 100644 (file)
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -43,6 +43,7 @@
  * 2nd ethernet port you have to "undef" the following define.
  */
 #define CONFIG_BAMBOO_NAND      1       /* enable nand flash support    */
+#define CFG_NAND_LEGACY
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the

diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 0a10e3c75b4c0bdd6c5d9c97afaa95f880c455fd..4cc5085293b430d0187b1856ba205a4f62327811 100644 (file)
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -81,8 +81,7 @@
                                   CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \
                                   CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C))
 #else /* CONFIG_DBAU1550 */
-/* Boot from Compact flash partition 2 as default */
-#define CONFIG_BOOTCOMMAND     "ide reset;disk 0x81000000 0:2;bootm"
+#define CONFIG_BOOTCOMMAND     "bootp;bootm"
 
 #define CONFIG_COMMANDS                ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \
                                 ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
@@ -133,8 +132,6 @@
 #define PHYS_FLASH_1           0xb8000000 /* Flash Bank #1 */
 #define PHYS_FLASH_2           0xbc000000 /* Flash Bank #2 */
 
-#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
-
 #else /* CONFIG_DBAU1550 */
 
 #define CFG_MAX_FLASH_BANKS    2       /* max number of memory banks */
@@ -145,6 +142,8 @@
 
 #endif /* CONFIG_DBAU1550 */
 
+#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
+
 #define CFG_FLASH_CFI           1
 #define CFG_FLASH_CFI_DRIVER    1
 

diff --git a/include/configs/delta.h b/include/configs/delta.h
new file mode 100644 (file)
index 0000000..e4c8cca
--- /dev/null
+++ b/include/configs/delta.h
@@ -0,0 +1,231 @@
+/*
+ * Configuation settings for the Delta board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_CPU_MONAHANS    1       /* Intel Monahan CPU    */
+#define CONFIG_DELTA           1       /* Delta board       */
+
+/* #define CONFIG_LCD          1 */
+#ifdef CONFIG_LCD
+#define CONFIG_SHARP_LM8V31
+#endif
+/* #define CONFIG_MMC          1 */
+#define BOARD_LATE_INIT                1
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#undef CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN     (CFG_ENV_SIZE + 256*1024)
+#define CFG_GBL_DATA_SIZE      128     /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#undef TURN_ON_ETHERNET
+#ifdef TURN_ON_ETHERNET
+# define CONFIG_DRIVER_SMC91111 1
+# define CONFIG_SMC91111_BASE   0x14000300
+# define CONFIG_SMC91111_EXT_PHY
+# define CONFIG_SMC_USE_32_BIT
+# undef CONFIG_SMC_USE_IOFUNCS          /* just for use with the kernel */
+#endif
+
+#define CONFIG_HARD_I2C                1       /* required for DA9030 access */
+#define CFG_I2C_SPEED          400000  /* I2C speed */
+#define CFG_I2C_SLAVE          1       /* I2C controllers address */
+#define DA9030_I2C_ADDR                0x49    /* I2C address of DA9030 */
+#define CFG_DA9030_EXTON_DELAY 100000  /* wait x us after DA9030 reset via EXTON */
+#define CFG_I2C_INIT_BOARD     1
+/* #define CONFIG_HW_WATCHDOG  1       /\* Required for hitting the DA9030 WD *\/ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART          1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE                115200
+
+/* #define CONFIG_COMMANDS       (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
+#ifdef TURN_ON_ETHERNET
+# define CONFIG_COMMANDS        (CONFIG_CMD_DFL | CFG_CMD_PING)
+#else
+# define CONFIG_COMMANDS       ((CONFIG_CMD_DFL \
+                                 | CFG_CMD_ENV \
+                                 | CFG_CMD_NAND \
+                                 | CFG_CMD_I2C) \
+                                & ~(CFG_CMD_NET \
+                                    | CFG_CMD_FLASH \
+                                    | CFG_CMD_IMLS))
+#endif
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY       -1
+#define CONFIG_ETHADDR         08:00:3e:26:0a:5b
+#define CONFIG_NETMASK         255.255.0.0
+#define CONFIG_IPADDR          192.168.0.21
+#define CONFIG_SERVERIP                192.168.0.250
+#define CONFIG_BOOTCOMMAND     "bootm 80000"
+#define CONFIG_BOOTARGS                "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_TIMESTAMP
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE   230400          /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX  2               /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER                1
+#define CFG_PROMPT_HUSH_PS2    "> "
+
+#define CFG_LONGHELP                           /* undef to save memory         */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT             "$ "            /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT             "=> "           /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE             256             /* Console I/O Buffer Size      */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS            16              /* max number of command args   */
+#define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size    */
+#define CFG_DEVICE_NULLDEV     1
+
+#define CFG_MEMTEST_START      0x80400000      /* memtest works on     */
+#define CFG_MEMTEST_END                0x80800000      /* 4 ... 8 MB in DRAM   */
+
+#undef CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR  (CFG_DRAM_BASE + 0x8000) /* default load address */
+
+#define CFG_HZ                 3250000         /* incrementer freq: 3.25 MHz */
+
+/* Monahans Core Frequency */
+#define CFG_MONAHANS_RUN_MODE_OSC_RATIO                16 /* valid values: 8, 16, 24, 31 */
+#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO      1  /* valid values: 1, 2 */
+
+
+                                               /* valid baudrates */
+#define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
+
+/* #define CFG_MMC_BASE                0xF0000000 */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE       (128*1024)      /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ   (4*1024)        /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ   (4*1024)        /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS   4          /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1           0x80000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE      0x1000000  /* 64 MB */
+#define PHYS_SDRAM_2           0x81000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE      0x1000000  /* 64 MB */
+#define PHYS_SDRAM_3           0x82000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE      0x1000000  /* 64 MB */
+#define PHYS_SDRAM_4           0x83000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE      0x1000000  /* 64 MB */
+
+#define CFG_DRAM_BASE          0x80000000 /* at CS0 */
+#define CFG_DRAM_SIZE          0x04000000 /* 64 MB Ram */
+
+#undef CFG_SKIP_DRAM_SCRUB
+
+/*
+ * NAND Flash
+ */
+/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
+#undef CFG_NAND_LEGACY
+
+#define CFG_NAND0_BASE         0x0 /* 0x43100040 */ /* 0x10000000 */
+#undef CFG_NAND1_BASE
+
+#define CFG_NAND_BASE_LIST     { CFG_NAND0_BASE }
+#define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices */
+
+/* nand timeout values */
+#define CFG_NAND_PROG_ERASE_TO 3000
+#define CFG_NAND_OTHER_TO      100
+#define CFG_NAND_SENDCMD_RETRY 3
+#undef NAND_ALLOW_ERASE_ALL    /* Allow erasing bad blocks - don't use */
+
+/* NAND Timing Parameters (in ns) */
+#define NAND_TIMING_tCH                10
+#define NAND_TIMING_tCS                0
+#define NAND_TIMING_tWH                20
+#define NAND_TIMING_tWP                40
+
+#define NAND_TIMING_tRH                20
+#define NAND_TIMING_tRP                40
+
+#define NAND_TIMING_tR         11123
+#define NAND_TIMING_tWHR       100
+#define NAND_TIMING_tAR                10
+
+/* NAND debugging */
+#define CFG_DFC_DEBUG1 /* usefull */
+#undef CFG_DFC_DEBUG2  /* noisy */
+#undef CFG_DFC_DEBUG3  /* extremly noisy  */
+
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 1
+
+#define ADDR_COLUMN            1
+#define ADDR_PAGE              2
+#define ADDR_COLUMN_PAGE       3
+
+#define NAND_ChipID_UNKNOWN    0x00
+#define NAND_MAX_FLOORS                1
+#define NAND_MAX_CHIPS         1
+
+#define CFG_NO_FLASH           1
+
+#define CFG_ENV_IS_IN_NAND     1
+#define CFG_ENV_OFFSET         0x40000
+#define CFG_ENV_OFFSET_REDUND  0x44000
+#define CFG_ENV_SIZE           0x4000
+
+#endif /* __CONFIG_H */

diff --git a/include/configs/ezkit533.h b/include/configs/ezkit533.h
new file mode 100644 (file)
index 0000000..5eda673
--- /dev/null
+++ b/include/configs/ezkit533.h
@@ -0,0 +1,188 @@
+#ifndef __CONFIG_EZKIT533_H__
+#define __CONFIG_EZKIT533_H__
+
+#define CFG_LONGHELP           1
+#define CONFIG_BAUDRATE                57600
+#define CONFIG_STAMP           1
+#define CONFIG_BOOTDELAY       5
+
+#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_SMC91111_BASE   0x20310300
+#if 0
+#define CONFIG_MII
+#define CFG_DISCOVER_PHY
+#endif
+
+#define CONFIG_RTC_BF533       1
+#define CONFIG_BOOT_RETRY_TIME -1      /* Enable this if bootretry required, currently its disabled */
+
+/* CONFIG_CLKIN_HZ is any value in Hz                           */
+#define CONFIG_CLKIN_HZ                 27000000
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN     */
+/*                                                 1=CLKIN/2    */
+#define CONFIG_CLKIN_HALF              0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass         */
+/*                                              1=bypass PLL    */
+#define CONFIG_PLL_BYPASS              0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.  */
+/* Values can range from 1-64                                   */
+#define CONFIG_VCO_MULT                        22
+/* CONFIG_CCLK_DIV controls what the core clock divider is      */
+/* Values can be 1, 2, 4, or 8 ONLY                             */
+#define CONFIG_CCLK_DIV                        1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
+/* Values can range from 1-15                                   */
+#define CONFIG_SCLK_DIV                        5
+
+#if ( CONFIG_CLKIN_HALF == 0 )
+#define CONFIG_VCO_HZ          ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#else
+#define CONFIG_VCO_HZ          (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#endif
+
+#if (CONFIG_PLL_BYPASS == 0)
+#define CONFIG_CCLK_HZ         ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ         ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#else
+#define CONFIG_CCLK_HZ         CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ         CONFIG_CLKIN_HZ
+#endif
+
+#define CONFIG_MEM_SIZE                        32             /* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH             9             /* 8, 9, 10, 11    */
+#define CONFIG_MEM_MT48LC16M16A2TG_75   1
+
+#define CONFIG_LOADS_ECHO      1
+
+
+#define CONFIG_COMMANDS                        (CONFIG_CMD_DFL | \
+                                        CFG_CMD_PING   | \
+                                        CFG_CMD_ELF    | \
+                                        CFG_CMD_I2C    | \
+                                        CFG_CMD_JFFS2  | \
+                                        CFG_CMD_DATE)
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off"
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_PROMPT             "ezkit> "       /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE             1024    /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE             256     /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE             (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)      /* Print Buffer Size */
+#define CFG_MAXARGS            16      /* max number of command args */
+#define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size */
+#define CFG_MEMTEST_START      0x00100000      /* memtest works on */
+#define CFG_MEMTEST_END                0x01F00000      /* 1 ... 31 MB in DRAM */
+#define CFG_LOAD_ADDR          0x01000000      /* default load address */
+#define CFG_HZ                 1000    /* decrementer freq: 10 ms ticks */
+#define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_SDRAM_BASE         0x00000000
+#define CFG_MAX_RAM_SIZE       0x02000000
+#define CFG_FLASH_BASE         0x20000000
+
+#define CFG_MONITOR_LEN                (256 << 10)     /* Reserve 256 kB for Monitor   */
+#define CFG_MONITOR_BASE       (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
+#define CFG_MALLOC_LEN         (128 << 10)     /* Reserve 128 kB for malloc()  */
+#define CFG_MALLOC_BASE                (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_SIZE      0x4000
+#define CFG_GBL_DATA_ADDR      (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE       (CFG_GBL_DATA_ADDR  - 4)
+
+#define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
+#define CFG_FLASH0_BASE                0x20000000
+#define CFG_FLASH1_BASE                0x20200000
+#define CFG_FLASH2_BASE                0x20280000
+#define CFG_MAX_FLASH_BANKS    3       /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT     40      /* max number of sectors on one chip */
+
+#define CFG_ENV_IS_IN_FLASH    1
+#define CFG_ENV_ADDR           0x20020000
+#define CFG_ENV_SECT_SIZE      0x10000 /* Total Size of Environment Sector */
+
+/* JFFS Partition offset set  */
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS  1
+/* 512k reserved for u-boot */
+#define CFG_JFFS2_FIRST_SECTOR                11
+
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE       (128*1024)      /* regular stack */
+
+#define POLL_MODE              1
+#define FLASH_TOT_SECT         40
+#define FLASH_SIZE             0x220000
+#define CFG_FLASH_SIZE         0x220000
+
+/*
+ * Initialize PSD4256 registers for using I2C
+ */
+#define CONFIG_MISC_INIT_R
+
+/*
+ * I2C settings
+ * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
+ */
+#define CONFIG_SOFT_I2C                        1       /* I2C bit-banged               */
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PF_SCL                         PF0
+#define PF_SDA                         PF1
+
+#define I2C_INIT                       (*pFIO_DIR |=  PF_SCL); asm("ssync;")
+#define I2C_ACTIVE                     (*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE                   (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ                       ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
+#define I2C_SDA(bit)                   if(bit) { \
+                                                       *pFIO_FLAG_S = PF_SDA; \
+                                                       asm("ssync;"); \
+                                               } \
+                                       else    { \
+                                                       *pFIO_FLAG_C = PF_SDA; \
+                                                       asm("ssync;"); \
+                                               }
+#define I2C_SCL(bit)                   if(bit) { \
+                                                       *pFIO_FLAG_S = PF_SCL; \
+                                                       asm("ssync;"); \
+                                               } \
+                                       else    { \
+                                                       *pFIO_FLAG_C = PF_SCL; \
+                                                       asm("ssync;"); \
+                                               }
+#define I2C_DELAY                      udelay(5)       /* 1/4 I2C clock duration */
+
+#define CFG_I2C_SPEED                  50000
+#define CFG_I2C_SLAVE                  0xFE
+
+
+#define __ADSPLPBLACKFIN__     1
+#define __ADSPBF533__          1
+
+/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
+/* #define AMGCTLVAL           (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL             (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL |    \
+                               ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
+#define AMBCTL1VAL             (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN |   \
+                               B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
+*/
+#define AMGCTLVAL              0xFF
+#define AMBCTL0VAL             0x7BB07BB0
+#define AMBCTL1VAL             0xFFC27BB0
+
+#define CONFIG_VDSP            1
+
+#ifdef CONFIG_VDSP
+#define ET_EXEC_VDSP           0x8
+#define SHT_STRTAB_VDSP                0x1
+#define ELFSHDRSIZE_VDSP       0x2C
+#define VDSP_ENTRY_ADDR                0xFFA00000
+#endif
+
+#endif

diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
index 6c080437ffa91325efdfa3a1cabd1629c873951c..4f83b1945d305ac0943c78a4031db34b090d949e 100644 (file)
--- a/include/configs/gw8260.h
+++ b/include/configs/gw8260.h
@@ -305,7 +305,6 @@
                               CFG_CMD_BEDBUG  | \
                               CFG_CMD_ELF | \
                               CFG_CMD_ASKENV  | \
-                              CFG_CMD_ECHO    | \
                               CFG_CMD_REGINFO | \
                               CFG_CMD_IMMAP   | \
                               CFG_CMD_MII)

diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index c0cc4f1fbecc88926dff31cf5ee58e9616ca899b..773d5d2c1d963374b0923f8da78e359fbe0390b8 100644 (file)
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -101,7 +101,7 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds */
+#define CONFIG_BOOTDELAY       1       /* autoboot after 1 second */
 
 #define CONFIG_PREBOOT "echo;" \
        "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
@@ -109,6 +109,16 @@
 
 #undef CONFIG_BOOTARGS
 
+#define        CONFIG_ETHADDR          00:a0:a4:03:00:00
+#define        CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#define        CONFIG_IPADDR           192.168.100.2
+#define        CONFIG_SERVERIP         192.168.100.1
+#define        CONFIG_NETMASK          255.255.255.0
+#define HOSTNAME               inka4x0
+#define CONFIG_BOOTFILE                /tftpboot/inka4x0/uImage
+#define        CONFIG_ROOTPATH         /opt/eldk/ppc_6xx
+
 #define CONFIG_EXTRA_ENV_SETTINGS                                      \
        "netdev=eth0\0"                                                 \
        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
@@ -117,13 +127,22 @@
        "addip=setenv bootargs ${bootargs} "                            \
                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
                ":${hostname}:${netdev}:off panic=1\0"                  \
-       "flash_nfs=run nfsargs addip;"                                  \
+       "addcons=setenv bootargs ${bootargs} "                          \
+               "console=ttyS0,${baudrate}\0"                           \
+       "flash_nfs=run nfsargs addip addcons;"                          \
                "bootm ${kernel_addr}\0"                                \
-       "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
-       "rootpath=/opt/eldk/ppc_82xx\0"                                 \
+       "net_nfs=tftp 200000 ${bootfile};"                              \
+               "run nfsargs addip addcons;bootm\0"                     \
+       "enable_disp=mw.l 100000 04000000 1;"                           \
+               "cp.l 100000 f0000b20 1;"                               \
+               "cp.l 100000 f0000b28 1\0"                              \
+       "ideargs=setenv bootargs root=/dev/hda1 rw\0"                   \
+       "ide_boot=ext2load ide 0:1 200000 uImage;"                      \
+               "run ideargs addip addcons enable_disp;bootm"           \
+       "brightness=255\0"                                              \
        ""
 
-#define CONFIG_BOOTCOMMAND     "run net_nfs"
+#define CONFIG_BOOTCOMMAND     "run ide_boot"
 
 /*
  * IPB Bus clocking configuration.
@@ -193,6 +212,7 @@
  */
 /* #define CONFIG_FEC_10MBIT 1 */
 #define CONFIG_PHY_ADDR                0x00
+#define CONFIG_MII
 
 /*
  * GPIO configuration

diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
new file mode 100644 (file)
index 0000000..2b1c0d0
--- /dev/null
+++ b/include/configs/mcc200.h
@@ -0,0 +1,267 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200
+#define CONFIG_MPC5xxx         1       /* This is an MPC5xxx CPU               */
+#define CONFIG_MCC200          1       /* ... on MCC200 board                  */
+
+#define CFG_MPC5XXX_CLKIN      33000000 /* ... running at 33MHz                */
+
+#define CONFIG_MISC_INIT_R
+
+#define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from FLASH     */
+#define BOOTFLAG_WARM          0x02    /* Software reboot                      */
+
+#define CFG_CACHELINE_SIZE     32      /* For MPC5xxx CPUs                     */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT  5       /* log base 2 of the above value        */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE     1       /* console is on PSC1                   */
+#define CONFIG_BAUDRATE                115200
+#define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_MII             1
+
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS               (CONFIG_CMD_DFL  | \
+                               ADD_USB_CMD     | \
+                               CFG_CMD_BEDBUG  | \
+                               CFG_CMD_FAT     | \
+                               CFG_CMD_I2C)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+       "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+       "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
+       "netdev=eth0\0"                                                 \
+       "hostname=mcc200\0"                                             \
+       "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
+               "nfsroot=${serverip}:${rootpath}\0"                     \
+       "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
+       "addip=setenv bootargs ${bootargs} "                            \
+               "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
+               ":${hostname}:${netdev}:off panic=1\0"                  \
+       "flash_nfs=run nfsargs addip;"                                  \
+               "bootm ${kernel_addr}\0"                                \
+       "flash_self=run ramargs addip;"                                 \
+               "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
+       "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
+       "rootpath=/opt/eldk/ppc_6xx\0"                                  \
+       "bootfile=/tftpboot/mcc200/uImage\0"                            \
+       "baudrate=115200\0"                                             \
+       "load=tftp 200000 /tftpboot/mcc200/u-boot.bin\0"                \
+       "update=protect off FFF00000 +${filesize};"                     \
+               "era FFF00000 +${filesize};"                            \
+               "cp.b 200000 FFF00000 ${filesize}\0"                    \
+       "serverip=192.168.1.1\0"                                        \
+       "ipaddr=192.168.133.144\0"                                      \
+       "netmask=255.255.0.0\0"                                         \
+       "unlock=yes\0"                                                  \
+       "ethaddr=00:02:44:7D:73:3B\0"                                   \
+       ""
+
+#define CONFIG_BOOTCOMMAND     "run flash_self"
+
+#define CFG_HUSH_PARSER                1       /* use "hush" command parser    */
+#define CFG_PROMPT_HUSH_PS2    "> "
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133               /* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C                1       /* I2C with hardware support */
+#define CFG_I2C_MODULE         1       /* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED          100000 /* 100 kHz */
+#define CFG_I2C_SLAVE          0x7F
+
+/*
+ * Flash configuration (8,16 or 32 MB)
+ * TEXT base always at 0xFFF00000
+ * ENV_ADDR always at  0xFFF40000
+ * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
+ *               0xFE000000 for 32 MB
+ *               0xFF000000 for 16 MB
+ *               0xFF800000 for  8 MB
+ */
+#define CFG_FLASH_BASE         0xfc000000
+#define CFG_FLASH_SIZE         0x04000000
+
+#define CFG_FLASH_CFI                          /* The flash is CFI compatible  */
+#define CFG_FLASH_CFI_DRIVER                   /* Use common CFI driver        */
+
+#define CFG_FLASH_BANKS_LIST   { CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS    1       /* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT     512     /* max number of sectors on one chip    */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1   /* use buffered writes (20x faster)     */
+#define CFG_FLASH_PROTECTION   1       /* hardware flash protection            */
+
+#define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
+#define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)      */
+
+#define CFG_FLASH_EMPTY_INFO           /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST   1       /* don't warn upon unknown flash        */
+
+#define CFG_ENV_IS_IN_FLASH     1      /* use FLASH for environment vars       */
+
+#define CFG_ENV_SECT_SIZE      0x40000         /* size of one complete sector  */
+#define CFG_ENV_ADDR           (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define        CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
+
+/* Address and size of Redundant Environment Sector    */
+#define CFG_ENV_ADDR_REDUND    (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND    (CFG_ENV_SIZE)
+
+#define CONFIG_ENV_OVERWRITE   1       /* allow modification of vendor params */
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR               0xf0000000
+#define CFG_SDRAM_BASE         0x00000000
+#define CFG_DEFAULT_MBAR       0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR      MPC5XXX_SRAM
+#define CFG_INIT_RAM_END       MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
+
+
+#define CFG_GBL_DATA_SIZE      128     /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT         1
+#endif
+
+#define CFG_MONITOR_LEN                (256 << 10)     /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN         (512 << 10)     /* Reserve 512 kB for malloc()  */
+#define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC     1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR                1
+
+/*
+ * GPIO configuration
+ */
+/* 0x10000004 = 32MB SDRAM */
+/* 0x90000004 = 64MB SDRAM */
+#define CFG_GPS_PORT_CONFIG    0x00000004
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                   /* undef to save memory     */
+#define CFG_PROMPT             "=> "   /* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE             1024    /* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE             256     /* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
+#define CFG_MAXARGS            16              /* max number of command args   */
+#define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START      0x00100000      /* memtest works on */
+#define CFG_MEMTEST_END                0x00f00000      /* 1 ... 15 MB in DRAM  */
+
+#define CFG_LOAD_ADDR          0x100000        /* default load address */
+
+#define CFG_HZ                 1000    /* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT          HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL         HID0_ICE
+
+#define CFG_BOOTCS_START       CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE                CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG         0x0004fb00
+#define CFG_CS0_START          CFG_FLASH_BASE
+#define CFG_CS0_SIZE           CFG_FLASH_SIZE
+
+/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
+#define CFG_CS2_START          0x80000000
+#define CFG_CS2_SIZE           0x00001000
+#define CFG_CS2_CFG            0x1d300
+
+#define CFG_CS_BURST           0x00000000
+#define CFG_CS_DEADCYCLE       0x33333333
+
+#define CFG_RESET_ADDRESS      0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK       0x0001BBBB
+#define CONFIG_USB_CONFIG      0x00005000
+
+#endif /* __CONFIG_H */

diff --git a/include/configs/netstar.h b/include/configs/netstar.h
new file mode 100644 (file)
index 0000000..697796a
--- /dev/null
+++ b/include/configs/netstar.h
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
+ *
+ * Configuation settings for the TI OMAP NetStar board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/omap1510.h>
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM925T 1               /* This is an arm925t CPU */
+#define CONFIG_OMAP    1               /* in a TI OMAP core */
+#define CONFIG_OMAP1510 1              /* which is in a 5910 */
+
+/* Input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ    150000000       /* 150MHz input clock */
+#define CONFIG_XTAL_FREQ       12000000
+
+#undef CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R             /* There is nothing to really init */
+#define BOARD_LATE_INIT                        /* but we flash the LEDs here */
+
+#define CONFIG_CMDLINE_TAG             1       /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS       1
+#define CONFIG_INITRD_TAG              1
+
+#define CFG_DEVICE_NULLDEV             1       /* enable null device */
+#define CONFIG_SILENT_CONSOLE          1       /* enable silent startup */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS   1               /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1           0x10000000      /* SDRAM Bank #1 */
+#define PHYS_FLASH_1           0x00000000      /* Flash Bank #1 */
+
+/*
+ * FLASH organization
+ */
+#define CFG_FLASH_BASE         PHYS_FLASH_1
+#define CFG_MAX_FLASH_BANKS    1
+#if (PHYS_SDRAM_1_SIZE == SZ_32M)
+/*#if 1*/
+#define CFG_FLASH_CFI                  /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER           /* Use the common driver */
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_MAX_FLASH_SECT     128
+#else
+#define PHYS_FLASH_1_SIZE      SZ_1M
+#define CFG_MAX_FLASH_SECT     19
+#define CFG_FLASH_ERASE_TOUT   (5*CFG_HZ) /* in ticks */
+#define CFG_FLASH_WRITE_TOUT   (5*CFG_HZ)
+#endif
+
+#define CFG_MONITOR_BASE       PHYS_FLASH_1
+#define CFG_MONITOR_LEN                SZ_256K
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH
+#define ENV_IS_SOLITARY
+#define CFG_ENV_ADDR           0x4000
+#define CFG_ENV_SIZE           SZ_8K
+#define CFG_ENV_SECT_SIZE      SZ_8K
+#define CFG_ENV_ADDR_REDUND    0x6000
+#define CFG_ENV_SIZE_REDUND    CFG_ENV_SIZE
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_GBL_DATA_SIZE      128     /* size in bytes reserved for initial data */
+/* XXX #define CFG_MALLOC_LEN          (SZ_64K - CFG_GBL_DATA_SIZE)*/
+#define CFG_MALLOC_LEN         SZ_4M
+
+/*
+ * The stack size is set up in start.S using the settings below
+ */
+/* XXX #define CONFIG_STACKSIZE        SZ_8K   /XXX* regular stack */
+#define CONFIG_STACKSIZE       SZ_1M   /* regular stack */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE   0x04000300
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE   (-4)
+#define CFG_NS16550_CLK                (CONFIG_XTAL_FREQ)      /* can be 12M/32Khz or 48Mhz  */
+#define CFG_NS16550_COM1       OMAP1510_UART1_BASE     /* uart1 */
+
+#define CONFIG_CONS_INDEX      1
+#define CONFIG_BAUDRATE                115200
+#define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
+
+/*#define CONFIG_SKIP_RELOCATE_UBOOT*/
+/*#define CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*
+ * NAND flash
+ */
+#define CFG_MAX_NAND_DEVICE    1
+#define NAND_MAX_CHIPS         1
+#define CFG_NAND_BASE  0x04000000 + (2 << 23)
+
+/*
+ * JFFS2 partitions (mtdparts command line support)
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT         "nor0=omapflash.0,nand0=omapnand.0"
+#define MTDPARTS_DEFAULT       "mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)"
+
+#if 0
+#define CONFIG_COMMANDS                (CFG_CMD_BDI    | \
+                                CFG_CMD_BOOTD  | \
+                                CFG_CMD_DHCP   | \
+                                CFG_CMD_ENV    | \
+                                CFG_CMD_FLASH  | \
+                                CFG_CMD_IMI    | \
+                                CFG_CMD_LOADB  | \
+                                CFG_CMD_NET    | \
+                                CFG_CMD_MEMORY | \
+                                CFG_CMD_PING   | \
+                                CFG_CMD_RUN)
+
+#else
+#define CONFIG_COMMANDS                (CFG_CMD_BDI    | \
+                                CFG_CMD_BOOTD  | \
+                                CFG_CMD_DHCP   | \
+                                CFG_CMD_ENV    | \
+                                CFG_CMD_FLASH  | \
+                                CFG_CMD_NAND   | \
+                                CFG_CMD_IMI    | \
+                                CFG_CMD_JFFS2  | \
+                                CFG_CMD_LOADB  | \
+                                CFG_CMD_NET    | \
+                                CFG_CMD_MEMORY | \
+                                CFG_CMD_PING   | \
+                                CFG_CMD_RUN)
+
+#define CONFIG_JFFS2_NAND      1       /* jffs2 on nand support */
+#endif
+
+#define CONFIG_BOOTP_MASK      CONFIG_BOOTP_DEFAULT
+#define CONFIG_LOOPW
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY       3
+#define CONFIG_ZERO_BOOTDELAY_CHECK    /* allow to break in always */
+#undef  CONFIG_BOOTARGS                /* the boot command will set bootargs*/
+#define CFG_AUTOLOAD           "n"             /* No autoload */
+#define CONFIG_BOOTCOMMAND     "run nboot"
+#define CONFIG_PREBOOT         "run setup"
+#define        CONFIG_EXTRA_ENV_SETTINGS                               \
+       "setup=setenv bootargs console=ttyS0,$baudrate "        \
+               "$mtdparts\0"                                   \
+       "ospart=0\0"                                            \
+       "setpart="                                              \
+       "if test -n $swapos; then "                             \
+               "if test $ospart -eq 0; then chpart nand0,1; else chpart nand0,0; fi; "\
+               "setenv swapos; saveenv; "                      \
+       "else "                                                 \
+               "chpart nand0,$ospart; "                        \
+       "fi\0"                                                  \
+       "nfsargs=setenv bootargs $bootargs "                    \
+               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
+               "nfsroot=$rootpath root=/dev/nfs\0"             \
+       "flashargs=run setpart;setenv bootargs $bootargs "      \
+               "root=/dev/mtdblock$partition ro "              \
+               "rootfstype=jffs2\0"                            \
+       "initrdargs=setenv bootargs $bootargs "                 \
+               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
+       "iboot=bootp;run initrdargs;tftp;bootm\0"               \
+       "fboot=run flashargs;fsload /boot/uImage;bootm\0"       \
+       "nboot=bootp;run nfsargs;tftp;bootm\0"
+
+#if 0  /* feel free to disable for development */
+#define        CONFIG_AUTOBOOT_KEYED           /* Enable password protection   */
+#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d sec...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR      "R"     /* 1st "password"       */
+#define CONFIG_BOOT_RETRY_TIME 30
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                           /* undef to save memory         */
+#define CFG_PROMPT             "# "            /* Monitor Command Prompt       */
+#define CFG_CBSIZE             256             /* Console I/O Buffer Size      */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS            16              /* max number of command args   */
+#define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size    */
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2    "> "
+#define CONFIG_AUTO_COMPLETE
+
+#define CFG_MEMTEST_START      PHYS_SDRAM_1
+#define CFG_MEMTEST_END                PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE
+
+#undef CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR          PHYS_SDRAM_1 + 0x400000 /* default load address */
+
+/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
+ * This time is further subdivided by a local divisor.
+ */
+#define CFG_TIMERBASE          OMAP1510_TIMER1_BASE
+#define CFG_PVT                        7               /* 2^(pvt+1), divide by 256 */
+#define CFG_HZ                 ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+#define OMAP5910_DPLL_DIV      1
+#define OMAP5910_DPLL_MUL      ((CONFIG_SYS_CLK_FREQ * \
+                                (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
+
+#define OMAP5910_ARM_PER_DIV   2       /* CKL/4 */
+#define OMAP5910_LCD_DIV       2       /* CKL/4 */
+#define OMAP5910_ARM_DIV       0       /* CKL/1 */
+#define OMAP5910_DSP_DIV       0       /* CKL/1 */
+#define OMAP5910_TC_DIV                1       /* CKL/2 */
+#define OMAP5910_DSP_MMU_DIV   1       /* CKL/2 */
+#define OMAP5910_ARM_TIM_SEL   1       /* CKL used for MPU timers */
+
+#define OMAP5910_ARM_EN_CLK    0x03d6  /* 0000 0011 1101 0110b  Clock Enable */
+#define OMAP5910_ARM_CKCTL     ((OMAP5910_ARM_PER_DIV)  |      \
+                                (OMAP5910_LCD_DIV << 2) |      \
+                                (OMAP5910_ARM_DIV << 4) |      \
+                                (OMAP5910_DSP_DIV << 6) |      \
+                                (OMAP5910_TC_DIV << 8) |       \
+                                (OMAP5910_DSP_MMU_DIV << 10) | \
+                                (OMAP5910_ARM_TIM_SEL << 12))
+
+#endif /* __CONFIG_H */

diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
index 12252ac129e096251d9013e02ea890f5d22852a5..58374616a14afb52f060792504dbe1e0055c49c9 100644 (file)
--- a/include/configs/omap2420h4.h
+++ b/include/configs/omap2420h4.h
@@ -132,6 +132,7 @@
 /*
  *  Board NAND Info.
  */
+#define CFG_NAND_LEGACY
 #define CFG_NAND_ADDR 0x04000000  /* physical address to access nand at CS0*/
 
 #define CFG_MAX_NAND_DEVICE 1  /* Max number of NAND devices */

diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index 831d018e2d47c3abc61c0806b2abc7d0bb19ba01..aa0901f3ff467d8a04d7844485a681e348b0c0fe 100644 (file)
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2006
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
@@ -71,9 +71,10 @@
  * DDR SDRAM
  *----------------------------------------------------------------------*/
 #define CONFIG_SDRAM_BANK0     1       /* init onboard DDR SDRAM bank 0*/
-#define CFG_SDRAM_TABLE        {       \
-               {(256 << 20), 0x000C4001}, /* 256MB mode 3, 13x10(4) */ \
-               {(64 << 20),  0x00082001}} /* 64MB mode 2, 12x9(4)   */
+#define CONFIG_SDRAM_ECC               /* enable ECC support           */
+#define CFG_SDRAM_TABLE        { \
+               {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
+               {(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)  */
 
 /*-----------------------------------------------------------------------
  * Serial Port
@@ -146,6 +147,7 @@
                "cp.b 100000 fffc0000 40000;"                           \
                "setenv filesize;saveenv\0"                             \
        "upd=run load;run update\0"                                     \
+       "unlock=yes\0"                                                  \
        ""
 #define CONFIG_BOOTCOMMAND     "run net_nfs"
 
@@ -275,6 +277,9 @@
 #define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
 #define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)      */
 
+#define CFG_FLASH_USE_BUFFER_WRITE 1   /* use buffered writes (20x faster)     */
+#define CFG_FLASH_PROTECTION   1       /* use hardware flash protection        */
+
 #define CFG_FLASH_EMPTY_INFO           /* print 'E' for empty sector on flinfo */
 #define CFG_FLASH_QUIET_TEST   1       /* don't warn upon unknown flash        */
 

diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
index 757922210244c0c2f8fe934853694f71a8081879..d671dccc19b7b7464c96210728c8d7b6bd7da285 100644 (file)
--- a/include/configs/ppmc8260.h
+++ b/include/configs/ppmc8260.h
@@ -279,7 +279,6 @@
 #define CONFIG_COMMANDS                (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
                                CFG_CMD_ELF     | \
                                CFG_CMD_ASKENV  | \
-                               CFG_CMD_ECHO    | \
                                CFG_CMD_REGINFO | \
                                CFG_CMD_MEMTEST | \
                                CFG_CMD_MII     | \

diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index 4e0cfdb4c36244a81eabf1261a50d196d5f590ee..97b52fa1ae7940ad00c89dd424853e510a4755ae 100644 (file)
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -507,7 +507,6 @@
 # define CONFIG_COMMANDS       (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
                                CFG_CMD_ELF     | \
                                CFG_CMD_ASKENV  | \
-                               CFG_CMD_ECHO    | \
                                CFG_CMD_I2C     | \
                                CFG_CMD_SPI     | \
                                CFG_CMD_SDRAM   | \
@@ -520,7 +519,6 @@
 # define CONFIG_COMMANDS       (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
                                CFG_CMD_ELF     | \
                                CFG_CMD_ASKENV  | \
-                               CFG_CMD_ECHO    | \
                                CFG_CMD_I2C     | \
                                CFG_CMD_SPI     | \
                                CFG_CMD_SDRAM   | \

diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h
index 180ce057d7921fda1e5408cf7690abe8ba938586..9cf0654be10e19555fe74f2d1a055af45b0f57d3 100644 (file)
--- a/include/configs/sbc8260.h
+++ b/include/configs/sbc8260.h
@@ -448,7 +448,6 @@
 #ifdef CONFIG_ETHER_ON_FCC
 # define CONFIG_COMMANDS       (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
                                CFG_CMD_ASKENV  | \
-                               CFG_CMD_ECHO    | \
                                CFG_CMD_ELF     | \
                                CFG_CMD_I2C     | \
                                CFG_CMD_IMMAP   | \
@@ -459,7 +458,6 @@
 #else
 # define CONFIG_COMMANDS       (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
                                CFG_CMD_ASKENV  | \
-                               CFG_CMD_ECHO    | \
                                CFG_CMD_ELF     | \
                                CFG_CMD_I2C     | \
                                CFG_CMD_IMMAP   | \

diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h
new file mode 100644 (file)
index 0000000..e106b3b
--- /dev/null
+++ b/include/configs/smmaco4.h
@@ -0,0 +1,373 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx         1       /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200         1       /* (more precisely an MPC5200 CPU) */
+#define CONFIG_TQM5200         1       /* ... on TQM5200 module */
+#undef CONFIG_TQM5200_REV100           /*  define for revision 100 modules */
+
+#define CFG_MPC5XXX_CLKIN      33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM          0x02    /* Software reboot           */
+
+#define CFG_CACHELINE_SIZE     32      /* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT  5       /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE     1       /* console is on PSC1 */
+#define CONFIG_BAUDRATE                115200  /* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* POST support */
+#define CONFIG_POST            (CFG_POST_MEMORY   | \
+                                CFG_POST_CPU      | \
+                                CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS               (CONFIG_CMD_DFL  | \
+                               CFG_CMD_ASKENV  | \
+                               CFG_CMD_DATE    | \
+                               CFG_CMD_DHCP    | \
+                               CFG_CMD_ECHO    | \
+                               CFG_CMD_EEPROM  | \
+                               CFG_CMD_I2C     | \
+                               CFG_CMD_JFFS2   | \
+                               CFG_CMD_MII     | \
+                               CFG_CMD_NFS     | \
+                               CFG_CMD_PING    | \
+                               CFG_CMD_POST_DIAG | \
+                               CFG_CMD_REGINFO | \
+                               CFG_CMD_SNTP    )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define        CONFIG_TIMESTAMP                /* display image timestamps */
+
+#if (TEXT_BASE == 0xFC000000)          /* Boot low */
+#   define CFG_LOWBOOT         1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+       "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+       "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS                                      \
+       "netdev=eth0\0"                                                 \
+       "rootpath=/opt/eldk/ppc_6xx\0"                                  \
+       "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
+       "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
+               "nfsroot=${serverip}:${rootpath}\0"                     \
+       "addip=setenv bootargs ${bootargs} "                            \
+               "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
+               ":${hostname}:${netdev}:off panic=1\0"                  \
+       "flash_self=run ramargs addip;"                                 \
+               "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
+       "flash_nfs=run nfsargs addip;"                                  \
+               "bootm ${kernel_addr}\0"                                \
+       "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
+       "bootfile=/tftpboot/smmaco4/uImage\0"                           \
+       "load=tftp 200000 ${u-boot}\0"                                  \
+       "u-boot=/tftpboot/smmaco4/u-boot.bin\0"                         \
+       "update=protect off FC000000 FC05FFFF;"                         \
+               "erase FC000000 FC05FFFF;"                              \
+               "cp.b 200000 FC000000 ${filesize};"                     \
+               "protect on FC000000 FC05FFFF\0"                        \
+       ""
+
+#define CONFIG_BOOTCOMMAND     "run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133               /* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66                        /* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C                1       /* I2C with hardware support */
+#ifdef CONFIG_TQM5200_REV100
+#define CFG_I2C_MODULE         1       /* Select I2C module #1 for rev. 100 board */
+#else
+#define CFG_I2C_MODULE         2       /* Select I2C module #2 for all other revs */
+#endif
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CFG_I2C_SPEED          100000 /* 100 kHz */
+#define CFG_I2C_SLAVE          0x7F
+
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
+ * also). For other EEPROMs configuration should be verified. On Mini-FAP the
+ * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
+ * same configuration could be used.
+ */
+#define CFG_I2C_EEPROM_ADDR            0x50    /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN                2
+#define CFG_EEPROM_PAGE_WRITE_BITS     5       /* =32 Bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE         TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver if no module variant is spezified */
+#define CFG_FLASH_CFI          1       /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER   1       /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST   { CFG_BOOTCS_START }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_SIZE         0x04000000 /* 64 MByte */
+#define CFG_MAX_FLASH_SECT     512     /* max num of sects on one chip */
+#undef CFG_FLASH_USE_BUFFER_WRITE      /* not supported yet for AMD */
+
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR           (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
+#else  /* CFG_LOWBOOT */
+#define CFG_ENV_ADDR           (CFG_FLASH_BASE + 0x00060000)
+#endif /* CFG_LOWBOOT */
+#define CFG_MAX_FLASH_BANKS    1       /* max num of flash banks
+                                          (= chip selects) */
+#define CFG_FLASH_ERASE_TOUT   240000  /* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT   500     /* Flash Write Timeout (in ms)  */
+
+/* Dynamic MTD partition support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT         "nor0=TQM5200-0"
+#define MTDPARTS_DEFAULT       "mtdparts=TQM5200-0:640k(firmware),"    \
+                                               "1408k(kernel),"        \
+                                               "2m(initrd),"           \
+                                               "4m(small-fs),"         \
+                                               "16m(big-fs),"          \
+                                               "8m(misc)"
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH    1
+#define CFG_ENV_SIZE           0x10000
+#define CFG_ENV_SECT_SIZE      0x20000
+#define CFG_ENV_ADDR_REDUND    (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define        CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR               0xF0000000
+#define CFG_SDRAM_BASE         0x00000000
+#define CFG_DEFAULT_MBAR       0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR      MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END       MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END       MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE      128     /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE       TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT         1
+#endif
+
+#define CFG_MONITOR_LEN                (384 << 10)     /* Reserve 384 kB for Monitor   */
+#define CFG_MALLOC_LEN         (256 << 10)     /* Reserve 256 kB for malloc()  */
+#define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC     1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR                0x00
+
+/*
+ * GPIO configuration
+ *
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
+ *     Bit 0 (mask: 0x80000000): 1
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ *     00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ *     01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ *           Use for REV200 STK52XX boards. Do not use with REV100 modules
+ *           (because, there I2C1 is used as I2C bus)
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
+ *     000 -> All PSC2 pins are GIOPs
+ *     001 -> CAN1/2 on PSC2 pins
+ *            Use for REV100 STK52xx boards
+ * use PSC6:
+ *   on STK52xx:
+ *     use as UART. Pins PSC6_0 to PSC6_3 are used.
+ *     Bits 9:11 (mask: 0x00700000):
+ *        101 -> PSC6 : Extended POST test is not available
+ *   on MINI-FAP and TQM5200_IB:
+ *     use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
+ *        000 -> PSC6 could not be used as UART, CODEC or IrDA
+ *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
+ *   tests.
+ */
+#if defined (CONFIG_MINIFAP)
+# define CFG_GPS_PORT_CONFIG   0x91000004
+#elif defined (CONFIG_STK52XX)
+# if defined (CONFIG_STK52XX_REV100)
+#  define CFG_GPS_PORT_CONFIG  0x81500014
+# else /* STK52xx REV200 and above */
+#  if defined (CONFIG_TQM5200_REV100)
+#   error TQM5200 REV100 not supported on STK52XX REV200 or above
+#  else/* TQM5200 REV200 and above */
+#   define CFG_GPS_PORT_CONFIG 0x91500004
+#  endif
+# endif
+#else  /* TMQ5200 Inbetriebnahme-Board */
+# define CFG_GPS_PORT_CONFIG   0x81000004
+#endif
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_MPC5200     1       /* use internal MPC5200 RTC */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                   /* undef to save memory     */
+#define CFG_PROMPT             "=> "   /* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE             1024    /* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE             256     /* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS            16      /* max number of command args   */
+#define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size    */
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START      0x00100000      /* memtest works on */
+#define CFG_MEMTEST_END                0x00f00000      /* 1 ... 15 MB in DRAM  */
+
+#define CFG_LOAD_ADDR          0x100000        /* default load address */
+
+#define CFG_HZ                 1000    /* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT          HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL         HID0_ICE
+#else
+#define CFG_HID0_INIT          0
+#define CFG_HID0_FINAL         0
+#endif
+
+#define CFG_BOOTCS_START       CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE                CFG_FLASH_SIZE
+#ifdef CFG_PCISPEED_66
+#define CFG_BOOTCS_CFG         0x0008DF30 /* for pci_clk  = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG         0x0004DF30 /* for pci_clk = 33 MHz */
+#endif
+#define CFG_CS0_START          CFG_FLASH_BASE
+#define CFG_CS0_SIZE           CFG_FLASH_SIZE
+
+#define CFG_CS_BURST           0x00000000
+#define CFG_CS_DEADCYCLE       0x33333311      /* 1 dead cycle for flash and SM501 */
+
+#define CFG_RESET_ADDRESS      0xff000000
+
+#endif /* __CONFIG_H */

diff --git a/include/configs/stamp.h b/include/configs/stamp.h
new file mode 100644 (file)
index 0000000..248ca70
--- /dev/null
+++ b/include/configs/stamp.h
@@ -0,0 +1,333 @@
+/*
+ * U-boot - stamp.h  Configuration file for STAMP board
+ *                     having BF533 processor
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_STAMP_H__
+#define __CONFIG_STAMP_H__
+
+/*
+ * Board settings
+ *
+ */
+
+#define __ADSPLPBLACKFIN__             1
+#define __ADSPBF533__                  1
+#define CONFIG_STAMP                   1
+#define CONFIG_RTC_BF533               1
+
+/* FLASH/ETHERNET uses the same address range */
+#define SHARED_RESOURCES               1
+
+#define CONFIG_VDSP                    1
+
+/*
+ * Clock settings
+ *
+ */
+
+/* CONFIG_CLKIN_HZ is any value in Hz                           */
+#define CONFIG_CLKIN_HZ                        11059200
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN     */
+/*                                                 1=CLKIN/2    */
+#define CONFIG_CLKIN_HALF              0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass         */
+/*                                              1=bypass PLL    */
+#define CONFIG_PLL_BYPASS              0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.  */
+/* Values can range from 1-64                                   */
+#define CONFIG_VCO_MULT                        45
+/* CONFIG_CCLK_DIV controls what the core clock divider is      */
+/* Values can be 1, 2, 4, or 8 ONLY                             */
+#define CONFIG_CCLK_DIV                        1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
+/* Values can range from 1-15                                   */
+#define CONFIG_SCLK_DIV                        6
+
+/*
+ * Network Settings
+ */
+/* network support */
+#define CONFIG_IPADDR          192.168.0.15
+#define CONFIG_NETMASK         255.255.255.0
+#define CONFIG_GATEWAYIP       192.168.0.1
+#define CONFIG_SERVERIP                192.168.0.2
+#define CONFIG_HOSTNAME                STAMP
+#define CONFIG_ROOTPATH                        /checkout/uClinux-dist/romfs
+
+/* To remove hardcoding and enable MAC storage in EEPROM  */
+/* #define CONFIG_ETHADDR              02:80:ad:20:31:b8 */
+
+/*
+ * Command settings
+ *
+ */
+
+#define CFG_LONGHELP                   1
+
+#define CONFIG_BOOTDELAY               5
+#define CONFIG_BOOT_RETRY_TIME         -1      /* Enable this if bootretry required, currently its disabled */
+#define CONFIG_BOOTCOMMAND             "run ramboot"
+#define CONFIG_AUTOBOOT_PROMPT         "autoboot in %d seconds\n"
+
+#define CONFIG_COMMANDS                        (CONFIG_CMD_DFL | \
+                                        CFG_CMD_PING   | \
+                                        CFG_CMD_ELF    | \
+                                        CFG_CMD_I2C    | \
+                                        CFG_CMD_CACHE  | \
+                                        CFG_CMD_JFFS2  | \
+                                        CFG_CMD_DATE)
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
+
+#define CONFIG_EXTRA_ENV_SETTINGS                                                                                              \
+       "ramargs=setenv bootargs root=/dev/mtdblock0 rw\0"                                                      \
+       "nfsargs=setenv bootargs root=/dev/nfs rw "                                                                     \
+       "nfsroot=$(serverip):$(rootpath)\0"                                                                                     \
+       "addip=setenv bootargs $(bootargs) "                                                                            \
+       "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"                                                      \
+       ":$(hostname):eth0:off\0"                                                                                                       \
+    "ramboot=tftpboot 0x1000000 linux;"                                                                                        \
+       "run ramargs;run addip;bootelf\0"                                                                                       \
+       "nfsboot=tftpboot 0x1000000 linux;"                                                                                     \
+       "run nfsargs;run addip;bootelf\0"                                                                                       \
+       "flashboot=bootm 0x20100000\0"                                                                                          \
+       ""
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Console settings
+ *
+ */
+
+#define CONFIG_BAUDRATE                        57600
+#define CFG_BAUDRATE_TABLE             { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_PROMPT                     "stamp>"        /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE                     1024    /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE                     256     /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE                     (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)      /* Print Buffer Size */
+#define CFG_MAXARGS                    16      /* max number of command args */
+#define CFG_BARGSIZE                   CFG_CBSIZE      /* Boot Argument Buffer Size */
+
+#define CONFIG_LOADS_ECHO              1
+
+/*
+ * Network settings
+ *
+ */
+
+#define CONFIG_DRIVER_SMC91111         1
+#define CONFIG_SMC91111_BASE           0x20300300
+/* To remove hardcoding and enable MAC storage in EEPROM */
+/* #define HARDCODE_MAC                        1 */
+
+/*
+ * Flash settings
+ *
+ */
+
+#define CFG_FLASH_CFI                          /* The flash is CFI compatible  */
+#define CFG_FLASH_CFI_DRIVER                   /* Use common CFI driver        */
+#define CFG_FLASH_CFI_AMD_RESET
+
+#define CFG_ENV_IS_IN_FLASH            1
+
+#define CFG_FLASH_BASE                 0x20000000
+#define CFG_MAX_FLASH_BANKS            1               /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT             67              /* max number of sectors on one chip */
+
+#define CFG_ENV_ADDR                   0x20020000
+#define CFG_ENV_SIZE                   0x10000
+#define CFG_ENV_SECT_SIZE              0x10000 /* Total Size of Environment Sector */
+
+#define CFG_FLASH_ERASE_TOUT           30000   /* Timeout for Chip Erase (in ms) */
+#define CFG_FLASH_ERASEBLOCK_TOUT      5000    /* Timeout for Block Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT           1       /* Timeout for Flash Write (in ms) */
+
+/* JFFS Partition offset set  */
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS  1
+/* 512k reserved for u-boot */
+#define CFG_JFFS2_FIRST_SECTOR         11
+
+/*
+ * following timeouts shall be used once the
+ * Flash real protection is enabled
+ */
+#define CFG_FLASH_LOCK_TOUT            5       /* Timeout for Flash Set Lock Bit (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT          10000   /* Timeout for Flash Clear Lock Bits (in ms) */
+
+/*
+ * I2C settings
+ * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
+ */
+#define CONFIG_SOFT_I2C                        1       /* I2C bit-banged               */
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PF_SCL                         PF3
+#define PF_SDA                         PF2
+
+#define I2C_INIT                       (*pFIO_DIR |=  PF_SCL); asm("ssync;")
+#define I2C_ACTIVE                     (*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE                   (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ                       ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
+#define I2C_SDA(bit)                   if(bit) { \
+                                                       *pFIO_FLAG_S = PF_SDA; \
+                                                       asm("ssync;"); \
+                                               } \
+                                       else    { \
+                                                       *pFIO_FLAG_C = PF_SDA; \
+                                                       asm("ssync;"); \
+                                               }
+#define I2C_SCL(bit)                   if(bit) { \
+                                                       *pFIO_FLAG_S = PF_SCL; \
+                                                       asm("ssync;"); \
+                                               } \
+                                       else    { \
+                                                       *pFIO_FLAG_C = PF_SCL; \
+                                                       asm("ssync;"); \
+                                               }
+#define I2C_DELAY                      udelay(5)       /* 1/4 I2C clock duration */
+
+#define CFG_I2C_SPEED                  50000
+#define CFG_I2C_SLAVE                  0xFE
+
+/*
+ * Compact Flash settings
+ */
+
+/* Enabled below option for CF support */
+/* #define CONFIG_STAMP_CF             1 */
+
+#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
+
+#define CONFIG_MISC_INIT_R             1
+#define CONFIG_DOS_PARTITION           1
+
+/*
+ * IDE/ATA stuff
+ */
+#undef CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
+#undef CONFIG_IDE_LED                  /* no led for ide supported */
+#undef CONFIG_IDE_RESET                /* no reset for ide supported */
+
+#define CFG_IDE_MAXBUS 1               /* max. 1 IDE busses */
+#define CFG_IDE_MAXDEVICE              (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR              0x20200000
+#define CFG_ATA_IDE0_OFFSET            0x0000
+
+#define CFG_ATA_DATA_OFFSET            0x0020  /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET             0x0020  /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET             0x0007  /* Offset for alternate registers */
+
+#define CFG_ATA_STRIDE                 2
+#endif
+
+/*
+ * SDRAM settings
+ *
+ */
+
+#define CONFIG_MEM_SIZE                        128             /* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH            11             /* 8, 9, 10, 11    */
+#define CONFIG_MEM_MT48LC64M4A2FB_7E   1
+
+#define CFG_MEMTEST_START              0x00100000      /* memtest works on */
+#define CFG_MEMTEST_END                        0x07EFFFFF      /* 1 ... 127 MB in DRAM */
+#define CFG_LOAD_ADDR                  0x01000000      /* default load address */
+
+#define CFG_SDRAM_BASE                 0x00000000
+#define CFG_MAX_RAM_SIZE               0x08000000
+
+#define CFG_MONITOR_LEN                        (256 << 10)     /* Reserve 256 kB for Monitor   */
+#define CFG_MONITOR_BASE               (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
+
+#if ( CONFIG_CLKIN_HALF == 0 )
+#define CONFIG_VCO_HZ                  ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#else
+#define CONFIG_VCO_HZ                  (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#endif
+
+#if (CONFIG_PLL_BYPASS == 0)
+#define CONFIG_CCLK_HZ                 ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ                 ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#else
+#define CONFIG_CCLK_HZ                 CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ                 CONFIG_CLKIN_HZ
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HZ                         1000            /* 1ms time tick */
+
+#define CFG_MALLOC_LEN                 (128 << 10)     /* Reserve 128 kB for malloc()  */
+#define CFG_MALLOC_BASE                        (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_SIZE              0x4000
+#define CFG_GBL_DATA_ADDR              (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE               (CFG_GBL_DATA_ADDR  - 4)
+
+#define CFG_LARGE_IMAGE_LEN    0x4000000       /* Large Image Length, set to 64 Meg */
+
+#define CONFIG_SHOW_BOOT_PROGRESS      1       /* Show boot progress on LEDs */
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE               (128*1024)      /* regular stack */
+
+/*
+ * FLASH organization and environment definitions
+ */
+#define CFG_BOOTMAPSZ                  (8 << 20)       /* Initial Memory map for Linux */
+
+/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
+/*#define AMGCTLVAL            (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL             (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL |    \
+                               B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
+#define AMBCTL1VAL             (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL |      \
+                               B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
+*/
+#define AMGCTLVAL              0xFF
+#define AMBCTL0VAL             0xBBC3BBC3
+#define AMBCTL1VAL             0x99B39983
+#define CF_AMBCTL1VAL          0x99B3ffc2
+
+#ifdef CONFIG_VDSP
+#define ET_EXEC_VDSP           0x8
+#define SHT_STRTAB_VDSP                0x1
+#define ELFSHDRSIZE_VDSP       0x2C
+#define VDSP_ENTRY_ADDR                0xFFA00000
+#endif
+
+#endif

diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index 3ffe6b2e05f429aeea8443f51821f143cc12fc39..614a046105cd616b7469abd2783bc63eded5204b 100644 (file)
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -436,6 +436,7 @@
 /****************************************************************/
 
 /* NAND */
+#define CFG_NAND_LEGACY
 #define CFG_NAND_BASE          NAND_BASE
 #define CONFIG_MTD_NAND_ECC_JFFS2
 #define CONFIG_MTD_NAND_VERIFY_WRITE
@@ -584,5 +585,7 @@ typedef unsigned int led_id_t;
 
 #define OF_CPU                 "PowerPC,MPC870@0"
 #define OF_TBCLK               (MPC8XX_HZ / 16)
+#define CONFIG_OF_HAS_BD_T     1
+#define CONFIG_OF_HAS_UBOOT_ENV        1
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
index 7118f3f74be7380d94fa2ab527e82d7e5bab5f52..92ee8cb3331f961cdceb467ae582928292ec7f3e 100644 (file)
--- a/include/configs/svm_sc8xx.h
+++ b/include/configs/svm_sc8xx.h
@@ -141,6 +141,7 @@
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
+#define CFG_NAND_LEGACY
 
 /*
  * Miscellaneous configurable options

diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h
index d312b6559ad3cc2b6969fd7fec8ad9c846ff582e..e5d4397d2c74c9e4f71b26dcd2c327013dbd0c9a 100644 (file)
--- a/include/configs/utx8245.h
+++ b/include/configs/utx8245.h
@@ -91,7 +91,6 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
                                                                | CFG_CMD_ENV | CFG_CMD_CONSOLE \
                                                                | CFG_CMD_LOADS | CFG_CMD_LOADB \
                                                                | CFG_CMD_IMI | CFG_CMD_CACHE \
-                                                               | CFG_CMD_RUN | CFG_CMD_ECHO \
                                                                | CFG_CMD_REGINFO | CFG_CMD_NET\
                                                                | CFG_CMD_DHCP | CFG_CMD_I2C \
                                                                | CFG_CMD_DATE)

diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
new file mode 100644 (file)
index 0000000..4232d50
--- /dev/null
+++ b/include/configs/zylonite.h
@@ -0,0 +1,256 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the Zylonite board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_CPU_MONAHANS    1       /* Intel Monahan CPU    */
+#define CONFIG_ZYLONITE                1       /* Zylonite board       */
+
+/* #define CONFIG_LCD          1 */
+#ifdef CONFIG_LCD
+#define CONFIG_SHARP_LM8V31
+#endif
+/* #define CONFIG_MMC          1 */
+#define BOARD_LATE_INIT                1
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#undef CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN     (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE      128     /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#undef TURN_ON_ETHERNET
+#ifdef TURN_ON_ETHERNET
+# define CONFIG_DRIVER_SMC91111 1
+# define CONFIG_SMC91111_BASE   0x14000300
+# define CONFIG_SMC91111_EXT_PHY
+# define CONFIG_SMC_USE_32_BIT
+# undef CONFIG_SMC_USE_IOFUNCS          /* just for use with the kernel */
+#endif
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART         1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE                115200
+
+/* #define CONFIG_COMMANDS       (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
+#ifdef TURN_ON_ETHERNET
+# define CONFIG_COMMANDS        (CONFIG_CMD_DFL | CFG_CMD_PING)
+#else
+# define CONFIG_COMMANDS       (CONFIG_CMD_DFL & ~CFG_CMD_NET)
+#endif
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY       -1
+#define CONFIG_ETHADDR         08:00:3e:26:0a:5b
+#define CONFIG_NETMASK         255.255.0.0
+#define CONFIG_IPADDR          192.168.0.21
+#define CONFIG_SERVERIP                192.168.0.250
+#define CONFIG_BOOTCOMMAND     "bootm 80000"
+#define CONFIG_BOOTARGS                "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_TIMESTAMP
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE   230400          /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX  2               /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER                1
+#define CFG_PROMPT_HUSH_PS2    "> "
+
+#define CFG_LONGHELP                           /* undef to save memory         */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT             "$ "            /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT             "=> "           /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE             256             /* Console I/O Buffer Size      */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS            16              /* max number of command args   */
+#define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size    */
+#define CFG_DEVICE_NULLDEV     1
+
+#define CFG_MEMTEST_START      0x9c000000      /* memtest works on     */
+#define CFG_MEMTEST_END                0x9c400000      /* 4 ... 8 MB in DRAM   */
+
+#undef CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR  (CFG_DRAM_BASE + 0x8000) /* default load address */
+
+#define CFG_HZ                 3686400         /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED           0x161           /* set core clock to 400/200/100 MHz */
+
+                                               /* valid baudrates */
+#define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
+
+/* #define CFG_MMC_BASE                0xF0000000 */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE       (128*1024)      /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ   (4*1024)        /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ   (4*1024)        /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS   4          /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1           0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE      0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2           0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE      0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3           0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE      0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4           0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE      0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1           0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2           0x04000000 /* Flash Bank #2 */
+#define PHYS_FLASH_SIZE                0x02000000 /* 32 MB */
+#define PHYS_FLASH_BANK_SIZE   0x02000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE   0x00040000 /* 256 KB sectors (x2) */
+
+#define CFG_DRAM_BASE          0xa0000000
+#define CFG_DRAM_SIZE          0x04000000
+
+#define CFG_FLASH_BASE         PHYS_FLASH_1
+
+#define FPGA_REGS_BASE_PHYSICAL 0x08000000
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPSR0_VAL          0x00008000
+#define CFG_GPSR1_VAL          0x00FC0382
+#define CFG_GPSR2_VAL          0x0001FFFF
+#define CFG_GPCR0_VAL          0x00000000
+#define CFG_GPCR1_VAL          0x00000000
+#define CFG_GPCR2_VAL          0x00000000
+#define CFG_GPDR0_VAL          0x0060A800
+#define CFG_GPDR1_VAL          0x00FF0382
+#define CFG_GPDR2_VAL          0x0001C000
+#define CFG_GAFR0_L_VAL                0x98400000
+#define CFG_GAFR0_U_VAL                0x00002950
+#define CFG_GAFR1_L_VAL                0x000A9558
+#define CFG_GAFR1_U_VAL                0x0005AAAA
+#define CFG_GAFR2_L_VAL                0xA0000000
+#define CFG_GAFR2_U_VAL                0x00000002
+
+#define CFG_PSSR_VAL           0x20
+
+/*
+ * Memory settings
+ */
+#define CFG_MSC0_VAL           0x23F223F2
+#define CFG_MSC1_VAL           0x3FF1A441
+#define CFG_MSC2_VAL           0x7FF97FF1
+#define CFG_MDCNFG_VAL         0x00001AC9
+#define CFG_MDREFR_VAL         0x00018018
+#define CFG_MDMRS_VAL          0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL           0x00000000
+#define CFG_MCMEM0_VAL         0x00010504
+#define CFG_MCMEM1_VAL         0x00010504
+#define CFG_MCATT0_VAL         0x00010504
+#define CFG_MCATT1_VAL         0x00010504
+#define CFG_MCIO0_VAL          0x00004715
+#define CFG_MCIO1_VAL          0x00004715
+
+#define _LED                   0x08000010
+#define LED_BLANK              0x08000040
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS    2       /* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT     128  /* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT   (25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT   (25*CFG_HZ) /* Timeout for Flash Write */
+
+/* NOTE: many default partitioning schemes assume the kernel starts at the
+ * second sector, not an environment.  You have been warned!
+ */
+#define        CFG_MONITOR_LEN         PHYS_FLASH_SECT_SIZE
+
+#define CFG_ENV_IS_IN_FLASH     1
+#define CFG_ENV_ADDR           (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
+#define CFG_ENV_SECT_SIZE      PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_SIZE           (PHYS_FLASH_SECT_SIZE / 16)
+
+
+/*
+ * FPGA Offsets
+ */
+#define WHOAMI_OFFSET          0x00
+#define HEXLED_OFFSET          0x10
+#define BLANKLED_OFFSET                0x40
+#define DISCRETELED_OFFSET     0x40
+#define CNFG_SWITCHES_OFFSET   0x50
+#define USER_SWITCHES_OFFSET   0x60
+#define MISC_WR_OFFSET         0x80
+#define MISC_RD_OFFSET         0x90
+#define INT_MASK_OFFSET                0xC0
+#define INT_CLEAR_OFFSET       0xD0
+#define GP_OFFSET              0x100
+
+#endif /* __CONFIG_H */

diff --git a/include/crc.h b/include/crc.h
new file mode 100644 (file)
index 0000000..10560c9
--- /dev/null
+++ b/include/crc.h
@@ -0,0 +1,100 @@
+/*
+ *==========================================================================
+ *
+ *      crc.h
+ *
+ *      Interface for the CRC algorithms.
+ *
+ *==========================================================================
+ *####ECOSGPLCOPYRIGHTBEGIN####
+ * -------------------------------------------
+ * This file is part of eCos, the Embedded Configurable Operating System.
+ * Copyright (C) 2002 Andrew Lunn
+ *
+ * eCos is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 or (at your option) any later version.
+ *
+ * eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+ * WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with eCos; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * As a special exception, if other files instantiate templates or use macros
+ * or inline functions from this file, or you compile this file and link it
+ * with other works to produce a work based on this file, this file does not
+ * by itself cause the resulting work to be covered by the GNU General Public
+ * License. However the source code for this file must still be made available
+ * in accordance with section (3) of the GNU General Public License.
+ *
+ * This exception does not invalidate any other reasons why a work based on
+ * this file might be covered by the GNU General Public License.
+ *
+ * Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+ * at http: *sources.redhat.com/ecos/ecos-license/
+ * -------------------------------------------
+ *####ECOSGPLCOPYRIGHTEND####
+ *==========================================================================
+ *#####DESCRIPTIONBEGIN####
+ *
+ * Author(s):    Andrew Lunn
+ * Contributors: Andrew Lunn
+ * Date:         2002-08-06
+ * Purpose:
+ * Description:
+ *
+ * This code is part of eCos (tm).
+ *
+ *####DESCRIPTIONEND####
+ *
+ *==========================================================================
+ */
+
+#ifndef _SERVICES_CRC_CRC_H_
+#define _SERVICES_CRC_CRC_H_
+
+#include <linux/types.h>
+
+#ifndef __externC
+# ifdef __cplusplus
+#  define __externC extern "C"
+# else
+#  define __externC extern
+# endif
+#endif
+
+/* Compute a CRC, using the POSIX 1003 definition */
+extern uint32_t
+cyg_posix_crc32(unsigned char *s, int len);
+
+/* Gary S. Brown's 32 bit CRC */
+
+extern uint32_t
+cyg_crc32(unsigned char *s, int len);
+
+/* Gary S. Brown's 32 bit CRC, but accumulate the result from a */
+/* previous CRC calculation */
+
+extern uint32_t
+cyg_crc32_accumulate(uint32_t crc, unsigned char *s, int len);
+
+/* Ethernet FCS Algorithm */
+
+extern uint32_t
+cyg_ether_crc32(unsigned char *s, int len);
+
+/* Ethernet FCS algorithm, but accumulate the result from a previous */
+/* CRC calculation. */
+
+extern uint32_t
+cyg_ether_crc32_accumulate(uint32_t crc, unsigned char *s, int len);
+
+/* 16 bit CRC with polynomial x^16+x^12+x^5+1 */
+
+extern uint16_t cyg_crc16(unsigned char *s, int len);
+
+#endif /* _SERVICES_CRC_CRC_H_ */

diff --git a/include/da9030.h b/include/da9030.h
new file mode 100644 (file)
index 0000000..41108b9
--- /dev/null
+++ b/include/da9030.h
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* DA9030 register definitions */
+#define CID                    0x00
+#define EVENT_A                        0x01
+#define EVENT_B                        0x02
+#define EVENT_C                        0x03
+#define STATUS                 0x04
+#define IRQ_MASK_A             0x05
+#define IRQ_MASK_B             0x06
+#define IRQ_MASK_C             0x07
+#define SYS_CONTROL_A          0x08
+#define SYS_CONTROL_B          0x09
+#define FAULT_LOG              0x0A
+#define LDO_10_11              0x10
+#define LDO_15                 0x11
+#define LDO_14_16              0x12
+#define LDO_18_19              0x13
+#define LDO_17_SIMCP0          0x14
+#define BUCK2_DVC1             0x15
+#define BUCK2_DVC2             0x16
+#define REG_CONTROL_1_17       0x17
+#define REG_CONTROL_2_18       0x18
+#define USBPUMP                        0x19
+#define SLEEP_CONTROL          0x1A
+#define STARTUP_CONTROL                0x1B
+#define LED1_CONTROL           0x20
+#define LED2_CONTROL           0x21
+#define LED3_CONTROL           0x22
+#define LED4_CONTROL           0x23
+#define LEDPC_CONTROL          0x24
+#define WLED_CONTROL           0x25
+#define MISC_CONTROLA          0x26
+#define MISC_CONTROLB          0x27
+#define CHARGE_CONTROL         0x28
+#define CCTR_CONTROL           0x29
+#define TCTR_CONTROL           0x2A
+#define CHARGE_PULSE           0x2B
+
+/* ... some missing ...*/
+
+#define LDO1                   0x90
+#define LDO2_3                 0x91
+#define LDO4_5                 0x92
+#define LDO6_SIMCP             0x93
+#define LDO7_8                 0x94
+#define LDO9_12                        0x95
+#define BUCK                   0x96
+#define REG_CONTROL_1_97       0x97
+#define REG_CONTROL_2_98       0x98
+#define REG_SLEEP_CONTROL1     0x99
+#define REG_SLEEP_CONTROL2     0x9A
+#define REG_SLEEP_CONTROL3     0x9B
+#define ADC_MAN_CONTROL                0xA0
+#define ADC_AUTO_CONTROL       0xA1
+#define VBATMON                        0xA2
+#define VBATMONTXMON           0xA3
+#define TBATHIGHP              0xA4
+#define TBATHIGHN              0xA5
+#define TBATLOW                        0xA6
+#define MAN_RES                        0xB0
+#define VBAT_RES               0xB1
+#define VBATMIN_RES            0xB2
+#define VBATMINTXON_RES                0xB3
+#define ICHMAX_RES             0xB4
+#define ICHMIN_RES             0xB5
+#define ICHAVERAGE_RES         0xB6
+#define VCHMAX_RES             0xB7
+#define VCHMIN_RES             0xB8
+#define TBAT_RES               0xB9
+#define ADC_IN4_RES            0xBA
+
+#define STATUS_ONKEY_N         0x1     /* current ONKEY_N value */
+#define STATUS_PWREN1          (1<<1)  /* PWREN1 value */
+#define STATUS_EXTON           (1<<2)  /* EXTON value */
+#define STATUS_CHDET           (1<<3)  /* Charger detection status */
+#define STATUS_TBAT            (1<<4)  /* Battery over/under temperature status */
+#define STATUS_VBATMON         (1<<5)  /* VBATMON comparison status */
+#define STATUS_VBATMONTXON     (1<<6)  /* VBATMONTXON comparison status */
+#define STATUS_CHIOVER         (1<<7)  /* Charge overcurrent */
+
+#define SYS_CONTROL_A_SLEEP_N_PIN_ENABLE       0x1
+#define SYS_CONTROL_A_SHUT_DOWN                        (1<<1)
+#define SYS_CONTROL_A_HWRES_ENABLE             (1<<2)
+#define SYS_CONTROL_A_WDOG_ACTION              (1<<3)
+#define SYS_CONTROL_A_WATCHDOG                 (1<<7)

diff --git a/include/environment.h b/include/environment.h
index bb109649f6bab7492ba9242d64fc43784c8ed2ab..422f800897fb78982e388d5ef9371aed34810ac5 100644 (file)
--- a/include/environment.h
+++ b/include/environment.h
@@ -69,6 +69,18 @@
 # endif
 #endif /* CFG_ENV_IS_IN_FLASH */
 
+#if defined(CFG_ENV_IS_IN_NAND)
+# ifndef CFG_ENV_OFFSET
+#  error "Need to define CFG_ENV_OFFSET when using CFG_ENV_IS_IN_NAND"
+# endif
+# ifndef CFG_ENV_SIZE
+#  error "Need to define CFG_ENV_SIZE when using CFG_ENV_IS_IN_NAND"
+# endif
+# ifdef CFG_ENV_OFFSET_REDUND
+#  define CFG_REDUNDAND_ENVIRONMENT
+# endif
+#endif /* CFG_ENV_IS_IN_NAND */
+
 
 #ifdef CFG_REDUNDAND_ENVIRONMENT
 # define ENV_HEADER_SIZE       (sizeof(unsigned long) + 1)

diff --git a/include/flash.h b/include/flash.h
index 069aa63414d05190963b05114c78253d4227e2c9..a84dc6872e113e2f1cd3bb2e016413f07b0e2449 100644 (file)
--- a/include/flash.h
+++ b/include/flash.h
@@ -45,6 +45,7 @@ typedef struct {
        ushort  vendor;                 /* the primary vendor id                */
        ushort  cmd_reset;              /* Vendor specific reset command        */
        ushort  interface;              /* used for x8/x16 adjustments          */
+       ushort  legacy_unlock;          /* support Intel legacy (un)locking     */
 #endif
 } flash_info_t;
 
@@ -242,6 +243,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define STM_ID_29W320DT 0x22CA22CA     /* M29W320DT ID (32 M, top boot sector) */
 #define STM_ID_29W320DB 0x22CB22CB     /* M29W320DB ID (32 M, bottom boot sect)        */
 #define STM_ID_29W040B 0x00E300E3      /* M29W040B ID (4M = 512K x 8)  */
+#define FLASH_PSD4256GV 0x00E9         /* PSD4256 Flash and CPLD combination   */
 
 #define INTEL_ID_28F016S    0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16)     */
 #define INTEL_ID_28F800B3T  0x88928892 /*  8M = 512K x 16 top boot sector      */
@@ -274,6 +276,12 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define INTEL_ID_28F64K3    0x88018801 /*  64M =  32K x 255 + 32k x 4 */
 #define INTEL_ID_28F128K3   0x88028802 /* 128M =  64K x 255 + 32k x 4 */
 #define INTEL_ID_28F256K3   0x88038803 /* 256M = 128K x 255 + 32k x 4 */
+#define INTEL_ID_28F64P30T  0x88178817 /*  64M =  32K x 255 + 32k x 4 */
+#define INTEL_ID_28F64P30B  0x881A881A /*  64M =  32K x 255 + 32k x 4 */
+#define INTEL_ID_28F128P30T 0x88188818 /* 128M =  64K x 255 + 32k x 4 */
+#define INTEL_ID_28F128P30B 0x881B881B /* 128M =  64K x 255 + 32k x 4 */
+#define INTEL_ID_28F256P30T 0x88198819 /* 256M = 128K x 255 + 32k x 4 */
+#define INTEL_ID_28F256P30B 0x881C881C /* 256M = 128K x 255 + 32k x 4 */
 
 #define INTEL_ID_28F160S3   0x00D000D0 /*  16M = 512K x  32 (64kB x 32)        */
 #define INTEL_ID_28F320S3   0x00D400D4 /*  32M = 512K x  64 (64kB x 64)        */

diff --git a/include/ft_build.h b/include/ft_build.h
index 9104b1a55508de8335bd721e790bc19e2cac4be8..47ca575d9fe295153644ecad54ba523573a24fb9 100644 (file)
--- a/include/ft_build.h
+++ b/include/ft_build.h
@@ -57,10 +57,12 @@ void ft_prop_int(struct ft_cxt *cxt, const char *name, int val);
 void ft_begin(struct ft_cxt *cxt, void *blob, int max_size);
 void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size);
 
-void ft_setup(void *blob, int size, bd_t * bd);
+void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end);
 
 void ft_dump_blob(const void *bphp);
 void ft_merge_blob(struct ft_cxt *cxt, void *blob);
 void *ft_get_prop(void *bphp, const char *propname, int *szp);
 
+void ft_board_setup(void *blob, bd_t *bd);
+
 #endif

diff --git a/include/image.h b/include/image.h
index af37bcad5aae712549fc38cd764ed59f95849ca4..139df0b2d1e783b836a81689a053071bd290f1a8 100644 (file)
--- a/include/image.h
+++ b/include/image.h
@@ -75,6 +75,7 @@
 #define IH_CPU_NIOS            13      /* Nios-32      */
 #define IH_CPU_MICROBLAZE      14      /* MicroBlaze   */
 #define IH_CPU_NIOS2           15      /* Nios-II      */
+#define IH_CPU_BLACKFIN                16      /* Blackfin     */
 
 /*
  * Image Types

diff --git a/include/linux/mtd/compat.h b/include/linux/mtd/compat.h
new file mode 100644 (file)
index 0000000..460cd45
--- /dev/null
+++ b/include/linux/mtd/compat.h
@@ -0,0 +1,44 @@
+#ifndef _LINUX_COMPAT_H_
+#define _LINUX_COMPAT_H_
+
+#define __user
+#define __iomem
+
+#define ndelay(x)      udelay(1)
+
+#define printk printf
+
+#define KERN_EMERG
+#define KERN_ALERT
+#define KERN_CRIT
+#define KERN_ERR
+#define KERN_WARNING
+#define KERN_NOTICE
+#define KERN_INFO
+#define KERN_DEBUG
+
+#define kmalloc(size, flags)   malloc(size)
+#define kfree(ptr)             free(ptr)
+
+/*
+ * ..and if you can't take the strict
+ * types, you can specify one yourself.
+ *
+ * Or not use min/max at all, of course.
+ */
+#define min_t(type,x,y) \
+       ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
+#define max_t(type,x,y) \
+       ({ type __x = (x); type __y = (y); __x > __y ? __x: __y; })
+
+#define BUG() do { \
+       printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \
+} while (0)
+
+#define BUG_ON(condition) do { if (condition) BUG(); } while(0)
+
+#define likely(x)      __builtin_expect(!!(x), 1)
+#define unlikely(x)    __builtin_expect(!!(x), 0)
+
+#define PAGE_SIZE      4096
+#endif

diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h
index ebf9a7692418c16edb003776b00c78e243a3ae2c..eeb1d7e98e639d0dec211448d58048865c2b441b 100644 (file)
--- a/include/linux/mtd/doc2000.h
+++ b/include/linux/mtd/doc2000.h
@@ -91,6 +91,13 @@ struct DiskOnChip;
 #define ADDR_PAGE 2
 #define ADDR_COLUMN_PAGE 3
 
+struct Nand {
+       char floor, chip;
+       unsigned long curadr;
+       unsigned char curmode;
+       /* Also some erase/write/pipeline info when we get that far */
+};
+
 struct DiskOnChip {
        unsigned long physadr;
        unsigned long virtadr;
@@ -148,4 +155,62 @@ void doc_probe(unsigned long physadr);
 
 void doc_print(struct DiskOnChip*);
 
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0         0
+#define NAND_CMD_READ1         1
+#define NAND_CMD_PAGEPROG      0x10
+#define NAND_CMD_READOOB       0x50
+#define NAND_CMD_ERASE1                0x60
+#define NAND_CMD_STATUS                0x70
+#define NAND_CMD_SEQIN         0x80
+#define NAND_CMD_READID                0x90
+#define NAND_CMD_ERASE2                0xd0
+#define NAND_CMD_RESET         0xff
+
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA       0x98
+#define NAND_MFR_SAMSUNG       0xec
+
+/*
+ * NAND Flash Device ID Structure
+ *
+ * Structure overview:
+ *
+ *  name - Complete name of device
+ *
+ *  manufacture_id - manufacturer ID code of device.
+ *
+ *  model_id - model ID code of device.
+ *
+ *  chipshift - total number of address bits for the device which
+ *              is used to calculate address offsets and the total
+ *              number of bytes the device is capable of.
+ *
+ *  page256 - denotes if flash device has 256 byte pages or not.
+ *
+ *  pageadrlen - number of bytes minus one needed to hold the
+ *               complete address into the flash array. Keep in
+ *               mind that when a read or write is done to a
+ *               specific address, the address is input serially
+ *               8 bits at a time. This structure member is used
+ *               by the read/write routines as a loop index for
+ *               shifting the address out 8 bits at a time.
+ *
+ *  erasesize - size of an erase block in the flash device.
+ */
+struct nand_flash_dev {
+       char * name;
+       int manufacture_id;
+       int model_id;
+       int chipshift;
+       char page256;
+       char pageadrlen;
+       unsigned long erasesize;
+       int bus16;
+};
+
 #endif /* __MTD_DOC2000_H__ */

diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h
new file mode 100644 (file)
index 0000000..3d1d416
--- /dev/null
+++ b/include/linux/mtd/mtd-abi.h
@@ -0,0 +1,99 @@
+/*
+ * $Id: mtd-abi.h,v 1.7 2004/11/23 15:37:32 gleixner Exp $
+ *
+ * Portions of MTD ABI definition which are shared by kernel and user space
+ */
+
+#ifndef __MTD_ABI_H__
+#define __MTD_ABI_H__
+
+struct erase_info_user {
+       uint32_t start;
+       uint32_t length;
+};
+
+struct mtd_oob_buf {
+       uint32_t start;
+       uint32_t length;
+       unsigned char *ptr;
+};
+
+#define MTD_ABSENT             0
+#define MTD_RAM                        1
+#define MTD_ROM                        2
+#define MTD_NORFLASH           3
+#define MTD_NANDFLASH          4
+#define MTD_PEROM              5
+#define MTD_OTHER              14
+#define MTD_UNKNOWN            15
+
+#define MTD_CLEAR_BITS         1       /* Bits can be cleared (flash) */
+#define MTD_SET_BITS           2       /* Bits can be set */
+#define MTD_ERASEABLE          4       /* Has an erase function */
+#define MTD_WRITEB_WRITEABLE   8       /* Direct IO is possible */
+#define MTD_VOLATILE           16      /* Set for RAMs */
+#define MTD_XIP                        32      /* eXecute-In-Place possible */
+#define MTD_OOB                        64      /* Out-of-band data (NAND flash) */
+#define MTD_ECC                        128     /* Device capable of automatic ECC */
+#define MTD_NO_VIRTBLOCKS      256     /* Virtual blocks not allowed */
+
+/* Some common devices / combinations of capabilities */
+#define MTD_CAP_ROM            0
+#define MTD_CAP_RAM            (MTD_CLEAR_BITS|MTD_SET_BITS|MTD_WRITEB_WRITEABLE)
+#define MTD_CAP_NORFLASH        (MTD_CLEAR_BITS|MTD_ERASEABLE)
+#define MTD_CAP_NANDFLASH       (MTD_CLEAR_BITS|MTD_ERASEABLE|MTD_OOB)
+#define MTD_WRITEABLE          (MTD_CLEAR_BITS|MTD_SET_BITS)
+
+
+/* Types of automatic ECC/Checksum available */
+#define MTD_ECC_NONE           0       /* No automatic ECC available */
+#define MTD_ECC_RS_DiskOnChip  1       /* Automatic ECC on DiskOnChip */
+#define MTD_ECC_SW             2       /* SW ECC for Toshiba & Samsung devices */
+
+/* ECC byte placement */
+#define MTD_NANDECC_OFF                0       /* Switch off ECC (Not recommended) */
+#define MTD_NANDECC_PLACE      1       /* Use the given placement in the structure (YAFFS1 legacy mode) */
+#define MTD_NANDECC_AUTOPLACE  2       /* Use the default placement scheme */
+#define MTD_NANDECC_PLACEONLY  3       /* Use the given placement in the structure (Do not store ecc result on read) */
+#define MTD_NANDECC_AUTOPL_USR         4       /* Use the given autoplacement scheme rather than using the default */
+
+struct mtd_info_user {
+       uint8_t type;
+       uint32_t flags;
+       uint32_t size;   /* Total size of the MTD */
+       uint32_t erasesize;
+       uint32_t oobblock;  /* Size of OOB blocks (e.g. 512) */
+       uint32_t oobsize;   /* Amount of OOB data per block (e.g. 16) */
+       uint32_t ecctype;
+       uint32_t eccsize;
+};
+
+struct region_info_user {
+       uint32_t offset;                /* At which this region starts,
+                                        * from the beginning of the MTD */
+       uint32_t erasesize;             /* For this region */
+       uint32_t numblocks;             /* Number of blocks in this region */
+       uint32_t regionindex;
+};
+
+#define MEMGETINFO              _IOR('M', 1, struct mtd_info_user)
+#define MEMERASE                _IOW('M', 2, struct erase_info_user)
+#define MEMWRITEOOB             _IOWR('M', 3, struct mtd_oob_buf)
+#define MEMREADOOB              _IOWR('M', 4, struct mtd_oob_buf)
+#define MEMLOCK                 _IOW('M', 5, struct erase_info_user)
+#define MEMUNLOCK               _IOW('M', 6, struct erase_info_user)
+#define MEMGETREGIONCOUNT      _IOR('M', 7, int)
+#define MEMGETREGIONINFO       _IOWR('M', 8, struct region_info_user)
+#define MEMSETOOBSEL           _IOW('M', 9, struct nand_oobinfo)
+#define MEMGETOOBSEL           _IOR('M', 10, struct nand_oobinfo)
+#define MEMGETBADBLOCK         _IOW('M', 11, loff_t)
+#define MEMSETBADBLOCK         _IOW('M', 12, loff_t)
+
+struct nand_oobinfo {
+       uint32_t useecc;
+       uint32_t eccbytes;
+       uint32_t oobfree[8][2];
+       uint32_t eccpos[32];
+};
+
+#endif /* __MTD_ABI_H__ */

diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
new file mode 100644 (file)
index 0000000..13e9080
--- /dev/null
+++ b/include/linux/mtd/mtd.h
@@ -0,0 +1,214 @@
+/*
+ * $Id: mtd.h,v 1.56 2004/08/09 18:46:04 dmarlin Exp $
+ *
+ * Copyright (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> et al.
+ *
+ * Released under GPL
+ */
+
+#ifndef __MTD_MTD_H__
+#define __MTD_MTD_H__
+#include <linux/types.h>
+#include <linux/mtd/mtd-abi.h>
+
+#define MAX_MTD_DEVICES 16
+
+#define MTD_ERASE_PENDING              0x01
+#define MTD_ERASING            0x02
+#define MTD_ERASE_SUSPEND      0x04
+#define MTD_ERASE_DONE          0x08
+#define MTD_ERASE_FAILED        0x10
+
+/* If the erase fails, fail_addr might indicate exactly which block failed.  If
+   fail_addr = 0xffffffff, the failure was not at the device level or was not
+   specific to any particular block. */
+struct erase_info {
+       struct mtd_info *mtd;
+       u_int32_t addr;
+       u_int32_t len;
+       u_int32_t fail_addr;
+       u_long time;
+       u_long retries;
+       u_int dev;
+       u_int cell;
+       void (*callback) (struct erase_info *self);
+       u_long priv;
+       u_char state;
+       struct erase_info *next;
+};
+
+struct mtd_erase_region_info {
+       u_int32_t offset;                       /* At which this region starts, from the beginning of the MTD */
+       u_int32_t erasesize;            /* For this region */
+       u_int32_t numblocks;            /* Number of blocks of erasesize in this region */
+};
+
+struct mtd_info {
+       u_char type;
+       u_int32_t flags;
+       u_int32_t size;  /* Total size of the MTD */
+
+       /* "Major" erase size for the device. Naïve users may take this
+        * to be the only erase size available, or may use the more detailed
+        * information below if they desire
+        */
+       u_int32_t erasesize;
+
+       u_int32_t oobblock;  /* Size of OOB blocks (e.g. 512) */
+       u_int32_t oobsize;   /* Amount of OOB data per block (e.g. 16) */
+       u_int32_t oobavail;  /* Number of bytes in OOB area available for fs  */
+       u_int32_t ecctype;
+       u_int32_t eccsize;
+
+
+       /* Kernel-only stuff starts here. */
+       char *name;
+       int index;
+
+       /* oobinfo is a nand_oobinfo structure, which can be set by iotcl (MEMSETOOBINFO) */
+       struct nand_oobinfo oobinfo;
+
+       /* Data for variable erase regions. If numeraseregions is zero,
+        * it means that the whole device has erasesize as given above.
+        */
+       int numeraseregions;
+       struct mtd_erase_region_info *eraseregions;
+
+       /* This really shouldn't be here. It can go away in 2.5 */
+       u_int32_t bank_size;
+
+       int (*erase) (struct mtd_info *mtd, struct erase_info *instr);
+
+       /* This stuff for eXecute-In-Place */
+       int (*point) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char **mtdbuf);
+
+       /* We probably shouldn't allow XIP if the unpoint isn't a NULL */
+       void (*unpoint) (struct mtd_info *mtd, u_char * addr, loff_t from, size_t len);
+
+
+       int (*read) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
+       int (*write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf);
+
+       int (*read_ecc) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf, u_char *eccbuf, struct nand_oobinfo *oobsel);
+       int (*write_ecc) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf, u_char *eccbuf, struct nand_oobinfo *oobsel);
+
+       int (*read_oob) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
+       int (*write_oob) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf);
+
+       /*
+        * Methods to access the protection register area, present in some
+        * flash devices. The user data is one time programmable but the
+        * factory data is read only.
+        */
+       int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
+
+       int (*read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
+
+       /* This function is not yet implemented */
+       int (*write_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
+#if 0
+       /* kvec-based read/write methods. We need these especially for NAND flash,
+          with its limited number of write cycles per erase.
+          NB: The 'count' parameter is the number of _vectors_, each of
+          which contains an (ofs, len) tuple.
+       */
+       int (*readv) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, size_t *retlen);
+       int (*readv_ecc) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from,
+               size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel);
+       int (*writev) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, size_t *retlen);
+       int (*writev_ecc) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to,
+               size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel);
+#endif
+       /* Sync */
+       void (*sync) (struct mtd_info *mtd);
+#if 0
+       /* Chip-supported device locking */
+       int (*lock) (struct mtd_info *mtd, loff_t ofs, size_t len);
+       int (*unlock) (struct mtd_info *mtd, loff_t ofs, size_t len);
+
+       /* Power Management functions */
+       int (*suspend) (struct mtd_info *mtd);
+       void (*resume) (struct mtd_info *mtd);
+#endif
+       /* Bad block management functions */
+       int (*block_isbad) (struct mtd_info *mtd, loff_t ofs);
+       int (*block_markbad) (struct mtd_info *mtd, loff_t ofs);
+
+       void *priv;
+
+       struct module *owner;
+       int usecount;
+};
+
+
+       /* Kernel-side ioctl definitions */
+
+extern int add_mtd_device(struct mtd_info *mtd);
+extern int del_mtd_device (struct mtd_info *mtd);
+
+extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num);
+
+extern void put_mtd_device(struct mtd_info *mtd);
+
+#if 0
+struct mtd_notifier {
+       void (*add)(struct mtd_info *mtd);
+       void (*remove)(struct mtd_info *mtd);
+       struct list_head list;
+};
+
+
+extern void register_mtd_user (struct mtd_notifier *new);
+extern int unregister_mtd_user (struct mtd_notifier *old);
+
+int default_mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
+                      unsigned long count, loff_t to, size_t *retlen);
+
+int default_mtd_readv(struct mtd_info *mtd, struct kvec *vecs,
+                     unsigned long count, loff_t from, size_t *retlen);
+#endif
+
+#define MTD_ERASE(mtd, args...) (*(mtd->erase))(mtd, args)
+#define MTD_POINT(mtd, a,b,c,d) (*(mtd->point))(mtd, a,b,c, (u_char **)(d))
+#define MTD_UNPOINT(mtd, arg) (*(mtd->unpoint))(mtd, (u_char *)arg)
+#define MTD_READ(mtd, args...) (*(mtd->read))(mtd, args)
+#define MTD_WRITE(mtd, args...) (*(mtd->write))(mtd, args)
+#define MTD_READV(mtd, args...) (*(mtd->readv))(mtd, args)
+#define MTD_WRITEV(mtd, args...) (*(mtd->writev))(mtd, args)
+#define MTD_READECC(mtd, args...) (*(mtd->read_ecc))(mtd, args)
+#define MTD_WRITEECC(mtd, args...) (*(mtd->write_ecc))(mtd, args)
+#define MTD_READOOB(mtd, args...) (*(mtd->read_oob))(mtd, args)
+#define MTD_WRITEOOB(mtd, args...) (*(mtd->write_oob))(mtd, args)
+#define MTD_SYNC(mtd) do { if (mtd->sync) (*(mtd->sync))(mtd);  } while (0)
+
+
+#ifdef CONFIG_MTD_PARTITIONS
+void mtd_erase_callback(struct erase_info *instr);
+#else
+static inline void mtd_erase_callback(struct erase_info *instr)
+{
+       if (instr->callback)
+               instr->callback(instr);
+}
+#endif
+
+/*
+ * Debugging macro and defines
+ */
+#define MTD_DEBUG_LEVEL0       (0)     /* Quiet   */
+#define MTD_DEBUG_LEVEL1       (1)     /* Audible */
+#define MTD_DEBUG_LEVEL2       (2)     /* Loud    */
+#define MTD_DEBUG_LEVEL3       (3)     /* Noisy   */
+
+#ifdef CONFIG_MTD_DEBUG
+#define DEBUG(n, args...)                              \
+       do {                                            \
+               if (n <= CONFIG_MTD_DEBUG_VERBOSE)      \
+                       printk(KERN_INFO args);         \
+       } while(0)
+#else /* CONFIG_MTD_DEBUG */
+#define DEBUG(n, args...) do { } while(0)
+
+#endif /* CONFIG_MTD_DEBUG */
+
+#endif /* __MTD_MTD_H__ */

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 5236904959ef8262fdca1465481183bad27b7a1c..a5227188d4f206e58aa37493170da32bb16566fa 100644 (file)
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -2,10 +2,10 @@
  *  linux/include/linux/mtd/nand.h
  *
  *  Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
- *                     Steven J. Hill <sjhill@cotw.com>
- *                    Thomas Gleixner <gleixner@autronix.de>
+ *                     Steven J. Hill <sjhill@realitydiluted.com>
+ *                    Thomas Gleixner <tglx@linutronix.de>
  *
- * $Id: nand.h,v 1.7 2003/07/24 23:30:46 a0384864 Exp $
+ * $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -32,10 +32,65 @@
  *                     command delay times for different chips
  *   04-28-2002 TG     OOB config defines moved from nand.c to avoid duplicate
  *                     defines in jffs2/wbuf.c
+ *   08-07-2002 TG     forced bad block location to byte 5 of OOB, even if
+ *                     CONFIG_MTD_NAND_ECC_JFFS2 is not set
+ *   08-10-2002 TG     extensions to nand_chip structure to support HW-ECC
+ *
+ *   08-29-2002 tglx   nand_chip structure: data_poi for selecting
+ *                     internal / fs-driver buffer
+ *                     support for 6byte/512byte hardware ECC
+ *                     read_ecc, write_ecc extended for different oob-layout
+ *                     oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB,
+ *                     NAND_YAFFS_OOB
+ *  11-25-2002 tglx    Added Manufacturer code FUJITSU, NATIONAL
+ *                     Split manufacturer and device ID structures
+ *
+ *  02-08-2004 tglx    added option field to nand structure for chip anomalities
+ *  05-25-2004 tglx    added bad block table support, ST-MICRO manufacturer id
+ *                     update of nand_chip structure description
  */
 #ifndef __LINUX_MTD_NAND_H
 #define __LINUX_MTD_NAND_H
 
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+
+struct mtd_info;
+/* Scan and identify a NAND device */
+extern int nand_scan (struct mtd_info *mtd, int max_chips);
+/* Free resources held by the NAND device */
+extern void nand_release (struct mtd_info *mtd);
+
+/* Read raw data from the device without ECC */
+extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen);
+
+
+/* This constant declares the max. oobsize / page, which
+ * is supported now. If you add a chip with bigger oobsize/page
+ * adjust this accordingly.
+ */
+#define NAND_MAX_OOBSIZE       64
+
+/*
+ * Constants for hardware specific CLE/ALE/NCE function
+*/
+/* Select the chip by setting nCE to low */
+#define NAND_CTL_SETNCE        1
+/* Deselect the chip by setting nCE to high */
+#define NAND_CTL_CLRNCE                2
+/* Select the command latch by setting CLE to high */
+#define NAND_CTL_SETCLE                3
+/* Deselect the command latch by setting CLE to low */
+#define NAND_CTL_CLRCLE                4
+/* Select the address latch by setting ALE to high */
+#define NAND_CTL_SETALE                5
+/* Deselect the address latch by setting ALE to low */
+#define NAND_CTL_CLRALE                6
+/* Set write protection by setting WP to high. Not used! */
+#define NAND_CTL_SETWP         7
+/* Clear write protection by setting WP to low. Not used! */
+#define NAND_CTL_CLRWP         8
+
 /*
  * Standard NAND flash commands
  */
@@ -45,12 +100,104 @@
 #define NAND_CMD_READOOB       0x50
 #define NAND_CMD_ERASE1                0x60
 #define NAND_CMD_STATUS                0x70
+#define NAND_CMD_STATUS_MULTI  0x71
 #define NAND_CMD_SEQIN         0x80
 #define NAND_CMD_READID                0x90
 #define NAND_CMD_ERASE2                0xd0
 #define NAND_CMD_RESET         0xff
 
+/* Extended commands for large page devices */
+#define NAND_CMD_READSTART     0x30
+#define NAND_CMD_CACHEDPROG    0x15
+
+/* Status bits */
+#define NAND_STATUS_FAIL       0x01
+#define NAND_STATUS_FAIL_N1    0x02
+#define NAND_STATUS_TRUE_READY 0x20
+#define NAND_STATUS_READY      0x40
+#define NAND_STATUS_WP         0x80
+
 /*
+ * Constants for ECC_MODES
+ */
+
+/* No ECC. Usage is not recommended ! */
+#define NAND_ECC_NONE          0
+/* Software ECC 3 byte ECC per 256 Byte data */
+#define NAND_ECC_SOFT          1
+/* Hardware ECC 3 byte ECC per 256 Byte data */
+#define NAND_ECC_HW3_256       2
+/* Hardware ECC 3 byte ECC per 512 Byte data */
+#define NAND_ECC_HW3_512       3
+/* Hardware ECC 3 byte ECC per 512 Byte data */
+#define NAND_ECC_HW6_512       4
+/* Hardware ECC 8 byte ECC per 512 Byte data */
+#define NAND_ECC_HW8_512       6
+/* Hardware ECC 12 byte ECC per 2048 Byte data */
+#define NAND_ECC_HW12_2048     7
+
+/*
+ * Constants for Hardware ECC
+*/
+/* Reset Hardware ECC for read */
+#define NAND_ECC_READ          0
+/* Reset Hardware ECC for write */
+#define NAND_ECC_WRITE         1
+/* Enable Hardware ECC before syndrom is read back from flash */
+#define NAND_ECC_READSYN       2
+
+/* Option constants for bizarre disfunctionality and real
+*  features
+*/
+/* Chip can not auto increment pages */
+#define NAND_NO_AUTOINCR       0x00000001
+/* Buswitdh is 16 bit */
+#define NAND_BUSWIDTH_16       0x00000002
+/* Device supports partial programming without padding */
+#define NAND_NO_PADDING                0x00000004
+/* Chip has cache program function */
+#define NAND_CACHEPRG          0x00000008
+/* Chip has copy back function */
+#define NAND_COPYBACK          0x00000010
+/* AND Chip which has 4 banks and a confusing page / block
+ * assignment. See Renesas datasheet for further information */
+#define NAND_IS_AND            0x00000020
+/* Chip has a array of 4 pages which can be read without
+ * additional ready /busy waits */
+#define NAND_4PAGE_ARRAY       0x00000040
+
+/* Options valid for Samsung large page devices */
+#define NAND_SAMSUNG_LP_OPTIONS \
+       (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
+
+/* Macros to identify the above */
+#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
+#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
+#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
+#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
+
+/* Mask to zero out the chip options, which come from the id table */
+#define NAND_CHIPOPTIONS_MSK   (0x0000ffff & ~NAND_NO_AUTOINCR)
+
+/* Non chip related options */
+/* Use a flash based bad block table. This option is passed to the
+ * default bad block table function. */
+#define NAND_USE_FLASH_BBT     0x00010000
+/* The hw ecc generator provides a syndrome instead a ecc value on read
+ * This can only work if we have the ecc bytes directly behind the
+ * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
+#define NAND_HWECC_SYNDROME    0x00020000
+
+
+/* Options set by nand scan */
+/* Nand scan has allocated oob_buf */
+#define NAND_OOBBUF_ALLOC      0x40000000
+/* Nand scan has allocated data_buf */
+#define NAND_DATABUF_ALLOC     0x80000000
+
+
+/*
+ * nand_state_t - chip states
  * Enumeration for NAND flash chip state
  */
 typedef enum {
@@ -58,71 +205,138 @@ typedef enum {
        FL_READING,
        FL_WRITING,
        FL_ERASING,
-       FL_SYNCING
+       FL_SYNCING,
+       FL_CACHEDPRG,
 } nand_state_t;
 
+/* Keep gcc happy */
+struct nand_chip;
 
-/*
- * NAND Private Flash Chip Data
- *
- * Structure overview:
- *
- *  IO_ADDR - address to access the 8 I/O lines of the flash device
- *
- *  hwcontrol - hardwarespecific function for accesing control-lines
- *
- *  dev_ready - hardwarespecific function for accesing device ready/busy line
- *
- *  chip_lock - spinlock used to protect access to this structure
- *
- *  wq - wait queue to sleep on if a NAND operation is in progress
- *
- *  state - give the current state of the NAND device
- *
- *  page_shift - number of address bits in a page (column address bits)
- *
- *  data_buf - data buffer passed to/from MTD user modules
- *
- *  data_cache - data cache for redundant page access and shadow for
- *              ECC failure
- *
- *  ecc_code_buf - used only for holding calculated or read ECCs for
- *                 a page read or written when ECC is in use
- *
- *  reserved - padding to make structure fall on word boundary if
- *             when ECC is in use
+#if 0
+/**
+ * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
+ * @lock:               protection lock
+ * @active:            the mtd device which holds the controller currently
  */
-struct Nand {
-       char floor, chip;
-       unsigned long curadr;
-       unsigned char curmode;
-       /* Also some erase/write/pipeline info when we get that far */
+struct nand_hw_control {
+       spinlock_t       lock;
+       struct nand_chip *active;
 };
+#endif
+
+/**
+ * struct nand_chip - NAND Private Flash Chip Data
+ * @IO_ADDR_R:         [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
+ * @IO_ADDR_W:         [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
+ * @read_byte:         [REPLACEABLE] read one byte from the chip
+ * @write_byte:                [REPLACEABLE] write one byte to the chip
+ * @read_word:         [REPLACEABLE] read one word from the chip
+ * @write_word:                [REPLACEABLE] write one word to the chip
+ * @write_buf:         [REPLACEABLE] write data from the buffer to the chip
+ * @read_buf:          [REPLACEABLE] read data from the chip into the buffer
+ * @verify_buf:                [REPLACEABLE] verify buffer contents against the chip data
+ * @select_chip:       [REPLACEABLE] select chip nr
+ * @block_bad:         [REPLACEABLE] check, if the block is bad
+ * @block_markbad:     [REPLACEABLE] mark the block bad
+ * @hwcontrol:         [BOARDSPECIFIC] hardwarespecific function for accesing control-lines
+ * @dev_ready:         [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
+ *                     If set to NULL no access to ready/busy is available and the ready/busy information
+ *                     is read from the chip status register
+ * @cmdfunc:           [REPLACEABLE] hardwarespecific function for writing commands to the chip
+ * @waitfunc:          [REPLACEABLE] hardwarespecific function for wait on ready
+ * @calculate_ecc:     [REPLACEABLE] function for ecc calculation or readback from ecc hardware
+ * @correct_data:      [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
+ * @enable_hwecc:      [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
+ *                     be provided if a hardware ECC is available
+ * @erase_cmd:         [INTERN] erase command write function, selectable due to AND support
+ * @scan_bbt:          [REPLACEABLE] function to scan bad block table
+ * @eccmode:           [BOARDSPECIFIC] mode of ecc, see defines
+ * @eccsize:           [INTERN] databytes used per ecc-calculation
+ * @eccbytes:          [INTERN] number of ecc bytes per ecc-calculation step
+ * @eccsteps:          [INTERN] number of ecc calculation steps per page
+ * @chip_delay:                [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
+ * @chip_lock:         [INTERN] spinlock used to protect access to this structure and the chip
+ * @wq:                        [INTERN] wait queue to sleep on if a NAND operation is in progress
+ * @state:             [INTERN] the current state of the NAND device
+ * @page_shift:                [INTERN] number of address bits in a page (column address bits)
+ * @phys_erase_shift:  [INTERN] number of address bits in a physical eraseblock
+ * @bbt_erase_shift:   [INTERN] number of address bits in a bbt entry
+ * @chip_shift:                [INTERN] number of address bits in one chip
+ * @data_buf:          [INTERN] internal buffer for one page + oob
+ * @oob_buf:           [INTERN] oob buffer for one eraseblock
+ * @oobdirty:          [INTERN] indicates that oob_buf must be reinitialized
+ * @data_poi:          [INTERN] pointer to a data buffer
+ * @options:           [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
+ *                     special functionality. See the defines for further explanation
+ * @badblockpos:       [INTERN] position of the bad block marker in the oob area
+ * @numchips:          [INTERN] number of physical chips
+ * @chipsize:          [INTERN] the size of one chip for multichip arrays
+ * @pagemask:          [INTERN] page number mask = number of (pages / chip) - 1
+ * @pagebuf:           [INTERN] holds the pagenumber which is currently in data_buf
+ * @autooob:           [REPLACEABLE] the default (auto)placement scheme
+ * @bbt:               [INTERN] bad block table pointer
+ * @bbt_td:            [REPLACEABLE] bad block table descriptor for flash lookup
+ * @bbt_md:            [REPLACEABLE] bad block table mirror descriptor
+ * @badblock_pattern:  [REPLACEABLE] bad block scan pattern used for initial bad block scan
+ * @controller:                [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices
+ * @priv:              [OPTIONAL] pointer to private chip date
+ */
 
 struct nand_chip {
+       void  __iomem   *IO_ADDR_R;
+       void  __iomem   *IO_ADDR_W;
+
+       u_char          (*read_byte)(struct mtd_info *mtd);
+       void            (*write_byte)(struct mtd_info *mtd, u_char byte);
+       u16             (*read_word)(struct mtd_info *mtd);
+       void            (*write_word)(struct mtd_info *mtd, u16 word);
+
+       void            (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len);
+       void            (*read_buf)(struct mtd_info *mtd, u_char *buf, int len);
+       int             (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len);
+       void            (*select_chip)(struct mtd_info *mtd, int chip);
+       int             (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
+       int             (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
+       void            (*hwcontrol)(struct mtd_info *mtd, int cmd);
+       int             (*dev_ready)(struct mtd_info *mtd);
+       void            (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
+       int             (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
+       int             (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
+       int             (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
+       void            (*enable_hwecc)(struct mtd_info *mtd, int mode);
+       void            (*erase_cmd)(struct mtd_info *mtd, int page);
+       int             (*scan_bbt)(struct mtd_info *mtd);
+       int             eccmode;
+       int             eccsize;
+       int             eccbytes;
+       int             eccsteps;
+       int             chip_delay;
+#if 0
+       spinlock_t      chip_lock;
+       wait_queue_head_t wq;
+       nand_state_t    state;
+#endif
        int             page_shift;
+       int             phys_erase_shift;
+       int             bbt_erase_shift;
+       int             chip_shift;
        u_char          *data_buf;
-       u_char          *data_cache;
-       int             cache_page;
-       u_char          ecc_code_buf[6];
-       u_char          reserved[2];
-       char ChipID; /* Type of DiskOnChip */
-       struct Nand *chips;
-       int chipshift;
-       char* chips_name;
-       unsigned long erasesize;
-       unsigned long mfr; /* Flash IDs - only one type of flash per device */
-       unsigned long id;
-       char* name;
-       int numchips;
-       char page256;
-       char pageadrlen;
-       unsigned long IO_ADDR;  /* address to access the 8 I/O lines to the flash device */
-       unsigned long totlen;
-       uint oobblock;  /* Size of OOB blocks (e.g. 512) */
-       uint oobsize;   /* Amount of OOB data per block (e.g. 16) */
-       uint eccsize;
-       int bus16;
+       u_char          *oob_buf;
+       int             oobdirty;
+       u_char          *data_poi;
+       unsigned int    options;
+       int             badblockpos;
+       int             numchips;
+       unsigned long   chipsize;
+       int             pagemask;
+       int             pagebuf;
+       struct nand_oobinfo     *autooob;
+       uint8_t         *bbt;
+       struct nand_bbt_descr   *bbt_td;
+       struct nand_bbt_descr   *bbt_md;
+       struct nand_bbt_descr   *badblock_pattern;
+       struct nand_hw_control  *controller;
+       void            *priv;
 };
 
 /*
@@ -130,71 +344,125 @@ struct nand_chip {
  */
 #define NAND_MFR_TOSHIBA       0x98
 #define NAND_MFR_SAMSUNG       0xec
+#define NAND_MFR_FUJITSU       0x04
+#define NAND_MFR_NATIONAL      0x8f
+#define NAND_MFR_RENESAS       0x07
+#define NAND_MFR_STMICRO       0x20
 
-/*
- * NAND Flash Device ID Structure
- *
- * Structure overview:
- *
- *  name - Complete name of device
- *
- *  manufacture_id - manufacturer ID code of device.
- *
- *  model_id - model ID code of device.
+/**
+ * struct nand_flash_dev - NAND Flash Device ID Structure
  *
- *  chipshift - total number of address bits for the device which
- *              is used to calculate address offsets and the total
- *              number of bytes the device is capable of.
- *
- *  page256 - denotes if flash device has 256 byte pages or not.
- *
- *  pageadrlen - number of bytes minus one needed to hold the
- *               complete address into the flash array. Keep in
- *               mind that when a read or write is done to a
- *               specific address, the address is input serially
- *               8 bits at a time. This structure member is used
- *               by the read/write routines as a loop index for
- *               shifting the address out 8 bits at a time.
- *
- *  erasesize - size of an erase block in the flash device.
+ * @name:      Identify the device type
+ * @id:        device ID code
+ * @pagesize:          Pagesize in bytes. Either 256 or 512 or 0
+ *             If the pagesize is 0, then the real pagesize
+ *             and the eraseize are determined from the
+ *             extended id bytes in the chip
+ * @erasesize:         Size of an erase block in the flash device.
+ * @chipsize:          Total chipsize in Mega Bytes
+ * @options:   Bitfield to store chip relevant options
  */
 struct nand_flash_dev {
-       char * name;
-       int manufacture_id;
-       int model_id;
-       int chipshift;
-       char page256;
-       char pageadrlen;
+       char *name;
+       int id;
+       unsigned long pagesize;
+       unsigned long chipsize;
        unsigned long erasesize;
-       int bus16;
+       unsigned long options;
 };
 
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @name:      Manufacturer name
+ * @id:        manufacturer ID code of device.
+*/
+struct nand_manufacturers {
+       int id;
+       char * name;
+};
+
+extern struct nand_flash_dev nand_flash_ids[];
+extern struct nand_manufacturers nand_manuf_ids[];
+
+/**
+ * struct nand_bbt_descr - bad block table descriptor
+ * @options:   options for this descriptor
+ * @pages:     the page(s) where we find the bbt, used with option BBT_ABSPAGE
+ *             when bbt is searched, then we store the found bbts pages here.
+ *             Its an array and supports up to 8 chips now
+ * @offs:      offset of the pattern in the oob area of the page
+ * @veroffs:   offset of the bbt version counter in the oob are of the page
+ * @version:   version read from the bbt page during scan
+ * @len:       length of the pattern, if 0 no pattern check is performed
+ * @maxblocks: maximum number of blocks to search for a bbt. This number of
+ *             blocks is reserved at the end of the device where the tables are
+ *             written.
+ * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
+ *              bad) block in the stored bbt
+ * @pattern:   pattern to identify bad block table or factory marked good /
+ *             bad blocks, can be NULL, if len = 0
+ *
+ * Descriptor for the bad block table marker and the descriptor for the
+ * pattern which identifies good and bad blocks. The assumption is made
+ * that the pattern and the version count are always located in the oob area
+ * of the first block.
+ */
+struct nand_bbt_descr {
+       int     options;
+       int     pages[NAND_MAX_CHIPS];
+       int     offs;
+       int     veroffs;
+       uint8_t version[NAND_MAX_CHIPS];
+       int     len;
+       int     maxblocks;
+       int     reserved_block_code;
+       uint8_t *pattern;
+};
+
+/* Options for the bad block table descriptors */
+
+/* The number of bits used per block in the bbt on the device */
+#define NAND_BBT_NRBITS_MSK    0x0000000F
+#define NAND_BBT_1BIT          0x00000001
+#define NAND_BBT_2BIT          0x00000002
+#define NAND_BBT_4BIT          0x00000004
+#define NAND_BBT_8BIT          0x00000008
+/* The bad block table is in the last good block of the device */
+#define        NAND_BBT_LASTBLOCK      0x00000010
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_ABSPAGE       0x00000020
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_SEARCH                0x00000040
+/* bbt is stored per chip on multichip devices */
+#define NAND_BBT_PERCHIP       0x00000080
+/* bbt has a version counter at offset veroffs */
+#define NAND_BBT_VERSION       0x00000100
+/* Create a bbt if none axists */
+#define NAND_BBT_CREATE                0x00000200
+/* Search good / bad pattern through all pages of a block */
+#define NAND_BBT_SCANALLPAGES  0x00000400
+/* Scan block empty during good / bad block scan */
+#define NAND_BBT_SCANEMPTY     0x00000800
+/* Write bbt if neccecary */
+#define NAND_BBT_WRITE         0x00001000
+/* Read and write back block contents when writing bbt */
+#define NAND_BBT_SAVECONTENT   0x00002000
+/* Search good / bad pattern on the first and the second page */
+#define NAND_BBT_SCAN2NDPAGE   0x00004000
+
+/* The maximum number of blocks to scan for a bbt */
+#define NAND_BBT_SCAN_MAXBLOCKS        4
+
+extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
+extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);
+extern int nand_default_bbt (struct mtd_info *mtd);
+extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt);
+extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
+
 /*
 * Constants for oob configuration
 */
-#define NAND_NOOB_ECCPOS0              0
-#define NAND_NOOB_ECCPOS1              1
-#define NAND_NOOB_ECCPOS2              2
-#define NAND_NOOB_ECCPOS3              3
-#define NAND_NOOB_ECCPOS4              6
-#define NAND_NOOB_ECCPOS5              7
-#define NAND_NOOB_BADBPOS              -1
-#define NAND_NOOB_ECCVPOS              -1
-
-#define NAND_JFFS2_OOB_ECCPOS0         0
-#define NAND_JFFS2_OOB_ECCPOS1         1
-#define NAND_JFFS2_OOB_ECCPOS2         2
-#define NAND_JFFS2_OOB_ECCPOS3         3
-#define NAND_JFFS2_OOB_ECCPOS4         6
-#define NAND_JFFS2_OOB_ECCPOS5         7
-#define NAND_JFFS2_OOB_BADBPOS         5
-#define NAND_JFFS2_OOB_ECCVPOS         4
-
-#define NAND_JFFS2_OOB8_FSDAPOS                6
-#define NAND_JFFS2_OOB16_FSDAPOS       8
-#define NAND_JFFS2_OOB8_FSDALEN                2
-#define NAND_JFFS2_OOB16_FSDALEN       8
-
-unsigned long nand_probe(unsigned long physadr);
+#define NAND_SMALL_BADBLOCK_POS                5
+#define NAND_LARGE_BADBLOCK_POS                0
 
 #endif /* __LINUX_MTD_NAND_H */

diff --git a/include/linux/mtd/nand_ecc.h b/include/linux/mtd/nand_ecc.h
new file mode 100644 (file)
index 0000000..12c5bc3
--- /dev/null
+++ b/include/linux/mtd/nand_ecc.h
@@ -0,0 +1,30 @@
+/*
+ *  drivers/mtd/nand_ecc.h
+ *
+ *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
+ *
+ * $Id: nand_ecc.h,v 1.4 2004/06/17 02:35:02 dbrown Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file is the header for the ECC algorithm.
+ */
+
+#ifndef __MTD_NAND_ECC_H__
+#define __MTD_NAND_ECC_H__
+
+struct mtd_info;
+
+/*
+ * Calculate 3 byte ECC code for 256 byte block
+ */
+int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
+
+/*
+ * Detect and correct a 1 bit error for 256 byte block
+ */
+int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
+
+#endif /* __MTD_NAND_ECC_H__ */

diff --git a/include/linux/mtd/nand_ids.h b/include/linux/mtd/nand_ids.h
index a3d0363a2a52de9b2bc0d49d59b6d5b5cb0b41da..d9eb9118280753ad6b93d3c6740f163b30665119 100644 (file)
--- a/include/linux/mtd/nand_ids.h
+++ b/include/linux/mtd/nand_ids.h
@@ -28,6 +28,10 @@
 #ifndef __LINUX_MTD_NAND_IDS_H
 #define __LINUX_MTD_NAND_IDS_H
 
+#ifndef CFG_NAND_LEGACY
+#error This module is for the legacy NAND support
+#endif
+
 static struct nand_flash_dev nand_flash_ids[] = {
        {"Toshiba TC5816BDC",     NAND_MFR_TOSHIBA, 0x64, 21, 1, 2, 0x1000, 0},
        {"Toshiba TC5832DC",      NAND_MFR_TOSHIBA, 0x6b, 22, 0, 2, 0x2000, 0},
@@ -49,6 +53,7 @@ static struct nand_flash_dev nand_flash_ids[] = {
        {"Samsung KM29W16000",    NAND_MFR_SAMSUNG, 0xea, 21, 1, 2, 0x1000, 0},
        {"Samsung K9F5616Q0C",    NAND_MFR_SAMSUNG, 0x45, 25, 0, 2, 0x4000, 1},
        {"Samsung K9K1216Q0C",    NAND_MFR_SAMSUNG, 0x46, 26, 0, 3, 0x4000, 1},
+       {"Samsung K9F1G08U0M",    NAND_MFR_SAMSUNG, 0xf1, 27, 0, 2, 0, 0},
        {NULL,}
 };
 

diff --git a/include/linux/mtd/nand_legacy.h b/include/linux/mtd/nand_legacy.h
new file mode 100644 (file)
index 0000000..a8769e7
--- /dev/null
+++ b/include/linux/mtd/nand_legacy.h
@@ -0,0 +1,203 @@
+/*
+ *  linux/include/linux/mtd/nand.h
+ *
+ *  Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
+ *                     Steven J. Hill <sjhill@cotw.com>
+ *                    Thomas Gleixner <gleixner@autronix.de>
+ *
+ * $Id: nand.h,v 1.7 2003/07/24 23:30:46 a0384864 Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Info:
+ *   Contains standard defines and IDs for NAND flash devices
+ *
+ *  Changelog:
+ *   01-31-2000 DMW     Created
+ *   09-18-2000 SJH     Moved structure out of the Disk-On-Chip drivers
+ *                     so it can be used by other NAND flash device
+ *                     drivers. I also changed the copyright since none
+ *                     of the original contents of this file are specific
+ *                     to DoC devices. David can whack me with a baseball
+ *                     bat later if I did something naughty.
+ *   10-11-2000 SJH     Added private NAND flash structure for driver
+ *   10-24-2000 SJH     Added prototype for 'nand_scan' function
+ *   10-29-2001 TG     changed nand_chip structure to support
+ *                     hardwarespecific function for accessing control lines
+ *   02-21-2002 TG     added support for different read/write adress and
+ *                     ready/busy line access function
+ *   02-26-2002 TG     added chip_delay to nand_chip structure to optimize
+ *                     command delay times for different chips
+ *   04-28-2002 TG     OOB config defines moved from nand.c to avoid duplicate
+ *                     defines in jffs2/wbuf.c
+ */
+#ifndef __LINUX_MTD_NAND_LEGACY_H
+#define __LINUX_MTD_NAND_LEGACY_H
+
+#ifndef CFG_NAND_LEGACY
+#error This module is for the legacy NAND support
+#endif
+
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0         0
+#define NAND_CMD_READ1         1
+#define NAND_CMD_PAGEPROG      0x10
+#define NAND_CMD_READOOB       0x50
+#define NAND_CMD_ERASE1                0x60
+#define NAND_CMD_STATUS                0x70
+#define NAND_CMD_SEQIN         0x80
+#define NAND_CMD_READID                0x90
+#define NAND_CMD_ERASE2                0xd0
+#define NAND_CMD_RESET         0xff
+
+/*
+ * Enumeration for NAND flash chip state
+ */
+typedef enum {
+       FL_READY,
+       FL_READING,
+       FL_WRITING,
+       FL_ERASING,
+       FL_SYNCING
+} nand_state_t;
+
+
+/*
+ * NAND Private Flash Chip Data
+ *
+ * Structure overview:
+ *
+ *  IO_ADDR - address to access the 8 I/O lines of the flash device
+ *
+ *  hwcontrol - hardwarespecific function for accesing control-lines
+ *
+ *  dev_ready - hardwarespecific function for accesing device ready/busy line
+ *
+ *  chip_lock - spinlock used to protect access to this structure
+ *
+ *  wq - wait queue to sleep on if a NAND operation is in progress
+ *
+ *  state - give the current state of the NAND device
+ *
+ *  page_shift - number of address bits in a page (column address bits)
+ *
+ *  data_buf - data buffer passed to/from MTD user modules
+ *
+ *  data_cache - data cache for redundant page access and shadow for
+ *              ECC failure
+ *
+ *  ecc_code_buf - used only for holding calculated or read ECCs for
+ *                 a page read or written when ECC is in use
+ *
+ *  reserved - padding to make structure fall on word boundary if
+ *             when ECC is in use
+ */
+struct Nand {
+       char floor, chip;
+       unsigned long curadr;
+       unsigned char curmode;
+       /* Also some erase/write/pipeline info when we get that far */
+};
+
+struct nand_chip {
+       int             page_shift;
+       u_char          *data_buf;
+       u_char          *data_cache;
+       int             cache_page;
+       u_char          ecc_code_buf[6];
+       u_char          reserved[2];
+       char ChipID; /* Type of DiskOnChip */
+       struct Nand *chips;
+       int chipshift;
+       char* chips_name;
+       unsigned long erasesize;
+       unsigned long mfr; /* Flash IDs - only one type of flash per device */
+       unsigned long id;
+       char* name;
+       int numchips;
+       char page256;
+       char pageadrlen;
+       unsigned long IO_ADDR;  /* address to access the 8 I/O lines to the flash device */
+       unsigned long totlen;
+       uint oobblock;  /* Size of OOB blocks (e.g. 512) */
+       uint oobsize;   /* Amount of OOB data per block (e.g. 16) */
+       uint eccsize;
+       int bus16;
+};
+
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA       0x98
+#define NAND_MFR_SAMSUNG       0xec
+
+/*
+ * NAND Flash Device ID Structure
+ *
+ * Structure overview:
+ *
+ *  name - Complete name of device
+ *
+ *  manufacture_id - manufacturer ID code of device.
+ *
+ *  model_id - model ID code of device.
+ *
+ *  chipshift - total number of address bits for the device which
+ *              is used to calculate address offsets and the total
+ *              number of bytes the device is capable of.
+ *
+ *  page256 - denotes if flash device has 256 byte pages or not.
+ *
+ *  pageadrlen - number of bytes minus one needed to hold the
+ *               complete address into the flash array. Keep in
+ *               mind that when a read or write is done to a
+ *               specific address, the address is input serially
+ *               8 bits at a time. This structure member is used
+ *               by the read/write routines as a loop index for
+ *               shifting the address out 8 bits at a time.
+ *
+ *  erasesize - size of an erase block in the flash device.
+ */
+struct nand_flash_dev {
+       char * name;
+       int manufacture_id;
+       int model_id;
+       int chipshift;
+       char page256;
+       char pageadrlen;
+       unsigned long erasesize;
+       int bus16;
+};
+
+/*
+* Constants for oob configuration
+*/
+#define NAND_NOOB_ECCPOS0              0
+#define NAND_NOOB_ECCPOS1              1
+#define NAND_NOOB_ECCPOS2              2
+#define NAND_NOOB_ECCPOS3              3
+#define NAND_NOOB_ECCPOS4              6
+#define NAND_NOOB_ECCPOS5              7
+#define NAND_NOOB_BADBPOS              -1
+#define NAND_NOOB_ECCVPOS              -1
+
+#define NAND_JFFS2_OOB_ECCPOS0         0
+#define NAND_JFFS2_OOB_ECCPOS1         1
+#define NAND_JFFS2_OOB_ECCPOS2         2
+#define NAND_JFFS2_OOB_ECCPOS3         3
+#define NAND_JFFS2_OOB_ECCPOS4         6
+#define NAND_JFFS2_OOB_ECCPOS5         7
+#define NAND_JFFS2_OOB_BADBPOS         5
+#define NAND_JFFS2_OOB_ECCVPOS         4
+
+#define NAND_JFFS2_OOB8_FSDAPOS                6
+#define NAND_JFFS2_OOB16_FSDAPOS       8
+#define NAND_JFFS2_OOB8_FSDALEN                2
+#define NAND_JFFS2_OOB16_FSDALEN       8
+
+unsigned long nand_probe(unsigned long physadr);
+#endif /* __LINUX_MTD_NAND_LEGACY_H */

diff --git a/include/linux/stat.h b/include/linux/stat.h
index 2f7a3b36acf08862dc486fd1364bf7e0cc91c3cf..f9422cb1fafcf2d2bb24e2b36ece2fe39335bda2 100644 (file)
--- a/include/linux/stat.h
+++ b/include/linux/stat.h
@@ -67,7 +67,7 @@ struct stat {
 
 #endif /* __PPC__ */
 
-#if defined (__ARM__) || defined (__I386__) || defined (__M68K__)
+#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__)
 
 struct stat {
        unsigned short st_dev;

diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index f33d8585522388826b1bba794adbeb05a5ed4f90..50a6ac1e98d5f1aabdb97bc0c31d0f50bebf33b1 100644 (file)
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -131,6 +131,7 @@
 #if defined(CONFIG_MGT5100)
 #define MPC5XXX_SDRAM_XLBSEL   (MPC5XXX_SDRAM + 0x0010)
 #endif
+#define MPC5XXX_SDRAM_SDELAY   (MPC5XXX_SDRAM + 0x0090)
 
 /* Clock Distribution Module */
 #define MPC5XXX_CDM_JTAGID     (MPC5XXX_CDM + 0x0000)

diff --git a/include/mpc85xx.h b/include/mpc85xx.h
index 60b6c61fb0bbd81409d377199a13c1c578892db3..a4d99b2a165074d1f654fa32c9dff63a891ddd3b 100644 (file)
--- a/include/mpc85xx.h
+++ b/include/mpc85xx.h
@@ -25,4 +25,39 @@
 #define SCCR_DFBRG10    0x00000002      /* BRGCLK division by 64 */
 #define SCCR_DFBRG11    0x00000003      /* BRGCLK division by 256 */
 
+/*
+ * Local Bus Controller - memory controller registers
+ */
+#define BRx_V          0x00000001      /* Bank Valid                   */
+#define BRx_MS_GPCM    0x00000000      /* G.P.C.M. Machine Select      */
+#define BRx_MS_SDRAM   0x00000000      /* SDRAM Machine Select         */
+#define BRx_MS_UPMA    0x00000080      /* U.P.M.A Machine Select       */
+#define BRx_MS_UPMB    0x000000a0      /* U.P.M.B Machine Select       */
+#define BRx_MS_UPMC    0x000000c0      /* U.P.M.C Machine Select       */
+#define BRx_PS_8       0x00000800      /*  8 bit port size             */
+#define BRx_PS_32      0x00001800      /* 32 bit port size             */
+#define BRx_BA_MSK     0xffff8000      /* Base Address Mask            */
+
+#define ORxG_EAD       0x00000001      /* External addr latch delay    */
+#define ORxG_EHTR      0x00000002      /* Extended hold time on read   */
+#define ORxG_TRLX      0x00000004      /* Timing relaxed               */
+#define ORxG_SETA      0x00000008      /* External address termination */
+#define ORxG_SCY_10_CLK        0x000000a0      /* 10 clock cycles wait states  */
+#define ORxG_SCY_15_CLK        0x000000f0      /* 15 clock cycles wait states  */
+#define ORxG_XACS      0x00000100      /* Extra addr to CS setup       */
+#define ORxG_ACS_DIV2  0x00000600      /* CS is output 1/2 a clock later*/
+#define ORxG_CSNT      0x00000800      /* Chip Select Negation Time    */
+
+#define ORxU_BI                0x00000100      /* Burst Inhibit                */
+#define ORxU_AM_MSK    0xffff8000      /* Address Mask Mask            */
+
+#define MxMR_OP_NORM   0x00000000      /* Normal Operation             */
+#define MxMR_DSx_2_CYCL 0x00400000     /* 2 cycle Disable Period       */
+#define MxMR_OP_WARR   0x10000000      /* Write to Array               */
+#define MxMR_BSEL      0x80000000      /* Bus Select                   */
+
+/* helpers to convert values into an OR address mask (GPCM mode) */
+#define P2SZ_TO_AM(s)  ((~((s) - 1)) & 0xffff8000)     /* must be pow of 2 */
+#define MEG_TO_AM(m)   P2SZ_TO_AM((m) << 20)
+
 #endif /* __MPC85xx_H__ */

diff --git a/include/nand.h b/include/nand.h
new file mode 100644 (file)
index 0000000..905115b
--- /dev/null
+++ b/include/nand.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2005
+ * 2N Telekomunikace, a.s. <www.2n.cz>
+ * Ladislav Michl <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _NAND_H_
+#define _NAND_H_
+
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+
+typedef struct mtd_info nand_info_t;
+
+extern int nand_curr_device;
+extern nand_info_t nand_info[];
+
+static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
+{
+       return info->read(info, ofs, *len, (size_t *)len, buf);
+}
+
+static inline int nand_write(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
+{
+       return info->write(info, ofs, *len, (size_t *)len, buf);
+}
+
+static inline int nand_block_isbad(nand_info_t *info, ulong ofs)
+{
+       return info->block_isbad(info, ofs);
+}
+
+static inline int nand_erase(nand_info_t *info, ulong off, ulong size)
+{
+       struct erase_info instr;
+
+       instr.mtd = info;
+       instr.addr = off;
+       instr.len = size;
+       instr.callback = 0;
+
+       return info->erase(info, &instr);
+}
+
+#endif

diff --git a/include/ns16550.h b/include/ns16550.h
index e17a11edca614a4e513668ddacf2d1c10073912c..d987a8b7edb21ab66142f35c70e8f07a250b6d0e 100644 (file)
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -45,15 +45,15 @@ struct NS16550 {
 } __attribute__ ((packed));
 #elif (CFG_NS16550_REG_SIZE == 4)
 struct NS16550 {
-       unsigned long rbr;              /* 0 */
-       unsigned long ier;              /* 1 */
-       unsigned long fcr;              /* 2 */
-       unsigned long lcr;              /* 3 */
-       unsigned long mcr;              /* 4 */
-       unsigned long lsr;              /* 5 */
-       unsigned long msr;              /* 6 */
-       unsigned long scr;              /* 7 */
-} __attribute__ ((packed));
+       unsigned long rbr;              /* 0 r  */
+       unsigned long ier;              /* 1 rw */
+       unsigned long fcr;              /* 2 w  */
+       unsigned long lcr;              /* 3 rw */
+       unsigned long mcr;              /* 4 rw */
+       unsigned long lsr;              /* 5 r  */
+       unsigned long msr;              /* 6 r  */
+       unsigned long scr;              /* 7 rw */
+}; /* No need to pack an already aligned struct */
 #elif (CFG_NS16550_REG_SIZE == -4)
 struct NS16550 {
        unsigned char rbr;              /* 0 */
@@ -102,7 +102,7 @@ typedef volatile struct NS16550 *NS16550_t;
 #define MCR_DMA_EN      0x04
 #define MCR_TX_DFR      0x08
 
-#define LCR_WLS_MSK    0x03            /* character length slect mask */
+#define LCR_WLS_MSK    0x03            /* character length select mask */
 #define LCR_WLS_5      0x00            /* 5 bit character length */
 #define LCR_WLS_6      0x01            /* 6 bit character length */
 #define LCR_WLS_7      0x02            /* 7 bit character length */

diff --git a/include/pci.h b/include/pci.h
index 8f19997559228d61b25dd84a883fd78fba635cfb..0fc00e42769fd130938b4c2079fd59b4297431c6 100644 (file)
--- a/include/pci.h
+++ b/include/pci.h
@@ -309,6 +309,7 @@ struct pci_region {
 #define PCI_REGION_MEM         0x00000000      /* PCI memory space */
 #define PCI_REGION_IO          0x00000001      /* PCI IO space */
 #define PCI_REGION_TYPE                0x00000001
+#define PCI_REGION_PREFETCH    0x00000008      /* prefetchable PCI memory */
 
 #define PCI_REGION_MEMORY      0x00000100      /* System memory */
 #define PCI_REGION_RO          0x00000200      /* Read-only memory */
@@ -351,8 +352,8 @@ struct pci_config_table {
        unsigned long priv[3];
 };
 
-extern void pci_cfgfunc_nothing(struct pci_controller* hose, pci_dev_t dev,
-                               struct pci_config_table *);
+extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
+                                  struct pci_config_table *);
 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
                                      struct pci_config_table *);
 
@@ -386,7 +387,7 @@ struct pci_controller {
        int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
 
        /* Used by auto config */
-       struct pci_region *pci_mem, *pci_io;
+       struct pci_region *pci_mem, *pci_io, *pci_prefetch;
 
        /* Used by ppc405 autoconfig*/
        struct pci_region *pci_fb;
@@ -472,6 +473,7 @@ extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, un
 extern void pciauto_setup_device(struct pci_controller *hose,
                                 pci_dev_t dev, int bars_num,
                                 struct pci_region *mem,
+                                struct pci_region *prefetch,
                                 struct pci_region *io);
 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 

diff --git a/include/pci_ids.h b/include/pci_ids.h
index 7dec378ad4be382410710b8bb16055b9d1340781..8cc3ec0a23537ceb79af94876ae80b633036c52d 100644 (file)
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -510,6 +510,7 @@
 #define PCI_DEVICE_ID_CT_65554         0x00e4
 #define PCI_DEVICE_ID_CT_65555         0x00e5
 #define PCI_DEVICE_ID_CT_69000         0x00c0
+#define PCI_DEVICE_ID_CT_69030         0x0c30
 
 #define PCI_VENDOR_ID_MIRO             0x1031
 #define PCI_DEVICE_ID_MIRO_36050       0x5601

diff --git a/include/spd_sdram.h b/include/spd_sdram.h
index 4e754ec9e335af9383af02a32f7067c78a2480d7..a2be96c1aa1e993627dbf126a39b7348460c95f6 100644 (file)
--- a/include/spd_sdram.h
+++ b/include/spd_sdram.h
@@ -1,6 +1,6 @@
 #ifndef _SPD_SDRAM_H_
 #define _SPD_SDRAM_H_
 
-long int spd_sdram(int(read_spd)(uint addr));
+long int spd_sdram(void);
 
 #endif

diff --git a/include/version.h b/include/version.h
index 4f8b498cf37bf0b59f91c2e06e84d4570e85661e..b56d2e9900b8309c66d3f265ab73b03ebd46137e 100644 (file)
--- a/include/version.h
+++ b/include/version.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2000-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -24,6 +24,6 @@
 #ifndef        __VERSION_H__
 #define        __VERSION_H__
 
-#define        U_BOOT_VERSION  "U-Boot 1.1.4"
+#include "version_autogenerated.h"
 
 #endif /* __VERSION_H__ */

diff --git a/include/xyzModem.h b/include/xyzModem.h
new file mode 100644 (file)
index 0000000..4ec10b5
--- /dev/null
+++ b/include/xyzModem.h
@@ -0,0 +1,114 @@
+/*
+ *==========================================================================
+ *
+ *      xyzModem.h
+ *
+ *      RedBoot stream handler for xyzModem protocol
+ *
+ *==========================================================================
+ *####ECOSGPLCOPYRIGHTBEGIN####
+ * -------------------------------------------
+ * This file is part of eCos, the Embedded Configurable Operating System.
+ * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+ * Copyright (C) 2002 Gary Thomas
+ *
+ * eCos is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 or (at your option) any later version.
+ *
+ * eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+ * WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with eCos; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * As a special exception, if other files instantiate templates or use macros
+ * or inline functions from this file, or you compile this file and link it
+ * with other works to produce a work based on this file, this file does not
+ * by itself cause the resulting work to be covered by the GNU General Public
+ * License. However the source code for this file must still be made available
+ * in accordance with section (3) of the GNU General Public License.
+ *
+ * This exception does not invalidate any other reasons why a work based on
+ * this file might be covered by the GNU General Public License.
+ *
+ * Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+ * at http: *sources.redhat.com/ecos/ecos-license/
+ * -------------------------------------------
+ *####ECOSGPLCOPYRIGHTEND####
+ *==========================================================================
+ *#####DESCRIPTIONBEGIN####
+ *
+ * Author(s):    gthomas
+ * Contributors: gthomas
+ * Date:         2000-07-14
+ * Purpose:
+ * Description:
+ *
+ * This code is part of RedBoot (tm).
+ *
+ *####DESCRIPTIONEND####
+ *
+ *==========================================================================
+ */
+
+#ifndef _XYZMODEM_H_
+#define _XYZMODEM_H_
+
+#define xyzModem_xmodem 1
+#define xyzModem_ymodem 2
+/* Don't define this until the protocol support is in place */
+/*#define xyzModem_zmodem 3 */
+
+#define xyzModem_access   -1
+#define xyzModem_noZmodem -2
+#define xyzModem_timeout  -3
+#define xyzModem_eof      -4
+#define xyzModem_cancel   -5
+#define xyzModem_frame    -6
+#define xyzModem_cksum    -7
+#define xyzModem_sequence -8
+
+#define xyzModem_close 1
+#define xyzModem_abort 2
+
+
+#ifdef REDBOOT
+extern getc_io_funcs_t xyzModem_io;
+#else
+#define CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT
+#define CYGACC_CALL_IF_SET_CONSOLE_COMM(x)
+
+#define diag_vprintf vprintf
+#define diag_printf printf
+#define diag_vsprintf vsprintf
+
+#define CYGACC_CALL_IF_DELAY_US(x) udelay(x)
+
+typedef struct {
+    char *filename;
+    int   mode;
+    int   chan;
+#ifdef CYGPKG_REDBOOT_NETWORKING
+    struct sockaddr_in *server;
+#endif
+} connection_info_t;
+
+typedef unsigned int bool;
+
+#define false 0
+#define true 1
+
+#endif
+
+
+int   xyzModem_stream_open(connection_info_t *info, int *err);
+void  xyzModem_stream_close(int *err);
+void  xyzModem_stream_terminate(bool method, int (*getc)(void));
+int   xyzModem_stream_read(char *buf, int size, int *err);
+char *xyzModem_error(int err);
+
+#endif /* _XYZMODEM_H_ */

diff --git a/lib_arm/armlinux.c b/lib_arm/armlinux.c
index ca630b377e7093c9f195b4896bcd8b23429a343d..56b7fca83331ec84e68c2af5a4868ebe7a539cd7 100644 (file)
--- a/lib_arm/armlinux.c
+++ b/lib_arm/armlinux.c
@@ -30,6 +30,8 @@
 #include <dataflash.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*cmd_boot.c*/
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
@@ -77,8 +79,6 @@ extern image_header_t header; /* from cmd_bootm.c */
 void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
                     ulong addr, ulong *len_ptr, int verify)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong len = 0, checksum;
        ulong initrd_start, initrd_end;
        ulong data;
@@ -124,7 +124,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
                checksum = ntohl (hdr->ih_hcrc);
                hdr->ih_hcrc = 0;
 
-               if (crc32 (0, (char *) data, len) != checksum) {
+               if (crc32 (0, (unsigned char *) data, len) != checksum) {
                        printf ("Bad Header Checksum\n");
                        SHOW_BOOT_PROGRESS (-11);
                        do_reset (cmdtp, flag, argc, argv);
@@ -148,7 +148,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
                        ulong csum = 0;
 
                        printf ("   Verifying Checksum ... ");
-                       csum = crc32 (0, (char *) data, len);
+                       csum = crc32 (0, (unsigned char *) data, len);
                        if (csum != ntohl (hdr->ih_dcrc)) {
                                printf ("Bad Data CRC\n");
                                SHOW_BOOT_PROGRESS (-12);

diff --git a/lib_arm/board.c b/lib_arm/board.c
index fa3c92e094e26343ea778079e62c7f6dc255138f..1028b046d8463842549711bac0ba782b97af3473 100644 (file)
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2002
+ * (C) Copyright 2002-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * (C) Copyright 2002
@@ -25,6 +25,19 @@
  * MA 02111-1307 USA
  */
 
+/*
+ * To match the U-Boot user interface on ARM platforms to the U-Boot
+ * standard (as on PPC platforms), some messages with debug character
+ * are removed from the default U-Boot build.
+ *
+ * Define DEBUG here if you want additional info as shown below
+ * printed upon startup:
+ *
+ * U-Boot code: 00F00000 -> 00F3C774  BSS: -> 00FC3274
+ * IRQ Stack: 00ebff7c
+ * FIQ Stack: 00ebef7c
+ */
+
 #include <common.h>
 #include <command.h>
 #include <malloc.h>
@@ -39,6 +52,8 @@
 #include "../drivers/lan91c96.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 void nand_init (void);
 #endif
@@ -106,9 +121,7 @@ void *sbrk (ptrdiff_t increment)
 
 static int init_baudrate (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
-       uchar tmp[64];  /* long enough for environment variables */
+       char tmp[64];   /* long enough for environment variables */
        int i = getenv_r ("baudrate", tmp, sizeof (tmp));
        gd->bd->bi_baudrate = gd->baudrate = (i > 0)
                        ? (int) simple_strtoul (tmp, NULL, 10)
@@ -120,14 +133,14 @@ static int init_baudrate (void)
 static int display_banner (void)
 {
        printf ("\n\n%s\n\n", version_string);
-       printf ("U-Boot code: %08lX -> %08lX  BSS: -> %08lX\n",
-               _armboot_start, _bss_start, _bss_end);
+       debug ("U-Boot code: %08lX -> %08lX  BSS: -> %08lX\n",
+              _armboot_start, _bss_start, _bss_end);
 #ifdef CONFIG_MODEM_SUPPORT
-       puts ("Modem Support enabled\n");
+       debug ("Modem Support enabled\n");
 #endif
 #ifdef CONFIG_USE_IRQ
-       printf ("IRQ Stack: %08lx\n", IRQ_STACK_START);
-       printf ("FIQ Stack: %08lx\n", FIQ_STACK_START);
+       debug ("IRQ Stack: %08lx\n", IRQ_STACK_START);
+       debug ("FIQ Stack: %08lx\n", FIQ_STACK_START);
 #endif
 
        return (0);
@@ -142,24 +155,35 @@ static int display_banner (void)
  */
 static int display_dram_config (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int i;
 
+#ifdef DEBUG
        puts ("RAM Configuration:\n");
 
        for(i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
                printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
                print_size (gd->bd->bi_dram[i].size, "\n");
        }
+#else
+       ulong size = 0;
+
+       for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+               size += gd->bd->bi_dram[i].size;
+       }
+       puts("DRAM:  ");
+       print_size(size, "\n");
+#endif
 
        return (0);
 }
 
+#ifndef CFG_NO_FLASH
 static void display_flash_config (ulong size)
 {
        puts ("Flash: ");
        print_size (size, "\n");
 }
+#endif /* CFG_NO_FLASH */
 
 
 /*
@@ -187,6 +211,8 @@ static void display_flash_config (ulong size)
  */
 typedef int (init_fnc_t) (void);
 
+int print_cpuinfo (void); /* test-only */
+
 init_fnc_t *init_sequence[] = {
        cpu_init,               /* basic cpu dependent setup */
        board_init,             /* basic board dependent setup */
@@ -196,21 +222,24 @@ init_fnc_t *init_sequence[] = {
        serial_init,            /* serial communications setup */
        console_init_f,         /* stage 1 init of console */
        display_banner,         /* say that we are here */
+#if defined(CONFIG_DISPLAY_CPUINFO)
+       print_cpuinfo,          /* display cpu info (and speed) */
+#endif
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+       checkboard,             /* display board info */
+#endif
        dram_init,              /* configure available RAM banks */
        display_dram_config,
-#if defined(CONFIG_VCMA9) || defined (CONFIG_CMC_PU2)
-       checkboard,
-#endif
        NULL,
 };
 
 void start_armboot (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
-       ulong size;
        init_fnc_t **init_fnc_ptr;
        char *s;
+#ifndef CFG_NO_FLASH
+       ulong size;
+#endif
 #if defined(CONFIG_VFD) || defined(CONFIG_LCD)
        unsigned long addr;
 #endif
@@ -232,9 +261,11 @@ void start_armboot (void)
                }
        }
 
+#ifndef CFG_NO_FLASH
        /* configure available FLASH banks */
        size = flash_init ();
        display_flash_config (size);
+#endif /* CFG_NO_FLASH */
 
 #ifdef CONFIG_VFD
 #      ifndef PAGE_SIZE
@@ -291,7 +322,7 @@ void start_armboot (void)
                int i;
                ulong reg;
                char *s, *e;
-               uchar tmp[64];
+               char tmp[64];
 
                i = getenv_r ("ethaddr", tmp, sizeof (tmp));
                s = (i > 0) ? tmp : NULL;
@@ -301,6 +332,17 @@ void start_armboot (void)
                        if (s)
                                s = (*e) ? e + 1 : e;
                }
+
+#ifdef CONFIG_HAS_ETH1
+               i = getenv_r ("eth1addr", tmp, sizeof (tmp));
+               s = (i > 0) ? tmp : NULL;
+
+               for (reg = 0; reg < 6; ++reg) {
+                       gd->bd->bi_enet1addr[reg] = s ? simple_strtoul (s, &e, 16) : 0;
+                       if (s)
+                               s = (*e) ? e + 1 : e;
+               }
+#endif
        }
 
        devices_init ();        /* get the devices list going. */
@@ -366,6 +408,8 @@ void hang (void)
 }
 
 #ifdef CONFIG_MODEM_SUPPORT
+static inline void mdm_readline(char *buf, int bufsiz);
+
 /* called from main loop (common/main.c) */
 extern void  dbg(const char *fmt, ...);
 int mdm_init (void)
@@ -374,7 +418,6 @@ int mdm_init (void)
        char *init_str;
        int i;
        extern char console_buffer[];
-       static inline void mdm_readline(char *buf, int bufsiz);
        extern void enable_putc(void);
        extern int hwflow_onoff(int);
 

diff --git a/lib_blackfin/Makefile b/lib_blackfin/Makefile
new file mode 100644 (file)
index 0000000..bc280d0
--- /dev/null
+++ b/lib_blackfin/Makefile
@@ -0,0 +1,47 @@
+#
+# U-boot Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(ARCH).a
+
+AOBJS  =
+
+COBJS  = board.o bf533_linux.o bf533_string.o cache.o muldi3.o
+OBJS   = $(AOBJS) $(COBJS)
+
+$(LIB):        .depend $(OBJS)
+       $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:       Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

diff --git a/lib_blackfin/bf533_linux.c b/lib_blackfin/bf533_linux.c
new file mode 100644 (file)
index 0000000..88b4da2
--- /dev/null
+++ b/lib_blackfin/bf533_linux.c
@@ -0,0 +1,91 @@
+/*
+ * U-boot - bf533_linux.c
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Dummy functions, currently not in Use */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <zlib.h>
+#include <asm/byteorder.h>
+
+#define        LINUX_MAX_ENVS          256
+#define        LINUX_MAX_ARGS          256
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+#include <status_led.h>
+#define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
+#else
+#define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+#define CMD_LINE_ADDR 0xFF900000  /* L1 scratchpad */
+
+#ifdef SHARED_RESOURCES
+       extern void swap_to(int device_id);
+#endif
+
+static char *make_command_line(void);
+
+extern image_header_t header;
+extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
+void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
+                   ulong addr, ulong * len_ptr, int verify)
+{
+       int (*appl)(char *cmdline);
+       char *cmdline;
+
+#ifdef SHARED_RESOURCES
+       swap_to(FLASH);
+#endif
+
+       appl = (int (*)(char *))ntohl(header.ih_ep);
+       printf("Starting Kernel at = %x\n", appl);
+       cmdline = make_command_line();
+       if(icache_status()){
+               flush_instruction_cache();
+               icache_disable();
+               }
+       if(dcache_status()){
+               flush_data_cache();
+               dcache_disable();
+               }
+       (*appl)(cmdline);
+}
+
+char *make_command_line(void)
+{
+    char *dest = (char *) CMD_LINE_ADDR;
+    char *bootargs;
+
+    if ( (bootargs = getenv("bootargs")) == NULL )
+       return NULL;
+
+    strncpy(dest, bootargs, 0x1000);
+    dest[0xfff] = 0;
+    return dest;
+}

diff --git a/lib_blackfin/bf533_string.c b/lib_blackfin/bf533_string.c
new file mode 100644 (file)
index 0000000..c8b1a3a
--- /dev/null
+++ b/lib_blackfin/bf533_string.c
@@ -0,0 +1,185 @@
+/*
+ * U-boot - bf533_string.c Contains library routines.
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/cpu/defBF533.h>
+
+void *dma_memcpy(void *,const void *,size_t);
+
+char *strcpy(char *dest, const char *src)
+{
+       char *xdest = dest;
+       char temp = 0;
+
+       __asm__ __volatile__
+               ("1:\t%2 = B [%1++] (Z);\n\t"
+               "B [%0++] = %2;\n\t"
+               "CC = %2;\n\t"
+               "if cc jump 1b (bp);\n":"=a"(dest), "=a"(src), "=d"(temp)
+               :"0"(dest), "1"(src), "2"(temp):"memory");
+
+       return xdest;
+}
+
+char *strncpy(char *dest, const char *src, size_t n)
+{
+       char *xdest = dest;
+       char temp = 0;
+
+       if (n == 0)
+               return xdest;
+
+       __asm__ __volatile__
+               ("1:\t%3 = B [%1++] (Z);\n\t"
+               "B [%0++] = %3;\n\t"
+               "CC = %3;\n\t"
+               "if ! cc jump 2f;\n\t"
+               "%2 += -1;\n\t"
+               "CC = %2 == 0;\n\t"
+               "if ! cc jump 1b (bp);\n"
+               "2:\n":"=a"(dest), "=a"(src), "=da"(n), "=d"(temp)
+               :"0"(dest), "1"(src), "2"(n), "3"(temp)
+               :"memory");
+
+       return xdest;
+}
+
+int strcmp(const char *cs, const char *ct)
+{
+       char __res1, __res2;
+
+       __asm__
+               ("1:\t%2 = B[%0++] (Z);\n\t"    /* get *cs */
+               "%3 = B[%1++] (Z);\n\t"         /* get *ct */
+               "CC = %2 == %3;\n\t"            /* compare a byte */
+               "if ! cc jump 2f;\n\t"          /* not equal, break out */
+               "CC = %2;\n\t"                  /* at end of cs? */
+               "if cc jump 1b (bp);\n\t"       /* no, keep going */
+               "jump.s 3f;\n"                  /* strings are equal */
+               "2:\t%2 = %2 - %3;\n"           /* *cs - *ct */
+               "3:\n": "=a"(cs), "=a"(ct), "=d"(__res1),
+               "=d"(__res2)
+               : "0"(cs), "1"(ct));
+
+       return __res1;
+}
+
+int strncmp(const char *cs, const char *ct, size_t count)
+{
+       char __res1, __res2;
+
+       if (!count)
+               return 0;
+
+       __asm__
+               ("1:\t%3 = B[%0++] (Z);\n\t"    /* get *cs */
+               "%4 = B[%1++] (Z);\n\t"         /* get *ct */
+               "CC = %3 == %4;\n\t"            /* compare a byte */
+               "if ! cc jump 3f;\n\t"          /* not equal, break out */
+               "CC = %3;\n\t"                  /* at end of cs? */
+               "if ! cc jump 4f;\n\t"          /* yes, all done */
+               "%2 += -1;\n\t"                 /* no, adjust count */
+               "CC = %2 == 0;\n\t" "if ! cc jump 1b;\n"        /* more to do, keep going */
+               "2:\t%3 = 0;\n\t"               /* strings are equal */
+               "jump.s    4f;\n" "3:\t%3 = %3 - %4;\n" /* *cs - *ct */
+               "4:":   "=a"(cs), "=a"(ct), "=da"(count), "=d"(__res1),
+               "=d"(__res2)
+               : "0"(cs), "1"(ct), "2"(count));
+
+       return __res1;
+}
+
+/*
+ * memcpy - Copy one area of memory to another
+ * @dest: Where to copy to
+ * @src: Where to copy from
+ * @count: The size of the area.
+ *
+ * You should not use this function to access IO space, use memcpy_toio()
+ * or memcpy_fromio() instead.
+ */
+void * memcpy(void * dest,const void *src,size_t count)
+{
+       char *tmp = (char *) dest, *s = (char *) src;
+
+/* Turn off the cache, if destination in the L1 memory */
+       if ( (tmp >= (char *)L1_ISRAM) && (tmp < (char *)L1_ISRAM_END)
+               || (tmp >= (char *)DATA_BANKA_SRAM) && (tmp < DATA_BANKA_SRAM_END)
+           || (tmp >= (char *)DATA_BANKB_SRAM) && (tmp < DATA_BANKB_SRAM_END) ){
+                       if(icache_status()){
+                                       blackfin_icache_flush_range(src, src+count);
+                                       icache_disable();
+                       }
+                       if(dcache_status()){
+                                       blackfin_dcache_flush_range(src, src+count);
+                                       dcache_disable();
+                       }
+                       dma_memcpy(dest,src,count);
+       }else{
+               while(count--)
+                       *tmp++ = *s++;
+       }
+       return dest;
+}
+
+void *dma_memcpy(void * dest,const void *src,size_t count)
+{
+
+               *pMDMA_D0_IRQ_STATUS = DMA_DONE | DMA_ERR;
+
+               /* Copy sram functions from sdram to sram */
+               /* Setup destination start address */
+               *pMDMA_D0_START_ADDR = (volatile void **)dest;
+               /* Setup destination xcount */
+               *pMDMA_D0_X_COUNT = count ;
+               /* Setup destination xmodify */
+               *pMDMA_D0_X_MODIFY = 1;
+
+               /* Setup Source start address */
+               *pMDMA_S0_START_ADDR = (volatile void **)src;
+               /* Setup Source xcount */
+               *pMDMA_S0_X_COUNT = count;
+               /* Setup Source xmodify */
+               *pMDMA_S0_X_MODIFY = 1;
+
+               /* Enable source DMA */
+               *pMDMA_S0_CONFIG = (DMAEN);
+               asm("ssync;");
+
+               *pMDMA_D0_CONFIG = ( WNR | DMAEN);
+
+               while(*pMDMA_D0_IRQ_STATUS & DMA_RUN){
+                       *pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR);
+               }
+               *pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR);
+
+               dest += count;
+               src  += count;
+               return dest;
+}

diff --git a/lib_blackfin/blackfin_board.h b/lib_blackfin/blackfin_board.h
new file mode 100644 (file)
index 0000000..31c16a2
--- /dev/null
+++ b/lib_blackfin/blackfin_board.h
@@ -0,0 +1,62 @@
+/*
+ * U-boot - blackfin_board.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BLACKFIN_BOARD_H__
+#define __BLACKFIN_BOARD_H__
+
+extern void timer_init(void);
+extern void init_IRQ(void);
+extern void rtc_init(void);
+
+extern ulong uboot_end_data;
+extern ulong uboot_end;
+
+ulong monitor_flash_len;
+
+
+#define VERSION_STRING_SIZE  150 /* including 40 bytes buffer to change any string */
+#define VERSION_STRING_FORMAT "%s (%s - %s)\n"
+#define VERSION_STRING         U_BOOT_VERSION, __DATE__, __TIME__
+
+char version_string[VERSION_STRING_SIZE];
+
+int *g_addr;
+static ulong mem_malloc_start;
+static ulong mem_malloc_end;
+static ulong mem_malloc_brk;
+extern char _sram_in_sdram_start[];
+extern char _sram_inst_size[];
+#ifdef DEBUG
+static void display_global_data(void);
+#endif
+
+/* definitions used to check the SMC card availability */
+#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
+#define UPPER_BYTE_MASK        0xFF00
+#define SMC_IDENT      0x3300
+
+#endif

diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c
new file mode 100644 (file)
index 0000000..d9dc2b6
--- /dev/null
+++ b/lib_blackfin/board.c
@@ -0,0 +1,279 @@
+/*
+ * U-boot - board.c First C file to be called contains init routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <devices.h>
+#include <version.h>
+#include <net.h>
+#include <environment.h>
+#include "blackfin_board.h"
+#include "../drivers/smc91111.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[];
+
+
+static void mem_malloc_init(void)
+{
+       mem_malloc_start = CFG_MALLOC_BASE;
+       mem_malloc_end = (CFG_MALLOC_BASE + CFG_MALLOC_LEN);
+       mem_malloc_brk = mem_malloc_start;
+       memset((void *) mem_malloc_start, 0,
+       mem_malloc_end - mem_malloc_start);
+}
+
+void *sbrk(ptrdiff_t increment)
+{
+       ulong old = mem_malloc_brk;
+       ulong new = old + increment;
+
+       if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
+               return (NULL);
+       }
+       mem_malloc_brk = new;
+
+       return ((void *) old);
+}
+
+static int display_banner(void)
+{
+       sprintf(version_string, VERSION_STRING_FORMAT, VERSION_STRING);
+       printf("%s\n", version_string);
+       return (0);
+}
+
+static void display_flash_config(ulong size)
+{
+       puts("FLASH:  ");
+       print_size(size, "\n");
+       return;
+}
+
+static int init_baudrate(void)
+{
+       uchar tmp[64];
+       int i = getenv_r("baudrate", tmp, sizeof(tmp));
+       gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+               ? (int) simple_strtoul(tmp, NULL, 10)
+               : CONFIG_BAUDRATE;
+       return (0);
+}
+
+#ifdef DEBUG
+static void display_global_data(void)
+{
+       bd_t *bd;
+       bd = gd->bd;
+       printf("--flags:%x\n", gd->flags);
+       printf("--board_type:%x\n", gd->board_type);
+       printf("--baudrate:%x\n", gd->baudrate);
+       printf("--have_console:%x\n", gd->have_console);
+       printf("--ram_size:%x\n", gd->ram_size);
+       printf("--reloc_off:%x\n", gd->reloc_off);
+       printf("--env_addr:%x\n", gd->env_addr);
+       printf("--env_valid:%x\n", gd->env_valid);
+       printf("--bd:%x %x\n", gd->bd, bd);
+       printf("---bi_baudrate:%x\n", bd->bi_baudrate);
+       printf("---bi_ip_addr:%x\n", bd->bi_ip_addr);
+       printf("---bi_enetaddr:%x %x %x %x %x %x\n",
+                               bd->bi_enetaddr[0],
+                               bd->bi_enetaddr[1],
+                               bd->bi_enetaddr[2],
+                               bd->bi_enetaddr[3],
+                               bd->bi_enetaddr[4],
+                               bd->bi_enetaddr[5]);
+       printf("---bi_arch_number:%x\n", bd->bi_arch_number);
+       printf("---bi_boot_params:%x\n", bd->bi_boot_params);
+       printf("---bi_memstart:%x\n", bd->bi_memstart);
+       printf("---bi_memsize:%x\n", bd->bi_memsize);
+       printf("---bi_flashstart:%x\n", bd->bi_flashstart);
+       printf("---bi_flashsize:%x\n", bd->bi_flashsize);
+       printf("---bi_flashoffset:%x\n", bd->bi_flashoffset);
+       printf("--jt:%x *:%x\n", gd->jt, *(gd->jt));
+}
+#endif
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependend #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+
+void board_init_f(ulong bootflag)
+{
+       ulong addr;
+       bd_t *bd;
+
+       gd = (gd_t *) (CFG_GBL_DATA_ADDR);
+       memset((void *) gd, 0, sizeof(gd_t));
+
+       /* Board data initialization */
+       addr = (CFG_GBL_DATA_ADDR + sizeof(gd_t));
+
+       /* Align to 4 byte boundary */
+       addr &= ~(4 - 1);
+       bd = (bd_t*)addr;
+       gd->bd = bd;
+       memset((void *) bd, 0, sizeof(bd_t));
+
+       /* Initialize */
+       init_IRQ();
+       env_init();             /* initialize environment */
+       init_baudrate();        /* initialze baudrate settings */
+       serial_init();          /* serial communications setup */
+       console_init_f();
+       display_banner();       /* say that we are here */
+       checkboard();
+#if defined(CONFIG_RTC_BF533) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+       rtc_init();
+#endif
+       timer_init();
+       printf("Clock: VCO: %lu MHz, Core: %lu MHz, System: %lu MHz\n", \
+       CONFIG_VCO_HZ/1000000, CONFIG_CCLK_HZ/1000000, CONFIG_SCLK_HZ/1000000);
+       printf("SDRAM: ");
+       print_size(initdram(0), "\n");
+       board_init_r((gd_t *) gd, 0x20000010);
+}
+
+void board_init_r(gd_t * id, ulong dest_addr)
+{
+       ulong size;
+       extern void malloc_bin_reloc(void);
+       char *s, *e;
+       bd_t *bd;
+       int i;
+       gd = id;
+       gd->flags |= GD_FLG_RELOC;      /* tell others: relocation done */
+       bd = gd->bd;
+
+#if    CONFIG_STAMP
+       /* There are some other pointer constants we must deal with */
+       /* configure available FLASH banks */
+       size = flash_init();
+       display_flash_config(size);
+       flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + 0x1ffff, &flash_info[0]);
+       bd->bi_flashstart = CFG_FLASH_BASE;
+       bd->bi_flashsize = size;
+       bd->bi_flashoffset = 0;
+#else
+       bd->bi_flashstart = 0;
+       bd->bi_flashsize = 0;
+       bd->bi_flashoffset = 0;
+#endif
+       /* initialize malloc() area */
+       mem_malloc_init();
+       malloc_bin_reloc();
+
+       /* relocate environment function pointers etc. */
+       env_relocate();
+
+       /* board MAC address */
+       s = getenv("ethaddr");
+       for (i = 0; i < 6; ++i) {
+               bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
+               if (s)
+                       s = (*e) ? e + 1 : e;
+       }
+
+       /* IP Address */
+       bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+       /* Initialize devices */
+       devices_init();
+       jumptable_init();
+
+       /* Initialize the console (after the relocation and devices init) */
+       console_init_r();
+
+       /* Initialize from environment */
+       if ((s = getenv("loadaddr")) != NULL) {
+               load_addr = simple_strtoul(s, NULL, 16);
+       }
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+       if ((s = getenv("bootfile")) != NULL) {
+               copy_filename(BootFile, s, sizeof(BootFile));
+       }
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+       /* miscellaneous platform dependent initialisations */
+       misc_init_r();
+#endif
+
+#ifdef CONFIG_DRIVER_SMC91111
+#ifdef SHARED_RESOURCES
+       /* Switch to Ethernet */
+       swap_to(ETHERNET);
+#endif
+       if  ( (SMC_inw(BANK_SELECT) & UPPER_BYTE_MASK) != SMC_IDENT ) {
+               printf("ERROR: Can't find SMC91111 at address %x\n", SMC_BASE_ADDRESS);
+       } else {
+               printf("Net:   SMC91111 at 0x%08X\n", SMC_BASE_ADDRESS);
+       }
+
+#ifdef SHARED_RESOURCES
+       swap_to(FLASH);
+#endif
+#endif
+#ifdef CONFIG_SOFT_I2C
+       init_func_i2c();
+#endif
+
+#ifdef DEBUG
+       display_global_data(void);
+#endif
+
+       /* main_loop() can return to retry autoboot, if so just run it again. */
+       for (;;) {
+               main_loop();
+       }
+}
+
+#ifdef CONFIG_SOFT_I2C
+static int init_func_i2c (void)
+{
+       puts ("I2C:   ");
+       i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+       puts ("ready\n");
+       return (0);
+}
+#endif
+
+void hang(void)
+{
+       puts("### ERROR ### Please RESET the board ###\n");
+       for (;;);
+}

diff --git a/lib_blackfin/cache.c b/lib_blackfin/cache.c
new file mode 100644 (file)
index 0000000..847278d
--- /dev/null
+++ b/lib_blackfin/cache.c
@@ -0,0 +1,40 @@
+/*
+ * U-boot - cache.c
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* for now: just dummy functions to satisfy the linker */
+extern void blackfin_icache_range (unsigned long *, unsigned long *);
+extern void blackfin_dcache_range (unsigned long *, unsigned long *);
+void flush_cache (unsigned long dummy1, unsigned long dummy2)
+{
+       if (icache_status ()) {
+               blackfin_icache_flush_range (dummy1, dummy1 + dummy2);
+       }
+       if (dcache_status ()) {
+               blackfin_dcache_flush_range (dummy1, dummy1 + dummy2);
+       }
+       return;
+}

diff --git a/lib_blackfin/muldi3.c b/lib_blackfin/muldi3.c
new file mode 100644 (file)
index 0000000..1fc34e3
--- /dev/null
+++ b/lib_blackfin/muldi3.c
@@ -0,0 +1,92 @@
+/*
+ * U-boot - muldi3.c contains routines for mult and div
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Generic function got from GNU gcc package, libgcc2.c */
+#ifndef SI_TYPE_SIZE
+#define SI_TYPE_SIZE 32
+#endif
+#define __ll_B (1L << (SI_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
+#define __ll_highpart(t) ((USItype) (t) / __ll_B)
+#define BITS_PER_UNIT 8
+
+#if !defined (umul_ppmm)
+#define umul_ppmm(w1, w0, u, v)                                                \
+do {                                                                   \
+       USItype __x0, __x1, __x2, __x3;                                 \
+       USItype __ul, __vl, __uh, __vh;                                 \
+                                                                       \
+       __ul = __ll_lowpart (u);                                        \
+       __uh = __ll_highpart (u);                                       \
+       __vl = __ll_lowpart (v);                                        \
+       __vh = __ll_highpart (v);                                       \
+                                                                       \
+       __x0 = (USItype) __ul * __vl;                                   \
+       __x1 = (USItype) __ul * __vh;                                   \
+       __x2 = (USItype) __uh * __vl;                                   \
+       __x3 = (USItype) __uh * __vh;                                   \
+                                                                       \
+       __x1 += __ll_highpart (__x0);/* this can't give carry */        \
+       __x1 += __x2;   /* but this indeed can */                       \
+       if (__x1 < __x2)        /* did we get it? */                    \
+               __x3 += __ll_B; /* yes, add it in the proper pos. */    \
+                                                                       \
+       (w1) = __x3 + __ll_highpart (__x1);                             \
+       (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);      \
+} while (0)
+#endif
+
+#if !defined (__umulsidi3)
+#define __umulsidi3(u, v)                                              \
+       ({DIunion __w;                                                  \
+       umul_ppmm (__w.s.high, __w.s.low, u, v);                        \
+       __w.ll; })
+#endif
+
+typedef unsigned int USItype    __attribute__ ((mode (SI)));
+typedef int SItype     __attribute__ ((mode (SI)));
+typedef int DItype     __attribute__ ((mode (DI)));
+typedef        int word_type __attribute__ ((mode (__word__)));
+
+struct DIstruct {SItype low, high;};
+typedef union
+{
+       struct DIstruct s;
+       DItype ll;
+} DIunion;
+
+DItype __muldi3 (DItype u, DItype v)
+{
+       DIunion w;
+       DIunion uu, vv;
+
+       uu.ll = u,
+       vv.ll = v;
+       /*  panic("kernel panic for __muldi3"); */
+       w.ll = __umulsidi3 (uu.s.low, vv.s.low);
+       w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
+       + (USItype) uu.s.high * (USItype) vv.s.low);
+
+       return w.ll;
+}

diff --git a/lib_i386/bios_setup.c b/lib_i386/bios_setup.c
index bc9781550dc60dfac3871c20a930f27120bbac2c..75f04a01fe637cc3aac4e79b203802c28a30fd91 100644 (file)
--- a/lib_i386/bios_setup.c
+++ b/lib_i386/bios_setup.c
@@ -36,6 +36,8 @@
 #include <asm/realmode.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define NUMVECTS       256
 
 #define BIOS_DATA        ((char*)0x400)
@@ -136,7 +138,6 @@ static void setvector(int vector, u16 segment, void *handler)
 
 int bios_setup(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        static int done=0;
        int vector;
        struct pci_controller *pri_hose;

diff --git a/lib_i386/board.c b/lib_i386/board.c
index e90eb6e569b8374c35731ac1ed40f368d568aa09..4175fdb1c49a01c44471fc54ef0d8c96106f36b8 100644 (file)
--- a/lib_i386/board.c
+++ b/lib_i386/board.c
@@ -38,6 +38,8 @@
 #include <ide.h>
 #include <asm/u-boot-i386.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern long _i386boot_start;
 extern long _i386boot_end;
 extern long _i386boot_romdata_start;
@@ -80,8 +82,6 @@ static ulong mem_malloc_brk = 0;
 
 static int mem_malloc_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* start malloc area right after the stack */
        mem_malloc_start = i386boot_bss_start +
                i386boot_bss_size + CFG_STACK_SIZE;
@@ -130,8 +130,6 @@ char *strmhz (char *buf, long hz)
  */
 static int init_baudrate (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        char tmp[64];   /* long enough for environment variables */
        int i = getenv_r("baudrate", tmp, 64);
 
@@ -167,7 +165,6 @@ static int display_banner (void)
  */
 static int display_dram_config (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int i;
 
        puts ("DRAM Configuration:\n");
@@ -233,7 +230,6 @@ gd_t *global_data;
 
 void start_i386boot (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        char *s;
        int i;
        ulong size;

diff --git a/lib_m68k/board.c b/lib_m68k/board.c
index 6b3edd61bb323b57e1fb9e0e3920871967e76a8c..e25833b32bef47308e5a605c6a6648fa303d0e79 100644 (file)
--- a/lib_m68k/board.c
+++ b/lib_m68k/board.c
@@ -60,6 +60,8 @@
 #include <i2c.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static char *failed = "*** failed ***\n";
 
 #ifdef CONFIG_PCU_E
@@ -111,8 +113,6 @@ static      ulong   mem_malloc_brk   = 0;
  */
 static void mem_malloc_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off;
 
        mem_malloc_end = dest_addr;
@@ -177,8 +177,6 @@ typedef int (init_fnc_t) (void);
 
 static int init_baudrate (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        uchar tmp[64];  /* long enough for environment variables */
        int i = getenv_r ("baudrate", tmp, sizeof (tmp));
 
@@ -192,8 +190,6 @@ static int init_baudrate (void)
 
 static int init_func_ram (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int board_type = 0;     /* use dummy arg */
        puts ("DRAM:  ");
 
@@ -263,8 +259,6 @@ init_fnc_t *init_sequence[] = {
 void
 board_init_f (ulong bootflag)
 {
-    DECLARE_GLOBAL_DATA_PTR;
-
        bd_t *bd;
        ulong len, addr, addr_sp;
        gd_t *id;
@@ -414,7 +408,6 @@ board_init_f (ulong bootflag)
  */
 void board_init_r (gd_t *id, ulong dest_addr)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        cmd_tbl_t *cmdtp;
        char *s, *e;
        bd_t *bd;

diff --git a/lib_m68k/m68k_linux.c b/lib_m68k/m68k_linux.c
index a32de1a907ef6e8f02dc41a4587d4315e4b23f4f..f87f56ea8f2ef9b96ec7581a2b042a8330253cd8 100644 (file)
--- a/lib_m68k/m68k_linux.c
+++ b/lib_m68k/m68k_linux.c
@@ -27,6 +27,8 @@
 #include <zlib.h>
 #include <asm/byteorder.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PHYSADDR(x) x
 
 #define LINUX_MAX_ENVS         256
@@ -56,8 +58,6 @@ static void linux_env_set (char *env_name, char *env_val);
 void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
                     ulong addr, ulong * len_ptr, int verify)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong len = 0, checksum;
        ulong initrd_start, initrd_end;
        ulong data;

diff --git a/lib_microblaze/board.c b/lib_microblaze/board.c
index bc987a338088546c17685a231c9398f2965dbfd4..026d247e54ad8a36a1b5ebf53ab6a5539583b8b5 100644 (file)
--- a/lib_microblaze/board.c
+++ b/lib_microblaze/board.c
@@ -28,6 +28,8 @@
 #include <version.h>
 #include <watchdog.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 const char version_string[] =
        U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")";
 
@@ -72,8 +74,6 @@ init_fnc_t *init_sequence[] = {
 
 void board_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        bd_t *bd;
        init_fnc_t **init_fnc_ptr;
 

diff --git a/lib_mips/mips_linux.c b/lib_mips/mips_linux.c
index 12e84359c92a14e08fac8a5bfd9f34f81a8d8b35..952d5a90ee9635650697ca594293f83354c6a0be 100644 (file)
--- a/lib_mips/mips_linux.c
+++ b/lib_mips/mips_linux.c
@@ -28,6 +28,8 @@
 #include <asm/byteorder.h>
 #include <asm/addrspace.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define        LINUX_MAX_ENVS          256
 #define        LINUX_MAX_ARGS          256
 
@@ -56,8 +58,6 @@ static void linux_env_set (char * env_name, char * env_val);
 void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
                     ulong addr, ulong * len_ptr, int verify)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        ulong len = 0, checksum;
        ulong initrd_start, initrd_end;
        ulong data;

diff --git a/lib_nios/board.c b/lib_nios/board.c
index e6cda521ed1743c7aa1b41a4e8c8334da85b7303..0a0d2e38fdacb72e7c070ac896c703712f7f6871 100644 (file)
--- a/lib_nios/board.c
+++ b/lib_nios/board.c
@@ -32,6 +32,7 @@
 #include <status_led.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * All attempts to come up with a "common" initialization sequence
@@ -106,8 +107,6 @@ init_fnc_t *init_sequence[] = {
 /***********************************************************************/
 void board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        bd_t *bd;
        init_fnc_t **init_fnc_ptr;
        char *s, *e;

diff --git a/lib_nios2/board.c b/lib_nios2/board.c
index 0e0b04244967a19d1fad4d65b05eee043f4143ef..cd23037771407993b92229166ed83efc66504702 100644 (file)
--- a/lib_nios2/board.c
+++ b/lib_nios2/board.c
@@ -32,6 +32,7 @@
 #include <status_led.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * All attempts to come up with a "common" initialization sequence
@@ -106,8 +107,6 @@ init_fnc_t *init_sequence[] = {
 /***********************************************************************/
 void board_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        bd_t *bd;
        init_fnc_t **init_fnc_ptr;
        char *s, *e;

diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index f40bb253b815a69db2dba67a28d97b30245110f3..e68cf1fe734672178aef41b1b7298be87507700e 100644 (file)
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -90,6 +90,7 @@ extern flash_info_t flash_info[];
 #endif
 
 #include <environment.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CFG_ENV_IS_EMBEDDED)
@@ -670,7 +671,8 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
        WATCHDOG_RESET();
 
-#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM)
+#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || \
+       defined (CONFIG_FLAGADM) || defined(CONFIG_MPC83XX)
        icache_enable ();       /* it's time to enable the instruction cache */
 #endif
 

diff --git a/net/bootp.c b/net/bootp.c
index 8c56c0845f3c61e977f95e4ff4bea932b2627101..669d74a6a50ae0f9f1a8ecba05101bb8ada04624 100644 (file)
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -715,7 +715,7 @@ BootpRequest (void)
 }
 
 #if (CONFIG_COMMANDS & CFG_CMD_DHCP)
-static void DhcpOptionsProcess (uchar * popt)
+static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp)
 {
        uchar *end = popt + BOOTP_HDR_SIZE;
        int oplen, size;
@@ -772,6 +772,34 @@ static void DhcpOptionsProcess (uchar * popt)
                        break;
                case 59:        /* Ignore Rebinding Time Option */
                        break;
+               case 66:        /* Ignore TFTP server name */
+                       break;
+               case 67:        /* vendor opt bootfile */
+                       /*
+                        * I can't use dhcp_vendorex_proc here because I need
+                        * to write into the bootp packet - even then I had to
+                        * pass the bootp packet pointer into here as the
+                        * second arg
+                        */
+                       size = truncate_sz ("Opt Boot File",
+                                           sizeof(bp->bp_file),
+                                           oplen);
+                       if (bp->bp_file[0] == '\0' && size > 0) {
+                               /*
+                                * only use vendor boot file if we didn't
+                                * receive a boot file in the main non-vendor
+                                * part of the packet - god only knows why
+                                * some vendors chose not to use this perfectly
+                                * good spot to store the boot file (join on
+                                * Tru64 Unix) it seems mind bogglingly crazy
+                                * to me
+                                */
+                               printf("*** WARNING: using vendor "
+                                       "optional boot file\n");
+                               memcpy(bp->bp_file, popt + 2, size);
+                               bp->bp_file[size] = '\0';
+                       }
+                       break;
                default:
 #if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX)
                        if (dhcp_vendorex_proc (popt))
@@ -882,7 +910,7 @@ DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len)
                        dhcp_state = REQUESTING;
 
                        if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
-                               DhcpOptionsProcess((u8 *)&bp->bp_vend[4]);
+                               DhcpOptionsProcess((u8 *)&bp->bp_vend[4], bp);
 
                        BootpCopyNetParams(bp); /* Store net params from reply */
 
@@ -901,7 +929,7 @@ DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len)
                        char *s;
 
                        if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
-                               DhcpOptionsProcess((u8 *)&bp->bp_vend[4]);
+                               DhcpOptionsProcess((u8 *)&bp->bp_vend[4], bp);
                        BootpCopyNetParams(bp); /* Store net params from reply */
                        dhcp_state = BOUND;
                        puts ("DHCP client bound to address ");

diff --git a/net/net.c b/net/net.c
index 37c5fb698e1b18ef1a4bc925a3685b1fe9dbddb1..1d1c98f3c20204c74ef3173b50537e21af8c60cd 100644 (file)
--- a/net/net.c
+++ b/net/net.c
@@ -92,6 +92,8 @@
 
 #if (CONFIG_COMMANDS & CFG_CMD_NET)
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define ARP_TIMEOUT            5               /* Seconds before trying ARP again */
 #ifndef        CONFIG_NET_RETRY_COUNT
 # define ARP_TIMEOUT_COUNT     5               /* # of timeouts before giving up  */
@@ -222,8 +224,10 @@ void ArpRequest (void)
            (NetOurIP & NetOurSubnetMask)) {
                if (NetOurGatewayIP == 0) {
                        puts ("## Warning: gatewayip needed but not set\n");
+                       NetArpWaitReplyIP = NetArpWaitPacketIP;
+               } else {
+                       NetArpWaitReplyIP = NetOurGatewayIP;
                }
-               NetArpWaitReplyIP = NetOurGatewayIP;
        } else {
                NetArpWaitReplyIP = NetArpWaitPacketIP;
        }
@@ -264,8 +268,6 @@ void ArpTimeoutCheck(void)
 int
 NetLoop(proto_t protocol)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        bd_t *bd = gd->bd;
 
 #ifdef CONFIG_NET_MULTI
@@ -570,9 +572,6 @@ startAgainHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len)
 
 void NetStartAgain (void)
 {
-#ifdef CONFIG_NET_MULTI
-       DECLARE_GLOBAL_DATA_PTR;
-#endif
        char *nretry;
        int noretry = 0, once = 0;
 

diff --git a/post/ether.c b/post/ether.c
index 660620e8f6282f7d04f4f6ac649ad61aa8d6a25d..8c87b5927e125c18c7f6c9d453d4ee450be0d2df 100644 (file)
--- a/post/ether.c
+++ b/post/ether.c
@@ -51,6 +51,8 @@
 #include <net.h>
 #include <serial.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define MIN_PACKET_LENGTH      64
 #define MAX_PACKET_LENGTH      256
 #define TEST_NUM               1
@@ -109,7 +111,6 @@ static RTXBD *rtx;
 
 static void scc_init (int scc_index)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        bd_t *bd = gd->bd;
 
        static int proff[] =

diff --git a/post/memory.c b/post/memory.c
index a10bc502d33e7ecce1befb347356bc1b5e9aa230..a2c088bad8d5f3cf274b4e62085e9b664f96cedd 100644 (file)
--- a/post/memory.c
+++ b/post/memory.c
@@ -157,6 +157,8 @@
 
 #if CONFIG_POST & CFG_POST_MEMORY
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Define INJECT_*_ERRORS for testing error detection in the presence of
  * _good_ hardware.
@@ -455,7 +457,6 @@ static int memory_post_tests (unsigned long start, unsigned long size)
 int memory_post_test (int flags)
 {
        int ret = 0;
-       DECLARE_GLOBAL_DATA_PTR;
        bd_t *bd = gd->bd;
        unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
                                 256 << 20 : bd->bi_memsize) - (1 << 20);

diff --git a/post/post.c b/post/post.c
index b3df91aa5c0c67bf723151adb9013ef980d7757b..e1066da6bd1e9b5ec7237e7f3e2eeb2f7346e2d8 100644 (file)
--- a/post/post.c
+++ b/post/post.c
@@ -32,14 +32,14 @@
 
 #ifdef CONFIG_POST
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define POST_MAX_NUMBER                32
 
 #define BOOTMODE_MAGIC 0xDEAD0000
 
 int post_init_f (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int res = 0;
        unsigned int i;
 
@@ -62,7 +62,6 @@ int post_init_f (void)
 
 void post_bootmode_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int bootmode = post_bootmode_get (0);
        int newword;
 
@@ -110,20 +109,17 @@ int post_bootmode_get (unsigned int *last_test)
 /* POST tests run before relocation only mark status bits .... */
 static void post_log_mark_start ( unsigned long testid )
 {
-       DECLARE_GLOBAL_DATA_PTR;
        gd->post_log_word |= (testid)<<16;
 }
 
 static void post_log_mark_succ ( unsigned long testid )
 {
-       DECLARE_GLOBAL_DATA_PTR;
        gd->post_log_word |= testid;
 }
 
 /* ... and the messages are output once we are relocated */
 void post_output_backlog ( void )
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int j;
 
        for (j = 0; j < post_list_size; j++) {
@@ -379,8 +375,6 @@ int post_log (char *format, ...)
 
 void post_reloc (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned int i;
 
        /*

diff --git a/post/sysmon.c b/post/sysmon.c
index 72fcac3850809489431e052d22c3f6dd122d1e62..f61d598244ccb025f1bbe2f7a86812cc97872d3f 100644 (file)
--- a/post/sysmon.c
+++ b/post/sysmon.c
@@ -52,6 +52,8 @@
 
 #if CONFIG_POST & CFG_POST_SYSMON
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static int sysmon_temp_invalid = 0;
 
 /* #define DEBUG */
@@ -159,8 +161,6 @@ int sysmon_init_f (void)
 
 void sysmon_reloc (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        sysmon_t ** l;
        sysmon_table_t * t;
 
@@ -281,8 +281,6 @@ static void sysmon_ccfl_enable (sysmon_table_t * this)
 
 int sysmon_post_test (int flags)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        int res = 0;
        sysmon_table_t * t;
        uint val;

diff --git a/post/uart.c b/post/uart.c
index 23bf036ba48534604bddb536a0f894f25da7c3c1..fd97e3899e9e1187aaff700cec7c97d06c89d4ee 100644 (file)
--- a/post/uart.c
+++ b/post/uart.c
@@ -50,6 +50,8 @@
 #include <command.h>
 #include <serial.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define CTLR_SMC 0
 #define CTLR_SCC 1
 
@@ -82,8 +84,6 @@ static int proff_scc[] =
 
 static void smc_init (int smc_index)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
 
        volatile immap_t *im = (immap_t *) CFG_IMMR;
@@ -288,8 +288,6 @@ static int smc_getc (int smc_index)
 
 static void scc_init (int scc_index)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        static int cpm_cr_ch[] = {
                CPM_CR_CH_SCC1,
                CPM_CR_CH_SCC2,

diff --git a/rtc/Makefile b/rtc/Makefile
index 4ceac76933e8050249f074436c7cef158fb54f35..2c5d099feef6a95a3809be9b4218bdc07e8453a8 100644 (file)
--- a/rtc/Makefile
+++ b/rtc/Makefile
@@ -28,8 +28,8 @@ include $(TOPDIR)/config.mk
 LIB    = librtc.a
 
 OBJS   = date.o   \
-         ds12887.o ds1302.o ds1306.o ds1307.o ds1337.o \
-         ds1556.o ds164x.o ds174x.o \
+         bf533_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \
+         ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o \
          m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \
          mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o
 

diff --git a/rtc/bf533_rtc.c b/rtc/bf533_rtc.c
new file mode 100644 (file)
index 0000000..948be64
--- /dev/null
+++ b/rtc/bf533_rtc.c
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ * Real Time Clock interface of ADI21535 (Blackfin) for uCLinux
+ *
+ * Copyright (C) 2003 Motorola Corporation.  All rights reserved.
+ *                             Richard Xiao (A2590C@email.mot.com)
+ *
+ * Copyright (C) 1996 Paul Gortmaker
+ *
+ *
+ *     Based on other minimal char device drivers, like Alan's
+ *     watchdog, Ted's random, etc. etc.
+ *
+ *     1.07    Paul Gortmaker.
+ *     1.08    Miquel van Smoorenburg: disallow certain things on the
+ *             DEC Alpha as the CMOS clock is also used for other things.
+ *     1.09    Nikita Schmidt: epoch support and some Alpha cleanup.
+ *     1.09a   Pete Zaitcev: Sun SPARC
+ *     1.09b   Jeff Garzik: Modularize, init cleanup
+ *     1.09c   Jeff Garzik: SMP cleanup
+ *     1.10    Paul Barton-Davis: add support for async I/O
+ *     1.10a   Andrea Arcangeli: Alpha updates
+ *     1.10b   Andrew Morton: SMP lock fix
+ *     1.10c   Cesar Barros: SMP locking fixes and cleanup
+ *     1.10d   Paul Gortmaker: delete paranoia check in rtc_exit
+ *     1.10e   LG Soft India: Register access is different in BF533.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+
+#if defined(CONFIG_RTC_BF533) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+
+#include <asm/blackfin.h>
+#include <asm/cpu/bf533_rtc.h>
+
+void rtc_reset (void)
+{
+       return;                 /* nothing to do */
+}
+
+/* Wait for pending writes to complete */
+void wait_for_complete (void)
+{
+       while (!(*(volatile unsigned short *) RTC_ISTAT & 0x8000)) {
+               printf ("");
+       }
+       *(volatile unsigned short *) RTC_ISTAT = 0x8000;
+}
+
+/* Enable the RTC prescaler enable register */
+void rtc_init ()
+{
+       *(volatile unsigned short *) RTC_PREN = 0x1;
+       wait_for_complete ();
+}
+
+/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers
+ * based on this value.
+ */
+void rtc_set (struct rtc_time *tmp)
+{
+       unsigned long n_days_1970 = 0;
+       unsigned long n_secs_rem = 0;
+       unsigned long n_hrs = 0;
+       unsigned long n_mins = 0;
+       unsigned long n_secs = 0;
+       unsigned long time_in_secs;
+
+       if (tmp == NULL) {
+               printf ("Error setting the date/time \n");
+               return;
+       }
+
+       time_in_secs =
+               mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour,
+                       tmp->tm_min, tmp->tm_sec);
+
+       /* Compute no. of days since 1970 */
+       n_days_1970 = (unsigned long) (time_in_secs / (NUM_SECS_IN_DAY));
+
+       /* From the remining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */
+       n_secs_rem = (unsigned long) (time_in_secs % (NUM_SECS_IN_DAY));
+       n_hrs = n_secs_rem / (NUM_SECS_IN_HOUR);
+       n_secs_rem = n_secs_rem % (NUM_SECS_IN_HOUR);
+       n_mins = n_secs_rem / (NUM_SECS_IN_MIN);
+       n_secs = n_secs_rem % (NUM_SECS_IN_MIN);
+
+       /* Store the new time in the RTC_STAT register */
+       *(volatile unsigned long *) RTC_STAT =
+               ((n_days_1970 << DAY_BITS_OFF) | (n_hrs << HOUR_BITS_OFF) |
+                (n_mins << MIN_BITS_OFF) | (n_secs << SEC_BITS_OFF));
+
+       wait_for_complete ();
+}
+
+/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */
+void rtc_get (struct rtc_time *tmp)
+{
+       unsigned long cur_rtc_stat = 0;
+       unsigned long time_in_sec;
+       unsigned long tm_sec = 0, tm_min = 0, tm_hour = 0, tm_day = 0;
+
+       if (tmp == NULL) {
+               printf ("Error getting the date/time \n");
+               return;
+       }
+
+       /* Read the RTC_STAT register */
+       cur_rtc_stat = *(volatile unsigned long *) RTC_STAT;
+
+       /* Get the secs (0-59), mins (0-59), hrs (0-23) and the days since Jan 1970 */
+       tm_sec = (cur_rtc_stat >> SEC_BITS_OFF) & 0x3f;
+       tm_min = (cur_rtc_stat >> MIN_BITS_OFF) & 0x3f;
+       tm_hour = (cur_rtc_stat >> HOUR_BITS_OFF) & 0x1f;
+       tm_day = (cur_rtc_stat >> DAY_BITS_OFF) & 0x7fff;
+
+       /* Calculate the total number of seconds since Jan 1970 */
+       time_in_sec = (tm_sec) +
+               MIN_TO_SECS (tm_min) +
+               HRS_TO_SECS (tm_hour) +
+               DAYS_TO_SECS (tm_day);
+       to_tm (time_in_sec, tmp);
+}
+#endif /* CONFIG_RTC_BF533 && CFG_CMD_DATE */

diff --git a/rtc/ds1374.c b/rtc/ds1374.c
new file mode 100644 (file)
index 0000000..50a996c
--- /dev/null
+++ b/rtc/ds1374.c
@@ -0,0 +1,253 @@
+/*
+ * (C) Copyright 2001, 2002, 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Keith Outwater, keith_outwater@mvis.com`
+ * Steven Scholz, steven.scholz@imc-berlin.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
+ * DS1374 Real Time Clock (RTC).
+ *
+ * based on ds1337.c
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+#include <i2c.h>
+
+#if (defined(CONFIG_RTC_DS1374)) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_RTC
+#define DEBUG_RTC
+
+#ifdef DEBUG_RTC
+#define DEBUGR(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGR(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+#ifndef CFG_I2C_RTC_ADDR
+# define CFG_I2C_RTC_ADDR      0x68
+#endif
+
+#if defined(CONFIG_RTC_DS1374) && (CFG_I2C_SPEED > 400000)
+# error The DS1374 is specified up to 400kHz in fast mode!
+#endif
+
+/*
+ * RTC register addresses
+ */
+#define RTC_TOD_CNT_BYTE0_ADDR         0x00 /* TimeOfDay */
+#define RTC_TOD_CNT_BYTE1_ADDR         0x01
+#define RTC_TOD_CNT_BYTE2_ADDR         0x02
+#define RTC_TOD_CNT_BYTE3_ADDR         0x03
+
+#define RTC_WD_ALM_CNT_BYTE0_ADDR      0x04
+#define RTC_WD_ALM_CNT_BYTE1_ADDR      0x05
+#define RTC_WD_ALM_CNT_BYTE2_ADDR      0x06
+
+#define RTC_CTL_ADDR                   0x07 /* RTC-CoNTrol-register */
+#define RTC_SR_ADDR                    0x08 /* RTC-StatusRegister */
+#define RTC_TCS_DS_ADDR                        0x09 /* RTC-TrickleChargeSelect DiodeSelect-register */
+
+#define RTC_CTL_BIT_AIE                        (1<<0) /* Bit 0 - Alarm Interrupt enable */
+#define RTC_CTL_BIT_RS1                        (1<<1) /* Bit 1/2 - Rate Select square wave output */
+#define RTC_CTL_BIT_RS2                        (1<<2) /* Bit 2/2 - Rate Select square wave output */
+#define RTC_CTL_BIT_WDSTR              (1<<3) /* Bit 3 - Watchdog Reset Steering */
+#define RTC_CTL_BIT_BBSQW              (1<<4) /* Bit 4 - Battery-Backed Square-Wave */
+#define RTC_CTL_BIT_WD_ALM             (1<<5) /* Bit 5 - Watchdoc/Alarm Counter Select */
+#define RTC_CTL_BIT_WACE               (1<<6) /* Bit 6 - Watchdog/Alarm Counter Enable WACE*/
+#define RTC_CTL_BIT_EN_OSC             (1<<7) /* Bit 7 - Enable Oscilator */
+
+#define RTC_SR_BIT_AF                  0x01 /* Bit 0 = Alarm Flag */
+#define RTC_SR_BIT_OSF                 0x80 /* Bit 7 - Osc Stop Flag */
+
+typedef unsigned char boolean_t;
+
+#ifndef TRUE
+#define TRUE ((boolean_t)(0==0))
+#endif
+#ifndef FALSE
+#define FALSE (!TRUE)
+#endif
+
+const char RtcTodAddr[] = {
+       RTC_TOD_CNT_BYTE0_ADDR,
+       RTC_TOD_CNT_BYTE1_ADDR,
+       RTC_TOD_CNT_BYTE2_ADDR,
+       RTC_TOD_CNT_BYTE3_ADDR
+};
+
+static uchar rtc_read (uchar reg);
+static void rtc_write (uchar reg, uchar val, boolean_t set);
+static void rtc_write_raw (uchar reg, uchar val);
+
+/*
+ * Get the current time from the RTC
+ */
+void rtc_get (struct rtc_time *tm){
+
+       unsigned long time1, time2;
+       unsigned int limit;
+       unsigned char tmp;
+       unsigned int i;
+
+       /*
+        * Since the reads are being performed one byte at a time,
+        * there is a chance that a carry will occur during the read.
+        * To detect this, 2 reads are performed and compared.
+        */
+       limit = 10;
+       do {
+               i = 4;
+               time1 = 0;
+               while (i--) {
+                       tmp = rtc_read(RtcTodAddr[i]);
+                       time1 = (time1 << 8) | (tmp & 0xff);
+               }
+
+               i = 4;
+               time2 = 0;
+               while (i--) {
+                       tmp = rtc_read(RtcTodAddr[i]);
+                       time2 = (time2 << 8) | (tmp & 0xff);
+               }
+       } while ((time1 != time2) && limit--);
+
+       if (time1 != time2) {
+               printf("can't get consistent time from rtc chip\n");
+       }
+
+       DEBUGR ("Get RTC s since 1.1.1970: %d\n", time1);
+
+       to_tm(time1, tm); /* To Gregorian Date */
+
+       if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF)
+               printf ("### Warning: RTC oscillator has stopped\n");
+
+       DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+               tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+               tm->tm_hour, tm->tm_min, tm->tm_sec);
+}
+
+/*
+ * Set the RTC
+ */
+void rtc_set (struct rtc_time *tmp){
+
+       unsigned long time;
+       unsigned i;
+
+       DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+               tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+               tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+       if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
+               printf("WARNING: year should be between 1970 and 2069!\n");
+
+       time = mktime(tmp->tm_year, tmp->tm_mon,
+                       tmp->tm_mday, tmp->tm_hour,
+                       tmp->tm_min, tmp->tm_sec);
+
+       DEBUGR ("Set RTC s since 1.1.1970: %d (0x%02x)\n", time, time);
+
+       /* write to RTC_TOD_CNT_BYTEn_ADDR */
+       for (i = 0; i <= 3; i++) {
+               rtc_write_raw(RtcTodAddr[i], (unsigned char)(time & 0xff));
+               time = time >> 8;
+       }
+
+       /* Start clock */
+       rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, FALSE);
+}
+
+/*
+ * Reset the RTC. We setting the date back to 1970-01-01.
+ * We also enable the oscillator output on the SQW/OUT pin and program
+ * it for 32,768 Hz output. Note that according to the datasheet, turning
+ * on the square wave output increases the current drain on the backup
+ * battery to something between 480nA and 800nA.
+ */
+void rtc_reset (void){
+
+       struct rtc_time tmp;
+
+       /* clear status flags */
+       rtc_write (RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), FALSE); /* clearing OSF and AF */
+
+       /* Initialise DS1374 oriented to MPC8349E-ADS */
+       rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC
+                                |RTC_CTL_BIT_WACE
+                                |RTC_CTL_BIT_AIE), FALSE);/* start osc, disable WACE, clear AIE
+                                                             - set to 0 */
+       rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM
+                               |RTC_CTL_BIT_WDSTR
+                               |RTC_CTL_BIT_RS1
+                               |RTC_CTL_BIT_RS2
+                               |RTC_CTL_BIT_BBSQW), TRUE);/* disable WD/ALM, WDSTR set to INT-pin,
+                                                             set BBSQW and SQW to 32k
+                                                             - set to 1 */
+       tmp.tm_year = 1970;
+       tmp.tm_mon = 1;
+       tmp.tm_mday= 1;
+       tmp.tm_hour = 0;
+       tmp.tm_min = 0;
+       tmp.tm_sec = 0;
+
+       rtc_set(&tmp);
+
+       printf("RTC:   %4d-%02d-%02d %2d:%02d:%02d UTC\n",
+               tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
+               tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
+
+       rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAC, TRUE);
+       rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR,0xDE, TRUE);
+       rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAD, TRUE);
+}
+
+/*
+ * Helper functions
+ */
+static uchar rtc_read (uchar reg)
+{
+       return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg));
+}
+
+static void rtc_write (uchar reg, uchar val, boolean_t set)
+{
+       if (set == TRUE) {
+               val |= i2c_reg_read (CFG_I2C_RTC_ADDR, reg);
+               i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val);
+       } else {
+               val = i2c_reg_read (CFG_I2C_RTC_ADDR, reg) & ~val;
+               i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val);
+       }
+}
+
+static void rtc_write_raw (uchar reg, uchar val)
+{
+               i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val);
+}
+#endif /* (CONFIG_RTC_DS1374) && (CFG_COMMANDS & CFG_CMD_DATE) */

diff --git a/rtc/rs5c372.c b/rtc/rs5c372.c
index 87f38c42bb6a66d8548b4ea0ec1be1a5f2f95c8e..b56808b8baeac76719f40f6d18de53dde6635f15 100644 (file)
--- a/rtc/rs5c372.c
+++ b/rtc/rs5c372.c
@@ -73,7 +73,7 @@ static unsigned bcd2bin (uchar c);
 static int setup_done = 0;
 
 static int
-rs5c372_readram(char *buf, int len)
+rs5c372_readram(unsigned char *buf, int len)
 {
        int ret;
 
@@ -128,7 +128,7 @@ rs5c372_enable(void)
 }
 
 static void
-rs5c372_convert_to_time(struct rtc_time *dt, char *buf)
+rs5c372_convert_to_time(struct rtc_time *dt, unsigned char *buf)
 {
        /* buf[0] is register 15 */
        dt->tm_sec = bcd2bin(buf[1]);

diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 74c0498d5a671c415f785b1386d8965585e89405..f723b5bca1d0f53f762fb8b20166e7ec02d81e42 100644 (file)
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -614,8 +614,7 @@ static int env_init (void)
                if (!crc1_ok) {
                        fprintf (stderr,
                                "Warning: Bad CRC, using default environment\n");
-                       environment.data = default_environment;
-                       free (addr1);
+                       memcpy(environment.data, default_environment, sizeof default_environment);
                }
        } else {
                flag1 = environment.flags;
@@ -652,9 +651,8 @@ static int env_init (void)
                } else if (!crc1_ok && !crc2_ok) {
                        fprintf (stderr,
                                "Warning: Bad CRC, using default environment\n");
-                       environment.data = default_environment;
+                       memcpy(environment.data, default_environment, sizeof default_environment);
                        curdev = 0;
-                       free (addr2);
                        free (addr1);
                } else if (flag1 == active_flag && flag2 == obsolete_flag) {
                        environment.data = addr1;

diff --git a/tools/mkimage.c b/tools/mkimage.c
index 70452db1c086c1f20d4cd236e671473c29c516e2..5222bb21a5b038da4462f1005d4c9781907cdd7e 100644 (file)
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -93,6 +93,7 @@ table_entry_t arch_name[] = {
     {  IH_CPU_SH,              "sh",           "SuperH",       },
     {  IH_CPU_SPARC,           "sparc",        "SPARC",        },
     {  IH_CPU_SPARC64,         "sparc64",      "SPARC 64 Bit", },
+    {  IH_CPU_BLACKFIN,        "blackfin",     "Blackfin",     },
     {  -1,                     "",             "",             },
 };
 

diff --git a/tools/setlocalversion b/tools/setlocalversion
new file mode 100755 (executable)
index 0000000..9a23825
--- /dev/null
+++ b/tools/setlocalversion
@@ -0,0 +1,22 @@
+#!/bin/sh
+# Print additional version information for non-release trees.
+
+usage() {
+       echo "Usage: $0 [srctree]" >&2
+       exit 1
+}
+
+cd "${1:-.}" || usage
+
+# Check for git and a git repo.
+if head=`git rev-parse --verify HEAD 2>/dev/null`; then
+       # Do we have an untagged version?
+       if  [ "`git name-rev --tags HEAD`" = "HEAD undefined" ]; then
+               printf '%s%s' -g `echo "$head" | cut -c1-8`
+       fi
+
+       # Are there uncommitted changes?
+       if git diff-files | read dummy; then
+               printf '%s' -dirty
+       fi
+fi